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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2022-04-29 12:22:36 +0200 |
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| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-04-29 12:22:36 +0200 |
| commit | a4744a1de601e86d2c78cb8c5a1c40d25117a97d (patch) | |
| tree | d043f5db4c671952aa7290314317d1ef61ae291a /tools/perf/scripts/python/stackcollapse.py | |
| parent | arm64: dts: renesas: rzg2ul-smarc-som: Enable watchdog (diff) | |
| parent | dt-bindings: clock: Add r8a779g0 CPG Core Clock Definitions (diff) | |
| download | linux-dev-a4744a1de601e86d2c78cb8c5a1c40d25117a97d.tar.xz linux-dev-a4744a1de601e86d2c78cb8c5a1c40d25117a97d.zip | |
Merge tag 'renesas-r8a779g0-dt-binding-defs-tag' into renesas-arm-dt-for-v5.19
Renesas R-Car V4H DT Binding Definitions
Clock and Power Domain definitions for the Renesas R-Car V4H (R8A779G0)
SoC, shared by driver and DT source files.
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions