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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2015-08-10 13:47:07 +0200 |
|---|---|---|
| committer |   Simon Horman <horms+renesas@verge.net.au> | 2016-04-27 14:10:27 +1000 |
| commit | abbecab1a0b8c2cc07edc30c8bced855ca4e239d (patch) | |
| tree | ea6ab53f4ea21c90c465cd92121b21f091efc60a /tools/perf/scripts/python/stackcollapse.py | |
| parent | Merge tag 'renesas-rcar-sysc2-for-v4.7' into arm64-dt-pm-domain-for-v4.7 (diff) | |
| download | linux-dev-abbecab1a0b8c2cc07edc30c8bced855ca4e239d.tar.xz linux-dev-abbecab1a0b8c2cc07edc30c8bced855ca4e239d.zip | |
arm64: dts: r8a7795: Add SYSC PM Domains
Add a device node for the System Controller.
Hook up the Cortex-A57 CPU cores and the Cortex-A57 and Cortex A53 L2
caches/SCUs to their respective PM Domains.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions