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| author |   Ping-Ke Shih <pkshih@realtek.com> | 2022-04-21 20:08:51 +0800 |
|---|---|---|
| committer |   Kalle Valo <kvalo@kernel.org> | 2022-04-24 14:30:33 +0300 |
| commit | e1757e80450164ede118993a889979e65ead591b (patch) | |
| tree | d08aee0bc13b1d5974e4e3ba6951d7fd227ef512 /tools/perf/scripts/python/stackcollapse.py | |
| parent | rtw89: pci: add variant IMR/ISR and configure functions (diff) | |
rtw89: pci: add variant RPWM/CPWM to enter low power mode
RPWM/CPWM are registers that can set and check low power mode. Since chips
use different address, add a field to access them in common flow.
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220421120903.73715-3-pkshih@realtek.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions