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| author |   Chris Wilson <chris@chris-wilson.co.uk> | 2020-06-11 10:30:15 +0100 |
|---|---|---|
| committer |   Joonas Lahtinen <joonas.lahtinen@linux.intel.com> | 2020-06-16 11:34:24 +0300 |
| commit | ef50fa9bd17d13d0611e39e13b37bbd3e1ea50bf (patch) | |
| tree | 012b0e55ab71722382ab8fd8c69930764748cf73 /tools/perf/scripts/python/stackcollapse.py | |
| parent | drm/i915/icl: Disable DIP on MST ports with the transcoder clock still on (diff) | |
| download | linux-dev-ef50fa9bd17d13d0611e39e13b37bbd3e1ea50bf.tar.xz linux-dev-ef50fa9bd17d13d0611e39e13b37bbd3e1ea50bf.zip | |
drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds
Rescue the GT workarounds from being buried inside init_clock_gating so
that we remember to apply them after a GT reset, and that they are
included in our verification that the workarounds are applied.
v2: Leave HSW_SCRATCH to set an explicit value, not or in our disable
bit.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2011
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: stable@vger.kernel.org
Link: https://patchwork.freedesktop.org/patch/msgid/20200611093015.11370-1-chris@chris-wilson.co.uk
(cherry picked from commit f93ec5fb563779bda4501890b1854526de58e0f1)
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions