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| author |   Athira Rajeev <atrajeev@linux.vnet.ibm.com> | 2020-10-21 14:23:26 +0530 |
|---|---|---|
| committer |   Michael Ellerman <mpe@ellerman.id.au> | 2020-11-19 16:56:56 +1100 |
| commit | fdf13a657508a12cd21a4d7b988cb260cb8fbd38 (patch) | |
| tree | 9aafd0a159bb43fa030ffe3a95b38e8796700424 /tools/perf/scripts/python/stackcollapse.py | |
| parent | powerpc/perf: Add new power PMU flag "PPMU_P10_DD1" for power10 DD1 (diff) | |
powerpc/perf: Drop the check for SIAR_VALID
In power10 DD1, there is an issue that causes the SIAR_VALID bit of
the SIER (Sampled Instruction Event Register) to not be set. But the
SIAR_VALID bit is used for fetching the instruction address from the
SIAR (Sampled Instruction Address Register), and marked events are
sampled only if the SIAR_VALID bit is set. So drop the check for
SIAR_VALID and return true always incase of power10 DD1.
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20201021085329.384535-2-maddy@linux.ibm.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions