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| author |   Thierry Reding <treding@nvidia.com> | 2014-04-04 15:55:15 +0200 |
|---|---|---|
| committer |   Peter De Schrijver <pdeschrijver@nvidia.com> | 2014-04-17 14:12:46 +0300 |
| commit | 4ccc402ece35695dd2884ec0b652d52ae0230f13 (patch) | |
| tree | e72273317bd892e4678ee6ccf776831e863554a1 /tools/perf/scripts/python/syscall-counts.py | |
| parent | clk: tegra: Introduce divider mask and shift helpers (diff) | |
| download | linux-dev-4ccc402ece35695dd2884ec0b652d52ae0230f13.tar.xz linux-dev-4ccc402ece35695dd2884ec0b652d52ae0230f13.zip | |
clk: tegra: Fix enabling of PLLE
When enabling the PLLE as its final step, clk_plle_enable() would
accidentally OR in the value previously written to the PLLE_SS_CTRL
register.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions