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| author |   Stephen Warren <swarren@nvidia.com> | 2012-04-12 14:13:05 -0600 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2012-04-25 15:22:09 -0600 |
| commit | 9abafa021e223f04d6589ee2b977bbaf2e1f1367 (patch) | |
| tree | 6029d68e9dc837b40677282e459fc807aa76e581 /tools/perf/scripts/python/syscall-counts.py | |
| parent | ARM: tegra: fix pclk rate (diff) | |
| download | linux-dev-9abafa021e223f04d6589ee2b977bbaf2e1f1367.tar.xz linux-dev-9abafa021e223f04d6589ee2b977bbaf2e1f1367.zip | |
ARM: tegra: change pll_p_out4's rate to 24MHz
pll_p_out4 is used on all/most Tegra boards to drive the cdev2 output pin
to provide a reference clock to a ULPI USB PHY. This reference clock must
run at 24MHz, and the cdev2 output has no additional dividers.
Remove board-paz00.c's now-duplicate initialization of this clock.
Reported-by: Marc Dietrich <marvin24@gmx.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions