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| author |   Chris Metcalf <cmetcalf@tilera.com> | 2012-03-29 15:25:59 -0400 |
|---|---|---|
| committer | Chris Metcalf <cmetcalf@tilera.com> | 2012-05-25 12:48:24 -0400 |
| commit | cd6f32aa088f4d328e676c35f51b440f2fe5b98c (patch) | |
| tree | 5668ff37a8690e5f5d919992756edb4466c37de2 /tools/perf/scripts/python/syscall-counts.py | |
| parent | arch/tile: Allow tilegx to build with either 16K or 64K page size (diff) | |
| download | linux-dev-cd6f32aa088f4d328e676c35f51b440f2fe5b98c.tar.xz linux-dev-cd6f32aa088f4d328e676c35f51b440f2fe5b98c.zip | |
arch/tile: support <asm/cachectl.h> header for cacheflush() syscall
We already had a syscall that did some dcache flushing, but it was
not used in practice. Make it MIPS compatible instead so it can
do both the DCACHE and ICACHE actions. We have code that wants to
be able to use the ICACHE flush mode from userspace so this change
enables that.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions