diff options
| author |   Xiang Chen <chenxiang66@hisilicon.com> | 2017-03-23 01:25:18 +0800 |
|---|---|---|
| committer |   Martin K. Petersen <martin.petersen@oracle.com> | 2017-03-23 11:12:01 -0400 |
| commit | 06ec0fb97c028102c95d52422fd6dc5ac701039f (patch) | |
| tree | c28bb8ca5a68622bb4a8e78348f2ec78eaa10c2c /tools/perf/scripts/python | |
| parent | scsi: hisi_sas: add to_hisi_sas_port() (diff) | |
scsi: hisi_sas: add controller reset
There are some scenarios that we need to warm-reset to reset registers
of SAS controller. During reset we disable interrupts/DQs/PHYs, and
after reset we re-init the hardware and rescan the topology to see if
anything changed.
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Signed-off-by: Xiaofei Tan <tanxiaofei@huawei.com>
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions