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| author |   Rodrigo Vivi <rodrigo.vivi@intel.com> | 2017-06-06 13:30:37 -0700 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2017-06-07 07:29:51 -0700 |
| commit | 1dc0766c33473d61fd85caa5031daf34f719cd3f (patch) | |
| tree | b4765bb365082e1d3d20a92fb47e2eafa4a1c124 /tools/perf/scripts/python | |
| parent | drm/i915/cnl: Configure EU slice power gating. (diff) | |
| download | linux-dev-1dc0766c33473d61fd85caa5031daf34f719cd3f.tar.xz linux-dev-1dc0766c33473d61fd85caa5031daf34f719cd3f.zip | |
drm/i915/cnl: Cannonlake has same MOCS table than Skylake.
All registers and default configuration are the same for Skylake
and Cannonlake.
v2: Don't apply Wa for platforms without MOCS. (Paulo)
v3: Removed WaDisableSkipCaching that Joonas noticed that
according to spec it is not applicable to CNL.
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1496781040-20888-8-git-send-email-rodrigo.vivi@intel.com
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions