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| author |   Alex Bee <knaerzche@gmail.com> | 2021-05-28 16:07:36 +0200 |
|---|---|---|
| committer |   Heiko Stuebner <heiko@sntech.de> | 2021-05-28 17:53:19 +0200 |
| commit | 2adafc0512625bbd090dc37a353ddda15d525e9d (patch) | |
| tree | 8e418b45f2bfbb738bca4f59d4edbf2905b2db73 /tools/perf/scripts/python | |
| parent | clk: rockchip: fix rk3568 cpll clk gate bits (diff) | |
| download | linux-dev-2adafc0512625bbd090dc37a353ddda15d525e9d.tar.xz linux-dev-2adafc0512625bbd090dc37a353ddda15d525e9d.zip | |
clk: rockchip: export ACLK_VCODEC for RK3036
It is required for the series at [1] to let hantro driver aquire the
clock and set the rate for RK3036 correctly, but I didn't want to
add a patch for yet another subsystem to this series.
[1] https://lore.kernel.org/linux-media/20210525152225.154302-1-knaerzche@gmail.com/
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20210528140736.79686-1-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions