diff options
| author |   Hans-Christian Egtvedt <hcegtvedt@atmel.com> | 2007-12-19 09:29:19 +0100 |
|---|---|---|
| committer |   Haavard Skinnemoen <haavard.skinnemoen@atmel.com> | 2008-04-19 20:40:08 -0400 |
| commit | 35bf50ccc80584a1404982f02fc4368e991ff55c (patch) | |
| tree | bb9add62acc4151b36c88b6bc893dc2000f08029 /tools/perf/scripts/python | |
| parent | avr32: Generic clockevents support (diff) | |
avr32: Implement set_rate(), set_parent() and mode() for pll1
This patch is a take two of adding full functionality to PLL1 on
AT32AP7000. This allows board-specific code and drivers to configure
and enable PLL1. This is useful when precise control over the
frequency of e.g. a genclock is needed and requested by users for the
ABDAC device.
The patch is based upon previous patches from both Haavard Skinnemoen
and David Brownell.
Signed-off-by: Hans-Christian Egtvedt <hcegtvedt@atmel.com>
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions