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| author |   Ville Syrjälä <ville.syrjala@linux.intel.com> | 2016-04-13 21:19:49 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2016-04-14 14:45:15 +0300 |
| commit | 7ce4d1f2730f2bd4320425dd376913c4a12bd3b2 (patch) | |
| tree | ec3f0b65a08485007711f27f079d2b537d95171b /tools/perf/scripts/python | |
| parent | drm/i915: Set up VLV_MASTER_IER consistently (diff) | |
drm/i915: Clear VLV_IIR after PIPESTAT
On VLV/CHV VLV_IIR is not double double buffered, and it doesn't detect
edges from PIPESTAT & co. like it does on gen4. Instead it just
directly latches the level from PIPESTAT & co. That means we must clear
VLV_IIR after PIPESTAT & co. or else we'll get a spurious bit in VLV_IIR
every single time.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1460571598-24452-4-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions