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| author |   Eric Anholt <eric@anholt.net> | 2016-02-15 17:31:41 -0800 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2016-02-26 17:42:47 -0800 |
| commit | a7c5047d1ce178dd2b1fa577fc8909ad663d56d5 (patch) | |
| tree | a817f72b9d1334c67e92392bf0e9d426c14aab81 /tools/perf/scripts/python | |
| parent | drm/vc4: Fix the name of the VSYNCD_EVEN register. (diff) | |
| download | linux-dev-a7c5047d1ce178dd2b1fa577fc8909ad663d56d5.tar.xz linux-dev-a7c5047d1ce178dd2b1fa577fc8909ad663d56d5.zip | |
drm/vc4: Fix setting of vertical timings in the CRTC.
It looks like when I went to add the interlaced bits, I just took the
existing PV_VERT* block and indented it, instead of copy and pasting
it first. Without this, changing resolution never worked.
Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions