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| author |   Florian Fainelli <florian@openwrt.org> | 2014-01-14 09:54:40 -0800 |
|---|---|---|
| committer |   Ralf Baechle <ralf@linux-mips.org> | 2014-01-24 22:39:55 +0100 |
| commit | af2418be63b4e994cfe4b625939d65b9afdfdf6c (patch) | |
| tree | 1b01cc2cab2f2fa6ed2c8316df447a68e8ff38b9 /tools/perf/scripts/python | |
| parent | MIPS: update MIPS_L1_CACHE_SHIFT based on MIPS_L1_CACHE_SHIFT_<N> (diff) | |
| download | linux-dev-af2418be63b4e994cfe4b625939d65b9afdfdf6c.tar.xz linux-dev-af2418be63b4e994cfe4b625939d65b9afdfdf6c.zip | |
MIPS: BCM63XX: select correct MIPS_L1_CACHE_SHIFT value
Broadcom BCM63xx DSL SoCs have a L1-cache line size of 16 bytes (shift
value of 4) instead of the currently configured 32 bytes L1-cache line
size.
Reported-by: Daniel Gonzalez <dgcbueu@gmail.com>
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions