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| author |   Jani Nikula <jani.nikula@intel.com> | 2013-09-06 07:40:05 +0300 |
|---|---|---|
| committer |   Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-09-06 10:49:34 +0200 |
| commit | bf13e81b904a37d94d83dd6c3b53a147719a3ead (patch) | |
| tree | 7502bd12e60bfe4a6aaafb31a422da254eb02317 /tools/perf/scripts/python | |
| parent | drm/i915: clean up power sequencing register port select definitions (diff) | |
drm/i915: add support for per-pipe power sequencing on vlv
VLV has per-pipe PP registers. Set up power sequencing on mode set. The
connector init time setup is problematic, since we don't have a pipe at
that time. Cook up something.
v2:
- use vlv_power_sequencer_pipe() also in _pp_{ctrl,stat}_reg()
- use PANEL_PORT_SELECT_DPC_VLV (Ville)
v3: make checkpatch happier
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
[danvet: Make checkpatch a bit more happier still ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions