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authorFabrice Gasnier <fabrice.gasnier@st.com>2019-10-28 17:11:48 +0100
committerJonathan Cameron <Jonathan.Cameron@huawei.com>2019-11-09 12:37:18 +0000
commitcb7e1b50e4e382c2c63ac0c80260db55c3a3c7ee (patch)
treeda91626900d5f527319900ed52f8f68ebd92e989 /tools/perf/scripts/python
parentdt-bindings: iio: stm32-adc: add max clock rate property (diff)
downloadlinux-dev-cb7e1b50e4e382c2c63ac0c80260db55c3a3c7ee.tar.xz
linux-dev-cb7e1b50e4e382c2c63ac0c80260db55c3a3c7ee.zip
iio: adc: stm32: allow to tune analog clock
Add new optional dt property to tune analog clock prescaler. Driver looks for optional "st,max-clk-rate-hz", then computes best approximation below that rate, using ADC internal prescaler. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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