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| author |   Athira Rajeev <atrajeev@linux.vnet.ibm.com> | 2022-06-10 19:10:54 +0530 |
|---|---|---|
| committer |   Michael Ellerman <mpe@ellerman.id.au> | 2022-06-29 08:57:43 +1000 |
| commit | 9258c0aa755fac469869dd647a6c3d5299ff7725 (patch) | |
| tree | 146f3839b833dbeb40feae86fa8af1b09853f87e /tools/perf/scripts | |
| parent | selftests/powerpc/pmu: Add support for perf event code tests (diff) | |
selftests/powerpc/pmu: Add selftest for group constraint check for PMC5 and PMC6
Events using Performance Monitor Counter 5 (PMC5) and Performance
Monitor Counter 6 (PMC6) can't have other fields in event code like
cache bits, thresholding or marked bit. PMC5 and PMC6 only supports base
events: ie 500fa and 600f4. Other combinations should fail. Testcase
tries setting other bits in event code for 500fa and 600f4 to check this
scenario.
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20220610134113.62991-17-atrajeev@linux.vnet.ibm.com
Diffstat (limited to 'tools/perf/scripts')
0 files changed, 0 insertions, 0 deletions