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| author |   Chris Wilson <chris@chris-wilson.co.uk> | 2021-01-25 22:02:47 +0000 |
|---|---|---|
| committer |   Rodrigo Vivi <rodrigo.vivi@intel.com> | 2021-02-08 16:56:57 -0500 |
| commit | d5109f739c9f14a3bda249cb48b16de1065932f0 (patch) | |
| tree | 4fb23c4424aae7da0558039b39ea01e580c718da /tools/perf/util/include/linux/git:/ssh:/git@git.zx2c4.com | |
| parent | drm/i915: Disable atomics in L3 for gen9 (diff) | |
| download | linux-dev-d5109f739c9f14a3bda249cb48b16de1065932f0.tar.xz linux-dev-d5109f739c9f14a3bda249cb48b16de1065932f0.zip | |
drm/i915/gt: Flush before changing register state
Flush; invalidate; change registers; invalidate; flush.
Will this finally work on every device? Or will Baytrail complain again?
On the positive side, we immediately see the benefit of having hsw-gt1 in
CI.
Fixes: ace44e13e577 ("drm/i915/gt: Clear CACHE_MODE prior to clearing residuals")
Testcase: igt/gem_render_tiled_blits # hsw-gt1
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210125220247.31701-1-chris@chris-wilson.co.uk
(cherry picked from commit d30bbd62b1bfd9e0a33c3583c5a9e5d66f60cbd7)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'tools/perf/util/include/linux/git:/ssh:/git@git.zx2c4.com')
0 files changed, 0 insertions, 0 deletions