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author | 2021-05-27 08:16:03 +0800 | |
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committer | 2021-06-01 11:02:56 -0300 | |
commit | ddc11da5eb37e27a4b66cddcaf11233ef51b3a79 (patch) | |
tree | d66a6b6b411a14b577c662a1f2e74b152df835cd /tools/perf/util/mem-events.h | |
parent | perf scripting python: intel-pt-events.py: Add --insn-trace and --src-trace (diff) | |
download | linux-dev-ddc11da5eb37e27a4b66cddcaf11233ef51b3a79.tar.xz linux-dev-ddc11da5eb37e27a4b66cddcaf11233ef51b3a79.zip |
perf tools: Check mem-loads auxiliary event
For some platforms, an auxiliary event has to be enabled
simultaneously with the load latency event.
For Alderlake, the auxiliary event is created in "cpu_core" pmu.
So first we need to check the existing of "cpu_core" pmu
and then check if this pmu has auxiliary event.
Signed-off-by: Jin Yao <yao.jin@linux.intel.com>
Acked-by: Jiri Olsa <jolsa@redhat.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Kan Liang <kan.liang@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: https://lore.kernel.org/r/20210527001610.10553-2-yao.jin@linux.intel.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Diffstat (limited to 'tools/perf/util/mem-events.h')
0 files changed, 0 insertions, 0 deletions