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| author |   Catalin Marinas <catalin.marinas@arm.com> | 2010-12-07 16:56:29 +0100 |
|---|---|---|
| committer |   Russell King <rmk+kernel@arm.linux.org.uk> | 2010-12-12 23:25:58 +0000 |
| commit | da30e0ac0f9a521f0cfec8145ddd1ad131f66d61 (patch) | |
| tree | 4a9002e6fca4d4763b40908403fc177153b9a6a8 /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | ARM: 6527/1: Use CTR instead of CCSIDR for the D-cache line size on ARMv7 (diff) | |
| download | linux-dev-da30e0ac0f9a521f0cfec8145ddd1ad131f66d61.tar.xz linux-dev-da30e0ac0f9a521f0cfec8145ddd1ad131f66d61.zip | |
ARM: 6528/1: Use CTR for the I-cache line size on ARMv7
The current implementation of the v7_coherent_*_range function assumes
that the D and I cache lines have the same size, which is incorrect
architecturally. This patch adds the icache_line_size macro which reads
the CTR register. The main loop in v7_coherent_*_range is split in two
independent loops or the D and I caches. This also has the performance
advantage that the DSB is moved outside the main loop.
Reported-by: Kevin Sapp <ksapp@quicinc.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions