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| author |   Artem Bityutskiy <artem.bityutskiy@linux.intel.com> | 2022-07-26 18:29:34 +0300 |
|---|---|---|
| committer |   Len Brown <len.brown@intel.com> | 2022-07-28 14:37:29 -0400 |
| commit | 0e4d42af81471ab801e059e1feac8e27547230cf (patch) | |
| tree | 13ccb1354c55271d2262505b458d4013add6a977 /tools/power/x86 | |
| parent | tools/power turbostat: cleanup 'automatic_cstate_conversion_probe()' (diff) | |
| download | linux-dev-0e4d42af81471ab801e059e1feac8e27547230cf.tar.xz linux-dev-0e4d42af81471ab801e059e1feac8e27547230cf.zip | |
tools/power turbostat: fix SPR PC6 limits
Sapphire Rapids Xeon (SPR) supports 2 flavors of PC6 - PC6N (non-retention) and
PC6R (retention). Before this patch we used ICX package C-state limits, which
was wrong, because ICX has only one PC6 flavor. With this patch, we use SKX PC6
limits for SPR, because they are the same.
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
Diffstat (limited to 'tools/power/x86')
| -rw-r--r-- | tools/power/x86/turbostat/turbostat.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c index 3ec10d141abb..05e993674015 100644 --- a/tools/power/x86/turbostat/turbostat.c +++ b/tools/power/x86/turbostat/turbostat.c @@ -3734,11 +3734,11 @@ int probe_nhm_msrs(unsigned int family, unsigned int model) has_misc_feature_control = 1; break; case INTEL_FAM6_SKYLAKE_X: /* SKX */ + case INTEL_FAM6_SAPPHIRERAPIDS_X: /* SPR */ pkg_cstate_limits = skx_pkg_cstate_limits; has_misc_feature_control = 1; break; case INTEL_FAM6_ICELAKE_X: /* ICX */ - case INTEL_FAM6_SAPPHIRERAPIDS_X: /* SPR */ pkg_cstate_limits = icx_pkg_cstate_limits; has_misc_feature_control = 1; break; |