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| author |   Len Brown <len.brown@intel.com> | 2017-01-27 02:13:27 -0500 |
|---|---|---|
| committer | Len Brown <len.brown@intel.com> | 2017-03-01 00:14:20 -0500 |
| commit | 7170a374377d7c70d63a2d3eb38f8fe32e6ffadd (patch) | |
| tree | f10afcda859f78591d2a9802e573ede124965142 /tools/power | |
| parent | tools/power turbostat: initial Gemini Lake SOC support (diff) | |
| download | linux-dev-7170a374377d7c70d63a2d3eb38f8fe32e6ffadd.tar.xz linux-dev-7170a374377d7c70d63a2d3eb38f8fe32e6ffadd.zip | |
tools/power turbostat: Denverton: use HW CC1 counter, skip C3, C7
The CC1 column in tubostat can be computed by subtracting
the core c-state residency countes from the total Cx residency.
CC1 = (Idle_time_as_measured by MPERF) - (all core C-states with
residency counters)
However, as the underlying counter reads are not atomic,
error can be noticed in this calculations, especially
when the numbers are small.
Denverton has a hardware CC1 residency counter
to improve the accuracy of the cc1 statistic -- use it.
At the same time, Denverton has no concept of CC3, PC3, CC7, PC7,
so skip collecting and printing those columns.
Finally, a note of clarification.
Turbostat prints the standard PC2 residency counter,
but on Denverton hardware, that actually means PC1E.
Turbostat prints the standard PC6 residency counter,
but on Denverton hardware, that actually means PC2.
At this point, we document that differnce in this commit message,
rather than adding a quirk to the software.
Signed-off-by: Len Brown <len.brown@intel.com>
Diffstat (limited to 'tools/power')
| -rw-r--r-- | tools/power/x86/turbostat/turbostat.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c index 819d67fbb6ca..1010135ee973 100644 --- a/tools/power/x86/turbostat/turbostat.c +++ b/tools/power/x86/turbostat/turbostat.c @@ -2572,6 +2572,18 @@ int has_slv_msrs(unsigned int family, unsigned int model) } return 0; } +int is_dnv(unsigned int family, unsigned int model) +{ + + if (!genuine_intel) + return 0; + + switch (model) { + case INTEL_FAM6_ATOM_DENVERTON: + return 1; + } + return 0; +} int has_nhm_turbo_ratio_limit(unsigned int family, unsigned int model) { @@ -3851,6 +3863,14 @@ void process_cpuid() BIC_PRESENT(BIC_Mod_c6); use_c1_residency_msr = 1; } + if (is_dnv(family, model)) { + BIC_PRESENT(BIC_CPU_c1); + BIC_NOT_PRESENT(BIC_CPU_c3); + BIC_NOT_PRESENT(BIC_Pkgpc3); + BIC_NOT_PRESENT(BIC_CPU_c7); + BIC_NOT_PRESENT(BIC_Pkgpc7); + use_c1_residency_msr = 1; + } if (has_hsw_msrs(family, model)) { BIC_PRESENT(BIC_Pkgpc8); BIC_PRESENT(BIC_Pkgpc9); |