diff options
| author |   Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> | 2019-09-05 16:37:47 -0700 |
|---|---|---|
| committer |   Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2019-09-09 13:19:35 +0300 |
| commit | 92e0e87d0be5eb192fab1edb9b44e724c63416ce (patch) | |
| tree | d35c7831e8dc939d40fe8fcd4a45999d9b5dcf62 /tools/power | |
| parent | tools/power/x86/intel-speed-select: Fix memory leak (diff) | |
| download | linux-dev-92e0e87d0be5eb192fab1edb9b44e724c63416ce.tar.xz linux-dev-92e0e87d0be5eb192fab1edb9b44e724c63416ce.zip | |
platform/x86: ISST: Allow additional TRL MSRs
Additional Turbo Ratio Limit (TRL) MSRs are required to get bucket vs core
count relationship. So add them to the list of allowed MSRs.
Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Diffstat (limited to 'tools/power')
0 files changed, 0 insertions, 0 deletions