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| author |   Richard Fitzgerald <rf@opensource.cirrus.com> | 2021-10-15 14:36:15 +0100 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2021-10-15 16:14:19 +0100 |
| commit | 4ae1d8f911d6fc20baefd5eb061bf6964fa22a32 (patch) | |
| tree | adbd339865ca92dbb92bc0ed78cc5bb667f3e82a /tools/testing/selftests/exec/git:/ssh:/git@git.zx2c4.com | |
| parent | ASoC: cs42l42: Use PLL for SCLK > 12.288MHz (diff) | |
| download | linux-dev-4ae1d8f911d6fc20baefd5eb061bf6964fa22a32.tar.xz linux-dev-4ae1d8f911d6fc20baefd5eb061bf6964fa22a32.zip | |
ASoC: cs42l42: Allow time for HP/ADC to power-up after enable
After enabling the HP or ADC by writing the corresponding PDN=0,
it takes around 20 milliseconds for it to power up and the midrail
supply to be stable. Add this wait into a DAPM widget callback.
If HP and ADC are both powering up in a DAPM sequence, there's no
need to do the wait twice. The widget will perform one wait in the
POST_PMU if there was a PRE_PMU for one or both.
Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20211015133619.4698-13-rf@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/testing/selftests/exec/git:/ssh:/git@git.zx2c4.com')
0 files changed, 0 insertions, 0 deletions