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| author |   Ricardo Koller <ricarkol@google.com> | 2021-11-08 18:38:50 -0800 |
|---|---|---|
| committer |   Marc Zyngier <maz@kernel.org> | 2021-12-28 19:22:54 +0000 |
| commit | 33a1ca736e74839d08948973d30f6def820b8b14 (patch) | |
| tree | 270625f6689a29cbecb4c20065e18e2b2bc9e26f /tools/testing/selftests/kvm/lib | |
| parent | Linux 5.16-rc3 (diff) | |
| download | linux-dev-33a1ca736e74839d08948973d30f6def820b8b14.tar.xz linux-dev-33a1ca736e74839d08948973d30f6def820b8b14.zip | |
KVM: selftests: aarch64: Move gic_v3.h to shared headers
Move gic_v3.h to the shared headers location. There are some definitions
that will be used in the vgic-irq test.
Signed-off-by: Ricardo Koller <ricarkol@google.com>
Acked-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211109023906.1091208-2-ricarkol@google.com
Diffstat (limited to 'tools/testing/selftests/kvm/lib')
| -rw-r--r-- | tools/testing/selftests/kvm/lib/aarch64/gic_v3.h | 70 |
1 files changed, 0 insertions, 70 deletions
diff --git a/tools/testing/selftests/kvm/lib/aarch64/gic_v3.h b/tools/testing/selftests/kvm/lib/aarch64/gic_v3.h deleted file mode 100644 index b51536d469a6..000000000000 --- a/tools/testing/selftests/kvm/lib/aarch64/gic_v3.h +++ /dev/null @@ -1,70 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * ARM Generic Interrupt Controller (GIC) v3 specific defines - */ - -#ifndef SELFTEST_KVM_GICV3_H -#define SELFTEST_KVM_GICV3_H - -#include <asm/sysreg.h> - -/* - * Distributor registers - */ -#define GICD_CTLR 0x0000 -#define GICD_TYPER 0x0004 -#define GICD_IGROUPR 0x0080 -#define GICD_ISENABLER 0x0100 -#define GICD_ICENABLER 0x0180 -#define GICD_ICACTIVER 0x0380 -#define GICD_IPRIORITYR 0x0400 - -/* - * The assumption is that the guest runs in a non-secure mode. - * The following bits of GICD_CTLR are defined accordingly. - */ -#define GICD_CTLR_RWP (1U << 31) -#define GICD_CTLR_nASSGIreq (1U << 8) -#define GICD_CTLR_ARE_NS (1U << 4) -#define GICD_CTLR_ENABLE_G1A (1U << 1) -#define GICD_CTLR_ENABLE_G1 (1U << 0) - -#define GICD_TYPER_SPIS(typer) ((((typer) & 0x1f) + 1) * 32) -#define GICD_INT_DEF_PRI_X4 0xa0a0a0a0 - -/* - * Redistributor registers - */ -#define GICR_CTLR 0x000 -#define GICR_WAKER 0x014 - -#define GICR_CTLR_RWP (1U << 3) - -#define GICR_WAKER_ProcessorSleep (1U << 1) -#define GICR_WAKER_ChildrenAsleep (1U << 2) - -/* - * Redistributor registers, offsets from SGI base - */ -#define GICR_IGROUPR0 GICD_IGROUPR -#define GICR_ISENABLER0 GICD_ISENABLER -#define GICR_ICENABLER0 GICD_ICENABLER -#define GICR_ICACTIVER0 GICD_ICACTIVER -#define GICR_IPRIORITYR0 GICD_IPRIORITYR - -/* CPU interface registers */ -#define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0) -#define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0) -#define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1) -#define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5) -#define SYS_ICC_GRPEN1_EL1 sys_reg(3, 0, 12, 12, 7) - -#define ICC_PMR_DEF_PRIO 0xf0 - -#define ICC_SRE_EL1_SRE (1U << 0) - -#define ICC_IGRPEN1_EL1_ENABLE (1U << 0) - -#define GICV3_MAX_CPUS 512 - -#endif /* SELFTEST_KVM_GICV3_H */ |