diff options
| author |   Anup Patel <apatel@ventanamicro.com> | 2022-04-09 09:15:44 +0530 |
|---|---|---|
| committer |   Anup Patel <anup@brainfault.org> | 2022-04-09 09:15:44 +0530 |
| commit | fac3725364397f9a40a101f089b86ea655a58d06 (patch) | |
| tree | 19c4c4c501e86957c4f8c3b4d212d58120f8351a /tools/testing/selftests/kvm | |
| parent | RISC-V: KVM: Don't clear hgatp CSR in kvm_arch_vcpu_put() (diff) | |
| download | linux-dev-fac3725364397f9a40a101f089b86ea655a58d06.tar.xz linux-dev-fac3725364397f9a40a101f089b86ea655a58d06.zip | |
KVM: selftests: riscv: Set PTE A and D bits in VS-stage page table
Supporting hardware updates of PTE A and D bits is optional for any
RISC-V implementation so current software strategy is to always set
these bits in both G-stage (hypervisor) and VS-stage (guest kernel).
If PTE A and D bits are not set by software (hypervisor or guest)
then RISC-V implementations not supporting hardware updates of these
bits will cause traps even for perfectly valid PTEs.
Based on above explanation, the VS-stage page table created by various
KVM selftest applications is not correct because PTE A and D bits are
not set. This patch fixes VS-stage page table programming of PTE A and
D bits for KVM selftests.
Fixes: 3e06cdf10520 ("KVM: selftests: Add initial support for RISC-V
64-bit")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Tested-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'tools/testing/selftests/kvm')
| -rw-r--r-- | tools/testing/selftests/kvm/include/riscv/processor.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/testing/selftests/kvm/include/riscv/processor.h index dc284c6bdbc3..eca5c622efd2 100644 --- a/tools/testing/selftests/kvm/include/riscv/processor.h +++ b/tools/testing/selftests/kvm/include/riscv/processor.h @@ -101,7 +101,9 @@ static inline void set_reg(struct kvm_vm *vm, uint32_t vcpuid, uint64_t id, #define PGTBL_PTE_WRITE_SHIFT 2 #define PGTBL_PTE_READ_MASK 0x0000000000000002ULL #define PGTBL_PTE_READ_SHIFT 1 -#define PGTBL_PTE_PERM_MASK (PGTBL_PTE_EXECUTE_MASK | \ +#define PGTBL_PTE_PERM_MASK (PGTBL_PTE_ACCESSED_MASK | \ + PGTBL_PTE_DIRTY_MASK | \ + PGTBL_PTE_EXECUTE_MASK | \ PGTBL_PTE_WRITE_MASK | \ PGTBL_PTE_READ_MASK) #define PGTBL_PTE_VALID_MASK 0x0000000000000001ULL |