diff options
| author |   Linus Torvalds <torvalds@linux-foundation.org> | 2016-12-12 11:46:21 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2016-12-12 11:46:21 -0800 |
| commit | bca13ce4554ae9cf5083e5adf395ad2266cb571b (patch) | |
| tree | de392199f8eecd9c1331e2bcff5b60d4f188a5db /tools | |
| parent | Merge branch 'mm-pat-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip (diff) | |
| parent | perf/x86: Fix exclusion of BTS and LBR for Goldmont (diff) | |
| download | linux-dev-bca13ce4554ae9cf5083e5adf395ad2266cb571b.tar.xz linux-dev-bca13ce4554ae9cf5083e5adf395ad2266cb571b.zip | |
Merge branch 'perf-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull perf updates from Ingo Molnar:
"This update is pretty big and almost exclusively includes tooling
changes, because v4.9's LTS status forced to completion most of the
pending kernel side hardware enablement work and because we tried to
freeze core perf work a bit to give a time window for the fuzzing
efforts.
The diff is large mostly due to the JSON hardware event tables added
for Intel and Power8 CPUs. This was a popular feature request from
people working close to hardware and from the HPC community.
Tree size is big because this added the CPU event tables for over a
decade of Intel CPUs. Future changes for a CPU vendor alrady support
should be much smaller, as events for new models are added. The new
events are listed in 'perf list', for the CPU model the tool is
running on. If you find an interesting event it can be used as-is:
$ perf stat -a -e l2_lines_out.pf_clean sleep 1
Performance counter stats for 'system wide':
7,860,403 l2_lines_out.pf_clean
1.000624918 seconds time elapsed
The event lists can be searched the usual 'perf list' fashion for
(case insensitive) substrings as well:
$ perf list l2_lines_out
List of pre-defined events (to be used in -e):
cache:
l2_lines_out.demand_clean
[Clean L2 cache lines evicted by demand]
l2_lines_out.demand_dirty
[Dirty L2 cache lines evicted by demand]
l2_lines_out.dirty_all
[Dirty L2 cache lines filling the L2]
l2_lines_out.pf_clean
[Clean L2 cache lines evicted by L2 prefetch]
l2_lines_out.pf_dirty
[Dirty L2 cache lines evicted by L2 prefetch]
etc.
There's a few high level categories as well that can be listed:
'cache', 'floating point', 'frontend', 'memory', 'pipeline', 'virtual
memory'.
Existing generic events and workflows should work as-is.
The only kernel side change is a late breaking fix for an older
regression, related to Intel BTS, LBR and PT feature interaction.
On the tooling side there are three new tools / major features:
- The new 'perf c2c' tool provides means for Shared Data C2C/HITM
analysis.
This allows you to track down cacheline contention. The tool is
based on x86's load latency and precise store facility events
provided by Intel CPUs.
It was tested by Joe Mario and has proven to be useful, finding
some cacheline contentions. Joe also wrote a blog about c2c tool
with examples:
https://joemario.github.io/blog/2016/09/01/c2c-blog/
excerpt of the content on this site:
At a high level, “perf c2c” will show you:
* The cachelines where false sharing was detected.
* The readers and writers to those cachelines, and the offsets where those accesses occurred.
* The pid, tid, instruction addr, function name, binary object name for those readers and writers.
* The source file and line number for each reader and writer.
* The average load latency for the loads to those cachelines.
* Which numa nodes the samples a cacheline came from and which CPUs were involved.
Using perf c2c is similar to using the Linux perf tool today.
First collect data with “perf c2c record”, then generate a
report output with “perf c2c report”
There one finds extensive details on using the tool, with tips on
reducing the volume of samples while still capturing enough to do
its job. (Dick Fowles, Joe Mario, Don Zickus, Jiri Olsa)
- The new 'perf sched timehist' tool provides tailored analysis of
scheduling events.
Example usage:
perf sched record -- sleep 1
perf sched timehist
By default it shows the individual schedule events, including the
wait time (time between sched-out and next sched-in events for the
task), the task scheduling delay (time between wakeup and actually
running) and run time for the task:
time cpu task name wait time sch delay run time
[tid/pid] (msec) (msec) (msec)
-------- ------ ---------------- --------- --------- --------
1.874569 [0011] gcc[31949] 0.014 0.000 1.148
1.874591 [0010] gcc[31951] 0.000 0.000 0.024
1.874603 [0010] migration/10[59] 3.350 0.004 0.011
1.874604 [0011] <idle> 1.148 0.000 0.035
1.874723 [0005] <idle> 0.016 0.000 1.383
1.874746 [0005] gcc[31949] 0.153 0.078 0.022
...
Times are in msec.usec. (David Ahern, Namhyung Kim)
- Add CPU vendor hardware event tables:
Add JSON files with vendor event naming for Intel and Power8
processors, allowing users of tools like oprofile to keep using the
event names they are used to, as well as people reading vendor
documentation, where such naming is used. (Andi Kleen, Sukadev
Bhattiprolu)
You should see all the new events with 'perf list' and you should
be able to search them, for example 'perf list miss' will list all
the myriads of miss events.
Other tooling features added were:
- Cross-arch annotation support:
o Improve ARM support in the annotation code, affecting 'perf
annotate', 'perf report' and live annotation in 'perf top' (Kim
Phillips)
o Initial support for PowerPC in the annotation code (Ravi
Bangoria)
o Support AArch64 in the 'annotate' code, native/local and
cross-arch/remote (Kim Phillips)
- Allow considering just events in a given time interval, via the
'--time start.s.ms,end.s.ms' command line, added to 'perf kmem',
'perf report', 'perf sched timehist' and 'perf script' (David
Ahern)
- Add option to stop printing a callchain at one of a given group of
symbol names (David Ahern)
- Track memory freed in 'perf kmem stat' (David Ahern)
- Allow querying and setting .perfconfig variables (Taeung Song)
- Show branch information in callchains (predicted, TSX aborts, loop
iteractions, etc) (Jin Yao)
- Dynamicly change verbosity level by pressing 'V' in the 'perf
top/report' hists TUI browser (Alexis Berlemont)
- Implement 'perf trace --delay' in the same fashion as in 'perf
record --delay', to skip sampling workload initialization events
(Alexis Berlemont)
- Make vendor named events case insensitive in 'perf list', i.e.
'perf list LONGEST_LAT' works just the same as 'perf list
longest_lat' (Andi Kleen)
- Add unwinding support for jitdump (Stefano Sanfilippo)
Tooling infrastructure changes:
- Support linking perf with clang and LLVM libraries, initially
statically, but this limitation will be lifted and shared
libraries, when available, will be preferred to the static build,
that should, as with other features, be enabled explicitly (Wang
Nan)
- Add initial support (and perf test entry) for tooling hooks,
starting with 'record_start' and 'record_end', that will have as
its initial user the eBPF infrastructure, where perf_ prefixed
functions will be JITed and run when such hooks are called (Wang
Nan)
- Implement assorted libbpf improvements (Wang Nan)"
... and lots of other changes, features, cleanups and refactorings I
did not list, see the shortlog and the git log for details"
* 'perf-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (220 commits)
perf/x86: Fix exclusion of BTS and LBR for Goldmont
perf tools: Explicitly document that --children is enabled by default
perf sched timehist: Cleanup idle_max_cpu handling
perf sched timehist: Handle zero sample->tid properly
perf callchain: Introduce callchain_cursor__copy()
perf sched: Cleanup option processing
perf sched timehist: Improve error message when analyzing wrong file
perf tools: Move perf build related variables under non fixdep leg
perf tools: Force fixdep compilation at the start of the build
perf tools: Move PERF-VERSION-FILE target into rules area
perf build: Check LLVM version in feature check
perf annotate: Show raw form for jump instruction with indirect target
perf tools: Add non config targets
perf tools: Cleanup build directory before each test
perf tools: Move python/perf.so target into rules area
perf tools: Move install-gtk target into rules area
tools build: Move tabs to spaces where suitable
tools build: Make the .cmd file more readable
perf clang: Compile BPF script using builtin clang support
perf clang: Support compile IR to BPF object and add testcase
...
Diffstat (limited to 'tools')
287 files changed, 98016 insertions, 1050 deletions
diff --git a/tools/build/Build.include b/tools/build/Build.include index 1dcb95e76f70..418871d02ebf 100644 --- a/tools/build/Build.include +++ b/tools/build/Build.include @@ -65,22 +65,22 @@ dep-cmd = $(if $(wildcard $(fixdep)), printf '\# cannot find fixdep (%s)\n' $(fixdep) > $(dot-target).cmd; \ printf '\# using basic dep data\n\n' >> $(dot-target).cmd; \ cat $(depfile) >> $(dot-target).cmd; \ - printf '%s\n' 'cmd_$@ := $(make-cmd)' >> $(dot-target).cmd) + printf '\n%s\n' 'cmd_$@ := $(make-cmd)' >> $(dot-target).cmd) ### # if_changed_dep - execute command if any prerequisite is newer than # target, or command line has changed and update # dependencies in the cmd file if_changed_dep = $(if $(strip $(any-prereq) $(arg-check)), \ - @set -e; \ - $(echo-cmd) $(cmd_$(1)) && $(dep-cmd)) + @set -e; \ + $(echo-cmd) $(cmd_$(1)) && $(dep-cmd)) # if_changed - execute command if any prerequisite is newer than # target, or command line has changed -if_changed = $(if $(strip $(any-prereq) $(arg-check)), \ - @set -e; \ - $(echo-cmd) $(cmd_$(1)); \ - printf '%s\n' 'cmd_$@ := $(make-cmd)' > $(dot-target).cmd) +if_changed = $(if $(strip $(any-prereq) $(arg-check)), \ + @set -e; \ + $(echo-cmd) $(cmd_$(1)); \ + printf '%s\n' 'cmd_$@ := $(make-cmd)' > $(dot-target).cmd) ### # C flags to be used in rule definitions, includes: @@ -89,10 +89,12 @@ if_changed = $(if $(strip $(any-prereq) $(arg-check)), \ # - per target C flags # - per object C flags # - BUILD_STR macro to allow '-D"$(variable)"' constructs -c_flags = -Wp,-MD,$(depfile),-MT,$@ $(CFLAGS) -D"BUILD_STR(s)=\#s" $(CFLAGS_$(basetarget).o) $(CFLAGS_$(obj)) -cxx_flags = -Wp,-MD,$(depfile),-MT,$@ $(CXXFLAGS) -D"BUILD_STR(s)=\#s" $(CXXFLAGS_$(basetarget).o) $(CXXFLAGS_$(obj)) +c_flags_1 = -Wp,-MD,$(depfile) -Wp,-MT,$@ $(CFLAGS) -D"BUILD_STR(s)=\#s" $(CFLAGS_$(basetarget).o) $(CFLAGS_$(obj)) +c_flags_2 = $(filter-out $(CFLAGS_REMOVE_$(basetarget).o), $(c_flags_1)) +c_flags = $(filter-out $(CFLAGS_REMOVE_$(obj)), $(c_flags_2)) +cxx_flags = -Wp,-MD,$(depfile) -Wp,-MT,$@ $(CXXFLAGS) -D"BUILD_STR(s)=\#s" $(CXXFLAGS_$(basetarget).o) $(CXXFLAGS_$(obj)) ### ## HOSTCC C flags -host_c_flags = -Wp,-MD,$(depfile),-MT,$@ $(CHOSTFLAGS) -D"BUILD_STR(s)=\#s" $(CHOSTFLAGS_$(basetarget).o) $(CHOSTFLAGS_$(obj)) +host_c_flags = -Wp,-MD,$(depfile) -Wp,-MT,$@ $(CHOSTFLAGS) -D"BUILD_STR(s)=\#s" $(CHOSTFLAGS_$(basetarget).o) $(CHOSTFLAGS_$(obj)) diff --git a/tools/build/Documentation/Build.txt b/tools/build/Documentation/Build.txt index a47bffbae159..a22587475dbe 100644 --- a/tools/build/Documentation/Build.txt +++ b/tools/build/Documentation/Build.txt @@ -135,8 +135,10 @@ CFLAGS It's possible to alter the standard object C flags in the following way: - CFLAGS_perf.o += '...' - alters CFLAGS for perf.o object - CFLAGS_gtk += '...' - alters CFLAGS for gtk build object + CFLAGS_perf.o += '...' - adds CFLAGS for perf.o object + CFLAGS_gtk += '...' - adds CFLAGS for gtk build object + CFLAGS_REMOVE_perf.o += '...' - removes CFLAGS for perf.o object + CFLAGS_REMOVE_gtk += '...' - removes CFLAGS for gtk build object This C flags changes has the scope of the Build makefile they are defined in. diff --git a/tools/build/Makefile.feature b/tools/build/Makefile.feature index ae52e029dd22..e3fb5ecbdcb6 100644 --- a/tools/build/Makefile.feature +++ b/tools/build/Makefile.feature @@ -27,58 +27,58 @@ endef # the rule that uses them - an example for that is the 'bionic' # feature check. ] # -FEATURE_TESTS_BASIC := \ - backtrace \ - dwarf \ - dwarf_getlocations \ - fortify-source \ - sync-compare-and-swap \ - glibc \ - gtk2 \ - gtk2-infobar \ - libaudit \ - libbfd \ - libelf \ - libelf-getphdrnum \ - libelf-gelf_getnote \ - libelf-getshdrstrndx \ - libelf-mmap \ - libnuma \ - numa_num_possible_cpus \ - libperl \ - libpython \ - libpython-version \ - libslang \ - libcrypto \ - libunwind \ - libunwind-x86 \ - libunwind-x86_64 \ - libunwind-arm \ - libunwind-aarch64 \ - pthread-attr-setaffinity-np \ - stackprotector-all \ - timerfd \ - libdw-dwarf-unwind \ - zlib \ - lzma \ - get_cpuid \ - bpf \ - sdt +FEATURE_TESTS_BASIC := \ + backtrace \ + dwarf \ + dwarf_getlocations \ + fortify-source \ + sync-compare-and-swap \ + glibc \ + gtk2 \ + gtk2-infobar \ + libaudit \ + libbfd \ + libelf \ + libelf-getphdrnum \ + libelf-gelf_getnote \ + libelf-getshdrstrndx \ + libelf-mmap \ + libnuma \ + numa_num_possible_cpus \ + libperl \ + libpython \ + libpython-version \ + libslang \ + libcrypto \ + libunwind \ + libunwind-x86 \ + libunwind-x86_64 \ + libunwind-arm \ + libunwind-aarch64 \ + pthread-attr-setaffinity-np \ + stackprotector-all \ + timerfd \ + libdw-dwarf-unwind \ + zlib \ + lzma \ + get_cpuid \ + bpf \ + sdt # FEATURE_TESTS_BASIC + FEATURE_TESTS_EXTRA is the complete list # of all feature tests -FEATURE_TESTS_EXTRA := \ - bionic \ - compile-32 \ - compile-x32 \ - cplus-demangle \ - hello \ - libbabeltrace \ - liberty \ - liberty-z \ - libunwind-debug-frame \ - libunwind-debug-frame-arm \ - libunwind-debug-frame-aarch64 +FEATURE_TESTS_EXTRA := \ + bionic \ + compile-32 \ + compile-x32 \ + cplus-demangle \ + hello \ + libbabeltrace \ + liberty \ + liberty-z \ + libunwind-debug-frame \ + libunwind-debug-frame-arm \ + libunwind-debug-frame-aarch64 FEATURE_TESTS ?= $(FEATURE_TESTS_BASIC) @@ -86,26 +86,26 @@ ifeq ($(FEATURE_TESTS),all) FEATURE_TESTS := $(FEATURE_TESTS_BASIC) $(FEATURE_TESTS_EXTRA) endif -FEATURE_DISPLAY ?= \ - dwarf \ - dwarf_getlocations \ - glibc \ - gtk2 \ - libaudit \ - libbfd \ - libelf \ - libnuma \ - numa_num_possible_cpus \ - libperl \ - libpython \ - libslang \ - libcrypto \ - libunwind \ - libdw-dwarf-unwind \ - zlib \ - lzma \ - get_cpuid \ - bpf +FEATURE_DISPLAY ?= \ + dwarf \ + dwarf_getlocations \ + glibc \ + gtk2 \ + libaudit \ + libbfd \ + libelf \ + libnuma \ + numa_num_possible_cpus \ + libperl \ + libpython \ + libslang \ + libcrypto \ + libunwind \ + libdw-dwarf-unwind \ + zlib \ + lzma \ + get_cpuid \ + bpf # Set FEATURE_CHECK_(C|LD)FLAGS-all for all FEATURE_TESTS features. # If in the future we need per-feature checks/flags for features not diff --git a/tools/build/feature/Makefile b/tools/build/feature/Makefile index ac9c477a2a48..b564a2eea039 100644 --- a/tools/build/feature/Makefile +++ b/tools/build/feature/Makefile @@ -1,59 +1,61 @@ -FILES= \ - test-all.bin \ - test-backtrace.bin \ - test-bionic.bin \ - test-dwarf.bin \ - test-dwarf_getlocations.bin \ - test-fortify-source.bin \ - test-sync-compare-and-swap.bin \ - test-glibc.bin \ - test-gtk2.bin \ - test-gtk2-infobar.bin \ - test-hello.bin \ - test-libaudit.bin \ - test-libbfd.bin \ - test-liberty.bin \ - test-liberty-z.bin \ - test-cplus-demangle.bin \ - test-libelf.bin \ - test-libelf-getphdrnum.bin \ - test-libelf-gelf_getnote.bin \ - test-libelf-getshdrstrndx.bin \ - test-libelf-mmap.bin \ - test-libnuma.bin \ - test-numa_num_possible_cpus.bin \ - test-libperl.bin \ - test-libpython.bin \ - test-libpython-version.bin \ - test-libslang.bin \ - test-libcrypto.bin \ - test-libunwind.bin \ - test-libunwind-debug-frame.bin \ - test-libunwind-x86.bin \ - test-libunwind-x86_64.bin \ - test-libunwind-arm.bin \ - test-libunwind-aarch64.bin \ - test-libunwind-debug-frame-arm.bin \ - test-libunwind-debug-frame-aarch64.bin \ - test-pthread-attr-setaffinity-np.bin \ - test-stackprotector-all.bin \ - test-timerfd.bin \ - test-libdw-dwarf-unwind.bin \ - test-libbabeltrace.bin \ - test-compile-32.bin \ - test-compile-x32.bin \ - test-zlib.bin \ - test-lzma.bin \ - test-bpf.bin \ - test-get_cpuid.bin \ - test-sdt.bin \ - test-cxx.bin +FILES= \ + test-all.bin \ + test-backtrace.bin \ + test-bionic.bin \ + test-dwarf.bin \ + test-dwarf_getlocations.bin \ + test-fortify-source.bin \ + test-sync-compare-and-swap.bin \ + test-glibc.bin \ + test-gtk2.bin \ + test-gtk2-infobar.bin \ + test-hello.bin \ + test-libaudit.bin \ + test-libbfd.bin \ + test-liberty.bin \ + test-liberty-z.bin \ + test-cplus-demangle.bin \ + test-libelf.bin \ + test-libelf-getphdrnum.bin \ + test-libelf-gelf_getnote.bin \ + test-libelf-getshdrstrndx.bin \ + test-libelf-mmap.bin \ + test-libnuma.bin \ + test-numa_num_possible_cpus.bin \ + test-libperl.bin \ + test-libpython.bin \ + test-libpython-version.bin \ + test-libslang.bin \ + test-libcrypto.bin \ + test-libunwind.bin \ + test-libunwind-debug-frame.bin \ + test-libunwind-x86.bin \ + test-libunwind-x86_64.bin \ + test-libunwind-arm.bin \ + test-libunwind-aarch64.bin \ + test-libunwind-debug-frame-arm.bin \ + test-libunwind-debug-frame-aarch64.bin \ + test-pthread-attr-setaffinity-np.bin \ + test-stackprotector-all.bin \ + test-timerfd.bin \ + test-libdw-dwarf-unwind.bin \ + test-libbabeltrace.bin \ + test-compile-32.bin \ + test-compile-x32.bin \ + test-zlib.bin \ + test-lzma.bin \ + test-bpf.bin \ + test-get_cpuid.bin \ + test-sdt.bin \ + test-cxx.bin \ + test-jvmti.bin FILES := $(addprefix $(OUTPUT),$(FILES)) CC := $(CROSS_COMPILE)gcc -MD CXX := $(CROSS_COMPILE)g++ -MD PKG_CONFIG := $(CROSS_COMPILE)pkg-config +LLVM_CONFIG ?= llvm-config all: $(FILES) @@ -225,6 +227,30 @@ $(OUTPUT)test-sdt.bin: $(OUTPUT)test-cxx.bin: $(BUILDXX) -std=gnu++11 +$(OUTPUT)test-jvmti.bin: + $(BUILD) + +$(OUTPUT)test-llvm.bin: + $(BUILDXX) -std=gnu++11 \ + -I$(shell $(LLVM_CONFIG) --includedir) \ + -L$(shell $(LLVM_CONFIG) --libdir) \ + $(shell $(LLVM_CONFIG) --libs Core BPF) \ + $(shell $(LLVM_CONFIG) --system-libs) + +$(OUTPUT)test-llvm-version.bin: + $(BUILDXX) -std=gnu++11 \ + -I$(shell $(LLVM_CONFIG) --includedir) + +$(OUTPUT)test-clang.bin: + $(BUILDXX) -std=gnu++11 \ + -I$(shell $(LLVM_CONFIG) --includedir) \ + -L$(shell $(LLVM_CONFIG) --libdir) \ + -Wl,--start-group -lclangBasic -lclangDriver \ + -lclangFrontend -lclangEdit -lclangLex \ + -lclangAST -Wl,--end-group \ + $(shell $(LLVM_CONFIG) --libs Core option) \ + $(shell $(LLVM_CONFIG) --system-libs) + -include $(OUTPUT)*.d ############################### diff --git a/tools/build/feature/test-clang.cpp b/tools/build/feature/test-clang.cpp new file mode 100644 index 000000000000..e23c1b1f1b91 --- /dev/null +++ b/tools/build/feature/test-clang.cpp @@ -0,0 +1,21 @@ +#include "clang/Basic/VirtualFileSystem.h" +#include "clang/Driver/Driver.h" +#include "clang/Frontend/TextDiagnosticPrinter.h" +#include "llvm/ADT/IntrusiveRefCntPtr.h" +#include "llvm/Support/ManagedStatic.h" +#include "llvm/Support/raw_ostream.h" + +using namespace clang; +using namespace clang::driver; + +int main() +{ + IntrusiveRefCntPtr<DiagnosticIDs> DiagID(new DiagnosticIDs()); + IntrusiveRefCntPtr<DiagnosticOptions> DiagOpts = new DiagnosticOptions(); + + DiagnosticsEngine Diags(DiagID, &*DiagOpts); + Driver TheDriver("test", "bpf-pc-linux", Diags); + + llvm::llvm_shutdown(); + return 0; +} diff --git a/tools/build/feature/test-jvmti.c b/tools/build/feature/test-jvmti.c new file mode 100644 index 000000000000..1c665f09b9d6 --- /dev/null +++ b/tools/build/feature/test-jvmti.c @@ -0,0 +1,13 @@ +#include <jvmti.h> +#include <jvmticmlr.h> + +int main(void) +{ + JavaVM jvm __attribute__((unused)); + jvmtiEventCallbacks cb __attribute__((unused)); + jvmtiCapabilities caps __attribute__((unused)); + jvmtiJlocationFormat format __attribute__((unused)); + jvmtiEnv jvmti __attribute__((unused)); + + return 0; +} diff --git a/tools/build/feature/test-llvm-version.cpp b/tools/build/feature/test-llvm-version.cpp new file mode 100644 index 000000000000..896d31724568 --- /dev/null +++ b/tools/build/feature/test-llvm-version.cpp @@ -0,0 +1,11 @@ +#include <cstdio> +#include "llvm/Config/llvm-config.h" + +#define NUM_VERSION (((LLVM_VERSION_MAJOR) << 16) + (LLVM_VERSION_MINOR << 8) + LLVM_VERSION_PATCH) +#define pass int main() {printf("%x\n", NUM_VERSION); return 0;} + +#if NUM_VERSION >= 0x030900 +pass +#else +# error This LLVM is not tested yet. +#endif diff --git a/tools/build/feature/test-llvm.cpp b/tools/build/feature/test-llvm.cpp new file mode 100644 index 000000000000..455a332dc8a8 --- /dev/null +++ b/tools/build/feature/test-llvm.cpp @@ -0,0 +1,13 @@ +#include "llvm/Support/ManagedStatic.h" +#include "llvm/Support/raw_ostream.h" +#define NUM_VERSION (((LLVM_VERSION_MAJOR) << 16) + (LLVM_VERSION_MINOR << 8) + LLVM_VERSION_PATCH) + +#if NUM_VERSION < 0x030900 +# error "LLVM version too low" +#endif +int main() +{ + llvm::errs() << "Hello World!\n"; + llvm::llvm_shutdown(); + return 0; +} diff --git a/tools/build/fixdep.c b/tools/build/fixdep.c index 1521d36cef0d..734d1547cbae 100644 --- a/tools/build/fixdep.c +++ b/tools/build/fixdep.c @@ -49,7 +49,7 @@ static void parse_dep_file(void *map, size_t len) char *end = m + len; char *p; char s[PATH_MAX]; - int is_target; + int is_target, has_target = 0; int saw_any_target = 0; int is_first_dep = 0; @@ -67,7 +67,8 @@ static void parse_dep_file(void *map, size_t len) if (is_target) { /* The /next/ file is the first dependency */ is_first_dep = 1; - } else { + has_target = 1; + } else if (has_target) { /* Save this token/filename */ memcpy(s, m, p-m); s[p - m] = 0; diff --git a/tools/include/asm-generic/bitops.h b/tools/include/asm-generic/bitops.h index 653d1bad77de..0304600121da 100644 --- a/tools/include/asm-generic/bitops.h +++ b/tools/include/asm-generic/bitops.h @@ -13,6 +13,7 @@ */ #include <asm-generic/bitops/__ffs.h> +#include <asm-generic/bitops/__ffz.h> #include <asm-generic/bitops/fls.h> #include <asm-generic/bitops/__fls.h> #include <asm-generic/bitops/fls64.h> diff --git a/tools/include/asm-generic/bitops/__ffz.h b/tools/include/asm-generic/bitops/__ffz.h new file mode 100644 index 000000000000..6744bd4cdf46 --- /dev/null +++ b/tools/include/asm-generic/bitops/__ffz.h @@ -0,0 +1,12 @@ +#ifndef _ASM_GENERIC_BITOPS_FFZ_H_ +#define _ASM_GENERIC_BITOPS_FFZ_H_ + +/* + * ffz - find first zero in word. + * @word: The word to search + * + * Undefined if no zero exists, so code should check against ~0UL first. + */ +#define ffz(x) __ffs(~(x)) + +#endif /* _ASM_GENERIC_BITOPS_FFZ_H_ */ diff --git a/tools/include/asm-generic/bitops/find.h b/tools/include/asm-generic/bitops/find.h index 31f51547fcd4..5538ecdc964a 100644 --- a/tools/include/asm-generic/bitops/find.h +++ b/tools/include/asm-generic/bitops/find.h @@ -15,6 +15,21 @@ extern unsigned long find_next_bit(const unsigned long *addr, unsigned long size, unsigned long offset); #endif +#ifndef find_next_zero_bit + +/** + * find_next_zero_bit - find the next cleared bit in a memory region + * @addr: The address to base the search on + * @offset: The bitnumber to start searching at + * @size: The bitmap size in bits + * + * Returns the bit number of the next zero bit + * If no bits are zero, returns @size. + */ +unsigned long find_next_zero_bit(const unsigned long *addr, unsigned long size, + unsigned long offset); +#endif + #ifndef find_first_bit /** @@ -30,4 +45,17 @@ extern unsigned long find_first_bit(const unsigned long *addr, #endif /* find_first_bit */ +#ifndef find_first_zero_bit + +/** + * find_first_zero_bit - find the first cleared bit in a memory region + * @addr: The address to start the search at + * @size: The maximum number of bits to search + * + * Returns the bit number of the first cleared bit. + * If no bits are zero, returns @size. + */ +unsigned long find_first_zero_bit(const unsigned long *addr, unsigned long size); +#endif + #endif /*_TOOLS_LINUX_ASM_GENERIC_BITOPS_FIND_H_ */ diff --git a/tools/include/linux/bitops.h b/tools/include/linux/bitops.h index 49c929a104ee..fc446343ff41 100644 --- a/tools/include/linux/bitops.h +++ b/tools/include/linux/bitops.h @@ -39,6 +39,11 @@ extern unsigned long __sw_hweight64(__u64 w); (bit) < (size); \ (bit) = find_next_bit((addr), (size), (bit) + 1)) +#define for_each_clear_bit(bit, addr, size) \ + for ((bit) = find_first_zero_bit((addr), (size)); \ + (bit) < (size); \ + (bit) = find_next_zero_bit((addr), (size), (bit) + 1)) + /* same as for_each_set_bit() but use bit as value to start with */ #define for_each_set_bit_from(bit, addr, size) \ for ((bit) = find_next_bit((addr), (size), (bit)); \ diff --git a/tools/include/uapi/asm-generic/mman-common.h b/tools/include/uapi/asm-generic/mman-common.h index 58274382a616..8c27db0c5c08 100644 --- a/tools/include/uapi/asm-generic/mman-common.h +++ b/tools/include/uapi/asm-generic/mman-common.h @@ -72,4 +72,9 @@ #define MAP_HUGE_SHIFT 26 #define MAP_HUGE_MASK 0x3f +#define PKEY_DISABLE_ACCESS 0x1 +#define PKEY_DISABLE_WRITE 0x2 +#define PKEY_ACCESS_MASK (PKEY_DISABLE_ACCESS |\ + PKEY_DISABLE_WRITE) + #endif /* __ASM_GENERIC_MMAN_COMMON_H */ diff --git a/tools/lib/bpf/bpf.c b/tools/lib/bpf/bpf.c index 4212ed62235b..8143536b462a 100644 --- a/tools/lib/bpf/bpf.c +++ b/tools/lib/bpf/bpf.c @@ -110,3 +110,59 @@ int bpf_map_update_elem(int fd, void *key, void *value, return sys_bpf(BPF_MAP_UPDATE_ELEM, &attr, sizeof(attr)); } + +int bpf_map_lookup_elem(int fd, void *key, void *value) +{ + union bpf_attr attr; + + bzero(&attr, sizeof(attr)); + attr.map_fd = fd; + attr.key = ptr_to_u64(key); + attr.value = ptr_to_u64(value); + + return sys_bpf(BPF_MAP_LOOKUP_ELEM, &attr, sizeof(attr)); +} + +int bpf_map_delete_elem(int fd, void *key) +{ + union bpf_attr attr; + + bzero(&attr, sizeof(attr)); + attr.map_fd = fd; + attr.key = ptr_to_u64(key); + + return sys_bpf(BPF_MAP_DELETE_ELEM, &attr, sizeof(attr)); +} + +int bpf_map_get_next_key(int fd, void *key, void *next_key) +{ + union bpf_attr attr; + + bzero(&attr, sizeof(attr)); + attr.map_fd = fd; + attr.key = ptr_to_u64(key); + attr.next_key = ptr_to_u64(next_key); + + return sys_bpf(BPF_MAP_GET_NEXT_KEY, &attr, sizeof(attr)); +} + +int bpf_obj_pin(int fd, const char *pathname) +{ + union bpf_attr attr; + + bzero(&attr, sizeof(attr)); + attr.pathname = ptr_to_u64((void *)pathname); + attr.bpf_fd = fd; + + return sys_bpf(BPF_OBJ_PIN, &attr, sizeof(attr)); +} + +int bpf_obj_get(const char *pathname) +{ + union bpf_attr attr; + + bzero(&attr, sizeof(attr)); + attr.pathname = ptr_to_u64((void *)pathname); + + return sys_bpf(BPF_OBJ_GET, &attr, sizeof(attr)); +} diff --git a/tools/lib/bpf/bpf.h b/tools/lib/bpf/bpf.h index e8ba54087497..253c3dbb06b4 100644 --- a/tools/lib/bpf/bpf.h +++ b/tools/lib/bpf/bpf.h @@ -35,4 +35,11 @@ int bpf_load_program(enum bpf_prog_type type, struct bpf_insn *insns, int bpf_map_update_elem(int fd, void *key, void *value, u64 flags); + +int bpf_map_lookup_elem(int fd, void *key, void *value); +int bpf_map_delete_elem(int fd, void *key); +int bpf_map_get_next_key(int fd, void *key, void *next_key); +int bpf_obj_pin(int fd, const char *pathname); +int bpf_obj_get(const char *pathname); + #endif diff --git a/tools/lib/bpf/libbpf.c b/tools/lib/bpf/libbpf.c index b699aea9a025..2e974593f3e8 100644 --- a/tools/lib/bpf/libbpf.c +++ b/tools/lib/bpf/libbpf.c @@ -185,6 +185,7 @@ struct bpf_program { struct bpf_map { int fd; char *name; + size_t offset; struct bpf_map_def def; void *priv; bpf_map_clear_priv_t clear_priv; @@ -228,6 +229,10 @@ struct bpf_object { * all objects. */ struct list_head list; + + void *priv; + bpf_object_clear_priv_t clear_priv; + char path[]; }; #define obj_elf_valid(o) ((o)->efile.elf) @@ -513,57 +518,106 @@ bpf_object__init_kversion(struct bpf_object *obj, } static int -bpf_object__init_maps(struct bpf_object *obj, void *data, - size_t size) +bpf_object__validate_maps(struct bpf_object *obj) { - size_t nr_maps; int i; - nr_maps = size / sizeof(struct bpf_map_def); - if (!data || !nr_maps) { - pr_debug("%s doesn't need map definition\n", - obj->path); + /* + * If there's only 1 map, the only error case should have been + * catched in bpf_object__init_maps(). + */ + if (!obj->maps || !obj->nr_maps || (obj->nr_maps == 1)) return 0; - } - pr_debug("maps in %s: %zd bytes\n", obj->path, size); + for (i = 1; i < obj->nr_maps; i++) { + const struct bpf_map *a = &obj->maps[i - 1]; + const struct bpf_map *b = &obj->maps[i]; - obj->maps = calloc(nr_maps, sizeof(obj->maps[0])); - if (!obj->maps) { - pr_warning("alloc maps for object failed\n"); - return -ENOMEM; + if (b->offset - a->offset < sizeof(struct bpf_map_def)) { + pr_warning("corrupted map section in %s: map \"%s\" too small\n", + obj->path, a->name); + return -EINVAL; + } } - obj->nr_maps = nr_maps; - - for (i = 0; i < nr_maps; i++) { - struct bpf_map_def *def = &obj->maps[i].def; + return 0; +} - /* - * fill all fd with -1 so won't close incorrect - * fd (fd=0 is stdin) when failure (zclose won't close - * negative fd)). - */ - obj->maps[i].fd = -1; +static int compare_bpf_map(const void *_a, const void *_b) +{ + const struct bpf_map *a = _a; + const struct bpf_map *b = _b; - /* Save map definition into obj->maps */ - *def = ((struct bpf_map_def *)data)[i]; - } - return 0; + return a->offset - b->offset; } static int -bpf_object__init_maps_name(struct bpf_object *obj) +bpf_object__init_maps(struct bpf_object *obj) { - int i; + int i, map_idx, nr_maps = 0; + Elf_Scn *scn; + Elf_Data *data; Elf_Data *symbols = obj->efile.symbols; - if (!symbols || obj->efile.maps_shndx < 0) + if (obj->efile.maps_shndx < 0) + return -EINVAL; + if (!symbols) + return -EINVAL; + + scn = elf_getscn(obj->efile.elf, obj->efile.maps_shndx); + if (scn) + data = elf_getdata(scn, NULL); + if (!scn || !data) { + pr_warning("failed to get Elf_Data from map section %d\n", + obj->efile.maps_shndx); return -EINVAL; + } + /* + * Count number of maps. Each map has a name. + * Array of maps is not supported: only the first element is + * considered. + * + * TODO: Detect array of map and report error. + */ for (i = 0; i < symbols->d_size / sizeof(GElf_Sym); i++) { GElf_Sym sym; - size_t map_idx; + + if (!gelf_getsym(symbols, i, &sym)) + continue; + if (sym.st_shndx != obj->efile.maps_shndx) + continue; + nr_maps++; + } + + /* Alloc obj->maps and fill nr_maps. */ + pr_debug("maps in %s: %d maps in %zd bytes\n", obj->path, + nr_maps, data->d_size); + + if (!nr_maps) + return 0; + + obj->maps = calloc(nr_maps, sizeof(obj->maps[0])); + if (!obj->maps) { + pr_warning("alloc maps for object failed\n"); + return -ENOMEM; + } + obj->nr_maps = nr_maps; + + /* + * fill all fd with -1 so won't close incorrect + * fd (fd=0 is stdin) when failure (zclose won't close + * negative fd)). + */ + for (i = 0; i < nr_maps; i++) + obj->maps[i].fd = -1; + + /* + * Fill obj->maps using data in "maps" section. + */ + for (i = 0, map_idx = 0; i < symbols->d_size / sizeof(GElf_Sym); i++) { + GElf_Sym sym; const char *map_name; + struct bpf_map_def *def; if (!gelf_getsym(symbols, i, &sym)) continue; @@ -573,21 +627,27 @@ bpf_object__init_maps_name(struct bpf_object *obj) map_name = elf_strptr(obj->efile.elf, obj->efile.strtabidx, sym.st_name); - map_idx = sym.st_value / sizeof(struct bpf_map_def); - if (map_idx >= obj->nr_maps) { - pr_warning("index of map \"%s\" is buggy: %zu > %zu\n", - map_name, map_idx, obj->nr_maps); - continue; + obj->maps[map_idx].offset = sym.st_value; + if (sym.st_value + sizeof(struct bpf_map_def) > data->d_size) { + pr_warning("corrupted maps section in %s: last map \"%s\" too small\n", + obj->path, map_name); + return -EINVAL; } + obj->maps[map_idx].name = strdup(map_name); if (!obj->maps[map_idx].name) { pr_warning("failed to alloc map name\n"); return -ENOMEM; } - pr_debug("map %zu is \"%s\"\n", map_idx, + pr_debug("map %d is \"%s\"\n", map_idx, obj->maps[map_idx].name); + def = (struct bpf_map_def *)(data->d_buf + sym.st_value); + obj->maps[map_idx].def = *def; + map_idx++; } - return 0; + + qsort(obj->maps, obj->nr_maps, sizeof(obj->maps[0]), compare_bpf_map); + return bpf_object__validate_maps(obj); } static int bpf_object__elf_collect(struct bpf_object *obj) @@ -645,11 +705,9 @@ static int bpf_object__elf_collect(struct bpf_object *obj) err = bpf_object__init_kversion(obj, data->d_buf, data->d_size); - else if (strcmp(name, "maps") == 0) { - err = bpf_object__init_maps(obj, data->d_buf, - data->d_size); + else if (strcmp(name, "maps") == 0) obj->efile.maps_shndx = idx; - } else if (sh.sh_type == SHT_SYMTAB) { + else if (sh.sh_type == SHT_SYMTAB) { if (obj->efile.symbols) { pr_warning("bpf: multiple SYMTAB in %s\n", obj->path); @@ -698,7 +756,7 @@ static int bpf_object__elf_collect(struct bpf_object *obj) return LIBBPF_ERRNO__FORMAT; } if (obj->efile.maps_shndx >= 0) - err = bpf_object__init_maps_name(obj); + err = bpf_object__init_maps(obj); out: return err; } @@ -807,7 +865,7 @@ bpf_object__create_maps(struct bpf_object *obj) zclose(obj->maps[j].fd); return err; } - pr_debug("create map: fd=%d\n", *pfd); + pr_debug("create map %s: fd=%d\n", obj->maps[i].name, *pfd); } return 0; @@ -1175,6 +1233,9 @@ void bpf_object__close(struct bpf_object *obj) if (!obj) return; + if (obj->clear_priv) + obj->clear_priv(obj, obj->priv); + bpf_object__elf_finish(obj); bpf_object__unload(obj); @@ -1228,6 +1289,22 @@ unsigned int bpf_object__kversion(struct bpf_object *obj) return obj ? obj->kern_version : 0; } +int bpf_object__set_priv(struct bpf_object *obj, void *priv, + bpf_object_clear_priv_t clear_priv) +{ + if (obj->priv && obj->clear_priv) + obj->clear_priv(obj, obj->priv); + + obj->priv = priv; + obj->clear_priv = clear_priv; + return 0; +} + +void *bpf_object__priv(struct bpf_object *obj) +{ + return obj ? obj->priv : ERR_PTR(-EINVAL); +} + struct bpf_program * bpf_program__next(struct bpf_program *prev, struct bpf_object *obj) { @@ -1447,3 +1524,15 @@ bpf_object__find_map_by_name(struct bpf_object *obj, const char *name) } return NULL; } + +struct bpf_map * +bpf_object__find_map_by_offset(struct bpf_object *obj, size_t offset) +{ + int i; + + for (i = 0; i < obj->nr_maps; i++) { + if (obj->maps[i].offset == offset) + return &obj->maps[i]; + } + return ERR_PTR(-ENOENT); +} diff --git a/tools/lib/bpf/libbpf.h b/tools/lib/bpf/libbpf.h index dd7a513efb10..a5a8b86a06fe 100644 --- a/tools/lib/bpf/libbpf.h +++ b/tools/lib/bpf/libbpf.h @@ -24,6 +24,7 @@ #include <stdio.h> #include <stdbool.h> #include <linux/err.h> +#include <sys/types.h> // for size_t enum libbpf_errno { __LIBBPF_ERRNO__START = 4000, @@ -79,6 +80,11 @@ struct bpf_object *bpf_object__next(struct bpf_object *prev); (pos) != NULL; \ (pos) = (tmp), (tmp) = bpf_object__next(tmp)) +typedef void (*bpf_object_clear_priv_t)(struct bpf_object *, void *); +int bpf_object__set_priv(struct bpf_object *obj, void *priv, + bpf_object_clear_priv_t clear_priv); +void *bpf_object__priv(struct bpf_object *prog); + /* Accessors of bpf_program. */ struct bpf_program; struct bpf_program *bpf_program__next(struct bpf_program *prog, @@ -195,6 +201,13 @@ struct bpf_map; struct bpf_map * bpf_object__find_map_by_name(struct bpf_object *obj, const char *name); +/* + * Get bpf_map through the offset of corresponding struct bpf_map_def + * in the bpf object file. + */ +struct bpf_map * +bpf_object__find_map_by_offset(struct bpf_object *obj, size_t offset); + struct bpf_map * bpf_map__next(struct bpf_map *map, struct bpf_object *obj); #define bpf_map__for_each(pos, obj) \ diff --git a/tools/lib/find_bit.c b/tools/lib/find_bit.c index 9122a9e80046..6d8b8f22cf55 100644 --- a/tools/lib/find_bit.c +++ b/tools/lib/find_bit.c @@ -82,3 +82,28 @@ unsigned long find_first_bit(const unsigned long *addr, unsigned long size) return size; } #endif + +#ifndef find_first_zero_bit +/* + * Find the first cleared bit in a memory region. + */ +unsigned long find_first_zero_bit(const unsigned long *addr, unsigned long size) +{ + unsigned long idx; + + for (idx = 0; idx * BITS_PER_LONG < size; idx++) { + if (addr[idx] != ~0UL) + return min(idx * BITS_PER_LONG + ffz(addr[idx]), size); + } + + return size; +} +#endif + +#ifndef find_next_zero_bit +unsigned long find_next_zero_bit(const unsigned long *addr, unsigned long size, + unsigned long offset) +{ + return _find_next_bit(addr, size, offset, ~0UL); +} +#endif diff --git a/tools/lib/subcmd/parse-options.c b/tools/lib/subcmd/parse-options.c index 981bb4481fd5..3284bb14ae78 100644 --- a/tools/lib/subcmd/parse-options.c +++ b/tools/lib/subcmd/parse-options.c @@ -314,12 +314,19 @@ static int get_value(struct parse_opt_ctx_t *p, static int parse_short_opt(struct parse_opt_ctx_t *p, const struct option *options) { +retry: for (; options->type != OPTION_END; options++) { if (options->short_name == *p->opt) { p->opt = p->opt[1] ? p->opt + 1 : NULL; return get_value(p, options, OPT_SHORT); } } + + if (options->parent) { + options = options->parent; + goto retry; + } + return -2; } @@ -333,6 +340,7 @@ static int parse_long_opt(struct parse_opt_ctx_t *p, const char *arg, if (!arg_end) arg_end = arg + strlen(arg); +retry: for (; options->type != OPTION_END; options++) { const char *rest; int flags = 0; @@ -426,6 +434,12 @@ match: } if (abbrev_option) return get_value(p, abbrev_option, abbrev_flags); + + if (options->parent) { + options = options->parent; + goto retry; + } + return -2; } diff --git a/tools/lib/subcmd/parse-options.h b/tools/lib/subcmd/parse-options.h index d60cab2726da..8866ac438b34 100644 --- a/tools/lib/subcmd/parse-options.h +++ b/tools/lib/subcmd/parse-options.h @@ -109,11 +109,13 @@ struct option { intptr_t defval; bool *set; void *data; + const struct option *parent; }; #define check_vtype(v, type) ( BUILD_BUG_ON_ZERO(!__builtin_types_compatible_p(typeof(v), type)) + v ) #define OPT_END() { .type = OPTION_END } +#define OPT_PARENT(p) { .type = OPTION_END, .parent = (p) } #define OPT_ARGUMENT(l, h) { .type = OPTION_ARGUMENT, .long_name = (l), .help = (h) } #define OPT_GROUP(h) { .type = OPTION_GROUP, .help = (h) } #define OPT_BIT(s, l, v, h, b) { .type = OPTION_BIT, .short_name = (s), .long_name = (l), .value = check_vtype(v, int *), .help = (h), .defval = (b) } diff --git a/tools/lib/traceevent/Makefile b/tools/lib/traceevent/Makefile index 7851df1490e0..c76012ebdb9c 100644 --- a/tools/lib/traceevent/Makefile +++ b/tools/lib/traceevent/Makefile @@ -99,8 +99,6 @@ libdir_SQ = $(subst ','\'',$(libdir)) libdir_relative_SQ = $(subst ','\'',$(libdir_relative)) plugin_dir_SQ = $(subst ','\'',$(plugin_dir)) -LIB_FILE = libtraceevent.a libtraceevent.so - CONFIG_INCLUDES = CONFIG_LIBS = CONFIG_FLAGS = @@ -114,6 +112,9 @@ N = EVENT_PARSE_VERSION = $(EP_VERSION).$(EP_PATCHLEVEL).$(EP_EXTRAVERSION) +LIB_TARGET = libtraceevent.a libtraceevent.so.$(EVENT_PARSE_VERSION) +LIB_INSTALL = libtraceevent.a libtraceevent.so* + INCLUDES = -I. -I $(srctree)/tools/include $(CONFIG_INCLUDES) # Set compile option CFLAGS @@ -156,11 +157,11 @@ PLUGINS += plugin_cfg80211.so PLUGINS := $(addprefix $(OUTPUT),$(PLUGINS)) PLUGINS_IN := $(PLUGINS:.so=-in.o) -TE_IN := $(OUTPUT)libtraceevent-in.o -LIB_FILE := $(addprefix $(OUTPUT),$(LIB_FILE)) +TE_IN := $(OUTPUT)libtraceevent-in.o +LIB_TARGET := $(addprefix $(OUTPUT),$(LIB_TARGET)) DYNAMIC_LIST_FILE := $(OUTPUT)libtraceevent-dynamic-list -CMD_TARGETS = $(LIB_FILE) $(PLUGINS) $(DYNAMIC_LIST_FILE) +CMD_TARGETS = $(LIB_TARGET) $(PLUGINS) $(DYNAMIC_LIST_FILE) TARGETS = $(CMD_TARGETS) @@ -171,8 +172,10 @@ all_cmd: $(CMD_TARGETS) $(TE_IN): force $(Q)$(MAKE) $(build)=libtraceevent -$(OUTPUT)libtraceevent.so: $(TE_IN) - $(QUIET_LINK)$(CC) --shared $^ -o $@ +$(OUTPUT)libtraceevent.so.$(EVENT_PARSE_VERSION): $(TE_IN) + $(QUIET_LINK)$(CC) --shared $^ -Wl,-soname,libtraceevent.so.$(EP_VERSION) -o $@ + @ln -sf $(@F) $(OUTPUT)libtraceevent.so + @ln -sf $(@F) $(OUTPUT)libtraceevent.so.$(EP_VERSION) $(OUTPUT)libtraceevent.a: $(TE_IN) $(QUIET_LINK)$(RM) $@; $(AR) rcs $@ $^ @@ -236,11 +239,15 @@ TAGS: force find . -name '*.[ch]' | xargs etags \ --regex='/_PE(\([^,)]*\).*/PEVENT_ERRNO__\1/' +define do_install_mkdir + if [ ! -d '$(DESTDIR_SQ)$1' ]; then \ + $(INSTALL) -d -m 755 '$(DESTDIR_SQ)$1'; \ + fi +endef + define do_install - if [ ! -d '$(DESTDIR_SQ)$2' ]; then \ - $(INSTALL) -d -m 755 '$(DESTDIR_SQ)$2'; \ - fi; \ - $(INSTALL) $1 '$(DESTDIR_SQ)$2' + $(call do_install_mkdir,$2); \ + $(INSTALL) $(if $3,-m $3,) $1 '$(DESTDIR_SQ)$2' endef define do_install_plugins @@ -257,13 +264,20 @@ define do_generate_dynamic_list_file endef install_lib: all_cmd install_plugins - $(call QUIET_INSTALL, $(LIB_FILE)) \ - $(call do_install,$(LIB_FILE),$(libdir_SQ)) + $(call QUIET_INSTALL, $(LIB_TARGET)) \ + $(call do_install_mkdir,$(libdir_SQ)); \ + cp -fpR $(LIB_INSTALL) $(DESTDIR)$(libdir_SQ) install_plugins: $(PLUGINS) $(call QUIET_INSTALL, trace_plugins) \ $(call do_install_plugins, $(PLUGINS)) +install_headers: + $(call QUIET_INSTALL, headers) \ + $(call do_install,event-parse.h,$(prefix)/include/traceevent,644); \ + $(call do_install,event-utils.h,$(prefix)/include/traceevent,644); \ + $(call do_install,kbuffer.h,$(prefix)/include/traceevent,644) + install: install_lib clean: diff --git a/tools/lib/traceevent/event-parse.c b/tools/lib/traceevent/event-parse.c index 664c90c8e22b..14a4f623c1a5 100644 --- a/tools/lib/traceevent/event-parse.c +++ b/tools/lib/traceevent/event-parse.c @@ -33,6 +33,7 @@ #include <stdint.h> #include <limits.h> #include <linux/string.h> +#include <linux/time64.h> #include <netinet/in.h> #include "event-parse.h" @@ -5191,11 +5192,11 @@ struct event_format *pevent_data_event_from_type(struct pevent *pevent, int type } /** - * pevent_data_pid - parse the PID from raw data + * pevent_data_pid - parse the PID from record * @pevent: a handle to the pevent * @rec: the record to parse * - * This returns the PID from a raw data. + * This returns the PID from a record. */ int pevent_data_pid(struct pevent *pevent, struct pevent_record *rec) { @@ -5203,6 +5204,32 @@ int pevent_data_pid(struct pevent *pevent, struct pevent_record *rec) } /** + * pevent_data_prempt_count - parse the preempt count from the record + * @pevent: a handle to the pevent + * @rec: the record to parse + * + * This returns the preempt count from a record. + */ +int pevent_data_prempt_count(struct pevent *pevent, struct pevent_record *rec) +{ + return parse_common_pc(pevent, rec->data); +} + +/** + * pevent_data_flags - parse the latency flags from the record + * @pevent: a handle to the pevent + * @rec: the record to parse + * + * This returns the latency flags from a record. + * + * Use trace_flag_type enum for the flags (see event-parse.h). + */ +int pevent_data_flags(struct pevent *pevent, struct pevent_record *rec) +{ + return parse_common_flags(pevent, rec->data); +} + +/** * pevent_data_comm_from_pid - return the command line from PID * @pevent: a handle to the pevent * @pid: the PID of the task to search for @@ -5424,8 +5451,8 @@ void pevent_print_event_time(struct pevent *pevent, struct trace_seq *s, use_usec_format = is_timestamp_in_us(pevent->trace_clock, use_trace_clock); if (use_usec_format) { - secs = record->ts / NSECS_PER_SEC; - nsecs = record->ts - secs * NSECS_PER_SEC; + secs = record->ts / NSEC_PER_SEC; + nsecs = record->ts - secs * NSEC_PER_SEC; } if (pevent->latency_format) { @@ -5437,10 +5464,10 @@ void pevent_print_event_time(struct pevent *pevent, struct trace_seq *s, usecs = nsecs; p = 9; } else { - usecs = (nsecs + 500) / NSECS_PER_USEC; + usecs = (nsecs + 500) / NSEC_PER_USEC; /* To avoid usecs larger than 1 sec */ - if (usecs >= 1000000) { - usecs -= 1000000; + if (usecs >= USEC_PER_SEC) { + usecs -= USEC_PER_SEC; secs++; } p = 6; diff --git a/tools/lib/traceevent/event-parse.h b/tools/lib/traceevent/event-parse.h index 9ffde377e89d..7aae746ec2fe 100644 --- a/tools/lib/traceevent/event-parse.h +++ b/tools/lib/traceevent/event-parse.h @@ -172,9 +172,6 @@ struct pevent_plugin_option { #define PEVENT_PLUGIN_OPTIONS_NAME MAKE_STR(PEVENT_PLUGIN_OPTIONS) #define PEVENT_PLUGIN_ALIAS_NAME MAKE_STR(PEVENT_PLUGIN_ALIAS) -#define NSECS_PER_SEC 1000000000ULL -#define NSECS_PER_USEC 1000ULL - enum format_flags { FIELD_IS_ARRAY = 1, FIELD_IS_POINTER = 2, @@ -712,6 +709,8 @@ void pevent_data_lat_fmt(struct pevent *pevent, int pevent_data_type(struct pevent *pevent, struct pevent_record *rec); struct event_format *pevent_data_event_from_type(struct pevent *pevent, int type); int pevent_data_pid(struct pevent *pevent, struct pevent_record *rec); +int pevent_data_prempt_count(struct pevent *pevent, struct pevent_record *rec); +int pevent_data_flags(struct pevent *pevent, struct pevent_record *rec); const char *pevent_data_comm_from_pid(struct pevent *pevent, int pid); struct cmdline; struct cmdline *pevent_data_pid_from_comm(struct pevent *pevent, const char *comm, diff --git a/tools/perf/Build b/tools/perf/Build index a43fae7f439a..b12d5d1666e3 100644 --- a/tools/perf/Build +++ b/tools/perf/Build @@ -21,6 +21,7 @@ perf-y += builtin-inject.o perf-y += builtin-mem.o perf-y += builtin-data.o perf-y += builtin-version.o +perf-y += builtin-c2c.o perf-$(CONFIG_AUDIT) += builtin-trace.o perf-$(CONFIG_LIBELF) += builtin-probe.o diff --git a/tools/perf/Documentation/intel-pt.txt b/tools/perf/Documentation/intel-pt.txt index c6c8318e38a2..b0b3007d3c9c 100644 --- a/tools/perf/Documentation/intel-pt.txt +++ b/tools/perf/Documentation/intel-pt.txt @@ -550,6 +550,18 @@ Unless /proc/sys/kernel/perf_event_paranoid is set to -1, unprivileged users have memory limits imposed upon them. That affects what buffer sizes they can have as outlined above. +The v4.2 kernel introduced support for a context switch metadata event, +PERF_RECORD_SWITCH, which allows unprivileged users to see when their processes +are scheduled out and in, just not by whom, which is left for the +PERF_RECORD_SWITCH_CPU_WIDE, that is only accessible in system wide context, +which in turn requires CAP_SYS_ADMIN. + +Please see the 45ac1403f564 ("perf: Add PERF_RECORD_SWITCH to indicate context +switches") commit, that introduces these metadata events for further info. + +When working with kernels < v4.2, the following considerations must be taken, +as the sched:sched_switch tracepoints will be used to receive such information: + Unless /proc/sys/kernel/perf_event_paranoid is set to -1, unprivileged users are not permitted to use tracepoints which means there is insufficient side-band information to decode Intel PT in per-cpu mode, and potentially workload-only @@ -564,8 +576,11 @@ sched_switch tracepoint ----------------------- The sched_switch tracepoint is used to provide side-band data for Intel PT -decoding. sched_switch events are automatically added. e.g. the second event -shown below +decoding in kernels where the PERF_RECORD_SWITCH metadata event isn't +available. + +The sched_switch events are automatically added. e.g. the second event shown +below: $ perf record -vv -e intel_pt//u uname ------------------------------------------------------------ diff --git a/tools/perf/Documentation/jitdump-specification.txt b/tools/perf/Documentation/jitdump-specification.txt new file mode 100644 index 000000000000..4c62b0713651 --- /dev/null +++ b/tools/perf/Documentation/jitdump-specification.txt @@ -0,0 +1,170 @@ +JITDUMP specification version 2 +Last Revised: 09/15/2016 +Author: Stephane Eranian <eranian@gmail.com> + +-------------------------------------------------------- +| Revision | Date | Description | +-------------------------------------------------------- +| 1 | 09/07/2016 | Initial revision | +-------------------------------------------------------- +| 2 | 09/15/2016 | Add JIT_CODE_UNWINDING_INFO | +-------------------------------------------------------- + + +I/ Introduction + + +This document describes the jitdump file format. The file is generated by Just-In-time compiler runtimes to save meta-data information about the generated code, such as address, size, and name of generated functions, the native code generated, the source line information. The data may then be used by performance tools, such as Linux perf to generate function and assembly level profiles. + +The format is not specific to any particular programming language. It can be extended as need be. + +The format of the file is binary. It is self-describing in terms of endianness and is portable across multiple processor architectures. + + +II/ Overview of the format + + +The format requires only sequential accesses, i.e., append only mode. The file starts with a fixed size file header describing the version of the specification, the endianness. + +The header is followed by a series of records, each starting with a fixed size header describing the type of record and its size. It is, itself, followed by the payload for the record. Records can have a variable size even for a given type. + +Each entry in the file is timestamped. All timestamps must use the same clock source. The CLOCK_MONOTONIC clock source is recommended. + + +III/ Jitdump file header format + +Each jitdump file starts with a fixed size header containing the following fields in order: + + +* uint32_t magic : a magic number tagging the file type. The value is 4-byte long and represents the string "JiTD" in ASCII form. It is 0x4A695444 or 0x4454694a depending on the endianness. The field can be used to detect the endianness of the file +* uint32_t version : a 4-byte value representing the format version. It is currently set to 2 +* uint32_t total_size: size in bytes of file header +* uint32_t elf_mach : ELF architecture encoding (ELF e_machine value as specified in /usr/include/elf.h) +* uint32_t pad1 : padding. Reserved for future use +* uint32_t pid : JIT runtime process identification (OS specific) +* uint64_t timestamp : timestamp of when the file was created +* uint64_t flags : a bitmask of flags + +The flags currently defined are as follows: + * bit 0: JITDUMP_FLAGS_ARCH_TIMESTAMP : set if the jitdump file is using an architecture-specific timestamp clock source. For instance, on x86, one could use TSC directly + +IV/ Record header + +The file header is immediately followed by records. Each record starts with a fixed size header describing the record that follows. + +The record header is specified in order as follows: +* uint32_t id : a value identifying the record type (see below) +* uint32_t total_size: the size in bytes of the record including the header. +* uint64_t timestamp : a timestamp of when the record was created. + +The following record types are defined: + * Value 0 : JIT_CODE_LOAD : record describing a jitted function + * Value 1 : JIT_CODE_MOVE : record describing an already jitted function which is moved + * Value 2 : JIT_CODE_DEBUG_INFO: record describing the debug information for a jitted function + * Value 3 : JIT_CODE_CLOSE : record marking the end of the jit runtime (optional) + * Value 4 : JIT_CODE_UNWINDING_INFO: record describing a function unwinding information + + The payload of the record must immediately follow the record header without padding. + +V/ JIT_CODE_LOAD record + + + The record has the following fields following the fixed-size record header in order: + * uint32_t pid: OS process id of the runtime generating the jitted code + * uint32_t tid: OS thread identification of the runtime thread generating the jitted code + * uint64_t vma: virtual address of jitted code start + * uint64_t code_addr: code start address for the jitted code. By default vma = code_addr + * uint64_t code_size: size in bytes of the generated jitted code + * uint64_t code_index: unique identifier for the jitted code (see below) + * char[n]: function name in ASCII including the null termination + * native code: raw byte encoding of the jitted code + + The record header total_size field is inclusive of all components: + * record header + * fixed-sized fields + * function name string, including termination + * native code length + * record specific variable data (e.g., array of data entries) + +The code_index is used to uniquely identify each jitted function. The index can be a monotonically increasing 64-bit value. Each time a function is jitted it gets a new number. This value is used in case the code for a function is moved and avoids having to issue another JIT_CODE_LOAD record. + +The format supports empty functions with no native code. + + +VI/ JIT_CODE_MOVE record + + The record type is optional. + + The record has the following fields following the fixed-size record header in order: + * uint32_t pid : OS process id of the runtime generating the jitted code + * uint32_t tid : OS thread identification of the runtime thread generating the jitted code + * uint64_t vma : new virtual address of jitted code start + * uint64_t old_code_addr: previous code address for the same function + * uint64_t new_code_addr: alternate new code started address for the jitted code. By default it should be equal to the vma address. + * uint64_t code_size : size in bytes of the jitted code + * uint64_t code_index : index referring to the JIT_CODE_LOAD code_index record of when the function was initially jitted + + +The MOVE record can be used in case an already jitted function is simply moved by the runtime inside the code cache. + +The JIT_CODE_MOVE record cannot come before the JIT_CODE_LOAD record for the same function name. The function cannot have changed name, otherwise a new JIT_CODE_LOAD record must be emitted. + +The code size of the function cannot change. + + +VII/ JIT_DEBUG_INFO record + +The record type is optional. + +The record contains source lines debug information, i.e., a way to map a code address back to a source line. This information may be used by the performance tool. + +The record has the following fields following the fixed-size record header in order: + * uint64_t code_addr: address of function for which the debug information is generated + * uint64_t nr_entry : number of debug entries for the function + * debug_entry[n]: array of nr_entry debug entries for the function + +The debug_entry describes the source line information. It is defined as follows in order: +* uint64_t code_addr: address of function for which the debug information is generated +* uint32_t line : source file line number (starting at 1) +* uint32_t discrim : column discriminator, 0 is default +* char name[n] : source file name in ASCII, including null termination + +The debug_entry entries are saved in sequence but given that they have variable sizes due to the file name string, they cannot be indexed directly. +They need to be walked sequentially. The next debug_entry is found at sizeof(debug_entry) + strlen(name) + 1. + +IMPORTANT: + The JIT_CODE_DEBUG for a given function must always be generated BEFORE the JIT_CODE_LOAD for the function. This facilitates greatly the parser for the jitdump file. + + +VIII/ JIT_CODE_CLOSE record + + +The record type is optional. + +The record is used as a marker for the end of the jitted runtime. It can be replaced by the end of the file. + +The JIT_CODE_CLOSE record does not have any specific fields, the record header contains all the information needed. + + +IX/ JIT_CODE_UNWINDING_INFO + + +The record type is optional. + +The record is used to describe the unwinding information for a jitted function. + +The record has the following fields following the fixed-size record header in order: + +uint64_t unwind_data_size : the size in bytes of the unwinding data table at the end of the record +uint64_t eh_frame_hdr_size : the size in bytes of the DWARF EH Frame Header at the start of the unwinding data table at the end of the record +uint64_t mapped_size : the size of the unwinding data mapped in memory +const char unwinding_data[n]: an array of unwinding data, consisting of the EH Frame Header, followed by the actual EH Frame + + +The EH Frame header follows the Linux Standard Base (LSB) specification as described in the document at https://refspecs.linuxfoundation.org/LSB_1.3.0/gLSB/gLSB/ehframehdr.html + + +The EH Frame follows the LSB specicfication as described in the document at https://refspecs.linuxbase.org/LSB_3.0.0/LSB-PDA/LSB-PDA/ehframechpt.html + + +NOTE: The mapped_size is generally either the same as unwind_data_size (if the unwinding data was mapped in memory by the running process) or zero (if the unwinding data is not mapped by the process). If the unwinding data was not mapped, then only the EH Frame Header will be read, which can be used to specify FP based unwinding for a function which does not have unwinding information. diff --git a/tools/perf/Documentation/perf-c2c.txt b/tools/perf/Documentation/perf-c2c.txt new file mode 100644 index 000000000000..3f06730c7f47 --- /dev/null +++ b/tools/perf/Documentation/perf-c2c.txt @@ -0,0 +1,290 @@ +perf-c2c(1) +=========== + +NAME +---- +perf-c2c - Shared Data C2C/HITM Analyzer. + +SYNOPSIS +-------- +[verse] +'perf c2c record' [<options>] <command> +'perf c2c record' [<options>] -- [<record command options>] <command> +'perf c2c report' [<options>] + +DESCRIPTION +----------- +C2C stands for Cache To Cache. + +The perf c2c tool provides means for Shared Data C2C/HITM analysis. It allows +you to track down the cacheline contentions. + +The tool is based on x86's load latency and precise store facility events +provided by Intel CPUs. These events provide: + - memory address of the access + - type of the access (load and store details) + - latency (in cycles) of the load access + +The c2c tool provide means to record this data and report back access details +for cachelines with highest contention - highest number of HITM accesses. + +The basic workflow with this tool follows the standard record/report phase. +User uses the record command to record events data and report command to +display it. + + +RECORD OPTIONS +-------------- +-e:: +--event=:: + Select the PMU event. Use 'perf mem record -e list' + to list available events. + +-v:: +--verbose:: + Be more verbose (show counter open errors, etc). + +-l:: +--ldlat:: + Configure mem-loads latency. + +-k:: +--all-kernel:: + Configure all used events to run in kernel space. + +-u:: +--all-user:: + Configure all used events to run in user space. + +REPORT OPTIONS +-------------- +-k:: +--vmlinux=<file>:: + vmlinux pathname + +-v:: +--verbose:: + Be more verbose (show counter open errors, etc). + +-i:: +--input:: + Specify the input file to process. + +-N:: +--node-info:: + Show extra node info in report (see NODE INFO section) + +-c:: +--coalesce:: + Specify sorintg fields for single cacheline display. + Following fields are available: tid,pid,iaddr,dso + (see COALESCE) + +-g:: +--call-graph:: + Setup callchains parameters. + Please refer to perf-report man page for details. + +--stdio:: + Force the stdio output (see STDIO OUTPUT) + +--stats:: + Display only statistic tables and force stdio mode. + +--full-symbols:: + Display full length of symbols. + +--no-source:: + Do not display Source:Line column. + +--show-all:: + Show all captured HITM lines, with no regard to HITM % 0.0005 limit. + +-f:: +--force:: + Don't do ownership validation. + +-d:: +--display:: + Siwtch to HITM type (rmt, lcl) to display and sort on. Total HITMs as default. + +C2C RECORD +---------- +The perf c2c record command setup options related to HITM cacheline analysis +and calls standard perf record command. + +Following perf record options are configured by default: +(check perf record man page for details) + + -W,-d,--sample-cpu + +Unless specified otherwise with '-e' option, following events are monitored by +default: + + cpu/mem-loads,ldlat=30/P + cpu/mem-stores/P + +User can pass any 'perf record' option behind '--' mark, like (to enable +callchains and system wide monitoring): + + $ perf c2c record -- -g -a + +Please check RECORD OPTIONS section for specific c2c record options. + +C2C REPORT +---------- +The perf c2c report command displays shared data analysis. It comes in two +display modes: stdio and tui (default). + +The report command workflow is following: + - sort all the data based on the cacheline address + - store access details for each cacheline + - sort all cachelines based on user settings + - display data + +In general perf report output consist of 2 basic views: + 1) most expensive cachelines list + 2) offsets details for each cacheline + +For each cacheline in the 1) list we display following data: +(Both stdio and TUI modes follow the same fields output) + + Index + - zero based index to identify the cacheline + + Cacheline + - cacheline address (hex number) + + Total records + - sum of all cachelines accesses + + Rmt/Lcl Hitm + - cacheline percentage of all Remote/Local HITM accesses + + LLC Load Hitm - Total, Lcl, Rmt + - count of Total/Local/Remote load HITMs + + Store Reference - Total, L1Hit, L1Miss + Total - all store accesses + L1Hit - store accesses that hit L1 + L1Hit - store accesses that missed L1 + + Load Dram + - count of local and remote DRAM accesses + + LLC Ld Miss + - count of all accesses that missed LLC + + Total Loads + - sum of all load accesses + + Core Load Hit - FB, L1, L2 + - count of load hits in FB (Fill Buffer), L1 and L2 cache + + LLC Load Hit - Llc, Rmt + - count of LLC and Remote load hits + +For each offset in the 2) list we display following data: + + HITM - Rmt, Lcl + - % of Remote/Local HITM accesses for given offset within cacheline + + Store Refs - L1 Hit, L1 Miss + - % of store accesses that hit/missed L1 for given offset within cacheline + + Data address - Offset + - offset address + + Pid + - pid of the process responsible for the accesses + + Tid + - tid of the process responsible for the accesses + + Code address + - code address responsible for the accesses + + cycles - rmt hitm, lcl hitm, load + - sum of cycles for given accesses - Remote/Local HITM and generic load + + cpu cnt + - number of cpus that participated on the access + + Symbol + - code symbol related to the 'Code address' value + + Shared Object + - shared object name related to the 'Code address' value + + Source:Line + - source information related to the 'Code address' value + + Node + - nodes participating on the access (see NODE INFO section) + +NODE INFO +--------- +The 'Node' field displays nodes that accesses given cacheline +offset. Its output comes in 3 flavors: + - node IDs separated by ',' + - node IDs with stats for each ID, in following format: + Node{cpus %hitms %stores} + - node IDs with list of affected CPUs in following format: + Node{cpu list} + +User can switch between above flavors with -N option or +use 'n' key to interactively switch in TUI mode. + +COALESCE +-------- +User can specify how to sort offsets for cacheline. + +Following fields are available and governs the final +output fields set for caheline offsets output: + + tid - coalesced by process TIDs + pid - coalesced by process PIDs + iaddr - coalesced by code address, following fields are displayed: + Code address, Code symbol, Shared Object, Source line + dso - coalesced by shared object + +By default the coalescing is setup with 'pid,tid,iaddr'. + +STDIO OUTPUT +------------ +The stdio output displays data on standard output. + +Following tables are displayed: + Trace Event Information + - overall statistics of memory accesses + + Global Shared Cache Line Event Information + - overall statistics on shared cachelines + + Shared Data Cache Line Table + - list of most expensive cachelines + + Shared Cache Line Distribution Pareto + - list of all accessed offsets for each cacheline + +TUI OUTPUT +---------- +The TUI output provides interactive interface to navigate +through cachelines list and to display offset details. + +For details please refer to the help window by pressing '?' key. + +CREDITS +------- +Although Don Zickus, Dick Fowles and Joe Mario worked together +to get this implemented, we got lots of early help from Arnaldo +Carvalho de Melo, Stephane Eranian, Jiri Olsa and Andi Kleen. + +C2C BLOG +-------- +Check Joe's blog on c2c tool for detailed use case explanation: + https://joemario.github.io/blog/2016/09/01/c2c-blog/ + +SEE ALSO +-------- +linkperf:perf-record[1], linkperf:perf-mem[1] diff --git a/tools/perf/Documentation/perf-config.txt b/tools/perf/Documentation/perf-config.txt index cb081ac59fd1..9365b75fd04f 100644 --- a/tools/perf/Documentation/perf-config.txt +++ b/tools/perf/Documentation/perf-config.txt @@ -8,6 +8,8 @@ perf-config - Get and set variables in a configuration file. SYNOPSIS -------- [verse] +'perf config' [<file-option>] [section.name[=value] ...] +or 'perf config' [<file-option>] -l | --list DESCRIPTION @@ -118,6 +120,39 @@ Given a $HOME/.perfconfig like this: children = true group = true +You can hide source code of annotate feature setting the config to false with + + % perf config annotate.hide_src_code=true + +If you want to add or modify several config items, you can do like + + % perf config ui.show-headers=false kmem.default=slab + +To modify the sort order of report functionality in user config file(i.e. `~/.perfconfig`), do + + % perf config --user report sort-order=srcline + +To change colors of selected line to other foreground and background colors +in system config file (i.e. `$(sysconf)/perfconfig`), do + + % perf config --system colors.selected=yellow,green + +To query the record mode of call graph, do + + % perf config call-graph.record-mode + +If you want to know multiple config key/value pairs, you can do like + + % perf config report.queue-size call-graph.order report.children + +To query the config value of sort order of call graph in user config file (i.e. `~/.perfconfig`), do + + % perf config --user call-graph.sort-order + +To query the config value of buildid directory in system config file (i.e. `$(sysconf)/perfconfig`), do + + % perf config --system buildid.dir + Variables ~~~~~~~~~ diff --git a/tools/perf/Documentation/perf-kmem.txt b/tools/perf/Documentation/perf-kmem.txt index ff0f433b3fce..479fc3261a50 100644 --- a/tools/perf/Documentation/perf-kmem.txt +++ b/tools/perf/Documentation/perf-kmem.txt @@ -61,6 +61,13 @@ OPTIONS default, but this option shows live (currently allocated) pages instead. (This option works with --page option only) +--time:: + Only analyze samples within given time window: <start>,<stop>. Times + have the format seconds.microseconds. If start is not given (i.e., time + string is ',x.y') then analysis starts at the beginning of the file. If + stop time is not given (i.e, time string is 'x.y,') then analysis goes + to end of file. + SEE ALSO -------- linkperf:perf-record[1] diff --git a/tools/perf/Documentation/perf-record.txt b/tools/perf/Documentation/perf-record.txt index 92335193dc33..27fc3617c6a4 100644 --- a/tools/perf/Documentation/perf-record.txt +++ b/tools/perf/Documentation/perf-record.txt @@ -45,9 +45,9 @@ OPTIONS param1 and param2 are defined as formats for the PMU in: /sys/bus/event_source/devices/<pmu>/format/* - There are also some params which are not defined in .../<pmu>/format/*. + There are also some parameters which are not defined in .../<pmu>/format/*. These params can be used to overload default config values per event. - Here is a list of the params. + Here are some common parameters: - 'period': Set event sampling period - 'freq': Set event sampling frequency - 'time': Disable/enable time stamping. Acceptable values are 1 for @@ -57,8 +57,11 @@ OPTIONS FP mode, "dwarf" for DWARF mode, "lbr" for LBR mode and "no" for disable callgraph. - 'stack-size': user stack size for dwarf mode + + See the linkperf:perf-list[1] man page for more parameters. + Note: If user explicitly sets options which conflict with the params, - the value set by the params will be overridden. + the value set by the parameters will be overridden. Also not defined in .../<pmu>/format/* are PMU driver specific configuration parameters. Any configuration parameter preceded by diff --git a/tools/perf/Documentation/perf-report.txt b/tools/perf/Documentation/perf-report.txt index 2d1746295abf..f2914f03ae7b 100644 --- a/tools/perf/Documentation/perf-report.txt +++ b/tools/perf/Documentation/perf-report.txt @@ -239,7 +239,8 @@ OPTIONS Accumulate callchain of children to parent entry so that then can show up in the output. The output will have a new "Children" column and will be sorted on the data. It requires callchains are recorded. - See the `overhead calculation' section for more details. + See the `overhead calculation' section for more details. Enabled by + default, disable with --no-children. --max-stack:: Set the stack depth limit when parsing the callchain, anything @@ -382,6 +383,13 @@ OPTIONS --header-only:: Show only perf.data header (forces --stdio). +--time:: + Only analyze samples within given time window: <start>,<stop>. Times + have the format seconds.microseconds. If start is not given (i.e., time + string is ',x.y') then analysis starts at the beginning of the file. If + stop time is not given (i.e, time string is 'x.y,') then analysis goes + to end of file. + --itrace:: Options for decoding instruction tracing data. The options are: diff --git a/tools/perf/Documentation/perf-sched.txt b/tools/perf/Documentation/perf-sched.txt index 1cc08cc47ac5..7775b1eb2bee 100644 --- a/tools/perf/Documentation/perf-sched.txt +++ b/tools/perf/Documentation/perf-sched.txt @@ -8,11 +8,11 @@ perf-sched - Tool to trace/measure scheduler properties (latencies) SYNOPSIS -------- [verse] -'perf sched' {record|latency|map|replay|script} +'perf sched' {record|latency|map|replay|script|timehist} DESCRIPTION ----------- -There are five variants of perf sched: +There are several variants of 'perf sched': 'perf sched record <command>' to record the scheduling events of an arbitrary workload. @@ -36,6 +36,30 @@ There are five variants of perf sched: are running on a CPU. A '*' denotes the CPU that had the event, and a dot signals an idle CPU. + 'perf sched timehist' provides an analysis of scheduling events. + + Example usage: + perf sched record -- sleep 1 + perf sched timehist + + By default it shows the individual schedule events, including the wait + time (time between sched-out and next sched-in events for the task), the + task scheduling delay (time between wakeup and actually running) and run + time for the task: + + time cpu task name wait time sch delay run time + [tid/pid] (msec) (msec) (msec) + -------------- ------ -------------------- --------- --------- --------- + 79371.874569 [0011] gcc[31949] 0.014 0.000 1.148 + 79371.874591 [0010] gcc[31951] 0.000 0.000 0.024 + 79371.874603 [0010] migration/10[59] 3.350 0.004 0.011 + 79371.874604 [0011] <idle> 1.148 0.000 0.035 + 79371.874723 [0005] <idle> 0.016 0.000 1.383 + 79371.874746 [0005] gcc[31949] 0.153 0.078 0.022 + ... + + Times are in msec.usec. + OPTIONS ------- -i:: @@ -66,6 +90,56 @@ OPTIONS for 'perf sched map' --color-pids:: Highlight the given pids. +OPTIONS for 'perf sched timehist' +--------------------------------- +-k:: +--vmlinux=<file>:: + vmlinux pathname + +--kallsyms=<file>:: + kallsyms pathname + +-g:: +--no-call-graph:: + Do not display call chains if present. + +--max-stack:: + Maximum number of functions to display in backtrace, default 5. + +-s:: +--summary:: + Show only a summary of scheduling by thread with min, max, and average + run times (in sec) and relative stddev. + +-S:: +--with-summary:: + Show all scheduling events followed by a summary by thread with min, + max, and average run times (in sec) and relative stddev. + +--symfs=<directory>:: + Look for files with symbols relative to this directory. + +-V:: +--cpu-visual:: + Show visual aid for sched switches by CPU: 'i' marks idle time, + 's' are scheduler events. + +-w:: +--wakeups:: + Show wakeup events. + +-M:: +--migrations:: + Show migration events. + +--time:: + Only analyze samples within given time window: <start>,<stop>. Times + have the format seconds.microseconds. If start is not given (i.e., time + string is ',x.y') then analysis starts at the beginning of the file. If + stop time is not given (i.e, time string is 'x.y,') then analysis goes + to end of file. + + SEE ALSO -------- linkperf:perf-record[1] diff --git a/tools/perf/Documentation/perf-script.txt b/tools/perf/Documentation/perf-script.txt index 053bbbd84ece..5dc5c6a09ac4 100644 --- a/tools/perf/Documentation/perf-script.txt +++ b/tools/perf/Documentation/perf-script.txt @@ -117,7 +117,7 @@ OPTIONS Comma separated list of fields to print. Options are: comm, tid, pid, time, cpu, event, trace, ip, sym, dso, addr, symoff, srcline, period, iregs, brstack, brstacksym, flags, bpf-output, - callindent. Field list can be prepended with the type, trace, sw or hw, + callindent, insn, insnlen. Field list can be prepended with the type, trace, sw or hw, to indicate to which event type the field list applies. e.g., -F sw:comm,tid,time,ip,sym and -F trace:time,cpu,trace @@ -181,6 +181,10 @@ OPTIONS Instruction Trace decoding. For calls and returns, it will display the name of the symbol indented with spaces to reflect the stack depth. + When doing instruction trace decoding insn and insnlen give the + instruction bytes and the instruction length of the current + instruction. + Finally, a user may not set fields to none for all event types. i.e., -F "" is not allowed. @@ -208,6 +212,9 @@ OPTIONS --hide-call-graph:: When printing symbols do not display call chain. +--stop-bt:: + Stop display of callgraph at these symbols + -C:: --cpu:: Only report samples for the list of CPUs provided. Multiple CPUs can be provided as a comma-separated list with no space: 0,1. Ranges of @@ -285,6 +292,13 @@ include::itrace.txt[] --force:: Don't do ownership validation. +--time:: + Only analyze samples within given time window: <start>,<stop>. Times + have the format seconds.microseconds. If start is not given (i.e., time + string is ',x.y') then analysis starts at the beginning of the file. If + stop time is not given (i.e, time string is 'x.y,') then analysis goes + to end of file. + SEE ALSO -------- linkperf:perf-record[1], linkperf:perf-script-perl[1], diff --git a/tools/perf/Documentation/perf-top.txt b/tools/perf/Documentation/perf-top.txt index 91d638df3a6b..e71d63843f45 100644 --- a/tools/perf/Documentation/perf-top.txt +++ b/tools/perf/Documentation/perf-top.txt @@ -170,6 +170,7 @@ Default is to monitor all CPUS. show up in the output. The output will have a new "Children" column and will be sorted on the data. It requires -g/--call-graph option enabled. See the `overhead calculation' section for more details. + Enabled by default, disable with --no-children. --max-stack:: Set the stack depth limit when parsing the callchain, anything diff --git a/tools/perf/Documentation/perf-trace.txt b/tools/perf/Documentation/perf-trace.txt index 1ab0782369b1..781b019751a4 100644 --- a/tools/perf/Documentation/perf-trace.txt +++ b/tools/perf/Documentation/perf-trace.txt @@ -39,6 +39,11 @@ OPTIONS Prefixing with ! shows all syscalls but the ones specified. You may need to escape it. +-D msecs:: +--delay msecs:: +After starting the program, wait msecs before measuring. This is useful to +filter out the startup phase of the program, which is often very different. + -o:: --output=:: Output file name. diff --git a/tools/perf/MANIFEST b/tools/perf/MANIFEST index 0bda2cca2b3a..a511e5f31e36 100644 --- a/tools/perf/MANIFEST +++ b/tools/perf/MANIFEST @@ -51,6 +51,7 @@ tools/include/asm-generic/bitops/arch_hweight.h tools/include/asm-generic/bitops/atomic.h tools/include/asm-generic/bitops/const_hweight.h tools/include/asm-generic/bitops/__ffs.h +tools/include/asm-generic/bitops/__ffz.h tools/include/asm-generic/bitops/__fls.h tools/include/asm-generic/bitops/find.h tools/include/asm-generic/bitops/fls64.h diff --git a/tools/perf/Makefile.config b/tools/perf/Makefile.config index 72edf83d76b7..76c84f0eec52 100644 --- a/tools/perf/Makefile.config +++ b/tools/perf/Makefile.config @@ -136,6 +136,7 @@ endif # Treat warnings as errors unless directed not to ifneq ($(WERROR),0) CFLAGS += -Werror + CXXFLAGS += -Werror endif ifndef DEBUG @@ -182,6 +183,13 @@ CFLAGS += -Wall CFLAGS += -Wextra CFLAGS += -std=gnu99 +CXXFLAGS += -std=gnu++11 -fno-exceptions -fno-rtti +CXXFLAGS += -Wall +CXXFLAGS += -fno-omit-frame-pointer +CXXFLAGS += -ggdb3 +CXXFLAGS += -funwind-tables +CXXFLAGS += -Wno-strict-aliasing + # Enforce a non-executable stack, as we may regress (again) in the future by # adding assembler files missing the .GNU-stack linker note. LDFLAGS += -Wl,-z,noexecstack @@ -204,24 +212,27 @@ ifeq ($(DEBUG),0) endif endif -CFLAGS += -I$(src-perf)/util/include -CFLAGS += -I$(src-perf)/arch/$(ARCH)/include -CFLAGS += -I$(srctree)/tools/include/uapi -CFLAGS += -I$(srctree)/tools/include/ -CFLAGS += -I$(srctree)/tools/arch/$(ARCH)/include/uapi -CFLAGS += -I$(srctree)/tools/arch/$(ARCH)/include/ -CFLAGS += -I$(srctree)/tools/arch/$(ARCH)/ +INC_FLAGS += -I$(src-perf)/util/include +INC_FLAGS += -I$(src-perf)/arch/$(ARCH)/include +INC_FLAGS += -I$(srctree)/tools/include/uapi +INC_FLAGS += -I$(srctree)/tools/include/ +INC_FLAGS += -I$(srctree)/tools/arch/$(ARCH)/include/uapi +INC_FLAGS += -I$(srctree)/tools/arch/$(ARCH)/include/ +INC_FLAGS += -I$(srctree)/tools/arch/$(ARCH)/ # $(obj-perf) for generated common-cmds.h # $(obj-perf)/util for generated bison/flex headers ifneq ($(OUTPUT),) -CFLAGS += -I$(obj-perf)/util -CFLAGS += -I$(obj-perf) +INC_FLAGS += -I$(obj-perf)/util +INC_FLAGS += -I$(obj-perf) endif -CFLAGS += -I$(src-perf)/util -CFLAGS += -I$(src-perf) -CFLAGS += -I$(srctree)/tools/lib/ +INC_FLAGS += -I$(src-perf)/util +INC_FLAGS += -I$(src-perf) +INC_FLAGS += -I$(srctree)/tools/lib/ + +CFLAGS += $(INC_FLAGS) +CXXFLAGS += $(INC_FLAGS) CFLAGS += -D_LARGEFILE64_SOURCE -D_FILE_OFFSET_BITS=64 -D_GNU_SOURCE @@ -366,7 +377,7 @@ ifndef NO_SDT endif ifdef PERF_HAVE_JITDUMP - ifndef NO_DWARF + ifndef NO_LIBELF $(call detected,CONFIG_JITDUMP) CFLAGS += -DHAVE_JITDUMP endif @@ -758,6 +769,62 @@ ifndef NO_AUXTRACE endif endif +ifndef NO_JVMTI + ifneq (,$(wildcard /usr/sbin/update-java-alternatives)) + JDIR=$(shell /usr/sbin/update-java-alternatives -l | head -1 | awk '{print $$3}') + else + ifneq (,$(wildcard /usr/sbin/alternatives)) + JDIR=$(shell alternatives --display java | tail -1 | cut -d' ' -f 5 | sed 's%/jre/bin/java.%%g') + endif + endif + ifndef JDIR + $(warning No alternatives command found, you need to set JDIR= to point to the root of your Java directory) + NO_JVMTI := 1 + endif +endif + +ifndef NO_JVMTI + FEATURE_CHECK_CFLAGS-jvmti := -I$(JDIR)/include -I$(JDIR)/include/linux + $(call feature_check,jvmti) + ifeq ($(feature-jvmti), 1) + $(call detected_var,JDIR) + else + $(warning No openjdk development package found, please install JDK package) + NO_JVMTI := 1 + endif +endif + +USE_CXX = 0 +USE_CLANGLLVM = 0 +ifdef LIBCLANGLLVM + $(call feature_check,cxx) + ifneq ($(feature-cxx), 1) + msg := $(warning No g++ found, disable clang and llvm support. Please install g++) + else + $(call feature_check,llvm) + $(call feature_check,llvm-version) + ifneq ($(feature-llvm), 1) + msg := $(warning No suitable libLLVM found, disabling builtin clang and LLVM support. Please install llvm-dev(el) (>= 3.9.0)) + else + $(call feature_check,clang) + ifneq ($(feature-clang), 1) + msg := $(warning No suitable libclang found, disabling builtin clang and LLVM support. Please install libclang-dev(el) (>= 3.9.0)) + else + CFLAGS += -DHAVE_LIBCLANGLLVM_SUPPORT + CXXFLAGS += -DHAVE_LIBCLANGLLVM_SUPPORT -I$(shell $(LLVM_CONFIG) --includedir) + $(call detected,CONFIG_CXX) + $(call detected,CONFIG_CLANGLLVM) + USE_CXX = 1 + USE_LLVM = 1 + USE_CLANG = 1 + ifneq ($(feature-llvm-version),1) + msg := $(warning This version of LLVM is not tested. May cause build errors) + endif + endif + endif + endif +endif + # Among the variables below, these: # perfexecdir # template_dir @@ -850,6 +917,7 @@ ifeq ($(VF),1) $(call print_var,sysconfdir) $(call print_var,LIBUNWIND_DIR) $(call print_var,LIBDW_DIR) + $(call print_var,JDIR) ifeq ($(dwarf-post-unwind),1) $(call feature_print_text,"DWARF post unwind library", $(dwarf-post-unwind-text)) diff --git a/tools/perf/Makefile.perf b/tools/perf/Makefile.perf index 982d6439bb07..8f1c258b151a 100644 --- a/tools/perf/Makefile.perf +++ b/tools/perf/Makefile.perf @@ -86,6 +86,12 @@ include ../scripts/utilities.mak # # Define FEATURES_DUMP to provide features detection dump file # and bypass the feature detection +# +# Define NO_JVMTI if you do not want jvmti agent built +# +# Define LIBCLANGLLVM if you DO want builtin clang and llvm support. +# When selected, pass LLVM_CONFIG=/path/to/llvm-config to `make' if +# llvm-config is not in $PATH. # As per kernel Makefile, avoid funny character set dependencies unexport LC_ALL @@ -122,10 +128,6 @@ endif # (this improves performance and avoids hard-to-debug behaviour); MAKEFLAGS += -r -$(OUTPUT)PERF-VERSION-FILE: ../../.git/HEAD - $(Q)$(SHELL_PATH) util/PERF-VERSION-GEN $(OUTPUT) - $(Q)touch $(OUTPUT)PERF-VERSION-FILE - # Makefiles suck: This macro sets a default value of $(2) for the # variable named by $(1), unless the variable has been set by # environment or command line. This is necessary for CC and AR @@ -141,6 +143,7 @@ endef $(call allow-override,CC,$(CROSS_COMPILE)gcc) $(call allow-override,AR,$(CROSS_COMPILE)ar) $(call allow-override,LD,$(CROSS_COMPILE)ld) +$(call allow-override,CXX,$(CROSS_COMPILE)g++) LD += $(EXTRA_LDFLAGS) @@ -149,6 +152,7 @@ HOSTLD ?= ld HOSTAR ?= ar PKG_CONFIG = $(CROSS_COMPILE)pkg-config +LLVM_CONFIG ?= llvm-config RM = rm -f LN = ln -f @@ -160,16 +164,11 @@ BISON = bison STRIP = strip AWK = awk -LIB_DIR = $(srctree)/tools/lib/api/ -TRACE_EVENT_DIR = $(srctree)/tools/lib/traceevent/ -BPF_DIR = $(srctree)/tools/lib/bpf/ -SUBCMD_DIR = $(srctree)/tools/lib/subcmd/ - # include Makefile.config by default and rule out # non-config cases config := 1 -NON_CONFIG_TARGETS := clean TAGS tags cscope help install-doc +NON_CONFIG_TARGETS := clean TAGS tags cscope help install-doc install-man install-html install-info install-pdf doc man html info pdf ifdef MAKECMDGOALS ifeq ($(filter-out $(NON_CONFIG_TARGETS),$(MAKECMDGOALS)),) @@ -177,6 +176,40 @@ ifeq ($(filter-out $(NON_CONFIG_TARGETS),$(MAKECMDGOALS)),) endif endif +# The fixdep build - we force fixdep tool to be built as +# the first target in the separate make session not to be +# disturbed by any parallel make jobs. Once fixdep is done +# we issue the requested build with FIXDEP=1 variable. +# +# The fixdep build is disabled for $(NON_CONFIG_TARGETS) +# targets, because it's not necessary. + +ifdef FIXDEP + force_fixdep := 0 +else + force_fixdep := $(config) +endif + +export srctree OUTPUT RM CC CXX LD AR CFLAGS CXXFLAGS V BISON FLEX AWK +export HOSTCC HOSTLD HOSTAR + +include $(srctree)/tools/build/Makefile.include + +ifeq ($(force_fixdep),1) +goals := $(filter-out all sub-make, $(MAKECMDGOALS)) + +$(goals) all: sub-make + +sub-make: fixdep + $(Q)$(MAKE) FIXDEP=1 -f Makefile.perf $(goals) + +else # force_fixdep + +LIB_DIR = $(srctree)/tools/lib/api/ +TRACE_EVENT_DIR = $(srctree)/tools/lib/traceevent/ +BPF_DIR = $(srctree)/tools/lib/bpf/ +SUBCMD_DIR = $(srctree)/tools/lib/subcmd/ + # Set FEATURE_TESTS to 'all' so all possible feature checkers are executed. # Without this setting the output feature dump file misses some features, for # example, liberty. Select all checkers so we won't get an incomplete feature @@ -260,17 +293,6 @@ python-clean := $(call QUIET_CLEAN, python) $(RM) -r $(PYTHON_EXTBUILD) $(OUTPUT PYTHON_EXT_SRCS := $(shell grep -v ^\# util/python-ext-sources) PYTHON_EXT_DEPS := util/python-ext-sources util/setup.py $(LIBTRACEEVENT) $(LIBAPI) -$(OUTPUT)python/perf.so: $(PYTHON_EXT_SRCS) $(PYTHON_EXT_DEPS) $(LIBTRACEEVENT_DYNAMIC_LIST) - $(QUIET_GEN)LDSHARED="$(CC) -pthread -shared" \ - CFLAGS='$(CFLAGS)' LDFLAGS='$(LDFLAGS) $(LIBTRACEEVENT_DYNAMIC_LIST_LDFLAGS)' \ - $(PYTHON_WORD) util/setup.py \ - --quiet build_ext; \ - mkdir -p $(OUTPUT)python && \ - cp $(PYTHON_EXTBUILD_LIB)perf.so $(OUTPUT)python/ -# -# No Perl scripts right now: -# - SCRIPTS = $(patsubst %.sh,%,$(SCRIPT_SH)) PROGRAMS += $(OUTPUT)perf @@ -283,6 +305,12 @@ ifndef NO_PERF_READ_VDSOX32 PROGRAMS += $(OUTPUT)perf-read-vdsox32 endif +LIBJVMTI = libperf-jvmti.so + +ifndef NO_JVMTI +PROGRAMS += $(OUTPUT)$(LIBJVMTI) +endif + # what 'all' will build and 'install' will install, in perfexecdir ALL_PROGRAMS = $(PROGRAMS) $(SCRIPTS) @@ -317,11 +345,6 @@ endif ifndef NO_GTK2 ALL_PROGRAMS += $(OUTPUT)libperf-gtk.so GTK_IN := $(OUTPUT)gtk-in.o - -install-gtk: $(OUTPUT)libperf-gtk.so - $(call QUIET_INSTALL, 'GTK UI') \ - $(INSTALL) -d -m 755 '$(DESTDIR_SQ)$(libdir_SQ)'; \ - $(INSTALL) $(OUTPUT)libperf-gtk.so '$(DESTDIR_SQ)$(libdir_SQ)' endif ifdef ASCIIDOC8 @@ -330,6 +353,21 @@ endif LIBS = -Wl,--whole-archive $(PERFLIBS) -Wl,--no-whole-archive -Wl,--start-group $(EXTLIBS) -Wl,--end-group +ifeq ($(USE_CLANG), 1) + CLANGLIBS_LIST = AST Basic CodeGen Driver Frontend Lex Tooling Edit Sema Analysis Parse Serialization + LIBCLANG = $(foreach l,$(CLANGLIBS_LIST),$(wildcard $(shell $(LLVM_CONFIG) --libdir)/libclang$(l).a)) + LIBS += -Wl,--start-group $(LIBCLANG) -Wl,--end-group +endif + +ifeq ($(USE_LLVM), 1) + LIBLLVM = $(shell $(LLVM_CONFIG) --libs all) $(shell $(LLVM_CONFIG) --system-libs) + LIBS += -L$(shell $(LLVM_CONFIG) --libdir) $(LIBLLVM) +endif + +ifeq ($(USE_CXX), 1) + LIBS += -lstdc++ +endif + export INSTALL SHELL_PATH ### Build rules @@ -338,6 +376,14 @@ SHELL = $(SHELL_PATH) all: shell_compatibility_test $(ALL_PROGRAMS) $(LANG_BINDINGS) $(OTHER_PROGRAMS) +$(OUTPUT)python/perf.so: $(PYTHON_EXT_SRCS) $(PYTHON_EXT_DEPS) $(LIBTRACEEVENT_DYNAMIC_LIST) + $(QUIET_GEN)LDSHARED="$(CC) -pthread -shared" \ + CFLAGS='$(CFLAGS)' LDFLAGS='$(LDFLAGS) $(LIBTRACEEVENT_DYNAMIC_LIST_LDFLAGS)' \ + $(PYTHON_WORD) util/setup.py \ + --quiet build_ext; \ + mkdir -p $(OUTPUT)python && \ + cp $(PYTHON_EXTBUILD_LIB)perf.so $(OUTPUT)python/ + please_set_SHELL_PATH_to_a_more_modern_shell: $(Q)$$(:) @@ -348,10 +394,6 @@ strip: $(PROGRAMS) $(OUTPUT)perf PERF_IN := $(OUTPUT)perf-in.o -export srctree OUTPUT RM CC LD AR CFLAGS V BISON FLEX AWK -export HOSTCC HOSTLD HOSTAR -include $(srctree)/tools/build/Makefile.include - JEVENTS := $(OUTPUT)pmu-events/jevents JEVENTS_IN := $(OUTPUT)pmu-events/jevents-in.o @@ -381,10 +423,10 @@ $(PERF_IN): prepare FORCE (diff -B ../arch/x86/include/asm/cpufeatures.h ../../arch/x86/include/asm/cpufeatures.h >/dev/null) \ || echo "Warning: tools/arch/x86/include/asm/cpufeatures.h differs from kernel" >&2 )) || true @(test -f ../../arch/x86/lib/memcpy_64.S && ( \ - (diff -B ../arch/x86/lib/memcpy_64.S ../../arch/x86/lib/memcpy_64.S >/dev/null) \ + (diff -B -I "^EXPORT_SYMBOL" -I "^#include <asm/export.h>" ../arch/x86/lib/memcpy_64.S ../../arch/x86/lib/memcpy_64.S >/dev/null) \ || echo "Warning: tools/arch/x86/lib/memcpy_64.S differs from kernel" >&2 )) || true @(test -f ../../arch/x86/lib/memset_64.S && ( \ - (diff -B ../arch/x86/lib/memset_64.S ../../arch/x86/lib/memset_64.S >/dev/null) \ + (diff -B -I "^EXPORT_SYMBOL" -I "^#include <asm/export.h>" ../arch/x86/lib/memset_64.S ../../arch/x86/lib/memset_64.S >/dev/null) \ || echo "Warning: tools/arch/x86/lib/memset_64.S differs from kernel" >&2 )) || true @(test -f ../../arch/arm/include/uapi/asm/perf_regs.h && ( \ (diff -B ../arch/arm/include/uapi/asm/perf_regs.h ../../arch/arm/include/uapi/asm/perf_regs.h >/dev/null) \ @@ -470,7 +512,7 @@ $(OUTPUT)perf: $(PERFLIBS) $(PERF_IN) $(PMU_EVENTS_IN) $(LIBTRACEEVENT_DYNAMIC_L $(QUIET_LINK)$(CC) $(CFLAGS) $(LDFLAGS) $(LIBTRACEEVENT_DYNAMIC_LIST_LDFLAGS) \ $(PERF_IN) $(PMU_EVENTS_IN) $(LIBS) -o $@ -$(GTK_IN): fixdep FORCE +$(GTK_IN): FORCE $(Q)$(MAKE) $(build)=gtk $(OUTPUT)libperf-gtk.so: $(GTK_IN) $(PERFLIBS) @@ -484,6 +526,10 @@ $(OUTPUT)common-cmds.h: $(wildcard Documentation/perf-*.txt) $(SCRIPTS) : % : %.sh $(QUIET_GEN)$(INSTALL) '$@.sh' '$(OUTPUT)$@' +$(OUTPUT)PERF-VERSION-FILE: ../../.git/HEAD + $(Q)$(SHELL_PATH) util/PERF-VERSION-GEN $(OUTPUT) + $(Q)touch $(OUTPUT)PERF-VERSION-FILE + # These can record PERF_VERSION perf.spec $(SCRIPTS) \ : $(OUTPUT)PERF-VERSION-FILE @@ -515,7 +561,7 @@ endif __build-dir = $(subst $(OUTPUT),,$(dir $@)) build-dir = $(if $(__build-dir),$(__build-dir),.) -prepare: $(OUTPUT)PERF-VERSION-FILE $(OUTPUT)common-cmds.h fixdep archheaders +prepare: $(OUTPUT)PERF-VERSION-FILE $(OUTPUT)common-cmds.h archheaders $(OUTPUT)%.o: %.c prepare FORCE $(Q)$(MAKE) -f $(srctree)/tools/build/Makefile.build dir=$(build-dir) $@ @@ -551,11 +597,21 @@ $(OUTPUT)perf-read-vdsox32: perf-read-vdso.c util/find-vdso-map.c $(QUIET_CC)$(CC) -mx32 $(filter -static,$(LDFLAGS)) -Wall -Werror -o $@ perf-read-vdso.c endif +ifndef NO_JVMTI +LIBJVMTI_IN := $(OUTPUT)jvmti/jvmti-in.o + +$(LIBJVMTI_IN): FORCE + $(Q)$(MAKE) -f $(srctree)/tools/build/Makefile.build dir=jvmti obj=jvmti + +$(OUTPUT)$(LIBJVMTI): $(LIBJVMTI_IN) + $(QUIET_LINK)$(CC) -shared -Wl,-soname -Wl,$(LIBJVMTI) -o $@ $< -lelf -lrt +endif + $(patsubst perf-%,%.o,$(PROGRAMS)): $(wildcard */*.h) LIBPERF_IN := $(OUTPUT)libperf-in.o -$(LIBPERF_IN): prepare fixdep FORCE +$(LIBPERF_IN): prepare FORCE $(Q)$(MAKE) $(build)=libperf $(LIB_FILE): $(LIBPERF_IN) @@ -563,10 +619,10 @@ $(LIB_FILE): $(LIBPERF_IN) LIBTRACEEVENT_FLAGS += plugin_dir=$(plugindir_SQ) -$(LIBTRACEEVENT): fixdep FORCE +$(LIBTRACEEVENT): FORCE $(Q)$(MAKE) -C $(TRACE_EVENT_DIR) $(LIBTRACEEVENT_FLAGS) O=$(OUTPUT) $(OUTPUT)libtraceevent.a -libtraceevent_plugins: fixdep FORCE +libtraceevent_plugins: FORCE $(Q)$(MAKE) -C $(TRACE_EVENT_DIR) $(LIBTRACEEVENT_FLAGS) O=$(OUTPUT) plugins $(LIBTRACEEVENT_DYNAMIC_LIST): libtraceevent_plugins @@ -579,21 +635,21 @@ $(LIBTRACEEVENT)-clean: install-traceevent-plugins: libtraceevent_plugins $(Q)$(MAKE) -C $(TRACE_EVENT_DIR) $(LIBTRACEEVENT_FLAGS) O=$(OUTPUT) install_plugins -$(LIBAPI): fixdep FORCE +$(LIBAPI): FORCE $(Q)$(MAKE) -C $(LIB_DIR) O=$(OUTPUT) $(OUTPUT)libapi.a $(LIBAPI)-clean: $(call QUIET_CLEAN, libapi) $(Q)$(MAKE) -C $(LIB_DIR) O=$(OUTPUT) clean >/dev/null -$(LIBBPF): fixdep FORCE +$(LIBBPF): FORCE $(Q)$(MAKE) -C $(BPF_DIR) O=$(OUTPUT) $(OUTPUT)libbpf.a FEATURES_DUMP=$(FEATURE_DUMP_EXPORT) $(LIBBPF)-clean: $(call QUIET_CLEAN, libbpf) $(Q)$(MAKE) -C $(BPF_DIR) O=$(OUTPUT) clean >/dev/null -$(LIBSUBCMD): fixdep FORCE +$(LIBSUBCMD): FORCE $(Q)$(MAKE) -C $(SUBCMD_DIR) O=$(OUTPUT) $(OUTPUT)libsubcmd.a $(LIBSUBCMD)-clean: @@ -673,7 +729,14 @@ check: $(OUTPUT)common-cmds.h ### Installation rules +ifndef NO_GTK2 +install-gtk: $(OUTPUT)libperf-gtk.so + $(call QUIET_INSTALL, 'GTK UI') \ + $(INSTALL) -d -m 755 '$(DESTDIR_SQ)$(libdir_SQ)'; \ + $(INSTALL) $(OUTPUT)libperf-gtk.so '$(DESTDIR_SQ)$(libdir_SQ)' +else install-gtk: +endif install-tools: all install-gtk $(call QUIET_INSTALL, binaries) \ @@ -688,6 +751,10 @@ ifndef NO_PERF_READ_VDSOX32 $(call QUIET_INSTALL, perf-read-vdsox32) \ $(INSTALL) $(OUTPUT)perf-read-vdsox32 '$(DESTDIR_SQ)$(bindir_SQ)'; endif +ifndef NO_JVMTI + $(call QUIET_INSTALL, $(LIBJVMTI)) \ + $(INSTALL) $(OUTPUT)$(LIBJVMTI) '$(DESTDIR_SQ)$(libdir_SQ)'; +endif $(call QUIET_INSTALL, libexec) \ $(INSTALL) -d -m 755 '$(DESTDIR_SQ)$(perfexec_instdir_SQ)' $(call QUIET_INSTALL, perf-archive) \ @@ -754,7 +821,7 @@ clean:: $(LIBTRACEEVENT)-clean $(LIBAPI)-clean $(LIBBPF)-clean $(LIBSUBCMD)-clea $(call QUIET_CLEAN, core-objs) $(RM) $(LIB_FILE) $(OUTPUT)perf-archive $(OUTPUT)perf-with-kcore $(LANG_BINDINGS) $(Q)find $(if $(OUTPUT),$(OUTPUT),.) -name '*.o' -delete -o -name '\.*.cmd' -delete -o -name '\.*.d' -delete $(Q)$(RM) $(OUTPUT).config-detected - $(call QUIET_CLEAN, core-progs) $(RM) $(ALL_PROGRAMS) perf perf-read-vdso32 perf-read-vdsox32 $(OUTPUT)pmu-events/jevents + $(call QUIET_CLEAN, core-progs) $(RM) $(ALL_PROGRAMS) perf perf-read-vdso32 perf-read-vdsox32 $(OUTPUT)pmu-events/jevents $(OUTPUT)$(LIBJVMTI).so $(call QUIET_CLEAN, core-gen) $(RM) *.spec *.pyc *.pyo */*.pyc */*.pyo $(OUTPUT)common-cmds.h TAGS tags cscope* $(OUTPUT)PERF-VERSION-FILE $(OUTPUT)FEATURE-DUMP $(OUTPUT)util/*-bison* $(OUTPUT)util/*-flex* \ $(OUTPUT)util/intel-pt-decoder/inat-tables.c $(OUTPUT)fixdep \ $(OUTPUT)tests/llvm-src-{base,kbuild,prologue,relocation}.c \ @@ -790,3 +857,4 @@ FORCE: .PHONY: $(GIT-HEAD-PHONY) TAGS tags cscope FORCE prepare .PHONY: libtraceevent_plugins archheaders +endif # force_fixdep diff --git a/tools/perf/arch/arm/annotate/instructions.c b/tools/perf/arch/arm/annotate/instructions.c new file mode 100644 index 000000000000..1ce0872b1726 --- /dev/null +++ b/tools/perf/arch/arm/annotate/instructions.c @@ -0,0 +1,59 @@ +#include <sys/types.h> +#include <regex.h> + +struct arm_annotate { + regex_t call_insn, + jump_insn; +}; + +static struct ins_ops *arm__associate_instruction_ops(struct arch *arch, const char *name) +{ + struct arm_annotate *arm = arch->priv; + struct ins_ops *ops; + regmatch_t match[2]; + + if (!regexec(&arm->call_insn, name, 2, match, 0)) + ops = &call_ops; + else if (!regexec(&arm->jump_insn, name, 2, match, 0)) + ops = &jump_ops; + else + return NULL; + + arch__associate_ins_ops(arch, name, ops); + return ops; +} + +static int arm__annotate_init(struct arch *arch) +{ + struct arm_annotate *arm; + int err; + + if (arch->initialized) + return 0; + + arm = zalloc(sizeof(*arm)); + if (!arm) + return -1; + +#define ARM_CONDS "(cc|cs|eq|ge|gt|hi|le|ls|lt|mi|ne|pl|vc|vs)" + err = regcomp(&arm->call_insn, "^blx?" ARM_CONDS "?$", REG_EXTENDED); + if (err) + goto out_free_arm; + err = regcomp(&arm->jump_insn, "^bx?" ARM_CONDS "?$", REG_EXTENDED); + if (err) + goto out_free_call; +#undef ARM_CONDS + + arch->initialized = true; + arch->priv = arm; + arch->associate_instruction_ops = arm__associate_instruction_ops; + arch->objdump.comment_char = ';'; + arch->objdump.skip_functions_char = '+'; + return 0; + +out_free_call: + regfree(&arm->call_insn); +out_free_arm: + free(arm); + return -1; +} diff --git a/tools/perf/arch/arm/util/cs-etm.c b/tools/perf/arch/arm/util/cs-etm.c index 47d584da5819..dfea6b635525 100644 --- a/tools/perf/arch/arm/util/cs-etm.c +++ b/tools/perf/arch/arm/util/cs-etm.c @@ -575,8 +575,6 @@ static FILE *cs_device__open_file(const char *name) snprintf(path, PATH_MAX, "%s" CS_BUS_DEVICE_PATH "%s", sysfs, name); - printf("path: %s\n", path); - if (stat(path, &st) < 0) return NULL; diff --git a/tools/perf/arch/arm64/annotate/instructions.c b/tools/perf/arch/arm64/annotate/instructions.c new file mode 100644 index 000000000000..44eafd6f2d50 --- /dev/null +++ b/tools/perf/arch/arm64/annotate/instructions.c @@ -0,0 +1,62 @@ +#include <sys/types.h> +#include <regex.h> + +struct arm64_annotate { + regex_t call_insn, + jump_insn; +}; + +static struct ins_ops *arm64__associate_instruction_ops(struct arch *arch, const char *name) +{ + struct arm64_annotate *arm = arch->priv; + struct ins_ops *ops; + regmatch_t match[2]; + + if (!regexec(&arm->jump_insn, name, 2, match, 0)) + ops = &jump_ops; + else if (!regexec(&arm->call_insn, name, 2, match, 0)) + ops = &call_ops; + else if (!strcmp(name, "ret")) + ops = &ret_ops; + else + return NULL; + + arch__associate_ins_ops(arch, name, ops); + return ops; +} + +static int arm64__annotate_init(struct arch *arch) +{ + struct arm64_annotate *arm; + int err; + + if (arch->initialized) + return 0; + + arm = zalloc(sizeof(*arm)); + if (!arm) + return -1; + + /* bl, blr */ + err = regcomp(&arm->call_insn, "^blr?$", REG_EXTENDED); + if (err) + goto out_free_arm; + /* b, b.cond, br, cbz/cbnz, tbz/tbnz */ + err = regcomp(&arm->jump_insn, "^[ct]?br?\\.?(cc|cs|eq|ge|gt|hi|le|ls|lt|mi|ne|pl)?n?z?$", + REG_EXTENDED); + if (err) + goto out_free_call; + + arch->initialized = true; + arch->priv = arm; + arch->associate_instruction_ops = arm64__associate_instruction_ops; + arch->objdump.comment_char = ';'; + arch->objdump.skip_functions_char = '+'; + return 0; + +out_free_call: + regfree(&arm->call_insn); +out_free_arm: + free(arm); + return -1; +} diff --git a/tools/perf/arch/powerpc/annotate/instructions.c b/tools/perf/arch/powerpc/annotate/instructions.c new file mode 100644 index 000000000000..3c4004db81b9 --- /dev/null +++ b/tools/perf/arch/powerpc/annotate/instructions.c @@ -0,0 +1,58 @@ +static struct ins_ops *powerpc__associate_instruction_ops(struct arch *arch, const char *name) +{ + int i; + struct ins_ops *ops; + + /* + * - Interested only if instruction starts with 'b'. + * - Few start with 'b', but aren't branch instructions. + */ + if (name[0] != 'b' || + !strncmp(name, "bcd", 3) || + !strncmp(name, "brinc", 5) || + !strncmp(name, "bper", 4)) + return NULL; + + ops = &jump_ops; + + i = strlen(name) - 1; + if (i < 0) + return NULL; + + /* ignore optional hints at the end of the instructions */ + if (name[i] == '+' || name[i] == '-') + i--; + + if (name[i] == 'l' || (name[i] == 'a' && name[i-1] == 'l')) { + /* + * if the instruction ends up with 'l' or 'la', then + * those are considered 'calls' since they update LR. + * ... except for 'bnl' which is branch if not less than + * and the absolute form of the same. + */ + if (strcmp(name, "bnl") && strcmp(name, "bnl+") && + strcmp(name, "bnl-") && strcmp(name, "bnla") && + strcmp(name, "bnla+") && strcmp(name, "bnla-")) + ops = &call_ops; + } + if (name[i] == 'r' && name[i-1] == 'l') + /* + * instructions ending with 'lr' are considered to be + * return instructions + */ + ops = &ret_ops; + + arch__associate_ins_ops(arch, name, ops); + return ops; +} + +static int powerpc__annotate_init(struct arch *arch) +{ + if (!arch->initialized) { + arch->initialized = true; + arch->associate_instruction_ops = powerpc__associate_instruction_ops; + arch->objdump.comment_char = '#'; + } + + return 0; +} diff --git a/tools/perf/arch/x86/annotate/instructions.c b/tools/perf/arch/x86/annotate/instructions.c new file mode 100644 index 000000000000..c1625f256df3 --- /dev/null +++ b/tools/perf/arch/x86/annotate/instructions.c @@ -0,0 +1,78 @@ +static struct ins x86__instructions[] = { + { .name = "add", .ops = &mov_ops, }, + { .name = "addl", .ops = &mov_ops, }, + { .name = "addq", .ops = &mov_ops, }, + { .name = "addw", .ops = &mov_ops, }, + { .name = "and", .ops = &mov_ops, }, + { .name = "bts", .ops = &mov_ops, }, + { .name = "call", .ops = &call_ops, }, + { .name = "callq", .ops = &call_ops, }, + { .name = "cmp", .ops = &mov_ops, }, + { .name = "cmpb", .ops = &mov_ops, }, + { .name = "cmpl", .ops = &mov_ops, }, + { .name = "cmpq", .ops = &mov_ops, }, + { .name = "cmpw", .ops = &mov_ops, }, + { .name = "cmpxch", .ops = &mov_ops, }, + { .name = "dec", .ops = &dec_ops, }, + { .name = "decl", .ops = &dec_ops, }, + { .name = "imul", .ops = &mov_ops, }, + { .name = "inc", .ops = &dec_ops, }, + { .name = "incl", .ops = &dec_ops, }, + { .name = "ja", .ops = &jump_ops, }, + { .name = "jae", .ops = &jump_ops, }, + { .name = "jb", .ops = &jump_ops, }, + { .name = "jbe", .ops = &jump_ops, }, + { .name = "jc", .ops = &jump_ops, }, + { .name = "jcxz", .ops = &jump_ops, }, + { .name = "je", .ops = &jump_ops, }, + { .name = "jecxz", .ops = &jump_ops, }, + { .name = "jg", .ops = &jump_ops, }, + { .name = "jge", .ops = &jump_ops, }, + { .name = "jl", .ops = &jump_ops, }, + { .name = "jle", .ops = &jump_ops, }, + { .name = "jmp", .ops = &jump_ops, }, + { .name = "jmpq", .ops = &jump_ops, }, + { .name = "jna", .ops = &jump_ops, }, + { .name = "jnae", .ops = &jump_ops, }, + { .name = "jnb", .ops = &jump_ops, }, + { .name = "jnbe", .ops = &jump_ops, }, + { .name = "jnc", .ops = &jump_ops, }, + { .name = "jne", .ops = &jump_ops, }, + { .name = "jng", .ops = &jump_ops, }, + { .name = "jnge", .ops = &jump_ops, }, + { .name = "jnl", .ops = &jump_ops, }, + { .name = "jnle", .ops = &jump_ops, }, + { .name = "jno", .ops = &jump_ops, }, + { .name = "jnp", .ops = &jump_ops, }, + { .name = "jns", .ops = &jump_ops, }, + { .name = "jnz", .ops = &jump_ops, }, + { .name = "jo", .ops = &jump_ops, }, + { .name = "jp", .ops = &jump_ops, }, + { .name = "jpe", .ops = &jump_ops, }, + { .name = "jpo", .ops = &jump_ops, }, + { .name = "jrcxz", .ops = &jump_ops, }, + { .name = "js", .ops = &jump_ops, }, + { .name = "jz", .ops = &jump_ops, }, + { .name = "lea", .ops = &mov_ops, }, + { .name = "lock", .ops = &lock_ops, }, + { .name = "mov", .ops = &mov_ops, }, + { .name = "movb", .ops = &mov_ops, }, + { .name = "movdqa", .ops = &mov_ops, }, + { .name = "movl", .ops = &mov_ops, }, + { .name = "movq", .ops = &mov_ops, }, + { .name = "movslq", .ops = &mov_ops, }, + { .name = "movzbl", .ops = &mov_ops, }, + { .name = "movzwl", .ops = &mov_ops, }, + { .name = "nop", .ops = &nop_ops, }, + { .name = "nopl", .ops = &nop_ops, }, + { .name = "nopw", .ops = &nop_ops, }, + { .name = "or", .ops = &mov_ops, }, + { .name = "orl", .ops = &mov_ops, }, + { .name = "test", .ops = &mov_ops, }, + { .name = "testb", .ops = &mov_ops, }, + { .name = "testl", .ops = &mov_ops, }, + { .name = "xadd", .ops = &mov_ops, }, + { .name = "xbeginl", .ops = &jump_ops, }, + { .name = "xbeginq", .ops = &jump_ops, }, + { .name = "retq", .ops = &ret_ops, }, +}; diff --git a/tools/perf/arch/x86/entry/syscalls/syscall_64.tbl b/tools/perf/arch/x86/entry/syscalls/syscall_64.tbl index 555263e385c9..e93ef0b38db8 100644 --- a/tools/perf/arch/x86/entry/syscalls/syscall_64.tbl +++ b/tools/perf/arch/x86/entry/syscalls/syscall_64.tbl @@ -335,6 +335,9 @@ 326 common copy_file_range sys_copy_file_range 327 64 preadv2 sys_preadv2 328 64 pwritev2 sys_pwritev2 +329 common pkey_mprotect sys_pkey_mprotect +330 common pkey_alloc sys_pkey_alloc +331 common pkey_free sys_pkey_free # # x32-specific system call numbers start at 512 to avoid cache impact @@ -374,5 +377,5 @@ 543 x32 io_setup compat_sys_io_setup 544 x32 io_submit compat_sys_io_submit 545 x32 execveat compat_sys_execveat/ptregs -534 x32 preadv2 compat_sys_preadv2 -535 x32 pwritev2 compat_sys_pwritev2 +546 x32 preadv2 compat_sys_preadv64v2 +547 x32 pwritev2 compat_sys_pwritev64v2 diff --git a/tools/perf/arch/x86/tests/arch-tests.c b/tools/perf/arch/x86/tests/arch-tests.c index 2218cb64f840..99d66191e56c 100644 --- a/tools/perf/arch/x86/tests/arch-tests.c +++ b/tools/perf/arch/x86/tests/arch-tests.c @@ -4,27 +4,27 @@ struct test arch_tests[] = { { - .desc = "x86 rdpmc test", + .desc = "x86 rdpmc", .func = test__rdpmc, }, { - .desc = "Test converting perf time to TSC", + .desc = "Convert perf time to TSC", .func = test__perf_time_to_tsc, }, #ifdef HAVE_DWARF_UNWIND_SUPPORT { - .desc = "Test dwarf unwind", + .desc = "DWARF unwind", .func = test__dwarf_unwind, }, #endif #ifdef HAVE_AUXTRACE_SUPPORT { - .desc = "Test x86 instruction decoder - new instructions", + .desc = "x86 instruction decoder - new instructions", .func = test__insn_x86, }, #endif { - .desc = "Test intel cqm nmi context read", + .desc = "Intel cqm nmi context read", .func = test__intel_cqm_count_nmi_context, }, { diff --git a/tools/perf/bench/futex-hash.c b/tools/perf/bench/futex-hash.c index 8024cd5febd2..bfbb6b5f609c 100644 --- a/tools/perf/bench/futex-hash.c +++ b/tools/perf/bench/futex-hash.c @@ -63,8 +63,9 @@ static const char * const bench_futex_hash_usage[] = { static void *workerfn(void *arg) { int ret; - unsigned int i; struct worker *w = (struct worker *) arg; + unsigned int i; + unsigned long ops = w->ops; /* avoid cacheline bouncing */ pthread_mutex_lock(&thread_lock); threads_starting--; @@ -74,7 +75,7 @@ static void *workerfn(void *arg) pthread_mutex_unlock(&thread_lock); do { - for (i = 0; i < nfutexes; i++, w->ops++) { + for (i = 0; i < nfutexes; i++, ops++) { /* * We want the futex calls to fail in order to stress * the hashing of uaddr and not measure other steps, @@ -88,6 +89,7 @@ static void *workerfn(void *arg) } } while (!done); + w->ops = ops; return NULL; } @@ -128,6 +130,8 @@ int bench_futex_hash(int argc, const char **argv, } ncpus = sysconf(_SC_NPROCESSORS_ONLN); + nsecs = futexbench_sanitize_numeric(nsecs); + nfutexes = futexbench_sanitize_numeric(nfutexes); sigfillset(&act.sa_mask); act.sa_sigaction = toggle_done; @@ -135,6 +139,8 @@ int bench_futex_hash(int argc, const char **argv, if (!nthreads) /* default to the number of CPUs */ nthreads = ncpus; + else + nthreads = futexbench_sanitize_numeric(nthreads); worker = calloc(nthreads, sizeof(*worker)); if (!worker) diff --git a/tools/perf/bench/futex-lock-pi.c b/tools/perf/bench/futex-lock-pi.c index 936d89d30483..465012b320ee 100644 --- a/tools/perf/bench/futex-lock-pi.c +++ b/tools/perf/bench/futex-lock-pi.c @@ -75,6 +75,7 @@ static void toggle_done(int sig __maybe_unused, static void *workerfn(void *arg) { struct worker *w = (struct worker *) arg; + unsigned long ops = w->ops; pthread_mutex_lock(&thread_lock); threads_starting--; @@ -103,9 +104,10 @@ static void *workerfn(void *arg) if (ret && !silent) warn("thread %d: Could not unlock pi-lock for %p (%d)", w->tid, w->futex, ret); - w->ops++; /* account for thread's share of work */ + ops++; /* account for thread's share of work */ } while (!done); + w->ops = ops; return NULL; } @@ -150,6 +152,7 @@ int bench_futex_lock_pi(int argc, const char **argv, goto err; ncpus = sysconf(_SC_NPROCESSORS_ONLN); + nsecs = futexbench_sanitize_numeric(nsecs); sigfillset(&act.sa_mask); act.sa_sigaction = toggle_done; @@ -157,6 +160,8 @@ int bench_futex_lock_pi(int argc, const char **argv, if (!nthreads) nthreads = ncpus; + else + nthreads = futexbench_sanitize_numeric(nthreads); worker = calloc(nthreads, sizeof(*worker)); if (!worker) diff --git a/tools/perf/bench/futex-requeue.c b/tools/perf/bench/futex-requeue.c index 2b9705a8734c..fd4ee95b689a 100644 --- a/tools/perf/bench/futex-requeue.c +++ b/tools/perf/bench/futex-requeue.c @@ -128,6 +128,8 @@ int bench_futex_requeue(int argc, const char **argv, if (!nthreads) nthreads = ncpus; + else + nthreads = futexbench_sanitize_numeric(nthreads); worker = calloc(nthreads, sizeof(*worker)); if (!worker) diff --git a/tools/perf/bench/futex-wake-parallel.c b/tools/perf/bench/futex-wake-parallel.c index 2c8fa67ad537..beaa6c142477 100644 --- a/tools/perf/bench/futex-wake-parallel.c +++ b/tools/perf/bench/futex-wake-parallel.c @@ -217,8 +217,12 @@ int bench_futex_wake_parallel(int argc, const char **argv, sigaction(SIGINT, &act, NULL); ncpus = sysconf(_SC_NPROCESSORS_ONLN); + nwaking_threads = futexbench_sanitize_numeric(nwaking_threads); + if (!nblocked_threads) nblocked_threads = ncpus; + else + nblocked_threads = futexbench_sanitize_numeric(nblocked_threads); /* some sanity checks */ if (nwaking_threads > nblocked_threads || !nwaking_threads) diff --git a/tools/perf/bench/futex-wake.c b/tools/perf/bench/futex-wake.c index e246b1b8388a..46efcb98b5a4 100644 --- a/tools/perf/bench/futex-wake.c +++ b/tools/perf/bench/futex-wake.c @@ -129,6 +129,7 @@ int bench_futex_wake(int argc, const char **argv, } ncpus = sysconf(_SC_NPROCESSORS_ONLN); + nwakes = futexbench_sanitize_numeric(nwakes); sigfillset(&act.sa_mask); act.sa_sigaction = toggle_done; @@ -136,6 +137,8 @@ int bench_futex_wake(int argc, const char **argv, if (!nthreads) nthreads = ncpus; + else + nthreads = futexbench_sanitize_numeric(nthreads); worker = calloc(nthreads, sizeof(*worker)); if (!worker) diff --git a/tools/perf/bench/futex.h b/tools/perf/bench/futex.h index b2e06d1190d0..ba7c735c0c62 100644 --- a/tools/perf/bench/futex.h +++ b/tools/perf/bench/futex.h @@ -7,6 +7,7 @@ #ifndef _FUTEX_H #define _FUTEX_H +#include <stdlib.h> #include <unistd.h> #include <sys/syscall.h> #include <sys/types.h> @@ -99,4 +100,7 @@ static inline int pthread_attr_setaffinity_np(pthread_attr_t *attr, } #endif +/* User input sanitation */ +#define futexbench_sanitize_numeric(__n) abs((__n)) + #endif /* _FUTEX_H */ diff --git a/tools/perf/bench/mem-functions.c b/tools/perf/bench/mem-functions.c index c684910e5a48..52504a83b5a1 100644 --- a/tools/perf/bench/mem-functions.c +++ b/tools/perf/bench/mem-functions.c @@ -106,9 +106,10 @@ static double timeval2double(struct timeval *ts) struct bench_mem_info { const struct function *functions; - u64 (*do_cycles)(const struct function *r, size_t size); - double (*do_gettimeofday)(const struct function *r, size_t size); + u64 (*do_cycles)(const struct function *r, size_t size, void *src, void *dst); + double (*do_gettimeofday)(const struct function *r, size_t size, void *src, void *dst); const char *const *usage; + bool alloc_src; }; static void __bench_mem_function(struct bench_mem_info *info, int r_idx, size_t size, double size_total) @@ -116,16 +117,26 @@ static void __bench_mem_function(struct bench_mem_info *info, int r_idx, size_t const struct function *r = &info->functions[r_idx]; double result_bps = 0.0; u64 result_cycles = 0; + void *src = NULL, *dst = zalloc(size); printf("# function '%s' (%s)\n", r->name, r->desc); + if (dst == NULL) + goto out_alloc_failed; + + if (info->alloc_src) { + src = zalloc(size); + if (src == NULL) + goto out_alloc_failed; + } + if (bench_format == BENCH_FORMAT_DEFAULT) printf("# Copying %s bytes ...\n\n", size_str); if (use_cycles) { - result_cycles = info->do_cycles(r, size); + result_cycles = info->do_cycles(r, size, src, dst); } else { - result_bps = info->do_gettimeofday(r, size); + result_bps = info->do_gettimeofday(r, size, src, dst); } switch (bench_format) { @@ -149,6 +160,14 @@ static void __bench_mem_function(struct bench_mem_info *info, int r_idx, size_t BUG_ON(1); break; } + +out_free: + free(src); + free(dst); + return; +out_alloc_failed: + printf("# Memory allocation failed - maybe size (%s) is too large?\n", size_str); + goto out_free; } static int bench_mem_common(int argc, const char **argv, struct bench_mem_info *info) @@ -201,28 +220,14 @@ static int bench_mem_common(int argc, const char **argv, struct bench_mem_info * return 0; } -static void memcpy_alloc_mem(void **dst, void **src, size_t size) -{ - *dst = zalloc(size); - if (!*dst) - die("memory allocation failed - maybe size is too large?\n"); - - *src = zalloc(size); - if (!*src) - die("memory allocation failed - maybe size is too large?\n"); - - /* Make sure to always prefault zero pages even if MMAP_THRESH is crossed: */ - memset(*src, 0, size); -} - -static u64 do_memcpy_cycles(const struct function *r, size_t size) +static u64 do_memcpy_cycles(const struct function *r, size_t size, void *src, void *dst) { u64 cycle_start = 0ULL, cycle_end = 0ULL; - void *src = NULL, *dst = NULL; memcpy_t fn = r->fn.memcpy; int i; - memcpy_alloc_mem(&dst, &src, size); + /* Make sure to always prefault zero pages even if MMAP_THRESH is crossed: */ + memset(src, 0, size); /* * We prefault the freshly allocated memory range here, @@ -235,20 +240,15 @@ static u64 do_memcpy_cycles(const struct function *r, size_t size) fn(dst, src, size); cycle_end = get_cycles(); - free(src); - free(dst); return cycle_end - cycle_start; } -static double do_memcpy_gettimeofday(const struct function *r, size_t size) +static double do_memcpy_gettimeofday(const struct function *r, size_t size, void *src, void *dst) { struct timeval tv_start, tv_end, tv_diff; memcpy_t fn = r->fn.memcpy; - void *src = NULL, *dst = NULL; int i; - memcpy_alloc_mem(&dst, &src, size); - /* * We prefault the freshly allocated memory range here, * to not measure page fault overhead: @@ -262,9 +262,6 @@ static double do_memcpy_gettimeofday(const struct function *r, size_t size) timersub(&tv_end, &tv_start, &tv_diff); - free(src); - free(dst); - return (double)(((double)size * nr_loops) / timeval2double(&tv_diff)); } @@ -294,27 +291,18 @@ int bench_mem_memcpy(int argc, const char **argv, const char *prefix __maybe_unu .do_cycles = do_memcpy_cycles, .do_gettimeofday = do_memcpy_gettimeofday, .usage = bench_mem_memcpy_usage, + .alloc_src = true, }; return bench_mem_common(argc, argv, &info); } -static void memset_alloc_mem(void **dst, size_t size) -{ - *dst = zalloc(size); - if (!*dst) - die("memory allocation failed - maybe size is too large?\n"); -} - -static u64 do_memset_cycles(const struct function *r, size_t size) +static u64 do_memset_cycles(const struct function *r, size_t size, void *src __maybe_unused, void *dst) { u64 cycle_start = 0ULL, cycle_end = 0ULL; memset_t fn = r->fn.memset; - void *dst = NULL; int i; - memset_alloc_mem(&dst, size); - /* * We prefault the freshly allocated memory range here, * to not measure page fault overhead: @@ -326,19 +314,15 @@ static u64 do_memset_cycles(const struct function *r, size_t size) fn(dst, i, size); cycle_end = get_cycles(); - free(dst); return cycle_end - cycle_start; } -static double do_memset_gettimeofday(const struct function *r, size_t size) +static double do_memset_gettimeofday(const struct function *r, size_t size, void *src __maybe_unused, void *dst) { struct timeval tv_start, tv_end, tv_diff; memset_t fn = r->fn.memset; - void *dst = NULL; int i; - memset_alloc_mem(&dst, size); - /* * We prefault the freshly allocated memory range here, * to not measure page fault overhead: @@ -352,7 +336,6 @@ static double do_memset_gettimeofday(const struct function *r, size_t size) timersub(&tv_end, &tv_start, &tv_diff); - free(dst); return (double)(((double)size * nr_loops) / timeval2double(&tv_diff)); } diff --git a/tools/perf/builtin-c2c.c b/tools/perf/builtin-c2c.c new file mode 100644 index 000000000000..4b419631753d --- /dev/null +++ b/tools/perf/builtin-c2c.c @@ -0,0 +1,2780 @@ +/* + * This is rewrite of original c2c tool introduced in here: + * http://lwn.net/Articles/588866/ + * + * The original tool was changed to fit in current perf state. + * + * Original authors: + * Don Zickus <dzickus@redhat.com> + * Dick Fowles <fowles@inreach.com> + * Joe Mario <jmario@redhat.com> + */ +#include <linux/compiler.h> +#include <linux/kernel.h> +#include <linux/stringify.h> +#include <asm/bug.h> +#include "util.h" +#include "debug.h" +#include "builtin.h" +#include <subcmd/parse-options.h> +#include "mem-events.h" +#include "session.h" +#include "hist.h" +#include "sort.h" +#include "tool.h" +#include "data.h" +#include "sort.h" +#include "evlist.h" +#include "evsel.h" +#include <asm/bug.h> +#include "ui/browsers/hists.h" +#include "evlist.h" + +struct c2c_hists { + struct hists hists; + struct perf_hpp_list list; + struct c2c_stats stats; +}; + +struct compute_stats { + struct stats lcl_hitm; + struct stats rmt_hitm; + struct stats load; +}; + +struct c2c_hist_entry { + struct c2c_hists *hists; + struct c2c_stats stats; + unsigned long *cpuset; + struct c2c_stats *node_stats; + unsigned int cacheline_idx; + + struct compute_stats cstats; + + /* + * must be at the end, + * because of its callchain dynamic entry + */ + struct hist_entry he; +}; + +static char const *coalesce_default = "pid,tid,iaddr"; + +struct perf_c2c { + struct perf_tool tool; + struct c2c_hists hists; + + unsigned long **nodes; + int nodes_cnt; + int cpus_cnt; + int *cpu2node; + int node_info; + + bool show_src; + bool show_all; + bool use_stdio; + bool stats_only; + bool symbol_full; + + /* HITM shared clines stats */ + struct c2c_stats hitm_stats; + int shared_clines; + + int display; + + const char *coalesce; + char *cl_sort; + char *cl_resort; + char *cl_output; +}; + +enum { + DISPLAY_LCL, + DISPLAY_RMT, + DISPLAY_TOT, + DISPLAY_MAX, +}; + +static const char *display_str[DISPLAY_MAX] = { + [DISPLAY_LCL] = "Local", + [DISPLAY_RMT] = "Remote", + [DISPLAY_TOT] = "Total", +}; + +static const struct option c2c_options[] = { + OPT_INCR('v', "verbose", &verbose, "be more verbose (show counter open errors, etc)"), + OPT_END() +}; + +static struct perf_c2c c2c; + +static void *c2c_he_zalloc(size_t size) +{ + struct c2c_hist_entry *c2c_he; + + c2c_he = zalloc(size + sizeof(*c2c_he)); + if (!c2c_he) + return NULL; + + c2c_he->cpuset = bitmap_alloc(c2c.cpus_cnt); + if (!c2c_he->cpuset) + return NULL; + + c2c_he->node_stats = zalloc(c2c.nodes_cnt * sizeof(*c2c_he->node_stats)); + if (!c2c_he->node_stats) + return NULL; + + init_stats(&c2c_he->cstats.lcl_hitm); + init_stats(&c2c_he->cstats.rmt_hitm); + init_stats(&c2c_he->cstats.load); + + return &c2c_he->he; +} + +static void c2c_he_free(void *he) +{ + struct c2c_hist_entry *c2c_he; + + c2c_he = container_of(he, struct c2c_hist_entry, he); + if (c2c_he->hists) { + hists__delete_entries(&c2c_he->hists->hists); + free(c2c_he->hists); + } + + free(c2c_he->cpuset); + free(c2c_he->node_stats); + free(c2c_he); +} + +static struct hist_entry_ops c2c_entry_ops = { + .new = c2c_he_zalloc, + .free = c2c_he_free, +}; + +static int c2c_hists__init(struct c2c_hists *hists, + const char *sort, + int nr_header_lines); + +static struct c2c_hists* +he__get_c2c_hists(struct hist_entry *he, + const char *sort, + int nr_header_lines) +{ + struct c2c_hist_entry *c2c_he; + struct c2c_hists *hists; + int ret; + + c2c_he = container_of(he, struct c2c_hist_entry, he); + if (c2c_he->hists) + return c2c_he->hists; + + hists = c2c_he->hists = zalloc(sizeof(*hists)); + if (!hists) + return NULL; + + ret = c2c_hists__init(hists, sort, nr_header_lines); + if (ret) { + free(hists); + return NULL; + } + + return hists; +} + +static void c2c_he__set_cpu(struct c2c_hist_entry *c2c_he, + struct perf_sample *sample) +{ + if (WARN_ONCE(sample->cpu == (unsigned int) -1, + "WARNING: no sample cpu value")) + return; + + set_bit(sample->cpu, c2c_he->cpuset); +} + +static void compute_stats(struct c2c_hist_entry *c2c_he, + struct c2c_stats *stats, + u64 weight) +{ + struct compute_stats *cstats = &c2c_he->cstats; + + if (stats->rmt_hitm) + update_stats(&cstats->rmt_hitm, weight); + else if (stats->lcl_hitm) + update_stats(&cstats->lcl_hitm, weight); + else if (stats->load) + update_stats(&cstats->load, weight); +} + +static int process_sample_event(struct perf_tool *tool __maybe_unused, + union perf_event *event, + struct perf_sample *sample, + struct perf_evsel *evsel __maybe_unused, + struct machine *machine) +{ + struct c2c_hists *c2c_hists = &c2c.hists; + struct c2c_hist_entry *c2c_he; + struct c2c_stats stats = { .nr_entries = 0, }; + struct hist_entry *he; + struct addr_location al; + struct mem_info *mi, *mi_dup; + int ret; + + if (machine__resolve(machine, &al, sample) < 0) { + pr_debug("problem processing %d event, skipping it.\n", + event->header.type); + return -1; + } + + ret = sample__resolve_callchain(sample, &callchain_cursor, NULL, + evsel, &al, sysctl_perf_event_max_stack); + if (ret) + goto out; + + mi = sample__resolve_mem(sample, &al); + if (mi == NULL) + return -ENOMEM; + + mi_dup = memdup(mi, sizeof(*mi)); + if (!mi_dup) + goto free_mi; + + c2c_decode_stats(&stats, mi); + + he = hists__add_entry_ops(&c2c_hists->hists, &c2c_entry_ops, + &al, NULL, NULL, mi, + sample, true); + if (he == NULL) + goto free_mi_dup; + + c2c_he = container_of(he, struct c2c_hist_entry, he); + c2c_add_stats(&c2c_he->stats, &stats); + c2c_add_stats(&c2c_hists->stats, &stats); + + c2c_he__set_cpu(c2c_he, sample); + + hists__inc_nr_samples(&c2c_hists->hists, he->filtered); + ret = hist_entry__append_callchain(he, sample); + + if (!ret) { + /* + * There's already been warning about missing + * sample's cpu value. Let's account all to + * node 0 in this case, without any further + * warning. + * + * Doing node stats only for single callchain data. + */ + int cpu = sample->cpu == (unsigned int) -1 ? 0 : sample->cpu; + int node = c2c.cpu2node[cpu]; + + mi = mi_dup; + + mi_dup = memdup(mi, sizeof(*mi)); + if (!mi_dup) + goto free_mi; + + c2c_hists = he__get_c2c_hists(he, c2c.cl_sort, 2); + if (!c2c_hists) + goto free_mi_dup; + + he = hists__add_entry_ops(&c2c_hists->hists, &c2c_entry_ops, + &al, NULL, NULL, mi, + sample, true); + if (he == NULL) + goto free_mi_dup; + + c2c_he = container_of(he, struct c2c_hist_entry, he); + c2c_add_stats(&c2c_he->stats, &stats); + c2c_add_stats(&c2c_hists->stats, &stats); + c2c_add_stats(&c2c_he->node_stats[node], &stats); + + compute_stats(c2c_he, &stats, sample->weight); + + c2c_he__set_cpu(c2c_he, sample); + + hists__inc_nr_samples(&c2c_hists->hists, he->filtered); + ret = hist_entry__append_callchain(he, sample); + } + +out: + addr_location__put(&al); + return ret; + +free_mi_dup: + free(mi_dup); +free_mi: + free(mi); + ret = -ENOMEM; + goto out; +} + +static struct perf_c2c c2c = { + .tool = { + .sample = process_sample_event, + .mmap = perf_event__process_mmap, + .mmap2 = perf_event__process_mmap2, + .comm = perf_event__process_comm, + .exit = perf_event__process_exit, + .fork = perf_event__process_fork, + .lost = perf_event__process_lost, + .ordered_events = true, + .ordering_requires_timestamps = true, + }, +}; + +static const char * const c2c_usage[] = { + "perf c2c {record|report}", + NULL +}; + +static const char * const __usage_report[] = { + "perf c2c report", + NULL +}; + +static const char * const *report_c2c_usage = __usage_report; + +#define C2C_HEADER_MAX 2 + +struct c2c_header { + struct { + const char *text; + int span; + } line[C2C_HEADER_MAX]; +}; + +struct c2c_dimension { + struct c2c_header header; + const char *name; + int width; + struct sort_entry *se; + + int64_t (*cmp)(struct perf_hpp_fmt *fmt, + struct hist_entry *, struct hist_entry *); + int (*entry)(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, + struct hist_entry *he); + int (*color)(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, + struct hist_entry *he); +}; + +struct c2c_fmt { + struct perf_hpp_fmt fmt; + struct c2c_dimension *dim; +}; + +#define SYMBOL_WIDTH 30 + +static struct c2c_dimension dim_symbol; +static struct c2c_dimension dim_srcline; + +static int symbol_width(struct hists *hists, struct sort_entry *se) +{ + int width = hists__col_len(hists, se->se_width_idx); + + if (!c2c.symbol_full) + width = MIN(width, SYMBOL_WIDTH); + + return width; +} + +static int c2c_width(struct perf_hpp_fmt *fmt, + struct perf_hpp *hpp __maybe_unused, + struct hists *hists __maybe_unused) +{ + struct c2c_fmt *c2c_fmt; + struct c2c_dimension *dim; + + c2c_fmt = container_of(fmt, struct c2c_fmt, fmt); + dim = c2c_fmt->dim; + + if (dim == &dim_symbol || dim == &dim_srcline) + return symbol_width(hists, dim->se); + + return dim->se ? hists__col_len(hists, dim->se->se_width_idx) : + c2c_fmt->dim->width; +} + +static int c2c_header(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, + struct hists *hists, int line, int *span) +{ + struct perf_hpp_list *hpp_list = hists->hpp_list; + struct c2c_fmt *c2c_fmt; + struct c2c_dimension *dim; + const char *text = NULL; + int width = c2c_width(fmt, hpp, hists); + + c2c_fmt = container_of(fmt, struct c2c_fmt, fmt); + dim = c2c_fmt->dim; + + if (dim->se) { + text = dim->header.line[line].text; + /* Use the last line from sort_entry if not defined. */ + if (!text && (line == hpp_list->nr_header_lines - 1)) + text = dim->se->se_header; + } else { + text = dim->header.line[line].text; + + if (*span) { + (*span)--; + return 0; + } else { + *span = dim->header.line[line].span; + } + } + + if (text == NULL) + text = ""; + + return scnprintf(hpp->buf, hpp->size, "%*s", width, text); +} + +#define HEX_STR(__s, __v) \ +({ \ + scnprintf(__s, sizeof(__s), "0x%" PRIx64, __v); \ + __s; \ +}) + +static int64_t +dcacheline_cmp(struct perf_hpp_fmt *fmt __maybe_unused, + struct hist_entry *left, struct hist_entry *right) +{ + return sort__dcacheline_cmp(left, right); +} + +static int dcacheline_entry(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, + struct hist_entry *he) +{ + uint64_t addr = 0; + int width = c2c_width(fmt, hpp, he->hists); + char buf[20]; + + if (he->mem_info) + addr = cl_address(he->mem_info->daddr.addr); + + return scnprintf(hpp->buf, hpp->size, "%*s", width, HEX_STR(buf, addr)); +} + +static int offset_entry(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, + struct hist_entry *he) +{ + uint64_t addr = 0; + int width = c2c_width(fmt, hpp, he->hists); + char buf[20]; + + if (he->mem_info) + addr = cl_offset(he->mem_info->daddr.al_addr); + + return scnprintf(hpp->buf, hpp->size, "%*s", width, HEX_STR(buf, addr)); +} + +static int64_t +offset_cmp(struct perf_hpp_fmt *fmt __maybe_unused, + struct hist_entry *left, struct hist_entry *right) +{ + uint64_t l = 0, r = 0; + + if (left->mem_info) + l = cl_offset(left->mem_info->daddr.addr); + if (right->mem_info) + r = cl_offset(right->mem_info->daddr.addr); + + return (int64_t)(r - l); +} + +static int +iaddr_entry(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, + struct hist_entry *he) +{ + uint64_t addr = 0; + int width = c2c_width(fmt, hpp, he->hists); + char buf[20]; + + if (he->mem_info) + addr = he->mem_info->iaddr.addr; + + return scnprintf(hpp->buf, hpp->size, "%*s", width, HEX_STR(buf, addr)); +} + +static int64_t +iaddr_cmp(struct perf_hpp_fmt *fmt __maybe_unused, + struct hist_entry *left, struct hist_entry *right) +{ + return sort__iaddr_cmp(left, right); +} + +static int +tot_hitm_entry(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, + struct hist_entry *he) +{ + struct c2c_hist_entry *c2c_he; + int width = c2c_width(fmt, hpp, he->hists); + unsigned int tot_hitm; + + c2c_he = container_of(he, struct c2c_hist_entry, he); + tot_hitm = c2c_he->stats.lcl_hitm + c2c_he->stats.rmt_hitm; + + return scnprintf(hpp->buf, hpp->size, "%*u", width, tot_hitm); +} + +static int64_t +tot_hitm_cmp(struct perf_hpp_fmt *fmt __maybe_unused, + struct hist_entry *left, struct hist_entry *right) +{ + struct c2c_hist_entry *c2c_left; + struct c2c_hist_entry *c2c_right; + unsigned int tot_hitm_left; + unsigned int tot_hitm_right; + + c2c_left = container_of(left, struct c2c_hist_entry, he); + c2c_right = container_of(right, struct c2c_hist_entry, he); + + tot_hitm_left = c2c_left->stats.lcl_hitm + c2c_left->stats.rmt_hitm; + tot_hitm_right = c2c_right->stats.lcl_hitm + c2c_right->stats.rmt_hitm; + + return tot_hitm_left - tot_hitm_right; +} + +#define STAT_FN_ENTRY(__f) \ +static int \ +__f ## _entry(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, \ + struct hist_entry *he) \ +{ \ + struct c2c_hist_entry *c2c_he; \ + int width = c2c_width(fmt, hpp, he->hists); \ + \ + c2c_he = container_of(he, struct c2c_hist_entry, he); \ + return scnprintf(hpp->buf, hpp->size, "%*u", width, \ + c2c_he->stats.__f); \ +} + +#define STAT_FN_CMP(__f) \ +static int64_t \ +__f ## _cmp(struct perf_hpp_fmt *fmt __maybe_unused, \ + struct hist_entry *left, struct hist_entry *right) \ +{ \ + struct c2c_hist_entry *c2c_left, *c2c_right; \ + \ + c2c_left = container_of(left, struct c2c_hist_entry, he); \ + c2c_right = container_of(right, struct c2c_hist_entry, he); \ + return c2c_left->stats.__f - c2c_right->stats.__f; \ +} + +#define STAT_FN(__f) \ + STAT_FN_ENTRY(__f) \ + STAT_FN_CMP(__f) + +STAT_FN(rmt_hitm) +STAT_FN(lcl_hitm) +STAT_FN(store) +STAT_FN(st_l1hit) +STAT_FN(st_l1miss) +STAT_FN(ld_fbhit) +STAT_FN(ld_l1hit) +STAT_FN(ld_l2hit) +STAT_FN(ld_llchit) +STAT_FN(rmt_hit) + +static uint64_t llc_miss(struct c2c_stats *stats) +{ + uint64_t llcmiss; + + llcmiss = stats->lcl_dram + + stats->rmt_dram + + stats->rmt_hitm + + stats->rmt_hit; + + return llcmiss; +} + +static int +ld_llcmiss_entry(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, + struct hist_entry *he) +{ + struct c2c_hist_entry *c2c_he; + int width = c2c_width(fmt, hpp, he->hists); + + c2c_he = container_of(he, struct c2c_hist_entry, he); + + return scnprintf(hpp->buf, hpp->size, "%*lu", width, + llc_miss(&c2c_he->stats)); +} + +static int64_t +ld_llcmiss_cmp(struct perf_hpp_fmt *fmt __maybe_unused, + struct hist_entry *left, struct hist_entry *right) +{ + struct c2c_hist_entry *c2c_left; + struct c2c_hist_entry *c2c_right; + + c2c_left = container_of(left, struct c2c_hist_entry, he); + c2c_right = container_of(right, struct c2c_hist_entry, he); + + return llc_miss(&c2c_left->stats) - llc_miss(&c2c_right->stats); +} + +static uint64_t total_records(struct c2c_stats *stats) +{ + uint64_t lclmiss, ldcnt, total; + + lclmiss = stats->lcl_dram + + stats->rmt_dram + + stats->rmt_hitm + + stats->rmt_hit; + + ldcnt = lclmiss + + stats->ld_fbhit + + stats->ld_l1hit + + stats->ld_l2hit + + stats->ld_llchit + + stats->lcl_hitm; + + total = ldcnt + + stats->st_l1hit + + stats->st_l1miss; + + return total; +} + +static int +tot_recs_entry(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, + struct hist_entry *he) +{ + struct c2c_hist_entry *c2c_he; + int width = c2c_width(fmt, hpp, he->hists); + uint64_t tot_recs; + + c2c_he = container_of(he, struct c2c_hist_entry, he); + tot_recs = total_records(&c2c_he->stats); + + return scnprintf(hpp->buf, hpp->size, "%*" PRIu64, width, tot_recs); +} + +static int64_t +tot_recs_cmp(struct perf_hpp_fmt *fmt __maybe_unused, + struct hist_entry *left, struct hist_entry *right) +{ + struct c2c_hist_entry *c2c_left; + struct c2c_hist_entry *c2c_right; + uint64_t tot_recs_left; + uint64_t tot_recs_right; + + c2c_left = container_of(left, struct c2c_hist_entry, he); + c2c_right = container_of(right, struct c2c_hist_entry, he); + + tot_recs_left = total_records(&c2c_left->stats); + tot_recs_right = total_records(&c2c_right->stats); + + return tot_recs_left - tot_recs_right; +} + +static uint64_t total_loads(struct c2c_stats *stats) +{ + uint64_t lclmiss, ldcnt; + + lclmiss = stats->lcl_dram + + stats->rmt_dram + + stats->rmt_hitm + + stats->rmt_hit; + + ldcnt = lclmiss + + stats->ld_fbhit + + stats->ld_l1hit + + stats->ld_l2hit + + stats->ld_llchit + + stats->lcl_hitm; + + return ldcnt; +} + +static int +tot_loads_entry(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, + struct hist_entry *he) +{ + struct c2c_hist_entry *c2c_he; + int width = c2c_width(fmt, hpp, he->hists); + uint64_t tot_recs; + + c2c_he = container_of(he, struct c2c_hist_entry, he); + tot_recs = total_loads(&c2c_he->stats); + + return scnprintf(hpp->buf, hpp->size, "%*" PRIu64, width, tot_recs); +} + +static int64_t +tot_loads_cmp(struct perf_hpp_fmt *fmt __maybe_unused, + struct hist_entry *left, struct hist_entry *right) +{ + struct c2c_hist_entry *c2c_left; + struct c2c_hist_entry *c2c_right; + uint64_t tot_recs_left; + uint64_t tot_recs_right; + + c2c_left = container_of(left, struct c2c_hist_entry, he); + c2c_right = container_of(right, struct c2c_hist_entry, he); + + tot_recs_left = total_loads(&c2c_left->stats); + tot_recs_right = total_loads(&c2c_right->stats); + + return tot_recs_left - tot_recs_right; +} + +typedef double (get_percent_cb)(struct c2c_hist_entry *); + +static int +percent_color(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, + struct hist_entry *he, get_percent_cb get_percent) +{ + struct c2c_hist_entry *c2c_he; + int width = c2c_width(fmt, hpp, he->hists); + double per; + + c2c_he = container_of(he, struct c2c_hist_entry, he); + per = get_percent(c2c_he); + +#ifdef HAVE_SLANG_SUPPORT + if (use_browser) + return __hpp__slsmg_color_printf(hpp, "%*.2f%%", width - 1, per); +#endif + return hpp_color_scnprintf(hpp, "%*.2f%%", width - 1, per); +} + +static double percent_hitm(struct c2c_hist_entry *c2c_he) +{ + struct c2c_hists *hists; + struct c2c_stats *stats; + struct c2c_stats *total; + int tot = 0, st = 0; + double p; + + hists = container_of(c2c_he->he.hists, struct c2c_hists, hists); + stats = &c2c_he->stats; + total = &hists->stats; + + switch (c2c.display) { + case DISPLAY_RMT: + st = stats->rmt_hitm; + tot = total->rmt_hitm; + break; + case DISPLAY_LCL: + st = stats->lcl_hitm; + tot = total->lcl_hitm; + break; + case DISPLAY_TOT: + st = stats->tot_hitm; + tot = total->tot_hitm; + default: + break; + } + + p = tot ? (double) st / tot : 0; + + return 100 * p; +} + +#define PERC_STR(__s, __v) \ +({ \ + scnprintf(__s, sizeof(__s), "%.2F%%", __v); \ + __s; \ +}) + +static int +percent_hitm_entry(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, + struct hist_entry *he) +{ + struct c2c_hist_entry *c2c_he; + int width = c2c_width(fmt, hpp, he->hists); + char buf[10]; + double per; + + c2c_he = container_of(he, struct c2c_hist_entry, he); + per = percent_hitm(c2c_he); + return scnprintf(hpp->buf, hpp->size, "%*s", width, PERC_STR(buf, per)); +} + +static int +percent_hitm_color(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, + struct hist_entry *he) +{ + return percent_color(fmt, hpp, he, percent_hitm); +} + +static int64_t +percent_hitm_cmp(struct perf_hpp_fmt *fmt __maybe_unused, + struct hist_entry *left, struct hist_entry *right) +{ + struct c2c_hist_entry *c2c_left; + struct c2c_hist_entry *c2c_right; + double per_left; + double per_right; + + c2c_left = container_of(left, struct c2c_hist_entry, he); + c2c_right = container_of(right, struct c2c_hist_entry, he); + + per_left = percent_hitm(c2c_left); + per_right = percent_hitm(c2c_right); + + return per_left - per_right; +} + +static struct c2c_stats *he_stats(struct hist_entry *he) +{ + struct c2c_hist_entry *c2c_he; + + c2c_he = container_of(he, struct c2c_hist_entry, he); + return &c2c_he->stats; +} + +static struct c2c_stats *total_stats(struct hist_entry *he) +{ + struct c2c_hists *hists; + + hists = container_of(he->hists, struct c2c_hists, hists); + return &hists->stats; +} + +static double percent(int st, int tot) +{ + return tot ? 100. * (double) st / (double) tot : 0; +} + +#define PERCENT(__h, __f) percent(he_stats(__h)->__f, total_stats(__h)->__f) + +#define PERCENT_FN(__f) \ +static double percent_ ## __f(struct c2c_hist_entry *c2c_he) \ +{ \ + struct c2c_hists *hists; \ + \ + hists = container_of(c2c_he->he.hists, struct c2c_hists, hists); \ + return percent(c2c_he->stats.__f, hists->stats.__f); \ +} + +PERCENT_FN(rmt_hitm) +PERCENT_FN(lcl_hitm) +PERCENT_FN(st_l1hit) +PERCENT_FN(st_l1miss) + +static int +percent_rmt_hitm_entry(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, + struct hist_entry *he) +{ + int width = c2c_width(fmt, hpp, he->hists); + double per = PERCENT(he, rmt_hitm); + char buf[10]; + + return scnprintf(hpp->buf, hpp->size, "%*s", width, PERC_STR(buf, per)); +} + +static int +percent_rmt_hitm_color(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, + struct hist_entry *he) +{ + return percent_color(fmt, hpp, he, percent_rmt_hitm); +} + +static int64_t +percent_rmt_hitm_cmp(struct perf_hpp_fmt *fmt __maybe_unused, + struct hist_entry *left, struct hist_entry *right) +{ + double per_left; + double per_right; + + per_left = PERCENT(left, lcl_hitm); + per_right = PERCENT(right, lcl_hitm); + + return per_left - per_right; +} + +static int +percent_lcl_hitm_entry(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, + struct hist_entry *he) +{ + int width = c2c_width(fmt, hpp, he->hists); + double per = PERCENT(he, lcl_hitm); + char buf[10]; + + return scnprintf(hpp->buf, hpp->size, "%*s", width, PERC_STR(buf, per)); +} + +static int +percent_lcl_hitm_color(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, + struct hist_entry *he) +{ + return percent_color(fmt, hpp, he, percent_lcl_hitm); +} + +static int64_t +percent_lcl_hitm_cmp(struct perf_hpp_fmt *fmt __maybe_unused, + struct hist_entry *left, struct hist_entry *right) +{ + double per_left; + double per_right; + + per_left = PERCENT(left, lcl_hitm); + per_right = PERCENT(right, lcl_hitm); + + return per_left - per_right; +} + +static int +percent_stores_l1hit_entry(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, + struct hist_entry *he) +{ + int width = c2c_width(fmt, hpp, he->hists); + double per = PERCENT(he, st_l1hit); + char buf[10]; + + return scnprintf(hpp->buf, hpp->size, "%*s", width, PERC_STR(buf, per)); +} + +static int +percent_stores_l1hit_color(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, + struct hist_entry *he) +{ + return percent_color(fmt, hpp, he, percent_st_l1hit); +} + +static int64_t +percent_stores_l1hit_cmp(struct perf_hpp_fmt *fmt __maybe_unused, + struct hist_entry *left, struct hist_entry *right) +{ + double per_left; + double per_right; + + per_left = PERCENT(left, st_l1hit); + per_right = PERCENT(right, st_l1hit); + + return per_left - per_right; +} + +static int +percent_stores_l1miss_entry(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, + struct hist_entry *he) +{ + int width = c2c_width(fmt, hpp, he->hists); + double per = PERCENT(he, st_l1miss); + char buf[10]; + + return scnprintf(hpp->buf, hpp->size, "%*s", width, PERC_STR(buf, per)); +} + +static int +percent_stores_l1miss_color(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, + struct hist_entry *he) +{ + return percent_color(fmt, hpp, he, percent_st_l1miss); +} + +static int64_t +percent_stores_l1miss_cmp(struct perf_hpp_fmt *fmt __maybe_unused, + struct hist_entry *left, struct hist_entry *right) +{ + double per_left; + double per_right; + + per_left = PERCENT(left, st_l1miss); + per_right = PERCENT(right, st_l1miss); + + return per_left - per_right; +} + +STAT_FN(lcl_dram) +STAT_FN(rmt_dram) + +static int +pid_entry(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, + struct hist_entry *he) +{ + int width = c2c_width(fmt, hpp, he->hists); + + return scnprintf(hpp->buf, hpp->size, "%*d", width, he->thread->pid_); +} + +static int64_t +pid_cmp(struct perf_hpp_fmt *fmt __maybe_unused, + struct hist_entry *left, struct hist_entry *right) +{ + return left->thread->pid_ - right->thread->pid_; +} + +static int64_t +empty_cmp(struct perf_hpp_fmt *fmt __maybe_unused, + struct hist_entry *left __maybe_unused, + struct hist_entry *right __maybe_unused) +{ + return 0; +} + +static int +node_entry(struct perf_hpp_fmt *fmt __maybe_unused, struct perf_hpp *hpp, + struct hist_entry *he) +{ + struct c2c_hist_entry *c2c_he; + bool first = true; + int node; + int ret = 0; + + c2c_he = container_of(he, struct c2c_hist_entry, he); + + for (node = 0; node < c2c.nodes_cnt; node++) { + DECLARE_BITMAP(set, c2c.cpus_cnt); + + bitmap_zero(set, c2c.cpus_cnt); + bitmap_and(set, c2c_he->cpuset, c2c.nodes[node], c2c.cpus_cnt); + + if (!bitmap_weight(set, c2c.cpus_cnt)) { + if (c2c.node_info == 1) { + ret = scnprintf(hpp->buf, hpp->size, "%21s", " "); + advance_hpp(hpp, ret); + } + continue; + } + + if (!first) { + ret = scnprintf(hpp->buf, hpp->size, " "); + advance_hpp(hpp, ret); + } + + switch (c2c.node_info) { + case 0: + ret = scnprintf(hpp->buf, hpp->size, "%2d", node); + advance_hpp(hpp, ret); + break; + case 1: + { + int num = bitmap_weight(c2c_he->cpuset, c2c.cpus_cnt); + struct c2c_stats *stats = &c2c_he->node_stats[node]; + + ret = scnprintf(hpp->buf, hpp->size, "%2d{%2d ", node, num); + advance_hpp(hpp, ret); + + #define DISPLAY_HITM(__h) \ + if (c2c_he->stats.__h> 0) { \ + ret = scnprintf(hpp->buf, hpp->size, "%5.1f%% ", \ + percent(stats->__h, c2c_he->stats.__h));\ + } else { \ + ret = scnprintf(hpp->buf, hpp->size, "%6s ", "n/a"); \ + } + + switch (c2c.display) { + case DISPLAY_RMT: + DISPLAY_HITM(rmt_hitm); + break; + case DISPLAY_LCL: + DISPLAY_HITM(lcl_hitm); + break; + case DISPLAY_TOT: + DISPLAY_HITM(tot_hitm); + default: + break; + } + + #undef DISPLAY_HITM + + advance_hpp(hpp, ret); + + if (c2c_he->stats.store > 0) { + ret = scnprintf(hpp->buf, hpp->size, "%5.1f%%}", + percent(stats->store, c2c_he->stats.store)); + } else { + ret = scnprintf(hpp->buf, hpp->size, "%6s}", "n/a"); + } + + advance_hpp(hpp, ret); + break; + } + case 2: + ret = scnprintf(hpp->buf, hpp->size, "%2d{", node); + advance_hpp(hpp, ret); + + ret = bitmap_scnprintf(set, c2c.cpus_cnt, hpp->buf, hpp->size); + advance_hpp(hpp, ret); + + ret = scnprintf(hpp->buf, hpp->size, "}"); + advance_hpp(hpp, ret); + break; + default: + break; + } + + first = false; + } + + return 0; +} + +static int +mean_entry(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, + struct hist_entry *he, double mean) +{ + int width = c2c_width(fmt, hpp, he->hists); + char buf[10]; + + scnprintf(buf, 10, "%6.0f", mean); + return scnprintf(hpp->buf, hpp->size, "%*s", width, buf); +} + +#define MEAN_ENTRY(__func, __val) \ +static int \ +__func(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, struct hist_entry *he) \ +{ \ + struct c2c_hist_entry *c2c_he; \ + c2c_he = container_of(he, struct c2c_hist_entry, he); \ + return mean_entry(fmt, hpp, he, avg_stats(&c2c_he->cstats.__val)); \ +} + +MEAN_ENTRY(mean_rmt_entry, rmt_hitm); +MEAN_ENTRY(mean_lcl_entry, lcl_hitm); +MEAN_ENTRY(mean_load_entry, load); + +static int +cpucnt_entry(struct perf_hpp_fmt *fmt __maybe_unused, struct perf_hpp *hpp, + struct hist_entry *he) +{ + struct c2c_hist_entry *c2c_he; + int width = c2c_width(fmt, hpp, he->hists); + char buf[10]; + + c2c_he = container_of(he, struct c2c_hist_entry, he); + + scnprintf(buf, 10, "%d", bitmap_weight(c2c_he->cpuset, c2c.cpus_cnt)); + return scnprintf(hpp->buf, hpp->size, "%*s", width, buf); +} + +static int +cl_idx_entry(struct perf_hpp_fmt *fmt __maybe_unused, struct perf_hpp *hpp, + struct hist_entry *he) +{ + struct c2c_hist_entry *c2c_he; + int width = c2c_width(fmt, hpp, he->hists); + char buf[10]; + + c2c_he = container_of(he, struct c2c_hist_entry, he); + + scnprintf(buf, 10, "%u", c2c_he->cacheline_idx); + return scnprintf(hpp->buf, hpp->size, "%*s", width, buf); +} + +static int +cl_idx_empty_entry(struct perf_hpp_fmt *fmt __maybe_unused, struct perf_hpp *hpp, + struct hist_entry *he) +{ + int width = c2c_width(fmt, hpp, he->hists); + + return scnprintf(hpp->buf, hpp->size, "%*s", width, ""); +} + +#define HEADER_LOW(__h) \ + { \ + .line[1] = { \ + .text = __h, \ + }, \ + } + +#define HEADER_BOTH(__h0, __h1) \ + { \ + .line[0] = { \ + .text = __h0, \ + }, \ + .line[1] = { \ + .text = __h1, \ + }, \ + } + +#define HEADER_SPAN(__h0, __h1, __s) \ + { \ + .line[0] = { \ + .text = __h0, \ + .span = __s, \ + }, \ + .line[1] = { \ + .text = __h1, \ + }, \ + } + +#define HEADER_SPAN_LOW(__h) \ + { \ + .line[1] = { \ + .text = __h, \ + }, \ + } + +static struct c2c_dimension dim_dcacheline = { + .header = HEADER_LOW("Cacheline"), + .name = "dcacheline", + .cmp = dcacheline_cmp, + .entry = dcacheline_entry, + .width = 18, +}; + +static struct c2c_header header_offset_tui = HEADER_LOW("Off"); + +static struct c2c_dimension dim_offset = { + .header = HEADER_BOTH("Data address", "Offset"), + .name = "offset", + .cmp = offset_cmp, + .entry = offset_entry, + .width = 18, +}; + +static struct c2c_dimension dim_iaddr = { + .header = HEADER_LOW("Code address"), + .name = "iaddr", + .cmp = iaddr_cmp, + .entry = iaddr_entry, + .width = 18, +}; + +static struct c2c_dimension dim_tot_hitm = { + .header = HEADER_SPAN("----- LLC Load Hitm -----", "Total", 2), + .name = "tot_hitm", + .cmp = tot_hitm_cmp, + .entry = tot_hitm_entry, + .width = 7, +}; + +static struct c2c_dimension dim_lcl_hitm = { + .header = HEADER_SPAN_LOW("Lcl"), + .name = "lcl_hitm", + .cmp = lcl_hitm_cmp, + .entry = lcl_hitm_entry, + .width = 7, +}; + +static struct c2c_dimension dim_rmt_hitm = { + .header = HEADER_SPAN_LOW("Rmt"), + .name = "rmt_hitm", + .cmp = rmt_hitm_cmp, + .entry = rmt_hitm_entry, + .width = 7, +}; + +static struct c2c_dimension dim_cl_rmt_hitm = { + .header = HEADER_SPAN("----- HITM -----", "Rmt", 1), + .name = "cl_rmt_hitm", + .cmp = rmt_hitm_cmp, + .entry = rmt_hitm_entry, + .width = 7, +}; + +static struct c2c_dimension dim_cl_lcl_hitm = { + .header = HEADER_SPAN_LOW("Lcl"), + .name = "cl_lcl_hitm", + .cmp = lcl_hitm_cmp, + .entry = lcl_hitm_entry, + .width = 7, +}; + +static struct c2c_dimension dim_stores = { + .header = HEADER_SPAN("---- Store Reference ----", "Total", 2), + .name = "stores", + .cmp = store_cmp, + .entry = store_entry, + .width = 7, +}; + +static struct c2c_dimension dim_stores_l1hit = { + .header = HEADER_SPAN_LOW("L1Hit"), + .name = "stores_l1hit", + .cmp = st_l1hit_cmp, + .entry = st_l1hit_entry, + .width = 7, +}; + +static struct c2c_dimension dim_stores_l1miss = { + .header = HEADER_SPAN_LOW("L1Miss"), + .name = "stores_l1miss", + .cmp = st_l1miss_cmp, + .entry = st_l1miss_entry, + .width = 7, +}; + +static struct c2c_dimension dim_cl_stores_l1hit = { + .header = HEADER_SPAN("-- Store Refs --", "L1 Hit", 1), + .name = "cl_stores_l1hit", + .cmp = st_l1hit_cmp, + .entry = st_l1hit_entry, + .width = 7, +}; + +static struct c2c_dimension dim_cl_stores_l1miss = { + .header = HEADER_SPAN_LOW("L1 Miss"), + .name = "cl_stores_l1miss", + .cmp = st_l1miss_cmp, + .entry = st_l1miss_entry, + .width = 7, +}; + +static struct c2c_dimension dim_ld_fbhit = { + .header = HEADER_SPAN("----- Core Load Hit -----", "FB", 2), + .name = "ld_fbhit", + .cmp = ld_fbhit_cmp, + .entry = ld_fbhit_entry, + .width = 7, +}; + +static struct c2c_dimension dim_ld_l1hit = { + .header = HEADER_SPAN_LOW("L1"), + .name = "ld_l1hit", + .cmp = ld_l1hit_cmp, + .entry = ld_l1hit_entry, + .width = 7, +}; + +static struct c2c_dimension dim_ld_l2hit = { + .header = HEADER_SPAN_LOW("L2"), + .name = "ld_l2hit", + .cmp = ld_l2hit_cmp, + .entry = ld_l2hit_entry, + .width = 7, +}; + +static struct c2c_dimension dim_ld_llchit = { + .header = HEADER_SPAN("-- LLC Load Hit --", "Llc", 1), + .name = "ld_lclhit", + .cmp = ld_llchit_cmp, + .entry = ld_llchit_entry, + .width = 8, +}; + +static struct c2c_dimension dim_ld_rmthit = { + .header = HEADER_SPAN_LOW("Rmt"), + .name = "ld_rmthit", + .cmp = rmt_hit_cmp, + .entry = rmt_hit_entry, + .width = 8, +}; + +static struct c2c_dimension dim_ld_llcmiss = { + .header = HEADER_BOTH("LLC", "Ld Miss"), + .name = "ld_llcmiss", + .cmp = ld_llcmiss_cmp, + .entry = ld_llcmiss_entry, + .width = 7, +}; + +static struct c2c_dimension dim_tot_recs = { + .header = HEADER_BOTH("Total", "records"), + .name = "tot_recs", + .cmp = tot_recs_cmp, + .entry = tot_recs_entry, + .width = 7, +}; + +static struct c2c_dimension dim_tot_loads = { + .header = HEADER_BOTH("Total", "Loads"), + .name = "tot_loads", + .cmp = tot_loads_cmp, + .entry = tot_loads_entry, + .width = 7, +}; + +static struct c2c_header percent_hitm_header[] = { + [DISPLAY_LCL] = HEADER_BOTH("Lcl", "Hitm"), + [DISPLAY_RMT] = HEADER_BOTH("Rmt", "Hitm"), + [DISPLAY_TOT] = HEADER_BOTH("Tot", "Hitm"), +}; + +static struct c2c_dimension dim_percent_hitm = { + .name = "percent_hitm", + .cmp = percent_hitm_cmp, + .entry = percent_hitm_entry, + .color = percent_hitm_color, + .width = 7, +}; + +static struct c2c_dimension dim_percent_rmt_hitm = { + .header = HEADER_SPAN("----- HITM -----", "Rmt", 1), + .name = "percent_rmt_hitm", + .cmp = percent_rmt_hitm_cmp, + .entry = percent_rmt_hitm_entry, + .color = percent_rmt_hitm_color, + .width = 7, +}; + +static struct c2c_dimension dim_percent_lcl_hitm = { + .header = HEADER_SPAN_LOW("Lcl"), + .name = "percent_lcl_hitm", + .cmp = percent_lcl_hitm_cmp, + .entry = percent_lcl_hitm_entry, + .color = percent_lcl_hitm_color, + .width = 7, +}; + +static struct c2c_dimension dim_percent_stores_l1hit = { + .header = HEADER_SPAN("-- Store Refs --", "L1 Hit", 1), + .name = "percent_stores_l1hit", + .cmp = percent_stores_l1hit_cmp, + .entry = percent_stores_l1hit_entry, + .color = percent_stores_l1hit_color, + .width = 7, +}; + +static struct c2c_dimension dim_percent_stores_l1miss = { + .header = HEADER_SPAN_LOW("L1 Miss"), + .name = "percent_stores_l1miss", + .cmp = percent_stores_l1miss_cmp, + .entry = percent_stores_l1miss_entry, + .color = percent_stores_l1miss_color, + .width = 7, +}; + +static struct c2c_dimension dim_dram_lcl = { + .header = HEADER_SPAN("--- Load Dram ----", "Lcl", 1), + .name = "dram_lcl", + .cmp = lcl_dram_cmp, + .entry = lcl_dram_entry, + .width = 8, +}; + +static struct c2c_dimension dim_dram_rmt = { + .header = HEADER_SPAN_LOW("Rmt"), + .name = "dram_rmt", + .cmp = rmt_dram_cmp, + .entry = rmt_dram_entry, + .width = 8, +}; + +static struct c2c_dimension dim_pid = { + .header = HEADER_LOW("Pid"), + .name = "pid", + .cmp = pid_cmp, + .entry = pid_entry, + .width = 7, +}; + +static struct c2c_dimension dim_tid = { + .header = HEADER_LOW("Tid"), + .name = "tid", + .se = &sort_thread, +}; + +static struct c2c_dimension dim_symbol = { + .name = "symbol", + .se = &sort_sym, +}; + +static struct c2c_dimension dim_dso = { + .header = HEADER_BOTH("Shared", "Object"), + .name = "dso", + .se = &sort_dso, +}; + +static struct c2c_header header_node[3] = { + HEADER_LOW("Node"), + HEADER_LOW("Node{cpus %hitms %stores}"), + HEADER_LOW("Node{cpu list}"), +}; + +static struct c2c_dimension dim_node = { + .name = "node", + .cmp = empty_cmp, + .entry = node_entry, + .width = 4, +}; + +static struct c2c_dimension dim_mean_rmt = { + .header = HEADER_SPAN("---------- cycles ----------", "rmt hitm", 2), + .name = "mean_rmt", + .cmp = empty_cmp, + .entry = mean_rmt_entry, + .width = 8, +}; + +static struct c2c_dimension dim_mean_lcl = { + .header = HEADER_SPAN_LOW("lcl hitm"), + .name = "mean_lcl", + .cmp = empty_cmp, + .entry = mean_lcl_entry, + .width = 8, +}; + +static struct c2c_dimension dim_mean_load = { + .header = HEADER_SPAN_LOW("load"), + .name = "mean_load", + .cmp = empty_cmp, + .entry = mean_load_entry, + .width = 8, +}; + +static struct c2c_dimension dim_cpucnt = { + .header = HEADER_BOTH("cpu", "cnt"), + .name = "cpucnt", + .cmp = empty_cmp, + .entry = cpucnt_entry, + .width = 8, +}; + +static struct c2c_dimension dim_srcline = { + .name = "cl_srcline", + .se = &sort_srcline, +}; + +static struct c2c_dimension dim_dcacheline_idx = { + .header = HEADER_LOW("Index"), + .name = "cl_idx", + .cmp = empty_cmp, + .entry = cl_idx_entry, + .width = 5, +}; + +static struct c2c_dimension dim_dcacheline_num = { + .header = HEADER_LOW("Num"), + .name = "cl_num", + .cmp = empty_cmp, + .entry = cl_idx_entry, + .width = 5, +}; + +static struct c2c_dimension dim_dcacheline_num_empty = { + .header = HEADER_LOW("Num"), + .name = "cl_num_empty", + .cmp = empty_cmp, + .entry = cl_idx_empty_entry, + .width = 5, +}; + +static struct c2c_dimension *dimensions[] = { + &dim_dcacheline, + &dim_offset, + &dim_iaddr, + &dim_tot_hitm, + &dim_lcl_hitm, + &dim_rmt_hitm, + &dim_cl_lcl_hitm, + &dim_cl_rmt_hitm, + &dim_stores, + &dim_stores_l1hit, + &dim_stores_l1miss, + &dim_cl_stores_l1hit, + &dim_cl_stores_l1miss, + &dim_ld_fbhit, + &dim_ld_l1hit, + &dim_ld_l2hit, + &dim_ld_llchit, + &dim_ld_rmthit, + &dim_ld_llcmiss, + &dim_tot_recs, + &dim_tot_loads, + &dim_percent_hitm, + &dim_percent_rmt_hitm, + &dim_percent_lcl_hitm, + &dim_percent_stores_l1hit, + &dim_percent_stores_l1miss, + &dim_dram_lcl, + &dim_dram_rmt, + &dim_pid, + &dim_tid, + &dim_symbol, + &dim_dso, + &dim_node, + &dim_mean_rmt, + &dim_mean_lcl, + &dim_mean_load, + &dim_cpucnt, + &dim_srcline, + &dim_dcacheline_idx, + &dim_dcacheline_num, + &dim_dcacheline_num_empty, + NULL, +}; + +static void fmt_free(struct perf_hpp_fmt *fmt) +{ + struct c2c_fmt *c2c_fmt; + + c2c_fmt = container_of(fmt, struct c2c_fmt, fmt); + free(c2c_fmt); +} + +static bool fmt_equal(struct perf_hpp_fmt *a, struct perf_hpp_fmt *b) +{ + struct c2c_fmt *c2c_a = container_of(a, struct c2c_fmt, fmt); + struct c2c_fmt *c2c_b = container_of(b, struct c2c_fmt, fmt); + + return c2c_a->dim == c2c_b->dim; +} + +static struct c2c_dimension *get_dimension(const char *name) +{ + unsigned int i; + + for (i = 0; dimensions[i]; i++) { + struct c2c_dimension *dim = dimensions[i]; + + if (!strcmp(dim->name, name)) + return dim; + }; + + return NULL; +} + +static int c2c_se_entry(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, + struct hist_entry *he) +{ + struct c2c_fmt *c2c_fmt = container_of(fmt, struct c2c_fmt, fmt); + struct c2c_dimension *dim = c2c_fmt->dim; + size_t len = fmt->user_len; + + if (!len) { + len = hists__col_len(he->hists, dim->se->se_width_idx); + + if (dim == &dim_symbol || dim == &dim_srcline) + len = symbol_width(he->hists, dim->se); + } + + return dim->se->se_snprintf(he, hpp->buf, hpp->size, len); +} + +static int64_t c2c_se_cmp(struct perf_hpp_fmt *fmt, + struct hist_entry *a, struct hist_entry *b) +{ + struct c2c_fmt *c2c_fmt = container_of(fmt, struct c2c_fmt, fmt); + struct c2c_dimension *dim = c2c_fmt->dim; + + return dim->se->se_cmp(a, b); +} + +static int64_t c2c_se_collapse(struct perf_hpp_fmt *fmt, + struct hist_entry *a, struct hist_entry *b) +{ + struct c2c_fmt *c2c_fmt = container_of(fmt, struct c2c_fmt, fmt); + struct c2c_dimension *dim = c2c_fmt->dim; + int64_t (*collapse_fn)(struct hist_entry *, struct hist_entry *); + + collapse_fn = dim->se->se_collapse ?: dim->se->se_cmp; + return collapse_fn(a, b); +} + +static struct c2c_fmt *get_format(const char *name) +{ + struct c2c_dimension *dim = get_dimension(name); + struct c2c_fmt *c2c_fmt; + struct perf_hpp_fmt *fmt; + + if (!dim) + return NULL; + + c2c_fmt = zalloc(sizeof(*c2c_fmt)); + if (!c2c_fmt) + return NULL; + + c2c_fmt->dim = dim; + + fmt = &c2c_fmt->fmt; + INIT_LIST_HEAD(&fmt->list); + INIT_LIST_HEAD(&fmt->sort_list); + + fmt->cmp = dim->se ? c2c_se_cmp : dim->cmp; + fmt->sort = dim->se ? c2c_se_cmp : dim->cmp; + fmt->color = dim->se ? NULL : dim->color; + fmt->entry = dim->se ? c2c_se_entry : dim->entry; + fmt->header = c2c_header; + fmt->width = c2c_width; + fmt->collapse = dim->se ? c2c_se_collapse : dim->cmp; + fmt->equal = fmt_equal; + fmt->free = fmt_free; + + return c2c_fmt; +} + +static int c2c_hists__init_output(struct perf_hpp_list *hpp_list, char *name) +{ + struct c2c_fmt *c2c_fmt = get_format(name); + + if (!c2c_fmt) { + reset_dimensions(); + return output_field_add(hpp_list, name); + } + + perf_hpp_list__column_register(hpp_list, &c2c_fmt->fmt); + return 0; +} + +static int c2c_hists__init_sort(struct perf_hpp_list *hpp_list, char *name) +{ + struct c2c_fmt *c2c_fmt = get_format(name); + struct c2c_dimension *dim; + + if (!c2c_fmt) { + reset_dimensions(); + return sort_dimension__add(hpp_list, name, NULL, 0); + } + + dim = c2c_fmt->dim; + if (dim == &dim_dso) + hpp_list->dso = 1; + + perf_hpp_list__register_sort_field(hpp_list, &c2c_fmt->fmt); + return 0; +} + +#define PARSE_LIST(_list, _fn) \ + do { \ + char *tmp, *tok; \ + ret = 0; \ + \ + if (!_list) \ + break; \ + \ + for (tok = strtok_r((char *)_list, ", ", &tmp); \ + tok; tok = strtok_r(NULL, ", ", &tmp)) { \ + ret = _fn(hpp_list, tok); \ + if (ret == -EINVAL) { \ + error("Invalid --fields key: `%s'", tok); \ + break; \ + } else if (ret == -ESRCH) { \ + error("Unknown --fields key: `%s'", tok); \ + break; \ + } \ + } \ + } while (0) + +static int hpp_list__parse(struct perf_hpp_list *hpp_list, + const char *output_, + const char *sort_) +{ + char *output = output_ ? strdup(output_) : NULL; + char *sort = sort_ ? strdup(sort_) : NULL; + int ret; + + PARSE_LIST(output, c2c_hists__init_output); + PARSE_LIST(sort, c2c_hists__init_sort); + + /* copy sort keys to output fields */ + perf_hpp__setup_output_field(hpp_list); + + /* + * We dont need other sorting keys other than those + * we already specified. It also really slows down + * the processing a lot with big number of output + * fields, so switching this off for c2c. + */ + +#if 0 + /* and then copy output fields to sort keys */ + perf_hpp__append_sort_keys(&hists->list); +#endif + + free(output); + free(sort); + return ret; +} + +static int c2c_hists__init(struct c2c_hists *hists, + const char *sort, + int nr_header_lines) +{ + __hists__init(&hists->hists, &hists->list); + + /* + * Initialize only with sort fields, we need to resort + * later anyway, and that's where we add output fields + * as well. + */ + perf_hpp_list__init(&hists->list); + + /* Overload number of header lines.*/ + hists->list.nr_header_lines = nr_header_lines; + + return hpp_list__parse(&hists->list, NULL, sort); +} + +__maybe_unused +static int c2c_hists__reinit(struct c2c_hists *c2c_hists, + const char *output, + const char *sort) +{ + perf_hpp__reset_output_field(&c2c_hists->list); + return hpp_list__parse(&c2c_hists->list, output, sort); +} + +#define DISPLAY_LINE_LIMIT 0.0005 + +static bool he__display(struct hist_entry *he, struct c2c_stats *stats) +{ + struct c2c_hist_entry *c2c_he; + double ld_dist; + + if (c2c.show_all) + return true; + + c2c_he = container_of(he, struct c2c_hist_entry, he); + +#define FILTER_HITM(__h) \ + if (stats->__h) { \ + ld_dist = ((double)c2c_he->stats.__h / stats->__h); \ + if (ld_dist < DISPLAY_LINE_LIMIT) \ + he->filtered = HIST_FILTER__C2C; \ + } else { \ + he->filtered = HIST_FILTER__C2C; \ + } + + switch (c2c.display) { + case DISPLAY_LCL: + FILTER_HITM(lcl_hitm); + break; + case DISPLAY_RMT: + FILTER_HITM(rmt_hitm); + break; + case DISPLAY_TOT: + FILTER_HITM(tot_hitm); + default: + break; + }; + +#undef FILTER_HITM + + return he->filtered == 0; +} + +static inline int valid_hitm_or_store(struct hist_entry *he) +{ + struct c2c_hist_entry *c2c_he; + bool has_hitm; + + c2c_he = container_of(he, struct c2c_hist_entry, he); + has_hitm = c2c.display == DISPLAY_TOT ? c2c_he->stats.tot_hitm : + c2c.display == DISPLAY_LCL ? c2c_he->stats.lcl_hitm : + c2c_he->stats.rmt_hitm; + return has_hitm || c2c_he->stats.store; +} + +static void calc_width(struct hist_entry *he) +{ + struct c2c_hists *c2c_hists; + + c2c_hists = container_of(he->hists, struct c2c_hists, hists); + hists__calc_col_len(&c2c_hists->hists, he); +} + +static int filter_cb(struct hist_entry *he) +{ + if (c2c.show_src && !he->srcline) + he->srcline = hist_entry__get_srcline(he); + + calc_width(he); + + if (!valid_hitm_or_store(he)) + he->filtered = HIST_FILTER__C2C; + + return 0; +} + +static int resort_cl_cb(struct hist_entry *he) +{ + struct c2c_hist_entry *c2c_he; + struct c2c_hists *c2c_hists; + bool display = he__display(he, &c2c.hitm_stats); + + c2c_he = container_of(he, struct c2c_hist_entry, he); + c2c_hists = c2c_he->hists; + + calc_width(he); + + if (display && c2c_hists) { + static unsigned int idx; + + c2c_he->cacheline_idx = idx++; + + c2c_hists__reinit(c2c_hists, c2c.cl_output, c2c.cl_resort); + + hists__collapse_resort(&c2c_hists->hists, NULL); + hists__output_resort_cb(&c2c_hists->hists, NULL, filter_cb); + } + + return 0; +} + +static void setup_nodes_header(void) +{ + dim_node.header = header_node[c2c.node_info]; +} + +static int setup_nodes(struct perf_session *session) +{ + struct numa_node *n; + unsigned long **nodes; + int node, cpu; + int *cpu2node; + + if (c2c.node_info > 2) + c2c.node_info = 2; + + c2c.nodes_cnt = session->header.env.nr_numa_nodes; + c2c.cpus_cnt = session->header.env.nr_cpus_online; + + n = session->header.env.numa_nodes; + if (!n) + return -EINVAL; + + nodes = zalloc(sizeof(unsigned long *) * c2c.nodes_cnt); + if (!nodes) + return -ENOMEM; + + c2c.nodes = nodes; + + cpu2node = zalloc(sizeof(int) * c2c.cpus_cnt); + if (!cpu2node) + return -ENOMEM; + + for (cpu = 0; cpu < c2c.cpus_cnt; cpu++) + cpu2node[cpu] = -1; + + c2c.cpu2node = cpu2node; + + for (node = 0; node < c2c.nodes_cnt; node++) { + struct cpu_map *map = n[node].map; + unsigned long *set; + + set = bitmap_alloc(c2c.cpus_cnt); + if (!set) + return -ENOMEM; + + for (cpu = 0; cpu < map->nr; cpu++) { + set_bit(map->map[cpu], set); + + if (WARN_ONCE(cpu2node[map->map[cpu]] != -1, "node/cpu topology bug")) + return -EINVAL; + + cpu2node[map->map[cpu]] = node; + } + + nodes[node] = set; + } + + setup_nodes_header(); + return 0; +} + +#define HAS_HITMS(__h) ((__h)->stats.lcl_hitm || (__h)->stats.rmt_hitm) + +static int resort_hitm_cb(struct hist_entry *he) +{ + struct c2c_hist_entry *c2c_he; + c2c_he = container_of(he, struct c2c_hist_entry, he); + + if (HAS_HITMS(c2c_he)) { + c2c.shared_clines++; + c2c_add_stats(&c2c.hitm_stats, &c2c_he->stats); + } + + return 0; +} + +static int hists__iterate_cb(struct hists *hists, hists__resort_cb_t cb) +{ + struct rb_node *next = rb_first(&hists->entries); + int ret = 0; + + while (next) { + struct hist_entry *he; + + he = rb_entry(next, struct hist_entry, rb_node); + ret = cb(he); + if (ret) + break; + next = rb_next(&he->rb_node); + } + + return ret; +} + +static void print_c2c__display_stats(FILE *out) +{ + int llc_misses; + struct c2c_stats *stats = &c2c.hists.stats; + + llc_misses = stats->lcl_dram + + stats->rmt_dram + + stats->rmt_hit + + stats->rmt_hitm; + + fprintf(out, "=================================================\n"); + fprintf(out, " Trace Event Information \n"); + fprintf(out, "=================================================\n"); + fprintf(out, " Total records : %10d\n", stats->nr_entries); + fprintf(out, " Locked Load/Store Operations : %10d\n", stats->locks); + fprintf(out, " Load Operations : %10d\n", stats->load); + fprintf(out, " Loads - uncacheable : %10d\n", stats->ld_uncache); + fprintf(out, " Loads - IO : %10d\n", stats->ld_io); + fprintf(out, " Loads - Miss : %10d\n", stats->ld_miss); + fprintf(out, " Loads - no mapping : %10d\n", stats->ld_noadrs); + fprintf(out, " Load Fill Buffer Hit : %10d\n", stats->ld_fbhit); + fprintf(out, " Load L1D hit : %10d\n", stats->ld_l1hit); + fprintf(out, " Load L2D hit : %10d\n", stats->ld_l2hit); + fprintf(out, " Load LLC hit : %10d\n", stats->ld_llchit + stats->lcl_hitm); + fprintf(out, " Load Local HITM : %10d\n", stats->lcl_hitm); + fprintf(out, " Load Remote HITM : %10d\n", stats->rmt_hitm); + fprintf(out, " Load Remote HIT : %10d\n", stats->rmt_hit); + fprintf(out, " Load Local DRAM : %10d\n", stats->lcl_dram); + fprintf(out, " Load Remote DRAM : %10d\n", stats->rmt_dram); + fprintf(out, " Load MESI State Exclusive : %10d\n", stats->ld_excl); + fprintf(out, " Load MESI State Shared : %10d\n", stats->ld_shared); + fprintf(out, " Load LLC Misses : %10d\n", llc_misses); + fprintf(out, " LLC Misses to Local DRAM : %10.1f%%\n", ((double)stats->lcl_dram/(double)llc_misses) * 100.); + fprintf(out, " LLC Misses to Remote DRAM : %10.1f%%\n", ((double)stats->rmt_dram/(double)llc_misses) * 100.); + fprintf(out, " LLC Misses to Remote cache (HIT) : %10.1f%%\n", ((double)stats->rmt_hit /(double)llc_misses) * 100.); + fprintf(out, " LLC Misses to Remote cache (HITM) : %10.1f%%\n", ((double)stats->rmt_hitm/(double)llc_misses) * 100.); + fprintf(out, " Store Operations : %10d\n", stats->store); + fprintf(out, " Store - uncacheable : %10d\n", stats->st_uncache); + fprintf(out, " Store - no mapping : %10d\n", stats->st_noadrs); + fprintf(out, " Store L1D Hit : %10d\n", stats->st_l1hit); + fprintf(out, " Store L1D Miss : %10d\n", stats->st_l1miss); + fprintf(out, " No Page Map Rejects : %10d\n", stats->nomap); + fprintf(out, " Unable to parse data source : %10d\n", stats->noparse); +} + +static void print_shared_cacheline_info(FILE *out) +{ + struct c2c_stats *stats = &c2c.hitm_stats; + int hitm_cnt = stats->lcl_hitm + stats->rmt_hitm; + + fprintf(out, "=================================================\n"); + fprintf(out, " Global Shared Cache Line Event Information \n"); + fprintf(out, "=================================================\n"); + fprintf(out, " Total Shared Cache Lines : %10d\n", c2c.shared_clines); + fprintf(out, " Load HITs on shared lines : %10d\n", stats->load); + fprintf(out, " Fill Buffer Hits on shared lines : %10d\n", stats->ld_fbhit); + fprintf(out, " L1D hits on shared lines : %10d\n", stats->ld_l1hit); + fprintf(out, " L2D hits on shared lines : %10d\n", stats->ld_l2hit); + fprintf(out, " LLC hits on shared lines : %10d\n", stats->ld_llchit + stats->lcl_hitm); + fprintf(out, " Locked Access on shared lines : %10d\n", stats->locks); + fprintf(out, " Store HITs on shared lines : %10d\n", stats->store); + fprintf(out, " Store L1D hits on shared lines : %10d\n", stats->st_l1hit); + fprintf(out, " Total Merged records : %10d\n", hitm_cnt + stats->store); +} + +static void print_cacheline(struct c2c_hists *c2c_hists, + struct hist_entry *he_cl, + struct perf_hpp_list *hpp_list, + FILE *out) +{ + char bf[1000]; + struct perf_hpp hpp = { + .buf = bf, + .size = 1000, + }; + static bool once; + + if (!once) { + hists__fprintf_headers(&c2c_hists->hists, out); + once = true; + } else { + fprintf(out, "\n"); + } + + fprintf(out, " -------------------------------------------------------------\n"); + __hist_entry__snprintf(he_cl, &hpp, hpp_list); + fprintf(out, "%s\n", bf); + fprintf(out, " -------------------------------------------------------------\n"); + + hists__fprintf(&c2c_hists->hists, false, 0, 0, 0, out, true); +} + +static void print_pareto(FILE *out) +{ + struct perf_hpp_list hpp_list; + struct rb_node *nd; + int ret; + + perf_hpp_list__init(&hpp_list); + ret = hpp_list__parse(&hpp_list, + "cl_num," + "cl_rmt_hitm," + "cl_lcl_hitm," + "cl_stores_l1hit," + "cl_stores_l1miss," + "dcacheline", + NULL); + + if (WARN_ONCE(ret, "failed to setup sort entries\n")) + return; + + nd = rb_first(&c2c.hists.hists.entries); + + for (; nd; nd = rb_next(nd)) { + struct hist_entry *he = rb_entry(nd, struct hist_entry, rb_node); + struct c2c_hist_entry *c2c_he; + + if (he->filtered) + continue; + + c2c_he = container_of(he, struct c2c_hist_entry, he); + print_cacheline(c2c_he->hists, he, &hpp_list, out); + } +} + +static void print_c2c_info(FILE *out, struct perf_session *session) +{ + struct perf_evlist *evlist = session->evlist; + struct perf_evsel *evsel; + bool first = true; + + fprintf(out, "=================================================\n"); + fprintf(out, " c2c details \n"); + fprintf(out, "=================================================\n"); + + evlist__for_each_entry(evlist, evsel) { + fprintf(out, "%-36s: %s\n", first ? " Events" : "", + perf_evsel__name(evsel)); + first = false; + } + fprintf(out, " Cachelines sort on : %s HITMs\n", + display_str[c2c.display]); + fprintf(out, " Cacheline data grouping : %s\n", c2c.cl_sort); +} + +static void perf_c2c__hists_fprintf(FILE *out, struct perf_session *session) +{ + setup_pager(); + + print_c2c__display_stats(out); + fprintf(out, "\n"); + print_shared_cacheline_info(out); + fprintf(out, "\n"); + print_c2c_info(out, session); + + if (c2c.stats_only) + return; + + fprintf(out, "\n"); + fprintf(out, "=================================================\n"); + fprintf(out, " Shared Data Cache Line Table \n"); + fprintf(out, "=================================================\n"); + fprintf(out, "#\n"); + + hists__fprintf(&c2c.hists.hists, true, 0, 0, 0, stdout, false); + + fprintf(out, "\n"); + fprintf(out, "=================================================\n"); + fprintf(out, " Shared Cache Line Distribution Pareto \n"); + fprintf(out, "=================================================\n"); + fprintf(out, "#\n"); + + print_pareto(out); +} + +#ifdef HAVE_SLANG_SUPPORT +static void c2c_browser__update_nr_entries(struct hist_browser *hb) +{ + u64 nr_entries = 0; + struct rb_node *nd = rb_first(&hb->hists->entries); + + while (nd) { + struct hist_entry *he = rb_entry(nd, struct hist_entry, rb_node); + + if (!he->filtered) + nr_entries++; + + nd = rb_next(nd); + } + + hb->nr_non_filtered_entries = nr_entries; +} + +struct c2c_cacheline_browser { + struct hist_browser hb; + struct hist_entry *he; +}; + +static int +perf_c2c_cacheline_browser__title(struct hist_browser *browser, + char *bf, size_t size) +{ + struct c2c_cacheline_browser *cl_browser; + struct hist_entry *he; + uint64_t addr = 0; + + cl_browser = container_of(browser, struct c2c_cacheline_browser, hb); + he = cl_browser->he; + + if (he->mem_info) + addr = cl_address(he->mem_info->daddr.addr); + + scnprintf(bf, size, "Cacheline 0x%lx", addr); + return 0; +} + +static struct c2c_cacheline_browser* +c2c_cacheline_browser__new(struct hists *hists, struct hist_entry *he) +{ + struct c2c_cacheline_browser *browser; + + browser = zalloc(sizeof(*browser)); + if (browser) { + hist_browser__init(&browser->hb, hists); + browser->hb.c2c_filter = true; + browser->hb.title = perf_c2c_cacheline_browser__title; + browser->he = he; + } + + return browser; +} + +static int perf_c2c__browse_cacheline(struct hist_entry *he) +{ + struct c2c_hist_entry *c2c_he; + struct c2c_hists *c2c_hists; + struct c2c_cacheline_browser *cl_browser; + struct hist_browser *browser; + int key = -1; + const char help[] = + " ENTER Togle callchains (if present) \n" + " n Togle Node details info \n" + " s Togle full lenght of symbol and source line columns \n" + " q Return back to cacheline list \n"; + + /* Display compact version first. */ + c2c.symbol_full = false; + + c2c_he = container_of(he, struct c2c_hist_entry, he); + c2c_hists = c2c_he->hists; + + cl_browser = c2c_cacheline_browser__new(&c2c_hists->hists, he); + if (cl_browser == NULL) + return -1; + + browser = &cl_browser->hb; + + /* reset abort key so that it can get Ctrl-C as a key */ + SLang_reset_tty(); + SLang_init_tty(0, 0, 0); + + c2c_browser__update_nr_entries(browser); + + while (1) { + key = hist_browser__run(browser, "? - help"); + + switch (key) { + case 's': + c2c.symbol_full = !c2c.symbol_full; + break; + case 'n': + c2c.node_info = (c2c.node_info + 1) % 3; + setup_nodes_header(); + break; + case 'q': + goto out; + case '?': + ui_browser__help_window(&browser->b, help); + break; + default: + break; + } + } + +out: + free(cl_browser); + return 0; +} + +static int perf_c2c_browser__title(struct hist_browser *browser, + char *bf, size_t size) +{ + scnprintf(bf, size, + "Shared Data Cache Line Table " + "(%lu entries, sorted on %s HITMs)", + browser->nr_non_filtered_entries, + display_str[c2c.display]); + return 0; +} + +static struct hist_browser* +perf_c2c_browser__new(struct hists *hists) +{ + struct hist_browser *browser = hist_browser__new(hists); + + if (browser) { + browser->title = perf_c2c_browser__title; + browser->c2c_filter = true; + } + + return browser; +} + +static int perf_c2c__hists_browse(struct hists *hists) +{ + struct hist_browser *browser; + int key = -1; + const char help[] = + " d Display cacheline details \n" + " ENTER Togle callchains (if present) \n" + " q Quit \n"; + + browser = perf_c2c_browser__new(hists); + if (browser == NULL) + return -1; + + /* reset abort key so that it can get Ctrl-C as a key */ + SLang_reset_tty(); + SLang_init_tty(0, 0, 0); + + c2c_browser__update_nr_entries(browser); + + while (1) { + key = hist_browser__run(browser, "? - help"); + + switch (key) { + case 'q': + goto out; + case 'd': + perf_c2c__browse_cacheline(browser->he_selection); + break; + case '?': + ui_browser__help_window(&browser->b, help); + break; + default: + break; + } + } + +out: + hist_browser__delete(browser); + return 0; +} + +static void perf_c2c_display(struct perf_session *session) +{ + if (c2c.use_stdio) + perf_c2c__hists_fprintf(stdout, session); + else + perf_c2c__hists_browse(&c2c.hists.hists); +} +#else +static void perf_c2c_display(struct perf_session *session) +{ + use_browser = 0; + perf_c2c__hists_fprintf(stdout, session); +} +#endif /* HAVE_SLANG_SUPPORT */ + +static void ui_quirks(void) +{ + if (!c2c.use_stdio) { + dim_offset.width = 5; + dim_offset.header = header_offset_tui; + } + + dim_percent_hitm.header = percent_hitm_header[c2c.display]; +} + +#define CALLCHAIN_DEFAULT_OPT "graph,0.5,caller,function,percent" + +const char callchain_help[] = "Display call graph (stack chain/backtrace):\n\n" + CALLCHAIN_REPORT_HELP + "\n\t\t\t\tDefault: " CALLCHAIN_DEFAULT_OPT; + +static int +parse_callchain_opt(const struct option *opt, const char *arg, int unset) +{ + struct callchain_param *callchain = opt->value; + + callchain->enabled = !unset; + /* + * --no-call-graph + */ + if (unset) { + symbol_conf.use_callchain = false; + callchain->mode = CHAIN_NONE; + return 0; + } + + return parse_callchain_report_opt(arg); +} + +static int setup_callchain(struct perf_evlist *evlist) +{ + u64 sample_type = perf_evlist__combined_sample_type(evlist); + enum perf_call_graph_mode mode = CALLCHAIN_NONE; + + if ((sample_type & PERF_SAMPLE_REGS_USER) && + (sample_type & PERF_SAMPLE_STACK_USER)) + mode = CALLCHAIN_DWARF; + else if (sample_type & PERF_SAMPLE_BRANCH_STACK) + mode = CALLCHAIN_LBR; + else if (sample_type & PERF_SAMPLE_CALLCHAIN) + mode = CALLCHAIN_FP; + + if (!callchain_param.enabled && + callchain_param.mode != CHAIN_NONE && + mode != CALLCHAIN_NONE) { + symbol_conf.use_callchain = true; + if (callchain_register_param(&callchain_param) < 0) { + ui__error("Can't register callchain params.\n"); + return -EINVAL; + } + } + + callchain_param.record_mode = mode; + callchain_param.min_percent = 0; + return 0; +} + +static int setup_display(const char *str) +{ + const char *display = str ?: "tot"; + + if (!strcmp(display, "tot")) + c2c.display = DISPLAY_TOT; + else if (!strcmp(display, "rmt")) + c2c.display = DISPLAY_RMT; + else if (!strcmp(display, "lcl")) + c2c.display = DISPLAY_LCL; + else { + pr_err("failed: unknown display type: %s\n", str); + return -1; + } + + return 0; +} + +#define for_each_token(__tok, __buf, __sep, __tmp) \ + for (__tok = strtok_r(__buf, __sep, &__tmp); __tok; \ + __tok = strtok_r(NULL, __sep, &__tmp)) + +static int build_cl_output(char *cl_sort, bool no_source) +{ + char *tok, *tmp, *buf = strdup(cl_sort); + bool add_pid = false; + bool add_tid = false; + bool add_iaddr = false; + bool add_sym = false; + bool add_dso = false; + bool add_src = false; + + if (!buf) + return -ENOMEM; + + for_each_token(tok, buf, ",", tmp) { + if (!strcmp(tok, "tid")) { + add_tid = true; + } else if (!strcmp(tok, "pid")) { + add_pid = true; + } else if (!strcmp(tok, "iaddr")) { + add_iaddr = true; + add_sym = true; + add_dso = true; + add_src = no_source ? false : true; + } else if (!strcmp(tok, "dso")) { + add_dso = true; + } else if (strcmp(tok, "offset")) { + pr_err("unrecognized sort token: %s\n", tok); + return -EINVAL; + } + } + + if (asprintf(&c2c.cl_output, + "%s%s%s%s%s%s%s%s%s%s", + c2c.use_stdio ? "cl_num_empty," : "", + "percent_rmt_hitm," + "percent_lcl_hitm," + "percent_stores_l1hit," + "percent_stores_l1miss," + "offset,", + add_pid ? "pid," : "", + add_tid ? "tid," : "", + add_iaddr ? "iaddr," : "", + "mean_rmt," + "mean_lcl," + "mean_load," + "cpucnt,", + add_sym ? "symbol," : "", + add_dso ? "dso," : "", + add_src ? "cl_srcline," : "", + "node") < 0) + return -ENOMEM; + + c2c.show_src = add_src; + + free(buf); + return 0; +} + +static int setup_coalesce(const char *coalesce, bool no_source) +{ + const char *c = coalesce ?: coalesce_default; + + if (asprintf(&c2c.cl_sort, "offset,%s", c) < 0) + return -ENOMEM; + + if (build_cl_output(c2c.cl_sort, no_source)) + return -1; + + if (asprintf(&c2c.cl_resort, "offset,%s", + c2c.display == DISPLAY_TOT ? + "tot_hitm" : + c2c.display == DISPLAY_RMT ? + "rmt_hitm,lcl_hitm" : + "lcl_hitm,rmt_hitm") < 0) + return -ENOMEM; + + pr_debug("coalesce sort fields: %s\n", c2c.cl_sort); + pr_debug("coalesce resort fields: %s\n", c2c.cl_resort); + pr_debug("coalesce output fields: %s\n", c2c.cl_output); + return 0; +} + +static int perf_c2c__report(int argc, const char **argv) +{ + struct perf_session *session; + struct ui_progress prog; + struct perf_data_file file = { + .mode = PERF_DATA_MODE_READ, + }; + char callchain_default_opt[] = CALLCHAIN_DEFAULT_OPT; + const char *display = NULL; + const char *coalesce = NULL; + bool no_source = false; + const struct option options[] = { + OPT_STRING('k', "vmlinux", &symbol_conf.vmlinux_name, + "file", "vmlinux pathname"), + OPT_STRING('i', "input", &input_name, "file", + "the input file to process"), + OPT_INCR('N', "node-info", &c2c.node_info, + "show extra node info in report (repeat for more info)"), +#ifdef HAVE_SLANG_SUPPORT + OPT_BOOLEAN(0, "stdio", &c2c.use_stdio, "Use the stdio interface"), +#endif + OPT_BOOLEAN(0, "stats", &c2c.stats_only, + "Use the stdio interface"), + OPT_BOOLEAN(0, "full-symbols", &c2c.symbol_full, + "Display full length of symbols"), + OPT_BOOLEAN(0, "no-source", &no_source, + "Do not display Source Line column"), + OPT_BOOLEAN(0, "show-all", &c2c.show_all, + "Show all captured HITM lines."), + OPT_CALLBACK_DEFAULT('g', "call-graph", &callchain_param, + "print_type,threshold[,print_limit],order,sort_key[,branch],value", + callchain_help, &parse_callchain_opt, + callchain_default_opt), + OPT_STRING('d', "display", &display, "Switch HITM output type", "lcl,rmt"), + OPT_STRING('c', "coalesce", &coalesce, "coalesce fields", + "coalesce fields: pid,tid,iaddr,dso"), + OPT_BOOLEAN('f', "force", &symbol_conf.force, "don't complain, do it"), + OPT_PARENT(c2c_options), + OPT_END() + }; + int err = 0; + + argc = parse_options(argc, argv, options, report_c2c_usage, + PARSE_OPT_STOP_AT_NON_OPTION); + if (argc) + usage_with_options(report_c2c_usage, options); + + if (c2c.stats_only) + c2c.use_stdio = true; + + if (!input_name || !strlen(input_name)) + input_name = "perf.data"; + + file.path = input_name; + file.force = symbol_conf.force; + + err = setup_display(display); + if (err) + goto out; + + err = setup_coalesce(coalesce, no_source); + if (err) { + pr_debug("Failed to initialize hists\n"); + goto out; + } + + err = c2c_hists__init(&c2c.hists, "dcacheline", 2); + if (err) { + pr_debug("Failed to initialize hists\n"); + goto out; + } + + session = perf_session__new(&file, 0, &c2c.tool); + if (session == NULL) { + pr_debug("No memory for session\n"); + goto out; + } + + err = setup_nodes(session); + if (err) { + pr_err("Failed setup nodes\n"); + goto out; + } + + err = setup_callchain(session->evlist); + if (err) + goto out_session; + + if (symbol__init(&session->header.env) < 0) + goto out_session; + + /* No pipe support at the moment. */ + if (perf_data_file__is_pipe(session->file)) { + pr_debug("No pipe support at the moment.\n"); + goto out_session; + } + + if (c2c.use_stdio) + use_browser = 0; + else + use_browser = 1; + + setup_browser(false); + + err = perf_session__process_events(session); + if (err) { + pr_err("failed to process sample\n"); + goto out_session; + } + + c2c_hists__reinit(&c2c.hists, + "cl_idx," + "dcacheline," + "tot_recs," + "percent_hitm," + "tot_hitm,lcl_hitm,rmt_hitm," + "stores,stores_l1hit,stores_l1miss," + "dram_lcl,dram_rmt," + "ld_llcmiss," + "tot_loads," + "ld_fbhit,ld_l1hit,ld_l2hit," + "ld_lclhit,ld_rmthit", + c2c.display == DISPLAY_TOT ? "tot_hitm" : + c2c.display == DISPLAY_LCL ? "lcl_hitm" : "rmt_hitm" + ); + + ui_progress__init(&prog, c2c.hists.hists.nr_entries, "Sorting..."); + + hists__collapse_resort(&c2c.hists.hists, NULL); + hists__output_resort_cb(&c2c.hists.hists, &prog, resort_hitm_cb); + hists__iterate_cb(&c2c.hists.hists, resort_cl_cb); + + ui_progress__finish(); + + ui_quirks(); + + perf_c2c_display(session); + +out_session: + perf_session__delete(session); +out: + return err; +} + +static int parse_record_events(const struct option *opt __maybe_unused, + const char *str, int unset __maybe_unused) +{ + bool *event_set = (bool *) opt->value; + + *event_set = true; + return perf_mem_events__parse(str); +} + + +static const char * const __usage_record[] = { + "perf c2c record [<options>] [<command>]", + "perf c2c record [<options>] -- <command> [<options>]", + NULL +}; + +static const char * const *record_mem_usage = __usage_record; + +static int perf_c2c__record(int argc, const char **argv) +{ + int rec_argc, i = 0, j; + const char **rec_argv; + int ret; + bool all_user = false, all_kernel = false; + bool event_set = false; + struct option options[] = { + OPT_CALLBACK('e', "event", &event_set, "event", + "event selector. Use 'perf mem record -e list' to list available events", + parse_record_events), + OPT_BOOLEAN('u', "all-user", &all_user, "collect only user level data"), + OPT_BOOLEAN('k', "all-kernel", &all_kernel, "collect only kernel level data"), + OPT_UINTEGER('l', "ldlat", &perf_mem_events__loads_ldlat, "setup mem-loads latency"), + OPT_PARENT(c2c_options), + OPT_END() + }; + + if (perf_mem_events__init()) { + pr_err("failed: memory events not supported\n"); + return -1; + } + + argc = parse_options(argc, argv, options, record_mem_usage, + PARSE_OPT_KEEP_UNKNOWN); + + rec_argc = argc + 10; /* max number of arguments */ + rec_argv = calloc(rec_argc + 1, sizeof(char *)); + if (!rec_argv) + return -1; + + rec_argv[i++] = "record"; + + if (!event_set) { + perf_mem_events[PERF_MEM_EVENTS__LOAD].record = true; + perf_mem_events[PERF_MEM_EVENTS__STORE].record = true; + } + + if (perf_mem_events[PERF_MEM_EVENTS__LOAD].record) + rec_argv[i++] = "-W"; + + rec_argv[i++] = "-d"; + rec_argv[i++] = "--sample-cpu"; + + for (j = 0; j < PERF_MEM_EVENTS__MAX; j++) { + if (!perf_mem_events[j].record) + continue; + + if (!perf_mem_events[j].supported) { + pr_err("failed: event '%s' not supported\n", + perf_mem_events[j].name); + return -1; + } + + rec_argv[i++] = "-e"; + rec_argv[i++] = perf_mem_events__name(j); + }; + + if (all_user) + rec_argv[i++] = "--all-user"; + + if (all_kernel) + rec_argv[i++] = "--all-kernel"; + + for (j = 0; j < argc; j++, i++) + rec_argv[i] = argv[j]; + + if (verbose > 0) { + pr_debug("calling: "); + + j = 0; + + while (rec_argv[j]) { + pr_debug("%s ", rec_argv[j]); + j++; + } + pr_debug("\n"); + } + + ret = cmd_record(i, rec_argv, NULL); + free(rec_argv); + return ret; +} + +int cmd_c2c(int argc, const char **argv, const char *prefix __maybe_unused) +{ + argc = parse_options(argc, argv, c2c_options, c2c_usage, + PARSE_OPT_STOP_AT_NON_OPTION); + + if (!argc) + usage_with_options(c2c_usage, c2c_options); + + if (!strncmp(argv[0], "rec", 3)) { + return perf_c2c__record(argc, argv); + } else if (!strncmp(argv[0], "rep", 3)) { + return perf_c2c__report(argc, argv); + } else { + usage_with_options(c2c_usage, c2c_options); + } + + return 0; +} diff --git a/tools/perf/builtin-config.c b/tools/perf/builtin-config.c index e4207a23b52c..8c0d93b7c2f0 100644 --- a/tools/perf/builtin-config.c +++ b/tools/perf/builtin-config.c @@ -17,7 +17,7 @@ static bool use_system_config, use_user_config; static const char * const config_usage[] = { - "perf config [<file-option>] [options]", + "perf config [<file-option>] [options] [section.name[=value] ...]", NULL }; @@ -33,6 +33,73 @@ static struct option config_options[] = { OPT_END() }; +static int set_config(struct perf_config_set *set, const char *file_name, + const char *var, const char *value) +{ + struct perf_config_section *section = NULL; + struct perf_config_item *item = NULL; + const char *first_line = "# this file is auto-generated."; + FILE *fp; + + if (set == NULL) + return -1; + + fp = fopen(file_name, "w"); + if (!fp) + return -1; + + perf_config_set__collect(set, file_name, var, value); + fprintf(fp, "%s\n", first_line); + + /* overwrite configvariables */ + perf_config_items__for_each_entry(&set->sections, section) { + if (!use_system_config && section->from_system_config) + continue; + fprintf(fp, "[%s]\n", section->name); + + perf_config_items__for_each_entry(§ion->items, item) { + if (!use_system_config && section->from_system_config) + continue; + if (item->value) + fprintf(fp, "\t%s = %s\n", + item->name, item->value); + } + } + fclose(fp); + + return 0; +} + +static int show_spec_config(struct perf_config_set *set, const char *var) +{ + struct perf_config_section *section; + struct perf_config_item *item; + + if (set == NULL) + return -1; + + perf_config_items__for_each_entry(&set->sections, section) { + if (prefixcmp(var, section->name) != 0) + continue; + + perf_config_items__for_each_entry(§ion->items, item) { + const char *name = var + strlen(section->name) + 1; + + if (strcmp(name, item->name) == 0) { + char *value = item->value; + + if (value) { + printf("%s=%s\n", var, value); + return 0; + } + } + + } + } + + return 0; +} + static int show_config(struct perf_config_set *set) { struct perf_config_section *section; @@ -52,9 +119,44 @@ static int show_config(struct perf_config_set *set) return 0; } +static int parse_config_arg(char *arg, char **var, char **value) +{ + const char *last_dot = strchr(arg, '.'); + + /* + * Since "var" actually contains the section name and the real + * config variable name separated by a dot, we have to know where the dot is. + */ + if (last_dot == NULL || last_dot == arg) { + pr_err("The config variable does not contain a section name: %s\n", arg); + return -1; + } + if (!last_dot[1]) { + pr_err("The config variable does not contain a variable name: %s\n", arg); + return -1; + } + + *value = strchr(arg, '='); + if (*value == NULL) + *var = arg; + else if (!strcmp(*value, "=")) { + pr_err("The config variable does not contain a value: %s\n", arg); + return -1; + } else { + *value = *value + 1; /* excluding a first character '=' */ + *var = strsep(&arg, "="); + if (*var[0] == '\0') { + pr_err("invalid config variable: %s\n", arg); + return -1; + } + } + + return 0; +} + int cmd_config(int argc, const char **argv, const char *prefix __maybe_unused) { - int ret = 0; + int i, ret = 0; struct perf_config_set *set; char *user_config = mkpath("%s/.perfconfig", getenv("HOME")); @@ -100,7 +202,36 @@ int cmd_config(int argc, const char **argv, const char *prefix __maybe_unused) } break; default: - usage_with_options(config_usage, config_options); + if (argc) { + for (i = 0; argv[i]; i++) { + char *var, *value; + char *arg = strdup(argv[i]); + + if (!arg) { + pr_err("%s: strdup failed\n", __func__); + ret = -1; + break; + } + + if (parse_config_arg(arg, &var, &value) < 0) { + free(arg); + ret = -1; + break; + } + + if (value == NULL) + ret = show_spec_config(set, var); + else { + const char *config_filename = config_exclusive_filename; + + if (!config_exclusive_filename) + config_filename = user_config; + ret = set_config(set, config_filename, var, value); + } + free(arg); + } + } else + usage_with_options(config_usage, config_options); } perf_config_set__delete(set); diff --git a/tools/perf/builtin-kmem.c b/tools/perf/builtin-kmem.c index d426dcb18ce9..35a02f8e5a4a 100644 --- a/tools/perf/builtin-kmem.c +++ b/tools/perf/builtin-kmem.c @@ -11,6 +11,7 @@ #include "util/session.h" #include "util/tool.h" #include "util/callchain.h" +#include "util/time-utils.h" #include <subcmd/parse-options.h> #include "util/trace-event.h" @@ -49,6 +50,7 @@ struct alloc_stat { u64 ptr; u64 bytes_req; u64 bytes_alloc; + u64 last_alloc; u32 hit; u32 pingpong; @@ -62,9 +64,13 @@ static struct rb_root root_alloc_sorted; static struct rb_root root_caller_stat; static struct rb_root root_caller_sorted; -static unsigned long total_requested, total_allocated; +static unsigned long total_requested, total_allocated, total_freed; static unsigned long nr_allocs, nr_cross_allocs; +/* filters for controlling start and stop of time of analysis */ +static struct perf_time_interval ptime; +const char *time_str; + static int insert_alloc_stat(unsigned long call_site, unsigned long ptr, int bytes_req, int bytes_alloc, int cpu) { @@ -105,6 +111,8 @@ static int insert_alloc_stat(unsigned long call_site, unsigned long ptr, } data->call_site = call_site; data->alloc_cpu = cpu; + data->last_alloc = bytes_alloc; + return 0; } @@ -223,6 +231,8 @@ static int perf_evsel__process_free_event(struct perf_evsel *evsel, if (!s_alloc) return 0; + total_freed += s_alloc->last_alloc; + if ((short)sample->cpu != s_alloc->alloc_cpu) { s_alloc->pingpong++; @@ -907,6 +917,15 @@ static int perf_evsel__process_page_free_event(struct perf_evsel *evsel, return 0; } +static bool perf_kmem__skip_sample(struct perf_sample *sample) +{ + /* skip sample based on time? */ + if (perf_time__skip_sample(&ptime, sample->time)) + return true; + + return false; +} + typedef int (*tracepoint_handler)(struct perf_evsel *evsel, struct perf_sample *sample); @@ -926,6 +945,9 @@ static int process_sample_event(struct perf_tool *tool __maybe_unused, return -1; } + if (perf_kmem__skip_sample(sample)) + return 0; + dump_printf(" ... thread: %s:%d\n", thread__comm_str(thread), thread->tid); if (evsel->handler != NULL) { @@ -1128,6 +1150,11 @@ static void print_slab_summary(void) printf("\n========================\n"); printf("Total bytes requested: %'lu\n", total_requested); printf("Total bytes allocated: %'lu\n", total_allocated); + printf("Total bytes freed: %'lu\n", total_freed); + if (total_allocated > total_freed) { + printf("Net total bytes allocated: %'lu\n", + total_allocated - total_freed); + } printf("Total bytes wasted on internal fragmentation: %'lu\n", total_allocated - total_requested); printf("Internal fragmentation: %f%%\n", @@ -1884,6 +1911,8 @@ int cmd_kmem(int argc, const char **argv, const char *prefix __maybe_unused) OPT_CALLBACK_NOOPT(0, "page", NULL, NULL, "Analyze page allocator", parse_page_opt), OPT_BOOLEAN(0, "live", &live_page, "Show live page stat"), + OPT_STRING(0, "time", &time_str, "str", + "Time span of interest (start,stop)"), OPT_END() }; const char *const kmem_subcommands[] = { "record", "stat", NULL }; @@ -1944,6 +1973,11 @@ int cmd_kmem(int argc, const char **argv, const char *prefix __maybe_unused) symbol__init(&session->header.env); + if (perf_time__parse_str(&ptime, time_str) != 0) { + pr_err("Invalid time string\n"); + return -EINVAL; + } + if (!strcmp(argv[0], "stat")) { setlocale(LC_ALL, ""); diff --git a/tools/perf/builtin-record.c b/tools/perf/builtin-record.c index 67d2a9003294..fa26865364b6 100644 --- a/tools/perf/builtin-record.c +++ b/tools/perf/builtin-record.c @@ -37,6 +37,7 @@ #include "util/llvm-utils.h" #include "util/bpf-loader.h" #include "util/trigger.h" +#include "util/perf-hooks.h" #include "asm/bug.h" #include <unistd.h> @@ -206,6 +207,12 @@ static void sig_handler(int sig) done = 1; } +static void sigsegv_handler(int sig) +{ + perf_hooks__recover(); + sighandler_dump_stack(sig); +} + static void record__sig_exit(void) { if (signr == -1) @@ -833,6 +840,7 @@ static int __cmd_record(struct record *rec, int argc, const char **argv) signal(SIGCHLD, sig_handler); signal(SIGINT, sig_handler); signal(SIGTERM, sig_handler); + signal(SIGSEGV, sigsegv_handler); if (rec->opts.auxtrace_snapshot_mode || rec->switch_output) { signal(SIGUSR2, snapshot_sig_handler); @@ -970,6 +978,7 @@ static int __cmd_record(struct record *rec, int argc, const char **argv) trigger_ready(&auxtrace_snapshot_trigger); trigger_ready(&switch_output_trigger); + perf_hooks__invoke_record_start(); for (;;) { unsigned long long hits = rec->samples; @@ -1114,6 +1123,8 @@ out_child: } } + perf_hooks__invoke_record_end(); + if (!err && !quiet) { char samples[128]; const char *postfix = rec->timestamp_filename ? diff --git a/tools/perf/builtin-report.c b/tools/perf/builtin-report.c index 6e88460cd13d..d2afbe4a240d 100644 --- a/tools/perf/builtin-report.c +++ b/tools/perf/builtin-report.c @@ -36,7 +36,7 @@ #include "util/hist.h" #include "util/data.h" #include "arch/common.h" - +#include "util/time-utils.h" #include "util/auxtrace.h" #include <dlfcn.h> @@ -59,6 +59,8 @@ struct report { const char *pretty_printing_style; const char *cpu_list; const char *symbol_filter_str; + const char *time_str; + struct perf_time_interval ptime; float min_percent; u64 nr_entries; u64 queue_size; @@ -158,6 +160,9 @@ static int process_sample_event(struct perf_tool *tool, }; int ret = 0; + if (perf_time__skip_sample(&rep->ptime, sample->time)) + return 0; + if (machine__resolve(machine, &al, sample) < 0) { pr_debug("problem processing %d event, skipping it.\n", event->header.type); @@ -207,11 +212,14 @@ static int process_read_event(struct perf_tool *tool, if (rep->show_threads) { const char *name = evsel ? perf_evsel__name(evsel) : "unknown"; - perf_read_values_add_value(&rep->show_threads_values, + int err = perf_read_values_add_value(&rep->show_threads_values, event->read.pid, event->read.tid, event->read.id, name, event->read.value); + + if (err) + return err; } dump_printf(": %d %d %s %" PRIu64 "\n", event->read.pid, event->read.tid, @@ -539,8 +547,11 @@ static int __cmd_report(struct report *rep) } } - if (rep->show_threads) - perf_read_values_init(&rep->show_threads_values); + if (rep->show_threads) { + ret = perf_read_values_init(&rep->show_threads_values); + if (ret) + return ret; + } ret = report__setup_sample_type(rep); if (ret) { @@ -824,6 +835,8 @@ int cmd_report(int argc, const char **argv, const char *prefix __maybe_unused) OPT_CALLBACK_DEFAULT(0, "stdio-color", NULL, "mode", "'always' (default), 'never' or 'auto' only applicable to --stdio mode", stdio__config_color, "always"), + OPT_STRING(0, "time", &report.time_str, "str", + "Time span of interest (start,stop)"), OPT_END() }; struct perf_data_file file = { @@ -905,6 +918,9 @@ repeat: if (itrace_synth_opts.last_branch) has_br_stack = true; + if (has_br_stack && branch_call_mode) + symbol_conf.show_branchflag_count = true; + /* * Branch mode is a tristate: * -1 means default, so decide based on the file having branch data. @@ -1006,6 +1022,11 @@ repeat: if (symbol__init(&session->header.env) < 0) goto error; + if (perf_time__parse_str(&report.ptime, report.time_str) != 0) { + pr_err("Invalid time string\n"); + return -EINVAL; + } + sort__setup_elide(stdout); ret = __cmd_report(&report); diff --git a/tools/perf/builtin-sched.c b/tools/perf/builtin-sched.c index f5503ca22e1c..1a3f1be93372 100644 --- a/tools/perf/builtin-sched.c +++ b/tools/perf/builtin-sched.c @@ -13,12 +13,16 @@ #include "util/cloexec.h" #include "util/thread_map.h" #include "util/color.h" +#include "util/stat.h" +#include "util/callchain.h" +#include "util/time-utils.h" #include <subcmd/parse-options.h> #include "util/trace-event.h" #include "util/debug.h" +#include <linux/log2.h> #include <sys/prctl.h> #include <sys/resource.h> @@ -192,8 +196,45 @@ struct perf_sched { bool force; bool skip_merge; struct perf_sched_map map; + + /* options for timehist command */ + bool summary; + bool summary_only; + bool show_callchain; + unsigned int max_stack; + bool show_cpu_visual; + bool show_wakeups; + bool show_migrations; + u64 skipped_samples; + const char *time_str; + struct perf_time_interval ptime; +}; + +/* per thread run time data */ +struct thread_runtime { + u64 last_time; /* time of previous sched in/out event */ + u64 dt_run; /* run time */ + u64 dt_wait; /* time between CPU access (off cpu) */ + u64 dt_delay; /* time between wakeup and sched-in */ + u64 ready_to_run; /* time of wakeup */ + + struct stats run_stats; + u64 total_run_time; + + u64 migrations; +}; + +/* per event run time data */ +struct evsel_runtime { + u64 *last_time; /* time this event was last seen per cpu */ + u32 ncpu; /* highest cpu slot allocated */ }; +/* track idle times per cpu */ +static struct thread **idle_threads; +static int idle_max_cpu; +static char idle_comm[] = "<idle>"; + static u64 get_nsecs(void) { struct timespec ts; @@ -1191,6 +1232,7 @@ static void output_lat_thread(struct perf_sched *sched, struct work_atoms *work_ int i; int ret; u64 avg; + char max_lat_at[32]; if (!work_list->nb_atoms) return; @@ -1212,12 +1254,13 @@ static void output_lat_thread(struct perf_sched *sched, struct work_atoms *work_ printf(" "); avg = work_list->total_lat / work_list->nb_atoms; + timestamp__scnprintf_usec(work_list->max_lat_at, max_lat_at, sizeof(max_lat_at)); - printf("|%11.3f ms |%9" PRIu64 " | avg:%9.3f ms | max:%9.3f ms | max at: %13.6f s\n", + printf("|%11.3f ms |%9" PRIu64 " | avg:%9.3f ms | max:%9.3f ms | max at: %13s s\n", (double)work_list->total_runtime / NSEC_PER_MSEC, work_list->nb_atoms, (double)avg / NSEC_PER_MSEC, (double)work_list->max_lat / NSEC_PER_MSEC, - (double)work_list->max_lat_at / NSEC_PER_SEC); + max_lat_at); } static int pid_cmp(struct work_atoms *l, struct work_atoms *r) @@ -1402,6 +1445,7 @@ static int map_switch_event(struct perf_sched *sched, struct perf_evsel *evsel, int cpus_nr; bool new_cpu = false; const char *color = PERF_COLOR_NORMAL; + char stimestamp[32]; BUG_ON(this_cpu >= MAX_CPUS || this_cpu < 0); @@ -1479,7 +1523,7 @@ static int map_switch_event(struct perf_sched *sched, struct perf_evsel *evsel, cpu_color = COLOR_CPUS; if (cpu != this_cpu) - color_fprintf(stdout, cpu_color, " "); + color_fprintf(stdout, color, " "); else color_fprintf(stdout, cpu_color, "*"); @@ -1492,8 +1536,9 @@ static int map_switch_event(struct perf_sched *sched, struct perf_evsel *evsel, if (sched->map.cpus && !cpu_map__has(sched->map.cpus, this_cpu)) goto out; - color_fprintf(stdout, color, " %12.6f secs ", (double)timestamp / NSEC_PER_SEC); - if (new_shortname) { + timestamp__scnprintf_usec(timestamp, stimestamp, sizeof(stimestamp)); + color_fprintf(stdout, color, " %12s secs ", stimestamp); + if (new_shortname || (verbose && sched_in->tid)) { const char *pid_color = color; if (thread__has_color(sched_in)) @@ -1650,6 +1695,988 @@ out_delete: return rc; } +/* + * scheduling times are printed as msec.usec + */ +static inline void print_sched_time(unsigned long long nsecs, int width) +{ + unsigned long msecs; + unsigned long usecs; + + msecs = nsecs / NSEC_PER_MSEC; + nsecs -= msecs * NSEC_PER_MSEC; + usecs = nsecs / NSEC_PER_USEC; + printf("%*lu.%03lu ", width, msecs, usecs); +} + +/* + * returns runtime data for event, allocating memory for it the + * first time it is used. + */ +static struct evsel_runtime *perf_evsel__get_runtime(struct perf_evsel *evsel) +{ + struct evsel_runtime *r = evsel->priv; + + if (r == NULL) { + r = zalloc(sizeof(struct evsel_runtime)); + evsel->priv = r; + } + + return r; +} + +/* + * save last time event was seen per cpu + */ +static void perf_evsel__save_time(struct perf_evsel *evsel, + u64 timestamp, u32 cpu) +{ + struct evsel_runtime *r = perf_evsel__get_runtime(evsel); + + if (r == NULL) + return; + + if ((cpu >= r->ncpu) || (r->last_time == NULL)) { + int i, n = __roundup_pow_of_two(cpu+1); + void *p = r->last_time; + + p = realloc(r->last_time, n * sizeof(u64)); + if (!p) + return; + + r->last_time = p; + for (i = r->ncpu; i < n; ++i) + r->last_time[i] = (u64) 0; + + r->ncpu = n; + } + + r->last_time[cpu] = timestamp; +} + +/* returns last time this event was seen on the given cpu */ +static u64 perf_evsel__get_time(struct perf_evsel *evsel, u32 cpu) +{ + struct evsel_runtime *r = perf_evsel__get_runtime(evsel); + + if ((r == NULL) || (r->last_time == NULL) || (cpu >= r->ncpu)) + return 0; + + return r->last_time[cpu]; +} + +static int comm_width = 20; + +static char *timehist_get_commstr(struct thread *thread) +{ + static char str[32]; + const char *comm = thread__comm_str(thread); + pid_t tid = thread->tid; + pid_t pid = thread->pid_; + int n; + + if (pid == 0) + n = scnprintf(str, sizeof(str), "%s", comm); + + else if (tid != pid) + n = scnprintf(str, sizeof(str), "%s[%d/%d]", comm, tid, pid); + + else + n = scnprintf(str, sizeof(str), "%s[%d]", comm, tid); + + if (n > comm_width) + comm_width = n; + + return str; +} + +static void timehist_header(struct perf_sched *sched) +{ + u32 ncpus = sched->max_cpu + 1; + u32 i, j; + + printf("%15s %6s ", "time", "cpu"); + + if (sched->show_cpu_visual) { + printf(" "); + for (i = 0, j = 0; i < ncpus; ++i) { + printf("%x", j++); + if (j > 15) + j = 0; + } + printf(" "); + } + + printf(" %-20s %9s %9s %9s", + "task name", "wait time", "sch delay", "run time"); + + printf("\n"); + + /* + * units row + */ + printf("%15s %-6s ", "", ""); + + if (sched->show_cpu_visual) + printf(" %*s ", ncpus, ""); + + printf(" %-20s %9s %9s %9s\n", "[tid/pid]", "(msec)", "(msec)", "(msec)"); + + /* + * separator + */ + printf("%.15s %.6s ", graph_dotted_line, graph_dotted_line); + + if (sched->show_cpu_visual) + printf(" %.*s ", ncpus, graph_dotted_line); + + printf(" %.20s %.9s %.9s %.9s", + graph_dotted_line, graph_dotted_line, graph_dotted_line, + graph_dotted_line); + + printf("\n"); +} + +static void timehist_print_sample(struct perf_sched *sched, + struct perf_sample *sample, + struct addr_location *al, + struct thread *thread, + u64 t) +{ + struct thread_runtime *tr = thread__priv(thread); + u32 max_cpus = sched->max_cpu + 1; + char tstr[64]; + + timestamp__scnprintf_usec(t, tstr, sizeof(tstr)); + printf("%15s [%04d] ", tstr, sample->cpu); + + if (sched->show_cpu_visual) { + u32 i; + char c; + + printf(" "); + for (i = 0; i < max_cpus; ++i) { + /* flag idle times with 'i'; others are sched events */ + if (i == sample->cpu) + c = (thread->tid == 0) ? 'i' : 's'; + else + c = ' '; + printf("%c", c); + } + printf(" "); + } + + printf(" %-*s ", comm_width, timehist_get_commstr(thread)); + + print_sched_time(tr->dt_wait, 6); + print_sched_time(tr->dt_delay, 6); + print_sched_time(tr->dt_run, 6); + + if (sched->show_wakeups) + printf(" %-*s", comm_width, ""); + + if (thread->tid == 0) + goto out; + + if (sched->show_callchain) + printf(" "); + + sample__fprintf_sym(sample, al, 0, + EVSEL__PRINT_SYM | EVSEL__PRINT_ONELINE | + EVSEL__PRINT_CALLCHAIN_ARROW | + EVSEL__PRINT_SKIP_IGNORED, + &callchain_cursor, stdout); + +out: + printf("\n"); +} + +/* + * Explanation of delta-time stats: + * + * t = time of current schedule out event + * tprev = time of previous sched out event + * also time of schedule-in event for current task + * last_time = time of last sched change event for current task + * (i.e, time process was last scheduled out) + * ready_to_run = time of wakeup for current task + * + * -----|------------|------------|------------|------ + * last ready tprev t + * time to run + * + * |-------- dt_wait --------| + * |- dt_delay -|-- dt_run --| + * + * dt_run = run time of current task + * dt_wait = time between last schedule out event for task and tprev + * represents time spent off the cpu + * dt_delay = time between wakeup and schedule-in of task + */ + +static void timehist_update_runtime_stats(struct thread_runtime *r, + u64 t, u64 tprev) +{ + r->dt_delay = 0; + r->dt_wait = 0; + r->dt_run = 0; + if (tprev) { + r->dt_run = t - tprev; + if (r->ready_to_run) { + if (r->ready_to_run > tprev) + pr_debug("time travel: wakeup time for task > previous sched_switch event\n"); + else + r->dt_delay = tprev - r->ready_to_run; + } + + if (r->last_time > tprev) + pr_debug("time travel: last sched out time for task > previous sched_switch event\n"); + else if (r->last_time) + r->dt_wait = tprev - r->last_time; + } + + update_stats(&r->run_stats, r->dt_run); + r->total_run_time += r->dt_run; +} + +static bool is_idle_sample(struct perf_sched *sched, + struct perf_sample *sample, + struct perf_evsel *evsel, + struct machine *machine) +{ + struct thread *thread; + struct callchain_cursor *cursor = &callchain_cursor; + + /* pid 0 == swapper == idle task */ + if (sample->pid == 0) + return true; + + if (strcmp(perf_evsel__name(evsel), "sched:sched_switch") == 0) { + if (perf_evsel__intval(evsel, sample, "prev_pid") == 0) + return true; + } + + /* want main thread for process - has maps */ + thread = machine__findnew_thread(machine, sample->pid, sample->pid); + if (thread == NULL) { + pr_debug("Failed to get thread for pid %d.\n", sample->pid); + return false; + } + + if (!symbol_conf.use_callchain || sample->callchain == NULL) + return false; + + if (thread__resolve_callchain(thread, cursor, evsel, sample, + NULL, NULL, sched->max_stack + 2) != 0) { + if (verbose) + error("Failed to resolve callchain. Skipping\n"); + + return false; + } + + callchain_cursor_commit(cursor); + + while (true) { + struct callchain_cursor_node *node; + struct symbol *sym; + + node = callchain_cursor_current(cursor); + if (node == NULL) + break; + + sym = node->sym; + if (sym && sym->name) { + if (!strcmp(sym->name, "schedule") || + !strcmp(sym->name, "__schedule") || + !strcmp(sym->name, "preempt_schedule")) + sym->ignore = 1; + } + + callchain_cursor_advance(cursor); + } + + return false; +} + +/* + * Track idle stats per cpu by maintaining a local thread + * struct for the idle task on each cpu. + */ +static int init_idle_threads(int ncpu) +{ + int i; + + idle_threads = zalloc(ncpu * sizeof(struct thread *)); + if (!idle_threads) + return -ENOMEM; + + idle_max_cpu = ncpu; + + /* allocate the actual thread struct if needed */ + for (i = 0; i < ncpu; ++i) { + idle_threads[i] = thread__new(0, 0); + if (idle_threads[i] == NULL) + return -ENOMEM; + + thread__set_comm(idle_threads[i], idle_comm, 0); + } + + return 0; +} + +static void free_idle_threads(void) +{ + int i; + + if (idle_threads == NULL) + return; + + for (i = 0; i < idle_max_cpu; ++i) { + if ((idle_threads[i])) + thread__delete(idle_threads[i]); + } + + free(idle_threads); +} + +static struct thread *get_idle_thread(int cpu) +{ + /* + * expand/allocate array of pointers to local thread + * structs if needed + */ + if ((cpu >= idle_max_cpu) || (idle_threads == NULL)) { + int i, j = __roundup_pow_of_two(cpu+1); + void *p; + + p = realloc(idle_threads, j * sizeof(struct thread *)); + if (!p) + return NULL; + + idle_threads = (struct thread **) p; + for (i = idle_max_cpu; i < j; ++i) + idle_threads[i] = NULL; + + idle_max_cpu = j; + } + + /* allocate a new thread struct if needed */ + if (idle_threads[cpu] == NULL) { + idle_threads[cpu] = thread__new(0, 0); + + if (idle_threads[cpu]) { + idle_threads[cpu]->tid = 0; + thread__set_comm(idle_threads[cpu], idle_comm, 0); + } + } + + return idle_threads[cpu]; +} + +/* + * handle runtime stats saved per thread + */ +static struct thread_runtime *thread__init_runtime(struct thread *thread) +{ + struct thread_runtime *r; + + r = zalloc(sizeof(struct thread_runtime)); + if (!r) + return NULL; + + init_stats(&r->run_stats); + thread__set_priv(thread, r); + + return r; +} + +static struct thread_runtime *thread__get_runtime(struct thread *thread) +{ + struct thread_runtime *tr; + + tr = thread__priv(thread); + if (tr == NULL) { + tr = thread__init_runtime(thread); + if (tr == NULL) + pr_debug("Failed to malloc memory for runtime data.\n"); + } + + return tr; +} + +static struct thread *timehist_get_thread(struct perf_sched *sched, + struct perf_sample *sample, + struct machine *machine, + struct perf_evsel *evsel) +{ + struct thread *thread; + + if (is_idle_sample(sched, sample, evsel, machine)) { + thread = get_idle_thread(sample->cpu); + if (thread == NULL) + pr_err("Failed to get idle thread for cpu %d.\n", sample->cpu); + + } else { + /* there were samples with tid 0 but non-zero pid */ + thread = machine__findnew_thread(machine, sample->pid, + sample->tid ?: sample->pid); + if (thread == NULL) { + pr_debug("Failed to get thread for tid %d. skipping sample.\n", + sample->tid); + } + } + + return thread; +} + +static bool timehist_skip_sample(struct perf_sched *sched, + struct thread *thread) +{ + bool rc = false; + + if (thread__is_filtered(thread)) { + rc = true; + sched->skipped_samples++; + } + + return rc; +} + +static void timehist_print_wakeup_event(struct perf_sched *sched, + struct perf_sample *sample, + struct machine *machine, + struct thread *awakened) +{ + struct thread *thread; + char tstr[64]; + + thread = machine__findnew_thread(machine, sample->pid, sample->tid); + if (thread == NULL) + return; + + /* show wakeup unless both awakee and awaker are filtered */ + if (timehist_skip_sample(sched, thread) && + timehist_skip_sample(sched, awakened)) { + return; + } + + timestamp__scnprintf_usec(sample->time, tstr, sizeof(tstr)); + printf("%15s [%04d] ", tstr, sample->cpu); + if (sched->show_cpu_visual) + printf(" %*s ", sched->max_cpu + 1, ""); + + printf(" %-*s ", comm_width, timehist_get_commstr(thread)); + + /* dt spacer */ + printf(" %9s %9s %9s ", "", "", ""); + + printf("awakened: %s", timehist_get_commstr(awakened)); + + printf("\n"); +} + +static int timehist_sched_wakeup_event(struct perf_tool *tool, + union perf_event *event __maybe_unused, + struct perf_evsel *evsel, + struct perf_sample *sample, + struct machine *machine) +{ + struct perf_sched *sched = container_of(tool, struct perf_sched, tool); + struct thread *thread; + struct thread_runtime *tr = NULL; + /* want pid of awakened task not pid in sample */ + const u32 pid = perf_evsel__intval(evsel, sample, "pid"); + + thread = machine__findnew_thread(machine, 0, pid); + if (thread == NULL) + return -1; + + tr = thread__get_runtime(thread); + if (tr == NULL) + return -1; + + if (tr->ready_to_run == 0) + tr->ready_to_run = sample->time; + + /* show wakeups if requested */ + if (sched->show_wakeups && + !perf_time__skip_sample(&sched->ptime, sample->time)) + timehist_print_wakeup_event(sched, sample, machine, thread); + + return 0; +} + +static void timehist_print_migration_event(struct perf_sched *sched, + struct perf_evsel *evsel, + struct perf_sample *sample, + struct machine *machine, + struct thread *migrated) +{ + struct thread *thread; + char tstr[64]; + u32 max_cpus = sched->max_cpu + 1; + u32 ocpu, dcpu; + + if (sched->summary_only) + return; + + max_cpus = sched->max_cpu + 1; + ocpu = perf_evsel__intval(evsel, sample, "orig_cpu"); + dcpu = perf_evsel__intval(evsel, sample, "dest_cpu"); + + thread = machine__findnew_thread(machine, sample->pid, sample->tid); + if (thread == NULL) + return; + + if (timehist_skip_sample(sched, thread) && + timehist_skip_sample(sched, migrated)) { + return; + } + + timestamp__scnprintf_usec(sample->time, tstr, sizeof(tstr)); + printf("%15s [%04d] ", tstr, sample->cpu); + + if (sched->show_cpu_visual) { + u32 i; + char c; + + printf(" "); + for (i = 0; i < max_cpus; ++i) { + c = (i == sample->cpu) ? 'm' : ' '; + printf("%c", c); + } + printf(" "); + } + + printf(" %-*s ", comm_width, timehist_get_commstr(thread)); + + /* dt spacer */ + printf(" %9s %9s %9s ", "", "", ""); + + printf("migrated: %s", timehist_get_commstr(migrated)); + printf(" cpu %d => %d", ocpu, dcpu); + + printf("\n"); +} + +static int timehist_migrate_task_event(struct perf_tool *tool, + union perf_event *event __maybe_unused, + struct perf_evsel *evsel, + struct perf_sample *sample, + struct machine *machine) +{ + struct perf_sched *sched = container_of(tool, struct perf_sched, tool); + struct thread *thread; + struct thread_runtime *tr = NULL; + /* want pid of migrated task not pid in sample */ + const u32 pid = perf_evsel__intval(evsel, sample, "pid"); + + thread = machine__findnew_thread(machine, 0, pid); + if (thread == NULL) + return -1; + + tr = thread__get_runtime(thread); + if (tr == NULL) + return -1; + + tr->migrations++; + + /* show migrations if requested */ + timehist_print_migration_event(sched, evsel, sample, machine, thread); + + return 0; +} + +static int timehist_sched_change_event(struct perf_tool *tool, + union perf_event *event, + struct perf_evsel *evsel, + struct perf_sample *sample, + struct machine *machine) +{ + struct perf_sched *sched = container_of(tool, struct perf_sched, tool); + struct perf_time_interval *ptime = &sched->ptime; + struct addr_location al; + struct thread *thread; + struct thread_runtime *tr = NULL; + u64 tprev, t = sample->time; + int rc = 0; + + if (machine__resolve(machine, &al, sample) < 0) { + pr_err("problem processing %d event. skipping it\n", + event->header.type); + rc = -1; + goto out; + } + + thread = timehist_get_thread(sched, sample, machine, evsel); + if (thread == NULL) { + rc = -1; + goto out; + } + + if (timehist_skip_sample(sched, thread)) + goto out; + + tr = thread__get_runtime(thread); + if (tr == NULL) { + rc = -1; + goto out; + } + + tprev = perf_evsel__get_time(evsel, sample->cpu); + + /* + * If start time given: + * - sample time is under window user cares about - skip sample + * - tprev is under window user cares about - reset to start of window + */ + if (ptime->start && ptime->start > t) + goto out; + + if (ptime->start > tprev) + tprev = ptime->start; + + /* + * If end time given: + * - previous sched event is out of window - we are done + * - sample time is beyond window user cares about - reset it + * to close out stats for time window interest + */ + if (ptime->end) { + if (tprev > ptime->end) + goto out; + + if (t > ptime->end) + t = ptime->end; + } + + timehist_update_runtime_stats(tr, t, tprev); + + if (!sched->summary_only) + timehist_print_sample(sched, sample, &al, thread, t); + +out: + if (tr) { + /* time of this sched_switch event becomes last time task seen */ + tr->last_time = sample->time; + + /* sched out event for task so reset ready to run time */ + tr->ready_to_run = 0; + } + + perf_evsel__save_time(evsel, sample->time, sample->cpu); + + return rc; +} + +static int timehist_sched_switch_event(struct perf_tool *tool, + union perf_event *event, + struct perf_evsel *evsel, + struct perf_sample *sample, + struct machine *machine __maybe_unused) +{ + return timehist_sched_change_event(tool, event, evsel, sample, machine); +} + +static int process_lost(struct perf_tool *tool __maybe_unused, + union perf_event *event, + struct perf_sample *sample, + struct machine *machine __maybe_unused) +{ + char tstr[64]; + + timestamp__scnprintf_usec(sample->time, tstr, sizeof(tstr)); + printf("%15s ", tstr); + printf("lost %" PRIu64 " events on cpu %d\n", event->lost.lost, sample->cpu); + + return 0; +} + + +static void print_thread_runtime(struct thread *t, + struct thread_runtime *r) +{ + double mean = avg_stats(&r->run_stats); + float stddev; + + printf("%*s %5d %9" PRIu64 " ", + comm_width, timehist_get_commstr(t), t->ppid, + (u64) r->run_stats.n); + + print_sched_time(r->total_run_time, 8); + stddev = rel_stddev_stats(stddev_stats(&r->run_stats), mean); + print_sched_time(r->run_stats.min, 6); + printf(" "); + print_sched_time((u64) mean, 6); + printf(" "); + print_sched_time(r->run_stats.max, 6); + printf(" "); + printf("%5.2f", stddev); + printf(" %5" PRIu64, r->migrations); + printf("\n"); +} + +struct total_run_stats { + u64 sched_count; + u64 task_count; + u64 total_run_time; +}; + +static int __show_thread_runtime(struct thread *t, void *priv) +{ + struct total_run_stats *stats = priv; + struct thread_runtime *r; + + if (thread__is_filtered(t)) + return 0; + + r = thread__priv(t); + if (r && r->run_stats.n) { + stats->task_count++; + stats->sched_count += r->run_stats.n; + stats->total_run_time += r->total_run_time; + print_thread_runtime(t, r); + } + + return 0; +} + +static int show_thread_runtime(struct thread *t, void *priv) +{ + if (t->dead) + return 0; + + return __show_thread_runtime(t, priv); +} + +static int show_deadthread_runtime(struct thread *t, void *priv) +{ + if (!t->dead) + return 0; + + return __show_thread_runtime(t, priv); +} + +static void timehist_print_summary(struct perf_sched *sched, + struct perf_session *session) +{ + struct machine *m = &session->machines.host; + struct total_run_stats totals; + u64 task_count; + struct thread *t; + struct thread_runtime *r; + int i; + + memset(&totals, 0, sizeof(totals)); + + if (comm_width < 30) + comm_width = 30; + + printf("\nRuntime summary\n"); + printf("%*s parent sched-in ", comm_width, "comm"); + printf(" run-time min-run avg-run max-run stddev migrations\n"); + printf("%*s (count) ", comm_width, ""); + printf(" (msec) (msec) (msec) (msec) %%\n"); + printf("%.117s\n", graph_dotted_line); + + machine__for_each_thread(m, show_thread_runtime, &totals); + task_count = totals.task_count; + if (!task_count) + printf("<no still running tasks>\n"); + + printf("\nTerminated tasks:\n"); + machine__for_each_thread(m, show_deadthread_runtime, &totals); + if (task_count == totals.task_count) + printf("<no terminated tasks>\n"); + + /* CPU idle stats not tracked when samples were skipped */ + if (sched->skipped_samples) + return; + + printf("\nIdle stats:\n"); + for (i = 0; i < idle_max_cpu; ++i) { + t = idle_threads[i]; + if (!t) + continue; + + r = thread__priv(t); + if (r && r->run_stats.n) { + totals.sched_count += r->run_stats.n; + printf(" CPU %2d idle for ", i); + print_sched_time(r->total_run_time, 6); + printf(" msec\n"); + } else + printf(" CPU %2d idle entire time window\n", i); + } + + printf("\n" + " Total number of unique tasks: %" PRIu64 "\n" + "Total number of context switches: %" PRIu64 "\n" + " Total run time (msec): ", + totals.task_count, totals.sched_count); + + print_sched_time(totals.total_run_time, 2); + printf("\n"); +} + +typedef int (*sched_handler)(struct perf_tool *tool, + union perf_event *event, + struct perf_evsel *evsel, + struct perf_sample *sample, + struct machine *machine); + +static int perf_timehist__process_sample(struct perf_tool *tool, + union perf_event *event, + struct perf_sample *sample, + struct perf_evsel *evsel, + struct machine *machine) +{ + struct perf_sched *sched = container_of(tool, struct perf_sched, tool); + int err = 0; + int this_cpu = sample->cpu; + + if (this_cpu > sched->max_cpu) + sched->max_cpu = this_cpu; + + if (evsel->handler != NULL) { + sched_handler f = evsel->handler; + + err = f(tool, event, evsel, sample, machine); + } + + return err; +} + +static int timehist_check_attr(struct perf_sched *sched, + struct perf_evlist *evlist) +{ + struct perf_evsel *evsel; + struct evsel_runtime *er; + + list_for_each_entry(evsel, &evlist->entries, node) { + er = perf_evsel__get_runtime(evsel); + if (er == NULL) { + pr_err("Failed to allocate memory for evsel runtime data\n"); + return -1; + } + + if (sched->show_callchain && + !(evsel->attr.sample_type & PERF_SAMPLE_CALLCHAIN)) { + pr_info("Samples do not have callchains.\n"); + sched->show_callchain = 0; + symbol_conf.use_callchain = 0; + } + } + + return 0; +} + +static int perf_sched__timehist(struct perf_sched *sched) +{ + const struct perf_evsel_str_handler handlers[] = { + { "sched:sched_switch", timehist_sched_switch_event, }, + { "sched:sched_wakeup", timehist_sched_wakeup_event, }, + { "sched:sched_wakeup_new", timehist_sched_wakeup_event, }, + }; + const struct perf_evsel_str_handler migrate_handlers[] = { + { "sched:sched_migrate_task", timehist_migrate_task_event, }, + }; + struct perf_data_file file = { + .path = input_name, + .mode = PERF_DATA_MODE_READ, + .force = sched->force, + }; + + struct perf_session *session; + struct perf_evlist *evlist; + int err = -1; + + /* + * event handlers for timehist option + */ + sched->tool.sample = perf_timehist__process_sample; + sched->tool.mmap = perf_event__process_mmap; + sched->tool.comm = perf_event__process_comm; + sched->tool.exit = perf_event__process_exit; + sched->tool.fork = perf_event__process_fork; + sched->tool.lost = process_lost; + sched->tool.attr = perf_event__process_attr; + sched->tool.tracing_data = perf_event__process_tracing_data; + sched->tool.build_id = perf_event__process_build_id; + + sched->tool.ordered_events = true; + sched->tool.ordering_requires_timestamps = true; + + symbol_conf.use_callchain = sched->show_callchain; + + session = perf_session__new(&file, false, &sched->tool); + if (session == NULL) + return -ENOMEM; + + evlist = session->evlist; + + symbol__init(&session->header.env); + + if (perf_time__parse_str(&sched->ptime, sched->time_str) != 0) { + pr_err("Invalid time string\n"); + return -EINVAL; + } + + if (timehist_check_attr(sched, evlist) != 0) + goto out; + + setup_pager(); + + /* setup per-evsel handlers */ + if (perf_session__set_tracepoints_handlers(session, handlers)) + goto out; + + /* sched_switch event at a minimum needs to exist */ + if (!perf_evlist__find_tracepoint_by_name(session->evlist, + "sched:sched_switch")) { + pr_err("No sched_switch events found. Have you run 'perf sched record'?\n"); + goto out; + } + + if (sched->show_migrations && + perf_session__set_tracepoints_handlers(session, migrate_handlers)) + goto out; + + /* pre-allocate struct for per-CPU idle stats */ + sched->max_cpu = session->header.env.nr_cpus_online; + if (sched->max_cpu == 0) + sched->max_cpu = 4; + if (init_idle_threads(sched->max_cpu)) + goto out; + + /* summary_only implies summary option, but don't overwrite summary if set */ + if (sched->summary_only) + sched->summary = sched->summary_only; + + if (!sched->summary_only) + timehist_header(sched); + + err = perf_session__process_events(session); + if (err) { + pr_err("Failed to process events, error %d", err); + goto out; + } + + sched->nr_events = evlist->stats.nr_events[0]; + sched->nr_lost_events = evlist->stats.total_lost; + sched->nr_lost_chunks = evlist->stats.nr_events[PERF_RECORD_LOST]; + + if (sched->summary) + timehist_print_summary(sched, session); + +out: + free_idle_threads(); + perf_session__delete(session); + + return err; +} + + static void print_bad_events(struct perf_sched *sched) { if (sched->nr_unordered_timestamps && sched->nr_timestamps) { @@ -1953,38 +2980,32 @@ int cmd_sched(int argc, const char **argv, const char *prefix __maybe_unused) .next_shortname1 = 'A', .next_shortname2 = '0', .skip_merge = 0, + .show_callchain = 1, + .max_stack = 5, + }; + const struct option sched_options[] = { + OPT_STRING('i', "input", &input_name, "file", + "input file name"), + OPT_INCR('v', "verbose", &verbose, + "be more verbose (show symbol address, etc)"), + OPT_BOOLEAN('D', "dump-raw-trace", &dump_trace, + "dump raw trace in ASCII"), + OPT_BOOLEAN('f', "force", &sched.force, "don't complain, do it"), + OPT_END() }; const struct option latency_options[] = { OPT_STRING('s', "sort", &sched.sort_order, "key[,key2...]", "sort by key(s): runtime, switch, avg, max"), - OPT_INCR('v', "verbose", &verbose, - "be more verbose (show symbol address, etc)"), OPT_INTEGER('C', "CPU", &sched.profile_cpu, "CPU to profile on"), - OPT_BOOLEAN('D', "dump-raw-trace", &dump_trace, - "dump raw trace in ASCII"), OPT_BOOLEAN('p', "pids", &sched.skip_merge, "latency stats per pid instead of per comm"), - OPT_END() + OPT_PARENT(sched_options) }; const struct option replay_options[] = { OPT_UINTEGER('r', "repeat", &sched.replay_repeat, "repeat the workload replay N times (-1: infinite)"), - OPT_INCR('v', "verbose", &verbose, - "be more verbose (show symbol address, etc)"), - OPT_BOOLEAN('D', "dump-raw-trace", &dump_trace, - "dump raw trace in ASCII"), - OPT_BOOLEAN('f', "force", &sched.force, "don't complain, do it"), - OPT_END() - }; - const struct option sched_options[] = { - OPT_STRING('i', "input", &input_name, "file", - "input file name"), - OPT_INCR('v', "verbose", &verbose, - "be more verbose (show symbol address, etc)"), - OPT_BOOLEAN('D', "dump-raw-trace", &dump_trace, - "dump raw trace in ASCII"), - OPT_END() + OPT_PARENT(sched_options) }; const struct option map_options[] = { OPT_BOOLEAN(0, "compact", &sched.map.comp, @@ -1995,8 +3016,31 @@ int cmd_sched(int argc, const char **argv, const char *prefix __maybe_unused) "highlight given CPUs in map"), OPT_STRING(0, "cpus", &sched.map.cpus_str, "cpus", "display given CPUs in map"), - OPT_END() + OPT_PARENT(sched_options) }; + const struct option timehist_options[] = { + OPT_STRING('k', "vmlinux", &symbol_conf.vmlinux_name, + "file", "vmlinux pathname"), + OPT_STRING(0, "kallsyms", &symbol_conf.kallsyms_name, + "file", "kallsyms pathname"), + OPT_BOOLEAN('g', "call-graph", &sched.show_callchain, + "Display call chains if present (default on)"), + OPT_UINTEGER(0, "max-stack", &sched.max_stack, + "Maximum number of functions to display backtrace."), + OPT_STRING(0, "symfs", &symbol_conf.symfs, "directory", + "Look for files with symbols relative to this directory"), + OPT_BOOLEAN('s', "summary", &sched.summary_only, + "Show only syscall summary with statistics"), + OPT_BOOLEAN('S', "with-summary", &sched.summary, + "Show all syscalls and summary with statistics"), + OPT_BOOLEAN('w', "wakeups", &sched.show_wakeups, "Show wakeup events"), + OPT_BOOLEAN('M', "migrations", &sched.show_migrations, "Show migration events"), + OPT_BOOLEAN('V', "cpu-visual", &sched.show_cpu_visual, "Add CPU visual"), + OPT_STRING(0, "time", &sched.time_str, "str", + "Time span for analysis (start,stop)"), + OPT_PARENT(sched_options) + }; + const char * const latency_usage[] = { "perf sched latency [<options>]", NULL @@ -2009,8 +3053,13 @@ int cmd_sched(int argc, const char **argv, const char *prefix __maybe_unused) "perf sched map [<options>]", NULL }; + const char * const timehist_usage[] = { + "perf sched timehist [<options>]", + NULL + }; const char *const sched_subcommands[] = { "record", "latency", "map", - "replay", "script", NULL }; + "replay", "script", + "timehist", NULL }; const char *sched_usage[] = { NULL, NULL @@ -2073,6 +3122,21 @@ int cmd_sched(int argc, const char **argv, const char *prefix __maybe_unused) usage_with_options(replay_usage, replay_options); } return perf_sched__replay(&sched); + } else if (!strcmp(argv[0], "timehist")) { + if (argc) { + argc = parse_options(argc, argv, timehist_options, + timehist_usage, 0); + if (argc) + usage_with_options(timehist_usage, timehist_options); + } + if (sched.show_wakeups && sched.summary_only) { + pr_err(" Error: -s and -w are mutually exclusive.\n"); + parse_options_usage(timehist_usage, timehist_options, "s", true); + parse_options_usage(NULL, timehist_options, "w", true); + return -EINVAL; + } + + return perf_sched__timehist(&sched); } else { usage_with_options(sched_usage, sched_options); } diff --git a/tools/perf/builtin-script.c b/tools/perf/builtin-script.c index 7228d141a789..2f3ff69fc4e7 100644 --- a/tools/perf/builtin-script.c +++ b/tools/perf/builtin-script.c @@ -22,6 +22,7 @@ #include "util/thread_map.h" #include "util/stat.h" #include "util/thread-stack.h" +#include "util/time-utils.h" #include <linux/bitmap.h> #include <linux/stringify.h> #include <linux/time64.h> @@ -66,6 +67,8 @@ enum perf_output_field { PERF_OUTPUT_WEIGHT = 1U << 18, PERF_OUTPUT_BPF_OUTPUT = 1U << 19, PERF_OUTPUT_CALLINDENT = 1U << 20, + PERF_OUTPUT_INSN = 1U << 21, + PERF_OUTPUT_INSNLEN = 1U << 22, }; struct output_option { @@ -93,6 +96,8 @@ struct output_option { {.str = "weight", .field = PERF_OUTPUT_WEIGHT}, {.str = "bpf-output", .field = PERF_OUTPUT_BPF_OUTPUT}, {.str = "callindent", .field = PERF_OUTPUT_CALLINDENT}, + {.str = "insn", .field = PERF_OUTPUT_INSN}, + {.str = "insnlen", .field = PERF_OUTPUT_INSNLEN}, }; /* default set to maintain compatibility with current format */ @@ -437,7 +442,6 @@ static void print_sample_start(struct perf_sample *sample, { struct perf_event_attr *attr = &evsel->attr; unsigned long secs; - unsigned long usecs; unsigned long long nsecs; if (PRINT_FIELD(COMM)) { @@ -467,11 +471,14 @@ static void print_sample_start(struct perf_sample *sample, nsecs = sample->time; secs = nsecs / NSEC_PER_SEC; nsecs -= secs * NSEC_PER_SEC; - usecs = nsecs / NSEC_PER_USEC; + if (nanosecs) printf("%5lu.%09llu: ", secs, nsecs); - else - printf("%5lu.%06lu: ", secs, usecs); + else { + char sample_time[32]; + timestamp__scnprintf_usec(sample->time, sample_time, sizeof(sample_time)); + printf("%12s: ", sample_time); + } } } @@ -624,6 +631,20 @@ static void print_sample_callindent(struct perf_sample *sample, printf("%*s", spacing - len, ""); } +static void print_insn(struct perf_sample *sample, + struct perf_event_attr *attr) +{ + if (PRINT_FIELD(INSNLEN)) + printf(" ilen: %d", sample->insn_len); + if (PRINT_FIELD(INSN)) { + int i; + + printf(" insn:"); + for (i = 0; i < sample->insn_len; i++) + printf(" %02x", (unsigned char)sample->insn[i]); + } +} + static void print_sample_bts(struct perf_sample *sample, struct perf_evsel *evsel, struct thread *thread, @@ -668,6 +689,8 @@ static void print_sample_bts(struct perf_sample *sample, if (print_srcline_last) map__fprintf_srcline(al->map, al->addr, "\n ", stdout); + print_insn(sample, attr); + printf("\n"); } @@ -811,6 +834,8 @@ struct perf_script { struct cpu_map *cpus; struct thread_map *threads; int name_width; + const char *time_str; + struct perf_time_interval ptime; }; static int perf_evlist__max_name_len(struct perf_evlist *evlist) @@ -911,7 +936,7 @@ static void process_event(struct perf_script *script, if (perf_evsel__is_bpf_output(evsel) && PRINT_FIELD(BPF_OUTPUT)) print_sample_bpf_output(sample); - + print_insn(sample, attr); printf("\n"); } @@ -992,6 +1017,9 @@ static int process_sample_event(struct perf_tool *tool, struct perf_script *scr = container_of(tool, struct perf_script, tool); struct addr_location al; + if (perf_time__skip_sample(&scr->ptime, sample->time)) + return 0; + if (debug_mode) { if (sample->time < last_timestamp) { pr_err("Samples misordered, previous: %" PRIu64 @@ -2124,11 +2152,13 @@ int cmd_script(int argc, const char **argv, const char *prefix __maybe_unused) "Valid types: hw,sw,trace,raw. " "Fields: comm,tid,pid,time,cpu,event,trace,ip,sym,dso," "addr,symoff,period,iregs,brstack,brstacksym,flags," - "bpf-output,callindent", parse_output_fields), + "bpf-output,callindent,insn,insnlen", parse_output_fields), OPT_BOOLEAN('a', "all-cpus", &system_wide, "system-wide collection from all CPUs"), OPT_STRING('S', "symbols", &symbol_conf.sym_list_str, "symbol[,symbol...]", "only consider these symbols"), + OPT_STRING(0, "stop-bt", &symbol_conf.bt_stop_list_str, "symbol[,symbol...]", + "Stop display of callgraph at these symbols"), OPT_STRING('C', "cpu", &cpu_list, "cpu", "list of cpus to profile"), OPT_STRING('c', "comms", &symbol_conf.comm_list_str, "comm[,comm...]", "only display events for these comms"), @@ -2162,7 +2192,8 @@ int cmd_script(int argc, const char **argv, const char *prefix __maybe_unused) "Enable symbol demangling"), OPT_BOOLEAN(0, "demangle-kernel", &symbol_conf.demangle_kernel, "Enable kernel symbol demangling"), - + OPT_STRING(0, "time", &script.time_str, "str", + "Time span of interest (start,stop)"), OPT_END() }; const char * const script_subcommands[] = { "record", "report", NULL }; @@ -2441,6 +2472,12 @@ int cmd_script(int argc, const char **argv, const char *prefix __maybe_unused) if (err < 0) goto out_delete; + /* needs to be parsed after looking up reference time */ + if (perf_time__parse_str(&script.ptime, script.time_str) != 0) { + pr_err("Invalid time string\n"); + return -EINVAL; + } + err = __cmd_script(&script); flush_scripting(); diff --git a/tools/perf/builtin-top.c b/tools/perf/builtin-top.c index fe3af9535e85..3df4178ba378 100644 --- a/tools/perf/builtin-top.c +++ b/tools/perf/builtin-top.c @@ -130,7 +130,7 @@ static int perf_top__parse_source(struct perf_top *top, struct hist_entry *he) return err; } - err = symbol__disassemble(sym, map, 0); + err = symbol__disassemble(sym, map, NULL, 0); if (err == 0) { out_assign: top->sym_filter_entry = he; diff --git a/tools/perf/builtin-trace.c b/tools/perf/builtin-trace.c index c298bd3e1d90..206bf72b77fc 100644 --- a/tools/perf/builtin-trace.c +++ b/tools/perf/builtin-trace.c @@ -74,8 +74,6 @@ struct trace { size_t nr; int *entries; } ev_qualifier_ids; - struct intlist *tid_list; - struct intlist *pid_list; struct { size_t nr; pid_t *entries; @@ -843,7 +841,6 @@ static size_t fprintf_duration(unsigned long t, FILE *fp) */ struct thread_trace { u64 entry_time; - u64 exit_time; bool entry_pending; unsigned long nr_events; unsigned long pfmaj, pfmin; @@ -1452,7 +1449,7 @@ static int trace__printf_interrupted_entry(struct trace *trace, struct perf_samp duration = sample->time - ttrace->entry_time; - printed = trace__fprintf_entry_head(trace, trace->current, duration, sample->time, trace->output); + printed = trace__fprintf_entry_head(trace, trace->current, duration, ttrace->entry_time, trace->output); printed += fprintf(trace->output, "%-70s) ...\n", ttrace->entry_str); ttrace->entry_pending = false; @@ -1499,7 +1496,7 @@ static int trace__sys_enter(struct trace *trace, struct perf_evsel *evsel, if (sc->is_exit) { if (!(trace->duration_filter || trace->summary_only || trace->min_stack)) { - trace__fprintf_entry_head(trace, thread, 1, sample->time, trace->output); + trace__fprintf_entry_head(trace, thread, 1, ttrace->entry_time, trace->output); fprintf(trace->output, "%-70s)\n", ttrace->entry_str); } } else { @@ -1571,8 +1568,6 @@ static int trace__sys_exit(struct trace *trace, struct perf_evsel *evsel, ++trace->stats.vfs_getname; } - ttrace->exit_time = sample->time; - if (ttrace->entry_time) { duration = sample->time - ttrace->entry_time; if (trace__filter_duration(trace, duration)) @@ -1592,7 +1587,7 @@ static int trace__sys_exit(struct trace *trace, struct perf_evsel *evsel, if (trace->summary_only) goto out; - trace__fprintf_entry_head(trace, thread, duration, sample->time, trace->output); + trace__fprintf_entry_head(trace, thread, duration, ttrace->entry_time, trace->output); if (ttrace->entry_pending) { fprintf(trace->output, "%-70s", ttrace->entry_str); @@ -1893,18 +1888,6 @@ out_put: return err; } -static bool skip_sample(struct trace *trace, struct perf_sample *sample) -{ - if ((trace->pid_list && intlist__find(trace->pid_list, sample->pid)) || - (trace->tid_list && intlist__find(trace->tid_list, sample->tid))) - return false; - - if (trace->pid_list || trace->tid_list) - return true; - - return false; -} - static void trace__set_base_time(struct trace *trace, struct perf_evsel *evsel, struct perf_sample *sample) @@ -1929,11 +1912,13 @@ static int trace__process_sample(struct perf_tool *tool, struct machine *machine __maybe_unused) { struct trace *trace = container_of(tool, struct trace, tool); + struct thread *thread; int err = 0; tracepoint_handler handler = evsel->handler; - if (skip_sample(trace, sample)) + thread = machine__findnew_thread(trace->host, sample->pid, sample->tid); + if (thread && thread__is_filtered(thread)) return 0; trace__set_base_time(trace, evsel, sample); @@ -1946,27 +1931,6 @@ static int trace__process_sample(struct perf_tool *tool, return err; } -static int parse_target_str(struct trace *trace) -{ - if (trace->opts.target.pid) { - trace->pid_list = intlist__new(trace->opts.target.pid); - if (trace->pid_list == NULL) { - pr_err("Error parsing process id string\n"); - return -EINVAL; - } - } - - if (trace->opts.target.tid) { - trace->tid_list = intlist__new(trace->opts.target.tid); - if (trace->tid_list == NULL) { - pr_err("Error parsing thread id string\n"); - return -EINVAL; - } - } - - return 0; -} - static int trace__record(struct trace *trace, int argc, const char **argv) { unsigned int rec_argc, i, j; @@ -2310,12 +2274,17 @@ static int trace__run(struct trace *trace, int argc, const char **argv) if (err < 0) goto out_error_mmap; - if (!target__none(&trace->opts.target)) + if (!target__none(&trace->opts.target) && !trace->opts.initial_delay) perf_evlist__enable(evlist); if (forks) perf_evlist__start_workload(evlist); + if (trace->opts.initial_delay) { + usleep(trace->opts.initial_delay * 1000); + perf_evlist__enable(evlist); + } + trace->multiple_threads = thread_map__pid(evlist->threads, 0) == -1 || evlist->threads->nr > 1 || perf_evlist__first(evlist)->attr.inherit; @@ -2458,6 +2427,12 @@ static int trace__replay(struct trace *trace) if (session == NULL) return -1; + if (trace->opts.target.pid) + symbol_conf.pid_list_str = strdup(trace->opts.target.pid); + + if (trace->opts.target.tid) + symbol_conf.tid_list_str = strdup(trace->opts.target.tid); + if (symbol__init(&session->header.env) < 0) goto out; @@ -2501,10 +2476,6 @@ static int trace__replay(struct trace *trace) evsel->handler = trace__pgfault; } - err = parse_target_str(trace); - if (err != 0) - goto out; - setup_pager(); err = perf_session__process_events(session); @@ -2816,6 +2787,9 @@ int cmd_trace(int argc, const char **argv, const char *prefix __maybe_unused) "Default: kernel.perf_event_max_stack or " __stringify(PERF_MAX_STACK_DEPTH)), OPT_UINTEGER(0, "proc-map-timeout", &trace.opts.proc_map_timeout, "per thread proc mmap processing timeout in ms"), + OPT_UINTEGER('D', "delay", &trace.opts.initial_delay, + "ms to wait before starting measurement after program " + "start"), OPT_END() }; bool __maybe_unused max_stack_user_set = true; diff --git a/tools/perf/builtin.h b/tools/perf/builtin.h index 41c24010ab43..0bcf68e98ccc 100644 --- a/tools/perf/builtin.h +++ b/tools/perf/builtin.h @@ -18,6 +18,7 @@ int cmd_bench(int argc, const char **argv, const char *prefix); int cmd_buildid_cache(int argc, const char **argv, const char *prefix); int cmd_buildid_list(int argc, const char **argv, const char *prefix); int cmd_config(int argc, const char **argv, const char *prefix); +int cmd_c2c(int argc, const char **argv, const char *prefix); int cmd_diff(int argc, const char **argv, const char *prefix); int cmd_evlist(int argc, const char **argv, const char *prefix); int cmd_help(int argc, const char **argv, const char *prefix); diff --git a/tools/perf/jvmti/Build b/tools/perf/jvmti/Build new file mode 100644 index 000000000000..eaeb8cb5379b --- /dev/null +++ b/tools/perf/jvmti/Build @@ -0,0 +1,8 @@ +jvmti-y += libjvmti.o +jvmti-y += jvmti_agent.o + +CFLAGS_jvmti = -fPIC -DPIC -I$(JDIR)/include -I$(JDIR)/include/linux +CFLAGS_REMOVE_jvmti = -Wmissing-declarations +CFLAGS_REMOVE_jvmti += -Wstrict-prototypes +CFLAGS_REMOVE_jvmti += -Wextra +CFLAGS_REMOVE_jvmti += -Wwrite-strings diff --git a/tools/perf/jvmti/Makefile b/tools/perf/jvmti/Makefile deleted file mode 100644 index df14e6b67b63..000000000000 --- a/tools/perf/jvmti/Makefile +++ /dev/null @@ -1,89 +0,0 @@ -ARCH=$(shell uname -m) - -ifeq ($(ARCH), x86_64) -JARCH=amd64 -endif -ifeq ($(ARCH), armv7l) -JARCH=armhf -endif -ifeq ($(ARCH), armv6l) -JARCH=armhf -endif -ifeq ($(ARCH), aarch64) -JARCH=aarch64 -endif -ifeq ($(ARCH), ppc64) -JARCH=powerpc -endif -ifeq ($(ARCH), ppc64le) -JARCH=powerpc -endif - -DESTDIR=/usr/local - -VERSION=1 -REVISION=0 -AGE=0 - -LN=ln -sf -RM=rm - -SLIBJVMTI=libjvmti.so.$(VERSION).$(REVISION).$(AGE) -VLIBJVMTI=libjvmti.so.$(VERSION) -SLDFLAGS=-shared -Wl,-soname -Wl,$(VLIBJVMTI) -SOLIBEXT=so - -# The following works at least on fedora 23, you may need the next -# line for other distros. -ifneq (,$(wildcard /usr/sbin/update-java-alternatives)) -JDIR=$(shell /usr/sbin/update-java-alternatives -l | head -1 | awk '{print $$3}') -else - ifneq (,$(wildcard /usr/sbin/alternatives)) - JDIR=$(shell alternatives --display java | tail -1 | cut -d' ' -f 5 | sed 's%/jre/bin/java.%%g') - endif -endif -ifndef JDIR -$(error Could not find alternatives command, you need to set JDIR= to point to the root of your Java directory) -else - ifeq (,$(wildcard $(JDIR)/include/jvmti.h)) - $(error the openjdk development package appears to me missing, install and try again) - endif -endif -$(info Using Java from $(JDIR)) -# -lrt required in 32-bit mode for clock_gettime() -LIBS=-lelf -lrt -INCDIR=-I $(JDIR)/include -I $(JDIR)/include/linux - -TARGETS=$(SLIBJVMTI) - -SRCS=libjvmti.c jvmti_agent.c -OBJS=$(SRCS:.c=.o) -SOBJS=$(OBJS:.o=.lo) -OPT=-O2 -g -Werror -Wall - -CFLAGS=$(INCDIR) $(OPT) - -all: $(TARGETS) - -.c.o: - $(CC) $(CFLAGS) -c $*.c -.c.lo: - $(CC) -fPIC -DPIC $(CFLAGS) -c $*.c -o $*.lo - -$(OBJS) $(SOBJS): Makefile jvmti_agent.h ../util/jitdump.h - -$(SLIBJVMTI): $(SOBJS) - $(CC) $(CFLAGS) $(SLDFLAGS) -o $@ $(SOBJS) $(LIBS) - $(LN) $@ libjvmti.$(SOLIBEXT) - -clean: - $(RM) -f *.o *.so.* *.so *.lo - -install: - -mkdir -p $(DESTDIR)/lib - install -m 755 $(SLIBJVMTI) $(DESTDIR)/lib/ - (cd $(DESTDIR)/lib; $(LN) $(SLIBJVMTI) $(VLIBJVMTI)) - (cd $(DESTDIR)/lib; $(LN) $(SLIBJVMTI) libjvmti.$(SOLIBEXT)) - ldconfig - -.SUFFIXES: .c .S .o .lo diff --git a/tools/perf/jvmti/jvmti_agent.c b/tools/perf/jvmti/jvmti_agent.c index 55daefff0d54..e9651a9d670e 100644 --- a/tools/perf/jvmti/jvmti_agent.c +++ b/tools/perf/jvmti/jvmti_agent.c @@ -44,11 +44,6 @@ static char jit_path[PATH_MAX]; static void *marker_addr; -/* - * padding buffer - */ -static const char pad_bytes[7]; - static inline pid_t gettid(void) { return (pid_t)syscall(__NR_gettid); @@ -230,7 +225,6 @@ init_arch_timestamp(void) void *jvmti_open(void) { - int pad_cnt; char dump_path[PATH_MAX]; struct jitheader header; int fd; @@ -288,10 +282,6 @@ void *jvmti_open(void) header.total_size = sizeof(header); header.pid = getpid(); - /* calculate amount of padding '\0' */ - pad_cnt = PADDING_8ALIGNED(header.total_size); - header.total_size += pad_cnt; - header.timestamp = perf_get_timestamp(); if (use_arch_timestamp) @@ -301,13 +291,6 @@ void *jvmti_open(void) warn("jvmti: cannot write dumpfile header"); goto error; } - - /* write padding '\0' if necessary */ - if (pad_cnt && !fwrite(pad_bytes, pad_cnt, 1, fp)) { - warn("jvmti: cannot write dumpfile header padding"); - goto error; - } - return fp; error: fclose(fp); @@ -349,7 +332,6 @@ jvmti_write_code(void *agent, char const *sym, static int code_generation = 1; struct jr_code_load rec; size_t sym_len; - size_t padding_count; FILE *fp = agent; int ret = -1; @@ -366,8 +348,6 @@ jvmti_write_code(void *agent, char const *sym, rec.p.id = JIT_CODE_LOAD; rec.p.total_size = sizeof(rec) + sym_len; - padding_count = PADDING_8ALIGNED(rec.p.total_size); - rec.p. total_size += padding_count; rec.p.timestamp = perf_get_timestamp(); rec.code_size = size; @@ -393,9 +373,6 @@ jvmti_write_code(void *agent, char const *sym, ret = fwrite_unlocked(&rec, sizeof(rec), 1, fp); fwrite_unlocked(sym, sym_len, 1, fp); - if (padding_count) - fwrite_unlocked(pad_bytes, padding_count, 1, fp); - if (code) fwrite_unlocked(code, size, 1, fp); @@ -412,7 +389,6 @@ jvmti_write_debug_info(void *agent, uint64_t code, const char *file, { struct jr_code_debug_info rec; size_t sret, len, size, flen; - size_t padding_count; uint64_t addr; const char *fn = file; FILE *fp = agent; @@ -443,16 +419,10 @@ jvmti_write_debug_info(void *agent, uint64_t code, const char *file, * int : line number * int : column discriminator * file[] : source file name - * padding : pad to multiple of 8 bytes */ size += nr_lines * sizeof(struct debug_entry); size += flen * nr_lines; - /* - * pad to 8 bytes - */ - padding_count = PADDING_8ALIGNED(size); - - rec.p.total_size = size + padding_count; + rec.p.total_size = size; /* * If JVM is multi-threaded, nultiple concurrent calls to agent @@ -486,12 +456,6 @@ jvmti_write_debug_info(void *agent, uint64_t code, const char *file, if (sret != 1) goto error; } - if (padding_count) { - sret = fwrite_unlocked(pad_bytes, padding_count, 1, fp); - if (sret != 1) - goto error; - } - funlockfile(fp); return 0; error: diff --git a/tools/perf/jvmti/libjvmti.c b/tools/perf/jvmti/libjvmti.c index ac12e4b91a92..5612641c69b4 100644 --- a/tools/perf/jvmti/libjvmti.c +++ b/tools/perf/jvmti/libjvmti.c @@ -12,6 +12,19 @@ static int has_line_numbers; void *jvmti_agent; +static void print_error(jvmtiEnv *jvmti, const char *msg, jvmtiError ret) +{ + char *err_msg = NULL; + jvmtiError err; + err = (*jvmti)->GetErrorName(jvmti, ret, &err_msg); + if (err == JVMTI_ERROR_NONE) { + warnx("%s failed with %s", msg, err_msg); + (*jvmti)->Deallocate(jvmti, (unsigned char *)err_msg); + } else { + warnx("%s failed with an unknown error %d", msg, ret); + } +} + static jvmtiError do_get_line_numbers(jvmtiEnv *jvmti, void *pc, jmethodID m, jint bci, jvmti_line_info_t *tab, jint *nr) @@ -22,8 +35,10 @@ do_get_line_numbers(jvmtiEnv *jvmti, void *pc, jmethodID m, jint bci, jvmtiError ret; ret = (*jvmti)->GetLineNumberTable(jvmti, m, &nr_lines, &loc_tab); - if (ret != JVMTI_ERROR_NONE) + if (ret != JVMTI_ERROR_NONE) { + print_error(jvmti, "GetLineNumberTable", ret); return ret; + } for (i = 0; i < nr_lines; i++) { if (loc_tab[i].start_location < bci) { @@ -71,6 +86,8 @@ get_line_numbers(jvmtiEnv *jvmti, const void *compile_info, jvmti_line_info_t ** /* free what was allocated for nothing */ (*jvmti)->Deallocate(jvmti, (unsigned char *)lne); nr_total += (int)nr; + } else { + print_error(jvmti, "GetLineNumberTable", ret); } } } @@ -130,7 +147,7 @@ compiled_method_load_cb(jvmtiEnv *jvmti, ret = (*jvmti)->GetMethodDeclaringClass(jvmti, method, &decl_class); if (ret != JVMTI_ERROR_NONE) { - warnx("jvmti: cannot get declaring class"); + print_error(jvmti, "GetMethodDeclaringClass", ret); return; } @@ -144,21 +161,21 @@ compiled_method_load_cb(jvmtiEnv *jvmti, ret = (*jvmti)->GetSourceFileName(jvmti, decl_class, &file_name); if (ret != JVMTI_ERROR_NONE) { - warnx("jvmti: cannot get source filename ret=%d", ret); + print_error(jvmti, "GetSourceFileName", ret); goto error; } ret = (*jvmti)->GetClassSignature(jvmti, decl_class, &class_sign, NULL); if (ret != JVMTI_ERROR_NONE) { - warnx("jvmti: getclassignature failed"); + print_error(jvmti, "GetClassSignature", ret); goto error; } ret = (*jvmti)->GetMethodName(jvmti, method, &func_name, &func_sign, NULL); if (ret != JVMTI_ERROR_NONE) { - warnx("jvmti: failed getmethodname"); + print_error(jvmti, "GetMethodName", ret); goto error; } @@ -253,7 +270,7 @@ Agent_OnLoad(JavaVM *jvm, char *options, void *reserved __unused) ret = (*jvmti)->AddCapabilities(jvmti, &caps1); if (ret != JVMTI_ERROR_NONE) { - warnx("jvmti: acquire compiled_method capability failed"); + print_error(jvmti, "AddCapabilities", ret); return -1; } ret = (*jvmti)->GetJLocationFormat(jvmti, &format); @@ -264,7 +281,9 @@ Agent_OnLoad(JavaVM *jvm, char *options, void *reserved __unused) ret = (*jvmti)->AddCapabilities(jvmti, &caps1); if (ret == JVMTI_ERROR_NONE) has_line_numbers = 1; - } + } else if (ret != JVMTI_ERROR_NONE) + print_error(jvmti, "GetJLocationFormat", ret); + memset(&cb, 0, sizeof(cb)); @@ -273,21 +292,21 @@ Agent_OnLoad(JavaVM *jvm, char *options, void *reserved __unused) ret = (*jvmti)->SetEventCallbacks(jvmti, &cb, sizeof(cb)); if (ret != JVMTI_ERROR_NONE) { - warnx("jvmti: cannot set event callbacks"); + print_error(jvmti, "SetEventCallbacks", ret); return -1; } ret = (*jvmti)->SetEventNotificationMode(jvmti, JVMTI_ENABLE, JVMTI_EVENT_COMPILED_METHOD_LOAD, NULL); if (ret != JVMTI_ERROR_NONE) { - warnx("jvmti: setnotification failed for method_load"); + print_error(jvmti, "SetEventNotificationMode(METHOD_LOAD)", ret); return -1; } ret = (*jvmti)->SetEventNotificationMode(jvmti, JVMTI_ENABLE, JVMTI_EVENT_DYNAMIC_CODE_GENERATED, NULL); if (ret != JVMTI_ERROR_NONE) { - warnx("jvmti: setnotification failed on code_generated"); + print_error(jvmti, "SetEventNotificationMode(CODE_GENERATED)", ret); return -1; } return 0; diff --git a/tools/perf/perf.c b/tools/perf/perf.c index 64c06961bfe4..aa23b3347d6b 100644 --- a/tools/perf/perf.c +++ b/tools/perf/perf.c @@ -43,6 +43,7 @@ static struct cmd_struct commands[] = { { "buildid-cache", cmd_buildid_cache, 0 }, { "buildid-list", cmd_buildid_list, 0 }, { "config", cmd_config, 0 }, + { "c2c", cmd_c2c, 0 }, { "diff", cmd_diff, 0 }, { "evlist", cmd_evlist, 0 }, { "help", cmd_help, 0 }, diff --git a/tools/perf/pmu-events/arch/powerpc/mapfile.csv b/tools/perf/pmu-events/arch/powerpc/mapfile.csv new file mode 100644 index 000000000000..e925baa0c30b --- /dev/null +++ b/tools/perf/pmu-events/arch/powerpc/mapfile.csv @@ -0,0 +1,21 @@ +# Format: +# PVR,Version,JSON/file/pathname,Type +# +# where +# PVR Processor version +# Version could be used to track version of of JSON file +# but currently unused. +# JSON/file/pathname is the path to JSON file, relative +# to tools/perf/pmu-events/arch/powerpc/. +# Type is core, uncore etc +# +# Multiple PVRs could map to a single JSON file. +# + +# Power8 entries +004b0000,1,power8.json,core +004b0201,1,power8.json,core +004c0000,1,power8.json,core +004d0000,1,power8.json,core +004d0100,1,power8.json,core +004d0200,1,power8.json,core diff --git a/tools/perf/pmu-events/arch/powerpc/power8/cache.json b/tools/perf/pmu-events/arch/powerpc/power8/cache.json new file mode 100644 index 000000000000..4a3daa6b4b96 --- /dev/null +++ b/tools/perf/pmu-events/arch/powerpc/power8/cache.json @@ -0,0 +1,176 @@ +[ + {, + "EventCode": "0x4c048", + "EventName": "PM_DATA_FROM_DL2L3_MOD", + "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load", + "PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x3c048", + "EventName": "PM_DATA_FROM_DL2L3_SHR", + "BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load", + "PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x3c04c", + "EventName": "PM_DATA_FROM_DL4", + "BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a demand load", + "PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x1c042", + "EventName": "PM_DATA_FROM_L2", + "BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand load", + "PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x200fe", + "EventName": "PM_DATA_FROM_L2MISS", + "BriefDescription": "Demand LD - L2 Miss (not L2 hit)", + "PublicDescription": "" + }, + {, + "EventCode": "0x1c04e", + "EventName": "PM_DATA_FROM_L2MISS_MOD", + "BriefDescription": "The processor's data cache was reloaded from a localtion other than the local core's L2 due to a demand load", + "PublicDescription": "The processor's data cache was reloaded from a localtion other than the local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x3c040", + "EventName": "PM_DATA_FROM_L2_DISP_CONFLICT_LDHITST", + "BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a demand load", + "PublicDescription": "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x4c040", + "EventName": "PM_DATA_FROM_L2_DISP_CONFLICT_OTHER", + "BriefDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a demand load", + "PublicDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x2c040", + "EventName": "PM_DATA_FROM_L2_MEPF", + "BriefDescription": "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to a demand load", + "PublicDescription": "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x1c040", + "EventName": "PM_DATA_FROM_L2_NO_CONFLICT", + "BriefDescription": "The processor's data cache was reloaded from local core's L2 without conflict due to a demand load", + "PublicDescription": "The processor's data cache was reloaded from local core's L2 without conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x4c042", + "EventName": "PM_DATA_FROM_L3", + "BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a demand load", + "PublicDescription": "The processor's data cache was reloaded from local core's L3 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x300fe", + "EventName": "PM_DATA_FROM_L3MISS", + "BriefDescription": "Demand LD - L3 Miss (not L2 hit and not L3 hit)", + "PublicDescription": "" + }, + {, + "EventCode": "0x4c04e", + "EventName": "PM_DATA_FROM_L3MISS_MOD", + "BriefDescription": "The processor's data cache was reloaded from a localtion other than the local core's L3 due to a demand load", + "PublicDescription": "The processor's data cache was reloaded from a localtion other than the local core's L3 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x3c042", + "EventName": "PM_DATA_FROM_L3_DISP_CONFLICT", + "BriefDescription": "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a demand load", + "PublicDescription": "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x2c042", + "EventName": "PM_DATA_FROM_L3_MEPF", + "BriefDescription": "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to a demand load", + "PublicDescription": "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x1c044", + "EventName": "PM_DATA_FROM_L3_NO_CONFLICT", + "BriefDescription": "The processor's data cache was reloaded from local core's L3 without conflict due to a demand load", + "PublicDescription": "The processor's data cache was reloaded from local core's L3 without conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x1c04c", + "EventName": "PM_DATA_FROM_LL4", + "BriefDescription": "The processor's data cache was reloaded from the local chip's L4 cache due to a demand load", + "PublicDescription": "The processor's data cache was reloaded from the local chip's L4 cache due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x4c04a", + "EventName": "PM_DATA_FROM_OFF_CHIP_CACHE", + "BriefDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a demand load", + "PublicDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x1c048", + "EventName": "PM_DATA_FROM_ON_CHIP_CACHE", + "BriefDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a demand load", + "PublicDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x2c046", + "EventName": "PM_DATA_FROM_RL2L3_MOD", + "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load", + "PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x1c04a", + "EventName": "PM_DATA_FROM_RL2L3_SHR", + "BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load", + "PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x3001a", + "EventName": "PM_DATA_TABLEWALK_CYC", + "BriefDescription": "Tablwalk Cycles (could be 1 or 2 active)", + "PublicDescription": "Data Tablewalk Active" + }, + {, + "EventCode": "0x4e04e", + "EventName": "PM_DPTEG_FROM_L3MISS", + "BriefDescription": "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0xd094", + "EventName": "PM_DSLB_MISS", + "BriefDescription": "Data SLB Miss - Total of all segment sizes", + "PublicDescription": "Data SLB Miss - Total of all segment sizesData SLB misses" + }, + {, + "EventCode": "0x1002c", + "EventName": "PM_L1_DCACHE_RELOADED_ALL", + "BriefDescription": "L1 data cache reloaded for demand or prefetch", + "PublicDescription": "" + }, + {, + "EventCode": "0x300f6", + "EventName": "PM_L1_DCACHE_RELOAD_VALID", + "BriefDescription": "DL1 reloaded due to Demand Load", + "PublicDescription": "" + }, + {, + "EventCode": "0x3e054", + "EventName": "PM_LD_MISS_L1", + "BriefDescription": "Load Missed L1", + "PublicDescription": "" + }, + {, + "EventCode": "0x100ee", + "EventName": "PM_LD_REF_L1", + "BriefDescription": "All L1 D cache load references counted at finish, gated by reject", + "PublicDescription": "Load Ref count combined for all units" + }, + {, + "EventCode": "0x300f0", + "EventName": "PM_ST_MISS_L1", + "BriefDescription": "Store Missed L1", + "PublicDescription": "" + }, +] diff --git a/tools/perf/pmu-events/arch/powerpc/power8/floating-point.json b/tools/perf/pmu-events/arch/powerpc/power8/floating-point.json new file mode 100644 index 000000000000..5f1bb9fca40c --- /dev/null +++ b/tools/perf/pmu-events/arch/powerpc/power8/floating-point.json @@ -0,0 +1,14 @@ +[ + {, + "EventCode": "0x2000e", + "EventName": "PM_FXU_BUSY", + "BriefDescription": "fxu0 busy and fxu1 busy", + "PublicDescription": "" + }, + {, + "EventCode": "0x1000e", + "EventName": "PM_FXU_IDLE", + "BriefDescription": "fxu0 idle and fxu1 idle", + "PublicDescription": "" + }, +] diff --git a/tools/perf/pmu-events/arch/powerpc/power8/frontend.json b/tools/perf/pmu-events/arch/powerpc/power8/frontend.json new file mode 100644 index 000000000000..04c5f1b7bee1 --- /dev/null +++ b/tools/perf/pmu-events/arch/powerpc/power8/frontend.json @@ -0,0 +1,470 @@ +[ + {, + "EventCode": "0x2505e", + "EventName": "PM_BACK_BR_CMPL", + "BriefDescription": "Branch instruction completed with a target address less than current instruction address", + "PublicDescription": "" + }, + {, + "EventCode": "0x10068", + "EventName": "PM_BRU_FIN", + "BriefDescription": "Branch Instruction Finished", + "PublicDescription": "" + }, + {, + "EventCode": "0x20036", + "EventName": "PM_BR_2PATH", + "BriefDescription": "two path branch", + "PublicDescription": "" + }, + {, + "EventCode": "0x40060", + "EventName": "PM_BR_CMPL", + "BriefDescription": "Branch Instruction completed", + "PublicDescription": "" + }, + {, + "EventCode": "0x400f6", + "EventName": "PM_BR_MPRED_CMPL", + "BriefDescription": "Number of Branch Mispredicts", + "PublicDescription": "" + }, + {, + "EventCode": "0x200fa", + "EventName": "PM_BR_TAKEN_CMPL", + "BriefDescription": "New event for Branch Taken", + "PublicDescription": "" + }, + {, + "EventCode": "0x10018", + "EventName": "PM_IC_DEMAND_CYC", + "BriefDescription": "Cycles when a demand ifetch was pending", + "PublicDescription": "Demand ifetch pending" + }, + {, + "EventCode": "0x100f6", + "EventName": "PM_IERAT_RELOAD", + "BriefDescription": "Number of I-ERAT reloads", + "PublicDescription": "IERAT Reloaded (Miss)" + }, + {, + "EventCode": "0x4006a", + "EventName": "PM_IERAT_RELOAD_16M", + "BriefDescription": "IERAT Reloaded (Miss) for a 16M page", + "PublicDescription": "" + }, + {, + "EventCode": "0x20064", + "EventName": "PM_IERAT_RELOAD_4K", + "BriefDescription": "IERAT Miss (Not implemented as DI on POWER6)", + "PublicDescription": "IERAT Reloaded (Miss) for a 4k page" + }, + {, + "EventCode": "0x3006a", + "EventName": "PM_IERAT_RELOAD_64K", + "BriefDescription": "IERAT Reloaded (Miss) for a 64k page", + "PublicDescription": "" + }, + {, + "EventCode": "0x14050", + "EventName": "PM_INST_CHIP_PUMP_CPRED", + "BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for an instruction fetch", + "PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for an instruction fetch" + }, + {, + "EventCode": "0x2", + "EventName": "PM_INST_CMPL", + "BriefDescription": "Number of PowerPC Instructions that completed", + "PublicDescription": "PPC Instructions Finished (completed)" + }, + {, + "EventCode": "0x200f2", + "EventName": "PM_INST_DISP", + "BriefDescription": "PPC Dispatched", + "PublicDescription": "" + }, + {, + "EventCode": "0x44048", + "EventName": "PM_INST_FROM_DL2L3_MOD", + "BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction fetch (not prefetch)", + "PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x34048", + "EventName": "PM_INST_FROM_DL2L3_SHR", + "BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction fetch (not prefetch)", + "PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x3404c", + "EventName": "PM_INST_FROM_DL4", + "BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to an instruction fetch (not prefetch)", + "PublicDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x4404c", + "EventName": "PM_INST_FROM_DMEM", + "BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Distant) due to an instruction fetch (not prefetch)", + "PublicDescription": "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x14042", + "EventName": "PM_INST_FROM_L2", + "BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 due to an instruction fetch (not prefetch)", + "PublicDescription": "The processor's Instruction cache was reloaded from local core's L2 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x1404e", + "EventName": "PM_INST_FROM_L2MISS", + "BriefDescription": "The processor's Instruction cache was reloaded from a localtion other than the local core's L2 due to an instruction fetch (not prefetch)", + "PublicDescription": "The processor's Instruction cache was reloaded from a localtion other than the local core's L2 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x34040", + "EventName": "PM_INST_FROM_L2_DISP_CONFLICT_LDHITST", + "BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 with load hit store conflict due to an instruction fetch (not prefetch)", + "PublicDescription": "The processor's Instruction cache was reloaded from local core's L2 with load hit store conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x44040", + "EventName": "PM_INST_FROM_L2_DISP_CONFLICT_OTHER", + "BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to an instruction fetch (not prefetch)", + "PublicDescription": "The processor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x24040", + "EventName": "PM_INST_FROM_L2_MEPF", + "BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to an instruction fetch (not prefetch)", + "PublicDescription": "The processor's Instruction cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x14040", + "EventName": "PM_INST_FROM_L2_NO_CONFLICT", + "BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 without conflict due to an instruction fetch (not prefetch)", + "PublicDescription": "The processor's Instruction cache was reloaded from local core's L2 without conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x44042", + "EventName": "PM_INST_FROM_L3", + "BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 due to an instruction fetch (not prefetch)", + "PublicDescription": "The processor's Instruction cache was reloaded from local core's L3 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x300fa", + "EventName": "PM_INST_FROM_L3MISS", + "BriefDescription": "Marked instruction was reloaded from a location beyond the local chiplet", + "PublicDescription": "Inst from L3 miss" + }, + {, + "EventCode": "0x4404e", + "EventName": "PM_INST_FROM_L3MISS_MOD", + "BriefDescription": "The processor's Instruction cache was reloaded from a localtion other than the local core's L3 due to a instruction fetch", + "PublicDescription": "The processor's Instruction cache was reloaded from a localtion other than the local core's L3 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x34042", + "EventName": "PM_INST_FROM_L3_DISP_CONFLICT", + "BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to an instruction fetch (not prefetch)", + "PublicDescription": "The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x24042", + "EventName": "PM_INST_FROM_L3_MEPF", + "BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to an instruction fetch (not prefetch)", + "PublicDescription": "The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x14044", + "EventName": "PM_INST_FROM_L3_NO_CONFLICT", + "BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 without conflict due to an instruction fetch (not prefetch)", + "PublicDescription": "The processor's Instruction cache was reloaded from local core's L3 without conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x1404c", + "EventName": "PM_INST_FROM_LL4", + "BriefDescription": "The processor's Instruction cache was reloaded from the local chip's L4 cache due to an instruction fetch (not prefetch)", + "PublicDescription": "The processor's Instruction cache was reloaded from the local chip's L4 cache due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x24048", + "EventName": "PM_INST_FROM_LMEM", + "BriefDescription": "The processor's Instruction cache was reloaded from the local chip's Memory due to an instruction fetch (not prefetch)", + "PublicDescription": "The processor's Instruction cache was reloaded from the local chip's Memory due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x2404c", + "EventName": "PM_INST_FROM_MEMORY", + "BriefDescription": "The processor's Instruction cache was reloaded from a memory location including L4 from local remote or distant due to an instruction fetch (not prefetch)", + "PublicDescription": "The processor's Instruction cache was reloaded from a memory location including L4 from local remote or distant due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x4404a", + "EventName": "PM_INST_FROM_OFF_CHIP_CACHE", + "BriefDescription": "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to an instruction fetch (not prefetch)", + "PublicDescription": "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x14048", + "EventName": "PM_INST_FROM_ON_CHIP_CACHE", + "BriefDescription": "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to an instruction fetch (not prefetch)", + "PublicDescription": "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x24046", + "EventName": "PM_INST_FROM_RL2L3_MOD", + "BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)", + "PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x1404a", + "EventName": "PM_INST_FROM_RL2L3_SHR", + "BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)", + "PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x2404a", + "EventName": "PM_INST_FROM_RL4", + "BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)", + "PublicDescription": "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x3404a", + "EventName": "PM_INST_FROM_RMEM", + "BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)", + "PublicDescription": "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x24050", + "EventName": "PM_INST_GRP_PUMP_CPRED", + "BriefDescription": "Initial and Final Pump Scope was group pump (prediction=correct) for an instruction fetch", + "PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was group pump for an instruction fetch" + }, + {, + "EventCode": "0x24052", + "EventName": "PM_INST_GRP_PUMP_MPRED", + "BriefDescription": "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for an instruction fetch", + "PublicDescription": "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro" + }, + {, + "EventCode": "0x14052", + "EventName": "PM_INST_GRP_PUMP_MPRED_RTY", + "BriefDescription": "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for an instruction fetch", + "PublicDescription": "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor an instruction fetch" + }, + {, + "EventCode": "0x1003a", + "EventName": "PM_INST_IMC_MATCH_CMPL", + "BriefDescription": "IMC Match Count ( Not architected in P8)", + "PublicDescription": "" + }, + {, + "EventCode": "0x14054", + "EventName": "PM_INST_PUMP_CPRED", + "BriefDescription": "Pump prediction correct. Counts across all types of pumps for an instruction fetch", + "PublicDescription": "Pump prediction correct. Counts across all types of pumpsfor an instruction fetch" + }, + {, + "EventCode": "0x44052", + "EventName": "PM_INST_PUMP_MPRED", + "BriefDescription": "Pump misprediction. Counts across all types of pumps for an instruction fetch", + "PublicDescription": "Pump Mis prediction Counts across all types of pumpsfor an instruction fetch" + }, + {, + "EventCode": "0x34050", + "EventName": "PM_INST_SYS_PUMP_CPRED", + "BriefDescription": "Initial and Final Pump Scope was system pump (prediction=correct) for an instruction fetch", + "PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was system pump for an instruction fetch" + }, + {, + "EventCode": "0x34052", + "EventName": "PM_INST_SYS_PUMP_MPRED", + "BriefDescription": "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for an instruction fetch", + "PublicDescription": "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or" + }, + {, + "EventCode": "0x44050", + "EventName": "PM_INST_SYS_PUMP_MPRED_RTY", + "BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for an instruction fetch", + "PublicDescription": "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for an instruction fetch" + }, + {, + "EventCode": "0x45048", + "EventName": "PM_IPTEG_FROM_DL2L3_MOD", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x35048", + "EventName": "PM_IPTEG_FROM_DL2L3_SHR", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x3504c", + "EventName": "PM_IPTEG_FROM_DL4", + "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a instruction side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x4504c", + "EventName": "PM_IPTEG_FROM_DMEM", + "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a instruction side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x15042", + "EventName": "PM_IPTEG_FROM_L2", + "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a instruction side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x1504e", + "EventName": "PM_IPTEG_FROM_L2MISS", + "BriefDescription": "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a instruction side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x25040", + "EventName": "PM_IPTEG_FROM_L2_MEPF", + "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a instruction side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x15040", + "EventName": "PM_IPTEG_FROM_L2_NO_CONFLICT", + "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a instruction side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x45042", + "EventName": "PM_IPTEG_FROM_L3", + "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a instruction side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x4504e", + "EventName": "PM_IPTEG_FROM_L3MISS", + "BriefDescription": "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a instruction side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x35042", + "EventName": "PM_IPTEG_FROM_L3_DISP_CONFLICT", + "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a instruction side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x25042", + "EventName": "PM_IPTEG_FROM_L3_MEPF", + "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a instruction side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x15044", + "EventName": "PM_IPTEG_FROM_L3_NO_CONFLICT", + "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a instruction side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x1504c", + "EventName": "PM_IPTEG_FROM_LL4", + "BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a instruction side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x25048", + "EventName": "PM_IPTEG_FROM_LMEM", + "BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a instruction side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x2504c", + "EventName": "PM_IPTEG_FROM_MEMORY", + "BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a instruction side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x4504a", + "EventName": "PM_IPTEG_FROM_OFF_CHIP_CACHE", + "BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a instruction side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x15048", + "EventName": "PM_IPTEG_FROM_ON_CHIP_CACHE", + "BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a instruction side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x25046", + "EventName": "PM_IPTEG_FROM_RL2L3_MOD", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x1504a", + "EventName": "PM_IPTEG_FROM_RL2L3_SHR", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x2504a", + "EventName": "PM_IPTEG_FROM_RL4", + "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x3504a", + "EventName": "PM_IPTEG_FROM_RMEM", + "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a instruction side request", + "PublicDescription": "" + }, + {, + "EventCode": "0xd096", + "EventName": "PM_ISLB_MISS", + "BriefDescription": "I SLB Miss", + "PublicDescription": "" + }, + {, + "EventCode": "0x400fc", + "EventName": "PM_ITLB_MISS", + "BriefDescription": "ITLB Reloaded (always zero on POWER6)", + "PublicDescription": "" + }, + {, + "EventCode": "0x200fd", + "EventName": "PM_L1_ICACHE_MISS", + "BriefDescription": "Demand iCache Miss", + "PublicDescription": "" + }, + {, + "EventCode": "0x40012", + "EventName": "PM_L1_ICACHE_RELOADED_ALL", + "BriefDescription": "Counts all Icache reloads includes demand, prefetchm prefetch turned into demand and demand turned into prefetch", + "PublicDescription": "" + }, + {, + "EventCode": "0x30068", + "EventName": "PM_L1_ICACHE_RELOADED_PREF", + "BriefDescription": "Counts all Icache prefetch reloads ( includes demand turned into prefetch)", + "PublicDescription": "" + }, + {, + "EventCode": "0x300f4", + "EventName": "PM_THRD_CONC_RUN_INST", + "BriefDescription": "PPC Instructions Finished when both threads in run_cycles", + "PublicDescription": "Concurrent Run Instructions" + }, + {, + "EventCode": "0x30060", + "EventName": "PM_TM_TRANS_RUN_INST", + "BriefDescription": "Instructions completed in transactional state", + "PublicDescription": "" + }, + {, + "EventCode": "0x4e014", + "EventName": "PM_TM_TX_PASS_RUN_INST", + "BriefDescription": "run instructions spent in successful transactions", + "PublicDescription": "" + }, +] diff --git a/tools/perf/pmu-events/arch/powerpc/power8/marked.json b/tools/perf/pmu-events/arch/powerpc/power8/marked.json new file mode 100644 index 000000000000..dcdcede3c3fe --- /dev/null +++ b/tools/perf/pmu-events/arch/powerpc/power8/marked.json @@ -0,0 +1,794 @@ +[ + {, + "EventCode": "0x3515e", + "EventName": "PM_MRK_BACK_BR_CMPL", + "BriefDescription": "Marked branch instruction completed with a target address less than current instruction address", + "PublicDescription": "" + }, + {, + "EventCode": "0x2013a", + "EventName": "PM_MRK_BRU_FIN", + "BriefDescription": "bru marked instr finish", + "PublicDescription": "" + }, + {, + "EventCode": "0x1016e", + "EventName": "PM_MRK_BR_CMPL", + "BriefDescription": "Branch Instruction completed", + "PublicDescription": "" + }, + {, + "EventCode": "0x301e4", + "EventName": "PM_MRK_BR_MPRED_CMPL", + "BriefDescription": "Marked Branch Mispredicted", + "PublicDescription": "" + }, + {, + "EventCode": "0x101e2", + "EventName": "PM_MRK_BR_TAKEN_CMPL", + "BriefDescription": "Marked Branch Taken completed", + "PublicDescription": "" + }, + {, + "EventCode": "0x4d148", + "EventName": "PM_MRK_DATA_FROM_DL2L3_MOD", + "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x2d128", + "EventName": "PM_MRK_DATA_FROM_DL2L3_MOD_CYC", + "BriefDescription": "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x3d148", + "EventName": "PM_MRK_DATA_FROM_DL2L3_SHR", + "BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x2c128", + "EventName": "PM_MRK_DATA_FROM_DL2L3_SHR_CYC", + "BriefDescription": "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x3d14c", + "EventName": "PM_MRK_DATA_FROM_DL4", + "BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x2c12c", + "EventName": "PM_MRK_DATA_FROM_DL4_CYC", + "BriefDescription": "Duration in cycles to reload from another chip's L4 on a different Node or Group (Distant) due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x4d14c", + "EventName": "PM_MRK_DATA_FROM_DMEM", + "BriefDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x2d12c", + "EventName": "PM_MRK_DATA_FROM_DMEM_CYC", + "BriefDescription": "Duration in cycles to reload from another chip's memory on the same Node or Group (Distant) due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x1d142", + "EventName": "PM_MRK_DATA_FROM_L2", + "BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x1d14e", + "EventName": "PM_MRK_DATA_FROM_L2MISS", + "BriefDescription": "Data cache reload L2 miss", + "PublicDescription": "" + }, + {, + "EventCode": "0x4c12e", + "EventName": "PM_MRK_DATA_FROM_L2MISS_CYC", + "BriefDescription": "Duration in cycles to reload from a localtion other than the local core's L2 due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x4c122", + "EventName": "PM_MRK_DATA_FROM_L2_CYC", + "BriefDescription": "Duration in cycles to reload from local core's L2 due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x3d140", + "EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST", + "BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x2c120", + "EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC", + "BriefDescription": "Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x4d140", + "EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER", + "BriefDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x2d120", + "EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER_CYC", + "BriefDescription": "Duration in cycles to reload from local core's L2 with dispatch conflict due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x2d140", + "EventName": "PM_MRK_DATA_FROM_L2_MEPF", + "BriefDescription": "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x4d120", + "EventName": "PM_MRK_DATA_FROM_L2_MEPF_CYC", + "BriefDescription": "Duration in cycles to reload from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x1d140", + "EventName": "PM_MRK_DATA_FROM_L2_NO_CONFLICT", + "BriefDescription": "The processor's data cache was reloaded from local core's L2 without conflict due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x4c120", + "EventName": "PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC", + "BriefDescription": "Duration in cycles to reload from local core's L2 without conflict due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x4d142", + "EventName": "PM_MRK_DATA_FROM_L3", + "BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x201e4", + "EventName": "PM_MRK_DATA_FROM_L3MISS", + "BriefDescription": "The processor's data cache was reloaded from a localtion other than the local core's L3 due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x2d12e", + "EventName": "PM_MRK_DATA_FROM_L3MISS_CYC", + "BriefDescription": "Duration in cycles to reload from a localtion other than the local core's L3 due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x2d122", + "EventName": "PM_MRK_DATA_FROM_L3_CYC", + "BriefDescription": "Duration in cycles to reload from local core's L3 due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x3d142", + "EventName": "PM_MRK_DATA_FROM_L3_DISP_CONFLICT", + "BriefDescription": "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x2c122", + "EventName": "PM_MRK_DATA_FROM_L3_DISP_CONFLICT_CYC", + "BriefDescription": "Duration in cycles to reload from local core's L3 with dispatch conflict due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x2d142", + "EventName": "PM_MRK_DATA_FROM_L3_MEPF", + "BriefDescription": "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x4d122", + "EventName": "PM_MRK_DATA_FROM_L3_MEPF_CYC", + "BriefDescription": "Duration in cycles to reload from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x1d144", + "EventName": "PM_MRK_DATA_FROM_L3_NO_CONFLICT", + "BriefDescription": "The processor's data cache was reloaded from local core's L3 without conflict due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x4c124", + "EventName": "PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC", + "BriefDescription": "Duration in cycles to reload from local core's L3 without conflict due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x1d14c", + "EventName": "PM_MRK_DATA_FROM_LL4", + "BriefDescription": "The processor's data cache was reloaded from the local chip's L4 cache due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x4c12c", + "EventName": "PM_MRK_DATA_FROM_LL4_CYC", + "BriefDescription": "Duration in cycles to reload from the local chip's L4 cache due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x2d148", + "EventName": "PM_MRK_DATA_FROM_LMEM", + "BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x4d128", + "EventName": "PM_MRK_DATA_FROM_LMEM_CYC", + "BriefDescription": "Duration in cycles to reload from the local chip's Memory due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x2d14c", + "EventName": "PM_MRK_DATA_FROM_MEMORY", + "BriefDescription": "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x4d12c", + "EventName": "PM_MRK_DATA_FROM_MEMORY_CYC", + "BriefDescription": "Duration in cycles to reload from a memory location including L4 from local remote or distant due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x4d14a", + "EventName": "PM_MRK_DATA_FROM_OFF_CHIP_CACHE", + "BriefDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x2d12a", + "EventName": "PM_MRK_DATA_FROM_OFF_CHIP_CACHE_CYC", + "BriefDescription": "Duration in cycles to reload either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x1d148", + "EventName": "PM_MRK_DATA_FROM_ON_CHIP_CACHE", + "BriefDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x4c128", + "EventName": "PM_MRK_DATA_FROM_ON_CHIP_CACHE_CYC", + "BriefDescription": "Duration in cycles to reload either shared or modified data from another core's L2/L3 on the same chip due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x2d146", + "EventName": "PM_MRK_DATA_FROM_RL2L3_MOD", + "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x4d126", + "EventName": "PM_MRK_DATA_FROM_RL2L3_MOD_CYC", + "BriefDescription": "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x1d14a", + "EventName": "PM_MRK_DATA_FROM_RL2L3_SHR", + "BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x4c12a", + "EventName": "PM_MRK_DATA_FROM_RL2L3_SHR_CYC", + "BriefDescription": "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x2d14a", + "EventName": "PM_MRK_DATA_FROM_RL4", + "BriefDescription": "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x4d12a", + "EventName": "PM_MRK_DATA_FROM_RL4_CYC", + "BriefDescription": "Duration in cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x3d14a", + "EventName": "PM_MRK_DATA_FROM_RMEM", + "BriefDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x2c12a", + "EventName": "PM_MRK_DATA_FROM_RMEM_CYC", + "BriefDescription": "Duration in cycles to reload from another chip's memory on the same Node or Group ( Remote) due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x40118", + "EventName": "PM_MRK_DCACHE_RELOAD_INTV", + "BriefDescription": "Combined Intervention event", + "PublicDescription": "" + }, + {, + "EventCode": "0x301e6", + "EventName": "PM_MRK_DERAT_MISS", + "BriefDescription": "Erat Miss (TLB Access) All page sizes", + "PublicDescription": "" + }, + {, + "EventCode": "0x4d154", + "EventName": "PM_MRK_DERAT_MISS_16G", + "BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 16G", + "PublicDescription": "" + }, + {, + "EventCode": "0x3d154", + "EventName": "PM_MRK_DERAT_MISS_16M", + "BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 16M", + "PublicDescription": "" + }, + {, + "EventCode": "0x1d156", + "EventName": "PM_MRK_DERAT_MISS_4K", + "BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 4K", + "PublicDescription": "" + }, + {, + "EventCode": "0x2d154", + "EventName": "PM_MRK_DERAT_MISS_64K", + "BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 64K", + "PublicDescription": "" + }, + {, + "EventCode": "0x20132", + "EventName": "PM_MRK_DFU_FIN", + "BriefDescription": "Decimal Unit marked Instruction Finish", + "PublicDescription": "" + }, + {, + "EventCode": "0x4f148", + "EventName": "PM_MRK_DPTEG_FROM_DL2L3_MOD", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x3f148", + "EventName": "PM_MRK_DPTEG_FROM_DL2L3_SHR", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x3f14c", + "EventName": "PM_MRK_DPTEG_FROM_DL4", + "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a marked data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x4f14c", + "EventName": "PM_MRK_DPTEG_FROM_DMEM", + "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a marked data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x1f142", + "EventName": "PM_MRK_DPTEG_FROM_L2", + "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a marked data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x1f14e", + "EventName": "PM_MRK_DPTEG_FROM_L2MISS", + "BriefDescription": "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a marked data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x2f140", + "EventName": "PM_MRK_DPTEG_FROM_L2_MEPF", + "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x1f140", + "EventName": "PM_MRK_DPTEG_FROM_L2_NO_CONFLICT", + "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a marked data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x4f142", + "EventName": "PM_MRK_DPTEG_FROM_L3", + "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x4f14e", + "EventName": "PM_MRK_DPTEG_FROM_L3MISS", + "BriefDescription": "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a marked data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x3f142", + "EventName": "PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT", + "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a marked data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x2f142", + "EventName": "PM_MRK_DPTEG_FROM_L3_MEPF", + "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x1f144", + "EventName": "PM_MRK_DPTEG_FROM_L3_NO_CONFLICT", + "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a marked data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x1f14c", + "EventName": "PM_MRK_DPTEG_FROM_LL4", + "BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a marked data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x2f148", + "EventName": "PM_MRK_DPTEG_FROM_LMEM", + "BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a marked data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x2f14c", + "EventName": "PM_MRK_DPTEG_FROM_MEMORY", + "BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a marked data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x4f14a", + "EventName": "PM_MRK_DPTEG_FROM_OFF_CHIP_CACHE", + "BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x1f148", + "EventName": "PM_MRK_DPTEG_FROM_ON_CHIP_CACHE", + "BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a marked data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x2f146", + "EventName": "PM_MRK_DPTEG_FROM_RL2L3_MOD", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x1f14a", + "EventName": "PM_MRK_DPTEG_FROM_RL2L3_SHR", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x2f14a", + "EventName": "PM_MRK_DPTEG_FROM_RL4", + "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a marked data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x3f14a", + "EventName": "PM_MRK_DPTEG_FROM_RMEM", + "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a marked data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x401e4", + "EventName": "PM_MRK_DTLB_MISS", + "BriefDescription": "Marked dtlb miss", + "PublicDescription": "" + }, + {, + "EventCode": "0x1d158", + "EventName": "PM_MRK_DTLB_MISS_16G", + "BriefDescription": "Marked Data TLB Miss page size 16G", + "PublicDescription": "" + }, + {, + "EventCode": "0x4d156", + "EventName": "PM_MRK_DTLB_MISS_16M", + "BriefDescription": "Marked Data TLB Miss page size 16M", + "PublicDescription": "" + }, + {, + "EventCode": "0x2d156", + "EventName": "PM_MRK_DTLB_MISS_4K", + "BriefDescription": "Marked Data TLB Miss page size 4k", + "PublicDescription": "" + }, + {, + "EventCode": "0x3d156", + "EventName": "PM_MRK_DTLB_MISS_64K", + "BriefDescription": "Marked Data TLB Miss page size 64K", + "PublicDescription": "" + }, + {, + "EventCode": "0x40154", + "EventName": "PM_MRK_FAB_RSP_BKILL", + "BriefDescription": "Marked store had to do a bkill", + "PublicDescription": "" + }, + {, + "EventCode": "0x2f150", + "EventName": "PM_MRK_FAB_RSP_BKILL_CYC", + "BriefDescription": "cycles L2 RC took for a bkill", + "PublicDescription": "" + }, + {, + "EventCode": "0x3015e", + "EventName": "PM_MRK_FAB_RSP_CLAIM_RTY", + "BriefDescription": "Sampled store did a rwitm and got a rty", + "PublicDescription": "" + }, + {, + "EventCode": "0x30154", + "EventName": "PM_MRK_FAB_RSP_DCLAIM", + "BriefDescription": "Marked store had to do a dclaim", + "PublicDescription": "" + }, + {, + "EventCode": "0x2f152", + "EventName": "PM_MRK_FAB_RSP_DCLAIM_CYC", + "BriefDescription": "cycles L2 RC took for a dclaim", + "PublicDescription": "" + }, + {, + "EventCode": "0x4015e", + "EventName": "PM_MRK_FAB_RSP_RD_RTY", + "BriefDescription": "Sampled L2 reads retry count", + "PublicDescription": "" + }, + {, + "EventCode": "0x1015e", + "EventName": "PM_MRK_FAB_RSP_RD_T_INTV", + "BriefDescription": "Sampled Read got a T intervention", + "PublicDescription": "" + }, + {, + "EventCode": "0x4f150", + "EventName": "PM_MRK_FAB_RSP_RWITM_CYC", + "BriefDescription": "cycles L2 RC took for a rwitm", + "PublicDescription": "" + }, + {, + "EventCode": "0x2015e", + "EventName": "PM_MRK_FAB_RSP_RWITM_RTY", + "BriefDescription": "Sampled store did a rwitm and got a rty", + "PublicDescription": "" + }, + {, + "EventCode": "0x20134", + "EventName": "PM_MRK_FXU_FIN", + "BriefDescription": "fxu marked instr finish", + "PublicDescription": "" + }, + {, + "EventCode": "0x401e0", + "EventName": "PM_MRK_INST_CMPL", + "BriefDescription": "marked instruction completed", + "PublicDescription": "" + }, + {, + "EventCode": "0x20130", + "EventName": "PM_MRK_INST_DECODED", + "BriefDescription": "marked instruction decoded", + "PublicDescription": "marked instruction decoded. Name from ISU?" + }, + {, + "EventCode": "0x101e0", + "EventName": "PM_MRK_INST_DISP", + "BriefDescription": "The thread has dispatched a randomly sampled marked instruction", + "PublicDescription": "Marked Instruction dispatched" + }, + {, + "EventCode": "0x30130", + "EventName": "PM_MRK_INST_FIN", + "BriefDescription": "marked instruction finished", + "PublicDescription": "marked instr finish any unit" + }, + {, + "EventCode": "0x401e6", + "EventName": "PM_MRK_INST_FROM_L3MISS", + "BriefDescription": "Marked instruction was reloaded from a location beyond the local chiplet", + "PublicDescription": "n/a" + }, + {, + "EventCode": "0x10132", + "EventName": "PM_MRK_INST_ISSUED", + "BriefDescription": "Marked instruction issued", + "PublicDescription": "" + }, + {, + "EventCode": "0x40134", + "EventName": "PM_MRK_INST_TIMEO", + "BriefDescription": "marked Instruction finish timeout (instruction lost)", + "PublicDescription": "" + }, + {, + "EventCode": "0x101e4", + "EventName": "PM_MRK_L1_ICACHE_MISS", + "BriefDescription": "sampled Instruction suffered an icache Miss", + "PublicDescription": "Marked L1 Icache Miss" + }, + {, + "EventCode": "0x101ea", + "EventName": "PM_MRK_L1_RELOAD_VALID", + "BriefDescription": "Marked demand reload", + "PublicDescription": "" + }, + {, + "EventCode": "0x20114", + "EventName": "PM_MRK_L2_RC_DISP", + "BriefDescription": "Marked Instruction RC dispatched in L2", + "PublicDescription": "" + }, + {, + "EventCode": "0x3012a", + "EventName": "PM_MRK_L2_RC_DONE", + "BriefDescription": "Marked RC done", + "PublicDescription": "" + }, + {, + "EventCode": "0x40116", + "EventName": "PM_MRK_LARX_FIN", + "BriefDescription": "Larx finished", + "PublicDescription": "" + }, + {, + "EventCode": "0x1013e", + "EventName": "PM_MRK_LD_MISS_EXPOSED_CYC", + "BriefDescription": "Marked Load exposed Miss cycles", + "PublicDescription": "Marked Load exposed Miss (use edge detect to count #)" + }, + {, + "EventCode": "0x201e2", + "EventName": "PM_MRK_LD_MISS_L1", + "BriefDescription": "Marked DL1 Demand Miss counted at exec time", + "PublicDescription": "" + }, + {, + "EventCode": "0x4013e", + "EventName": "PM_MRK_LD_MISS_L1_CYC", + "BriefDescription": "Marked ld latency", + "PublicDescription": "" + }, + {, + "EventCode": "0x40132", + "EventName": "PM_MRK_LSU_FIN", + "BriefDescription": "lsu marked instr finish", + "PublicDescription": "" + }, + {, + "EventCode": "0x20112", + "EventName": "PM_MRK_NTF_FIN", + "BriefDescription": "Marked next to finish instruction finished", + "PublicDescription": "" + }, + {, + "EventCode": "0x1d15e", + "EventName": "PM_MRK_RUN_CYC", + "BriefDescription": "Marked run cycles", + "PublicDescription": "" + }, + {, + "EventCode": "0x3013e", + "EventName": "PM_MRK_STALL_CMPLU_CYC", + "BriefDescription": "Marked Group completion Stall", + "PublicDescription": "Marked Group Completion Stall cycles (use edge detect to count #)" + }, + {, + "EventCode": "0x3e158", + "EventName": "PM_MRK_STCX_FAIL", + "BriefDescription": "marked stcx failed", + "PublicDescription": "" + }, + {, + "EventCode": "0x10134", + "EventName": "PM_MRK_ST_CMPL", + "BriefDescription": "marked store completed and sent to nest", + "PublicDescription": "Marked store completed" + }, + {, + "EventCode": "0x30134", + "EventName": "PM_MRK_ST_CMPL_INT", + "BriefDescription": "marked store finished with intervention", + "PublicDescription": "marked store complete (data home) with intervention" + }, + {, + "EventCode": "0x3f150", + "EventName": "PM_MRK_ST_DRAIN_TO_L2DISP_CYC", + "BriefDescription": "cycles to drain st from core to L2", + "PublicDescription": "" + }, + {, + "EventCode": "0x3012c", + "EventName": "PM_MRK_ST_FWD", + "BriefDescription": "Marked st forwards", + "PublicDescription": "" + }, + {, + "EventCode": "0x1f150", + "EventName": "PM_MRK_ST_L2DISP_TO_CMPL_CYC", + "BriefDescription": "cycles from L2 rc disp to l2 rc completion", + "PublicDescription": "" + }, + {, + "EventCode": "0x20138", + "EventName": "PM_MRK_ST_NEST", + "BriefDescription": "Marked store sent to nest", + "PublicDescription": "" + }, + {, + "EventCode": "0x30132", + "EventName": "PM_MRK_VSU_FIN", + "BriefDescription": "VSU marked instr finish", + "PublicDescription": "vsu (fpu) marked instr finish" + }, + {, + "EventCode": "0x3d15e", + "EventName": "PM_MULT_MRK", + "BriefDescription": "mult marked instr", + "PublicDescription": "" + }, + {, + "EventCode": "0x15152", + "EventName": "PM_SYNC_MRK_BR_LINK", + "BriefDescription": "Marked Branch and link branch that can cause a synchronous interrupt", + "PublicDescription": "" + }, + {, + "EventCode": "0x1515c", + "EventName": "PM_SYNC_MRK_BR_MPRED", + "BriefDescription": "Marked Branch mispredict that can cause a synchronous interrupt", + "PublicDescription": "" + }, + {, + "EventCode": "0x15156", + "EventName": "PM_SYNC_MRK_FX_DIVIDE", + "BriefDescription": "Marked fixed point divide that can cause a synchronous interrupt", + "PublicDescription": "" + }, + {, + "EventCode": "0x15158", + "EventName": "PM_SYNC_MRK_L2HIT", + "BriefDescription": "Marked L2 Hits that can throw a synchronous interrupt", + "PublicDescription": "" + }, + {, + "EventCode": "0x1515a", + "EventName": "PM_SYNC_MRK_L2MISS", + "BriefDescription": "Marked L2 Miss that can throw a synchronous interrupt", + "PublicDescription": "" + }, + {, + "EventCode": "0x15154", + "EventName": "PM_SYNC_MRK_L3MISS", + "BriefDescription": "Marked L3 misses that can throw a synchronous interrupt", + "PublicDescription": "" + }, + {, + "EventCode": "0x15150", + "EventName": "PM_SYNC_MRK_PROBE_NOP", + "BriefDescription": "Marked probeNops which can cause synchronous interrupts", + "PublicDescription": "" + }, +] diff --git a/tools/perf/pmu-events/arch/powerpc/power8/memory.json b/tools/perf/pmu-events/arch/powerpc/power8/memory.json new file mode 100644 index 000000000000..87cdaadba7bd --- /dev/null +++ b/tools/perf/pmu-events/arch/powerpc/power8/memory.json @@ -0,0 +1,212 @@ +[ + {, + "EventCode": "0x10050", + "EventName": "PM_CHIP_PUMP_CPRED", + "BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", + "PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for all data types ( demand load,data,inst prefetch,inst fetch,xlate (I or d)" + }, + {, + "EventCode": "0x1c050", + "EventName": "PM_DATA_CHIP_PUMP_CPRED", + "BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for a demand load", + "PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for a demand load" + }, + {, + "EventCode": "0x4c04c", + "EventName": "PM_DATA_FROM_DMEM", + "BriefDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a demand load", + "PublicDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x2c048", + "EventName": "PM_DATA_FROM_LMEM", + "BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a demand load", + "PublicDescription": "The processor's data cache was reloaded from the local chip's Memory due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x2c04c", + "EventName": "PM_DATA_FROM_MEMORY", + "BriefDescription": "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a demand load", + "PublicDescription": "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x2c04a", + "EventName": "PM_DATA_FROM_RL4", + "BriefDescription": "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a demand load", + "PublicDescription": "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x3c04a", + "EventName": "PM_DATA_FROM_RMEM", + "BriefDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a demand load", + "PublicDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x2c050", + "EventName": "PM_DATA_GRP_PUMP_CPRED", + "BriefDescription": "Initial and Final Pump Scope was group pump (prediction=correct) for a demand load", + "PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was group pump for a demand load" + }, + {, + "EventCode": "0x2c052", + "EventName": "PM_DATA_GRP_PUMP_MPRED", + "BriefDescription": "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for a demand load", + "PublicDescription": "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro" + }, + {, + "EventCode": "0x1c052", + "EventName": "PM_DATA_GRP_PUMP_MPRED_RTY", + "BriefDescription": "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a demand load", + "PublicDescription": "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor a demand load" + }, + {, + "EventCode": "0x1c054", + "EventName": "PM_DATA_PUMP_CPRED", + "BriefDescription": "Pump prediction correct. Counts across all types of pumps for a demand load", + "PublicDescription": "" + }, + {, + "EventCode": "0x4c052", + "EventName": "PM_DATA_PUMP_MPRED", + "BriefDescription": "Pump misprediction. Counts across all types of pumps for a demand load", + "PublicDescription": "Pump Mis prediction Counts across all types of pumpsfor a demand load" + }, + {, + "EventCode": "0x3c050", + "EventName": "PM_DATA_SYS_PUMP_CPRED", + "BriefDescription": "Initial and Final Pump Scope was system pump (prediction=correct) for a demand load", + "PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was system pump for a demand load" + }, + {, + "EventCode": "0x3c052", + "EventName": "PM_DATA_SYS_PUMP_MPRED", + "BriefDescription": "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for a demand load", + "PublicDescription": "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or" + }, + {, + "EventCode": "0x4c050", + "EventName": "PM_DATA_SYS_PUMP_MPRED_RTY", + "BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for a demand load", + "PublicDescription": "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for a demand load" + }, + {, + "EventCode": "0x3e04c", + "EventName": "PM_DPTEG_FROM_DL4", + "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x4e04c", + "EventName": "PM_DPTEG_FROM_DMEM", + "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x3e04a", + "EventName": "PM_DPTEG_FROM_RMEM", + "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x20050", + "EventName": "PM_GRP_PUMP_CPRED", + "BriefDescription": "Initial and Final Pump Scope and data sourced across this scope was group pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", + "PublicDescription": "" + }, + {, + "EventCode": "0x20052", + "EventName": "PM_GRP_PUMP_MPRED", + "BriefDescription": "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", + "PublicDescription": "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro" + }, + {, + "EventCode": "0x10052", + "EventName": "PM_GRP_PUMP_MPRED_RTY", + "BriefDescription": "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", + "PublicDescription": "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)" + }, + {, + "EventCode": "0x18082", + "EventName": "PM_L3_CO_MEPF", + "BriefDescription": "L3 CO of line in Mep state ( includes casthrough", + "PublicDescription": "" + }, + {, + "EventCode": "0x4c058", + "EventName": "PM_MEM_CO", + "BriefDescription": "Memory castouts from this lpar", + "PublicDescription": "" + }, + {, + "EventCode": "0x10058", + "EventName": "PM_MEM_LOC_THRESH_IFU", + "BriefDescription": "Local Memory above threshold for IFU speculation control", + "PublicDescription": "" + }, + {, + "EventCode": "0x40056", + "EventName": "PM_MEM_LOC_THRESH_LSU_HIGH", + "BriefDescription": "Local memory above threshold for LSU medium", + "PublicDescription": "" + }, + {, + "EventCode": "0x1c05e", + "EventName": "PM_MEM_LOC_THRESH_LSU_MED", + "BriefDescription": "Local memory above theshold for data prefetch", + "PublicDescription": "" + }, + {, + "EventCode": "0x2c058", + "EventName": "PM_MEM_PREF", + "BriefDescription": "Memory prefetch for this lpar. Includes L4", + "PublicDescription": "" + }, + {, + "EventCode": "0x10056", + "EventName": "PM_MEM_READ", + "BriefDescription": "Reads from Memory from this lpar (includes data/inst/xlate/l1prefetch/inst prefetch). Includes L4", + "PublicDescription": "" + }, + {, + "EventCode": "0x3c05e", + "EventName": "PM_MEM_RWITM", + "BriefDescription": "Memory rwitm for this lpar", + "PublicDescription": "" + }, + {, + "EventCode": "0x3006e", + "EventName": "PM_NEST_REF_CLK", + "BriefDescription": "Multiply by 4 to obtain the number of PB cycles", + "PublicDescription": "Nest reference clocks" + }, + {, + "EventCode": "0x10054", + "EventName": "PM_PUMP_CPRED", + "BriefDescription": "Pump prediction correct. Counts across all types of pumps for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", + "PublicDescription": "Pump prediction correct. Counts across all types of pumpsfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)" + }, + {, + "EventCode": "0x40052", + "EventName": "PM_PUMP_MPRED", + "BriefDescription": "Pump misprediction. Counts across all types of pumps for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", + "PublicDescription": "Pump Mis prediction Counts across all types of pumpsfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)" + }, + {, + "EventCode": "0x30050", + "EventName": "PM_SYS_PUMP_CPRED", + "BriefDescription": "Initial and Final Pump Scope was system pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", + "PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was system pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)" + }, + {, + "EventCode": "0x30052", + "EventName": "PM_SYS_PUMP_MPRED", + "BriefDescription": "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", + "PublicDescription": "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or" + }, + {, + "EventCode": "0x40050", + "EventName": "PM_SYS_PUMP_MPRED_RTY", + "BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", + "PublicDescription": "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)" + }, +] diff --git a/tools/perf/pmu-events/arch/powerpc/power8/other.json b/tools/perf/pmu-events/arch/powerpc/power8/other.json new file mode 100644 index 000000000000..704302c3e67d --- /dev/null +++ b/tools/perf/pmu-events/arch/powerpc/power8/other.json @@ -0,0 +1,4064 @@ +[ + {, + "EventCode": "0x1f05e", + "EventName": "PM_1LPAR_CYC", + "BriefDescription": "Number of cycles in single lpar mode. All threads in the core are assigned to the same lpar", + "PublicDescription": "" + }, + {, + "EventCode": "0x2006e", + "EventName": "PM_2LPAR_CYC", + "BriefDescription": "Cycles in 2-lpar mode. Threads 0-3 belong to Lpar0 and threads 4-7 belong to Lpar1", + "PublicDescription": "Number of cycles in 2 lpar mode" + }, + {, + "EventCode": "0x4e05e", + "EventName": "PM_4LPAR_CYC", + "BriefDescription": "Number of cycles in 4 LPAR mode. Threads 0-1 belong to lpar0, threads 2-3 belong to lpar1, threads 4-5 belong to lpar2, and threads 6-7 belong to lpar3", + "PublicDescription": "" + }, + {, + "EventCode": "0x610050", + "EventName": "PM_ALL_CHIP_PUMP_CPRED", + "BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)", + "PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for all data types ( demand load,data,inst prefetch,inst fetch,xlate (I or d)" + }, + {, + "EventCode": "0x520050", + "EventName": "PM_ALL_GRP_PUMP_CPRED", + "BriefDescription": "Initial and Final Pump Scope and data sourced across this scope was group pump for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)", + "PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was group pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)" + }, + {, + "EventCode": "0x620052", + "EventName": "PM_ALL_GRP_PUMP_MPRED", + "BriefDescription": "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)", + "PublicDescription": "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro" + }, + {, + "EventCode": "0x610052", + "EventName": "PM_ALL_GRP_PUMP_MPRED_RTY", + "BriefDescription": "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)", + "PublicDescription": "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)" + }, + {, + "EventCode": "0x610054", + "EventName": "PM_ALL_PUMP_CPRED", + "BriefDescription": "Pump prediction correct. Counts across all types of pumps for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)", + "PublicDescription": "Pump prediction correct. Counts across all types of pumpsfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)" + }, + {, + "EventCode": "0x640052", + "EventName": "PM_ALL_PUMP_MPRED", + "BriefDescription": "Pump misprediction. Counts across all types of pumps for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)", + "PublicDescription": "Pump Mis prediction Counts across all types of pumpsfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)" + }, + {, + "EventCode": "0x630050", + "EventName": "PM_ALL_SYS_PUMP_CPRED", + "BriefDescription": "Initial and Final Pump Scope was system pump for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)", + "PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was system pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)" + }, + {, + "EventCode": "0x630052", + "EventName": "PM_ALL_SYS_PUMP_MPRED", + "BriefDescription": "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)", + "PublicDescription": "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or" + }, + {, + "EventCode": "0x640050", + "EventName": "PM_ALL_SYS_PUMP_MPRED_RTY", + "BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)", + "PublicDescription": "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)" + }, + {, + "EventCode": "0x4082", + "EventName": "PM_BANK_CONFLICT", + "BriefDescription": "Read blocked due to interleave conflict. The ifar logic will detect an interleave conflict and kill the data that was read that cycle", + "PublicDescription": "" + }, + {, + "EventCode": "0x5086", + "EventName": "PM_BR_BC_8", + "BriefDescription": "Pairable BC+8 branch that has not been converted to a Resolve Finished in the BRU pipeline", + "PublicDescription": "" + }, + {, + "EventCode": "0x5084", + "EventName": "PM_BR_BC_8_CONV", + "BriefDescription": "Pairable BC+8 branch that was converted to a Resolve Finished in the BRU pipeline", + "PublicDescription": "" + }, + {, + "EventCode": "0x40ac", + "EventName": "PM_BR_MPRED_CCACHE", + "BriefDescription": "Conditional Branch Completed that was Mispredicted due to the Count Cache Target Prediction", + "PublicDescription": "" + }, + {, + "EventCode": "0x40b8", + "EventName": "PM_BR_MPRED_CR", + "BriefDescription": "Conditional Branch Completed that was Mispredicted due to the BHT Direction Prediction (taken/not taken)", + "PublicDescription": "" + }, + {, + "EventCode": "0x40ae", + "EventName": "PM_BR_MPRED_LSTACK", + "BriefDescription": "Conditional Branch Completed that was Mispredicted due to the Link Stack Target Prediction", + "PublicDescription": "" + }, + {, + "EventCode": "0x40ba", + "EventName": "PM_BR_MPRED_TA", + "BriefDescription": "Conditional Branch Completed that was Mispredicted due to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that resolved Taken set this event", + "PublicDescription": "" + }, + {, + "EventCode": "0x10138", + "EventName": "PM_BR_MRK_2PATH", + "BriefDescription": "marked two path branch", + "PublicDescription": "" + }, + {, + "EventCode": "0x409c", + "EventName": "PM_BR_PRED_BR0", + "BriefDescription": "Conditional Branch Completed on BR0 (1st branch in group) in which the HW predicted the Direction or Target", + "PublicDescription": "" + }, + {, + "EventCode": "0x409e", + "EventName": "PM_BR_PRED_BR1", + "BriefDescription": "Conditional Branch Completed on BR1 (2nd branch in group) in which the HW predicted the Direction or Target. Note: BR1 can only be used in Single Thread Mode. In all of the SMT modes, only one branch can complete, thus BR1 is unused", + "PublicDescription": "" + }, + {, + "EventCode": "0x489c", + "EventName": "PM_BR_PRED_BR_CMPL", + "BriefDescription": "Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred(0) OR if_pc_br0_br_pred(1)", + "PublicDescription": "IFU" + }, + {, + "EventCode": "0x40a4", + "EventName": "PM_BR_PRED_CCACHE_BR0", + "BriefDescription": "Conditional Branch Completed on BR0 that used the Count Cache for Target Prediction", + "PublicDescription": "" + }, + {, + "EventCode": "0x40a6", + "EventName": "PM_BR_PRED_CCACHE_BR1", + "BriefDescription": "Conditional Branch Completed on BR1 that used the Count Cache for Target Prediction", + "PublicDescription": "" + }, + {, + "EventCode": "0x48a4", + "EventName": "PM_BR_PRED_CCACHE_CMPL", + "BriefDescription": "Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred(0) AND if_pc_br0_pred_type", + "PublicDescription": "IFU" + }, + {, + "EventCode": "0x40b0", + "EventName": "PM_BR_PRED_CR_BR0", + "BriefDescription": "Conditional Branch Completed on BR0 that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and branches", + "PublicDescription": "" + }, + {, + "EventCode": "0x40b2", + "EventName": "PM_BR_PRED_CR_BR1", + "BriefDescription": "Conditional Branch Completed on BR1 that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and branches", + "PublicDescription": "" + }, + {, + "EventCode": "0x48b0", + "EventName": "PM_BR_PRED_CR_CMPL", + "BriefDescription": "Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred(1)='1'", + "PublicDescription": "IFU" + }, + {, + "EventCode": "0x40a8", + "EventName": "PM_BR_PRED_LSTACK_BR0", + "BriefDescription": "Conditional Branch Completed on BR0 that used the Link Stack for Target Prediction", + "PublicDescription": "" + }, + {, + "EventCode": "0x40aa", + "EventName": "PM_BR_PRED_LSTACK_BR1", + "BriefDescription": "Conditional Branch Completed on BR1 that used the Link Stack for Target Prediction", + "PublicDescription": "" + }, + {, + "EventCode": "0x48a8", + "EventName": "PM_BR_PRED_LSTACK_CMPL", + "BriefDescription": "Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred(0) AND (not if_pc_br0_pred_type)", + "PublicDescription": "IFU" + }, + {, + "EventCode": "0x40b4", + "EventName": "PM_BR_PRED_TA_BR0", + "BriefDescription": "Conditional Branch Completed on BR0 that had its target address predicted. Only XL-form branches set this event", + "PublicDescription": "" + }, + {, + "EventCode": "0x40b6", + "EventName": "PM_BR_PRED_TA_BR1", + "BriefDescription": "Conditional Branch Completed on BR1 that had its target address predicted. Only XL-form branches set this event", + "PublicDescription": "" + }, + {, + "EventCode": "0x48b4", + "EventName": "PM_BR_PRED_TA_CMPL", + "BriefDescription": "Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred(0)='1'", + "PublicDescription": "IFU" + }, + {, + "EventCode": "0x40a0", + "EventName": "PM_BR_UNCOND_BR0", + "BriefDescription": "Unconditional Branch Completed on BR0. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was coverted to a Resolve", + "PublicDescription": "" + }, + {, + "EventCode": "0x40a2", + "EventName": "PM_BR_UNCOND_BR1", + "BriefDescription": "Unconditional Branch Completed on BR1. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was coverted to a Resolve", + "PublicDescription": "" + }, + {, + "EventCode": "0x48a0", + "EventName": "PM_BR_UNCOND_CMPL", + "BriefDescription": "Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred=00 AND if_pc_br0_completed", + "PublicDescription": "IFU" + }, + {, + "EventCode": "0x3094", + "EventName": "PM_CASTOUT_ISSUED", + "BriefDescription": "Castouts issued", + "PublicDescription": "" + }, + {, + "EventCode": "0x3096", + "EventName": "PM_CASTOUT_ISSUED_GPR", + "BriefDescription": "Castouts issued GPR", + "PublicDescription": "" + }, + {, + "EventCode": "0x2090", + "EventName": "PM_CLB_HELD", + "BriefDescription": "CLB Hold: Any Reason", + "PublicDescription": "" + }, + {, + "EventCode": "0x2d018", + "EventName": "PM_CMPLU_STALL_BRU_CRU", + "BriefDescription": "Completion stall due to IFU", + "PublicDescription": "" + }, + {, + "EventCode": "0x30026", + "EventName": "PM_CMPLU_STALL_COQ_FULL", + "BriefDescription": "Completion stall due to CO q full", + "PublicDescription": "" + }, + {, + "EventCode": "0x30038", + "EventName": "PM_CMPLU_STALL_FLUSH", + "BriefDescription": "completion stall due to flush by own thread", + "PublicDescription": "" + }, + {, + "EventCode": "0x30028", + "EventName": "PM_CMPLU_STALL_MEM_ECC_DELAY", + "BriefDescription": "Completion stall due to mem ECC delay", + "PublicDescription": "" + }, + {, + "EventCode": "0x2e01c", + "EventName": "PM_CMPLU_STALL_NO_NTF", + "BriefDescription": "Completion stall due to nop", + "PublicDescription": "" + }, + {, + "EventCode": "0x2e01e", + "EventName": "PM_CMPLU_STALL_NTCG_FLUSH", + "BriefDescription": "Completion stall due to ntcg flush", + "PublicDescription": "Completion stall due to reject (load hit store)" + }, + {, + "EventCode": "0x4c010", + "EventName": "PM_CMPLU_STALL_REJECT", + "BriefDescription": "Completion stall due to LSU reject", + "PublicDescription": "" + }, + {, + "EventCode": "0x2c01a", + "EventName": "PM_CMPLU_STALL_REJECT_LHS", + "BriefDescription": "Completion stall due to reject (load hit store)", + "PublicDescription": "" + }, + {, + "EventCode": "0x4c014", + "EventName": "PM_CMPLU_STALL_REJ_LMQ_FULL", + "BriefDescription": "Completion stall due to LSU reject LMQ full", + "PublicDescription": "" + }, + {, + "EventCode": "0x4d010", + "EventName": "PM_CMPLU_STALL_SCALAR", + "BriefDescription": "Completion stall due to VSU scalar instruction", + "PublicDescription": "" + }, + {, + "EventCode": "0x2d010", + "EventName": "PM_CMPLU_STALL_SCALAR_LONG", + "BriefDescription": "Completion stall due to VSU scalar long latency instruction", + "PublicDescription": "" + }, + {, + "EventCode": "0x2c014", + "EventName": "PM_CMPLU_STALL_STORE", + "BriefDescription": "Completion stall by stores this includes store agen finishes in pipe LS0/LS1 and store data finishes in LS2/LS3", + "PublicDescription": "" + }, + {, + "EventCode": "0x2d014", + "EventName": "PM_CMPLU_STALL_VECTOR", + "BriefDescription": "Completion stall due to VSU vector instruction", + "PublicDescription": "" + }, + {, + "EventCode": "0x4d012", + "EventName": "PM_CMPLU_STALL_VECTOR_LONG", + "BriefDescription": "Completion stall due to VSU vector long instruction", + "PublicDescription": "" + }, + {, + "EventCode": "0x2d012", + "EventName": "PM_CMPLU_STALL_VSU", + "BriefDescription": "Completion stall due to VSU instruction", + "PublicDescription": "" + }, + {, + "EventCode": "0x16083", + "EventName": "PM_CO0_ALLOC", + "BriefDescription": "CO mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point)", + "PublicDescription": "0.0" + }, + {, + "EventCode": "0x16082", + "EventName": "PM_CO0_BUSY", + "BriefDescription": "CO mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point)", + "PublicDescription": "" + }, + {, + "EventCode": "0x517082", + "EventName": "PM_CO_DISP_FAIL", + "BriefDescription": "CO dispatch failed due to all CO machines being busy", + "PublicDescription": "" + }, + {, + "EventCode": "0x527084", + "EventName": "PM_CO_TM_SC_FOOTPRINT", + "BriefDescription": "L2 did a cleanifdirty CO to the L3 (ie created an SC line in the L3)", + "PublicDescription": "" + }, + {, + "EventCode": "0x3608a", + "EventName": "PM_CO_USAGE", + "BriefDescription": "Continuous 16 cycle(2to1) window where this signals rotates thru sampling each L2 CO machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running", + "PublicDescription": "" + }, + {, + "EventCode": "0x40066", + "EventName": "PM_CRU_FIN", + "BriefDescription": "IFU Finished a (non-branch) instruction", + "PublicDescription": "" + }, + {, + "EventCode": "0x61c050", + "EventName": "PM_DATA_ALL_CHIP_PUMP_CPRED", + "BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for either demand loads or data prefetch", + "PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for a demand load" + }, + {, + "EventCode": "0x64c048", + "EventName": "PM_DATA_ALL_FROM_DL2L3_MOD", + "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either demand loads or data prefetch", + "PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x63c048", + "EventName": "PM_DATA_ALL_FROM_DL2L3_SHR", + "BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either demand loads or data prefetch", + "PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x63c04c", + "EventName": "PM_DATA_ALL_FROM_DL4", + "BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to either demand loads or data prefetch", + "PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x64c04c", + "EventName": "PM_DATA_ALL_FROM_DMEM", + "BriefDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to either demand loads or data prefetch", + "PublicDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x61c042", + "EventName": "PM_DATA_ALL_FROM_L2", + "BriefDescription": "The processor's data cache was reloaded from local core's L2 due to either demand loads or data prefetch", + "PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x64c046", + "EventName": "PM_DATA_ALL_FROM_L21_MOD", + "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to either demand loads or data prefetch", + "PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x63c046", + "EventName": "PM_DATA_ALL_FROM_L21_SHR", + "BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to either demand loads or data prefetch", + "PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x61c04e", + "EventName": "PM_DATA_ALL_FROM_L2MISS_MOD", + "BriefDescription": "The processor's data cache was reloaded from a localtion other than the local core's L2 due to either demand loads or data prefetch", + "PublicDescription": "The processor's data cache was reloaded from a localtion other than the local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x63c040", + "EventName": "PM_DATA_ALL_FROM_L2_DISP_CONFLICT_LDHITST", + "BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to either demand loads or data prefetch", + "PublicDescription": "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x64c040", + "EventName": "PM_DATA_ALL_FROM_L2_DISP_CONFLICT_OTHER", + "BriefDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to either demand loads or data prefetch", + "PublicDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x62c040", + "EventName": "PM_DATA_ALL_FROM_L2_MEPF", + "BriefDescription": "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to either demand loads or data prefetch", + "PublicDescription": "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x61c040", + "EventName": "PM_DATA_ALL_FROM_L2_NO_CONFLICT", + "BriefDescription": "The processor's data cache was reloaded from local core's L2 without conflict due to either demand loads or data prefetch", + "PublicDescription": "The processor's data cache was reloaded from local core's L2 without conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x64c042", + "EventName": "PM_DATA_ALL_FROM_L3", + "BriefDescription": "The processor's data cache was reloaded from local core's L3 due to either demand loads or data prefetch", + "PublicDescription": "The processor's data cache was reloaded from local core's L3 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x64c044", + "EventName": "PM_DATA_ALL_FROM_L31_ECO_MOD", + "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to either demand loads or data prefetch", + "PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x63c044", + "EventName": "PM_DATA_ALL_FROM_L31_ECO_SHR", + "BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to either demand loads or data prefetch", + "PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x62c044", + "EventName": "PM_DATA_ALL_FROM_L31_MOD", + "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to either demand loads or data prefetch", + "PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x61c046", + "EventName": "PM_DATA_ALL_FROM_L31_SHR", + "BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to either demand loads or data prefetch", + "PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x64c04e", + "EventName": "PM_DATA_ALL_FROM_L3MISS_MOD", + "BriefDescription": "The processor's data cache was reloaded from a localtion other than the local core's L3 due to either demand loads or data prefetch", + "PublicDescription": "The processor's data cache was reloaded from a localtion other than the local core's L3 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x63c042", + "EventName": "PM_DATA_ALL_FROM_L3_DISP_CONFLICT", + "BriefDescription": "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to either demand loads or data prefetch", + "PublicDescription": "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x62c042", + "EventName": "PM_DATA_ALL_FROM_L3_MEPF", + "BriefDescription": "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to either demand loads or data prefetch", + "PublicDescription": "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x61c044", + "EventName": "PM_DATA_ALL_FROM_L3_NO_CONFLICT", + "BriefDescription": "The processor's data cache was reloaded from local core's L3 without conflict due to either demand loads or data prefetch", + "PublicDescription": "The processor's data cache was reloaded from local core's L3 without conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x61c04c", + "EventName": "PM_DATA_ALL_FROM_LL4", + "BriefDescription": "The processor's data cache was reloaded from the local chip's L4 cache due to either demand loads or data prefetch", + "PublicDescription": "The processor's data cache was reloaded from the local chip's L4 cache due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x62c048", + "EventName": "PM_DATA_ALL_FROM_LMEM", + "BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to either demand loads or data prefetch", + "PublicDescription": "The processor's data cache was reloaded from the local chip's Memory due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x62c04c", + "EventName": "PM_DATA_ALL_FROM_MEMORY", + "BriefDescription": "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to either demand loads or data prefetch", + "PublicDescription": "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x64c04a", + "EventName": "PM_DATA_ALL_FROM_OFF_CHIP_CACHE", + "BriefDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to either demand loads or data prefetch", + "PublicDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x61c048", + "EventName": "PM_DATA_ALL_FROM_ON_CHIP_CACHE", + "BriefDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to either demand loads or data prefetch", + "PublicDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x62c046", + "EventName": "PM_DATA_ALL_FROM_RL2L3_MOD", + "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either demand loads or data prefetch", + "PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x61c04a", + "EventName": "PM_DATA_ALL_FROM_RL2L3_SHR", + "BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either demand loads or data prefetch", + "PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x62c04a", + "EventName": "PM_DATA_ALL_FROM_RL4", + "BriefDescription": "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to either demand loads or data prefetch", + "PublicDescription": "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x63c04a", + "EventName": "PM_DATA_ALL_FROM_RMEM", + "BriefDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to either demand loads or data prefetch", + "PublicDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x62c050", + "EventName": "PM_DATA_ALL_GRP_PUMP_CPRED", + "BriefDescription": "Initial and Final Pump Scope was group pump (prediction=correct) for either demand loads or data prefetch", + "PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was group pump for a demand load" + }, + {, + "EventCode": "0x62c052", + "EventName": "PM_DATA_ALL_GRP_PUMP_MPRED", + "BriefDescription": "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for either demand loads or data prefetch", + "PublicDescription": "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro" + }, + {, + "EventCode": "0x61c052", + "EventName": "PM_DATA_ALL_GRP_PUMP_MPRED_RTY", + "BriefDescription": "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for either demand loads or data prefetch", + "PublicDescription": "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor a demand load" + }, + {, + "EventCode": "0x61c054", + "EventName": "PM_DATA_ALL_PUMP_CPRED", + "BriefDescription": "Pump prediction correct. Counts across all types of pumps for either demand loads or data prefetch", + "PublicDescription": "Pump prediction correct. Counts across all types of pumps for a demand load" + }, + {, + "EventCode": "0x64c052", + "EventName": "PM_DATA_ALL_PUMP_MPRED", + "BriefDescription": "Pump misprediction. Counts across all types of pumps for either demand loads or data prefetch", + "PublicDescription": "Pump Mis prediction Counts across all types of pumpsfor a demand load" + }, + {, + "EventCode": "0x63c050", + "EventName": "PM_DATA_ALL_SYS_PUMP_CPRED", + "BriefDescription": "Initial and Final Pump Scope was system pump (prediction=correct) for either demand loads or data prefetch", + "PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was system pump for a demand load" + }, + {, + "EventCode": "0x63c052", + "EventName": "PM_DATA_ALL_SYS_PUMP_MPRED", + "BriefDescription": "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for either demand loads or data prefetch", + "PublicDescription": "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or" + }, + {, + "EventCode": "0x64c050", + "EventName": "PM_DATA_ALL_SYS_PUMP_MPRED_RTY", + "BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for either demand loads or data prefetch", + "PublicDescription": "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for a demand load" + }, + {, + "EventCode": "0x4c046", + "EventName": "PM_DATA_FROM_L21_MOD", + "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a demand load", + "PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x3c046", + "EventName": "PM_DATA_FROM_L21_SHR", + "BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a demand load", + "PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x4c044", + "EventName": "PM_DATA_FROM_L31_ECO_MOD", + "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a demand load", + "PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x3c044", + "EventName": "PM_DATA_FROM_L31_ECO_SHR", + "BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a demand load", + "PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x2c044", + "EventName": "PM_DATA_FROM_L31_MOD", + "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to a demand load", + "PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x1c046", + "EventName": "PM_DATA_FROM_L31_SHR", + "BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to a demand load", + "PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" + }, + {, + "EventCode": "0x400fe", + "EventName": "PM_DATA_FROM_MEM", + "BriefDescription": "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a demand load", + "PublicDescription": "Data cache reload from memory (including L4)" + }, + {, + "EventCode": "0xe0bc", + "EventName": "PM_DC_COLLISIONS", + "BriefDescription": "DATA Cache collisions", + "PublicDescription": "DATA Cache collisions42" + }, + {, + "EventCode": "0x1e050", + "EventName": "PM_DC_PREF_STREAM_ALLOC", + "BriefDescription": "Stream marked valid. The stream could have been allocated through the hardware prefetch mechanism or through software. This is combined ls0 and ls1", + "PublicDescription": "" + }, + {, + "EventCode": "0x2e050", + "EventName": "PM_DC_PREF_STREAM_CONF", + "BriefDescription": "A demand load referenced a line in an active prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. Combine up + down", + "PublicDescription": "" + }, + {, + "EventCode": "0x4e050", + "EventName": "PM_DC_PREF_STREAM_FUZZY_CONF", + "BriefDescription": "A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up)", + "PublicDescription": "" + }, + {, + "EventCode": "0x3e050", + "EventName": "PM_DC_PREF_STREAM_STRIDED_CONF", + "BriefDescription": "A demand load referenced a line in an active strided prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software", + "PublicDescription": "" + }, + {, + "EventCode": "0xb0ba", + "EventName": "PM_DFU", + "BriefDescription": "Finish DFU (all finish)", + "PublicDescription": "" + }, + {, + "EventCode": "0xb0be", + "EventName": "PM_DFU_DCFFIX", + "BriefDescription": "Convert from fixed opcode finish (dcffix,dcffixq)", + "PublicDescription": "" + }, + {, + "EventCode": "0xb0bc", + "EventName": "PM_DFU_DENBCD", + "BriefDescription": "BCD->DPD opcode finish (denbcd, denbcdq)", + "PublicDescription": "" + }, + {, + "EventCode": "0xb0b8", + "EventName": "PM_DFU_MC", + "BriefDescription": "Finish DFU multicycle", + "PublicDescription": "" + }, + {, + "EventCode": "0x2092", + "EventName": "PM_DISP_CLB_HELD_BAL", + "BriefDescription": "Dispatch/CLB Hold: Balance", + "PublicDescription": "" + }, + {, + "EventCode": "0x2094", + "EventName": "PM_DISP_CLB_HELD_RES", + "BriefDescription": "Dispatch/CLB Hold: Resource", + "PublicDescription": "" + }, + {, + "EventCode": "0x20a8", + "EventName": "PM_DISP_CLB_HELD_SB", + "BriefDescription": "Dispatch/CLB Hold: Scoreboard", + "PublicDescription": "" + }, + {, + "EventCode": "0x2098", + "EventName": "PM_DISP_CLB_HELD_SYNC", + "BriefDescription": "Dispatch/CLB Hold: Sync type instruction", + "PublicDescription": "" + }, + {, + "EventCode": "0x2096", + "EventName": "PM_DISP_CLB_HELD_TLBIE", + "BriefDescription": "Dispatch Hold: Due to TLBIE", + "PublicDescription": "" + }, + {, + "EventCode": "0x20006", + "EventName": "PM_DISP_HELD_IQ_FULL", + "BriefDescription": "Dispatch held due to Issue q full", + "PublicDescription": "" + }, + {, + "EventCode": "0x1002a", + "EventName": "PM_DISP_HELD_MAP_FULL", + "BriefDescription": "Dispatch for this thread was held because the Mappers were full", + "PublicDescription": "Dispatch held due to Mapper full" + }, + {, + "EventCode": "0x30018", + "EventName": "PM_DISP_HELD_SRQ_FULL", + "BriefDescription": "Dispatch held due SRQ no room", + "PublicDescription": "" + }, + {, + "EventCode": "0x30a6", + "EventName": "PM_DISP_HOLD_GCT_FULL", + "BriefDescription": "Dispatch Hold Due to no space in the GCT", + "PublicDescription": "" + }, + {, + "EventCode": "0x30008", + "EventName": "PM_DISP_WT", + "BriefDescription": "Dispatched Starved", + "PublicDescription": "Dispatched Starved (not held, nothing to dispatch)" + }, + {, + "EventCode": "0x4e046", + "EventName": "PM_DPTEG_FROM_L21_MOD", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x3e046", + "EventName": "PM_DPTEG_FROM_L21_SHR", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x3e040", + "EventName": "PM_DPTEG_FROM_L2_DISP_CONFLICT_LDHITST", + "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 with load hit store conflict due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x4e040", + "EventName": "PM_DPTEG_FROM_L2_DISP_CONFLICT_OTHER", + "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 with dispatch conflict due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x4e044", + "EventName": "PM_DPTEG_FROM_L31_ECO_MOD", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x3e044", + "EventName": "PM_DPTEG_FROM_L31_ECO_SHR", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x2e044", + "EventName": "PM_DPTEG_FROM_L31_MOD", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x1e046", + "EventName": "PM_DPTEG_FROM_L31_SHR", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x50a8", + "EventName": "PM_EAT_FORCE_MISPRED", + "BriefDescription": "XL-form branch was mispredicted due to the predicted target address missing from EAT. The EAT forces a mispredict in this case since there is no predicated target to validate. This is a rare case that may occur when the EAT is full and a branch is issue", + "PublicDescription": "" + }, + {, + "EventCode": "0x4084", + "EventName": "PM_EAT_FULL_CYC", + "BriefDescription": "Cycles No room in EAT", + "PublicDescription": "Cycles No room in EATSet on bank conflict and case where no ibuffers available" + }, + {, + "EventCode": "0x2080", + "EventName": "PM_EE_OFF_EXT_INT", + "BriefDescription": "Ee off and external interrupt", + "PublicDescription": "" + }, + {, + "EventCode": "0x20b4", + "EventName": "PM_FAV_TBEGIN", + "BriefDescription": "Dispatch time Favored tbegin", + "PublicDescription": "" + }, + {, + "EventCode": "0x100f4", + "EventName": "PM_FLOP", + "BriefDescription": "Floating Point Operation Finished", + "PublicDescription": "Floating Point Operations Finished" + }, + {, + "EventCode": "0xa0ae", + "EventName": "PM_FLOP_SUM_SCALAR", + "BriefDescription": "flops summary scalar instructions", + "PublicDescription": "" + }, + {, + "EventCode": "0xa0ac", + "EventName": "PM_FLOP_SUM_VEC", + "BriefDescription": "flops summary vector instructions", + "PublicDescription": "" + }, + {, + "EventCode": "0x2084", + "EventName": "PM_FLUSH_BR_MPRED", + "BriefDescription": "Flush caused by branch mispredict", + "PublicDescription": "" + }, + {, + "EventCode": "0x2082", + "EventName": "PM_FLUSH_DISP", + "BriefDescription": "Dispatch flush", + "PublicDescription": "" + }, + {, + "EventCode": "0x208c", + "EventName": "PM_FLUSH_DISP_SB", + "BriefDescription": "Dispatch Flush: Scoreboard", + "PublicDescription": "" + }, + {, + "EventCode": "0x2088", + "EventName": "PM_FLUSH_DISP_SYNC", + "BriefDescription": "Dispatch Flush: Sync", + "PublicDescription": "" + }, + {, + "EventCode": "0x208a", + "EventName": "PM_FLUSH_DISP_TLBIE", + "BriefDescription": "Dispatch Flush: TLBIE", + "PublicDescription": "" + }, + {, + "EventCode": "0x208e", + "EventName": "PM_FLUSH_LSU", + "BriefDescription": "Flush initiated by LSU", + "PublicDescription": "" + }, + {, + "EventCode": "0x2086", + "EventName": "PM_FLUSH_PARTIAL", + "BriefDescription": "Partial flush", + "PublicDescription": "" + }, + {, + "EventCode": "0xa0b0", + "EventName": "PM_FPU0_FCONV", + "BriefDescription": "Convert instruction executed", + "PublicDescription": "" + }, + {, + "EventCode": "0xa0b8", + "EventName": "PM_FPU0_FEST", + "BriefDescription": "Estimate instruction executed", + "PublicDescription": "" + }, + {, + "EventCode": "0xa0b4", + "EventName": "PM_FPU0_FRSP", + "BriefDescription": "Round to single precision instruction executed", + "PublicDescription": "" + }, + {, + "EventCode": "0xa0b2", + "EventName": "PM_FPU1_FCONV", + "BriefDescription": "Convert instruction executed", + "PublicDescription": "" + }, + {, + "EventCode": "0xa0ba", + "EventName": "PM_FPU1_FEST", + "BriefDescription": "Estimate instruction executed", + "PublicDescription": "" + }, + {, + "EventCode": "0xa0b6", + "EventName": "PM_FPU1_FRSP", + "BriefDescription": "Round to single precision instruction executed", + "PublicDescription": "" + }, + {, + "EventCode": "0x50b0", + "EventName": "PM_FUSION_TOC_GRP0_1", + "BriefDescription": "One pair of instructions fused with TOC in Group0", + "PublicDescription": "" + }, + {, + "EventCode": "0x50ae", + "EventName": "PM_FUSION_TOC_GRP0_2", + "BriefDescription": "Two pairs of instructions fused with TOCin Group0", + "PublicDescription": "" + }, + {, + "EventCode": "0x50ac", + "EventName": "PM_FUSION_TOC_GRP0_3", + "BriefDescription": "Three pairs of instructions fused with TOC in Group0", + "PublicDescription": "" + }, + {, + "EventCode": "0x50b2", + "EventName": "PM_FUSION_TOC_GRP1_1", + "BriefDescription": "One pair of instructions fused with TOX in Group1", + "PublicDescription": "" + }, + {, + "EventCode": "0x50b8", + "EventName": "PM_FUSION_VSX_GRP0_1", + "BriefDescription": "One pair of instructions fused with VSX in Group0", + "PublicDescription": "" + }, + {, + "EventCode": "0x50b6", + "EventName": "PM_FUSION_VSX_GRP0_2", + "BriefDescription": "Two pairs of instructions fused with VSX in Group0", + "PublicDescription": "" + }, + {, + "EventCode": "0x50b4", + "EventName": "PM_FUSION_VSX_GRP0_3", + "BriefDescription": "Three pairs of instructions fused with VSX in Group0", + "PublicDescription": "" + }, + {, + "EventCode": "0x50ba", + "EventName": "PM_FUSION_VSX_GRP1_1", + "BriefDescription": "One pair of instructions fused with VSX in Group1", + "PublicDescription": "" + }, + {, + "EventCode": "0x3000e", + "EventName": "PM_FXU0_BUSY_FXU1_IDLE", + "BriefDescription": "fxu0 busy and fxu1 idle", + "PublicDescription": "" + }, + {, + "EventCode": "0x10004", + "EventName": "PM_FXU0_FIN", + "BriefDescription": "The fixed point unit Unit 0 finished an instruction. Instructions that finish may not necessary complete", + "PublicDescription": "FXU0 Finished" + }, + {, + "EventCode": "0x4000e", + "EventName": "PM_FXU1_BUSY_FXU0_IDLE", + "BriefDescription": "fxu0 idle and fxu1 busy", + "PublicDescription": "" + }, + {, + "EventCode": "0x40004", + "EventName": "PM_FXU1_FIN", + "BriefDescription": "FXU1 Finished", + "PublicDescription": "" + }, + {, + "EventCode": "0x20008", + "EventName": "PM_GCT_EMPTY_CYC", + "BriefDescription": "No itags assigned either thread (GCT Empty)", + "PublicDescription": "" + }, + {, + "EventCode": "0x30a4", + "EventName": "PM_GCT_MERGE", + "BriefDescription": "Group dispatched on a merged GCT empty. GCT entries can be merged only within the same thread", + "PublicDescription": "" + }, + {, + "EventCode": "0x4d01e", + "EventName": "PM_GCT_NOSLOT_BR_MPRED", + "BriefDescription": "Gct empty for this thread due to branch mispred", + "PublicDescription": "" + }, + {, + "EventCode": "0x4d01a", + "EventName": "PM_GCT_NOSLOT_BR_MPRED_ICMISS", + "BriefDescription": "Gct empty for this thread due to Icache Miss and branch mispred", + "PublicDescription": "" + }, + {, + "EventCode": "0x100f8", + "EventName": "PM_GCT_NOSLOT_CYC", + "BriefDescription": "No itags assigned", + "PublicDescription": "Pipeline empty (No itags assigned , no GCT slots used)" + }, + {, + "EventCode": "0x2d01e", + "EventName": "PM_GCT_NOSLOT_DISP_HELD_ISSQ", + "BriefDescription": "Gct empty for this thread due to dispatch hold on this thread due to Issue q full", + "PublicDescription": "" + }, + {, + "EventCode": "0x4d01c", + "EventName": "PM_GCT_NOSLOT_DISP_HELD_MAP", + "BriefDescription": "Gct empty for this thread due to dispatch hold on this thread due to Mapper full", + "PublicDescription": "" + }, + {, + "EventCode": "0x2e010", + "EventName": "PM_GCT_NOSLOT_DISP_HELD_OTHER", + "BriefDescription": "Gct empty for this thread due to dispatch hold on this thread due to sync", + "PublicDescription": "" + }, + {, + "EventCode": "0x2d01c", + "EventName": "PM_GCT_NOSLOT_DISP_HELD_SRQ", + "BriefDescription": "Gct empty for this thread due to dispatch hold on this thread due to SRQ full", + "PublicDescription": "" + }, + {, + "EventCode": "0x4e010", + "EventName": "PM_GCT_NOSLOT_IC_L3MISS", + "BriefDescription": "Gct empty for this thread due to icach l3 miss", + "PublicDescription": "" + }, + {, + "EventCode": "0x2d01a", + "EventName": "PM_GCT_NOSLOT_IC_MISS", + "BriefDescription": "Gct empty for this thread due to Icache Miss", + "PublicDescription": "" + }, + {, + "EventCode": "0x20a2", + "EventName": "PM_GCT_UTIL_11_14_ENTRIES", + "BriefDescription": "GCT Utilization 11-14 entries", + "PublicDescription": "" + }, + {, + "EventCode": "0x20a4", + "EventName": "PM_GCT_UTIL_15_17_ENTRIES", + "BriefDescription": "GCT Utilization 15-17 entries", + "PublicDescription": "" + }, + {, + "EventCode": "0x20a6", + "EventName": "PM_GCT_UTIL_18_ENTRIES", + "BriefDescription": "GCT Utilization 18+ entries", + "PublicDescription": "" + }, + {, + "EventCode": "0x209c", + "EventName": "PM_GCT_UTIL_1_2_ENTRIES", + "BriefDescription": "GCT Utilization 1-2 entries", + "PublicDescription": "" + }, + {, + "EventCode": "0x209e", + "EventName": "PM_GCT_UTIL_3_6_ENTRIES", + "BriefDescription": "GCT Utilization 3-6 entries", + "PublicDescription": "" + }, + {, + "EventCode": "0x20a0", + "EventName": "PM_GCT_UTIL_7_10_ENTRIES", + "BriefDescription": "GCT Utilization 7-10 entries", + "PublicDescription": "" + }, + {, + "EventCode": "0x1000a", + "EventName": "PM_GRP_BR_MPRED_NONSPEC", + "BriefDescription": "Group experienced non-speculative branch redirect", + "PublicDescription": "Group experienced Non-speculative br mispredicct" + }, + {, + "EventCode": "0x30004", + "EventName": "PM_GRP_CMPL", + "BriefDescription": "group completed", + "PublicDescription": "" + }, + {, + "EventCode": "0x3000a", + "EventName": "PM_GRP_DISP", + "BriefDescription": "group dispatch", + "PublicDescription": "dispatch_success (Group Dispatched)" + }, + {, + "EventCode": "0x1000c", + "EventName": "PM_GRP_IC_MISS_NONSPEC", + "BriefDescription": "Group experienced non-speculative I cache miss", + "PublicDescription": "Group experi enced Non-specu lative I cache miss" + }, + {, + "EventCode": "0x10130", + "EventName": "PM_GRP_MRK", + "BriefDescription": "Instruction Marked", + "PublicDescription": "Instruction marked in idu" + }, + {, + "EventCode": "0x509c", + "EventName": "PM_GRP_NON_FULL_GROUP", + "BriefDescription": "GROUPs where we did not have 6 non branch instructions in the group(ST mode), in SMT mode 3 non branches", + "PublicDescription": "" + }, + {, + "EventCode": "0x50a4", + "EventName": "PM_GRP_TERM_2ND_BRANCH", + "BriefDescription": "There were enough instructions in the Ibuffer, but 2nd branch ends group", + "PublicDescription": "" + }, + {, + "EventCode": "0x50a6", + "EventName": "PM_GRP_TERM_FPU_AFTER_BR", + "BriefDescription": "There were enough instructions in the Ibuffer, but FPU OP IN same group after a branch terminates a group, cant do partial flushes", + "PublicDescription": "" + }, + {, + "EventCode": "0x509e", + "EventName": "PM_GRP_TERM_NOINST", + "BriefDescription": "Do not fill every slot in the group, Not enough instructions in the Ibuffer. This includes cases where the group started with enough instructions, but some got knocked out by a cache miss or branch redirect (which would also empty the Ibuffer)", + "PublicDescription": "" + }, + {, + "EventCode": "0x50a0", + "EventName": "PM_GRP_TERM_OTHER", + "BriefDescription": "There were enough instructions in the Ibuffer, but the group terminated early for some other reason, most likely due to a First or Last", + "PublicDescription": "" + }, + {, + "EventCode": "0x50a2", + "EventName": "PM_GRP_TERM_SLOT_LIMIT", + "BriefDescription": "There were enough instructions in the Ibuffer, but 3 src RA/RB/RC , 2 way crack caused a group termination", + "PublicDescription": "" + }, + {, + "EventCode": "0x4086", + "EventName": "PM_IBUF_FULL_CYC", + "BriefDescription": "Cycles No room in ibuff", + "PublicDescription": "Cycles No room in ibufffully qualified transfer (if5 valid)" + }, + {, + "EventCode": "0x4098", + "EventName": "PM_IC_DEMAND_L2_BHT_REDIRECT", + "BriefDescription": "L2 I cache demand request due to BHT redirect, branch redirect ( 2 bubbles 3 cycles)", + "PublicDescription": "" + }, + {, + "EventCode": "0x409a", + "EventName": "PM_IC_DEMAND_L2_BR_REDIRECT", + "BriefDescription": "L2 I cache demand request due to branch Mispredict ( 15 cycle path)", + "PublicDescription": "" + }, + {, + "EventCode": "0x4088", + "EventName": "PM_IC_DEMAND_REQ", + "BriefDescription": "Demand Instruction fetch request", + "PublicDescription": "" + }, + {, + "EventCode": "0x508a", + "EventName": "PM_IC_INVALIDATE", + "BriefDescription": "Ic line invalidated", + "PublicDescription": "" + }, + {, + "EventCode": "0x4092", + "EventName": "PM_IC_PREF_CANCEL_HIT", + "BriefDescription": "Prefetch Canceled due to icache hit", + "PublicDescription": "" + }, + {, + "EventCode": "0x4094", + "EventName": "PM_IC_PREF_CANCEL_L2", + "BriefDescription": "L2 Squashed request", + "PublicDescription": "" + }, + {, + "EventCode": "0x4090", + "EventName": "PM_IC_PREF_CANCEL_PAGE", + "BriefDescription": "Prefetch Canceled due to page boundary", + "PublicDescription": "" + }, + {, + "EventCode": "0x408a", + "EventName": "PM_IC_PREF_REQ", + "BriefDescription": "Instruction prefetch requests", + "PublicDescription": "" + }, + {, + "EventCode": "0x408e", + "EventName": "PM_IC_PREF_WRITE", + "BriefDescription": "Instruction prefetch written into IL1", + "PublicDescription": "" + }, + {, + "EventCode": "0x4096", + "EventName": "PM_IC_RELOAD_PRIVATE", + "BriefDescription": "Reloading line was brought in private for a specific thread. Most lines are brought in shared for all eight thrreads. If RA does not match then invalidates and then brings it shared to other thread. In P7 line brought in private , then line was invalidat", + "PublicDescription": "" + }, + {, + "EventCode": "0x5088", + "EventName": "PM_IFU_L2_TOUCH", + "BriefDescription": "L2 touch to update MRU on a line", + "PublicDescription": "" + }, + {, + "EventCode": "0x514050", + "EventName": "PM_INST_ALL_CHIP_PUMP_CPRED", + "BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for instruction fetches and prefetches", + "PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for an instruction fetch" + }, + {, + "EventCode": "0x544048", + "EventName": "PM_INST_ALL_FROM_DL2L3_MOD", + "BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to instruction fetches and prefetches", + "PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x534048", + "EventName": "PM_INST_ALL_FROM_DL2L3_SHR", + "BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to instruction fetches and prefetches", + "PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x53404c", + "EventName": "PM_INST_ALL_FROM_DL4", + "BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to instruction fetches and prefetches", + "PublicDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x54404c", + "EventName": "PM_INST_ALL_FROM_DMEM", + "BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Distant) due to instruction fetches and prefetches", + "PublicDescription": "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x514042", + "EventName": "PM_INST_ALL_FROM_L2", + "BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 due to instruction fetches and prefetches", + "PublicDescription": "The processor's Instruction cache was reloaded from local core's L2 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x544046", + "EventName": "PM_INST_ALL_FROM_L21_MOD", + "BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another core's L2 on the same chip due to instruction fetches and prefetches", + "PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another core's L2 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x534046", + "EventName": "PM_INST_ALL_FROM_L21_SHR", + "BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due to instruction fetches and prefetches", + "PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x51404e", + "EventName": "PM_INST_ALL_FROM_L2MISS", + "BriefDescription": "The processor's Instruction cache was reloaded from a localtion other than the local core's L2 due to instruction fetches and prefetches", + "PublicDescription": "The processor's Instruction cache was reloaded from a localtion other than the local core's L2 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x534040", + "EventName": "PM_INST_ALL_FROM_L2_DISP_CONFLICT_LDHITST", + "BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 with load hit store conflict due to instruction fetches and prefetches", + "PublicDescription": "The processor's Instruction cache was reloaded from local core's L2 with load hit store conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x544040", + "EventName": "PM_INST_ALL_FROM_L2_DISP_CONFLICT_OTHER", + "BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to instruction fetches and prefetches", + "PublicDescription": "The processor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x524040", + "EventName": "PM_INST_ALL_FROM_L2_MEPF", + "BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to instruction fetches and prefetches", + "PublicDescription": "The processor's Instruction cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x514040", + "EventName": "PM_INST_ALL_FROM_L2_NO_CONFLICT", + "BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 without conflict due to instruction fetches and prefetches", + "PublicDescription": "The processor's Instruction cache was reloaded from local core's L2 without conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x544042", + "EventName": "PM_INST_ALL_FROM_L3", + "BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 due to instruction fetches and prefetches", + "PublicDescription": "The processor's Instruction cache was reloaded from local core's L3 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x544044", + "EventName": "PM_INST_ALL_FROM_L31_ECO_MOD", + "BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to instruction fetches and prefetches", + "PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x534044", + "EventName": "PM_INST_ALL_FROM_L31_ECO_SHR", + "BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to instruction fetches and prefetches", + "PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x524044", + "EventName": "PM_INST_ALL_FROM_L31_MOD", + "BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another core's L3 on the same chip due to instruction fetches and prefetches", + "PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another core's L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x514046", + "EventName": "PM_INST_ALL_FROM_L31_SHR", + "BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another core's L3 on the same chip due to instruction fetches and prefetches", + "PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another core's L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x54404e", + "EventName": "PM_INST_ALL_FROM_L3MISS_MOD", + "BriefDescription": "The processor's Instruction cache was reloaded from a localtion other than the local core's L3 due to a instruction fetch", + "PublicDescription": "The processor's Instruction cache was reloaded from a localtion other than the local core's L3 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x534042", + "EventName": "PM_INST_ALL_FROM_L3_DISP_CONFLICT", + "BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to instruction fetches and prefetches", + "PublicDescription": "The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x524042", + "EventName": "PM_INST_ALL_FROM_L3_MEPF", + "BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to instruction fetches and prefetches", + "PublicDescription": "The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x514044", + "EventName": "PM_INST_ALL_FROM_L3_NO_CONFLICT", + "BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 without conflict due to instruction fetches and prefetches", + "PublicDescription": "The processor's Instruction cache was reloaded from local core's L3 without conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x51404c", + "EventName": "PM_INST_ALL_FROM_LL4", + "BriefDescription": "The processor's Instruction cache was reloaded from the local chip's L4 cache due to instruction fetches and prefetches", + "PublicDescription": "The processor's Instruction cache was reloaded from the local chip's L4 cache due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x524048", + "EventName": "PM_INST_ALL_FROM_LMEM", + "BriefDescription": "The processor's Instruction cache was reloaded from the local chip's Memory due to instruction fetches and prefetches", + "PublicDescription": "The processor's Instruction cache was reloaded from the local chip's Memory due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x52404c", + "EventName": "PM_INST_ALL_FROM_MEMORY", + "BriefDescription": "The processor's Instruction cache was reloaded from a memory location including L4 from local remote or distant due to instruction fetches and prefetches", + "PublicDescription": "The processor's Instruction cache was reloaded from a memory location including L4 from local remote or distant due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x54404a", + "EventName": "PM_INST_ALL_FROM_OFF_CHIP_CACHE", + "BriefDescription": "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to instruction fetches and prefetches", + "PublicDescription": "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x514048", + "EventName": "PM_INST_ALL_FROM_ON_CHIP_CACHE", + "BriefDescription": "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to instruction fetches and prefetches", + "PublicDescription": "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x524046", + "EventName": "PM_INST_ALL_FROM_RL2L3_MOD", + "BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to instruction fetches and prefetches", + "PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x51404a", + "EventName": "PM_INST_ALL_FROM_RL2L3_SHR", + "BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to instruction fetches and prefetches", + "PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x52404a", + "EventName": "PM_INST_ALL_FROM_RL4", + "BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to instruction fetches and prefetches", + "PublicDescription": "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x53404a", + "EventName": "PM_INST_ALL_FROM_RMEM", + "BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to instruction fetches and prefetches", + "PublicDescription": "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x524050", + "EventName": "PM_INST_ALL_GRP_PUMP_CPRED", + "BriefDescription": "Initial and Final Pump Scope was group pump (prediction=correct) for instruction fetches and prefetches", + "PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was group pump for an instruction fetch" + }, + {, + "EventCode": "0x524052", + "EventName": "PM_INST_ALL_GRP_PUMP_MPRED", + "BriefDescription": "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for instruction fetches and prefetches", + "PublicDescription": "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro" + }, + {, + "EventCode": "0x514052", + "EventName": "PM_INST_ALL_GRP_PUMP_MPRED_RTY", + "BriefDescription": "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for instruction fetches and prefetches", + "PublicDescription": "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor an instruction fetch" + }, + {, + "EventCode": "0x514054", + "EventName": "PM_INST_ALL_PUMP_CPRED", + "BriefDescription": "Pump prediction correct. Counts across all types of pumps for instruction fetches and prefetches", + "PublicDescription": "Pump prediction correct. Counts across all types of pumpsfor an instruction fetch" + }, + {, + "EventCode": "0x544052", + "EventName": "PM_INST_ALL_PUMP_MPRED", + "BriefDescription": "Pump misprediction. Counts across all types of pumps for instruction fetches and prefetches", + "PublicDescription": "Pump Mis prediction Counts across all types of pumpsfor an instruction fetch" + }, + {, + "EventCode": "0x534050", + "EventName": "PM_INST_ALL_SYS_PUMP_CPRED", + "BriefDescription": "Initial and Final Pump Scope was system pump (prediction=correct) for instruction fetches and prefetches", + "PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was system pump for an instruction fetch" + }, + {, + "EventCode": "0x534052", + "EventName": "PM_INST_ALL_SYS_PUMP_MPRED", + "BriefDescription": "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for instruction fetches and prefetches", + "PublicDescription": "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or" + }, + {, + "EventCode": "0x544050", + "EventName": "PM_INST_ALL_SYS_PUMP_MPRED_RTY", + "BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for instruction fetches and prefetches", + "PublicDescription": "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for an instruction fetch" + }, + {, + "EventCode": "0x4080", + "EventName": "PM_INST_FROM_L1", + "BriefDescription": "Instruction fetches from L1", + "PublicDescription": "" + }, + {, + "EventCode": "0x44046", + "EventName": "PM_INST_FROM_L21_MOD", + "BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another core's L2 on the same chip due to an instruction fetch (not prefetch)", + "PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another core's L2 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x34046", + "EventName": "PM_INST_FROM_L21_SHR", + "BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due to an instruction fetch (not prefetch)", + "PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x44044", + "EventName": "PM_INST_FROM_L31_ECO_MOD", + "BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to an instruction fetch (not prefetch)", + "PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x34044", + "EventName": "PM_INST_FROM_L31_ECO_SHR", + "BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to an instruction fetch (not prefetch)", + "PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x24044", + "EventName": "PM_INST_FROM_L31_MOD", + "BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another core's L3 on the same chip due to an instruction fetch (not prefetch)", + "PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another core's L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x14046", + "EventName": "PM_INST_FROM_L31_SHR", + "BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another core's L3 on the same chip due to an instruction fetch (not prefetch)", + "PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another core's L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1" + }, + {, + "EventCode": "0x30016", + "EventName": "PM_INST_IMC_MATCH_DISP", + "BriefDescription": "Matched Instructions Dispatched", + "PublicDescription": "IMC Matches dispatched" + }, + {, + "EventCode": "0x30014", + "EventName": "PM_IOPS_DISP", + "BriefDescription": "Internal Operations dispatched", + "PublicDescription": "IOPS dispatched" + }, + {, + "EventCode": "0x45046", + "EventName": "PM_IPTEG_FROM_L21_MOD", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a instruction side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x35046", + "EventName": "PM_IPTEG_FROM_L21_SHR", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a instruction side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x35040", + "EventName": "PM_IPTEG_FROM_L2_DISP_CONFLICT_LDHITST", + "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 with load hit store conflict due to a instruction side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x45040", + "EventName": "PM_IPTEG_FROM_L2_DISP_CONFLICT_OTHER", + "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 with dispatch conflict due to a instruction side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x45044", + "EventName": "PM_IPTEG_FROM_L31_ECO_MOD", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a instruction side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x35044", + "EventName": "PM_IPTEG_FROM_L31_ECO_SHR", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a instruction side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x25044", + "EventName": "PM_IPTEG_FROM_L31_MOD", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a instruction side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x15046", + "EventName": "PM_IPTEG_FROM_L31_SHR", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a instruction side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x617082", + "EventName": "PM_ISIDE_DISP", + "BriefDescription": "All i-side dispatch attempts", + "PublicDescription": "" + }, + {, + "EventCode": "0x627084", + "EventName": "PM_ISIDE_DISP_FAIL", + "BriefDescription": "All i-side dispatch attempts that failed due to a addr collision with another machine", + "PublicDescription": "" + }, + {, + "EventCode": "0x627086", + "EventName": "PM_ISIDE_DISP_FAIL_OTHER", + "BriefDescription": "All i-side dispatch attempts that failed due to a reason other than addrs collision", + "PublicDescription": "" + }, + {, + "EventCode": "0x4608e", + "EventName": "PM_ISIDE_L2MEMACC", + "BriefDescription": "valid when first beat of data comes in for an i-side fetch where data came from mem(or L4)", + "PublicDescription": "" + }, + {, + "EventCode": "0x44608e", + "EventName": "PM_ISIDE_MRU_TOUCH", + "BriefDescription": "Iside L2 MRU touch", + "PublicDescription": "" + }, + {, + "EventCode": "0x30ac", + "EventName": "PM_ISU_REF_FX0", + "BriefDescription": "FX0 ISU reject", + "PublicDescription": "" + }, + {, + "EventCode": "0x30ae", + "EventName": "PM_ISU_REF_FX1", + "BriefDescription": "FX1 ISU reject", + "PublicDescription": "" + }, + {, + "EventCode": "0x38ac", + "EventName": "PM_ISU_REF_FXU", + "BriefDescription": "FXU ISU reject from either pipe", + "PublicDescription": "" + }, + {, + "EventCode": "0x30b0", + "EventName": "PM_ISU_REF_LS0", + "BriefDescription": "LS0 ISU reject", + "PublicDescription": "" + }, + {, + "EventCode": "0x30b2", + "EventName": "PM_ISU_REF_LS1", + "BriefDescription": "LS1 ISU reject", + "PublicDescription": "" + }, + {, + "EventCode": "0x30b4", + "EventName": "PM_ISU_REF_LS2", + "BriefDescription": "LS2 ISU reject", + "PublicDescription": "" + }, + {, + "EventCode": "0x30b6", + "EventName": "PM_ISU_REF_LS3", + "BriefDescription": "LS3 ISU reject", + "PublicDescription": "" + }, + {, + "EventCode": "0x309c", + "EventName": "PM_ISU_REJECTS_ALL", + "BriefDescription": "All isu rejects could be more than 1 per cycle", + "PublicDescription": "" + }, + {, + "EventCode": "0x30a2", + "EventName": "PM_ISU_REJECT_RES_NA", + "BriefDescription": "ISU reject due to resource not available", + "PublicDescription": "" + }, + {, + "EventCode": "0x309e", + "EventName": "PM_ISU_REJECT_SAR_BYPASS", + "BriefDescription": "Reject because of SAR bypass", + "PublicDescription": "" + }, + {, + "EventCode": "0x30a0", + "EventName": "PM_ISU_REJECT_SRC_NA", + "BriefDescription": "ISU reject due to source not available", + "PublicDescription": "" + }, + {, + "EventCode": "0x30a8", + "EventName": "PM_ISU_REJ_VS0", + "BriefDescription": "VS0 ISU reject", + "PublicDescription": "" + }, + {, + "EventCode": "0x30aa", + "EventName": "PM_ISU_REJ_VS1", + "BriefDescription": "VS1 ISU reject", + "PublicDescription": "" + }, + {, + "EventCode": "0x38a8", + "EventName": "PM_ISU_REJ_VSU", + "BriefDescription": "VSU ISU reject from either pipe", + "PublicDescription": "" + }, + {, + "EventCode": "0x30b8", + "EventName": "PM_ISYNC", + "BriefDescription": "Isync count per thread", + "PublicDescription": "" + }, + {, + "EventCode": "0x200301ea", + "EventName": "PM_L1MISS_LAT_EXC_1024", + "BriefDescription": "L1 misses that took longer than 1024 cyles to resolve (miss to reload)", + "PublicDescription": "Reload latency exceeded 1024 cyc" + }, + {, + "EventCode": "0x200401ec", + "EventName": "PM_L1MISS_LAT_EXC_2048", + "BriefDescription": "L1 misses that took longer than 2048 cyles to resolve (miss to reload)", + "PublicDescription": "Reload latency exceeded 2048 cyc" + }, + {, + "EventCode": "0x200101e8", + "EventName": "PM_L1MISS_LAT_EXC_256", + "BriefDescription": "L1 misses that took longer than 256 cyles to resolve (miss to reload)", + "PublicDescription": "Reload latency exceeded 256 cyc" + }, + {, + "EventCode": "0x200201e6", + "EventName": "PM_L1MISS_LAT_EXC_32", + "BriefDescription": "L1 misses that took longer than 32 cyles to resolve (miss to reload)", + "PublicDescription": "Reload latency exceeded 32 cyc" + }, + {, + "EventCode": "0x26086", + "EventName": "PM_L1PF_L2MEMACC", + "BriefDescription": "valid when first beat of data comes in for an L1pref where data came from mem(or L4)", + "PublicDescription": "" + }, + {, + "EventCode": "0x408c", + "EventName": "PM_L1_DEMAND_WRITE", + "BriefDescription": "Instruction Demand sectors wriittent into IL1", + "PublicDescription": "" + }, + {, + "EventCode": "0x417080", + "EventName": "PM_L2_CASTOUT_MOD", + "BriefDescription": "L2 Castouts - Modified (M, Mu, Me)", + "PublicDescription": "" + }, + {, + "EventCode": "0x417082", + "EventName": "PM_L2_CASTOUT_SHR", + "BriefDescription": "L2 Castouts - Shared (T, Te, Si, S)", + "PublicDescription": "" + }, + {, + "EventCode": "0x27084", + "EventName": "PM_L2_CHIP_PUMP", + "BriefDescription": "RC requests that were local on chip pump attempts", + "PublicDescription": "" + }, + {, + "EventCode": "0x427086", + "EventName": "PM_L2_DC_INV", + "BriefDescription": "Dcache invalidates from L2", + "PublicDescription": "" + }, + {, + "EventCode": "0x44608c", + "EventName": "PM_L2_DISP_ALL_L2MISS", + "BriefDescription": "All successful Ld/St dispatches for this thread that were an L2miss", + "PublicDescription": "" + }, + {, + "EventCode": "0x27086", + "EventName": "PM_L2_GROUP_PUMP", + "BriefDescription": "RC requests that were on Node Pump attempts", + "PublicDescription": "" + }, + {, + "EventCode": "0x626084", + "EventName": "PM_L2_GRP_GUESS_CORRECT", + "BriefDescription": "L2 guess grp and guess was correct (data intra-6chip AND ^on-chip)", + "PublicDescription": "" + }, + {, + "EventCode": "0x626086", + "EventName": "PM_L2_GRP_GUESS_WRONG", + "BriefDescription": "L2 guess grp and guess was not correct (ie data on-chip OR beyond-6chip)", + "PublicDescription": "" + }, + {, + "EventCode": "0x427084", + "EventName": "PM_L2_IC_INV", + "BriefDescription": "Icache Invalidates from L2", + "PublicDescription": "" + }, + {, + "EventCode": "0x436088", + "EventName": "PM_L2_INST", + "BriefDescription": "All successful I-side dispatches for this thread (excludes i_l2mru_tch reqs)", + "PublicDescription": "" + }, + {, + "EventCode": "0x43608a", + "EventName": "PM_L2_INST_MISS", + "BriefDescription": "All successful i-side dispatches that were an L2miss for this thread (excludes i_l2mru_tch reqs)", + "PublicDescription": "" + }, + {, + "EventCode": "0x416080", + "EventName": "PM_L2_LD", + "BriefDescription": "All successful D-side Load dispatches for this thread", + "PublicDescription": "" + }, + {, + "EventCode": "0x437088", + "EventName": "PM_L2_LD_DISP", + "BriefDescription": "All successful load dispatches", + "PublicDescription": "" + }, + {, + "EventCode": "0x43708a", + "EventName": "PM_L2_LD_HIT", + "BriefDescription": "All successful load dispatches that were L2 hits", + "PublicDescription": "" + }, + {, + "EventCode": "0x426084", + "EventName": "PM_L2_LD_MISS", + "BriefDescription": "All successful D-Side Load dispatches that were an L2miss for this thread", + "PublicDescription": "" + }, + {, + "EventCode": "0x616080", + "EventName": "PM_L2_LOC_GUESS_CORRECT", + "BriefDescription": "L2 guess loc and guess was correct (ie data local)", + "PublicDescription": "" + }, + {, + "EventCode": "0x616082", + "EventName": "PM_L2_LOC_GUESS_WRONG", + "BriefDescription": "L2 guess loc and guess was not correct (ie data not on chip)", + "PublicDescription": "" + }, + {, + "EventCode": "0x516080", + "EventName": "PM_L2_RCLD_DISP", + "BriefDescription": "L2 RC load dispatch attempt", + "PublicDescription": "" + }, + {, + "EventCode": "0x516082", + "EventName": "PM_L2_RCLD_DISP_FAIL_ADDR", + "BriefDescription": "L2 RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ", + "PublicDescription": "" + }, + {, + "EventCode": "0x526084", + "EventName": "PM_L2_RCLD_DISP_FAIL_OTHER", + "BriefDescription": "L2 RC load dispatch attempt failed due to other reasons", + "PublicDescription": "" + }, + {, + "EventCode": "0x536088", + "EventName": "PM_L2_RCST_DISP", + "BriefDescription": "L2 RC store dispatch attempt", + "PublicDescription": "" + }, + {, + "EventCode": "0x53608a", + "EventName": "PM_L2_RCST_DISP_FAIL_ADDR", + "BriefDescription": "L2 RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ", + "PublicDescription": "" + }, + {, + "EventCode": "0x54608c", + "EventName": "PM_L2_RCST_DISP_FAIL_OTHER", + "BriefDescription": "L2 RC store dispatch attempt failed due to other reasons", + "PublicDescription": "" + }, + {, + "EventCode": "0x537088", + "EventName": "PM_L2_RC_ST_DONE", + "BriefDescription": "RC did st to line that was Tx or Sx", + "PublicDescription": "" + }, + {, + "EventCode": "0x63708a", + "EventName": "PM_L2_RTY_LD", + "BriefDescription": "RC retries on PB for any load from core", + "PublicDescription": "" + }, + {, + "EventCode": "0x3708a", + "EventName": "PM_L2_RTY_ST", + "BriefDescription": "RC retries on PB for any store from core", + "PublicDescription": "" + }, + {, + "EventCode": "0x54708c", + "EventName": "PM_L2_SN_M_RD_DONE", + "BriefDescription": "SNP dispatched for a read and was M", + "PublicDescription": "" + }, + {, + "EventCode": "0x54708e", + "EventName": "PM_L2_SN_M_WR_DONE", + "BriefDescription": "SNP dispatched for a write and was M", + "PublicDescription": "" + }, + {, + "EventCode": "0x53708a", + "EventName": "PM_L2_SN_SX_I_DONE", + "BriefDescription": "SNP dispatched and went from Sx or Tx to Ix", + "PublicDescription": "" + }, + {, + "EventCode": "0x17080", + "EventName": "PM_L2_ST", + "BriefDescription": "All successful D-side store dispatches for this thread", + "PublicDescription": "" + }, + {, + "EventCode": "0x44708c", + "EventName": "PM_L2_ST_DISP", + "BriefDescription": "All successful store dispatches", + "PublicDescription": "" + }, + {, + "EventCode": "0x44708e", + "EventName": "PM_L2_ST_HIT", + "BriefDescription": "All successful store dispatches that were L2Hits", + "PublicDescription": "" + }, + {, + "EventCode": "0x17082", + "EventName": "PM_L2_ST_MISS", + "BriefDescription": "All successful D-side store dispatches for this thread that were L2 Miss", + "PublicDescription": "" + }, + {, + "EventCode": "0x636088", + "EventName": "PM_L2_SYS_GUESS_CORRECT", + "BriefDescription": "L2 guess sys and guess was correct (ie data beyond-6chip)", + "PublicDescription": "" + }, + {, + "EventCode": "0x63608a", + "EventName": "PM_L2_SYS_GUESS_WRONG", + "BriefDescription": "L2 guess sys and guess was not correct (ie data ^beyond-6chip)", + "PublicDescription": "" + }, + {, + "EventCode": "0x617080", + "EventName": "PM_L2_SYS_PUMP", + "BriefDescription": "RC requests that were system pump attempts", + "PublicDescription": "" + }, + {, + "EventCode": "0x1e05e", + "EventName": "PM_L2_TM_REQ_ABORT", + "BriefDescription": "TM abort", + "PublicDescription": "" + }, + {, + "EventCode": "0x3e05c", + "EventName": "PM_L2_TM_ST_ABORT_SISTER", + "BriefDescription": "TM marked store abort", + "PublicDescription": "" + }, + {, + "EventCode": "0x23808a", + "EventName": "PM_L3_CINJ", + "BriefDescription": "l3 ci of cache inject", + "PublicDescription": "" + }, + {, + "EventCode": "0x128084", + "EventName": "PM_L3_CI_HIT", + "BriefDescription": "L3 Castins Hit (total count", + "PublicDescription": "" + }, + {, + "EventCode": "0x128086", + "EventName": "PM_L3_CI_MISS", + "BriefDescription": "L3 castins miss (total count", + "PublicDescription": "" + }, + {, + "EventCode": "0x819082", + "EventName": "PM_L3_CI_USAGE", + "BriefDescription": "rotating sample of 16 CI or CO actives", + "PublicDescription": "" + }, + {, + "EventCode": "0x438088", + "EventName": "PM_L3_CO", + "BriefDescription": "l3 castout occurring ( does not include casthrough or log writes (cinj/dmaw)", + "PublicDescription": "" + }, + {, + "EventCode": "0x83908b", + "EventName": "PM_L3_CO0_ALLOC", + "BriefDescription": "lifetime, sample of CO machine 0 valid", + "PublicDescription": "0.0" + }, + {, + "EventCode": "0x83908a", + "EventName": "PM_L3_CO0_BUSY", + "BriefDescription": "lifetime, sample of CO machine 0 valid", + "PublicDescription": "" + }, + {, + "EventCode": "0x28086", + "EventName": "PM_L3_CO_L31", + "BriefDescription": "L3 CO to L3.1 OR of port 0 and 1 ( lossy)", + "PublicDescription": "" + }, + {, + "EventCode": "0x238088", + "EventName": "PM_L3_CO_LCO", + "BriefDescription": "Total L3 castouts occurred on LCO", + "PublicDescription": "" + }, + {, + "EventCode": "0x28084", + "EventName": "PM_L3_CO_MEM", + "BriefDescription": "L3 CO to memory OR of port 0 and 1 ( lossy)", + "PublicDescription": "" + }, + {, + "EventCode": "0xb19082", + "EventName": "PM_L3_GRP_GUESS_CORRECT", + "BriefDescription": "Initial scope=group and data from same group (near) (pred successful)", + "PublicDescription": "" + }, + {, + "EventCode": "0xb3908a", + "EventName": "PM_L3_GRP_GUESS_WRONG_HIGH", + "BriefDescription": "Initial scope=group but data from local node. Predition too high", + "PublicDescription": "" + }, + {, + "EventCode": "0xb39088", + "EventName": "PM_L3_GRP_GUESS_WRONG_LOW", + "BriefDescription": "Initial scope=group but data from outside group (far or rem). Prediction too Low", + "PublicDescription": "" + }, + {, + "EventCode": "0x218080", + "EventName": "PM_L3_HIT", + "BriefDescription": "L3 Hits", + "PublicDescription": "" + }, + {, + "EventCode": "0x138088", + "EventName": "PM_L3_L2_CO_HIT", + "BriefDescription": "L2 castout hits", + "PublicDescription": "" + }, + {, + "EventCode": "0x13808a", + "EventName": "PM_L3_L2_CO_MISS", + "BriefDescription": "L2 castout miss", + "PublicDescription": "" + }, + {, + "EventCode": "0x14808c", + "EventName": "PM_L3_LAT_CI_HIT", + "BriefDescription": "L3 Lateral Castins Hit", + "PublicDescription": "" + }, + {, + "EventCode": "0x14808e", + "EventName": "PM_L3_LAT_CI_MISS", + "BriefDescription": "L3 Lateral Castins Miss", + "PublicDescription": "" + }, + {, + "EventCode": "0x228084", + "EventName": "PM_L3_LD_HIT", + "BriefDescription": "L3 demand LD Hits", + "PublicDescription": "" + }, + {, + "EventCode": "0x228086", + "EventName": "PM_L3_LD_MISS", + "BriefDescription": "L3 demand LD Miss", + "PublicDescription": "" + }, + {, + "EventCode": "0x1e052", + "EventName": "PM_L3_LD_PREF", + "BriefDescription": "L3 Load Prefetches", + "PublicDescription": "" + }, + {, + "EventCode": "0xb19080", + "EventName": "PM_L3_LOC_GUESS_CORRECT", + "BriefDescription": "initial scope=node/chip and data from local node (local) (pred successful)", + "PublicDescription": "" + }, + {, + "EventCode": "0xb29086", + "EventName": "PM_L3_LOC_GUESS_WRONG", + "BriefDescription": "Initial scope=node but data from out side local node (near or far or rem). Prediction too Low", + "PublicDescription": "" + }, + {, + "EventCode": "0x218082", + "EventName": "PM_L3_MISS", + "BriefDescription": "L3 Misses", + "PublicDescription": "" + }, + {, + "EventCode": "0x54808c", + "EventName": "PM_L3_P0_CO_L31", + "BriefDescription": "l3 CO to L3.1 (lco) port 0", + "PublicDescription": "" + }, + {, + "EventCode": "0x538088", + "EventName": "PM_L3_P0_CO_MEM", + "BriefDescription": "l3 CO to memory port 0", + "PublicDescription": "" + }, + {, + "EventCode": "0x929084", + "EventName": "PM_L3_P0_CO_RTY", + "BriefDescription": "L3 CO received retry port 0", + "PublicDescription": "" + }, + {, + "EventCode": "0xa29084", + "EventName": "PM_L3_P0_GRP_PUMP", + "BriefDescription": "L3 pf sent with grp scope port 0", + "PublicDescription": "" + }, + {, + "EventCode": "0x528084", + "EventName": "PM_L3_P0_LCO_DATA", + "BriefDescription": "lco sent with data port 0", + "PublicDescription": "" + }, + {, + "EventCode": "0x518080", + "EventName": "PM_L3_P0_LCO_NO_DATA", + "BriefDescription": "dataless l3 lco sent port 0", + "PublicDescription": "" + }, + {, + "EventCode": "0xa4908c", + "EventName": "PM_L3_P0_LCO_RTY", + "BriefDescription": "L3 LCO received retry port 0", + "PublicDescription": "" + }, + {, + "EventCode": "0xa19080", + "EventName": "PM_L3_P0_NODE_PUMP", + "BriefDescription": "L3 pf sent with nodal scope port 0", + "PublicDescription": "" + }, + {, + "EventCode": "0x919080", + "EventName": "PM_L3_P0_PF_RTY", + "BriefDescription": "L3 PF received retry port 0", + "PublicDescription": "" + }, + {, + "EventCode": "0x939088", + "EventName": "PM_L3_P0_SN_HIT", + "BriefDescription": "L3 snoop hit port 0", + "PublicDescription": "" + }, + {, + "EventCode": "0x118080", + "EventName": "PM_L3_P0_SN_INV", + "BriefDescription": "Port0 snooper detects someone doing a store to a line thats Sx", + "PublicDescription": "" + }, + {, + "EventCode": "0x94908c", + "EventName": "PM_L3_P0_SN_MISS", + "BriefDescription": "L3 snoop miss port 0", + "PublicDescription": "" + }, + {, + "EventCode": "0xa39088", + "EventName": "PM_L3_P0_SYS_PUMP", + "BriefDescription": "L3 pf sent with sys scope port 0", + "PublicDescription": "" + }, + {, + "EventCode": "0x54808e", + "EventName": "PM_L3_P1_CO_L31", + "BriefDescription": "l3 CO to L3.1 (lco) port 1", + "PublicDescription": "" + }, + {, + "EventCode": "0x53808a", + "EventName": "PM_L3_P1_CO_MEM", + "BriefDescription": "l3 CO to memory port 1", + "PublicDescription": "" + }, + {, + "EventCode": "0x929086", + "EventName": "PM_L3_P1_CO_RTY", + "BriefDescription": "L3 CO received retry port 1", + "PublicDescription": "" + }, + {, + "EventCode": "0xa29086", + "EventName": "PM_L3_P1_GRP_PUMP", + "BriefDescription": "L3 pf sent with grp scope port 1", + "PublicDescription": "" + }, + {, + "EventCode": "0x528086", + "EventName": "PM_L3_P1_LCO_DATA", + "BriefDescription": "lco sent with data port 1", + "PublicDescription": "" + }, + {, + "EventCode": "0x518082", + "EventName": "PM_L3_P1_LCO_NO_DATA", + "BriefDescription": "dataless l3 lco sent port 1", + "PublicDescription": "" + }, + {, + "EventCode": "0xa4908e", + "EventName": "PM_L3_P1_LCO_RTY", + "BriefDescription": "L3 LCO received retry port 1", + "PublicDescription": "" + }, + {, + "EventCode": "0xa19082", + "EventName": "PM_L3_P1_NODE_PUMP", + "BriefDescription": "L3 pf sent with nodal scope port 1", + "PublicDescription": "" + }, + {, + "EventCode": "0x919082", + "EventName": "PM_L3_P1_PF_RTY", + "BriefDescription": "L3 PF received retry port 1", + "PublicDescription": "" + }, + {, + "EventCode": "0x93908a", + "EventName": "PM_L3_P1_SN_HIT", + "BriefDescription": "L3 snoop hit port 1", + "PublicDescription": "" + }, + {, + "EventCode": "0x118082", + "EventName": "PM_L3_P1_SN_INV", + "BriefDescription": "Port1 snooper detects someone doing a store to a line thats Sx", + "PublicDescription": "" + }, + {, + "EventCode": "0x94908e", + "EventName": "PM_L3_P1_SN_MISS", + "BriefDescription": "L3 snoop miss port 1", + "PublicDescription": "" + }, + {, + "EventCode": "0xa3908a", + "EventName": "PM_L3_P1_SYS_PUMP", + "BriefDescription": "L3 pf sent with sys scope port 1", + "PublicDescription": "" + }, + {, + "EventCode": "0x84908d", + "EventName": "PM_L3_PF0_ALLOC", + "BriefDescription": "lifetime, sample of PF machine 0 valid", + "PublicDescription": "0.0" + }, + {, + "EventCode": "0x84908c", + "EventName": "PM_L3_PF0_BUSY", + "BriefDescription": "lifetime, sample of PF machine 0 valid", + "PublicDescription": "" + }, + {, + "EventCode": "0x428084", + "EventName": "PM_L3_PF_HIT_L3", + "BriefDescription": "l3 pf hit in l3", + "PublicDescription": "" + }, + {, + "EventCode": "0x18080", + "EventName": "PM_L3_PF_MISS_L3", + "BriefDescription": "L3 Prefetch missed in L3", + "PublicDescription": "" + }, + {, + "EventCode": "0x3808a", + "EventName": "PM_L3_PF_OFF_CHIP_CACHE", + "BriefDescription": "L3 Prefetch from Off chip cache", + "PublicDescription": "" + }, + {, + "EventCode": "0x4808e", + "EventName": "PM_L3_PF_OFF_CHIP_MEM", + "BriefDescription": "L3 Prefetch from Off chip memory", + "PublicDescription": "" + }, + {, + "EventCode": "0x38088", + "EventName": "PM_L3_PF_ON_CHIP_CACHE", + "BriefDescription": "L3 Prefetch from On chip cache", + "PublicDescription": "" + }, + {, + "EventCode": "0x4808c", + "EventName": "PM_L3_PF_ON_CHIP_MEM", + "BriefDescription": "L3 Prefetch from On chip memory", + "PublicDescription": "" + }, + {, + "EventCode": "0x829084", + "EventName": "PM_L3_PF_USAGE", + "BriefDescription": "rotating sample of 32 PF actives", + "PublicDescription": "" + }, + {, + "EventCode": "0x4e052", + "EventName": "PM_L3_PREF_ALL", + "BriefDescription": "Total HW L3 prefetches(Load+store)", + "PublicDescription": "" + }, + {, + "EventCode": "0x84908f", + "EventName": "PM_L3_RD0_ALLOC", + "BriefDescription": "lifetime, sample of RD machine 0 valid", + "PublicDescription": "0.0" + }, + {, + "EventCode": "0x84908e", + "EventName": "PM_L3_RD0_BUSY", + "BriefDescription": "lifetime, sample of RD machine 0 valid", + "PublicDescription": "" + }, + {, + "EventCode": "0x829086", + "EventName": "PM_L3_RD_USAGE", + "BriefDescription": "rotating sample of 16 RD actives", + "PublicDescription": "" + }, + {, + "EventCode": "0x839089", + "EventName": "PM_L3_SN0_ALLOC", + "BriefDescription": "lifetime, sample of snooper machine 0 valid", + "PublicDescription": "0.0" + }, + {, + "EventCode": "0x839088", + "EventName": "PM_L3_SN0_BUSY", + "BriefDescription": "lifetime, sample of snooper machine 0 valid", + "PublicDescription": "" + }, + {, + "EventCode": "0x819080", + "EventName": "PM_L3_SN_USAGE", + "BriefDescription": "rotating sample of 8 snoop valids", + "PublicDescription": "" + }, + {, + "EventCode": "0x2e052", + "EventName": "PM_L3_ST_PREF", + "BriefDescription": "L3 store Prefetches", + "PublicDescription": "" + }, + {, + "EventCode": "0x3e052", + "EventName": "PM_L3_SW_PREF", + "BriefDescription": "Data stream touchto L3", + "PublicDescription": "" + }, + {, + "EventCode": "0xb29084", + "EventName": "PM_L3_SYS_GUESS_CORRECT", + "BriefDescription": "Initial scope=system and data from outside group (far or rem)(pred successful)", + "PublicDescription": "" + }, + {, + "EventCode": "0xb4908c", + "EventName": "PM_L3_SYS_GUESS_WRONG", + "BriefDescription": "Initial scope=system but data from local or near. Predction too high", + "PublicDescription": "" + }, + {, + "EventCode": "0x24808e", + "EventName": "PM_L3_TRANS_PF", + "BriefDescription": "L3 Transient prefetch", + "PublicDescription": "" + }, + {, + "EventCode": "0x18081", + "EventName": "PM_L3_WI0_ALLOC", + "BriefDescription": "lifetime, sample of Write Inject machine 0 valid", + "PublicDescription": "0.0" + }, + {, + "EventCode": "0x418080", + "EventName": "PM_L3_WI0_BUSY", + "BriefDescription": "lifetime, sample of Write Inject machine 0 valid", + "PublicDescription": "" + }, + {, + "EventCode": "0x418082", + "EventName": "PM_L3_WI_USAGE", + "BriefDescription": "rotating sample of 8 WI actives", + "PublicDescription": "" + }, + {, + "EventCode": "0xc080", + "EventName": "PM_LD_REF_L1_LSU0", + "BriefDescription": "LS0 L1 D cache load references counted at finish, gated by reject", + "PublicDescription": "LS0 L1 D cache load references counted at finish, gated by rejectLSU0 L1 D cache load references" + }, + {, + "EventCode": "0xc082", + "EventName": "PM_LD_REF_L1_LSU1", + "BriefDescription": "LS1 L1 D cache load references counted at finish, gated by reject", + "PublicDescription": "LS1 L1 D cache load references counted at finish, gated by rejectLSU1 L1 D cache load references" + }, + {, + "EventCode": "0xc094", + "EventName": "PM_LD_REF_L1_LSU2", + "BriefDescription": "LS2 L1 D cache load references counted at finish, gated by reject", + "PublicDescription": "LS2 L1 D cache load references counted at finish, gated by reject42" + }, + {, + "EventCode": "0xc096", + "EventName": "PM_LD_REF_L1_LSU3", + "BriefDescription": "LS3 L1 D cache load references counted at finish, gated by reject", + "PublicDescription": "LS3 L1 D cache load references counted at finish, gated by reject42" + }, + {, + "EventCode": "0x509a", + "EventName": "PM_LINK_STACK_INVALID_PTR", + "BriefDescription": "A flush were LS ptr is invalid, results in a pop , A lot of interrupts between push and pops", + "PublicDescription": "" + }, + {, + "EventCode": "0x5098", + "EventName": "PM_LINK_STACK_WRONG_ADD_PRED", + "BriefDescription": "Link stack predicts wrong address, because of link stack design limitation", + "PublicDescription": "" + }, + {, + "EventCode": "0xe080", + "EventName": "PM_LS0_ERAT_MISS_PREF", + "BriefDescription": "LS0 Erat miss due to prefetch", + "PublicDescription": "LS0 Erat miss due to prefetch42" + }, + {, + "EventCode": "0xd0b8", + "EventName": "PM_LS0_L1_PREF", + "BriefDescription": "LS0 L1 cache data prefetches", + "PublicDescription": "LS0 L1 cache data prefetches42" + }, + {, + "EventCode": "0xc098", + "EventName": "PM_LS0_L1_SW_PREF", + "BriefDescription": "Software L1 Prefetches, including SW Transient Prefetches", + "PublicDescription": "Software L1 Prefetches, including SW Transient Prefetches42" + }, + {, + "EventCode": "0xe082", + "EventName": "PM_LS1_ERAT_MISS_PREF", + "BriefDescription": "LS1 Erat miss due to prefetch", + "PublicDescription": "LS1 Erat miss due to prefetch42" + }, + {, + "EventCode": "0xd0ba", + "EventName": "PM_LS1_L1_PREF", + "BriefDescription": "LS1 L1 cache data prefetches", + "PublicDescription": "LS1 L1 cache data prefetches42" + }, + {, + "EventCode": "0xc09a", + "EventName": "PM_LS1_L1_SW_PREF", + "BriefDescription": "Software L1 Prefetches, including SW Transient Prefetches", + "PublicDescription": "Software L1 Prefetches, including SW Transient Prefetches42" + }, + {, + "EventCode": "0xc0b0", + "EventName": "PM_LSU0_FLUSH_LRQ", + "BriefDescription": "LS0 Flush: LRQ", + "PublicDescription": "LS0 Flush: LRQLSU0 LRQ flushes" + }, + {, + "EventCode": "0xc0b8", + "EventName": "PM_LSU0_FLUSH_SRQ", + "BriefDescription": "LS0 Flush: SRQ", + "PublicDescription": "LS0 Flush: SRQLSU0 SRQ lhs flushes" + }, + {, + "EventCode": "0xc0a4", + "EventName": "PM_LSU0_FLUSH_ULD", + "BriefDescription": "LS0 Flush: Unaligned Load", + "PublicDescription": "LS0 Flush: Unaligned LoadLSU0 unaligned load flushes" + }, + {, + "EventCode": "0xc0ac", + "EventName": "PM_LSU0_FLUSH_UST", + "BriefDescription": "LS0 Flush: Unaligned Store", + "PublicDescription": "LS0 Flush: Unaligned StoreLSU0 unaligned store flushes" + }, + {, + "EventCode": "0xf088", + "EventName": "PM_LSU0_L1_CAM_CANCEL", + "BriefDescription": "ls0 l1 tm cam cancel", + "PublicDescription": "ls0 l1 tm cam cancel42" + }, + {, + "EventCode": "0x1e056", + "EventName": "PM_LSU0_LARX_FIN", + "BriefDescription": "Larx finished in LSU pipe0", + "PublicDescription": "" + }, + {, + "EventCode": "0xd08c", + "EventName": "PM_LSU0_LMQ_LHR_MERGE", + "BriefDescription": "LS0 Load Merged with another cacheline request", + "PublicDescription": "LS0 Load Merged with another cacheline request42" + }, + {, + "EventCode": "0xc08c", + "EventName": "PM_LSU0_NCLD", + "BriefDescription": "LS0 Non-cachable Loads counted at finish", + "PublicDescription": "LS0 Non-cachable Loads counted at finishLSU0 non-cacheable loads" + }, + {, + "EventCode": "0xe090", + "EventName": "PM_LSU0_PRIMARY_ERAT_HIT", + "BriefDescription": "Primary ERAT hit", + "PublicDescription": "Primary ERAT hit42" + }, + {, + "EventCode": "0x1e05a", + "EventName": "PM_LSU0_REJECT", + "BriefDescription": "LSU0 reject", + "PublicDescription": "" + }, + {, + "EventCode": "0xc09c", + "EventName": "PM_LSU0_SRQ_STFWD", + "BriefDescription": "LS0 SRQ forwarded data to a load", + "PublicDescription": "LS0 SRQ forwarded data to a loadLSU0 SRQ store forwarded" + }, + {, + "EventCode": "0xf084", + "EventName": "PM_LSU0_STORE_REJECT", + "BriefDescription": "ls0 store reject", + "PublicDescription": "ls0 store reject42" + }, + {, + "EventCode": "0xe0a8", + "EventName": "PM_LSU0_TMA_REQ_L2", + "BriefDescription": "addrs only req to L2 only on the first one,Indication that Load footprint is not expanding", + "PublicDescription": "addrs only req to L2 only on the first one,Indication that Load footprint is not expanding42" + }, + {, + "EventCode": "0xe098", + "EventName": "PM_LSU0_TM_L1_HIT", + "BriefDescription": "Load tm hit in L1", + "PublicDescription": "Load tm hit in L142" + }, + {, + "EventCode": "0xe0a0", + "EventName": "PM_LSU0_TM_L1_MISS", + "BriefDescription": "Load tm L1 miss", + "PublicDescription": "Load tm L1 miss42" + }, + {, + "EventCode": "0xc0b2", + "EventName": "PM_LSU1_FLUSH_LRQ", + "BriefDescription": "LS1 Flush: LRQ", + "PublicDescription": "LS1 Flush: LRQLSU1 LRQ flushes" + }, + {, + "EventCode": "0xc0ba", + "EventName": "PM_LSU1_FLUSH_SRQ", + "BriefDescription": "LS1 Flush: SRQ", + "PublicDescription": "LS1 Flush: SRQLSU1 SRQ lhs flushes" + }, + {, + "EventCode": "0xc0a6", + "EventName": "PM_LSU1_FLUSH_ULD", + "BriefDescription": "LS 1 Flush: Unaligned Load", + "PublicDescription": "LS 1 Flush: Unaligned LoadLSU1 unaligned load flushes" + }, + {, + "EventCode": "0xc0ae", + "EventName": "PM_LSU1_FLUSH_UST", + "BriefDescription": "LS1 Flush: Unaligned Store", + "PublicDescription": "LS1 Flush: Unaligned StoreLSU1 unaligned store flushes" + }, + {, + "EventCode": "0xf08a", + "EventName": "PM_LSU1_L1_CAM_CANCEL", + "BriefDescription": "ls1 l1 tm cam cancel", + "PublicDescription": "ls1 l1 tm cam cancel42" + }, + {, + "EventCode": "0x2e056", + "EventName": "PM_LSU1_LARX_FIN", + "BriefDescription": "Larx finished in LSU pipe1", + "PublicDescription": "" + }, + {, + "EventCode": "0xd08e", + "EventName": "PM_LSU1_LMQ_LHR_MERGE", + "BriefDescription": "LS1 Load Merge with another cacheline request", + "PublicDescription": "LS1 Load Merge with another cacheline request42" + }, + {, + "EventCode": "0xc08e", + "EventName": "PM_LSU1_NCLD", + "BriefDescription": "LS1 Non-cachable Loads counted at finish", + "PublicDescription": "LS1 Non-cachable Loads counted at finishLSU1 non-cacheable loads" + }, + {, + "EventCode": "0xe092", + "EventName": "PM_LSU1_PRIMARY_ERAT_HIT", + "BriefDescription": "Primary ERAT hit", + "PublicDescription": "Primary ERAT hit42" + }, + {, + "EventCode": "0x2e05a", + "EventName": "PM_LSU1_REJECT", + "BriefDescription": "LSU1 reject", + "PublicDescription": "" + }, + {, + "EventCode": "0xc09e", + "EventName": "PM_LSU1_SRQ_STFWD", + "BriefDescription": "LS1 SRQ forwarded data to a load", + "PublicDescription": "LS1 SRQ forwarded data to a loadLSU1 SRQ store forwarded" + }, + {, + "EventCode": "0xf086", + "EventName": "PM_LSU1_STORE_REJECT", + "BriefDescription": "ls1 store reject", + "PublicDescription": "ls1 store reject42" + }, + {, + "EventCode": "0xe0aa", + "EventName": "PM_LSU1_TMA_REQ_L2", + "BriefDescription": "addrs only req to L2 only on the first one,Indication that Load footprint is not expanding", + "PublicDescription": "addrs only req to L2 only on the first one,Indication that Load footprint is not expanding42" + }, + {, + "EventCode": "0xe09a", + "EventName": "PM_LSU1_TM_L1_HIT", + "BriefDescription": "Load tm hit in L1", + "PublicDescription": "Load tm hit in L142" + }, + {, + "EventCode": "0xe0a2", + "EventName": "PM_LSU1_TM_L1_MISS", + "BriefDescription": "Load tm L1 miss", + "PublicDescription": "Load tm L1 miss42" + }, + {, + "EventCode": "0xc0b4", + "EventName": "PM_LSU2_FLUSH_LRQ", + "BriefDescription": "LS02Flush: LRQ", + "PublicDescription": "LS02Flush: LRQ42" + }, + {, + "EventCode": "0xc0bc", + "EventName": "PM_LSU2_FLUSH_SRQ", + "BriefDescription": "LS2 Flush: SRQ", + "PublicDescription": "LS2 Flush: SRQ42" + }, + {, + "EventCode": "0xc0a8", + "EventName": "PM_LSU2_FLUSH_ULD", + "BriefDescription": "LS3 Flush: Unaligned Load", + "PublicDescription": "LS3 Flush: Unaligned Load42" + }, + {, + "EventCode": "0xf08c", + "EventName": "PM_LSU2_L1_CAM_CANCEL", + "BriefDescription": "ls2 l1 tm cam cancel", + "PublicDescription": "ls2 l1 tm cam cancel42" + }, + {, + "EventCode": "0x3e056", + "EventName": "PM_LSU2_LARX_FIN", + "BriefDescription": "Larx finished in LSU pipe2", + "PublicDescription": "" + }, + {, + "EventCode": "0xc084", + "EventName": "PM_LSU2_LDF", + "BriefDescription": "LS2 Scalar Loads", + "PublicDescription": "LS2 Scalar Loads42" + }, + {, + "EventCode": "0xc088", + "EventName": "PM_LSU2_LDX", + "BriefDescription": "LS0 Vector Loads", + "PublicDescription": "LS0 Vector Loads42" + }, + {, + "EventCode": "0xd090", + "EventName": "PM_LSU2_LMQ_LHR_MERGE", + "BriefDescription": "LS0 Load Merged with another cacheline request", + "PublicDescription": "LS0 Load Merged with another cacheline request42" + }, + {, + "EventCode": "0xe094", + "EventName": "PM_LSU2_PRIMARY_ERAT_HIT", + "BriefDescription": "Primary ERAT hit", + "PublicDescription": "Primary ERAT hit42" + }, + {, + "EventCode": "0x3e05a", + "EventName": "PM_LSU2_REJECT", + "BriefDescription": "LSU2 reject", + "PublicDescription": "" + }, + {, + "EventCode": "0xc0a0", + "EventName": "PM_LSU2_SRQ_STFWD", + "BriefDescription": "LS2 SRQ forwarded data to a load", + "PublicDescription": "LS2 SRQ forwarded data to a load42" + }, + {, + "EventCode": "0xe0ac", + "EventName": "PM_LSU2_TMA_REQ_L2", + "BriefDescription": "addrs only req to L2 only on the first one,Indication that Load footprint is not expanding", + "PublicDescription": "addrs only req to L2 only on the first one,Indication that Load footprint is not expanding42" + }, + {, + "EventCode": "0xe09c", + "EventName": "PM_LSU2_TM_L1_HIT", + "BriefDescription": "Load tm hit in L1", + "PublicDescription": "Load tm hit in L142" + }, + {, + "EventCode": "0xe0a4", + "EventName": "PM_LSU2_TM_L1_MISS", + "BriefDescription": "Load tm L1 miss", + "PublicDescription": "Load tm L1 miss42" + }, + {, + "EventCode": "0xc0b6", + "EventName": "PM_LSU3_FLUSH_LRQ", + "BriefDescription": "LS3 Flush: LRQ", + "PublicDescription": "LS3 Flush: LRQ42" + }, + {, + "EventCode": "0xc0be", + "EventName": "PM_LSU3_FLUSH_SRQ", + "BriefDescription": "LS13 Flush: SRQ", + "PublicDescription": "LS13 Flush: SRQ42" + }, + {, + "EventCode": "0xc0aa", + "EventName": "PM_LSU3_FLUSH_ULD", + "BriefDescription": "LS 14Flush: Unaligned Load", + "PublicDescription": "LS 14Flush: Unaligned Load42" + }, + {, + "EventCode": "0xf08e", + "EventName": "PM_LSU3_L1_CAM_CANCEL", + "BriefDescription": "ls3 l1 tm cam cancel", + "PublicDescription": "ls3 l1 tm cam cancel42" + }, + {, + "EventCode": "0x4e056", + "EventName": "PM_LSU3_LARX_FIN", + "BriefDescription": "Larx finished in LSU pipe3", + "PublicDescription": "" + }, + {, + "EventCode": "0xc086", + "EventName": "PM_LSU3_LDF", + "BriefDescription": "LS3 Scalar Loads", + "PublicDescription": "LS3 Scalar Loads 42" + }, + {, + "EventCode": "0xc08a", + "EventName": "PM_LSU3_LDX", + "BriefDescription": "LS1 Vector Loads", + "PublicDescription": "LS1 Vector Loads42" + }, + {, + "EventCode": "0xd092", + "EventName": "PM_LSU3_LMQ_LHR_MERGE", + "BriefDescription": "LS1 Load Merge with another cacheline request", + "PublicDescription": "LS1 Load Merge with another cacheline request42" + }, + {, + "EventCode": "0xe096", + "EventName": "PM_LSU3_PRIMARY_ERAT_HIT", + "BriefDescription": "Primary ERAT hit", + "PublicDescription": "Primary ERAT hit42" + }, + {, + "EventCode": "0x4e05a", + "EventName": "PM_LSU3_REJECT", + "BriefDescription": "LSU3 reject", + "PublicDescription": "" + }, + {, + "EventCode": "0xc0a2", + "EventName": "PM_LSU3_SRQ_STFWD", + "BriefDescription": "LS3 SRQ forwarded data to a load", + "PublicDescription": "LS3 SRQ forwarded data to a load42" + }, + {, + "EventCode": "0xe0ae", + "EventName": "PM_LSU3_TMA_REQ_L2", + "BriefDescription": "addrs only req to L2 only on the first one,Indication that Load footprint is not expanding", + "PublicDescription": "addrs only req to L2 only on the first one,Indication that Load footprint is not expanding42" + }, + {, + "EventCode": "0xe09e", + "EventName": "PM_LSU3_TM_L1_HIT", + "BriefDescription": "Load tm hit in L1", + "PublicDescription": "Load tm hit in L142" + }, + {, + "EventCode": "0xe0a6", + "EventName": "PM_LSU3_TM_L1_MISS", + "BriefDescription": "Load tm L1 miss", + "PublicDescription": "Load tm L1 miss42" + }, + {, + "EventCode": "0xe880", + "EventName": "PM_LSU_ERAT_MISS_PREF", + "BriefDescription": "Erat miss due to prefetch, on either pipe", + "PublicDescription": "LSU" + }, + {, + "EventCode": "0xc8ac", + "EventName": "PM_LSU_FLUSH_UST", + "BriefDescription": "Unaligned Store Flush on either pipe", + "PublicDescription": "LSU" + }, + {, + "EventCode": "0xd0a4", + "EventName": "PM_LSU_FOUR_TABLEWALK_CYC", + "BriefDescription": "Cycles when four tablewalks pending on this thread", + "PublicDescription": "Cycles when four tablewalks pending on this thread42" + }, + {, + "EventCode": "0x10066", + "EventName": "PM_LSU_FX_FIN", + "BriefDescription": "LSU Finished a FX operation (up to 2 per cycle", + "PublicDescription": "" + }, + {, + "EventCode": "0xd8b8", + "EventName": "PM_LSU_L1_PREF", + "BriefDescription": "hw initiated , include sw streaming forms as well , include sw streams as a separate event", + "PublicDescription": "LSU" + }, + {, + "EventCode": "0xc898", + "EventName": "PM_LSU_L1_SW_PREF", + "BriefDescription": "Software L1 Prefetches, including SW Transient Prefetches, on both pipes", + "PublicDescription": "LSU" + }, + {, + "EventCode": "0xc884", + "EventName": "PM_LSU_LDF", + "BriefDescription": "FPU loads only on LS2/LS3 ie LU0/LU1", + "PublicDescription": "LSU" + }, + {, + "EventCode": "0xc888", + "EventName": "PM_LSU_LDX", + "BriefDescription": "Vector loads can issue only on LS2/LS3", + "PublicDescription": "LSU" + }, + {, + "EventCode": "0xd0a2", + "EventName": "PM_LSU_LMQ_FULL_CYC", + "BriefDescription": "LMQ full", + "PublicDescription": "LMQ fullCycles LMQ full" + }, + {, + "EventCode": "0xd0a1", + "EventName": "PM_LSU_LMQ_S0_ALLOC", + "BriefDescription": "Per thread - use edge detect to count allocates On a per thread basis, level signal indicating Slot 0 is valid. By instrumenting a single slot we can calculate service time for that slot. Previous machines required a separate signal indicating the slot was allocated. Because any signal can be routed to any counter in P8, we can count level in one PMC and edge detect in another PMC using the same signal", + "PublicDescription": "0.0" + }, + {, + "EventCode": "0xd0a0", + "EventName": "PM_LSU_LMQ_S0_VALID", + "BriefDescription": "Slot 0 of LMQ valid", + "PublicDescription": "Slot 0 of LMQ validLMQ slot 0 valid" + }, + {, + "EventCode": "0x3001c", + "EventName": "PM_LSU_LMQ_SRQ_EMPTY_ALL_CYC", + "BriefDescription": "ALL threads lsu empty (lmq and srq empty)", + "PublicDescription": "ALL threads lsu empty (lmq and srq empty). Issue HW016541" + }, + {, + "EventCode": "0xd09f", + "EventName": "PM_LSU_LRQ_S0_ALLOC", + "BriefDescription": "Per thread - use edge detect to count allocates On a per thread basis, level signal indicating Slot 0 is valid. By instrumenting a single slot we can calculate service time for that slot. Previous machines required a separate signal indicating the slot was allocated. Because any signal can be routed to any counter in P8, we can count level in one PMC and edge detect in another PMC using the same signal", + "PublicDescription": "0.0" + }, + {, + "EventCode": "0xd09e", + "EventName": "PM_LSU_LRQ_S0_VALID", + "BriefDescription": "Slot 0 of LRQ valid", + "PublicDescription": "Slot 0 of LRQ validLRQ slot 0 valid" + }, + {, + "EventCode": "0xf091", + "EventName": "PM_LSU_LRQ_S43_ALLOC", + "BriefDescription": "LRQ slot 43 was released", + "PublicDescription": "0.0" + }, + {, + "EventCode": "0xf090", + "EventName": "PM_LSU_LRQ_S43_VALID", + "BriefDescription": "LRQ slot 43 was busy", + "PublicDescription": "LRQ slot 43 was busy42" + }, + {, + "EventCode": "0x30162", + "EventName": "PM_LSU_MRK_DERAT_MISS", + "BriefDescription": "DERAT Reloaded (Miss)", + "PublicDescription": "" + }, + {, + "EventCode": "0xc88c", + "EventName": "PM_LSU_NCLD", + "BriefDescription": "count at finish so can return only on ls0 or ls1", + "PublicDescription": "LSU" + }, + {, + "EventCode": "0xc092", + "EventName": "PM_LSU_NCST", + "BriefDescription": "Non-cachable Stores sent to nest", + "PublicDescription": "Non-cachable Stores sent to nest42" + }, + {, + "EventCode": "0x10064", + "EventName": "PM_LSU_REJECT", + "BriefDescription": "LSU Reject (up to 4 per cycle)", + "PublicDescription": "" + }, + {, + "EventCode": "0xd082", + "EventName": "PM_LSU_SET_MPRED", + "BriefDescription": "Line already in cache at reload time", + "PublicDescription": "Line already in cache at reload time42" + }, + {, + "EventCode": "0x40008", + "EventName": "PM_LSU_SRQ_EMPTY_CYC", + "BriefDescription": "ALL threads srq empty", + "PublicDescription": "All threads srq empty" + }, + {, + "EventCode": "0xd09d", + "EventName": "PM_LSU_SRQ_S0_ALLOC", + "BriefDescription": "Per thread - use edge detect to count allocates On a per thread basis, level signal indicating Slot 0 is valid. By instrumenting a single slot we can calculate service time for that slot. Previous machines required a separate signal indicating the slot was allocated. Because any signal can be routed to any counter in P8, we can count level in one PMC and edge detect in another PMC using the same signal", + "PublicDescription": "0.0" + }, + {, + "EventCode": "0xd09c", + "EventName": "PM_LSU_SRQ_S0_VALID", + "BriefDescription": "Slot 0 of SRQ valid", + "PublicDescription": "Slot 0 of SRQ validSRQ slot 0 valid" + }, + {, + "EventCode": "0xf093", + "EventName": "PM_LSU_SRQ_S39_ALLOC", + "BriefDescription": "SRQ slot 39 was released", + "PublicDescription": "0.0" + }, + {, + "EventCode": "0xf092", + "EventName": "PM_LSU_SRQ_S39_VALID", + "BriefDescription": "SRQ slot 39 was busy", + "PublicDescription": "SRQ slot 39 was busy42" + }, + {, + "EventCode": "0xd09b", + "EventName": "PM_LSU_SRQ_SYNC", + "BriefDescription": "A sync in the SRQ ended", + "PublicDescription": "0.0" + }, + {, + "EventCode": "0xd09a", + "EventName": "PM_LSU_SRQ_SYNC_CYC", + "BriefDescription": "A sync is in the SRQ (edge detect to count)", + "PublicDescription": "A sync is in the SRQ (edge detect to count)SRQ sync duration" + }, + {, + "EventCode": "0xf084", + "EventName": "PM_LSU_STORE_REJECT", + "BriefDescription": "Store reject on either pipe", + "PublicDescription": "LSU" + }, + {, + "EventCode": "0xd0a6", + "EventName": "PM_LSU_TWO_TABLEWALK_CYC", + "BriefDescription": "Cycles when two tablewalks pending on this thread", + "PublicDescription": "Cycles when two tablewalks pending on this thread42" + }, + {, + "EventCode": "0x5094", + "EventName": "PM_LWSYNC", + "BriefDescription": "threaded version, IC Misses where we got EA dir hit but no sector valids were on. ICBI took line out", + "PublicDescription": "" + }, + {, + "EventCode": "0x209a", + "EventName": "PM_LWSYNC_HELD", + "BriefDescription": "LWSYNC held at dispatch", + "PublicDescription": "" + }, + {, + "EventCode": "0x3013a", + "EventName": "PM_MRK_CRU_FIN", + "BriefDescription": "IFU non-branch finished", + "PublicDescription": "IFU non-branch marked instruction finished" + }, + {, + "EventCode": "0x4d146", + "EventName": "PM_MRK_DATA_FROM_L21_MOD", + "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x2d126", + "EventName": "PM_MRK_DATA_FROM_L21_MOD_CYC", + "BriefDescription": "Duration in cycles to reload with Modified (M) data from another core's L2 on the same chip due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x3d146", + "EventName": "PM_MRK_DATA_FROM_L21_SHR", + "BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x2c126", + "EventName": "PM_MRK_DATA_FROM_L21_SHR_CYC", + "BriefDescription": "Duration in cycles to reload with Shared (S) data from another core's L2 on the same chip due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x4d144", + "EventName": "PM_MRK_DATA_FROM_L31_ECO_MOD", + "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x2d124", + "EventName": "PM_MRK_DATA_FROM_L31_ECO_MOD_CYC", + "BriefDescription": "Duration in cycles to reload with Modified (M) data from another core's ECO L3 on the same chip due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x3d144", + "EventName": "PM_MRK_DATA_FROM_L31_ECO_SHR", + "BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x2c124", + "EventName": "PM_MRK_DATA_FROM_L31_ECO_SHR_CYC", + "BriefDescription": "Duration in cycles to reload with Shared (S) data from another core's ECO L3 on the same chip due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x2d144", + "EventName": "PM_MRK_DATA_FROM_L31_MOD", + "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x4d124", + "EventName": "PM_MRK_DATA_FROM_L31_MOD_CYC", + "BriefDescription": "Duration in cycles to reload with Modified (M) data from another core's L3 on the same chip due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x1d146", + "EventName": "PM_MRK_DATA_FROM_L31_SHR", + "BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x4c126", + "EventName": "PM_MRK_DATA_FROM_L31_SHR_CYC", + "BriefDescription": "Duration in cycles to reload with Shared (S) data from another core's L3 on the same chip due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x201e0", + "EventName": "PM_MRK_DATA_FROM_MEM", + "BriefDescription": "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked load", + "PublicDescription": "" + }, + {, + "EventCode": "0x4f146", + "EventName": "PM_MRK_DPTEG_FROM_L21_MOD", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a marked data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x3f146", + "EventName": "PM_MRK_DPTEG_FROM_L21_SHR", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a marked data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x3f140", + "EventName": "PM_MRK_DPTEG_FROM_L2_DISP_CONFLICT_LDHITST", + "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 with load hit store conflict due to a marked data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x4f140", + "EventName": "PM_MRK_DPTEG_FROM_L2_DISP_CONFLICT_OTHER", + "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 with dispatch conflict due to a marked data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x4f144", + "EventName": "PM_MRK_DPTEG_FROM_L31_ECO_MOD", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a marked data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x3f144", + "EventName": "PM_MRK_DPTEG_FROM_L31_ECO_SHR", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a marked data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x2f144", + "EventName": "PM_MRK_DPTEG_FROM_L31_MOD", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a marked data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x1f146", + "EventName": "PM_MRK_DPTEG_FROM_L31_SHR", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a marked data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x30156", + "EventName": "PM_MRK_FAB_RSP_MATCH", + "BriefDescription": "ttype and cresp matched as specified in MMCR1", + "PublicDescription": "" + }, + {, + "EventCode": "0x4f152", + "EventName": "PM_MRK_FAB_RSP_MATCH_CYC", + "BriefDescription": "cresp/ttype match cycles", + "PublicDescription": "" + }, + {, + "EventCode": "0x2013c", + "EventName": "PM_MRK_FILT_MATCH", + "BriefDescription": "Marked filter Match", + "PublicDescription": "" + }, + {, + "EventCode": "0x1013c", + "EventName": "PM_MRK_FIN_STALL_CYC", + "BriefDescription": "Marked instruction Finish Stall cycles (marked finish after NTC) (use edge detect to count )", + "PublicDescription": "Marked instruction Finish Stall cycles (marked finish after NTC) (use edge detect to count #)" + }, + {, + "EventCode": "0x40130", + "EventName": "PM_MRK_GRP_CMPL", + "BriefDescription": "marked instruction finished (completed)", + "PublicDescription": "" + }, + {, + "EventCode": "0x4013a", + "EventName": "PM_MRK_GRP_IC_MISS", + "BriefDescription": "Marked Group experienced I cache miss", + "PublicDescription": "" + }, + {, + "EventCode": "0x3013c", + "EventName": "PM_MRK_GRP_NTC", + "BriefDescription": "Marked group ntc cycles", + "PublicDescription": "" + }, + {, + "EventCode": "0x1013f", + "EventName": "PM_MRK_LD_MISS_EXPOSED", + "BriefDescription": "Marked Load exposed Miss (exposed period ended)", + "PublicDescription": "Marked Load exposed Miss (use edge detect to count #)" + }, + {, + "EventCode": "0xd180", + "EventName": "PM_MRK_LSU_FLUSH", + "BriefDescription": "Flush: (marked) : All Cases", + "PublicDescription": "Flush: (marked) : All Cases42" + }, + {, + "EventCode": "0xd188", + "EventName": "PM_MRK_LSU_FLUSH_LRQ", + "BriefDescription": "Flush: (marked) LRQ", + "PublicDescription": "Flush: (marked) LRQMarked LRQ flushes" + }, + {, + "EventCode": "0xd18a", + "EventName": "PM_MRK_LSU_FLUSH_SRQ", + "BriefDescription": "Flush: (marked) SRQ", + "PublicDescription": "Flush: (marked) SRQMarked SRQ lhs flushes" + }, + {, + "EventCode": "0xd184", + "EventName": "PM_MRK_LSU_FLUSH_ULD", + "BriefDescription": "Flush: (marked) Unaligned Load", + "PublicDescription": "Flush: (marked) Unaligned LoadMarked unaligned load flushes" + }, + {, + "EventCode": "0xd186", + "EventName": "PM_MRK_LSU_FLUSH_UST", + "BriefDescription": "Flush: (marked) Unaligned Store", + "PublicDescription": "Flush: (marked) Unaligned StoreMarked unaligned store flushes" + }, + {, + "EventCode": "0x40164", + "EventName": "PM_MRK_LSU_REJECT", + "BriefDescription": "LSU marked reject (up to 2 per cycle)", + "PublicDescription": "" + }, + {, + "EventCode": "0x30164", + "EventName": "PM_MRK_LSU_REJECT_ERAT_MISS", + "BriefDescription": "LSU marked reject due to ERAT (up to 2 per cycle)", + "PublicDescription": "" + }, + {, + "EventCode": "0x1d15a", + "EventName": "PM_MRK_SRC_PREF_TRACK_EFF", + "BriefDescription": "Marked src pref track was effective", + "PublicDescription": "" + }, + {, + "EventCode": "0x3d15a", + "EventName": "PM_MRK_SRC_PREF_TRACK_INEFF", + "BriefDescription": "Prefetch tracked was ineffective for marked src", + "PublicDescription": "" + }, + {, + "EventCode": "0x4d15c", + "EventName": "PM_MRK_SRC_PREF_TRACK_MOD", + "BriefDescription": "Prefetch tracked was moderate for marked src", + "PublicDescription": "" + }, + {, + "EventCode": "0x1d15c", + "EventName": "PM_MRK_SRC_PREF_TRACK_MOD_L2", + "BriefDescription": "Marked src Prefetch Tracked was moderate (source L2)", + "PublicDescription": "" + }, + {, + "EventCode": "0x3d15c", + "EventName": "PM_MRK_SRC_PREF_TRACK_MOD_L3", + "BriefDescription": "Prefetch tracked was moderate (L3 hit) for marked src", + "PublicDescription": "" + }, + {, + "EventCode": "0x1c15a", + "EventName": "PM_MRK_TGT_PREF_TRACK_EFF", + "BriefDescription": "Marked target pref track was effective", + "PublicDescription": "" + }, + {, + "EventCode": "0x3c15a", + "EventName": "PM_MRK_TGT_PREF_TRACK_INEFF", + "BriefDescription": "Prefetch tracked was ineffective for marked target", + "PublicDescription": "" + }, + {, + "EventCode": "0x4c15c", + "EventName": "PM_MRK_TGT_PREF_TRACK_MOD", + "BriefDescription": "Prefetch tracked was moderate for marked target", + "PublicDescription": "" + }, + {, + "EventCode": "0x1c15c", + "EventName": "PM_MRK_TGT_PREF_TRACK_MOD_L2", + "BriefDescription": "Marked target Prefetch Tracked was moderate (source L2)", + "PublicDescription": "" + }, + {, + "EventCode": "0x3c15c", + "EventName": "PM_MRK_TGT_PREF_TRACK_MOD_L3", + "BriefDescription": "Prefetch tracked was moderate (L3 hit) for marked target", + "PublicDescription": "" + }, + {, + "EventCode": "0x20b0", + "EventName": "PM_NESTED_TEND", + "BriefDescription": "Completion time nested tend", + "PublicDescription": "" + }, + {, + "EventCode": "0x20b6", + "EventName": "PM_NON_FAV_TBEGIN", + "BriefDescription": "Dispatch time non favored tbegin", + "PublicDescription": "" + }, + {, + "EventCode": "0x328084", + "EventName": "PM_NON_TM_RST_SC", + "BriefDescription": "non tm snp rst tm sc", + "PublicDescription": "" + }, + {, + "EventCode": "0x2001a", + "EventName": "PM_NTCG_ALL_FIN", + "BriefDescription": "Cycles after all instructions have finished to group completed", + "PublicDescription": "Ccycles after all instructions have finished to group completed" + }, + {, + "EventCode": "0x20ac", + "EventName": "PM_OUTER_TBEGIN", + "BriefDescription": "Completion time outer tbegin", + "PublicDescription": "" + }, + {, + "EventCode": "0x20ae", + "EventName": "PM_OUTER_TEND", + "BriefDescription": "Completion time outer tend", + "PublicDescription": "" + }, + {, + "EventCode": "0x2005a", + "EventName": "PM_PREF_TRACKED", + "BriefDescription": "Total number of Prefetch Operations that were tracked", + "PublicDescription": "" + }, + {, + "EventCode": "0x1005a", + "EventName": "PM_PREF_TRACK_EFF", + "BriefDescription": "Prefetch Tracked was effective", + "PublicDescription": "" + }, + {, + "EventCode": "0x3005a", + "EventName": "PM_PREF_TRACK_INEFF", + "BriefDescription": "Prefetch tracked was ineffective", + "PublicDescription": "" + }, + {, + "EventCode": "0x4005a", + "EventName": "PM_PREF_TRACK_MOD", + "BriefDescription": "Prefetch tracked was moderate", + "PublicDescription": "" + }, + {, + "EventCode": "0x1005c", + "EventName": "PM_PREF_TRACK_MOD_L2", + "BriefDescription": "Prefetch Tracked was moderate (source L2)", + "PublicDescription": "" + }, + {, + "EventCode": "0x3005c", + "EventName": "PM_PREF_TRACK_MOD_L3", + "BriefDescription": "Prefetch tracked was moderate (L3)", + "PublicDescription": "" + }, + {, + "EventCode": "0xe084", + "EventName": "PM_PTE_PREFETCH", + "BriefDescription": "PTE prefetches", + "PublicDescription": "PTE prefetches42" + }, + {, + "EventCode": "0x16081", + "EventName": "PM_RC0_ALLOC", + "BriefDescription": "RC mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point)", + "PublicDescription": "0.0" + }, + {, + "EventCode": "0x16080", + "EventName": "PM_RC0_BUSY", + "BriefDescription": "RC mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point)", + "PublicDescription": "" + }, + {, + "EventCode": "0x200301ea", + "EventName": "PM_RC_LIFETIME_EXC_1024", + "BriefDescription": "Number of times the RC machine for a sampled instruction was active for more than 1024 cycles", + "PublicDescription": "Reload latency exceeded 1024 cyc" + }, + {, + "EventCode": "0x200401ec", + "EventName": "PM_RC_LIFETIME_EXC_2048", + "BriefDescription": "Number of times the RC machine for a sampled instruction was active for more than 2048 cycles", + "PublicDescription": "Threshold counter exceeded a value of 2048" + }, + {, + "EventCode": "0x200101e8", + "EventName": "PM_RC_LIFETIME_EXC_256", + "BriefDescription": "Number of times the RC machine for a sampled instruction was active for more than 256 cycles", + "PublicDescription": "Threshold counter exceed a count of 256" + }, + {, + "EventCode": "0x200201e6", + "EventName": "PM_RC_LIFETIME_EXC_32", + "BriefDescription": "Number of times the RC machine for a sampled instruction was active for more than 32 cycles", + "PublicDescription": "Reload latency exceeded 32 cyc" + }, + {, + "EventCode": "0x36088", + "EventName": "PM_RC_USAGE", + "BriefDescription": "Continuous 16 cycle(2to1) window where this signals rotates thru sampling each L2 RC machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running", + "PublicDescription": "" + }, + {, + "EventCode": "0x34808e", + "EventName": "PM_RD_CLEARING_SC", + "BriefDescription": "rd clearing sc", + "PublicDescription": "" + }, + {, + "EventCode": "0x34808c", + "EventName": "PM_RD_FORMING_SC", + "BriefDescription": "rd forming sc", + "PublicDescription": "" + }, + {, + "EventCode": "0x428086", + "EventName": "PM_RD_HIT_PF", + "BriefDescription": "rd machine hit l3 pf machine", + "PublicDescription": "" + }, + {, + "EventCode": "0x20004", + "EventName": "PM_REAL_SRQ_FULL", + "BriefDescription": "Out of real srq entries", + "PublicDescription": "" + }, + {, + "EventCode": "0x2006a", + "EventName": "PM_RUN_CYC_SMT2_SHRD_MODE", + "BriefDescription": "cycles this threads run latch is set and the core is in SMT2 shared mode", + "PublicDescription": "Cycles run latch is set and core is in SMT2-shared mode" + }, + {, + "EventCode": "0x1006a", + "EventName": "PM_RUN_CYC_SMT2_SPLIT_MODE", + "BriefDescription": "Cycles run latch is set and core is in SMT2-split mode", + "PublicDescription": "" + }, + {, + "EventCode": "0x4006c", + "EventName": "PM_RUN_CYC_SMT8_MODE", + "BriefDescription": "Cycles run latch is set and core is in SMT8 mode", + "PublicDescription": "" + }, + {, + "EventCode": "0xf082", + "EventName": "PM_SEC_ERAT_HIT", + "BriefDescription": "secondary ERAT Hit", + "PublicDescription": "secondary ERAT Hit42" + }, + {, + "EventCode": "0x508c", + "EventName": "PM_SHL_CREATED", + "BriefDescription": "Store-Hit-Load Table Entry Created", + "PublicDescription": "" + }, + {, + "EventCode": "0x508e", + "EventName": "PM_SHL_ST_CONVERT", + "BriefDescription": "Store-Hit-Load Table Read Hit with entry Enabled", + "PublicDescription": "" + }, + {, + "EventCode": "0x5090", + "EventName": "PM_SHL_ST_DISABLE", + "BriefDescription": "Store-Hit-Load Table Read Hit with entry Disabled (entry was disabled due to the entry shown to not prevent the flush)", + "PublicDescription": "" + }, + {, + "EventCode": "0x26085", + "EventName": "PM_SN0_ALLOC", + "BriefDescription": "SN mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point)", + "PublicDescription": "0.0" + }, + {, + "EventCode": "0x26084", + "EventName": "PM_SN0_BUSY", + "BriefDescription": "SN mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point)", + "PublicDescription": "" + }, + {, + "EventCode": "0xd0b2", + "EventName": "PM_SNOOP_TLBIE", + "BriefDescription": "TLBIE snoop", + "PublicDescription": "TLBIE snoopSnoop TLBIE" + }, + {, + "EventCode": "0x338088", + "EventName": "PM_SNP_TM_HIT_M", + "BriefDescription": "snp tm st hit m mu", + "PublicDescription": "" + }, + {, + "EventCode": "0x33808a", + "EventName": "PM_SNP_TM_HIT_T", + "BriefDescription": "snp tm_st_hit t tn te", + "PublicDescription": "" + }, + {, + "EventCode": "0x4608c", + "EventName": "PM_SN_USAGE", + "BriefDescription": "Continuous 16 cycle(2to1) window where this signals rotates thru sampling each L2 SN machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running", + "PublicDescription": "" + }, + {, + "EventCode": "0x10028", + "EventName": "PM_STALL_END_GCT_EMPTY", + "BriefDescription": "Count ended because GCT went empty", + "PublicDescription": "" + }, + {, + "EventCode": "0xc090", + "EventName": "PM_STCX_LSU", + "BriefDescription": "STCX executed reported at sent to nest", + "PublicDescription": "STCX executed reported at sent to nest42" + }, + {, + "EventCode": "0x717080", + "EventName": "PM_ST_CAUSED_FAIL", + "BriefDescription": "Non TM St caused any thread to fail", + "PublicDescription": "" + }, + {, + "EventCode": "0x3090", + "EventName": "PM_SWAP_CANCEL", + "BriefDescription": "SWAP cancel , rtag not available", + "PublicDescription": "" + }, + {, + "EventCode": "0x3092", + "EventName": "PM_SWAP_CANCEL_GPR", + "BriefDescription": "SWAP cancel , rtag not available for gpr", + "PublicDescription": "" + }, + {, + "EventCode": "0x308c", + "EventName": "PM_SWAP_COMPLETE", + "BriefDescription": "swap cast in completed", + "PublicDescription": "" + }, + {, + "EventCode": "0x308e", + "EventName": "PM_SWAP_COMPLETE_GPR", + "BriefDescription": "swap cast in completed fpr gpr", + "PublicDescription": "" + }, + {, + "EventCode": "0xe086", + "EventName": "PM_TABLEWALK_CYC_PREF", + "BriefDescription": "tablewalk qualified for pte prefetches", + "PublicDescription": "tablewalk qualified for pte prefetches42" + }, + {, + "EventCode": "0x20b2", + "EventName": "PM_TABORT_TRECLAIM", + "BriefDescription": "Completion time tabortnoncd, tabortcd, treclaim", + "PublicDescription": "" + }, + {, + "EventCode": "0xe0ba", + "EventName": "PM_TEND_PEND_CYC", + "BriefDescription": "TEND latency per thread", + "PublicDescription": "TEND latency per thread42" + }, + {, + "EventCode": "0x10012", + "EventName": "PM_THRD_GRP_CMPL_BOTH_CYC", + "BriefDescription": "Cycles group completed on both completion slots by any thread", + "PublicDescription": "Two threads finished same cycle (gated by run latch)" + }, + {, + "EventCode": "0x40bc", + "EventName": "PM_THRD_PRIO_0_1_CYC", + "BriefDescription": "Cycles thread running at priority level 0 or 1", + "PublicDescription": "" + }, + {, + "EventCode": "0x40be", + "EventName": "PM_THRD_PRIO_2_3_CYC", + "BriefDescription": "Cycles thread running at priority level 2 or 3", + "PublicDescription": "" + }, + {, + "EventCode": "0x5080", + "EventName": "PM_THRD_PRIO_4_5_CYC", + "BriefDescription": "Cycles thread running at priority level 4 or 5", + "PublicDescription": "" + }, + {, + "EventCode": "0x5082", + "EventName": "PM_THRD_PRIO_6_7_CYC", + "BriefDescription": "Cycles thread running at priority level 6 or 7", + "PublicDescription": "" + }, + {, + "EventCode": "0x3098", + "EventName": "PM_THRD_REBAL_CYC", + "BriefDescription": "cycles rebalance was active", + "PublicDescription": "" + }, + {, + "EventCode": "0x20b8", + "EventName": "PM_TM_BEGIN_ALL", + "BriefDescription": "Tm any tbegin", + "PublicDescription": "" + }, + {, + "EventCode": "0x318082", + "EventName": "PM_TM_CAM_OVERFLOW", + "BriefDescription": "l3 tm cam overflow during L2 co of SC", + "PublicDescription": "" + }, + {, + "EventCode": "0x74708c", + "EventName": "PM_TM_CAP_OVERFLOW", + "BriefDescription": "TM Footprint Capactiy Overflow", + "PublicDescription": "" + }, + {, + "EventCode": "0x20ba", + "EventName": "PM_TM_END_ALL", + "BriefDescription": "Tm any tend", + "PublicDescription": "" + }, + {, + "EventCode": "0x3086", + "EventName": "PM_TM_FAIL_CONF_NON_TM", + "BriefDescription": "TEXAS fail reason @ completion", + "PublicDescription": "" + }, + {, + "EventCode": "0x3088", + "EventName": "PM_TM_FAIL_CON_TM", + "BriefDescription": "TEXAS fail reason @ completion", + "PublicDescription": "" + }, + {, + "EventCode": "0xe0b2", + "EventName": "PM_TM_FAIL_DISALLOW", + "BriefDescription": "TM fail disallow", + "PublicDescription": "TM fail disallow42" + }, + {, + "EventCode": "0x3084", + "EventName": "PM_TM_FAIL_FOOTPRINT_OVERFLOW", + "BriefDescription": "TEXAS fail reason @ completion", + "PublicDescription": "" + }, + {, + "EventCode": "0xe0b8", + "EventName": "PM_TM_FAIL_NON_TX_CONFLICT", + "BriefDescription": "Non transactional conflict from LSU whtver gets repoted to texas", + "PublicDescription": "Non transactional conflict from LSU whtver gets repoted to texas42" + }, + {, + "EventCode": "0x308a", + "EventName": "PM_TM_FAIL_SELF", + "BriefDescription": "TEXAS fail reason @ completion", + "PublicDescription": "" + }, + {, + "EventCode": "0xe0b4", + "EventName": "PM_TM_FAIL_TLBIE", + "BriefDescription": "TLBIE hit bloom filter", + "PublicDescription": "TLBIE hit bloom filter42" + }, + {, + "EventCode": "0xe0b6", + "EventName": "PM_TM_FAIL_TX_CONFLICT", + "BriefDescription": "Transactional conflict from LSU, whatever gets reported to texas", + "PublicDescription": "Transactional conflict from LSU, whatever gets reported to texas 42" + }, + {, + "EventCode": "0x727086", + "EventName": "PM_TM_FAV_CAUSED_FAIL", + "BriefDescription": "TM Load (fav) caused another thread to fail", + "PublicDescription": "" + }, + {, + "EventCode": "0x717082", + "EventName": "PM_TM_LD_CAUSED_FAIL", + "BriefDescription": "Non TM Ld caused any thread to fail", + "PublicDescription": "" + }, + {, + "EventCode": "0x727084", + "EventName": "PM_TM_LD_CONF", + "BriefDescription": "TM Load (fav or non-fav) ran into conflict (failed)", + "PublicDescription": "" + }, + {, + "EventCode": "0x328086", + "EventName": "PM_TM_RST_SC", + "BriefDescription": "tm snp rst tm sc", + "PublicDescription": "" + }, + {, + "EventCode": "0x318080", + "EventName": "PM_TM_SC_CO", + "BriefDescription": "l3 castout tm Sc line", + "PublicDescription": "" + }, + {, + "EventCode": "0x73708a", + "EventName": "PM_TM_ST_CAUSED_FAIL", + "BriefDescription": "TM Store (fav or non-fav) caused another thread to fail", + "PublicDescription": "" + }, + {, + "EventCode": "0x737088", + "EventName": "PM_TM_ST_CONF", + "BriefDescription": "TM Store (fav or non-fav) ran into conflict (failed)", + "PublicDescription": "" + }, + {, + "EventCode": "0x20bc", + "EventName": "PM_TM_TBEGIN", + "BriefDescription": "Tm nested tbegin", + "PublicDescription": "" + }, + {, + "EventCode": "0x3080", + "EventName": "PM_TM_TRESUME", + "BriefDescription": "Tm resume", + "PublicDescription": "" + }, + {, + "EventCode": "0x20be", + "EventName": "PM_TM_TSUSPEND", + "BriefDescription": "Tm suspend", + "PublicDescription": "" + }, + {, + "EventCode": "0xe08c", + "EventName": "PM_UP_PREF_L3", + "BriefDescription": "Micropartition prefetch", + "PublicDescription": "Micropartition prefetch42" + }, + {, + "EventCode": "0xe08e", + "EventName": "PM_UP_PREF_POINTER", + "BriefDescription": "Micrpartition pointer prefetches", + "PublicDescription": "Micrpartition pointer prefetches42" + }, + {, + "EventCode": "0xa0a4", + "EventName": "PM_VSU0_16FLOP", + "BriefDescription": "Sixteen flops operation (SP vector versions of fdiv,fsqrt)", + "PublicDescription": "" + }, + {, + "EventCode": "0xa080", + "EventName": "PM_VSU0_1FLOP", + "BriefDescription": "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished", + "PublicDescription": "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finishedDecode into 1,2,4 FLOP according to instr IOP, multiplied by #vector elements according to route( eg x1, x2, x4) Only if instr sends finish to ISU" + }, + {, + "EventCode": "0xa098", + "EventName": "PM_VSU0_2FLOP", + "BriefDescription": "two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)", + "PublicDescription": "" + }, + {, + "EventCode": "0xa09c", + "EventName": "PM_VSU0_4FLOP", + "BriefDescription": "four flops operation (scalar fdiv, fsqrt, DP vector version of fmadd, fnmadd, fmsub, fnmsub, SP vector versions of single flop instructions)", + "PublicDescription": "" + }, + {, + "EventCode": "0xa0a0", + "EventName": "PM_VSU0_8FLOP", + "BriefDescription": "eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub)", + "PublicDescription": "" + }, + {, + "EventCode": "0xb0a4", + "EventName": "PM_VSU0_COMPLEX_ISSUED", + "BriefDescription": "Complex VMX instruction issued", + "PublicDescription": "" + }, + {, + "EventCode": "0xb0b4", + "EventName": "PM_VSU0_CY_ISSUED", + "BriefDescription": "Cryptographic instruction RFC02196 Issued", + "PublicDescription": "" + }, + {, + "EventCode": "0xb0a8", + "EventName": "PM_VSU0_DD_ISSUED", + "BriefDescription": "64BIT Decimal Issued", + "PublicDescription": "" + }, + {, + "EventCode": "0xa08c", + "EventName": "PM_VSU0_DP_2FLOP", + "BriefDescription": "DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg", + "PublicDescription": "" + }, + {, + "EventCode": "0xa090", + "EventName": "PM_VSU0_DP_FMA", + "BriefDescription": "DP vector version of fmadd,fnmadd,fmsub,fnmsub", + "PublicDescription": "" + }, + {, + "EventCode": "0xa094", + "EventName": "PM_VSU0_DP_FSQRT_FDIV", + "BriefDescription": "DP vector versions of fdiv,fsqrt", + "PublicDescription": "" + }, + {, + "EventCode": "0xb0ac", + "EventName": "PM_VSU0_DQ_ISSUED", + "BriefDescription": "128BIT Decimal Issued", + "PublicDescription": "" + }, + {, + "EventCode": "0xb0b0", + "EventName": "PM_VSU0_EX_ISSUED", + "BriefDescription": "Direct move 32/64b VRFtoGPR RFC02206 Issued", + "PublicDescription": "" + }, + {, + "EventCode": "0xa0bc", + "EventName": "PM_VSU0_FIN", + "BriefDescription": "VSU0 Finished an instruction", + "PublicDescription": "" + }, + {, + "EventCode": "0xa084", + "EventName": "PM_VSU0_FMA", + "BriefDescription": "two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only!", + "PublicDescription": "" + }, + {, + "EventCode": "0xb098", + "EventName": "PM_VSU0_FPSCR", + "BriefDescription": "Move to/from FPSCR type instruction issued on Pipe 0", + "PublicDescription": "" + }, + {, + "EventCode": "0xa088", + "EventName": "PM_VSU0_FSQRT_FDIV", + "BriefDescription": "four flops operation (fdiv,fsqrt) Scalar Instructions only!", + "PublicDescription": "" + }, + {, + "EventCode": "0xb090", + "EventName": "PM_VSU0_PERMUTE_ISSUED", + "BriefDescription": "Permute VMX Instruction Issued", + "PublicDescription": "" + }, + {, + "EventCode": "0xb088", + "EventName": "PM_VSU0_SCALAR_DP_ISSUED", + "BriefDescription": "Double Precision scalar instruction issued on Pipe0", + "PublicDescription": "" + }, + {, + "EventCode": "0xb094", + "EventName": "PM_VSU0_SIMPLE_ISSUED", + "BriefDescription": "Simple VMX instruction issued", + "PublicDescription": "" + }, + {, + "EventCode": "0xa0a8", + "EventName": "PM_VSU0_SINGLE", + "BriefDescription": "FPU single precision", + "PublicDescription": "" + }, + {, + "EventCode": "0xb09c", + "EventName": "PM_VSU0_SQ", + "BriefDescription": "Store Vector Issued", + "PublicDescription": "" + }, + {, + "EventCode": "0xb08c", + "EventName": "PM_VSU0_STF", + "BriefDescription": "FPU store (SP or DP) issued on Pipe0", + "PublicDescription": "" + }, + {, + "EventCode": "0xb080", + "EventName": "PM_VSU0_VECTOR_DP_ISSUED", + "BriefDescription": "Double Precision vector instruction issued on Pipe0", + "PublicDescription": "" + }, + {, + "EventCode": "0xb084", + "EventName": "PM_VSU0_VECTOR_SP_ISSUED", + "BriefDescription": "Single Precision vector instruction issued (executed)", + "PublicDescription": "" + }, + {, + "EventCode": "0xa0a6", + "EventName": "PM_VSU1_16FLOP", + "BriefDescription": "Sixteen flops operation (SP vector versions of fdiv,fsqrt)", + "PublicDescription": "" + }, + {, + "EventCode": "0xa082", + "EventName": "PM_VSU1_1FLOP", + "BriefDescription": "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished", + "PublicDescription": "" + }, + {, + "EventCode": "0xa09a", + "EventName": "PM_VSU1_2FLOP", + "BriefDescription": "two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)", + "PublicDescription": "" + }, + {, + "EventCode": "0xa09e", + "EventName": "PM_VSU1_4FLOP", + "BriefDescription": "four flops operation (scalar fdiv, fsqrt, DP vector version of fmadd, fnmadd, fmsub, fnmsub, SP vector versions of single flop instructions)", + "PublicDescription": "" + }, + {, + "EventCode": "0xa0a2", + "EventName": "PM_VSU1_8FLOP", + "BriefDescription": "eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub)", + "PublicDescription": "" + }, + {, + "EventCode": "0xb0a6", + "EventName": "PM_VSU1_COMPLEX_ISSUED", + "BriefDescription": "Complex VMX instruction issued", + "PublicDescription": "" + }, + {, + "EventCode": "0xb0b6", + "EventName": "PM_VSU1_CY_ISSUED", + "BriefDescription": "Cryptographic instruction RFC02196 Issued", + "PublicDescription": "" + }, + {, + "EventCode": "0xb0aa", + "EventName": "PM_VSU1_DD_ISSUED", + "BriefDescription": "64BIT Decimal Issued", + "PublicDescription": "" + }, + {, + "EventCode": "0xa08e", + "EventName": "PM_VSU1_DP_2FLOP", + "BriefDescription": "DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg", + "PublicDescription": "" + }, + {, + "EventCode": "0xa092", + "EventName": "PM_VSU1_DP_FMA", + "BriefDescription": "DP vector version of fmadd,fnmadd,fmsub,fnmsub", + "PublicDescription": "" + }, + {, + "EventCode": "0xa096", + "EventName": "PM_VSU1_DP_FSQRT_FDIV", + "BriefDescription": "DP vector versions of fdiv,fsqrt", + "PublicDescription": "" + }, + {, + "EventCode": "0xb0ae", + "EventName": "PM_VSU1_DQ_ISSUED", + "BriefDescription": "128BIT Decimal Issued", + "PublicDescription": "" + }, + {, + "EventCode": "0xb0b2", + "EventName": "PM_VSU1_EX_ISSUED", + "BriefDescription": "Direct move 32/64b VRFtoGPR RFC02206 Issued", + "PublicDescription": "" + }, + {, + "EventCode": "0xa0be", + "EventName": "PM_VSU1_FIN", + "BriefDescription": "VSU1 Finished an instruction", + "PublicDescription": "" + }, + {, + "EventCode": "0xa086", + "EventName": "PM_VSU1_FMA", + "BriefDescription": "two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only!", + "PublicDescription": "" + }, + {, + "EventCode": "0xb09a", + "EventName": "PM_VSU1_FPSCR", + "BriefDescription": "Move to/from FPSCR type instruction issued on Pipe 0", + "PublicDescription": "" + }, + {, + "EventCode": "0xa08a", + "EventName": "PM_VSU1_FSQRT_FDIV", + "BriefDescription": "four flops operation (fdiv,fsqrt) Scalar Instructions only!", + "PublicDescription": "" + }, + {, + "EventCode": "0xb092", + "EventName": "PM_VSU1_PERMUTE_ISSUED", + "BriefDescription": "Permute VMX Instruction Issued", + "PublicDescription": "" + }, + {, + "EventCode": "0xb08a", + "EventName": "PM_VSU1_SCALAR_DP_ISSUED", + "BriefDescription": "Double Precision scalar instruction issued on Pipe1", + "PublicDescription": "" + }, + {, + "EventCode": "0xb096", + "EventName": "PM_VSU1_SIMPLE_ISSUED", + "BriefDescription": "Simple VMX instruction issued", + "PublicDescription": "" + }, + {, + "EventCode": "0xa0aa", + "EventName": "PM_VSU1_SINGLE", + "BriefDescription": "FPU single precision", + "PublicDescription": "" + }, + {, + "EventCode": "0xb09e", + "EventName": "PM_VSU1_SQ", + "BriefDescription": "Store Vector Issued", + "PublicDescription": "" + }, + {, + "EventCode": "0xb08e", + "EventName": "PM_VSU1_STF", + "BriefDescription": "FPU store (SP or DP) issued on Pipe1", + "PublicDescription": "" + }, + {, + "EventCode": "0xb082", + "EventName": "PM_VSU1_VECTOR_DP_ISSUED", + "BriefDescription": "Double Precision vector instruction issued on Pipe1", + "PublicDescription": "" + }, + {, + "EventCode": "0xb086", + "EventName": "PM_VSU1_VECTOR_SP_ISSUED", + "BriefDescription": "Single Precision vector instruction issued (executed)", + "PublicDescription": "" + }, +] diff --git a/tools/perf/pmu-events/arch/powerpc/power8/pipeline.json b/tools/perf/pmu-events/arch/powerpc/power8/pipeline.json new file mode 100644 index 000000000000..293f3a4c6901 --- /dev/null +++ b/tools/perf/pmu-events/arch/powerpc/power8/pipeline.json @@ -0,0 +1,350 @@ +[ + {, + "EventCode": "0x100f2", + "EventName": "PM_1PLUS_PPC_CMPL", + "BriefDescription": "1 or more ppc insts finished", + "PublicDescription": "1 or more ppc insts finished (completed)" + }, + {, + "EventCode": "0x400f2", + "EventName": "PM_1PLUS_PPC_DISP", + "BriefDescription": "Cycles at least one Instr Dispatched", + "PublicDescription": "Cycles at least one Instr Dispatched. Could be a group with only microcode. Issue HW016521" + }, + {, + "EventCode": "0x100fa", + "EventName": "PM_ANY_THRD_RUN_CYC", + "BriefDescription": "One of threads in run_cycles", + "PublicDescription": "Any thread in run_cycles (was one thread in run_cycles)" + }, + {, + "EventCode": "0x4000a", + "EventName": "PM_CMPLU_STALL", + "BriefDescription": "Completion stall", + "PublicDescription": "" + }, + {, + "EventCode": "0x4d018", + "EventName": "PM_CMPLU_STALL_BRU", + "BriefDescription": "Completion stall due to a Branch Unit", + "PublicDescription": "" + }, + {, + "EventCode": "0x2c012", + "EventName": "PM_CMPLU_STALL_DCACHE_MISS", + "BriefDescription": "Completion stall by Dcache miss", + "PublicDescription": "" + }, + {, + "EventCode": "0x2c018", + "EventName": "PM_CMPLU_STALL_DMISS_L21_L31", + "BriefDescription": "Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3)", + "PublicDescription": "" + }, + {, + "EventCode": "0x2c016", + "EventName": "PM_CMPLU_STALL_DMISS_L2L3", + "BriefDescription": "Completion stall by Dcache miss which resolved in L2/L3", + "PublicDescription": "" + }, + {, + "EventCode": "0x4c016", + "EventName": "PM_CMPLU_STALL_DMISS_L2L3_CONFLICT", + "BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 with a conflict", + "PublicDescription": "Completion stall due to cache miss resolving in core's L2/L3 with a conflict" + }, + {, + "EventCode": "0x4c01a", + "EventName": "PM_CMPLU_STALL_DMISS_L3MISS", + "BriefDescription": "Completion stall due to cache miss resolving missed the L3", + "PublicDescription": "" + }, + {, + "EventCode": "0x4c018", + "EventName": "PM_CMPLU_STALL_DMISS_LMEM", + "BriefDescription": "Completion stall due to cache miss that resolves in local memory", + "PublicDescription": "Completion stall due to cache miss resolving in core's Local Memory" + }, + {, + "EventCode": "0x2c01c", + "EventName": "PM_CMPLU_STALL_DMISS_REMOTE", + "BriefDescription": "Completion stall by Dcache miss which resolved from remote chip (cache or memory)", + "PublicDescription": "Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3)" + }, + {, + "EventCode": "0x4c012", + "EventName": "PM_CMPLU_STALL_ERAT_MISS", + "BriefDescription": "Completion stall due to LSU reject ERAT miss", + "PublicDescription": "" + }, + {, + "EventCode": "0x4d016", + "EventName": "PM_CMPLU_STALL_FXLONG", + "BriefDescription": "Completion stall due to a long latency fixed point instruction", + "PublicDescription": "" + }, + {, + "EventCode": "0x2d016", + "EventName": "PM_CMPLU_STALL_FXU", + "BriefDescription": "Completion stall due to FXU", + "PublicDescription": "" + }, + {, + "EventCode": "0x30036", + "EventName": "PM_CMPLU_STALL_HWSYNC", + "BriefDescription": "completion stall due to hwsync", + "PublicDescription": "" + }, + {, + "EventCode": "0x4d014", + "EventName": "PM_CMPLU_STALL_LOAD_FINISH", + "BriefDescription": "Completion stall due to a Load finish", + "PublicDescription": "" + }, + {, + "EventCode": "0x2c010", + "EventName": "PM_CMPLU_STALL_LSU", + "BriefDescription": "Completion stall by LSU instruction", + "PublicDescription": "" + }, + {, + "EventCode": "0x10036", + "EventName": "PM_CMPLU_STALL_LWSYNC", + "BriefDescription": "completion stall due to isync/lwsync", + "PublicDescription": "" + }, + {, + "EventCode": "0x30006", + "EventName": "PM_CMPLU_STALL_OTHER_CMPL", + "BriefDescription": "Instructions core completed while this tread was stalled", + "PublicDescription": "Instructions core completed while this thread was stalled" + }, + {, + "EventCode": "0x4c01c", + "EventName": "PM_CMPLU_STALL_ST_FWD", + "BriefDescription": "Completion stall due to store forward", + "PublicDescription": "" + }, + {, + "EventCode": "0x1001c", + "EventName": "PM_CMPLU_STALL_THRD", + "BriefDescription": "Completion Stalled due to thread conflict. Group ready to complete but it was another thread's turn", + "PublicDescription": "Completion stall due to thread conflict" + }, + {, + "EventCode": "0x1e", + "EventName": "PM_CYC", + "BriefDescription": "Cycles", + "PublicDescription": "" + }, + {, + "EventCode": "0x10006", + "EventName": "PM_DISP_HELD", + "BriefDescription": "Dispatch Held", + "PublicDescription": "" + }, + {, + "EventCode": "0x4003c", + "EventName": "PM_DISP_HELD_SYNC_HOLD", + "BriefDescription": "Dispatch held due to SYNC hold", + "PublicDescription": "" + }, + {, + "EventCode": "0x200f8", + "EventName": "PM_EXT_INT", + "BriefDescription": "external interrupt", + "PublicDescription": "" + }, + {, + "EventCode": "0x400f8", + "EventName": "PM_FLUSH", + "BriefDescription": "Flush (any type)", + "PublicDescription": "" + }, + {, + "EventCode": "0x30012", + "EventName": "PM_FLUSH_COMPLETION", + "BriefDescription": "Completion Flush", + "PublicDescription": "" + }, + {, + "EventCode": "0x3000c", + "EventName": "PM_FREQ_DOWN", + "BriefDescription": "Power Management: Below Threshold B", + "PublicDescription": "Frequency is being slewed down due to Power Management" + }, + {, + "EventCode": "0x4000c", + "EventName": "PM_FREQ_UP", + "BriefDescription": "Power Management: Above Threshold A", + "PublicDescription": "Frequency is being slewed up due to Power Management" + }, + {, + "EventCode": "0x2000a", + "EventName": "PM_HV_CYC", + "BriefDescription": "Cycles in which msr_hv is high. Note that this event does not take msr_pr into consideration", + "PublicDescription": "cycles in hypervisor mode" + }, + {, + "EventCode": "0x3405e", + "EventName": "PM_IFETCH_THROTTLE", + "BriefDescription": "Cycles in which Instruction fetch throttle was active", + "PublicDescription": "Cycles instruction fecth was throttled in IFU" + }, + {, + "EventCode": "0x10014", + "EventName": "PM_IOPS_CMPL", + "BriefDescription": "Internal Operations completed", + "PublicDescription": "IOPS Completed" + }, + {, + "EventCode": "0x3c058", + "EventName": "PM_LARX_FIN", + "BriefDescription": "Larx finished", + "PublicDescription": "" + }, + {, + "EventCode": "0x1002e", + "EventName": "PM_LD_CMPL", + "BriefDescription": "count of Loads completed", + "PublicDescription": "" + }, + {, + "EventCode": "0x10062", + "EventName": "PM_LD_L3MISS_PEND_CYC", + "BriefDescription": "Cycles L3 miss was pending for this thread", + "PublicDescription": "" + }, + {, + "EventCode": "0x30066", + "EventName": "PM_LSU_FIN", + "BriefDescription": "LSU Finished an instruction (up to 2 per cycle)", + "PublicDescription": "" + }, + {, + "EventCode": "0x2003e", + "EventName": "PM_LSU_LMQ_SRQ_EMPTY_CYC", + "BriefDescription": "LSU empty (lmq and srq empty)", + "PublicDescription": "" + }, + {, + "EventCode": "0x2e05c", + "EventName": "PM_LSU_REJECT_ERAT_MISS", + "BriefDescription": "LSU Reject due to ERAT (up to 4 per cycles)", + "PublicDescription": "" + }, + {, + "EventCode": "0x4e05c", + "EventName": "PM_LSU_REJECT_LHS", + "BriefDescription": "LSU Reject due to LHS (up to 4 per cycle)", + "PublicDescription": "" + }, + {, + "EventCode": "0x1e05c", + "EventName": "PM_LSU_REJECT_LMQ_FULL", + "BriefDescription": "LSU reject due to LMQ full ( 4 per cycle)", + "PublicDescription": "" + }, + {, + "EventCode": "0x1001a", + "EventName": "PM_LSU_SRQ_FULL_CYC", + "BriefDescription": "Storage Queue is full and is blocking dispatch", + "PublicDescription": "SRQ is Full" + }, + {, + "EventCode": "0x40014", + "EventName": "PM_PROBE_NOP_DISP", + "BriefDescription": "ProbeNops dispatched", + "PublicDescription": "" + }, + {, + "EventCode": "0x600f4", + "EventName": "PM_RUN_CYC", + "BriefDescription": "Run_cycles", + "PublicDescription": "" + }, + {, + "EventCode": "0x3006c", + "EventName": "PM_RUN_CYC_SMT2_MODE", + "BriefDescription": "Cycles run latch is set and core is in SMT2 mode", + "PublicDescription": "" + }, + {, + "EventCode": "0x2006c", + "EventName": "PM_RUN_CYC_SMT4_MODE", + "BriefDescription": "cycles this threads run latch is set and the core is in SMT4 mode", + "PublicDescription": "Cycles run latch is set and core is in SMT4 mode" + }, + {, + "EventCode": "0x1006c", + "EventName": "PM_RUN_CYC_ST_MODE", + "BriefDescription": "Cycles run latch is set and core is in ST mode", + "PublicDescription": "" + }, + {, + "EventCode": "0x500fa", + "EventName": "PM_RUN_INST_CMPL", + "BriefDescription": "Run_Instructions", + "PublicDescription": "" + }, + {, + "EventCode": "0x1e058", + "EventName": "PM_STCX_FAIL", + "BriefDescription": "stcx failed", + "PublicDescription": "" + }, + {, + "EventCode": "0x20016", + "EventName": "PM_ST_CMPL", + "BriefDescription": "Store completion count", + "PublicDescription": "" + }, + {, + "EventCode": "0x200f0", + "EventName": "PM_ST_FIN", + "BriefDescription": "Store Instructions Finished", + "PublicDescription": "Store Instructions Finished (store sent to nest)" + }, + {, + "EventCode": "0x20018", + "EventName": "PM_ST_FWD", + "BriefDescription": "Store forwards that finished", + "PublicDescription": "" + }, + {, + "EventCode": "0x10026", + "EventName": "PM_TABLEWALK_CYC", + "BriefDescription": "Cycles when a tablewalk (I or D) is active", + "PublicDescription": "Tablewalk Active" + }, + {, + "EventCode": "0x300f8", + "EventName": "PM_TB_BIT_TRANS", + "BriefDescription": "timebase event", + "PublicDescription": "" + }, + {, + "EventCode": "0x2000c", + "EventName": "PM_THRD_ALL_RUN_CYC", + "BriefDescription": "All Threads in Run_cycles (was both threads in run_cycles)", + "PublicDescription": "" + }, + {, + "EventCode": "0x30058", + "EventName": "PM_TLBIE_FIN", + "BriefDescription": "tlbie finished", + "PublicDescription": "" + }, + {, + "EventCode": "0x10060", + "EventName": "PM_TM_TRANS_RUN_CYC", + "BriefDescription": "run cycles in transactional state", + "PublicDescription": "" + }, + {, + "EventCode": "0x2e012", + "EventName": "PM_TM_TX_PASS_RUN_CYC", + "BriefDescription": "cycles spent in successful transactions", + "PublicDescription": "run cycles spent in successful transactions" + }, +] diff --git a/tools/perf/pmu-events/arch/powerpc/power8/pmc.json b/tools/perf/pmu-events/arch/powerpc/power8/pmc.json new file mode 100644 index 000000000000..583e4d937621 --- /dev/null +++ b/tools/perf/pmu-events/arch/powerpc/power8/pmc.json @@ -0,0 +1,140 @@ +[ + {, + "EventCode": "0x20010", + "EventName": "PM_PMC1_OVERFLOW", + "BriefDescription": "Overflow from counter 1", + "PublicDescription": "" + }, + {, + "EventCode": "0x30010", + "EventName": "PM_PMC2_OVERFLOW", + "BriefDescription": "Overflow from counter 2", + "PublicDescription": "" + }, + {, + "EventCode": "0x30020", + "EventName": "PM_PMC2_REWIND", + "BriefDescription": "PMC2 Rewind Event (did not match condition)", + "PublicDescription": "" + }, + {, + "EventCode": "0x10022", + "EventName": "PM_PMC2_SAVED", + "BriefDescription": "PMC2 Rewind Value saved", + "PublicDescription": "PMC2 Rewind Value saved (matched condition)" + }, + {, + "EventCode": "0x40010", + "EventName": "PM_PMC3_OVERFLOW", + "BriefDescription": "Overflow from counter 3", + "PublicDescription": "" + }, + {, + "EventCode": "0x10010", + "EventName": "PM_PMC4_OVERFLOW", + "BriefDescription": "Overflow from counter 4", + "PublicDescription": "" + }, + {, + "EventCode": "0x10020", + "EventName": "PM_PMC4_REWIND", + "BriefDescription": "PMC4 Rewind Event", + "PublicDescription": "PMC4 Rewind Event (did not match condition)" + }, + {, + "EventCode": "0x30022", + "EventName": "PM_PMC4_SAVED", + "BriefDescription": "PMC4 Rewind Value saved (matched condition)", + "PublicDescription": "" + }, + {, + "EventCode": "0x10024", + "EventName": "PM_PMC5_OVERFLOW", + "BriefDescription": "Overflow from counter 5", + "PublicDescription": "" + }, + {, + "EventCode": "0x30024", + "EventName": "PM_PMC6_OVERFLOW", + "BriefDescription": "Overflow from counter 6", + "PublicDescription": "" + }, + {, + "EventCode": "0x400f4", + "EventName": "PM_RUN_PURR", + "BriefDescription": "Run_PURR", + "PublicDescription": "" + }, + {, + "EventCode": "0x10008", + "EventName": "PM_RUN_SPURR", + "BriefDescription": "Run SPURR", + "PublicDescription": "" + }, + {, + "EventCode": "0x0", + "EventName": "PM_SUSPENDED", + "BriefDescription": "Counter OFF", + "PublicDescription": "" + }, + {, + "EventCode": "0x301ea", + "EventName": "PM_THRESH_EXC_1024", + "BriefDescription": "Threshold counter exceeded a value of 1024", + "PublicDescription": "" + }, + {, + "EventCode": "0x401ea", + "EventName": "PM_THRESH_EXC_128", + "BriefDescription": "Threshold counter exceeded a value of 128", + "PublicDescription": "" + }, + {, + "EventCode": "0x401ec", + "EventName": "PM_THRESH_EXC_2048", + "BriefDescription": "Threshold counter exceeded a value of 2048", + "PublicDescription": "" + }, + {, + "EventCode": "0x101e8", + "EventName": "PM_THRESH_EXC_256", + "BriefDescription": "Threshold counter exceed a count of 256", + "PublicDescription": "" + }, + {, + "EventCode": "0x201e6", + "EventName": "PM_THRESH_EXC_32", + "BriefDescription": "Threshold counter exceeded a value of 32", + "PublicDescription": "" + }, + {, + "EventCode": "0x101e6", + "EventName": "PM_THRESH_EXC_4096", + "BriefDescription": "Threshold counter exceed a count of 4096", + "PublicDescription": "" + }, + {, + "EventCode": "0x201e8", + "EventName": "PM_THRESH_EXC_512", + "BriefDescription": "Threshold counter exceeded a value of 512", + "PublicDescription": "" + }, + {, + "EventCode": "0x301e8", + "EventName": "PM_THRESH_EXC_64", + "BriefDescription": "IFU non-branch finished", + "PublicDescription": "Threshold counter exceeded a value of 64" + }, + {, + "EventCode": "0x101ec", + "EventName": "PM_THRESH_MET", + "BriefDescription": "threshold exceeded", + "PublicDescription": "" + }, + {, + "EventCode": "0x4016e", + "EventName": "PM_THRESH_NOT_MET", + "BriefDescription": "Threshold counter did not meet threshold", + "PublicDescription": "" + }, +] diff --git a/tools/perf/pmu-events/arch/powerpc/power8/translation.json b/tools/perf/pmu-events/arch/powerpc/power8/translation.json new file mode 100644 index 000000000000..e47a55459bc8 --- /dev/null +++ b/tools/perf/pmu-events/arch/powerpc/power8/translation.json @@ -0,0 +1,176 @@ +[ + {, + "EventCode": "0x4c054", + "EventName": "PM_DERAT_MISS_16G", + "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16G", + "PublicDescription": "" + }, + {, + "EventCode": "0x3c054", + "EventName": "PM_DERAT_MISS_16M", + "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16M", + "PublicDescription": "" + }, + {, + "EventCode": "0x1c056", + "EventName": "PM_DERAT_MISS_4K", + "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 4K", + "PublicDescription": "" + }, + {, + "EventCode": "0x2c054", + "EventName": "PM_DERAT_MISS_64K", + "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K", + "PublicDescription": "" + }, + {, + "EventCode": "0x4e048", + "EventName": "PM_DPTEG_FROM_DL2L3_MOD", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x3e048", + "EventName": "PM_DPTEG_FROM_DL2L3_SHR", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x1e042", + "EventName": "PM_DPTEG_FROM_L2", + "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x1e04e", + "EventName": "PM_DPTEG_FROM_L2MISS", + "BriefDescription": "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x2e040", + "EventName": "PM_DPTEG_FROM_L2_MEPF", + "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x1e040", + "EventName": "PM_DPTEG_FROM_L2_NO_CONFLICT", + "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x4e042", + "EventName": "PM_DPTEG_FROM_L3", + "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x3e042", + "EventName": "PM_DPTEG_FROM_L3_DISP_CONFLICT", + "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x2e042", + "EventName": "PM_DPTEG_FROM_L3_MEPF", + "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x1e044", + "EventName": "PM_DPTEG_FROM_L3_NO_CONFLICT", + "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x1e04c", + "EventName": "PM_DPTEG_FROM_LL4", + "BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x2e048", + "EventName": "PM_DPTEG_FROM_LMEM", + "BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x2e04c", + "EventName": "PM_DPTEG_FROM_MEMORY", + "BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x4e04a", + "EventName": "PM_DPTEG_FROM_OFF_CHIP_CACHE", + "BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x1e048", + "EventName": "PM_DPTEG_FROM_ON_CHIP_CACHE", + "BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x2e046", + "EventName": "PM_DPTEG_FROM_RL2L3_MOD", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x1e04a", + "EventName": "PM_DPTEG_FROM_RL2L3_SHR", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x2e04a", + "EventName": "PM_DPTEG_FROM_RL4", + "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x300fc", + "EventName": "PM_DTLB_MISS", + "BriefDescription": "Data PTEG reload", + "PublicDescription": "Data PTEG Reloaded (DTLB Miss)" + }, + {, + "EventCode": "0x1c058", + "EventName": "PM_DTLB_MISS_16G", + "BriefDescription": "Data TLB Miss page size 16G", + "PublicDescription": "" + }, + {, + "EventCode": "0x4c056", + "EventName": "PM_DTLB_MISS_16M", + "BriefDescription": "Data TLB Miss page size 16M", + "PublicDescription": "" + }, + {, + "EventCode": "0x2c056", + "EventName": "PM_DTLB_MISS_4K", + "BriefDescription": "Data TLB Miss page size 4k", + "PublicDescription": "" + }, + {, + "EventCode": "0x3c056", + "EventName": "PM_DTLB_MISS_64K", + "BriefDescription": "Data TLB Miss page size 64K", + "PublicDescription": "" + }, + {, + "EventCode": "0x200f6", + "EventName": "PM_LSU_DERAT_MISS", + "BriefDescription": "DERAT Reloaded due to a DERAT miss", + "PublicDescription": "DERAT Reloaded (Miss)" + }, + {, + "EventCode": "0x20066", + "EventName": "PM_TLB_MISS", + "BriefDescription": "TLB Miss (I + D)", + "PublicDescription": "" + }, +] diff --git a/tools/perf/pmu-events/arch/x86/bonnell/cache.json b/tools/perf/pmu-events/arch/x86/bonnell/cache.json new file mode 100644 index 000000000000..ffab90c5891c --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/bonnell/cache.json @@ -0,0 +1,746 @@ +[ + { + "EventCode": "0x21", + "Counter": "0,1", + "UMask": "0x40", + "EventName": "L2_ADS.SELF", + "SampleAfterValue": "200000", + "BriefDescription": "Cycles L2 address bus is in use." + }, + { + "EventCode": "0x22", + "Counter": "0,1", + "UMask": "0x40", + "EventName": "L2_DBUS_BUSY.SELF", + "SampleAfterValue": "200000", + "BriefDescription": "Cycles the L2 cache data bus is busy." + }, + { + "EventCode": "0x23", + "Counter": "0,1", + "UMask": "0x40", + "EventName": "L2_DBUS_BUSY_RD.SELF", + "SampleAfterValue": "200000", + "BriefDescription": "Cycles the L2 transfers data to the core." + }, + { + "EventCode": "0x24", + "Counter": "0,1", + "UMask": "0x70", + "EventName": "L2_LINES_IN.SELF.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cache misses." + }, + { + "EventCode": "0x24", + "Counter": "0,1", + "UMask": "0x40", + "EventName": "L2_LINES_IN.SELF.DEMAND", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cache misses." + }, + { + "EventCode": "0x24", + "Counter": "0,1", + "UMask": "0x50", + "EventName": "L2_LINES_IN.SELF.PREFETCH", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cache misses." + }, + { + "EventCode": "0x25", + "Counter": "0,1", + "UMask": "0x40", + "EventName": "L2_M_LINES_IN.SELF", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cache line modifications." + }, + { + "EventCode": "0x26", + "Counter": "0,1", + "UMask": "0x70", + "EventName": "L2_LINES_OUT.SELF.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cache lines evicted." + }, + { + "EventCode": "0x26", + "Counter": "0,1", + "UMask": "0x40", + "EventName": "L2_LINES_OUT.SELF.DEMAND", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cache lines evicted." + }, + { + "EventCode": "0x26", + "Counter": "0,1", + "UMask": "0x50", + "EventName": "L2_LINES_OUT.SELF.PREFETCH", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cache lines evicted." + }, + { + "EventCode": "0x27", + "Counter": "0,1", + "UMask": "0x70", + "EventName": "L2_M_LINES_OUT.SELF.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "Modified lines evicted from the L2 cache" + }, + { + "EventCode": "0x27", + "Counter": "0,1", + "UMask": "0x40", + "EventName": "L2_M_LINES_OUT.SELF.DEMAND", + "SampleAfterValue": "200000", + "BriefDescription": "Modified lines evicted from the L2 cache" + }, + { + "EventCode": "0x27", + "Counter": "0,1", + "UMask": "0x50", + "EventName": "L2_M_LINES_OUT.SELF.PREFETCH", + "SampleAfterValue": "200000", + "BriefDescription": "Modified lines evicted from the L2 cache" + }, + { + "EventCode": "0x28", + "Counter": "0,1", + "UMask": "0x44", + "EventName": "L2_IFETCH.SELF.E_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cacheable instruction fetch requests" + }, + { + "EventCode": "0x28", + "Counter": "0,1", + "UMask": "0x41", + "EventName": "L2_IFETCH.SELF.I_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cacheable instruction fetch requests" + }, + { + "EventCode": "0x28", + "Counter": "0,1", + "UMask": "0x48", + "EventName": "L2_IFETCH.SELF.M_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cacheable instruction fetch requests" + }, + { + "EventCode": "0x28", + "Counter": "0,1", + "UMask": "0x42", + "EventName": "L2_IFETCH.SELF.S_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cacheable instruction fetch requests" + }, + { + "EventCode": "0x28", + "Counter": "0,1", + "UMask": "0x4f", + "EventName": "L2_IFETCH.SELF.MESI", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cacheable instruction fetch requests" + }, + { + "EventCode": "0x29", + "Counter": "0,1", + "UMask": "0x74", + "EventName": "L2_LD.SELF.ANY.E_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cache reads" + }, + { + "EventCode": "0x29", + "Counter": "0,1", + "UMask": "0x71", + "EventName": "L2_LD.SELF.ANY.I_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cache reads" + }, + { + "EventCode": "0x29", + "Counter": "0,1", + "UMask": "0x78", + "EventName": "L2_LD.SELF.ANY.M_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cache reads" + }, + { + "EventCode": "0x29", + "Counter": "0,1", + "UMask": "0x72", + "EventName": "L2_LD.SELF.ANY.S_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cache reads" + }, + { + "EventCode": "0x29", + "Counter": "0,1", + "UMask": "0x7f", + "EventName": "L2_LD.SELF.ANY.MESI", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cache reads" + }, + { + "EventCode": "0x29", + "Counter": "0,1", + "UMask": "0x44", + "EventName": "L2_LD.SELF.DEMAND.E_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cache reads" + }, + { + "EventCode": "0x29", + "Counter": "0,1", + "UMask": "0x41", + "EventName": "L2_LD.SELF.DEMAND.I_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cache reads" + }, + { + "EventCode": "0x29", + "Counter": "0,1", + "UMask": "0x48", + "EventName": "L2_LD.SELF.DEMAND.M_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cache reads" + }, + { + "EventCode": "0x29", + "Counter": "0,1", + "UMask": "0x42", + "EventName": "L2_LD.SELF.DEMAND.S_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cache reads" + }, + { + "EventCode": "0x29", + "Counter": "0,1", + "UMask": "0x4f", + "EventName": "L2_LD.SELF.DEMAND.MESI", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cache reads" + }, + { + "EventCode": "0x29", + "Counter": "0,1", + "UMask": "0x54", + "EventName": "L2_LD.SELF.PREFETCH.E_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cache reads" + }, + { + "EventCode": "0x29", + "Counter": "0,1", + "UMask": "0x51", + "EventName": "L2_LD.SELF.PREFETCH.I_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cache reads" + }, + { + "EventCode": "0x29", + "Counter": "0,1", + "UMask": "0x58", + "EventName": "L2_LD.SELF.PREFETCH.M_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cache reads" + }, + { + "EventCode": "0x29", + "Counter": "0,1", + "UMask": "0x52", + "EventName": "L2_LD.SELF.PREFETCH.S_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cache reads" + }, + { + "EventCode": "0x29", + "Counter": "0,1", + "UMask": "0x5f", + "EventName": "L2_LD.SELF.PREFETCH.MESI", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cache reads" + }, + { + "EventCode": "0x2A", + "Counter": "0,1", + "UMask": "0x44", + "EventName": "L2_ST.SELF.E_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 store requests" + }, + { + "EventCode": "0x2A", + "Counter": "0,1", + "UMask": "0x41", + "EventName": "L2_ST.SELF.I_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 store requests" + }, + { + "EventCode": "0x2A", + "Counter": "0,1", + "UMask": "0x48", + "EventName": "L2_ST.SELF.M_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 store requests" + }, + { + "EventCode": "0x2A", + "Counter": "0,1", + "UMask": "0x42", + "EventName": "L2_ST.SELF.S_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 store requests" + }, + { + "EventCode": "0x2A", + "Counter": "0,1", + "UMask": "0x4f", + "EventName": "L2_ST.SELF.MESI", + "SampleAfterValue": "200000", + "BriefDescription": "L2 store requests" + }, + { + "EventCode": "0x2B", + "Counter": "0,1", + "UMask": "0x44", + "EventName": "L2_LOCK.SELF.E_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 locked accesses" + }, + { + "EventCode": "0x2B", + "Counter": "0,1", + "UMask": "0x41", + "EventName": "L2_LOCK.SELF.I_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 locked accesses" + }, + { + "EventCode": "0x2B", + "Counter": "0,1", + "UMask": "0x48", + "EventName": "L2_LOCK.SELF.M_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 locked accesses" + }, + { + "EventCode": "0x2B", + "Counter": "0,1", + "UMask": "0x42", + "EventName": "L2_LOCK.SELF.S_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 locked accesses" + }, + { + "EventCode": "0x2B", + "Counter": "0,1", + "UMask": "0x4f", + "EventName": "L2_LOCK.SELF.MESI", + "SampleAfterValue": "200000", + "BriefDescription": "L2 locked accesses" + }, + { + "EventCode": "0x2C", + "Counter": "0,1", + "UMask": "0x44", + "EventName": "L2_DATA_RQSTS.SELF.E_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "All data requests from the L1 data cache" + }, + { + "EventCode": "0x2C", + "Counter": "0,1", + "UMask": "0x41", + "EventName": "L2_DATA_RQSTS.SELF.I_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "All data requests from the L1 data cache" + }, + { + "EventCode": "0x2C", + "Counter": "0,1", + "UMask": "0x48", + "EventName": "L2_DATA_RQSTS.SELF.M_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "All data requests from the L1 data cache" + }, + { + "EventCode": "0x2C", + "Counter": "0,1", + "UMask": "0x42", + "EventName": "L2_DATA_RQSTS.SELF.S_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "All data requests from the L1 data cache" + }, + { + "EventCode": "0x2C", + "Counter": "0,1", + "UMask": "0x4f", + "EventName": "L2_DATA_RQSTS.SELF.MESI", + "SampleAfterValue": "200000", + "BriefDescription": "All data requests from the L1 data cache" + }, + { + "EventCode": "0x2D", + "Counter": "0,1", + "UMask": "0x44", + "EventName": "L2_LD_IFETCH.SELF.E_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "All read requests from L1 instruction and data caches" + }, + { + "EventCode": "0x2D", + "Counter": "0,1", + "UMask": "0x41", + "EventName": "L2_LD_IFETCH.SELF.I_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "All read requests from L1 instruction and data caches" + }, + { + "EventCode": "0x2D", + "Counter": "0,1", + "UMask": "0x48", + "EventName": "L2_LD_IFETCH.SELF.M_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "All read requests from L1 instruction and data caches" + }, + { + "EventCode": "0x2D", + "Counter": "0,1", + "UMask": "0x42", + "EventName": "L2_LD_IFETCH.SELF.S_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "All read requests from L1 instruction and data caches" + }, + { + "EventCode": "0x2D", + "Counter": "0,1", + "UMask": "0x4f", + "EventName": "L2_LD_IFETCH.SELF.MESI", + "SampleAfterValue": "200000", + "BriefDescription": "All read requests from L1 instruction and data caches" + }, + { + "EventCode": "0x2E", + "Counter": "0,1", + "UMask": "0x74", + "EventName": "L2_RQSTS.SELF.ANY.E_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cache requests" + }, + { + "EventCode": "0x2E", + "Counter": "0,1", + "UMask": "0x71", + "EventName": "L2_RQSTS.SELF.ANY.I_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cache requests" + }, + { + "EventCode": "0x2E", + "Counter": "0,1", + "UMask": "0x78", + "EventName": "L2_RQSTS.SELF.ANY.M_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cache requests" + }, + { + "EventCode": "0x2E", + "Counter": "0,1", + "UMask": "0x72", + "EventName": "L2_RQSTS.SELF.ANY.S_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cache requests" + }, + { + "EventCode": "0x2E", + "Counter": "0,1", + "UMask": "0x7f", + "EventName": "L2_RQSTS.SELF.ANY.MESI", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cache requests" + }, + { + "EventCode": "0x2E", + "Counter": "0,1", + "UMask": "0x44", + "EventName": "L2_RQSTS.SELF.DEMAND.E_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cache requests" + }, + { + "EventCode": "0x2E", + "Counter": "0,1", + "UMask": "0x48", + "EventName": "L2_RQSTS.SELF.DEMAND.M_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cache requests" + }, + { + "EventCode": "0x2E", + "Counter": "0,1", + "UMask": "0x42", + "EventName": "L2_RQSTS.SELF.DEMAND.S_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cache requests" + }, + { + "EventCode": "0x2E", + "Counter": "0,1", + "UMask": "0x54", + "EventName": "L2_RQSTS.SELF.PREFETCH.E_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cache requests" + }, + { + "EventCode": "0x2E", + "Counter": "0,1", + "UMask": "0x51", + "EventName": "L2_RQSTS.SELF.PREFETCH.I_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cache requests" + }, + { + "EventCode": "0x2E", + "Counter": "0,1", + "UMask": "0x58", + "EventName": "L2_RQSTS.SELF.PREFETCH.M_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cache requests" + }, + { + "EventCode": "0x2E", + "Counter": "0,1", + "UMask": "0x52", + "EventName": "L2_RQSTS.SELF.PREFETCH.S_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cache requests" + }, + { + "EventCode": "0x2E", + "Counter": "0,1", + "UMask": "0x5f", + "EventName": "L2_RQSTS.SELF.PREFETCH.MESI", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cache requests" + }, + { + "EventCode": "0x2E", + "Counter": "0,1", + "UMask": "0x41", + "EventName": "L2_RQSTS.SELF.DEMAND.I_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cache demand requests from this core that missed the L2" + }, + { + "EventCode": "0x2E", + "Counter": "0,1", + "UMask": "0x4f", + "EventName": "L2_RQSTS.SELF.DEMAND.MESI", + "SampleAfterValue": "200000", + "BriefDescription": "L2 cache demand requests from this core" + }, + { + "EventCode": "0x30", + "Counter": "0,1", + "UMask": "0x74", + "EventName": "L2_REJECT_BUSQ.SELF.ANY.E_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "Rejected L2 cache requests" + }, + { + "EventCode": "0x30", + "Counter": "0,1", + "UMask": "0x71", + "EventName": "L2_REJECT_BUSQ.SELF.ANY.I_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "Rejected L2 cache requests" + }, + { + "EventCode": "0x30", + "Counter": "0,1", + "UMask": "0x78", + "EventName": "L2_REJECT_BUSQ.SELF.ANY.M_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "Rejected L2 cache requests" + }, + { + "EventCode": "0x30", + "Counter": "0,1", + "UMask": "0x72", + "EventName": "L2_REJECT_BUSQ.SELF.ANY.S_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "Rejected L2 cache requests" + }, + { + "EventCode": "0x30", + "Counter": "0,1", + "UMask": "0x7f", + "EventName": "L2_REJECT_BUSQ.SELF.ANY.MESI", + "SampleAfterValue": "200000", + "BriefDescription": "Rejected L2 cache requests" + }, + { + "EventCode": "0x30", + "Counter": "0,1", + "UMask": "0x44", + "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.E_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "Rejected L2 cache requests" + }, + { + "EventCode": "0x30", + "Counter": "0,1", + "UMask": "0x41", + "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.I_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "Rejected L2 cache requests" + }, + { + "EventCode": "0x30", + "Counter": "0,1", + "UMask": "0x48", + "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.M_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "Rejected L2 cache requests" + }, + { + "EventCode": "0x30", + "Counter": "0,1", + "UMask": "0x42", + "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.S_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "Rejected L2 cache requests" + }, + { + "EventCode": "0x30", + "Counter": "0,1", + "UMask": "0x4f", + "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.MESI", + "SampleAfterValue": "200000", + "BriefDescription": "Rejected L2 cache requests" + }, + { + "EventCode": "0x30", + "Counter": "0,1", + "UMask": "0x54", + "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.E_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "Rejected L2 cache requests" + }, + { + "EventCode": "0x30", + "Counter": "0,1", + "UMask": "0x51", + "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.I_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "Rejected L2 cache requests" + }, + { + "EventCode": "0x30", + "Counter": "0,1", + "UMask": "0x58", + "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.M_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "Rejected L2 cache requests" + }, + { + "EventCode": "0x30", + "Counter": "0,1", + "UMask": "0x52", + "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.S_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "Rejected L2 cache requests" + }, + { + "EventCode": "0x30", + "Counter": "0,1", + "UMask": "0x5f", + "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.MESI", + "SampleAfterValue": "200000", + "BriefDescription": "Rejected L2 cache requests" + }, + { + "EventCode": "0x32", + "Counter": "0,1", + "UMask": "0x40", + "EventName": "L2_NO_REQ.SELF", + "SampleAfterValue": "200000", + "BriefDescription": "Cycles no L2 cache requests are pending" + }, + { + "EventCode": "0x40", + "Counter": "0,1", + "UMask": "0xa1", + "EventName": "L1D_CACHE.LD", + "SampleAfterValue": "2000000", + "BriefDescription": "L1 Cacheable Data Reads" + }, + { + "EventCode": "0x40", + "Counter": "0,1", + "UMask": "0xa2", + "EventName": "L1D_CACHE.ST", + "SampleAfterValue": "2000000", + "BriefDescription": "L1 Cacheable Data Writes" + }, + { + "EventCode": "0x40", + "Counter": "0,1", + "UMask": "0x83", + "EventName": "L1D_CACHE.ALL_REF", + "SampleAfterValue": "2000000", + "BriefDescription": "L1 Data reads and writes" + }, + { + "EventCode": "0x40", + "Counter": "0,1", + "UMask": "0xa3", + "EventName": "L1D_CACHE.ALL_CACHE_REF", + "SampleAfterValue": "2000000", + "BriefDescription": "L1 Data Cacheable reads and writes" + }, + { + "EventCode": "0x40", + "Counter": "0,1", + "UMask": "0x8", + "EventName": "L1D_CACHE.REPL", + "SampleAfterValue": "200000", + "BriefDescription": "L1 Data line replacements" + }, + { + "EventCode": "0x40", + "Counter": "0,1", + "UMask": "0x48", + "EventName": "L1D_CACHE.REPLM", + "SampleAfterValue": "200000", + "BriefDescription": "Modified cache lines allocated in the L1 data cache" + }, + { + "EventCode": "0x40", + "Counter": "0,1", + "UMask": "0x10", + "EventName": "L1D_CACHE.EVICT", + "SampleAfterValue": "200000", + "BriefDescription": "Modified cache lines evicted from the L1 data cache" + }, + { + "EventCode": "0xCB", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "MEM_LOAD_RETIRED.L2_HIT", + "SampleAfterValue": "200000", + "BriefDescription": "Retired loads that hit the L2 cache (precise event)." + }, + { + "EventCode": "0xCB", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "MEM_LOAD_RETIRED.L2_MISS", + "SampleAfterValue": "10000", + "BriefDescription": "Retired loads that miss the L2 cache" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/bonnell/floating-point.json b/tools/perf/pmu-events/arch/x86/bonnell/floating-point.json new file mode 100644 index 000000000000..f0e090cdb9f0 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/bonnell/floating-point.json @@ -0,0 +1,261 @@ +[ + { + "EventCode": "0x10", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "X87_COMP_OPS_EXE.ANY.S", + "SampleAfterValue": "2000000", + "BriefDescription": "Floating point computational micro-ops executed." + }, + { + "PEBS": "2", + "EventCode": "0x10", + "Counter": "0,1", + "UMask": "0x81", + "EventName": "X87_COMP_OPS_EXE.ANY.AR", + "SampleAfterValue": "2000000", + "BriefDescription": "Floating point computational micro-ops retired." + }, + { + "EventCode": "0x10", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "X87_COMP_OPS_EXE.FXCH.S", + "SampleAfterValue": "2000000", + "BriefDescription": "FXCH uops executed." + }, + { + "PEBS": "2", + "EventCode": "0x10", + "Counter": "0,1", + "UMask": "0x82", + "EventName": "X87_COMP_OPS_EXE.FXCH.AR", + "SampleAfterValue": "2000000", + "BriefDescription": "FXCH uops retired." + }, + { + "EventCode": "0x11", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "FP_ASSIST.S", + "SampleAfterValue": "10000", + "BriefDescription": "Floating point assists." + }, + { + "EventCode": "0x11", + "Counter": "0,1", + "UMask": "0x81", + "EventName": "FP_ASSIST.AR", + "SampleAfterValue": "10000", + "BriefDescription": "Floating point assists for retired operations." + }, + { + "EventCode": "0xB0", + "Counter": "0,1", + "UMask": "0x0", + "EventName": "SIMD_UOPS_EXEC.S", + "SampleAfterValue": "2000000", + "BriefDescription": "SIMD micro-ops executed (excluding stores)." + }, + { + "PEBS": "2", + "EventCode": "0xB0", + "Counter": "0,1", + "UMask": "0x80", + "EventName": "SIMD_UOPS_EXEC.AR", + "SampleAfterValue": "2000000", + "BriefDescription": "SIMD micro-ops retired (excluding stores)." + }, + { + "EventCode": "0xB1", + "Counter": "0,1", + "UMask": "0x0", + "EventName": "SIMD_SAT_UOP_EXEC.S", + "SampleAfterValue": "2000000", + "BriefDescription": "SIMD saturated arithmetic micro-ops executed." + }, + { + "EventCode": "0xB1", + "Counter": "0,1", + "UMask": "0x80", + "EventName": "SIMD_SAT_UOP_EXEC.AR", + "SampleAfterValue": "2000000", + "BriefDescription": "SIMD saturated arithmetic micro-ops retired." + }, + { + "EventCode": "0xB3", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "SIMD_UOP_TYPE_EXEC.MUL.S", + "SampleAfterValue": "2000000", + "BriefDescription": "SIMD packed multiply micro-ops executed" + }, + { + "EventCode": "0xB3", + "Counter": "0,1", + "UMask": "0x81", + "EventName": "SIMD_UOP_TYPE_EXEC.MUL.AR", + "SampleAfterValue": "2000000", + "BriefDescription": "SIMD packed multiply micro-ops retired" + }, + { + "EventCode": "0xB3", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.S", + "SampleAfterValue": "2000000", + "BriefDescription": "SIMD packed shift micro-ops executed" + }, + { + "EventCode": "0xB3", + "Counter": "0,1", + "UMask": "0x82", + "EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.AR", + "SampleAfterValue": "2000000", + "BriefDescription": "SIMD packed shift micro-ops retired" + }, + { + "EventCode": "0xB3", + "Counter": "0,1", + "UMask": "0x4", + "EventName": "SIMD_UOP_TYPE_EXEC.PACK.S", + "SampleAfterValue": "2000000", + "BriefDescription": "SIMD packed micro-ops executed" + }, + { + "EventCode": "0xB3", + "Counter": "0,1", + "UMask": "0x84", + "EventName": "SIMD_UOP_TYPE_EXEC.PACK.AR", + "SampleAfterValue": "2000000", + "BriefDescription": "SIMD packed micro-ops retired" + }, + { + "EventCode": "0xB3", + "Counter": "0,1", + "UMask": "0x8", + "EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.S", + "SampleAfterValue": "2000000", + "BriefDescription": "SIMD unpacked micro-ops executed" + }, + { + "EventCode": "0xB3", + "Counter": "0,1", + "UMask": "0x88", + "EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.AR", + "SampleAfterValue": "2000000", + "BriefDescription": "SIMD unpacked micro-ops retired" + }, + { + "EventCode": "0xB3", + "Counter": "0,1", + "UMask": "0x10", + "EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.S", + "SampleAfterValue": "2000000", + "BriefDescription": "SIMD packed logical micro-ops executed" + }, + { + "EventCode": "0xB3", + "Counter": "0,1", + "UMask": "0x90", + "EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.AR", + "SampleAfterValue": "2000000", + "BriefDescription": "SIMD packed logical micro-ops retired" + }, + { + "EventCode": "0xB3", + "Counter": "0,1", + "UMask": "0x20", + "EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.S", + "SampleAfterValue": "2000000", + "BriefDescription": "SIMD packed arithmetic micro-ops executed" + }, + { + "EventCode": "0xB3", + "Counter": "0,1", + "UMask": "0xa0", + "EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.AR", + "SampleAfterValue": "2000000", + "BriefDescription": "SIMD packed arithmetic micro-ops retired" + }, + { + "EventCode": "0xC7", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "SIMD_INST_RETIRED.PACKED_SINGLE", + "SampleAfterValue": "2000000", + "BriefDescription": "Retired Streaming SIMD Extensions (SSE) packed-single instructions." + }, + { + "EventCode": "0xC7", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "SIMD_INST_RETIRED.SCALAR_SINGLE", + "SampleAfterValue": "2000000", + "BriefDescription": "Retired Streaming SIMD Extensions (SSE) scalar-single instructions." + }, + { + "EventCode": "0xC7", + "Counter": "0,1", + "UMask": "0x8", + "EventName": "SIMD_INST_RETIRED.SCALAR_DOUBLE", + "SampleAfterValue": "2000000", + "BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions." + }, + { + "EventCode": "0xC7", + "Counter": "0,1", + "UMask": "0x10", + "EventName": "SIMD_INST_RETIRED.VECTOR", + "SampleAfterValue": "2000000", + "BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) vector instructions." + }, + { + "EventCode": "0xCA", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "SIMD_COMP_INST_RETIRED.PACKED_SINGLE", + "SampleAfterValue": "2000000", + "BriefDescription": "Retired computational Streaming SIMD Extensions (SSE) packed-single instructions." + }, + { + "EventCode": "0xCA", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "SIMD_COMP_INST_RETIRED.SCALAR_SINGLE", + "SampleAfterValue": "2000000", + "BriefDescription": "Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions." + }, + { + "EventCode": "0xCA", + "Counter": "0,1", + "UMask": "0x8", + "EventName": "SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE", + "SampleAfterValue": "2000000", + "BriefDescription": "Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions." + }, + { + "EventCode": "0xCD", + "Counter": "0,1", + "UMask": "0x0", + "EventName": "SIMD_ASSIST", + "SampleAfterValue": "100000", + "BriefDescription": "SIMD assists invoked." + }, + { + "EventCode": "0xCE", + "Counter": "0,1", + "UMask": "0x0", + "EventName": "SIMD_INSTR_RETIRED", + "SampleAfterValue": "2000000", + "BriefDescription": "SIMD Instructions retired." + }, + { + "EventCode": "0xCF", + "Counter": "0,1", + "UMask": "0x0", + "EventName": "SIMD_SAT_INSTR_RETIRED", + "SampleAfterValue": "2000000", + "BriefDescription": "Saturated arithmetic instructions retired." + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/bonnell/frontend.json b/tools/perf/pmu-events/arch/x86/bonnell/frontend.json new file mode 100644 index 000000000000..935b7dcf067d --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/bonnell/frontend.json @@ -0,0 +1,83 @@ +[ + { + "EventCode": "0x80", + "Counter": "0,1", + "UMask": "0x3", + "EventName": "ICACHE.ACCESSES", + "SampleAfterValue": "200000", + "BriefDescription": "Instruction fetches." + }, + { + "EventCode": "0x80", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "ICACHE.HIT", + "SampleAfterValue": "200000", + "BriefDescription": "Icache hit" + }, + { + "EventCode": "0x80", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "ICACHE.MISSES", + "SampleAfterValue": "200000", + "BriefDescription": "Icache miss" + }, + { + "EventCode": "0x86", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles during which instruction fetches are stalled." + }, + { + "EventCode": "0x87", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "DECODE_STALL.PFB_EMPTY", + "SampleAfterValue": "2000000", + "BriefDescription": "Decode stall due to PFB empty" + }, + { + "EventCode": "0x87", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "DECODE_STALL.IQ_FULL", + "SampleAfterValue": "2000000", + "BriefDescription": "Decode stall due to IQ full" + }, + { + "EventCode": "0xAA", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "MACRO_INSTS.NON_CISC_DECODED", + "SampleAfterValue": "2000000", + "BriefDescription": "Non-CISC nacro instructions decoded" + }, + { + "EventCode": "0xAA", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "MACRO_INSTS.CISC_DECODED", + "SampleAfterValue": "2000000", + "BriefDescription": "CISC macro instructions decoded" + }, + { + "EventCode": "0xAA", + "Counter": "0,1", + "UMask": "0x3", + "EventName": "MACRO_INSTS.ALL_DECODED", + "SampleAfterValue": "2000000", + "BriefDescription": "All Instructions decoded" + }, + { + "EventCode": "0xA9", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "UOPS.MS_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ. ", + "CounterMask": "1" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/bonnell/memory.json b/tools/perf/pmu-events/arch/x86/bonnell/memory.json new file mode 100644 index 000000000000..3ae843b20c8a --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/bonnell/memory.json @@ -0,0 +1,154 @@ +[ + { + "EventCode": "0x5", + "Counter": "0,1", + "UMask": "0xf", + "EventName": "MISALIGN_MEM_REF.SPLIT", + "SampleAfterValue": "200000", + "BriefDescription": "Memory references that cross an 8-byte boundary." + }, + { + "EventCode": "0x5", + "Counter": "0,1", + "UMask": "0x9", + "EventName": "MISALIGN_MEM_REF.LD_SPLIT", + "SampleAfterValue": "200000", + "BriefDescription": "Load splits" + }, + { + "EventCode": "0x5", + "Counter": "0,1", + "UMask": "0xa", + "EventName": "MISALIGN_MEM_REF.ST_SPLIT", + "SampleAfterValue": "200000", + "BriefDescription": "Store splits" + }, + { + "EventCode": "0x5", + "Counter": "0,1", + "UMask": "0x8f", + "EventName": "MISALIGN_MEM_REF.SPLIT.AR", + "SampleAfterValue": "200000", + "BriefDescription": "Memory references that cross an 8-byte boundary (At Retirement)" + }, + { + "EventCode": "0x5", + "Counter": "0,1", + "UMask": "0x89", + "EventName": "MISALIGN_MEM_REF.LD_SPLIT.AR", + "SampleAfterValue": "200000", + "BriefDescription": "Load splits (At Retirement)" + }, + { + "EventCode": "0x5", + "Counter": "0,1", + "UMask": "0x8a", + "EventName": "MISALIGN_MEM_REF.ST_SPLIT.AR", + "SampleAfterValue": "200000", + "BriefDescription": "Store splits (Ar Retirement)" + }, + { + "EventCode": "0x5", + "Counter": "0,1", + "UMask": "0x8c", + "EventName": "MISALIGN_MEM_REF.RMW_SPLIT", + "SampleAfterValue": "200000", + "BriefDescription": "ld-op-st splits" + }, + { + "EventCode": "0x5", + "Counter": "0,1", + "UMask": "0x97", + "EventName": "MISALIGN_MEM_REF.BUBBLE", + "SampleAfterValue": "200000", + "BriefDescription": "Nonzero segbase 1 bubble" + }, + { + "EventCode": "0x5", + "Counter": "0,1", + "UMask": "0x91", + "EventName": "MISALIGN_MEM_REF.LD_BUBBLE", + "SampleAfterValue": "200000", + "BriefDescription": "Nonzero segbase load 1 bubble" + }, + { + "EventCode": "0x5", + "Counter": "0,1", + "UMask": "0x92", + "EventName": "MISALIGN_MEM_REF.ST_BUBBLE", + "SampleAfterValue": "200000", + "BriefDescription": "Nonzero segbase store 1 bubble" + }, + { + "EventCode": "0x5", + "Counter": "0,1", + "UMask": "0x94", + "EventName": "MISALIGN_MEM_REF.RMW_BUBBLE", + "SampleAfterValue": "200000", + "BriefDescription": "Nonzero segbase ld-op-st 1 bubble" + }, + { + "EventCode": "0x7", + "Counter": "0,1", + "UMask": "0x81", + "EventName": "PREFETCH.PREFETCHT0", + "SampleAfterValue": "200000", + "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed." + }, + { + "EventCode": "0x7", + "Counter": "0,1", + "UMask": "0x82", + "EventName": "PREFETCH.PREFETCHT1", + "SampleAfterValue": "200000", + "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed." + }, + { + "EventCode": "0x7", + "Counter": "0,1", + "UMask": "0x84", + "EventName": "PREFETCH.PREFETCHT2", + "SampleAfterValue": "200000", + "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed." + }, + { + "EventCode": "0x7", + "Counter": "0,1", + "UMask": "0x86", + "EventName": "PREFETCH.SW_L2", + "SampleAfterValue": "200000", + "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed" + }, + { + "EventCode": "0x7", + "Counter": "0,1", + "UMask": "0x88", + "EventName": "PREFETCH.PREFETCHNTA", + "SampleAfterValue": "200000", + "BriefDescription": "Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed" + }, + { + "EventCode": "0x7", + "Counter": "0,1", + "UMask": "0x10", + "EventName": "PREFETCH.HW_PREFETCH", + "SampleAfterValue": "2000000", + "BriefDescription": "L1 hardware prefetch request" + }, + { + "EventCode": "0x7", + "Counter": "0,1", + "UMask": "0xf", + "EventName": "PREFETCH.SOFTWARE_PREFETCH", + "SampleAfterValue": "200000", + "BriefDescription": "Any Software prefetch" + }, + { + "EventCode": "0x7", + "Counter": "0,1", + "UMask": "0x8f", + "EventName": "PREFETCH.SOFTWARE_PREFETCH.AR", + "SampleAfterValue": "200000", + "BriefDescription": "Any Software prefetch" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/bonnell/other.json b/tools/perf/pmu-events/arch/x86/bonnell/other.json new file mode 100644 index 000000000000..4bc1c582d1cd --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/bonnell/other.json @@ -0,0 +1,450 @@ +[ + { + "EventCode": "0x6", + "Counter": "0,1", + "UMask": "0x80", + "EventName": "SEGMENT_REG_LOADS.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "Number of segment register loads." + }, + { + "EventCode": "0x9", + "Counter": "0,1", + "UMask": "0x20", + "EventName": "DISPATCH_BLOCKED.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "Memory cluster signals to block micro-op dispatch for any reason" + }, + { + "EventCode": "0x3A", + "Counter": "0,1", + "UMask": "0x0", + "EventName": "EIST_TRANS", + "SampleAfterValue": "200000", + "BriefDescription": "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions" + }, + { + "EventCode": "0x3B", + "Counter": "0,1", + "UMask": "0xc0", + "EventName": "THERMAL_TRIP", + "SampleAfterValue": "200000", + "BriefDescription": "Number of thermal trips" + }, + { + "EventCode": "0x60", + "Counter": "0,1", + "UMask": "0xe0", + "EventName": "BUS_REQUEST_OUTSTANDING.ALL_AGENTS", + "SampleAfterValue": "200000", + "BriefDescription": "Outstanding cacheable data read bus requests duration." + }, + { + "EventCode": "0x60", + "Counter": "0,1", + "UMask": "0x40", + "EventName": "BUS_REQUEST_OUTSTANDING.SELF", + "SampleAfterValue": "200000", + "BriefDescription": "Outstanding cacheable data read bus requests duration." + }, + { + "EventCode": "0x61", + "Counter": "0,1", + "UMask": "0x20", + "EventName": "BUS_BNR_DRV.ALL_AGENTS", + "SampleAfterValue": "200000", + "BriefDescription": "Number of Bus Not Ready signals asserted." + }, + { + "EventCode": "0x61", + "Counter": "0,1", + "UMask": "0x0", + "EventName": "BUS_BNR_DRV.THIS_AGENT", + "SampleAfterValue": "200000", + "BriefDescription": "Number of Bus Not Ready signals asserted." + }, + { + "EventCode": "0x62", + "Counter": "0,1", + "UMask": "0x20", + "EventName": "BUS_DRDY_CLOCKS.ALL_AGENTS", + "SampleAfterValue": "200000", + "BriefDescription": "Bus cycles when data is sent on the bus." + }, + { + "EventCode": "0x62", + "Counter": "0,1", + "UMask": "0x0", + "EventName": "BUS_DRDY_CLOCKS.THIS_AGENT", + "SampleAfterValue": "200000", + "BriefDescription": "Bus cycles when data is sent on the bus." + }, + { + "EventCode": "0x63", + "Counter": "0,1", + "UMask": "0xe0", + "EventName": "BUS_LOCK_CLOCKS.ALL_AGENTS", + "SampleAfterValue": "200000", + "BriefDescription": "Bus cycles when a LOCK signal is asserted." + }, + { + "EventCode": "0x63", + "Counter": "0,1", + "UMask": "0x40", + "EventName": "BUS_LOCK_CLOCKS.SELF", + "SampleAfterValue": "200000", + "BriefDescription": "Bus cycles when a LOCK signal is asserted." + }, + { + "EventCode": "0x64", + "Counter": "0,1", + "UMask": "0x40", + "EventName": "BUS_DATA_RCV.SELF", + "SampleAfterValue": "200000", + "BriefDescription": "Bus cycles while processor receives data." + }, + { + "EventCode": "0x65", + "Counter": "0,1", + "UMask": "0xe0", + "EventName": "BUS_TRANS_BRD.ALL_AGENTS", + "SampleAfterValue": "200000", + "BriefDescription": "Burst read bus transactions." + }, + { + "EventCode": "0x65", + "Counter": "0,1", + "UMask": "0x40", + "EventName": "BUS_TRANS_BRD.SELF", + "SampleAfterValue": "200000", + "BriefDescription": "Burst read bus transactions." + }, + { + "EventCode": "0x66", + "Counter": "0,1", + "UMask": "0xe0", + "EventName": "BUS_TRANS_RFO.ALL_AGENTS", + "SampleAfterValue": "200000", + "BriefDescription": "RFO bus transactions." + }, + { + "EventCode": "0x66", + "Counter": "0,1", + "UMask": "0x40", + "EventName": "BUS_TRANS_RFO.SELF", + "SampleAfterValue": "200000", + "BriefDescription": "RFO bus transactions." + }, + { + "EventCode": "0x67", + "Counter": "0,1", + "UMask": "0xe0", + "EventName": "BUS_TRANS_WB.ALL_AGENTS", + "SampleAfterValue": "200000", + "BriefDescription": "Explicit writeback bus transactions." + }, + { + "EventCode": "0x67", + "Counter": "0,1", + "UMask": "0x40", + "EventName": "BUS_TRANS_WB.SELF", + "SampleAfterValue": "200000", + "BriefDescription": "Explicit writeback bus transactions." + }, + { + "EventCode": "0x68", + "Counter": "0,1", + "UMask": "0xe0", + "EventName": "BUS_TRANS_IFETCH.ALL_AGENTS", + "SampleAfterValue": "200000", + "BriefDescription": "Instruction-fetch bus transactions." + }, + { + "EventCode": "0x68", + "Counter": "0,1", + "UMask": "0x40", + "EventName": "BUS_TRANS_IFETCH.SELF", + "SampleAfterValue": "200000", + "BriefDescription": "Instruction-fetch bus transactions." + }, + { + "EventCode": "0x69", + "Counter": "0,1", + "UMask": "0xe0", + "EventName": "BUS_TRANS_INVAL.ALL_AGENTS", + "SampleAfterValue": "200000", + "BriefDescription": "Invalidate bus transactions." + }, + { + "EventCode": "0x69", + "Counter": "0,1", + "UMask": "0x40", + "EventName": "BUS_TRANS_INVAL.SELF", + "SampleAfterValue": "200000", + "BriefDescription": "Invalidate bus transactions." + }, + { + "EventCode": "0x6A", + "Counter": "0,1", + "UMask": "0xe0", + "EventName": "BUS_TRANS_PWR.ALL_AGENTS", + "SampleAfterValue": "200000", + "BriefDescription": "Partial write bus transaction." + }, + { + "EventCode": "0x6A", + "Counter": "0,1", + "UMask": "0x40", + "EventName": "BUS_TRANS_PWR.SELF", + "SampleAfterValue": "200000", + "BriefDescription": "Partial write bus transaction." + }, + { + "EventCode": "0x6B", + "Counter": "0,1", + "UMask": "0xe0", + "EventName": "BUS_TRANS_P.ALL_AGENTS", + "SampleAfterValue": "200000", + "BriefDescription": "Partial bus transactions." + }, + { + "EventCode": "0x6B", + "Counter": "0,1", + "UMask": "0x40", + "EventName": "BUS_TRANS_P.SELF", + "SampleAfterValue": "200000", + "BriefDescription": "Partial bus transactions." + }, + { + "EventCode": "0x6C", + "Counter": "0,1", + "UMask": "0xe0", + "EventName": "BUS_TRANS_IO.ALL_AGENTS", + "SampleAfterValue": "200000", + "BriefDescription": "IO bus transactions." + }, + { + "EventCode": "0x6C", + "Counter": "0,1", + "UMask": "0x40", + "EventName": "BUS_TRANS_IO.SELF", + "SampleAfterValue": "200000", + "BriefDescription": "IO bus transactions." + }, + { + "EventCode": "0x6D", + "Counter": "0,1", + "UMask": "0xe0", + "EventName": "BUS_TRANS_DEF.ALL_AGENTS", + "SampleAfterValue": "200000", + "BriefDescription": "Deferred bus transactions." + }, + { + "EventCode": "0x6D", + "Counter": "0,1", + "UMask": "0x40", + "EventName": "BUS_TRANS_DEF.SELF", + "SampleAfterValue": "200000", + "BriefDescription": "Deferred bus transactions." + }, + { + "EventCode": "0x6E", + "Counter": "0,1", + "UMask": "0xe0", + "EventName": "BUS_TRANS_BURST.ALL_AGENTS", + "SampleAfterValue": "200000", + "BriefDescription": "Burst (full cache-line) bus transactions." + }, + { + "EventCode": "0x6E", + "Counter": "0,1", + "UMask": "0x40", + "EventName": "BUS_TRANS_BURST.SELF", + "SampleAfterValue": "200000", + "BriefDescription": "Burst (full cache-line) bus transactions." + }, + { + "EventCode": "0x6F", + "Counter": "0,1", + "UMask": "0xe0", + "EventName": "BUS_TRANS_MEM.ALL_AGENTS", + "SampleAfterValue": "200000", + "BriefDescription": "Memory bus transactions." + }, + { + "EventCode": "0x6F", + "Counter": "0,1", + "UMask": "0x40", + "EventName": "BUS_TRANS_MEM.SELF", + "SampleAfterValue": "200000", + "BriefDescription": "Memory bus transactions." + }, + { + "EventCode": "0x70", + "Counter": "0,1", + "UMask": "0xe0", + "EventName": "BUS_TRANS_ANY.ALL_AGENTS", + "SampleAfterValue": "200000", + "BriefDescription": "All bus transactions." + }, + { + "EventCode": "0x70", + "Counter": "0,1", + "UMask": "0x40", + "EventName": "BUS_TRANS_ANY.SELF", + "SampleAfterValue": "200000", + "BriefDescription": "All bus transactions." + }, + { + "EventCode": "0x77", + "Counter": "0,1", + "UMask": "0xb", + "EventName": "EXT_SNOOP.THIS_AGENT.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "External snoops." + }, + { + "EventCode": "0x77", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "EXT_SNOOP.THIS_AGENT.CLEAN", + "SampleAfterValue": "200000", + "BriefDescription": "External snoops." + }, + { + "EventCode": "0x77", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "EXT_SNOOP.THIS_AGENT.HIT", + "SampleAfterValue": "200000", + "BriefDescription": "External snoops." + }, + { + "EventCode": "0x77", + "Counter": "0,1", + "UMask": "0x8", + "EventName": "EXT_SNOOP.THIS_AGENT.HITM", + "SampleAfterValue": "200000", + "BriefDescription": "External snoops." + }, + { + "EventCode": "0x77", + "Counter": "0,1", + "UMask": "0x2b", + "EventName": "EXT_SNOOP.ALL_AGENTS.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "External snoops." + }, + { + "EventCode": "0x77", + "Counter": "0,1", + "UMask": "0x21", + "EventName": "EXT_SNOOP.ALL_AGENTS.CLEAN", + "SampleAfterValue": "200000", + "BriefDescription": "External snoops." + }, + { + "EventCode": "0x77", + "Counter": "0,1", + "UMask": "0x22", + "EventName": "EXT_SNOOP.ALL_AGENTS.HIT", + "SampleAfterValue": "200000", + "BriefDescription": "External snoops." + }, + { + "EventCode": "0x77", + "Counter": "0,1", + "UMask": "0x28", + "EventName": "EXT_SNOOP.ALL_AGENTS.HITM", + "SampleAfterValue": "200000", + "BriefDescription": "External snoops." + }, + { + "EventCode": "0x7A", + "Counter": "0,1", + "UMask": "0x20", + "EventName": "BUS_HIT_DRV.ALL_AGENTS", + "SampleAfterValue": "200000", + "BriefDescription": "HIT signal asserted." + }, + { + "EventCode": "0x7A", + "Counter": "0,1", + "UMask": "0x0", + "EventName": "BUS_HIT_DRV.THIS_AGENT", + "SampleAfterValue": "200000", + "BriefDescription": "HIT signal asserted." + }, + { + "EventCode": "0x7B", + "Counter": "0,1", + "UMask": "0x20", + "EventName": "BUS_HITM_DRV.ALL_AGENTS", + "SampleAfterValue": "200000", + "BriefDescription": "HITM signal asserted." + }, + { + "EventCode": "0x7B", + "Counter": "0,1", + "UMask": "0x0", + "EventName": "BUS_HITM_DRV.THIS_AGENT", + "SampleAfterValue": "200000", + "BriefDescription": "HITM signal asserted." + }, + { + "EventCode": "0x7D", + "Counter": "0,1", + "UMask": "0x40", + "EventName": "BUSQ_EMPTY.SELF", + "SampleAfterValue": "200000", + "BriefDescription": "Bus queue is empty." + }, + { + "EventCode": "0x7E", + "Counter": "0,1", + "UMask": "0xe0", + "EventName": "SNOOP_STALL_DRV.ALL_AGENTS", + "SampleAfterValue": "200000", + "BriefDescription": "Bus stalled for snoops." + }, + { + "EventCode": "0x7E", + "Counter": "0,1", + "UMask": "0x40", + "EventName": "SNOOP_STALL_DRV.SELF", + "SampleAfterValue": "200000", + "BriefDescription": "Bus stalled for snoops." + }, + { + "EventCode": "0x7F", + "Counter": "0,1", + "UMask": "0x40", + "EventName": "BUS_IO_WAIT.SELF", + "SampleAfterValue": "200000", + "BriefDescription": "IO requests waiting in the bus queue." + }, + { + "EventCode": "0xC6", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "CYCLES_INT_MASKED.CYCLES_INT_MASKED", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles during which interrupts are disabled." + }, + { + "EventCode": "0xC6", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "CYCLES_INT_MASKED.CYCLES_INT_PENDING_AND_MASKED", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles during which interrupts are pending and disabled." + }, + { + "EventCode": "0xC8", + "Counter": "0,1", + "UMask": "0x0", + "EventName": "HW_INT_RCV", + "SampleAfterValue": "200000", + "BriefDescription": "Hardware interrupts received." + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json b/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json new file mode 100644 index 000000000000..b2e681c78466 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json @@ -0,0 +1,364 @@ +[ + { + "EventCode": "0x2", + "Counter": "0,1", + "UMask": "0x83", + "EventName": "STORE_FORWARDS.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "All store forwards" + }, + { + "EventCode": "0x2", + "Counter": "0,1", + "UMask": "0x81", + "EventName": "STORE_FORWARDS.GOOD", + "SampleAfterValue": "200000", + "BriefDescription": "Good store forwards" + }, + { + "EventCode": "0x3", + "Counter": "0,1", + "UMask": "0x7f", + "EventName": "REISSUE.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "Micro-op reissues for any cause" + }, + { + "EventCode": "0x3", + "Counter": "0,1", + "UMask": "0xff", + "EventName": "REISSUE.ANY.AR", + "SampleAfterValue": "200000", + "BriefDescription": "Micro-op reissues for any cause (At Retirement)" + }, + { + "EventCode": "0x12", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "MUL.S", + "SampleAfterValue": "2000000", + "BriefDescription": "Multiply operations executed." + }, + { + "EventCode": "0x12", + "Counter": "0,1", + "UMask": "0x81", + "EventName": "MUL.AR", + "SampleAfterValue": "2000000", + "BriefDescription": "Multiply operations retired" + }, + { + "EventCode": "0x13", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "DIV.S", + "SampleAfterValue": "2000000", + "BriefDescription": "Divide operations executed." + }, + { + "EventCode": "0x13", + "Counter": "0,1", + "UMask": "0x81", + "EventName": "DIV.AR", + "SampleAfterValue": "2000000", + "BriefDescription": "Divide operations retired" + }, + { + "EventCode": "0x14", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "CYCLES_DIV_BUSY", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles the divider is busy." + }, + { + "EventCode": "0x3C", + "Counter": "0,1", + "UMask": "0x0", + "EventName": "CPU_CLK_UNHALTED.CORE_P", + "SampleAfterValue": "2000000", + "BriefDescription": "Core cycles when core is not halted" + }, + { + "EventCode": "0x3C", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "CPU_CLK_UNHALTED.BUS", + "SampleAfterValue": "200000", + "BriefDescription": "Bus cycles when core is not halted" + }, + { + "EventCode": "0xA", + "Counter": "Fixed counter 2", + "UMask": "0x0", + "EventName": "CPU_CLK_UNHALTED.CORE", + "SampleAfterValue": "2000000", + "BriefDescription": "Core cycles when core is not halted" + }, + { + "EventCode": "0xA", + "Counter": "Fixed counter 3", + "UMask": "0x0", + "EventName": "CPU_CLK_UNHALTED.REF", + "SampleAfterValue": "2000000", + "BriefDescription": "Reference cycles when core is not halted." + }, + { + "EventCode": "0x88", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "BR_INST_TYPE_RETIRED.COND", + "SampleAfterValue": "2000000", + "BriefDescription": "All macro conditional branch instructions." + }, + { + "EventCode": "0x88", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "BR_INST_TYPE_RETIRED.UNCOND", + "SampleAfterValue": "2000000", + "BriefDescription": "All macro unconditional branch instructions, excluding calls and indirects" + }, + { + "EventCode": "0x88", + "Counter": "0,1", + "UMask": "0x4", + "EventName": "BR_INST_TYPE_RETIRED.IND", + "SampleAfterValue": "2000000", + "BriefDescription": "All indirect branches that are not calls." + }, + { + "EventCode": "0x88", + "Counter": "0,1", + "UMask": "0x8", + "EventName": "BR_INST_TYPE_RETIRED.RET", + "SampleAfterValue": "2000000", + "BriefDescription": "All indirect branches that have a return mnemonic" + }, + { + "EventCode": "0x88", + "Counter": "0,1", + "UMask": "0x10", + "EventName": "BR_INST_TYPE_RETIRED.DIR_CALL", + "SampleAfterValue": "2000000", + "BriefDescription": "All non-indirect calls" + }, + { + "EventCode": "0x88", + "Counter": "0,1", + "UMask": "0x20", + "EventName": "BR_INST_TYPE_RETIRED.IND_CALL", + "SampleAfterValue": "2000000", + "BriefDescription": "All indirect calls, including both register and memory indirect." + }, + { + "EventCode": "0x88", + "Counter": "0,1", + "UMask": "0x41", + "EventName": "BR_INST_TYPE_RETIRED.COND_TAKEN", + "SampleAfterValue": "2000000", + "BriefDescription": "Only taken macro conditional branch instructions" + }, + { + "EventCode": "0x89", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "BR_MISSP_TYPE_RETIRED.COND", + "SampleAfterValue": "200000", + "BriefDescription": "Mispredicted cond branch instructions retired" + }, + { + "EventCode": "0x89", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "BR_MISSP_TYPE_RETIRED.IND", + "SampleAfterValue": "200000", + "BriefDescription": "Mispredicted ind branches that are not calls" + }, + { + "EventCode": "0x89", + "Counter": "0,1", + "UMask": "0x4", + "EventName": "BR_MISSP_TYPE_RETIRED.RETURN", + "SampleAfterValue": "200000", + "BriefDescription": "Mispredicted return branches" + }, + { + "EventCode": "0x89", + "Counter": "0,1", + "UMask": "0x8", + "EventName": "BR_MISSP_TYPE_RETIRED.IND_CALL", + "SampleAfterValue": "200000", + "BriefDescription": "Mispredicted indirect calls, including both register and memory indirect. " + }, + { + "EventCode": "0x89", + "Counter": "0,1", + "UMask": "0x11", + "EventName": "BR_MISSP_TYPE_RETIRED.COND_TAKEN", + "SampleAfterValue": "200000", + "BriefDescription": "Mispredicted and taken cond branch instructions retired" + }, + { + "PEBS": "2", + "EventCode": "0xC0", + "Counter": "0,1", + "UMask": "0x0", + "EventName": "INST_RETIRED.ANY_P", + "SampleAfterValue": "2000000", + "BriefDescription": "Instructions retired (precise event)." + }, + { + "EventCode": "0xA", + "Counter": "Fixed counter 1", + "UMask": "0x0", + "EventName": "INST_RETIRED.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "Instructions retired." + }, + { + "EventCode": "0xC2", + "Counter": "0,1", + "UMask": "0x10", + "EventName": "UOPS_RETIRED.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "Micro-ops retired." + }, + { + "EventCode": "0xC2", + "Counter": "0,1", + "UMask": "0x10", + "EventName": "UOPS_RETIRED.STALLED_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles no micro-ops retired." + }, + { + "EventCode": "0xC2", + "Counter": "0,1", + "UMask": "0x10", + "EventName": "UOPS_RETIRED.STALLS", + "SampleAfterValue": "2000000", + "BriefDescription": "Periods no micro-ops retired." + }, + { + "EventCode": "0xC3", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "MACHINE_CLEARS.SMC", + "SampleAfterValue": "200000", + "BriefDescription": "Self-Modifying Code detected." + }, + { + "EventCode": "0xC4", + "Counter": "0,1", + "UMask": "0x0", + "EventName": "BR_INST_RETIRED.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "Retired branch instructions." + }, + { + "EventCode": "0xC4", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "BR_INST_RETIRED.PRED_NOT_TAKEN", + "SampleAfterValue": "2000000", + "BriefDescription": "Retired branch instructions that were predicted not-taken." + }, + { + "EventCode": "0xC4", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "BR_INST_RETIRED.MISPRED_NOT_TAKEN", + "SampleAfterValue": "200000", + "BriefDescription": "Retired branch instructions that were mispredicted not-taken." + }, + { + "EventCode": "0xC4", + "Counter": "0,1", + "UMask": "0x4", + "EventName": "BR_INST_RETIRED.PRED_TAKEN", + "SampleAfterValue": "2000000", + "BriefDescription": "Retired branch instructions that were predicted taken." + }, + { + "EventCode": "0xC4", + "Counter": "0,1", + "UMask": "0x8", + "EventName": "BR_INST_RETIRED.MISPRED_TAKEN", + "SampleAfterValue": "200000", + "BriefDescription": "Retired branch instructions that were mispredicted taken." + }, + { + "EventCode": "0xC4", + "Counter": "0,1", + "UMask": "0xc", + "EventName": "BR_INST_RETIRED.TAKEN", + "SampleAfterValue": "2000000", + "BriefDescription": "Retired taken branch instructions." + }, + { + "EventCode": "0xC4", + "Counter": "0,1", + "UMask": "0xf", + "EventName": "BR_INST_RETIRED.ANY1", + "SampleAfterValue": "2000000", + "BriefDescription": "Retired branch instructions." + }, + { + "PEBS": "1", + "EventCode": "0xC5", + "Counter": "0,1", + "UMask": "0x0", + "EventName": "BR_INST_RETIRED.MISPRED", + "SampleAfterValue": "200000", + "BriefDescription": "Retired mispredicted branch instructions (precise event)." + }, + { + "EventCode": "0xDC", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "RESOURCE_STALLS.DIV_BUSY", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles issue is stalled due to div busy." + }, + { + "EventCode": "0xE0", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "BR_INST_DECODED", + "SampleAfterValue": "2000000", + "BriefDescription": "Branch instructions decoded" + }, + { + "EventCode": "0xE4", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "BOGUS_BR", + "SampleAfterValue": "2000000", + "BriefDescription": "Bogus branches" + }, + { + "EventCode": "0xE6", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "BACLEARS.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "BACLEARS asserted." + }, + { + "EventCode": "0x3", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "REISSUE.OVERLAP_STORE", + "SampleAfterValue": "200000", + "BriefDescription": "Micro-op reissues on a store-load collision" + }, + { + "EventCode": "0x3", + "Counter": "0,1", + "UMask": "0x81", + "EventName": "REISSUE.OVERLAP_STORE.AR", + "SampleAfterValue": "200000", + "BriefDescription": "Micro-op reissues on a store-load collision (At Retirement)" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json b/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json new file mode 100644 index 000000000000..7bb817588721 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json @@ -0,0 +1,124 @@ +[ + { + "EventCode": "0x8", + "Counter": "0,1", + "UMask": "0x7", + "EventName": "DATA_TLB_MISSES.DTLB_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "Memory accesses that missed the DTLB." + }, + { + "EventCode": "0x8", + "Counter": "0,1", + "UMask": "0x5", + "EventName": "DATA_TLB_MISSES.DTLB_MISS_LD", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB misses due to load operations." + }, + { + "EventCode": "0x8", + "Counter": "0,1", + "UMask": "0x9", + "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_LD", + "SampleAfterValue": "200000", + "BriefDescription": "L0 DTLB misses due to load operations." + }, + { + "EventCode": "0x8", + "Counter": "0,1", + "UMask": "0x6", + "EventName": "DATA_TLB_MISSES.DTLB_MISS_ST", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB misses due to store operations." + }, + { + "EventCode": "0x8", + "Counter": "0,1", + "UMask": "0xa", + "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_ST", + "SampleAfterValue": "200000", + "BriefDescription": "L0 DTLB misses due to store operations" + }, + { + "EventCode": "0xC", + "Counter": "0,1", + "UMask": "0x3", + "EventName": "PAGE_WALKS.WALKS", + "SampleAfterValue": "200000", + "BriefDescription": "Number of page-walks executed." + }, + { + "EventCode": "0xC", + "Counter": "0,1", + "UMask": "0x3", + "EventName": "PAGE_WALKS.CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Duration of page-walks in core cycles" + }, + { + "EventCode": "0xC", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "PAGE_WALKS.D_SIDE_WALKS", + "SampleAfterValue": "200000", + "BriefDescription": "Number of D-side only page walks" + }, + { + "EventCode": "0xC", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "PAGE_WALKS.D_SIDE_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Duration of D-side only page walks" + }, + { + "EventCode": "0xC", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "PAGE_WALKS.I_SIDE_WALKS", + "SampleAfterValue": "200000", + "BriefDescription": "Number of I-Side page walks" + }, + { + "EventCode": "0xC", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "PAGE_WALKS.I_SIDE_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Duration of I-Side page walks" + }, + { + "EventCode": "0x82", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "ITLB.HIT", + "SampleAfterValue": "200000", + "BriefDescription": "ITLB hits." + }, + { + "EventCode": "0x82", + "Counter": "0,1", + "UMask": "0x4", + "EventName": "ITLB.FLUSH", + "SampleAfterValue": "200000", + "BriefDescription": "ITLB flushes." + }, + { + "PEBS": "2", + "EventCode": "0x82", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "ITLB.MISSES", + "SampleAfterValue": "200000", + "BriefDescription": "ITLB misses." + }, + { + "PEBS": "1", + "EventCode": "0xCB", + "Counter": "0,1", + "UMask": "0x4", + "EventName": "MEM_LOAD_RETIRED.DTLB_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "Retired loads that miss the DTLB (precise event)." + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwell/cache.json b/tools/perf/pmu-events/arch/x86/broadwell/cache.json new file mode 100644 index 000000000000..73688a9dab2a --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/broadwell/cache.json @@ -0,0 +1,3198 @@ +[ + { + "PublicDescription": "This event counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x21", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", + "SampleAfterValue": "200003", + "BriefDescription": "Demand Data Read miss L2, no rejects", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of demand Data Read requests that hit L2 cache. Only not rejected loads are counted.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x41", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "SampleAfterValue": "200003", + "BriefDescription": "Demand Data Read requests that hit L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that miss L2 cache.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "L2_RQSTS.L2_PF_MISS", + "SampleAfterValue": "200003", + "BriefDescription": "L2 prefetch requests that miss L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x50", + "EventName": "L2_RQSTS.L2_PF_HIT", + "SampleAfterValue": "200003", + "BriefDescription": "L2 prefetch requests that hit L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xe1", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "SampleAfterValue": "200003", + "BriefDescription": "Demand Data Read requests", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xe2", + "EventName": "L2_RQSTS.ALL_RFO", + "SampleAfterValue": "200003", + "BriefDescription": "RFO requests to L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the total number of L2 code requests.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xe4", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "SampleAfterValue": "200003", + "BriefDescription": "L2 code requests", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the total number of requests from the L2 hardware prefetchers.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xf8", + "EventName": "L2_RQSTS.ALL_PF", + "SampleAfterValue": "200003", + "BriefDescription": "Requests from L2 hardware prefetchers", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of WB requests that hit L2 cache.", + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x50", + "EventName": "L2_DEMAND_RQSTS.WB_HIT", + "SampleAfterValue": "200003", + "BriefDescription": "Not rejected writebacks that hit L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.", + "EventCode": "0x2E", + "Counter": "0,1,2,3", + "UMask": "0x41", + "EventName": "LONGEST_LAT_CACHE.MISS", + "SampleAfterValue": "100003", + "BriefDescription": "Core-originated cacheable demand requests missed L3", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.", + "EventCode": "0x2E", + "Counter": "0,1,2,3", + "UMask": "0x4f", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "SampleAfterValue": "100003", + "BriefDescription": "Core-originated cacheable demand requests that refer to L3", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch.\nNote: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", + "EventCode": "0x48", + "Counter": "2", + "UMask": "0x1", + "EventName": "L1D_PEND_MISS.PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "L1D miss oustandings duration in cycles", + "CounterHTOff": "2" + }, + { + "PublicDescription": "This event counts duration of L1D miss outstanding in cycles.", + "EventCode": "0x48", + "Counter": "2", + "UMask": "0x1", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with L1D load Misses outstanding.", + "CounterMask": "1", + "CounterHTOff": "2" + }, + { + "PublicDescription": "This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", + "EventCode": "0x51", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L1D.REPLACEMENT", + "SampleAfterValue": "2000003", + "BriefDescription": "L1D data line replacements", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.\nNote: A prefetch promoted to Demand is counted from the promotion point.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Errata": "BDM76", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The \"Offcore outstanding\" state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x2", + "Errata": "BDM76", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x4", + "Errata": "BDM76", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x8", + "Errata": "BDM76", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation).", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Errata": "BDM76", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x8", + "Errata": "BDM76", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The \"Offcore outstanding\" state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x4", + "Errata": "BDM76", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).", + "EventCode": "0x63", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when L1D is locked", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.", + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "SampleAfterValue": "100003", + "BriefDescription": "Demand Data Read requests sent to uncore", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts both cacheable and noncachaeble code read requests.", + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "SampleAfterValue": "100003", + "BriefDescription": "Cacheable and noncachaeble code read requests", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.", + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "SampleAfterValue": "100003", + "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the demand and prefetch data reads. All Core Data Reads include cacheable \"Demands\" and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.", + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", + "SampleAfterValue": "100003", + "BriefDescription": "Demand and prefetch data reads", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.\nNote: Writeback pending FIFO has six entries.", + "EventCode": "0xb2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x11", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load uops that miss the STLB.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts store uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x12", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", + "SampleAfterValue": "100003", + "BriefDescription": "Retired store uops that miss the STLB.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "L1_Hit_Indication": "1" + }, + { + "PEBS": "1", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts load uops with locked access retired to the architected path.", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x21", + "Errata": "BDM35", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "SampleAfterValue": "100007", + "BriefDescription": "Retired load uops with locked access.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x41", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load uops that split across a cacheline boundary.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x42", + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "SampleAfterValue": "100003", + "BriefDescription": "Retired store uops that split across a cacheline boundary.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "L1_Hit_Indication": "1" + }, + { + "PEBS": "1", + "PublicDescription": "This event counts load uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches.", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x81", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "SampleAfterValue": "2000003", + "BriefDescription": "All retired load uops.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "PublicDescription": "This event counts store uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement.", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x82", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "SampleAfterValue": "2000003", + "BriefDescription": "All retired store uops.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "L1_Hit_Indication": "1" + }, + { + "PEBS": "1", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were hits in the nearest-level (L1) cache.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source.", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "SampleAfterValue": "2000003", + "BriefDescription": "Retired load uops with L1 cache hits as data sources.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were hits in the mid-level (L2) cache.", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "Errata": "BDM35", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load uops with L2 cache hits as data sources.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required.", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x4", + "Errata": "BDM100", + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", + "SampleAfterValue": "50021", + "BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source.", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load uops misses in L1 cache as data sources.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source.", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "SampleAfterValue": "50021", + "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x20", + "Errata": "BDM100, BDE70", + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS", + "SampleAfterValue": "100007", + "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load.", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache.", + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Errata": "BDM100", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS", + "SampleAfterValue": "20011", + "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache.", + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "Errata": "BDM100", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT", + "SampleAfterValue": "20011", + "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were HitM responses from a core on same socket (shared L3).", + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "Errata": "BDM100", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM", + "SampleAfterValue": "20011", + "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required.", + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x8", + "Errata": "BDM100", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "PublicDescription": "Retired load uop whose Data Source was: local DRAM either Snoop not needed or Snoop Miss (RspI).", + "EventCode": "0xD3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Errata": "BDE70, BDM100", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", + "SampleAfterValue": "100007", + "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PublicDescription": "This event counts Demand Data Read requests that access L2 cache, including rejects.", + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_TRANS.DEMAND_DATA_RD", + "SampleAfterValue": "200003", + "BriefDescription": "Demand Data Read requests that access L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts Read for Ownership (RFO) requests that access L2 cache.", + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_TRANS.RFO", + "SampleAfterValue": "200003", + "BriefDescription": "RFO requests that access L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of L2 cache accesses when fetching instructions.", + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_TRANS.CODE_RD", + "SampleAfterValue": "200003", + "BriefDescription": "L2 cache accesses when fetching instructions", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts L2 or L3 HW prefetches that access L2 cache including rejects.", + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_TRANS.ALL_PF", + "SampleAfterValue": "200003", + "BriefDescription": "L2 or L3 HW prefetches that access L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts L1D writebacks that access L2 cache.", + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "L2_TRANS.L1D_WB", + "SampleAfterValue": "200003", + "BriefDescription": "L1D writebacks that access L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts L2 fill requests that access L2 cache.", + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "L2_TRANS.L2_FILL", + "SampleAfterValue": "200003", + "BriefDescription": "L2 fill requests that access L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts L2 writebacks that access L2 cache.", + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "L2_TRANS.L2_WB", + "SampleAfterValue": "200003", + "BriefDescription": "L2 writebacks that access L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts transactions that access the L2 pipe including snoops, pagewalks, and so on.", + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "L2_TRANS.ALL_REQUESTS", + "SampleAfterValue": "200003", + "BriefDescription": "Transactions accessing L2 pipe", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of L2 cache lines in the Invalidate state filling the L2. Counting does not cover rejects.", + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_LINES_IN.I", + "SampleAfterValue": "100003", + "BriefDescription": "L2 cache lines in I state filling L2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of L2 cache lines in the Shared state filling the L2. Counting does not cover rejects.", + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_LINES_IN.S", + "SampleAfterValue": "100003", + "BriefDescription": "L2 cache lines in S state filling L2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of L2 cache lines in the Exclusive state filling the L2. Counting does not cover rejects.", + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_LINES_IN.E", + "SampleAfterValue": "100003", + "BriefDescription": "L2 cache lines in E state filling L2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does not cover rejects.", + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x7", + "EventName": "L2_LINES_IN.ALL", + "SampleAfterValue": "100003", + "BriefDescription": "L2 cache lines filling L2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x5", + "EventName": "L2_LINES_OUT.DEMAND_CLEAN", + "SampleAfterValue": "100003", + "BriefDescription": "Clean L2 cache lines evicted by demand.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of split locks in the super queue.", + "EventCode": "0xf4", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "SQ_MISC.SPLIT_LOCK", + "SampleAfterValue": "100003", + "BriefDescription": "Split locks in SQ", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x42", + "EventName": "L2_RQSTS.RFO_HIT", + "SampleAfterValue": "200003", + "BriefDescription": "RFO requests that hit L2 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x22", + "EventName": "L2_RQSTS.RFO_MISS", + "SampleAfterValue": "200003", + "BriefDescription": "RFO requests that miss L2 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x44", + "EventName": "L2_RQSTS.CODE_RD_HIT", + "SampleAfterValue": "200003", + "BriefDescription": "L2 cache hits when fetching instructions, code reads.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x24", + "EventName": "L2_RQSTS.CODE_RD_MISS", + "SampleAfterValue": "200003", + "BriefDescription": "L2 cache misses when fetching instructions.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x27", + "EventName": "L2_RQSTS.ALL_DEMAND_MISS", + "SampleAfterValue": "200003", + "BriefDescription": "Demand requests that miss L2 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xe7", + "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", + "SampleAfterValue": "200003", + "BriefDescription": "Demand requests to L2 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x3f", + "EventName": "L2_RQSTS.MISS", + "SampleAfterValue": "200003", + "BriefDescription": "All requests that miss L2 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xff", + "EventName": "L2_RQSTS.REFERENCES", + "SampleAfterValue": "200003", + "BriefDescription": "All L2 requests.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB7, 0xBB", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE", + "SampleAfterValue": "100003", + "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Errata": "BDM76", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", + "CounterMask": "6", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x48", + "Counter": "2", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", + "CounterMask": "1", + "CounterHTOff": "2" + }, + { + "EventCode": "0x48", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L1D_PEND_MISS.FB_FULL", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0000010001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that have any response type.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080020001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100020001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200020001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400020001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000020001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f80020001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00803c0001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that hit in the L3 with no details on snoop-related information.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x01003c0001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x02003c0001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that hit in the L3 with a snoop miss response.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x04003c0001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L3_HIT & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that hit in the L3.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0000010002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand data writes (RFOs) that have any response type.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00803c0002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 with no details on snoop-related information.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x01003c0002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x02003c0002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 with a snoop miss response.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x04003c0002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & L3_HIT & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0000010004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand code reads that have any response type.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080020004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & SUPPLIER_NONE & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100020004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & SUPPLIER_NONE & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200020004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & SUPPLIER_NONE & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400020004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & SUPPLIER_NONE & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000020004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & SUPPLIER_NONE & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f80020004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & SUPPLIER_NONE & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00803c0004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand code reads that hit in the L3 with no details on snoop-related information.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x01003c0004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x02003c0004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand code reads that hit in the L3 with a snoop miss response.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x04003c0004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L3_HIT & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand code reads that hit in the L3.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0000010008 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts writebacks (modified to exclusive) that have any response type.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080020008 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "COREWB & SUPPLIER_NONE & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100020008 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "COREWB & SUPPLIER_NONE & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200020008 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "COREWB & SUPPLIER_NONE & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400020008 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "COREWB & SUPPLIER_NONE & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000020008 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "COREWB & SUPPLIER_NONE & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f80020008 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "COREWB & SUPPLIER_NONE & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00803c0008 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts writebacks (modified to exclusive) that hit in the L3 with no details on snoop-related information.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x01003c0008 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts writebacks (modified to exclusive) that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x02003c0008 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts writebacks (modified to exclusive) that hit in the L3 with a snoop miss response.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x04003c0008 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts writebacks (modified to exclusive) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0008 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "COREWB & L3_HIT & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0008 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts writebacks (modified to exclusive) that hit in the L3.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0000010010 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that have any response type.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080020010 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_DATA_RD & SUPPLIER_NONE & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100020010 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_DATA_RD & SUPPLIER_NONE & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200020010 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_DATA_RD & SUPPLIER_NONE & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400020010 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_DATA_RD & SUPPLIER_NONE & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000020010 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_DATA_RD & SUPPLIER_NONE & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f80020010 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_DATA_RD & SUPPLIER_NONE & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00803c0010 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 with no details on snoop-related information.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x01003c0010 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x02003c0010 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 with a snoop miss response.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x04003c0010 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0010 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_DATA_RD & L3_HIT & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0010 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0000010020 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that have any response type.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080020020 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_RFO & SUPPLIER_NONE & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100020020 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_RFO & SUPPLIER_NONE & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200020020 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_RFO & SUPPLIER_NONE & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400020020 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_RFO & SUPPLIER_NONE & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000020020 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_RFO & SUPPLIER_NONE & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f80020020 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_RFO & SUPPLIER_NONE & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00803c0020 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 with no details on snoop-related information.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x01003c0020 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x02003c0020 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 with a snoop miss response.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x04003c0020 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0020 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_RFO & L3_HIT & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0020 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0000010040 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that have any response type.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080020040 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_CODE_RD & SUPPLIER_NONE & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100020040 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_CODE_RD & SUPPLIER_NONE & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200020040 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_CODE_RD & SUPPLIER_NONE & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400020040 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_CODE_RD & SUPPLIER_NONE & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000020040 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_CODE_RD & SUPPLIER_NONE & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f80020040 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_CODE_RD & SUPPLIER_NONE & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00803c0040 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 with no details on snoop-related information.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x01003c0040 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x02003c0040 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 with a snoop miss response.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x04003c0040 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0040 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_CODE_RD & L3_HIT & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0040 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0000010080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that have any response type.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080020080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & SUPPLIER_NONE & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100020080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & SUPPLIER_NONE & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200020080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & SUPPLIER_NONE & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400020080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & SUPPLIER_NONE & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000020080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & SUPPLIER_NONE & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f80020080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & SUPPLIER_NONE & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00803c0080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 with no details on snoop-related information.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x01003c0080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x02003c0080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 with a snoop miss response.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x04003c0080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L3_HIT & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0000010100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that have any response type.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080020100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & SUPPLIER_NONE & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100020100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & SUPPLIER_NONE & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200020100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & SUPPLIER_NONE & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400020100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & SUPPLIER_NONE & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000020100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & SUPPLIER_NONE & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f80020100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & SUPPLIER_NONE & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00803c0100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 with no details on snoop-related information.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x01003c0100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x02003c0100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 with a snoop miss response.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x04003c0100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L3_HIT & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0000010200 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that have any response type.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080020200 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_CODE_RD & SUPPLIER_NONE & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100020200 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_CODE_RD & SUPPLIER_NONE & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200020200 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_CODE_RD & SUPPLIER_NONE & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400020200 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_CODE_RD & SUPPLIER_NONE & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000020200 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_CODE_RD & SUPPLIER_NONE & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f80020200 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_CODE_RD & SUPPLIER_NONE & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00803c0200 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3 with no details on snoop-related information.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x01003c0200 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x02003c0200 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3 with a snoop miss response.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x04003c0200 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0200 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_CODE_RD & L3_HIT & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0200 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0000018000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts any other requests that have any response type.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080028000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & SUPPLIER_NONE & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100028000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & SUPPLIER_NONE & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200028000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & SUPPLIER_NONE & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400028000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & SUPPLIER_NONE & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000028000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & SUPPLIER_NONE & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f80028000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & SUPPLIER_NONE & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00803c8000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts any other requests that hit in the L3 with no details on snoop-related information.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x01003c8000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts any other requests that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x02003c8000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts any other requests that hit in the L3 with a snoop miss response.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x04003c8000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts any other requests that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c8000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_HIT & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c8000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts any other requests that hit in the L3.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0000010090 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch data reads that have any response type.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080020090 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_PF_DATA_RD & SUPPLIER_NONE & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100020090 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_PF_DATA_RD & SUPPLIER_NONE & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200020090 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_PF_DATA_RD & SUPPLIER_NONE & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400020090 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_PF_DATA_RD & SUPPLIER_NONE & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000020090 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_PF_DATA_RD & SUPPLIER_NONE & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f80020090 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_PF_DATA_RD & SUPPLIER_NONE & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00803c0090 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch data reads that hit in the L3 with no details on snoop-related information.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x01003c0090 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x02003c0090 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch data reads that hit in the L3 with a snoop miss response.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x04003c0090 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0090 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_PF_DATA_RD & L3_HIT & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0090 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch data reads that hit in the L3.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0000010120 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch RFOs that have any response type.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080020120 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_PF_RFO & SUPPLIER_NONE & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100020120 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_PF_RFO & SUPPLIER_NONE & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200020120 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_PF_RFO & SUPPLIER_NONE & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400020120 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_PF_RFO & SUPPLIER_NONE & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000020120 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_PF_RFO & SUPPLIER_NONE & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f80020120 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_PF_RFO & SUPPLIER_NONE & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00803c0120 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch RFOs that hit in the L3 with no details on snoop-related information.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x01003c0120 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x02003c0120 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch RFOs that hit in the L3 with a snoop miss response.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x04003c0120 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0120 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_PF_RFO & L3_HIT & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0120 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch RFOs that hit in the L3.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0000010240 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch code reads that have any response type.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080020240 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_PF_CODE_RD & SUPPLIER_NONE & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100020240 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_PF_CODE_RD & SUPPLIER_NONE & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200020240 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_PF_CODE_RD & SUPPLIER_NONE & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400020240 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_PF_CODE_RD & SUPPLIER_NONE & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000020240 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_PF_CODE_RD & SUPPLIER_NONE & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f80020240 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_PF_CODE_RD & SUPPLIER_NONE & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00803c0240 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch code reads that hit in the L3 with no details on snoop-related information.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x01003c0240 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x02003c0240 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch code reads that hit in the L3 with a snoop miss response.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x04003c0240 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0240 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_PF_CODE_RD & L3_HIT & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0240 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch code reads that hit in the L3.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0000010091 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch data reads that have any response type.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080020091 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_DATA_RD & SUPPLIER_NONE & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100020091 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_DATA_RD & SUPPLIER_NONE & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200020091 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_DATA_RD & SUPPLIER_NONE & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400020091 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_DATA_RD & SUPPLIER_NONE & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000020091 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_DATA_RD & SUPPLIER_NONE & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f80020091 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_DATA_RD & SUPPLIER_NONE & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00803c0091 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 with no details on snoop-related information.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x01003c0091 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x02003c0091 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 with a snoop miss response.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x04003c0091 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0091 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_DATA_RD & L3_HIT & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0091 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0000010122 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch RFOs that have any response type.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080020122 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_RFO & SUPPLIER_NONE & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100020122 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_RFO & SUPPLIER_NONE & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200020122 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_RFO & SUPPLIER_NONE & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400020122 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_RFO & SUPPLIER_NONE & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000020122 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_RFO & SUPPLIER_NONE & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f80020122 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_RFO & SUPPLIER_NONE & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00803c0122 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 with no details on snoop-related information.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x01003c0122 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x02003c0122 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 with a snoop miss response.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x04003c0122 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0122 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_RFO & L3_HIT & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0122 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwell/floating-point.json b/tools/perf/pmu-events/arch/x86/broadwell/floating-point.json new file mode 100644 index 000000000000..102bfb808199 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/broadwell/floating-point.json @@ -0,0 +1,171 @@ +[ + { + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable.", + "EventCode": "0xC1", + "Counter": "0,1,2,3", + "UMask": "0x8", + "Errata": "BDM30", + "EventName": "OTHER_ASSISTS.AVX_TO_SSE", + "SampleAfterValue": "100003", + "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable.", + "EventCode": "0xC1", + "Counter": "0,1,2,3", + "UMask": "0x10", + "Errata": "BDM30", + "EventName": "OTHER_ASSISTS.SSE_TO_AVX", + "SampleAfterValue": "100003", + "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "EventCode": "0xC7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xC7", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xC7", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xC7", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xC7", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.", + "EventCode": "0xCA", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "FP_ASSIST.X87_OUTPUT", + "SampleAfterValue": "100003", + "BriefDescription": "Number of X87 assists due to output value.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.", + "EventCode": "0xCA", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "FP_ASSIST.X87_INPUT", + "SampleAfterValue": "100003", + "BriefDescription": "Number of X87 assists due to input value.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.", + "EventCode": "0xCA", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "FP_ASSIST.SIMD_OUTPUT", + "SampleAfterValue": "100003", + "BriefDescription": "Number of SIMD FP assists due to Output values", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.", + "EventCode": "0xCA", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "FP_ASSIST.SIMD_INPUT", + "SampleAfterValue": "100003", + "BriefDescription": "Number of SIMD FP assists due to input values", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.", + "EventCode": "0xCA", + "Counter": "0,1,2,3", + "UMask": "0x1e", + "EventName": "FP_ASSIST.ANY", + "SampleAfterValue": "100003", + "BriefDescription": "Cycles with any input/output SSE or FP assist", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xc7", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC7", + "Counter": "0,1,2,3", + "UMask": "0x3", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC7", + "Counter": "0,1,2,3", + "UMask": "0x3c", + "EventName": "FP_ARITH_INST_RETIRED.PACKED", + "SampleAfterValue": "2000004", + "BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC7", + "Counter": "0,1,2,3", + "UMask": "0x2a", + "EventName": "FP_ARITH_INST_RETIRED.SINGLE", + "SampleAfterValue": "2000005", + "BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC7", + "Counter": "0,1,2,3", + "UMask": "0x15", + "EventName": "FP_ARITH_INST_RETIRED.DOUBLE", + "SampleAfterValue": "2000006", + "BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.", + "CounterHTOff": "0,1,2,3" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwell/frontend.json b/tools/perf/pmu-events/arch/x86/broadwell/frontend.json new file mode 100644 index 000000000000..b0cdf1f097a0 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/broadwell/frontend.json @@ -0,0 +1,286 @@ +[ + { + "PublicDescription": "This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "IDQ.EMPTY", + "SampleAfterValue": "2000003", + "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may \"bypass\" the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "IDQ.MITE_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may \"bypass\" the IDQ.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "IDQ.DSB_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may \"bypass\" the IDQ.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "IDQ.MS_DSB_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may \"bypass\" the IDQ.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "IDQ.MS_MITE_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may \"bypass\" the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "IDQ.MS_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may \"bypass\" the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "IDQ.MS_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may \"bypass\" the IDQ.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "IDQ.MITE_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may \"bypass\" the IDQ.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "IDQ.DSB_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may \"bypass\" the IDQ.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "IDQ.MS_DSB_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) is busy. Counting includes uops that may \"bypass\" the IDQ.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EdgeDetect": "1", + "EventName": "IDQ.MS_DSB_OCCUR", + "SampleAfterValue": "2000003", + "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may \"bypass\" the IDQ.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x18", + "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may \"bypass\" the IDQ.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x18", + "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may \"bypass\" the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x24", + "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles MITE is delivering 4 Uops", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may \"bypass\" the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x24", + "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles MITE is delivering any Uop", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may \"bypass\" the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x3c", + "EventName": "IDQ.MITE_ALL_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches.", + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ICACHE.HIT", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.", + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "ICACHE.MISSES", + "SampleAfterValue": "200003", + "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).", + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "ICACHE.IFDATA_STALL", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding ?4 ? x? when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); \n c. Instruction Decode Queue (IDQ) delivers four uops.", + "EventCode": "0x9C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "This event counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4.", + "EventCode": "0x9C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "This event counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >=3.", + "EventCode": "0x9C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled", + "CounterMask": "3", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", + "CounterMask": "2", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with less than 3 uops delivered by the front end.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 0?2 cycles.", + "EventCode": "0xAB", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EdgeDetect": "1", + "EventName": "IDQ.MS_SWITCHES", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwell/memory.json b/tools/perf/pmu-events/arch/x86/broadwell/memory.json new file mode 100644 index 000000000000..ff5416d29d0d --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/broadwell/memory.json @@ -0,0 +1,2845 @@ +[ + { + "PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.", + "EventCode": "0x05", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MISALIGN_MEM_REF.LOADS", + "SampleAfterValue": "2000003", + "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.", + "EventCode": "0x05", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MISALIGN_MEM_REF.STORES", + "SampleAfterValue": "2000003", + "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of times a TSX line had a cache conflict.", + "EventCode": "0x54", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "TX_MEM.ABORT_CONFLICT", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times a TSX line had a cache conflict", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.", + "EventCode": "0x54", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", + "EventCode": "0x54", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", + "EventCode": "0x54", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", + "EventCode": "0x54", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", + "EventCode": "0x54", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of times we could not allocate Lock Buffer.", + "EventCode": "0x54", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times we could not allocate Lock Buffer", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Unfriendly TSX abort triggered by a flowmarker.", + "EventCode": "0x5d", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "TX_EXEC.MISC1", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", + "EventCode": "0x5d", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "TX_EXEC.MISC2", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", + "EventCode": "0x5d", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "TX_EXEC.MISC3", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "RTM region detected inside HLE.", + "EventCode": "0x5d", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "TX_EXEC.MISC4", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5d", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "TX_EXEC.MISC5", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.", + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "SampleAfterValue": "100003", + "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.", + "EventCode": "0xc8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "HLE_RETIRED.START", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times we entered an HLE region; does not count nested transactions", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of times HLE commit succeeded.", + "EventCode": "0xc8", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "HLE_RETIRED.COMMIT", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times HLE commit succeeded", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "PublicDescription": "Number of times HLE abort was triggered.", + "EventCode": "0xc8", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "HLE_RETIRED.ABORTED", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times HLE abort was triggered", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).", + "EventCode": "0xc8", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "HLE_RETIRED.ABORTED_MISC1", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.", + "EventCode": "0xc8", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "HLE_RETIRED.ABORTED_MISC2", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of times a disallowed operation caused an HLE abort.", + "EventCode": "0xc8", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "HLE_RETIRED.ABORTED_MISC3", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of times HLE caused a fault.", + "EventCode": "0xc8", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "HLE_RETIRED.ABORTED_MISC4", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.", + "EventCode": "0xc8", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "HLE_RETIRED.ABORTED_MISC5", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.", + "EventCode": "0xc9", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "RTM_RETIRED.START", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times we entered an RTM region; does not count nested transactions", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Number of times RTM commit succeeded.", + "EventCode": "0xc9", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "RTM_RETIRED.COMMIT", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times RTM commit succeeded", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "PublicDescription": "Number of times RTM abort was triggered .", + "EventCode": "0xc9", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "RTM_RETIRED.ABORTED", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times RTM abort was triggered", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).", + "EventCode": "0xc9", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "RTM_RETIRED.ABORTED_MISC1", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.", + "EventCode": "0xc9", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "RTM_RETIRED.ABORTED_MISC2", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Number of times a disallowed operation caused an RTM abort.", + "EventCode": "0xc9", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "RTM_RETIRED.ABORTED_MISC3", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Number of times a RTM caused a fault.", + "EventCode": "0xc9", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "RTM_RETIRED.ABORTED_MISC4", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.", + "EventCode": "0xc9", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "RTM_RETIRED.ABORTED_MISC5", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "2", + "PublicDescription": "This event counts loads with latency value being above four.", + "EventCode": "0xCD", + "MSRValue": "0x4", + "Counter": "3", + "UMask": "0x1", + "Errata": "BDM100, BDM35", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "SampleAfterValue": "100003", + "BriefDescription": "Loads with latency value being above 4", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "PublicDescription": "This event counts loads with latency value being above eight.", + "EventCode": "0xCD", + "MSRValue": "0x8", + "Counter": "3", + "UMask": "0x1", + "Errata": "BDM100, BDM35", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "MSRIndex": "0x3F6", + "SampleAfterValue": "50021", + "BriefDescription": "Loads with latency value being above 8", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "PublicDescription": "This event counts loads with latency value being above 16.", + "EventCode": "0xCD", + "MSRValue": "0x10", + "Counter": "3", + "UMask": "0x1", + "Errata": "BDM100, BDM35", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "MSRIndex": "0x3F6", + "SampleAfterValue": "20011", + "BriefDescription": "Loads with latency value being above 16", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "PublicDescription": "This event counts loads with latency value being above 32.", + "EventCode": "0xCD", + "MSRValue": "0x20", + "Counter": "3", + "UMask": "0x1", + "Errata": "BDM100, BDM35", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "MSRIndex": "0x3F6", + "SampleAfterValue": "100007", + "BriefDescription": "Loads with latency value being above 32", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "PublicDescription": "This event counts loads with latency value being above 64.", + "EventCode": "0xCD", + "MSRValue": "0x40", + "Counter": "3", + "UMask": "0x1", + "Errata": "BDM100, BDM35", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "MSRIndex": "0x3F6", + "SampleAfterValue": "2003", + "BriefDescription": "Loads with latency value being above 64", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "PublicDescription": "This event counts loads with latency value being above 128.", + "EventCode": "0xCD", + "MSRValue": "0x80", + "Counter": "3", + "UMask": "0x1", + "Errata": "BDM100, BDM35", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "MSRIndex": "0x3F6", + "SampleAfterValue": "1009", + "BriefDescription": "Loads with latency value being above 128", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "PublicDescription": "This event counts loads with latency value being above 256.", + "EventCode": "0xCD", + "MSRValue": "0x100", + "Counter": "3", + "UMask": "0x1", + "Errata": "BDM100, BDM35", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "MSRIndex": "0x3F6", + "SampleAfterValue": "503", + "BriefDescription": "Loads with latency value being above 256", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "PublicDescription": "This event counts loads with latency value being above 512.", + "EventCode": "0xCD", + "MSRValue": "0x200", + "Counter": "3", + "UMask": "0x1", + "Errata": "BDM100, BDM35", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "MSRIndex": "0x3F6", + "SampleAfterValue": "101", + "BriefDescription": "Loads with latency value being above 512", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2000020001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & SNOOP_NON_DRAM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x20003c0001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that hit in the L3 and the target was non-DRAM system address.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0084000001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0104000001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0204000001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0404000001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": 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"0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f84000001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00bc000001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that miss the L3 with no details on snoop-related information.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x013c000001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L3_MISS & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x023c000001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that miss the L3 with a snoop miss response.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x043c000001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L3_MISS & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x20003c0002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the target was non-DRAM system address.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f84000002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & L3_MISS_LOCAL_DRAM & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00bc000002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 with no details on snoop-related information.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x013c000002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & L3_MISS & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x023c000002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 with a snoop miss response.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x043c000002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & L3_MISS & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2000020004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & SUPPLIER_NONE & SNOOP_NON_DRAM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x20003c0004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand code reads that hit in the L3 and the target was non-DRAM system address.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0084000004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0104000004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0204000004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0404000004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1004000004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2004000004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_NON_DRAM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f84000004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00bc000004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand code reads that miss the L3 with no details on snoop-related information.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x013c000004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L3_MISS & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x023c000004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand code reads that miss the L3 with a snoop miss response.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x043c000004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L3_MISS & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2000020008 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "COREWB & SUPPLIER_NONE & SNOOP_NON_DRAM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x20003c0008 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts writebacks (modified to exclusive) that hit in the L3 and the target was non-DRAM system address.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0084000008 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "COREWB & L3_MISS_LOCAL_DRAM & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0104000008 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "COREWB & L3_MISS_LOCAL_DRAM & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0204000008 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "COREWB & L3_MISS_LOCAL_DRAM & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0404000008 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "COREWB & L3_MISS_LOCAL_DRAM & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1004000008 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "COREWB & L3_MISS_LOCAL_DRAM & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2004000008 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "COREWB & L3_MISS_LOCAL_DRAM & SNOOP_NON_DRAM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f84000008 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "COREWB & L3_MISS_LOCAL_DRAM & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00bc000008 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts writebacks (modified to exclusive) that miss the L3 with no details on snoop-related information.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x013c000008 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "COREWB & L3_MISS & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x023c000008 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts writebacks (modified to exclusive) that miss the L3 with a snoop miss response.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x043c000008 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "COREWB & L3_MISS & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2000020010 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_DATA_RD & SUPPLIER_NONE & SNOOP_NON_DRAM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x20003c0010 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 and the target was non-DRAM system address.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0084000010 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0104000010 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0204000010 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0404000010 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1004000010 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2004000010 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NON_DRAM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f84000010 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_DATA_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00bc000010 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 with no details on snoop-related information.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x013c000010 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_DATA_RD & L3_MISS & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x023c000010 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 with a snoop miss response.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x043c000010 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_DATA_RD & L3_MISS & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2000020020 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_RFO & SUPPLIER_NONE & SNOOP_NON_DRAM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x20003c0020 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the target was non-DRAM system address.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0084000020 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_RFO & L3_MISS_LOCAL_DRAM & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0104000020 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_RFO & L3_MISS_LOCAL_DRAM & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0204000020 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_RFO & L3_MISS_LOCAL_DRAM & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0404000020 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_RFO & L3_MISS_LOCAL_DRAM & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1004000020 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_RFO & L3_MISS_LOCAL_DRAM & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2004000020 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_RFO & L3_MISS_LOCAL_DRAM & SNOOP_NON_DRAM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f84000020 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_RFO & L3_MISS_LOCAL_DRAM & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00bc000020 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 with no details on snoop-related information.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x013c000020 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_RFO & L3_MISS & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x023c000020 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 with a snoop miss response.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x043c000020 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_RFO & L3_MISS & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2000020040 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_CODE_RD & SUPPLIER_NONE & SNOOP_NON_DRAM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x20003c0040 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 and the target was non-DRAM system address.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0084000040 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0104000040 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0204000040 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0404000040 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1004000040 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2004000040 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_NON_DRAM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f84000040 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_CODE_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00bc000040 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss the L3 with no details on snoop-related information.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x013c000040 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_CODE_RD & L3_MISS & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x023c000040 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss the L3 with a snoop miss response.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x043c000040 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L2_CODE_RD & L3_MISS & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2000020080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & SUPPLIER_NONE & SNOOP_NON_DRAM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x20003c0080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the target was non-DRAM system address.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0084000080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0104000080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0204000080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0404000080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1004000080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2004000080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NON_DRAM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f84000080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00bc000080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 with no details on snoop-related information.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x013c000080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L3_MISS & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x023c000080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 with a snoop miss response.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x043c000080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L3_MISS & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2000020100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & SUPPLIER_NONE & SNOOP_NON_DRAM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x20003c0100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the target was non-DRAM system address.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0084000100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L3_MISS_LOCAL_DRAM & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0104000100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L3_MISS_LOCAL_DRAM & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0204000100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L3_MISS_LOCAL_DRAM & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0404000100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L3_MISS_LOCAL_DRAM & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1004000100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L3_MISS_LOCAL_DRAM & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2004000100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L3_MISS_LOCAL_DRAM & SNOOP_NON_DRAM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f84000100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L3_MISS_LOCAL_DRAM & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00bc000100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 with no details on snoop-related information.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x013c000100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L3_MISS & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x023c000100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 with a snoop miss response.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x043c000100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L3_MISS & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2000020200 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_CODE_RD & SUPPLIER_NONE & SNOOP_NON_DRAM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x20003c0200 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3 and the target was non-DRAM system address.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0084000200 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0104000200 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0204000200 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0404000200 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1004000200 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2004000200 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_NON_DRAM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f84000200 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_CODE_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00bc000200 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that miss the L3 with no details on snoop-related information.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x013c000200 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_CODE_RD & L3_MISS & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x023c000200 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that miss the L3 with a snoop miss response.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x043c000200 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_CODE_RD & L3_MISS & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": 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"SampleAfterValue": "100003", + "BriefDescription": "ALL_PF_DATA_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00bc000090 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch data reads that miss the L3 with no details on snoop-related information.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x013c000090 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_PF_DATA_RD & L3_MISS & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x023c000090 ", + "Counter": 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"1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x20003c0120 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch RFOs that hit in the L3 and the target was non-DRAM system address.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0084000120 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_PF_RFO & L3_MISS_LOCAL_DRAM & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0104000120 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", + "MSRIndex": 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"0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_PF_RFO & L3_MISS_LOCAL_DRAM & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2004000120 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_PF_RFO & L3_MISS_LOCAL_DRAM & SNOOP_NON_DRAM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f84000120 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_PF_RFO & L3_MISS_LOCAL_DRAM & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00bc000120 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch RFOs that miss the L3 with no details on snoop-related information.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x013c000120 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_PF_RFO & L3_MISS & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x023c000120 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch RFOs that miss the L3 with a snoop miss response.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x043c000120 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_PF_RFO & L3_MISS & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2000020240 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_PF_CODE_RD & SUPPLIER_NONE & SNOOP_NON_DRAM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x20003c0240 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": 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"MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_PF_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2004000240 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_PF_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_NON_DRAM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f84000240 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_PF_CODE_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00bc000240 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch code reads that miss the L3 with no details on snoop-related information.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x013c000240 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_PF_CODE_RD & L3_MISS & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x023c000240 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch code reads that miss the L3 with a snoop miss response.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x043c000240 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_PF_CODE_RD & L3_MISS & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2000020091 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_DATA_RD & SUPPLIER_NONE & SNOOP_NON_DRAM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x20003c0091 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the target was non-DRAM system address.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0084000091 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0104000091 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0204000091 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0404000091 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1004000091 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2004000091 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NON_DRAM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f84000091 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_DATA_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00bc000091 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 with no details on snoop-related information.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x013c000091 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_DATA_RD & L3_MISS & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x023c000091 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 with a snoop miss response.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x043c000091 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_DATA_RD & L3_MISS & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2000020122 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_RFO & SUPPLIER_NONE & SNOOP_NON_DRAM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x20003c0122 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the target was non-DRAM system address.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0084000122 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_RFO & L3_MISS_LOCAL_DRAM & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0104000122 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_RFO & L3_MISS_LOCAL_DRAM & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0204000122 ", + "Counter": "0,1,2,3", + "UMask": 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"EventCode": "0xB7, 0xBB", + "MSRValue": "0x2004000122 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_RFO & L3_MISS_LOCAL_DRAM & SNOOP_NON_DRAM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f84000122 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_RFO & L3_MISS_LOCAL_DRAM & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00bc000122 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 with no details on snoop-related information.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x013c000122 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_RFO & L3_MISS & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x023c000122 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 with a snoop miss response.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x043c000122 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "ALL_RFO & L3_MISS & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwell/other.json b/tools/perf/pmu-events/arch/x86/broadwell/other.json new file mode 100644 index 000000000000..edf14f0d0eaf --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/broadwell/other.json @@ -0,0 +1,44 @@ +[ + { + "PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.", + "EventCode": "0x5C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CPL_CYCLES.RING0", + "SampleAfterValue": "2000003", + "BriefDescription": "Unhalted core cycles when the thread is in ring 0", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.", + "EventCode": "0x5C", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "CPL_CYCLES.RING123", + "SampleAfterValue": "2000003", + "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.", + "EventCode": "0x5C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EdgeDetect": "1", + "EventName": "CPL_CYCLES.RING0_TRANS", + "SampleAfterValue": "100007", + "BriefDescription": "Number of intervals between processor halts while thread is in ring 0", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.", + "EventCode": "0x63", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwell/pipeline.json b/tools/perf/pmu-events/arch/x86/broadwell/pipeline.json new file mode 100644 index 000000000000..78913ae87703 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/broadwell/pipeline.json @@ -0,0 +1,1417 @@ +[ + { + "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. \nNotes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. \nCounting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.", + "EventCode": "0x00", + "Counter": "Fixed counter 1", + "UMask": "0x1", + "EventName": "INST_RETIRED.ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Instructions retired from execution.", + "CounterHTOff": "Fixed counter 1" + }, + { + "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.", + "EventCode": "0x00", + "Counter": "Fixed counter 2", + "UMask": "0x2", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "SampleAfterValue": "2000003", + "BriefDescription": "Core cycles when the thread is not in halt state", + "CounterHTOff": "Fixed counter 2" + }, + { + "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. \nNote: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", + "EventCode": "0x00", + "Counter": "Fixed counter 3", + "UMask": "0x3", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "SampleAfterValue": "2000003", + "BriefDescription": "Reference cycles when the core is not in halt state.", + "CounterHTOff": "Fixed counter 3" + }, + { + "PublicDescription": "This event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:\n - preceding store conflicts with the load (incomplete overlap);\n - store forwarding is impossible due to u-arch limitations;\n - preceding lock RMW operations are not forwarded;\n - store has the no-forward bit set (uncacheable/page-split/masked stores);\n - all-blocking stores are used (mostly, fences and port I/O);\nand others.\nThe most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events.\nSee the table of not supported store forwards in the Optimization Guide.", + "EventCode": "0x03", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "SampleAfterValue": "100003", + "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x03", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "LD_BLOCKS.NO_SR", + "SampleAfterValue": "100003", + "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.", + "EventCode": "0x07", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "SampleAfterValue": "100003", + "BriefDescription": "False dependencies in MOB due to partial compare", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of cycles during which Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the current thread. This also includes the cycles during which the Allocator is serving another thread.", + "EventCode": "0x0D", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "INT_MISC.RAT_STALL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles checkpoints in Resource Allocation Table (RAT) are recovering from JEClear or machine clear.", + "EventCode": "0x0D", + "Counter": "0,1,2,3", + "UMask": "0x3", + "EventName": "INT_MISC.RECOVERY_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS).", + "EventCode": "0x0E", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_ISSUED.ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive\n added by GSR u-arch.", + "EventCode": "0x0E", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "UOPS_ISSUED.FLAGS_MERGE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0E", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "UOPS_ISSUED.SLOW_LEA", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0E", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "UOPS_ISSUED.SINGLE_MUL", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.", + "EventCode": "0x0E", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "This event counts the number of the divide operations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DIV_ACTIVE to get the number of the divide operations executed.", + "EventCode": "0x14", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ARITH.FPU_DIV_ACTIVE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when divider is busy executing divide operations", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This is a fixed-frequency event programmed to general counters. It counts when the core is unhalted at 100 Mhz.", + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", + "SampleAfterValue": "2000003", + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3c", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "2000003", + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by asm inspection of the nearby instructions.", + "EventCode": "0x4c", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LOAD_HIT_PRE.SW_PF", + "SampleAfterValue": "100003", + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the hardware prefetch.", + "EventCode": "0x4C", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "LOAD_HIT_PRE.HW_PF", + "SampleAfterValue": "100003", + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x58", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", + "SampleAfterValue": "1000003", + "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x58", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", + "SampleAfterValue": "1000003", + "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x58", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", + "SampleAfterValue": "1000003", + "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x58", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", + "SampleAfterValue": "1000003", + "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts cycles during which the reservation station (RS) is empty for the thread.\nNote: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.", + "EventCode": "0x5E", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "RS_EVENTS.EMPTY_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", + "EventCode": "0x87", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ILD_STALL.LCP", + "SampleAfterValue": "2000003", + "BriefDescription": "Stalls caused by changing prefix length of the instruction.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts not taken macro-conditional branch instructions.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x41", + "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Not taken macro-conditional branches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x81", + "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired macro-conditional branches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions excluding calls and indirect branches.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x82", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts taken speculative and retired indirect branches excluding calls and return branches.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x84", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts taken speculative and retired indirect branches that have a return mnemonic.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts taken speculative and retired direct near calls.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x90", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired direct near calls", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts taken speculative and retired indirect calls including both register and memory indirect.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xa0", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired indirect calls", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts both taken and not taken speculative and retired macro-conditional branch instructions.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xc1", + "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired macro-conditional branches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts both taken and not taken speculative and retired macro-unconditional branch instructions, excluding calls and indirects.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xc2", + "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches excluding calls and return branches.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xc4", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired indirect branches excluding calls and returns", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches that have a return mnemonic.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xc8", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired indirect return branches.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts both taken and not taken speculative and retired direct near calls.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xd0", + "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired direct near calls", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts both taken and not taken speculative and retired branch instructions.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xff", + "EventName": "BR_INST_EXEC.ALL_BRANCHES", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired branches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts not taken speculative and retired mispredicted macro conditional branch instructions.", + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x41", + "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts taken speculative and retired mispredicted macro conditional branch instructions.", + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x81", + "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches excluding calls and returns.", + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x84", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches that have a return mnemonic.", + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x88", + "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted macro conditional branch instructions.", + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0xc1", + "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired mispredicted macro conditional branches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts both taken and not taken mispredicted indirect branches excluding calls and returns.", + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0xc4", + "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "BriefDescription": "Mispredicted indirect branches excluding calls and returns", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted branch instructions.", + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0xff", + "EventName": "BR_MISP_EXEC.ALL_BRANCHES", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired mispredicted macro conditional branches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are executed in port 0", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are executed in port 1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are executed in port 2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are executed in port 3", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are executed in port 4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are executed in port 5", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "UOPS_DISPATCHED_PORT.PORT_6", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are executed in port 6", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "UOPS_DISPATCHED_PORT.PORT_7", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are executed in port 7", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts resource-related stall cycles. Reasons for stalls can be as follows:\n - *any* u-arch structure got full (LB, SB, RS, ROB, BOB, LM, Physical Register Reclaim Table (PRRT), or Physical History Table (PHT) slots)\n - *any* u-arch structure got empty (like INT/SIMD FreeLists)\n - FPU control word (FPCW), MXCSR\nand others. This counts cycles that the pipeline backend blocked uop delivery from the front end.", + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "RESOURCE_STALLS.ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Resource-related stall cycles", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts stall cycles caused by absence of eligible entries in the reservation station (RS). This may result from RS overflow, or from RS deallocation because of the RS array Write Port allocation scheme (each RS entry has two write ports instead of four. As a result, empty entries could not be used, although RS is not really full). This counts cycles that the pipeline backend blocked uop delivery from the front end.", + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "RESOURCE_STALLS.RS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles stalled due to no eligible RS entry available.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front end.", + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "RESOURCE_STALLS.SB", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts ROB full stall cycles. This counts cycles that the pipeline backend blocked uop delivery from the front end.", + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "RESOURCE_STALLS.ROB", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles stalled due to re-order buffer full.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts number of cycles the CPU has at least one pending demand* load request missing the L2 cache.", + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts number of cycles the CPU has at least one pending demand load request missing the L1 data cache.", + "EventCode": "0xA3", + "Counter": "2", + "UMask": "0x8", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", + "CounterMask": "8", + "CounterHTOff": "2" + }, + { + "PublicDescription": "Counts number of cycles the CPU has at least one pending demand load request (that is cycles with non-completed load waiting for its data from memory subsystem).", + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles while memory subsystem has an outstanding load.", + "CounterMask": "2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts number of cycles nothing is executed on any execution port.", + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", + "SampleAfterValue": "2000003", + "BriefDescription": "Total execution stalls", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand* load request missing the L2 cache.(as a footprint) * includes also L1 HW prefetch requests that may or may not be required by demands.", + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x5", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", + "CounterMask": "5", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request.", + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x6", + "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", + "CounterMask": "6", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request missing the L1 data cache.", + "EventCode": "0xA3", + "Counter": "2", + "UMask": "0xc", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "CounterMask": "12", + "CounterHTOff": "2" + }, + { + "PublicDescription": "Number of Uops delivered by the LSD. ", + "EventCode": "0xA8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LSD.UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of Uops delivered by the LSD.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of uops to be executed per-thread each cycle.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_EXECUTED.THREAD", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of uops executed from any thread.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of uops executed on the core.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.", + "EventCode": "0xB1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_EXECUTED.STALL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "This event counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two).", + "EventCode": "0xC0", + "Counter": "0,1,2,3", + "UMask": "0x0", + "Errata": "BDM61", + "EventName": "INST_RETIRED.ANY_P", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of instructions retired. General Counter - architectural event", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.", + "EventCode": "0xC0", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "INST_RETIRED.X87", + "SampleAfterValue": "2000003", + "BriefDescription": "FP operations retired. X87 FP operations that have no exceptions:", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "2", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts instructions retired.", + "EventCode": "0xC0", + "Counter": "1", + "UMask": "0x1", + "Errata": "BDM11, BDM55", + "EventName": "INST_RETIRED.PREC_DIST", + "SampleAfterValue": "2000003", + "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution", + "CounterHTOff": "1" + }, + { + "EventCode": "0xC1", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", + "SampleAfterValue": "100003", + "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "PublicDescription": "This event counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight.", + "EventCode": "0xC2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.ALL", + "SampleAfterValue": "2000003", + "BriefDescription": "Actually retired uops.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Data_LA": "1" + }, + { + "PEBS": "1", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts the number of retirement slots used.", + "EventCode": "0xC2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "SampleAfterValue": "2000003", + "BriefDescription": "Retirement slots used.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts cycles without actually retired uops.", + "EventCode": "0xC2", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles without actually retired uops.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.", + "EventCode": "0xC2", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with less than 10 actually retired uops.", + "CounterMask": "10", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "This event counts both thread-specific (TS) and all-thread (AT) nukes.", + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MACHINE_CLEARS.CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts self-modifying code (SMC) detected, which causes a machine clear.", + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "MACHINE_CLEARS.SMC", + "SampleAfterValue": "100003", + "BriefDescription": "Self-modifying code (SMC) detected.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.", + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "MACHINE_CLEARS.MASKMOV", + "SampleAfterValue": "100003", + "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts conditional branch instructions retired.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BR_INST_RETIRED.CONDITIONAL", + "SampleAfterValue": "400009", + "BriefDescription": "Conditional branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts both direct and indirect near call instructions retired.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "SampleAfterValue": "100007", + "BriefDescription": "Direct and indirect near call instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts all (macro) branch instructions retired.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "SampleAfterValue": "400009", + "BriefDescription": "All (macro) branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts return instructions retired.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "SampleAfterValue": "100007", + "BriefDescription": "Return instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts not taken branch instructions retired.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "BR_INST_RETIRED.NOT_TAKEN", + "SampleAfterValue": "400009", + "BriefDescription": "Not taken branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts taken branch instructions retired.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "SampleAfterValue": "400009", + "BriefDescription": "Taken branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts far branch instructions retired.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x40", + "Errata": "BDW98", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "SampleAfterValue": "100007", + "BriefDescription": "Far branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "2", + "PublicDescription": "This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x4", + "Errata": "BDW98", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", + "SampleAfterValue": "400009", + "BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS)", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted conditional branch instructions retired.", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BR_MISP_RETIRED.CONDITIONAL", + "SampleAfterValue": "400009", + "BriefDescription": "Mispredicted conditional branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts all mispredicted macro branch instructions retired.", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "SampleAfterValue": "400009", + "BriefDescription": "All mispredicted macro branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired.", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "BR_MISP_RETIRED.RET", + "SampleAfterValue": "100007", + "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "2", + "PublicDescription": "This is a precise version of BR_MISP_RETIRED.ALL_BRANCHES that counts all mispredicted macro branch instructions retired.", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", + "SampleAfterValue": "400009", + "BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "This event counts cases of saving new LBR records by hardware. This assumes proper enabling of LBRs and takes into account LBR filtering done by the LBR_SELECT register.", + "EventCode": "0xCC", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", + "SampleAfterValue": "2000003", + "BriefDescription": "Count cases of saving new LBR", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.", + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "SampleAfterValue": "2000003", + "BriefDescription": "Thread cycles when thread is not in halt state", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0xa0", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired mispredicted indirect calls.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when uops are exectuted in port 0.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when uops are exectuted in port 1.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x4", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when uops are dispatched to port 2.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x8", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when uops are dispatched to port 3.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x10", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when uops are exectuted in port 4.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x20", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when uops are exectuted in port 5.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x40", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when uops are exectuted in port 6.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x80", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when uops are dispatched to port 7.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "PublicDescription": "Number of near branch instructions retired that were mispredicted and taken.", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "SampleAfterValue": "400009", + "BriefDescription": "number of near branch instructions retired that were mispredicted and taken.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles where at least 1 uop was executed per-thread.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles where at least 2 uops were executed per-thread.", + "CounterMask": "2", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles where at least 3 uops were executed per-thread.", + "CounterMask": "3", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles where at least 4 uops were executed per-thread.", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xe6", + "Counter": "0,1,2,3", + "UMask": "0x1f", + "EventName": "BACLEARS.ANY", + "SampleAfterValue": "100003", + "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA3", + "Counter": "2", + "UMask": "0x8", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", + "CounterMask": "8", + "CounterHTOff": "2" + }, + { + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles while memory subsystem has an outstanding load.", + "CounterMask": "2", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", + "SampleAfterValue": "2000003", + "BriefDescription": "Total execution stalls.", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA3", + "Counter": "2", + "UMask": "0xc", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", + "SampleAfterValue": "2000003", + "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "CounterMask": "12", + "CounterHTOff": "2" + }, + { + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x5", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", + "SampleAfterValue": "2000003", + "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", + "CounterMask": "5", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x6", + "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", + "CounterMask": "6", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EdgeDetect": "1", + "EventName": "MACHINE_CLEARS.COUNT", + "SampleAfterValue": "100003", + "BriefDescription": "Number of machine clears (nukes) of any type.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LSD.CYCLES_4_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5E", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EdgeDetect": "1", + "EventName": "RS_EVENTS.EMPTY_END", + "SampleAfterValue": "200003", + "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LSD.CYCLES_ACTIVE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_EXECUTED_PORT.PORT_0", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are executed in port 0", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED_PORT.PORT_1", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are executed in port 1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "UOPS_EXECUTED_PORT.PORT_2", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are executed in port 2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "UOPS_EXECUTED_PORT.PORT_3", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are executed in port 3", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "UOPS_EXECUTED_PORT.PORT_4", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are executed in port 4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "UOPS_EXECUTED_PORT.PORT_5", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are executed in port 5", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "UOPS_EXECUTED_PORT.PORT_6", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are executed in port 6", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "UOPS_EXECUTED_PORT.PORT_7", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are executed in port 7", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file. The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more information.", + "EventCode": "0xA0", + "Counter": "0,1,2,3", + "UMask": "0x3", + "EventName": "UOP_DISPATCHES_CANCELLED.SIMD_PRF", + "SampleAfterValue": "2000003", + "BriefDescription": "Micro-op dispatches cancelled due to insufficient SIMD physical register file read ports", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x00", + "Counter": "Fixed counter 2", + "UMask": "0x2", + "AnyThread": "1", + "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "CounterHTOff": "Fixed counter 2" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x0", + "AnyThread": "1", + "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0D", + "Counter": "0,1,2,3", + "UMask": "0x3", + "AnyThread": "1", + "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xb1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xb1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", + "CounterMask": "2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xb1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", + "CounterMask": "3", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xb1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xb1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).", + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "SampleAfterValue": "2000003", + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "2000003", + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwell/virtual-memory.json b/tools/perf/pmu-events/arch/x86/broadwell/virtual-memory.json new file mode 100644 index 000000000000..4301e6fbc5eb --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/broadwell/virtual-memory.json @@ -0,0 +1,388 @@ +[ + { + "PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Errata": "BDM69", + "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", + "SampleAfterValue": "100003", + "BriefDescription": "Load misses in all DTLB levels that cause page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x2", + "Errata": "BDM69", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "SampleAfterValue": "2000003", + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x4", + "Errata": "BDM69", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "SampleAfterValue": "2000003", + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x8", + "Errata": "BDM69", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", + "SampleAfterValue": "2000003", + "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.", + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x10", + "Errata": "BDM69", + "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when PMH is busy with page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", + "SampleAfterValue": "2000003", + "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", + "SampleAfterValue": "2000003", + "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Errata": "BDM69", + "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", + "SampleAfterValue": "100003", + "BriefDescription": "Store misses in all DTLB levels that cause page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x2", + "Errata": "BDM69", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "SampleAfterValue": "100003", + "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x4", + "Errata": "BDM69", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "SampleAfterValue": "100003", + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x8", + "Errata": "BDM69", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", + "SampleAfterValue": "100003", + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (1G)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.", + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x10", + "Errata": "BDM69", + "EventName": "DTLB_STORE_MISSES.WALK_DURATION", + "SampleAfterValue": "100003", + "BriefDescription": "Cycles when PMH is busy with page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", + "SampleAfterValue": "100003", + "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", + "SampleAfterValue": "100003", + "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches.", + "EventCode": "0x4F", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "EPT.WALK_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycle count for an Extended Page table walk.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Errata": "BDM69", + "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", + "SampleAfterValue": "100003", + "BriefDescription": "Misses at all ITLB levels that cause page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x2", + "Errata": "BDM69", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "SampleAfterValue": "100003", + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x4", + "Errata": "BDM69", + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "SampleAfterValue": "100003", + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x8", + "Errata": "BDM69", + "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", + "SampleAfterValue": "100003", + "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.", + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x10", + "Errata": "BDM69", + "EventName": "ITLB_MISSES.WALK_DURATION", + "SampleAfterValue": "100003", + "BriefDescription": "Cycles when PMH is busy with page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "ITLB_MISSES.STLB_HIT_4K", + "SampleAfterValue": "100003", + "BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "ITLB_MISSES.STLB_HIT_2M", + "SampleAfterValue": "100003", + "BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).", + "EventCode": "0xAE", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ITLB.ITLB_FLUSH", + "SampleAfterValue": "100007", + "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xBC", + "Counter": "0,1,2,3", + "UMask": "0x11", + "Errata": "BDM69, BDM98", + "EventName": "PAGE_WALKER_LOADS.DTLB_L1", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of DTLB page walker hits in the L1+FB.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBC", + "Counter": "0,1,2,3", + "UMask": "0x21", + "Errata": "BDM69, BDM98", + "EventName": "PAGE_WALKER_LOADS.ITLB_L1", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of ITLB page walker hits in the L1+FB.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBC", + "Counter": "0,1,2,3", + "UMask": "0x12", + "Errata": "BDM69, BDM98", + "EventName": "PAGE_WALKER_LOADS.DTLB_L2", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of DTLB page walker hits in the L2.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBC", + "Counter": "0,1,2,3", + "UMask": "0x22", + "Errata": "BDM69, BDM98", + "EventName": "PAGE_WALKER_LOADS.ITLB_L2", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of ITLB page walker hits in the L2.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBC", + "Counter": "0,1,2,3", + "UMask": "0x14", + "Errata": "BDM69, BDM98", + "EventName": "PAGE_WALKER_LOADS.DTLB_L3", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBC", + "Counter": "0,1,2,3", + "UMask": "0x24", + "Errata": "BDM69, BDM98", + "EventName": "PAGE_WALKER_LOADS.ITLB_L3", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBC", + "Counter": "0,1,2,3", + "UMask": "0x18", + "Errata": "BDM69, BDM98", + "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of DTLB page walker hits in Memory.", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "This event counts the number of DTLB flush attempts of the thread-specific entries.", + "EventCode": "0xBD", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "TLB_FLUSH.DTLB_THREAD", + "SampleAfterValue": "100007", + "BriefDescription": "DTLB flush attempts of the thread-specific entries", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).", + "EventCode": "0xBD", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "TLB_FLUSH.STLB_ANY", + "SampleAfterValue": "100007", + "BriefDescription": "STLB flush attempts", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0xe", + "Errata": "BDM69", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "SampleAfterValue": "100003", + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x60", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "SampleAfterValue": "2000003", + "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0xe", + "Errata": "BDM69", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "SampleAfterValue": "100003", + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x60", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "SampleAfterValue": "100003", + "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0xe", + "Errata": "BDM69", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "SampleAfterValue": "100003", + "BriefDescription": "Misses in all ITLB levels that cause completed page walks.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x60", + "EventName": "ITLB_MISSES.STLB_HIT", + "SampleAfterValue": "100003", + "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/cache.json b/tools/perf/pmu-events/arch/x86/broadwellde/cache.json new file mode 100644 index 000000000000..36fe398029b9 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/broadwellde/cache.json @@ -0,0 +1,774 @@ +[ + { + "EventCode": "0x24", + "UMask": "0x21", + "BriefDescription": "Demand Data Read miss L2, no rejects", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", + "PublicDescription": "This event counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0x41", + "BriefDescription": "Demand Data Read requests that hit L2 cache", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "PublicDescription": "This event counts the number of demand Data Read requests that hit L2 cache. Only not rejected loads are counted.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0x30", + "BriefDescription": "L2 prefetch requests that miss L2 cache", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.L2_PF_MISS", + "PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that miss L2 cache.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0x50", + "BriefDescription": "L2 prefetch requests that hit L2 cache", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.L2_PF_HIT", + "PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0xe1", + "BriefDescription": "Demand Data Read requests", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "PublicDescription": "This event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0xe2", + "BriefDescription": "RFO requests to L2 cache", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.ALL_RFO", + "PublicDescription": "This event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0xe4", + "BriefDescription": "L2 code requests", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "PublicDescription": "This event counts the total number of L2 code requests.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0xf8", + "BriefDescription": "Requests from L2 hardware prefetchers", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.ALL_PF", + "PublicDescription": "This event counts the total number of requests from the L2 hardware prefetchers.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x27", + "UMask": "0x50", + "BriefDescription": "Not rejected writebacks that hit L2 cache", + "Counter": "0,1,2,3", + "EventName": "L2_DEMAND_RQSTS.WB_HIT", + "PublicDescription": "This event counts the number of WB requests that hit L2 cache.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x2E", + "UMask": "0x41", + "BriefDescription": "Core-originated cacheable demand requests missed L3", + "Counter": "0,1,2,3", + "EventName": "LONGEST_LAT_CACHE.MISS", + "PublicDescription": "This event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x2E", + "UMask": "0x4f", + "BriefDescription": "Core-originated cacheable demand requests that refer to L3", + "Counter": "0,1,2,3", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "PublicDescription": "This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x48", + "UMask": "0x1", + "BriefDescription": "L1D miss oustandings duration in cycles", + "Counter": "2", + "EventName": "L1D_PEND_MISS.PENDING", + "PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch.\nNote: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", + "SampleAfterValue": "2000003", + "CounterHTOff": "2" + }, + { + "EventCode": "0x48", + "UMask": "0x1", + "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "2", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", + "CounterMask": "1", + "PublicDescription": "This event counts duration of L1D miss outstanding in cycles.", + "SampleAfterValue": "2000003", + "CounterHTOff": "2" + }, + { + "EventCode": "0x51", + "UMask": "0x1", + "BriefDescription": "L1D data line replacements", + "Counter": "0,1,2,3", + "EventName": "L1D.REPLACEMENT", + "PublicDescription": "This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "UMask": "0x1", + "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "Errata": "BDM76", + "PublicDescription": "This event counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.\nNote: A prefetch promoted to Demand is counted from the promotion point.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "UMask": "0x2", + "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", + "Errata": "BDM76", + "PublicDescription": "This event counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The \"Offcore outstanding\" state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "UMask": "0x4", + "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", + "Errata": "BDM76", + "PublicDescription": "This event counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "UMask": "0x8", + "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "Errata": "BDM76", + "PublicDescription": "This event counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "UMask": "0x1", + "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "CounterMask": "1", + "Errata": "BDM76", + "PublicDescription": "This event counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation).", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "UMask": "0x8", + "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "CounterMask": "1", + "Errata": "BDM76", + "PublicDescription": "This event counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "UMask": "0x4", + "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "CounterMask": "1", + "Errata": "BDM76", + "PublicDescription": "This event counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The \"Offcore outstanding\" state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x63", + "UMask": "0x2", + "BriefDescription": "Cycles when L1D is locked", + "Counter": "0,1,2,3", + "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", + "PublicDescription": "This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB0", + "UMask": "0x1", + "BriefDescription": "Demand Data Read requests sent to uncore", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "PublicDescription": "This event counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB0", + "UMask": "0x2", + "BriefDescription": "Cacheable and noncachaeble code read requests", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "PublicDescription": "This event counts both cacheable and noncachaeble code read requests.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB0", + "UMask": "0x4", + "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "PublicDescription": "This event counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB0", + "UMask": "0x8", + "BriefDescription": "Demand and prefetch data reads", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", + "PublicDescription": "This event counts the demand and prefetch data reads. All Core Data Reads include cacheable \"Demands\" and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xb2", + "UMask": "0x1", + "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", + "PublicDescription": "This event counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.\nNote: Writeback pending FIFO has six entries.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xD0", + "UMask": "0x11", + "BriefDescription": "Retired load uops that miss the STLB.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD0", + "UMask": "0x12", + "BriefDescription": "Retired store uops that miss the STLB.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts store uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.", + "SampleAfterValue": "100003", + "L1_Hit_Indication": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD0", + "UMask": "0x21", + "BriefDescription": "Retired load uops with locked access.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "Errata": "BDM35", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts load uops with locked access retired to the architected path.", + "SampleAfterValue": "100007", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD0", + "UMask": "0x41", + "BriefDescription": "Retired load uops that split across a cacheline boundary.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD0", + "UMask": "0x42", + "BriefDescription": "Retired store uops that split across a cacheline boundary.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "SampleAfterValue": "100003", + "L1_Hit_Indication": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD0", + "UMask": "0x81", + "BriefDescription": "All retired load uops.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "PublicDescription": "This event counts load uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD0", + "UMask": "0x82", + "BriefDescription": "All retired store uops.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "PublicDescription": "This event counts store uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement.", + "SampleAfterValue": "2000003", + "L1_Hit_Indication": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD1", + "UMask": "0x1", + "BriefDescription": "Retired load uops with L1 cache hits as data sources.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were hits in the nearest-level (L1) cache.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD1", + "UMask": "0x2", + "BriefDescription": "Retired load uops with L2 cache hits as data sources.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "Errata": "BDM35", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were hits in the mid-level (L2) cache.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD1", + "UMask": "0x4", + "BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", + "Errata": "BDM100", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required.", + "SampleAfterValue": "50021", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD1", + "UMask": "0x8", + "BriefDescription": "Retired load uops misses in L1 cache as data sources.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD1", + "UMask": "0x10", + "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source.", + "SampleAfterValue": "50021", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD1", + "UMask": "0x20", + "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS", + "Errata": "BDM100, BDE70", + "SampleAfterValue": "100007", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD1", + "UMask": "0x40", + "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD2", + "UMask": "0x1", + "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS", + "Errata": "BDM100", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache.", + "SampleAfterValue": "20011", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD2", + "UMask": "0x2", + "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT", + "Errata": "BDM100", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache.", + "SampleAfterValue": "20011", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD2", + "UMask": "0x4", + "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM", + "Errata": "BDM100", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were HitM responses from a core on same socket (shared L3).", + "SampleAfterValue": "20011", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD2", + "UMask": "0x8", + "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE", + "Errata": "BDM100", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD3", + "UMask": "0x1", + "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", + "Errata": "BDE70, BDM100", + "PublicDescription": "Retired load uop whose Data Source was: local DRAM either Snoop not needed or Snoop Miss (RspI).", + "SampleAfterValue": "100007", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xF0", + "UMask": "0x1", + "BriefDescription": "Demand Data Read requests that access L2 cache", + "Counter": "0,1,2,3", + "EventName": "L2_TRANS.DEMAND_DATA_RD", + "PublicDescription": "This event counts Demand Data Read requests that access L2 cache, including rejects.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF0", + "UMask": "0x2", + "BriefDescription": "RFO requests that access L2 cache", + "Counter": "0,1,2,3", + "EventName": "L2_TRANS.RFO", + "PublicDescription": "This event counts Read for Ownership (RFO) requests that access L2 cache.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF0", + "UMask": "0x4", + "BriefDescription": "L2 cache accesses when fetching instructions", + "Counter": "0,1,2,3", + "EventName": "L2_TRANS.CODE_RD", + "PublicDescription": "This event counts the number of L2 cache accesses when fetching instructions.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF0", + "UMask": "0x8", + "BriefDescription": "L2 or L3 HW prefetches that access L2 cache", + "Counter": "0,1,2,3", + "EventName": "L2_TRANS.ALL_PF", + "PublicDescription": "This event counts L2 or L3 HW prefetches that access L2 cache including rejects.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF0", + "UMask": "0x10", + "BriefDescription": "L1D writebacks that access L2 cache", + "Counter": "0,1,2,3", + "EventName": "L2_TRANS.L1D_WB", + "PublicDescription": "This event counts L1D writebacks that access L2 cache.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF0", + "UMask": "0x20", + "BriefDescription": "L2 fill requests that access L2 cache", + "Counter": "0,1,2,3", + "EventName": "L2_TRANS.L2_FILL", + "PublicDescription": "This event counts L2 fill requests that access L2 cache.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF0", + "UMask": "0x40", + "BriefDescription": "L2 writebacks that access L2 cache", + "Counter": "0,1,2,3", + "EventName": "L2_TRANS.L2_WB", + "PublicDescription": "This event counts L2 writebacks that access L2 cache.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF0", + "UMask": "0x80", + "BriefDescription": "Transactions accessing L2 pipe", + "Counter": "0,1,2,3", + "EventName": "L2_TRANS.ALL_REQUESTS", + "PublicDescription": "This event counts transactions that access the L2 pipe including snoops, pagewalks, and so on.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF1", + "UMask": "0x1", + "BriefDescription": "L2 cache lines in I state filling L2", + "Counter": "0,1,2,3", + "EventName": "L2_LINES_IN.I", + "PublicDescription": "This event counts the number of L2 cache lines in the Invalidate state filling the L2. Counting does not cover rejects.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF1", + "UMask": "0x2", + "BriefDescription": "L2 cache lines in S state filling L2", + "Counter": "0,1,2,3", + "EventName": "L2_LINES_IN.S", + "PublicDescription": "This event counts the number of L2 cache lines in the Shared state filling the L2. Counting does not cover rejects.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF1", + "UMask": "0x4", + "BriefDescription": "L2 cache lines in E state filling L2", + "Counter": "0,1,2,3", + "EventName": "L2_LINES_IN.E", + "PublicDescription": "This event counts the number of L2 cache lines in the Exclusive state filling the L2. Counting does not cover rejects.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF1", + "UMask": "0x7", + "BriefDescription": "L2 cache lines filling L2", + "Counter": "0,1,2,3", + "EventName": "L2_LINES_IN.ALL", + "PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does not cover rejects.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF2", + "UMask": "0x5", + "BriefDescription": "Clean L2 cache lines evicted by demand.", + "Counter": "0,1,2,3", + "EventName": "L2_LINES_OUT.DEMAND_CLEAN", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xf4", + "UMask": "0x10", + "BriefDescription": "Split locks in SQ", + "Counter": "0,1,2,3", + "EventName": "SQ_MISC.SPLIT_LOCK", + "PublicDescription": "This event counts the number of split locks in the super queue.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0x42", + "BriefDescription": "RFO requests that hit L2 cache.", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.RFO_HIT", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0x22", + "BriefDescription": "RFO requests that miss L2 cache.", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.RFO_MISS", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0x44", + "BriefDescription": "L2 cache hits when fetching instructions, code reads.", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.CODE_RD_HIT", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0x24", + "BriefDescription": "L2 cache misses when fetching instructions.", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.CODE_RD_MISS", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0x27", + "BriefDescription": "Demand requests that miss L2 cache.", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.ALL_DEMAND_MISS", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0xe7", + "BriefDescription": "Demand requests to L2 cache.", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0x3f", + "BriefDescription": "All requests that miss L2 cache.", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.MISS", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0xff", + "BriefDescription": "All L2 requests.", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.REFERENCES", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x60", + "UMask": "0x1", + "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", + "CounterMask": "6", + "Errata": "BDM76", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x48", + "UMask": "0x1", + "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", + "Counter": "2", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", + "AnyThread": "1", + "CounterMask": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "2" + }, + { + "EventCode": "0x48", + "UMask": "0x2", + "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", + "Counter": "0,1,2,3", + "EventName": "L1D_PEND_MISS.FB_FULL", + "CounterMask": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/floating-point.json b/tools/perf/pmu-events/arch/x86/broadwellde/floating-point.json new file mode 100644 index 000000000000..4ae1ea24f22f --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/broadwellde/floating-point.json @@ -0,0 +1,171 @@ +[ + { + "EventCode": "0xC1", + "UMask": "0x8", + "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.", + "Counter": "0,1,2,3", + "EventName": "OTHER_ASSISTS.AVX_TO_SSE", + "Errata": "BDM30", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC1", + "UMask": "0x10", + "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.", + "Counter": "0,1,2,3", + "EventName": "OTHER_ASSISTS.SSE_TO_AVX", + "Errata": "BDM30", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC7", + "UMask": "0x1", + "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC7", + "UMask": "0x2", + "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC7", + "UMask": "0x4", + "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC7", + "UMask": "0x8", + "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC7", + "UMask": "0x10", + "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xCA", + "UMask": "0x2", + "BriefDescription": "Number of X87 assists due to output value.", + "Counter": "0,1,2,3", + "EventName": "FP_ASSIST.X87_OUTPUT", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xCA", + "UMask": "0x4", + "BriefDescription": "Number of X87 assists due to input value.", + "Counter": "0,1,2,3", + "EventName": "FP_ASSIST.X87_INPUT", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xCA", + "UMask": "0x8", + "BriefDescription": "Number of SIMD FP assists due to Output values", + "Counter": "0,1,2,3", + "EventName": "FP_ASSIST.SIMD_OUTPUT", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xCA", + "UMask": "0x10", + "BriefDescription": "Number of SIMD FP assists due to input values", + "Counter": "0,1,2,3", + "EventName": "FP_ASSIST.SIMD_INPUT", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xCA", + "UMask": "0x1e", + "BriefDescription": "Cycles with any input/output SSE or FP assist", + "Counter": "0,1,2,3", + "EventName": "FP_ASSIST.ANY", + "CounterMask": "1", + "PublicDescription": "This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xc7", + "UMask": "0x20", + "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC7", + "UMask": "0x3", + "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "Counter": "0,1,2,3", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC7", + "UMask": "0x3c", + "BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "Counter": "0,1,2,3", + "EventName": "FP_ARITH_INST_RETIRED.PACKED", + "SampleAfterValue": "2000004", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC7", + "UMask": "0x2a", + "BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.", + "Counter": "0,1,2,3", + "EventName": "FP_ARITH_INST_RETIRED.SINGLE", + "SampleAfterValue": "2000005", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC7", + "UMask": "0x15", + "BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.", + "Counter": "0,1,2,3", + "EventName": "FP_ARITH_INST_RETIRED.DOUBLE", + "SampleAfterValue": "2000006", + "CounterHTOff": "0,1,2,3" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/frontend.json b/tools/perf/pmu-events/arch/x86/broadwellde/frontend.json new file mode 100644 index 000000000000..06bf0a40e568 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/broadwellde/frontend.json @@ -0,0 +1,286 @@ +[ + { + "EventCode": "0x79", + "UMask": "0x2", + "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", + "Counter": "0,1,2,3", + "EventName": "IDQ.EMPTY", + "PublicDescription": "This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x79", + "UMask": "0x4", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "Counter": "0,1,2,3", + "EventName": "IDQ.MITE_UOPS", + "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may \"bypass\" the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "UMask": "0x8", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", + "EventName": "IDQ.DSB_UOPS", + "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may \"bypass\" the IDQ.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "UMask": "0x10", + "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "EventName": "IDQ.MS_DSB_UOPS", + "PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may \"bypass\" the IDQ.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "UMask": "0x20", + "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "EventName": "IDQ.MS_MITE_UOPS", + "PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may \"bypass\" the IDQ.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "UMask": "0x30", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "EventName": "IDQ.MS_UOPS", + "PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may \"bypass\" the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "UMask": "0x30", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "EventName": "IDQ.MS_CYCLES", + "CounterMask": "1", + "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may \"bypass\" the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "UMask": "0x4", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path", + "Counter": "0,1,2,3", + "EventName": "IDQ.MITE_CYCLES", + "CounterMask": "1", + "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may \"bypass\" the IDQ.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "UMask": "0x8", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", + "EventName": "IDQ.DSB_CYCLES", + "CounterMask": "1", + "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may \"bypass\" the IDQ.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "UMask": "0x10", + "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "EventName": "IDQ.MS_DSB_CYCLES", + "CounterMask": "1", + "PublicDescription": "This event counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may \"bypass\" the IDQ.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EdgeDetect": "1", + "EventCode": "0x79", + "UMask": "0x10", + "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "EventName": "IDQ.MS_DSB_OCCUR", + "CounterMask": "1", + "PublicDescription": "This event counts the number of deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) is busy. Counting includes uops that may \"bypass\" the IDQ.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "UMask": "0x18", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", + "Counter": "0,1,2,3", + "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", + "CounterMask": "4", + "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may \"bypass\" the IDQ.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "UMask": "0x18", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", + "Counter": "0,1,2,3", + "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", + "CounterMask": "1", + "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may \"bypass\" the IDQ.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "UMask": "0x24", + "BriefDescription": "Cycles MITE is delivering 4 Uops", + "Counter": "0,1,2,3", + "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", + "CounterMask": "4", + "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may \"bypass\" the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "UMask": "0x24", + "BriefDescription": "Cycles MITE is delivering any Uop", + "Counter": "0,1,2,3", + "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", + "CounterMask": "1", + "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may \"bypass\" the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "UMask": "0x3c", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "Counter": "0,1,2,3", + "EventName": "IDQ.MITE_ALL_UOPS", + "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may \"bypass\" the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x80", + "UMask": "0x1", + "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches", + "Counter": "0,1,2,3", + "EventName": "ICACHE.HIT", + "PublicDescription": "This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x80", + "UMask": "0x2", + "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.", + "Counter": "0,1,2,3", + "EventName": "ICACHE.MISSES", + "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x80", + "UMask": "0x4", + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", + "Counter": "0,1,2,3", + "EventName": "ICACHE.IFDATA_STALL", + "PublicDescription": "This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x9C", + "UMask": "0x1", + "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled", + "Counter": "0,1,2,3", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "PublicDescription": "This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding ?4 ? x? when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); \n c. Instruction Decode Queue (IDQ) delivers four uops.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "UMask": "0x1", + "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled", + "Counter": "0,1,2,3", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "CounterMask": "4", + "PublicDescription": "This event counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "UMask": "0x1", + "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled", + "Counter": "0,1,2,3", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", + "CounterMask": "3", + "PublicDescription": "This event counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >=3.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "UMask": "0x1", + "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", + "Counter": "0,1,2,3", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", + "CounterMask": "2", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "UMask": "0x1", + "BriefDescription": "Cycles with less than 3 uops delivered by the front end.", + "Counter": "0,1,2,3", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", + "CounterMask": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "Invert": "1", + "EventCode": "0x9C", + "UMask": "0x1", + "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.", + "Counter": "0,1,2,3", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "CounterMask": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xAB", + "UMask": "0x2", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", + "Counter": "0,1,2,3", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 0?2 cycles.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EdgeDetect": "1", + "EventCode": "0x79", + "UMask": "0x30", + "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "Counter": "0,1,2,3", + "EventName": "IDQ.MS_SWITCHES", + "CounterMask": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/memory.json b/tools/perf/pmu-events/arch/x86/broadwellde/memory.json new file mode 100644 index 000000000000..cfa1e5876ec3 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/broadwellde/memory.json @@ -0,0 +1,433 @@ +[ + { + "EventCode": "0x05", + "UMask": "0x1", + "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", + "Counter": "0,1,2,3", + "EventName": "MISALIGN_MEM_REF.LOADS", + "PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x05", + "UMask": "0x2", + "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", + "Counter": "0,1,2,3", + "EventName": "MISALIGN_MEM_REF.STORES", + "PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x54", + "UMask": "0x1", + "BriefDescription": "Number of times a TSX line had a cache conflict", + "Counter": "0,1,2,3", + "EventName": "TX_MEM.ABORT_CONFLICT", + "PublicDescription": "Number of times a TSX line had a cache conflict.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x54", + "UMask": "0x2", + "BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow", + "Counter": "0,1,2,3", + "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", + "PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x54", + "UMask": "0x4", + "BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock", + "Counter": "0,1,2,3", + "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", + "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x54", + "UMask": "0x8", + "BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty", + "Counter": "0,1,2,3", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", + "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x54", + "UMask": "0x10", + "BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch", + "Counter": "0,1,2,3", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", + "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x54", + "UMask": "0x20", + "BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer", + "Counter": "0,1,2,3", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", + "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x54", + "UMask": "0x40", + "BriefDescription": "Number of times we could not allocate Lock Buffer", + "Counter": "0,1,2,3", + "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", + "PublicDescription": "Number of times we could not allocate Lock Buffer.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5d", + "UMask": "0x1", + "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", + "Counter": "0,1,2,3", + "EventName": "TX_EXEC.MISC1", + "PublicDescription": "Unfriendly TSX abort triggered by a flowmarker.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5d", + "UMask": "0x2", + "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", + "Counter": "0,1,2,3", + "EventName": "TX_EXEC.MISC2", + "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5d", + "UMask": "0x4", + "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", + "Counter": "0,1,2,3", + "EventName": "TX_EXEC.MISC3", + "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5d", + "UMask": "0x8", + "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", + "Counter": "0,1,2,3", + "EventName": "TX_EXEC.MISC4", + "PublicDescription": "RTM region detected inside HLE.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5d", + "UMask": "0x10", + "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", + "Counter": "0,1,2,3", + "EventName": "TX_EXEC.MISC5", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC3", + "UMask": "0x2", + "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", + "Counter": "0,1,2,3", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xc8", + "UMask": "0x1", + "BriefDescription": "Number of times we entered an HLE region; does not count nested transactions", + "Counter": "0,1,2,3", + "EventName": "HLE_RETIRED.START", + "PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xc8", + "UMask": "0x2", + "BriefDescription": "Number of times HLE commit succeeded", + "Counter": "0,1,2,3", + "EventName": "HLE_RETIRED.COMMIT", + "PublicDescription": "Number of times HLE commit succeeded.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xc8", + "UMask": "0x4", + "BriefDescription": "Number of times HLE abort was triggered", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "HLE_RETIRED.ABORTED", + "PublicDescription": "Number of times HLE abort was triggered.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xc8", + "UMask": "0x8", + "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", + "Counter": "0,1,2,3", + "EventName": "HLE_RETIRED.ABORTED_MISC1", + "PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xc8", + "UMask": "0x10", + "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions", + "Counter": "0,1,2,3", + "EventName": "HLE_RETIRED.ABORTED_MISC2", + "PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xc8", + "UMask": "0x20", + "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions", + "Counter": "0,1,2,3", + "EventName": "HLE_RETIRED.ABORTED_MISC3", + "PublicDescription": "Number of times a disallowed operation caused an HLE abort.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xc8", + "UMask": "0x40", + "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", + "Counter": "0,1,2,3", + "EventName": "HLE_RETIRED.ABORTED_MISC4", + "PublicDescription": "Number of times HLE caused a fault.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xc8", + "UMask": "0x80", + "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)", + "Counter": "0,1,2,3", + "EventName": "HLE_RETIRED.ABORTED_MISC5", + "PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xc9", + "UMask": "0x1", + "BriefDescription": "Number of times we entered an RTM region; does not count nested transactions", + "Counter": "0,1,2,3", + "EventName": "RTM_RETIRED.START", + "PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xc9", + "UMask": "0x2", + "BriefDescription": "Number of times RTM commit succeeded", + "Counter": "0,1,2,3", + "EventName": "RTM_RETIRED.COMMIT", + "PublicDescription": "Number of times RTM commit succeeded.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xc9", + "UMask": "0x4", + "BriefDescription": "Number of times RTM abort was triggered", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "RTM_RETIRED.ABORTED", + "PublicDescription": "Number of times RTM abort was triggered .", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xc9", + "UMask": "0x8", + "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", + "Counter": "0,1,2,3", + "EventName": "RTM_RETIRED.ABORTED_MISC1", + "PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xc9", + "UMask": "0x10", + "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).", + "Counter": "0,1,2,3", + "EventName": "RTM_RETIRED.ABORTED_MISC2", + "PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xc9", + "UMask": "0x20", + "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", + "Counter": "0,1,2,3", + "EventName": "RTM_RETIRED.ABORTED_MISC3", + "PublicDescription": "Number of times a disallowed operation caused an RTM abort.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xc9", + "UMask": "0x40", + "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", + "Counter": "0,1,2,3", + "EventName": "RTM_RETIRED.ABORTED_MISC4", + "PublicDescription": "Number of times a RTM caused a fault.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xc9", + "UMask": "0x80", + "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", + "Counter": "0,1,2,3", + "EventName": "RTM_RETIRED.ABORTED_MISC5", + "PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xCD", + "UMask": "0x1", + "BriefDescription": "Loads with latency value being above 4", + "PEBS": "2", + "MSRValue": "0x4", + "Counter": "3", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "Errata": "BDM100, BDM35", + "PublicDescription": "This event counts loads with latency value being above four.", + "TakenAlone": "1", + "SampleAfterValue": "100003", + "CounterHTOff": "3" + }, + { + "EventCode": "0xCD", + "UMask": "0x1", + "BriefDescription": "Loads with latency value being above 8", + "PEBS": "2", + "MSRValue": "0x8", + "Counter": "3", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "MSRIndex": "0x3F6", + "Errata": "BDM100, BDM35", + "PublicDescription": "This event counts loads with latency value being above eight.", + "TakenAlone": "1", + "SampleAfterValue": "50021", + "CounterHTOff": "3" + }, + { + "EventCode": "0xCD", + "UMask": "0x1", + "BriefDescription": "Loads with latency value being above 16", + "PEBS": "2", + "MSRValue": "0x10", + "Counter": "3", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "MSRIndex": "0x3F6", + "Errata": "BDM100, BDM35", + "PublicDescription": "This event counts loads with latency value being above 16.", + "TakenAlone": "1", + "SampleAfterValue": "20011", + "CounterHTOff": "3" + }, + { + "EventCode": "0xCD", + "UMask": "0x1", + "BriefDescription": "Loads with latency value being above 32", + "PEBS": "2", + "MSRValue": "0x20", + "Counter": "3", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "MSRIndex": "0x3F6", + "Errata": "BDM100, BDM35", + "PublicDescription": "This event counts loads with latency value being above 32.", + "TakenAlone": "1", + "SampleAfterValue": "100007", + "CounterHTOff": "3" + }, + { + "EventCode": "0xCD", + "UMask": "0x1", + "BriefDescription": "Loads with latency value being above 64", + "PEBS": "2", + "MSRValue": "0x40", + "Counter": "3", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "MSRIndex": "0x3F6", + "Errata": "BDM100, BDM35", + "PublicDescription": "This event counts loads with latency value being above 64.", + "TakenAlone": "1", + "SampleAfterValue": "2003", + "CounterHTOff": "3" + }, + { + "EventCode": "0xCD", + "UMask": "0x1", + "BriefDescription": "Loads with latency value being above 128", + "PEBS": "2", + "MSRValue": "0x80", + "Counter": "3", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "MSRIndex": "0x3F6", + "Errata": "BDM100, BDM35", + "PublicDescription": "This event counts loads with latency value being above 128.", + "TakenAlone": "1", + "SampleAfterValue": "1009", + "CounterHTOff": "3" + }, + { + "EventCode": "0xCD", + "UMask": "0x1", + "BriefDescription": "Loads with latency value being above 256", + "PEBS": "2", + "MSRValue": "0x100", + "Counter": "3", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "MSRIndex": "0x3F6", + "Errata": "BDM100, BDM35", + "PublicDescription": "This event counts loads with latency value being above 256.", + "TakenAlone": "1", + "SampleAfterValue": "503", + "CounterHTOff": "3" + }, + { + "EventCode": "0xCD", + "UMask": "0x1", + "BriefDescription": "Loads with latency value being above 512", + "PEBS": "2", + "MSRValue": "0x200", + "Counter": "3", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "MSRIndex": "0x3F6", + "Errata": "BDM100, BDM35", + "PublicDescription": "This event counts loads with latency value being above 512.", + "TakenAlone": "1", + "SampleAfterValue": "101", + "CounterHTOff": "3" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/other.json b/tools/perf/pmu-events/arch/x86/broadwellde/other.json new file mode 100644 index 000000000000..718fcb1db2ee --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/broadwellde/other.json @@ -0,0 +1,44 @@ +[ + { + "EventCode": "0x5C", + "UMask": "0x1", + "BriefDescription": "Unhalted core cycles when the thread is in ring 0", + "Counter": "0,1,2,3", + "EventName": "CPL_CYCLES.RING0", + "PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5C", + "UMask": "0x2", + "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", + "Counter": "0,1,2,3", + "EventName": "CPL_CYCLES.RING123", + "PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EdgeDetect": "1", + "EventCode": "0x5C", + "UMask": "0x1", + "BriefDescription": "Number of intervals between processor halts while thread is in ring 0", + "Counter": "0,1,2,3", + "EventName": "CPL_CYCLES.RING0_TRANS", + "CounterMask": "1", + "PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.", + "SampleAfterValue": "100007", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x63", + "UMask": "0x1", + "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", + "Counter": "0,1,2,3", + "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", + "PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/pipeline.json b/tools/perf/pmu-events/arch/x86/broadwellde/pipeline.json new file mode 100644 index 000000000000..02b4e1035f2d --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/broadwellde/pipeline.json @@ -0,0 +1,1417 @@ +[ + { + "EventCode": "0x00", + "UMask": "0x1", + "BriefDescription": "Instructions retired from execution.", + "Counter": "Fixed counter 1", + "EventName": "INST_RETIRED.ANY", + "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. \nNotes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. \nCounting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.", + "SampleAfterValue": "2000003", + "CounterHTOff": "Fixed counter 1" + }, + { + "EventCode": "0x00", + "UMask": "0x2", + "BriefDescription": "Core cycles when the thread is not in halt state", + "Counter": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.", + "SampleAfterValue": "2000003", + "CounterHTOff": "Fixed counter 2" + }, + { + "EventCode": "0x00", + "UMask": "0x3", + "BriefDescription": "Reference cycles when the core is not in halt state.", + "Counter": "Fixed counter 3", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. \nNote: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", + "SampleAfterValue": "2000003", + "CounterHTOff": "Fixed counter 3" + }, + { + "EventCode": "0x03", + "UMask": "0x2", + "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding", + "Counter": "0,1,2,3", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "PublicDescription": "This event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:\n - preceding store conflicts with the load (incomplete overlap);\n - store forwarding is impossible due to u-arch limitations;\n - preceding lock RMW operations are not forwarded;\n - store has the no-forward bit set (uncacheable/page-split/masked stores);\n - all-blocking stores are used (mostly, fences and port I/O);\nand others.\nThe most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events.\nSee the table of not supported store forwards in the Optimization Guide.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x03", + "UMask": "0x8", + "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "Counter": "0,1,2,3", + "EventName": "LD_BLOCKS.NO_SR", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x07", + "UMask": "0x1", + "BriefDescription": "False dependencies in MOB due to partial compare", + "Counter": "0,1,2,3", + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "PublicDescription": "This event counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0D", + "UMask": "0x8", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread", + "Counter": "0,1,2,3", + "EventName": "INT_MISC.RAT_STALL_CYCLES", + "PublicDescription": "This event counts the number of cycles during which Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the current thread. This also includes the cycles during which the Allocator is serving another thread.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0D", + "UMask": "0x3", + "BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)", + "Counter": "0,1,2,3", + "EventName": "INT_MISC.RECOVERY_CYCLES", + "CounterMask": "1", + "PublicDescription": "Cycles checkpoints in Resource Allocation Table (RAT) are recovering from JEClear or machine clear.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0E", + "UMask": "0x1", + "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)", + "Counter": "0,1,2,3", + "EventName": "UOPS_ISSUED.ANY", + "PublicDescription": "This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS).", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0E", + "UMask": "0x10", + "BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.", + "Counter": "0,1,2,3", + "EventName": "UOPS_ISSUED.FLAGS_MERGE", + "PublicDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive\n added by GSR u-arch.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0E", + "UMask": "0x20", + "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", + "Counter": "0,1,2,3", + "EventName": "UOPS_ISSUED.SLOW_LEA", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0E", + "UMask": "0x40", + "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated.", + "Counter": "0,1,2,3", + "EventName": "UOPS_ISSUED.SINGLE_MUL", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "Invert": "1", + "EventCode": "0x0E", + "UMask": "0x1", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread", + "Counter": "0,1,2,3", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "CounterMask": "1", + "PublicDescription": "This event counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x14", + "UMask": "0x1", + "BriefDescription": "Cycles when divider is busy executing divide operations", + "Counter": "0,1,2,3", + "EventName": "ARITH.FPU_DIV_ACTIVE", + "PublicDescription": "This event counts the number of the divide operations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DIV_ACTIVE to get the number of the divide operations executed.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "UMask": "0x1", + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", + "Counter": "0,1,2,3", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", + "PublicDescription": "This is a fixed-frequency event programmed to general counters. It counts when the core is unhalted at 100 Mhz.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3c", + "UMask": "0x2", + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", + "Counter": "0,1,2,3", + "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x4c", + "UMask": "0x1", + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch", + "Counter": "0,1,2,3", + "EventName": "LOAD_HIT_PRE.SW_PF", + "PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by asm inspection of the nearby instructions.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x4C", + "UMask": "0x2", + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch", + "Counter": "0,1,2,3", + "EventName": "LOAD_HIT_PRE.HW_PF", + "PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the hardware prefetch.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x58", + "UMask": "0x1", + "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.", + "Counter": "0,1,2,3", + "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", + "SampleAfterValue": "1000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x58", + "UMask": "0x2", + "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.", + "Counter": "0,1,2,3", + "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", + "SampleAfterValue": "1000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x58", + "UMask": "0x4", + "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.", + "Counter": "0,1,2,3", + "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", + "SampleAfterValue": "1000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x58", + "UMask": "0x8", + "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.", + "Counter": "0,1,2,3", + "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", + "SampleAfterValue": "1000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5E", + "UMask": "0x1", + "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", + "Counter": "0,1,2,3", + "EventName": "RS_EVENTS.EMPTY_CYCLES", + "PublicDescription": "This event counts cycles during which the reservation station (RS) is empty for the thread.\nNote: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x87", + "UMask": "0x1", + "BriefDescription": "Stalls caused by changing prefix length of the instruction.", + "Counter": "0,1,2,3", + "EventName": "ILD_STALL.LCP", + "PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "UMask": "0x41", + "BriefDescription": "Not taken macro-conditional branches", + "Counter": "0,1,2,3", + "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", + "PublicDescription": "This event counts not taken macro-conditional branch instructions.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "UMask": "0x81", + "BriefDescription": "Taken speculative and retired macro-conditional branches", + "Counter": "0,1,2,3", + "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", + "PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "UMask": "0x82", + "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects", + "Counter": "0,1,2,3", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", + "PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions excluding calls and indirect branches.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "UMask": "0x84", + "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns", + "Counter": "0,1,2,3", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "This event counts taken speculative and retired indirect branches excluding calls and return branches.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "UMask": "0x88", + "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic", + "Counter": "0,1,2,3", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", + "PublicDescription": "This event counts taken speculative and retired indirect branches that have a return mnemonic.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "UMask": "0x90", + "BriefDescription": "Taken speculative and retired direct near calls", + "Counter": "0,1,2,3", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", + "PublicDescription": "This event counts taken speculative and retired direct near calls.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "UMask": "0xa0", + "BriefDescription": "Taken speculative and retired indirect calls", + "Counter": "0,1,2,3", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "PublicDescription": "This event counts taken speculative and retired indirect calls including both register and memory indirect.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "UMask": "0xc1", + "BriefDescription": "Speculative and retired macro-conditional branches", + "Counter": "0,1,2,3", + "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", + "PublicDescription": "This event counts both taken and not taken speculative and retired macro-conditional branch instructions.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "UMask": "0xc2", + "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects", + "Counter": "0,1,2,3", + "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", + "PublicDescription": "This event counts both taken and not taken speculative and retired macro-unconditional branch instructions, excluding calls and indirects.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "UMask": "0xc4", + "BriefDescription": "Speculative and retired indirect branches excluding calls and returns", + "Counter": "0,1,2,3", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches excluding calls and return branches.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "UMask": "0xc8", + "BriefDescription": "Speculative and retired indirect return branches.", + "Counter": "0,1,2,3", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", + "PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches that have a return mnemonic.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "UMask": "0xd0", + "BriefDescription": "Speculative and retired direct near calls", + "Counter": "0,1,2,3", + "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", + "PublicDescription": "This event counts both taken and not taken speculative and retired direct near calls.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "UMask": "0xff", + "BriefDescription": "Speculative and retired branches", + "Counter": "0,1,2,3", + "EventName": "BR_INST_EXEC.ALL_BRANCHES", + "PublicDescription": "This event counts both taken and not taken speculative and retired branch instructions.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "UMask": "0x41", + "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches", + "Counter": "0,1,2,3", + "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", + "PublicDescription": "This event counts not taken speculative and retired mispredicted macro conditional branch instructions.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "UMask": "0x81", + "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches", + "Counter": "0,1,2,3", + "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", + "PublicDescription": "This event counts taken speculative and retired mispredicted macro conditional branch instructions.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "UMask": "0x84", + "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns", + "Counter": "0,1,2,3", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches excluding calls and returns.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "UMask": "0x88", + "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic", + "Counter": "0,1,2,3", + "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", + "PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches that have a return mnemonic.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "UMask": "0xc1", + "BriefDescription": "Speculative and retired mispredicted macro conditional branches", + "Counter": "0,1,2,3", + "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", + "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted macro conditional branch instructions.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "UMask": "0xc4", + "BriefDescription": "Mispredicted indirect branches excluding calls and returns", + "Counter": "0,1,2,3", + "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "This event counts both taken and not taken mispredicted indirect branches excluding calls and returns.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "UMask": "0xff", + "BriefDescription": "Speculative and retired mispredicted macro conditional branches", + "Counter": "0,1,2,3", + "EventName": "BR_MISP_EXEC.ALL_BRANCHES", + "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted branch instructions.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x1", + "BriefDescription": "Cycles per thread when uops are executed in port 0", + "Counter": "0,1,2,3", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x2", + "BriefDescription": "Cycles per thread when uops are executed in port 1", + "Counter": "0,1,2,3", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x4", + "BriefDescription": "Cycles per thread when uops are executed in port 2", + "Counter": "0,1,2,3", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x8", + "BriefDescription": "Cycles per thread when uops are executed in port 3", + "Counter": "0,1,2,3", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x10", + "BriefDescription": "Cycles per thread when uops are executed in port 4", + "Counter": "0,1,2,3", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x20", + "BriefDescription": "Cycles per thread when uops are executed in port 5", + "Counter": "0,1,2,3", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x40", + "BriefDescription": "Cycles per thread when uops are executed in port 6", + "Counter": "0,1,2,3", + "EventName": "UOPS_DISPATCHED_PORT.PORT_6", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x80", + "BriefDescription": "Cycles per thread when uops are executed in port 7", + "Counter": "0,1,2,3", + "EventName": "UOPS_DISPATCHED_PORT.PORT_7", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA2", + "UMask": "0x1", + "BriefDescription": "Resource-related stall cycles", + "Counter": "0,1,2,3", + "EventName": "RESOURCE_STALLS.ANY", + "PublicDescription": "This event counts resource-related stall cycles. Reasons for stalls can be as follows:\n - *any* u-arch structure got full (LB, SB, RS, ROB, BOB, LM, Physical Register Reclaim Table (PRRT), or Physical History Table (PHT) slots)\n - *any* u-arch structure got empty (like INT/SIMD FreeLists)\n - FPU control word (FPCW), MXCSR\nand others. This counts cycles that the pipeline backend blocked uop delivery from the front end.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA2", + "UMask": "0x4", + "BriefDescription": "Cycles stalled due to no eligible RS entry available.", + "Counter": "0,1,2,3", + "EventName": "RESOURCE_STALLS.RS", + "PublicDescription": "This event counts stall cycles caused by absence of eligible entries in the reservation station (RS). This may result from RS overflow, or from RS deallocation because of the RS array Write Port allocation scheme (each RS entry has two write ports instead of four. As a result, empty entries could not be used, although RS is not really full). This counts cycles that the pipeline backend blocked uop delivery from the front end.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA2", + "UMask": "0x8", + "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", + "Counter": "0,1,2,3", + "EventName": "RESOURCE_STALLS.SB", + "PublicDescription": "This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front end.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA2", + "UMask": "0x10", + "BriefDescription": "Cycles stalled due to re-order buffer full.", + "Counter": "0,1,2,3", + "EventName": "RESOURCE_STALLS.ROB", + "PublicDescription": "This event counts ROB full stall cycles. This counts cycles that the pipeline backend blocked uop delivery from the front end.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA3", + "UMask": "0x1", + "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", + "CounterMask": "1", + "PublicDescription": "Counts number of cycles the CPU has at least one pending demand* load request missing the L2 cache.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA3", + "UMask": "0x8", + "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", + "Counter": "2", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", + "CounterMask": "8", + "PublicDescription": "Counts number of cycles the CPU has at least one pending demand load request missing the L1 data cache.", + "SampleAfterValue": "2000003", + "CounterHTOff": "2" + }, + { + "EventCode": "0xA3", + "UMask": "0x2", + "BriefDescription": "Cycles while memory subsystem has an outstanding load.", + "Counter": "0,1,2,3", + "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", + "CounterMask": "2", + "PublicDescription": "Counts number of cycles the CPU has at least one pending demand load request (that is cycles with non-completed load waiting for its data from memory subsystem).", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA3", + "UMask": "0x4", + "BriefDescription": "Total execution stalls", + "Counter": "0,1,2,3", + "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", + "CounterMask": "4", + "PublicDescription": "Counts number of cycles nothing is executed on any execution port.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xA3", + "UMask": "0x5", + "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", + "CounterMask": "5", + "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand* load request missing the L2 cache.(as a footprint) * includes also L1 HW prefetch requests that may or may not be required by demands.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xA3", + "UMask": "0x6", + "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", + "Counter": "0,1,2,3", + "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", + "CounterMask": "6", + "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xA3", + "UMask": "0xc", + "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "Counter": "2", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", + "CounterMask": "12", + "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request missing the L1 data cache.", + "SampleAfterValue": "2000003", + "CounterHTOff": "2" + }, + { + "EventCode": "0xA8", + "UMask": "0x1", + "BriefDescription": "Number of Uops delivered by the LSD.", + "Counter": "0,1,2,3", + "EventName": "LSD.UOPS", + "PublicDescription": "Number of Uops delivered by the LSD. ", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB1", + "UMask": "0x1", + "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED.THREAD", + "PublicDescription": "Number of uops to be executed per-thread each cycle.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB1", + "UMask": "0x2", + "BriefDescription": "Number of uops executed on the core.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED.CORE", + "PublicDescription": "Number of uops executed from any thread.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "Invert": "1", + "EventCode": "0xB1", + "UMask": "0x1", + "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED.STALL_CYCLES", + "CounterMask": "1", + "PublicDescription": "This event counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC0", + "UMask": "0x0", + "BriefDescription": "Number of instructions retired. General Counter - architectural event", + "Counter": "0,1,2,3", + "EventName": "INST_RETIRED.ANY_P", + "Errata": "BDM61", + "PublicDescription": "This event counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two).", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC0", + "UMask": "0x2", + "BriefDescription": "FP operations retired. X87 FP operations that have no exceptions:", + "Counter": "0,1,2,3", + "EventName": "INST_RETIRED.X87", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC0", + "UMask": "0x1", + "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution", + "PEBS": "2", + "Counter": "1", + "EventName": "INST_RETIRED.PREC_DIST", + "Errata": "BDM11, BDM55", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts instructions retired.", + "SampleAfterValue": "2000003", + "CounterHTOff": "1" + }, + { + "EventCode": "0xC1", + "UMask": "0x40", + "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.", + "Counter": "0,1,2,3", + "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC2", + "UMask": "0x1", + "BriefDescription": "Actually retired uops.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "UOPS_RETIRED.ALL", + "PublicDescription": "This event counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC2", + "UMask": "0x2", + "BriefDescription": "Retirement slots used.", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts the number of retirement slots used.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "Invert": "1", + "EventCode": "0xC2", + "UMask": "0x1", + "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "CounterMask": "1", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts cycles without actually retired uops.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "Invert": "1", + "EventCode": "0xC2", + "UMask": "0x1", + "BriefDescription": "Cycles with less than 10 actually retired uops.", + "Counter": "0,1,2,3", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "CounterMask": "10", + "PublicDescription": "Number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC3", + "UMask": "0x1", + "BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.", + "Counter": "0,1,2,3", + "EventName": "MACHINE_CLEARS.CYCLES", + "PublicDescription": "This event counts both thread-specific (TS) and all-thread (AT) nukes.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC3", + "UMask": "0x4", + "BriefDescription": "Self-modifying code (SMC) detected.", + "Counter": "0,1,2,3", + "EventName": "MACHINE_CLEARS.SMC", + "PublicDescription": "This event counts self-modifying code (SMC) detected, which causes a machine clear.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC3", + "UMask": "0x20", + "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.", + "Counter": "0,1,2,3", + "EventName": "MACHINE_CLEARS.MASKMOV", + "PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC4", + "UMask": "0x1", + "BriefDescription": "Conditional branch instructions retired.", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "BR_INST_RETIRED.CONDITIONAL", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts conditional branch instructions retired.", + "SampleAfterValue": "400009", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC4", + "UMask": "0x2", + "BriefDescription": "Direct and indirect near call instructions retired.", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts both direct and indirect near call instructions retired.", + "SampleAfterValue": "100007", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC4", + "UMask": "0x0", + "BriefDescription": "All (macro) branch instructions retired.", + "Counter": "0,1,2,3", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "PublicDescription": "This event counts all (macro) branch instructions retired.", + "SampleAfterValue": "400009", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC4", + "UMask": "0x8", + "BriefDescription": "Return instructions retired.", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts return instructions retired.", + "SampleAfterValue": "100007", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC4", + "UMask": "0x10", + "BriefDescription": "Not taken branch instructions retired.", + "Counter": "0,1,2,3", + "EventName": "BR_INST_RETIRED.NOT_TAKEN", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts not taken branch instructions retired.", + "SampleAfterValue": "400009", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC4", + "UMask": "0x20", + "BriefDescription": "Taken branch instructions retired.", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts taken branch instructions retired.", + "SampleAfterValue": "400009", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC4", + "UMask": "0x40", + "BriefDescription": "Far branch instructions retired.", + "Counter": "0,1,2,3", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "Errata": "BDW98", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts far branch instructions retired.", + "SampleAfterValue": "100007", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC4", + "UMask": "0x4", + "BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS)", + "PEBS": "2", + "Counter": "0,1,2,3", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", + "Errata": "BDW98", + "PublicDescription": "This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired.", + "SampleAfterValue": "400009", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC5", + "UMask": "0x1", + "BriefDescription": "Mispredicted conditional branch instructions retired.", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "BR_MISP_RETIRED.CONDITIONAL", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted conditional branch instructions retired.", + "SampleAfterValue": "400009", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC5", + "UMask": "0x0", + "BriefDescription": "All mispredicted macro branch instructions retired.", + "Counter": "0,1,2,3", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PublicDescription": "This event counts all mispredicted macro branch instructions retired.", + "SampleAfterValue": "400009", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC5", + "UMask": "0x8", + "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "BR_MISP_RETIRED.RET", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired.", + "SampleAfterValue": "100007", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC5", + "UMask": "0x4", + "BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)", + "PEBS": "2", + "Counter": "0,1,2,3", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", + "PublicDescription": "This is a precise version of BR_MISP_RETIRED.ALL_BRANCHES that counts all mispredicted macro branch instructions retired.", + "SampleAfterValue": "400009", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xCC", + "UMask": "0x20", + "BriefDescription": "Count cases of saving new LBR", + "Counter": "0,1,2,3", + "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", + "PublicDescription": "This event counts cases of saving new LBR records by hardware. This assumes proper enabling of LBRs and takes into account LBR filtering done by the LBR_SELECT register.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "UMask": "0x0", + "BriefDescription": "Thread cycles when thread is not in halt state", + "Counter": "0,1,2,3", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "UMask": "0xa0", + "BriefDescription": "Taken speculative and retired mispredicted indirect calls.", + "Counter": "0,1,2,3", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x1", + "BriefDescription": "Cycles per core when uops are exectuted in port 0.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", + "AnyThread": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x2", + "BriefDescription": "Cycles per core when uops are exectuted in port 1.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", + "AnyThread": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x4", + "BriefDescription": "Cycles per core when uops are dispatched to port 2.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE", + "AnyThread": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x8", + "BriefDescription": "Cycles per core when uops are dispatched to port 3.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE", + "AnyThread": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x10", + "BriefDescription": "Cycles per core when uops are exectuted in port 4.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", + "AnyThread": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x20", + "BriefDescription": "Cycles per core when uops are exectuted in port 5.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", + "AnyThread": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x40", + "BriefDescription": "Cycles per core when uops are exectuted in port 6.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", + "AnyThread": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x80", + "BriefDescription": "Cycles per core when uops are dispatched to port 7.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE", + "AnyThread": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC5", + "UMask": "0x20", + "BriefDescription": "number of near branch instructions retired that were mispredicted and taken.", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "PublicDescription": "Number of near branch instructions retired that were mispredicted and taken.", + "SampleAfterValue": "400009", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB1", + "UMask": "0x1", + "BriefDescription": "Cycles where at least 1 uop was executed per-thread.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", + "CounterMask": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB1", + "UMask": "0x1", + "BriefDescription": "Cycles where at least 2 uops were executed per-thread.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", + "CounterMask": "2", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB1", + "UMask": "0x1", + "BriefDescription": "Cycles where at least 3 uops were executed per-thread.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", + "CounterMask": "3", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB1", + "UMask": "0x1", + "BriefDescription": "Cycles where at least 4 uops were executed per-thread.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", + "CounterMask": "4", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xe6", + "UMask": "0x1f", + "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", + "Counter": "0,1,2,3", + "EventName": "BACLEARS.ANY", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA3", + "UMask": "0x8", + "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", + "Counter": "2", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", + "CounterMask": "8", + "SampleAfterValue": "2000003", + "CounterHTOff": "2" + }, + { + "EventCode": "0xA3", + "UMask": "0x1", + "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", + "CounterMask": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA3", + "UMask": "0x2", + "BriefDescription": "Cycles while memory subsystem has an outstanding load.", + "Counter": "0,1,2,3", + "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "CounterMask": "2", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xA3", + "UMask": "0x4", + "BriefDescription": "Total execution stalls.", + "Counter": "0,1,2,3", + "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", + "CounterMask": "4", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA3", + "UMask": "0xc", + "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "Counter": "2", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", + "CounterMask": "12", + "SampleAfterValue": "2000003", + "CounterHTOff": "2" + }, + { + "EventCode": "0xA3", + "UMask": "0x5", + "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", + "CounterMask": "5", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA3", + "UMask": "0x6", + "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", + "Counter": "0,1,2,3", + "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "CounterMask": "6", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EdgeDetect": "1", + "EventCode": "0xC3", + "UMask": "0x1", + "BriefDescription": "Number of machine clears (nukes) of any type.", + "Counter": "0,1,2,3", + "EventName": "MACHINE_CLEARS.COUNT", + "CounterMask": "1", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA8", + "UMask": "0x1", + "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", + "Counter": "0,1,2,3", + "EventName": "LSD.CYCLES_4_UOPS", + "CounterMask": "4", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EdgeDetect": "1", + "Invert": "1", + "EventCode": "0x5E", + "UMask": "0x1", + "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.", + "Counter": "0,1,2,3", + "EventName": "RS_EVENTS.EMPTY_END", + "CounterMask": "1", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA8", + "UMask": "0x1", + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", + "Counter": "0,1,2,3", + "EventName": "LSD.CYCLES_ACTIVE", + "CounterMask": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x1", + "BriefDescription": "Cycles per thread when uops are executed in port 0", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_0", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x2", + "BriefDescription": "Cycles per thread when uops are executed in port 1", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_1", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x4", + "BriefDescription": "Cycles per thread when uops are executed in port 2", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_2", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x8", + "BriefDescription": "Cycles per thread when uops are executed in port 3", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_3", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x10", + "BriefDescription": "Cycles per thread when uops are executed in port 4", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_4", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x20", + "BriefDescription": "Cycles per thread when uops are executed in port 5", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_5", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x40", + "BriefDescription": "Cycles per thread when uops are executed in port 6", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_6", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x80", + "BriefDescription": "Cycles per thread when uops are executed in port 7", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_7", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA0", + "UMask": "0x3", + "BriefDescription": "Micro-op dispatches cancelled due to insufficient SIMD physical register file read ports", + "Counter": "0,1,2,3", + "EventName": "UOP_DISPATCHES_CANCELLED.SIMD_PRF", + "PublicDescription": "This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file. The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more information.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x00", + "UMask": "0x2", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "Counter": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", + "AnyThread": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "Fixed counter 2" + }, + { + "EventCode": "0x3C", + "UMask": "0x0", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "Counter": "0,1,2,3", + "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", + "AnyThread": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "UMask": "0x1", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", + "Counter": "0,1,2,3", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", + "AnyThread": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0D", + "UMask": "0x3", + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).", + "Counter": "0,1,2,3", + "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", + "AnyThread": "1", + "CounterMask": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xb1", + "UMask": "0x2", + "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "CounterMask": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xb1", + "UMask": "0x2", + "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "CounterMask": "2", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xb1", + "UMask": "0x2", + "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "CounterMask": "3", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xb1", + "UMask": "0x2", + "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "CounterMask": "4", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "Invert": "1", + "EventCode": "0xb1", + "UMask": "0x2", + "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "UMask": "0x1", + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", + "Counter": "0,1,2,3", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "UMask": "0x1", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", + "Counter": "0,1,2,3", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", + "AnyThread": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "UMask": "0x2", + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", + "Counter": "0,1,2,3", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/virtual-memory.json b/tools/perf/pmu-events/arch/x86/broadwellde/virtual-memory.json new file mode 100644 index 000000000000..5ce8b67ba076 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/broadwellde/virtual-memory.json @@ -0,0 +1,388 @@ +[ + { + "EventCode": "0x08", + "UMask": "0x1", + "BriefDescription": "Load misses in all DTLB levels that cause page walks", + "Counter": "0,1,2,3", + "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", + "Errata": "BDM69", + "PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x08", + "UMask": "0x2", + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).", + "Counter": "0,1,2,3", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "Errata": "BDM69", + "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x08", + "UMask": "0x4", + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).", + "Counter": "0,1,2,3", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "Errata": "BDM69", + "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x08", + "UMask": "0x8", + "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)", + "Counter": "0,1,2,3", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", + "Errata": "BDM69", + "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x08", + "UMask": "0x10", + "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", + "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", + "Errata": "BDM69", + "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x08", + "UMask": "0x20", + "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).", + "Counter": "0,1,2,3", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x08", + "UMask": "0x40", + "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).", + "Counter": "0,1,2,3", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "UMask": "0x1", + "BriefDescription": "Store misses in all DTLB levels that cause page walks", + "Counter": "0,1,2,3", + "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", + "Errata": "BDM69", + "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "UMask": "0x2", + "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)", + "Counter": "0,1,2,3", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "Errata": "BDM69", + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "UMask": "0x4", + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)", + "Counter": "0,1,2,3", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "Errata": "BDM69", + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "UMask": "0x8", + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (1G)", + "Counter": "0,1,2,3", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", + "Errata": "BDM69", + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "UMask": "0x10", + "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", + "EventName": "DTLB_STORE_MISSES.WALK_DURATION", + "Errata": "BDM69", + "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "UMask": "0x20", + "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K).", + "Counter": "0,1,2,3", + "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "UMask": "0x40", + "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M).", + "Counter": "0,1,2,3", + "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x4F", + "UMask": "0x10", + "BriefDescription": "Cycle count for an Extended Page table walk.", + "Counter": "0,1,2,3", + "EventName": "EPT.WALK_CYCLES", + "PublicDescription": "This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "UMask": "0x1", + "BriefDescription": "Misses at all ITLB levels that cause page walks", + "Counter": "0,1,2,3", + "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", + "Errata": "BDM69", + "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "UMask": "0x2", + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", + "Counter": "0,1,2,3", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "Errata": "BDM69", + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "UMask": "0x4", + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", + "Counter": "0,1,2,3", + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "Errata": "BDM69", + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "UMask": "0x8", + "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)", + "Counter": "0,1,2,3", + "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", + "Errata": "BDM69", + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "UMask": "0x10", + "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", + "EventName": "ITLB_MISSES.WALK_DURATION", + "Errata": "BDM69", + "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "UMask": "0x20", + "BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K).", + "Counter": "0,1,2,3", + "EventName": "ITLB_MISSES.STLB_HIT_4K", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "UMask": "0x40", + "BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M).", + "Counter": "0,1,2,3", + "EventName": "ITLB_MISSES.STLB_HIT_2M", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xAE", + "UMask": "0x1", + "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", + "Counter": "0,1,2,3", + "EventName": "ITLB.ITLB_FLUSH", + "PublicDescription": "This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).", + "SampleAfterValue": "100007", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xBC", + "UMask": "0x11", + "BriefDescription": "Number of DTLB page walker hits in the L1+FB.", + "Counter": "0,1,2,3", + "EventName": "PAGE_WALKER_LOADS.DTLB_L1", + "Errata": "BDM69, BDM98", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBC", + "UMask": "0x21", + "BriefDescription": "Number of ITLB page walker hits in the L1+FB.", + "Counter": "0,1,2,3", + "EventName": "PAGE_WALKER_LOADS.ITLB_L1", + "Errata": "BDM69, BDM98", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBC", + "UMask": "0x12", + "BriefDescription": "Number of DTLB page walker hits in the L2.", + "Counter": "0,1,2,3", + "EventName": "PAGE_WALKER_LOADS.DTLB_L2", + "Errata": "BDM69, BDM98", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBC", + "UMask": "0x22", + "BriefDescription": "Number of ITLB page walker hits in the L2.", + "Counter": "0,1,2,3", + "EventName": "PAGE_WALKER_LOADS.ITLB_L2", + "Errata": "BDM69, BDM98", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBC", + "UMask": "0x14", + "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP.", + "Counter": "0,1,2,3", + "EventName": "PAGE_WALKER_LOADS.DTLB_L3", + "Errata": "BDM69, BDM98", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBC", + "UMask": "0x24", + "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP.", + "Counter": "0,1,2,3", + "EventName": "PAGE_WALKER_LOADS.ITLB_L3", + "Errata": "BDM69, BDM98", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBC", + "UMask": "0x18", + "BriefDescription": "Number of DTLB page walker hits in Memory.", + "Counter": "0,1,2,3", + "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY", + "Errata": "BDM69, BDM98", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBD", + "UMask": "0x1", + "BriefDescription": "DTLB flush attempts of the thread-specific entries", + "Counter": "0,1,2,3", + "EventName": "TLB_FLUSH.DTLB_THREAD", + "PublicDescription": "This event counts the number of DTLB flush attempts of the thread-specific entries.", + "SampleAfterValue": "100007", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xBD", + "UMask": "0x20", + "BriefDescription": "STLB flush attempts", + "Counter": "0,1,2,3", + "EventName": "TLB_FLUSH.STLB_ANY", + "PublicDescription": "This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).", + "SampleAfterValue": "100007", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x08", + "UMask": "0xe", + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", + "Counter": "0,1,2,3", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "Errata": "BDM69", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x08", + "UMask": "0x60", + "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.", + "Counter": "0,1,2,3", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "UMask": "0xe", + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.", + "Counter": "0,1,2,3", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "Errata": "BDM69", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "UMask": "0x60", + "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", + "Counter": "0,1,2,3", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "UMask": "0xe", + "BriefDescription": "Misses in all ITLB levels that cause completed page walks.", + "Counter": "0,1,2,3", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "Errata": "BDM69", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "UMask": "0x60", + "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.", + "Counter": "0,1,2,3", + "EventName": "ITLB_MISSES.STLB_HIT", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/cache.json b/tools/perf/pmu-events/arch/x86/broadwellx/cache.json new file mode 100644 index 000000000000..d1d043829b95 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/broadwellx/cache.json @@ -0,0 +1,942 @@ +[ + { + "EventCode": "0x24", + "UMask": "0x21", + "BriefDescription": "Demand Data Read miss L2, no rejects", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", + "PublicDescription": "This event counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0x41", + "BriefDescription": "Demand Data Read requests that hit L2 cache", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "PublicDescription": "This event counts the number of demand Data Read requests that hit L2 cache. Only not rejected loads are counted.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0x30", + "BriefDescription": "L2 prefetch requests that miss L2 cache", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.L2_PF_MISS", + "PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that miss L2 cache.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0x50", + "BriefDescription": "L2 prefetch requests that hit L2 cache", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.L2_PF_HIT", + "PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0xe1", + "BriefDescription": "Demand Data Read requests", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "PublicDescription": "This event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0xe2", + "BriefDescription": "RFO requests to L2 cache", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.ALL_RFO", + "PublicDescription": "This event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0xe4", + "BriefDescription": "L2 code requests", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "PublicDescription": "This event counts the total number of L2 code requests.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0xf8", + "BriefDescription": "Requests from L2 hardware prefetchers", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.ALL_PF", + "PublicDescription": "This event counts the total number of requests from the L2 hardware prefetchers.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x27", + "UMask": "0x50", + "BriefDescription": "Not rejected writebacks that hit L2 cache", + "Counter": "0,1,2,3", + "EventName": "L2_DEMAND_RQSTS.WB_HIT", + "PublicDescription": "This event counts the number of WB requests that hit L2 cache.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x2E", + "UMask": "0x41", + "BriefDescription": "Core-originated cacheable demand requests missed L3", + "Counter": "0,1,2,3", + "EventName": "LONGEST_LAT_CACHE.MISS", + "PublicDescription": "This event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x2E", + "UMask": "0x4f", + "BriefDescription": "Core-originated cacheable demand requests that refer to L3", + "Counter": "0,1,2,3", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "PublicDescription": "This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x48", + "UMask": "0x1", + "BriefDescription": "L1D miss oustandings duration in cycles", + "Counter": "2", + "EventName": "L1D_PEND_MISS.PENDING", + "PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch.\nNote: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", + "SampleAfterValue": "2000003", + "CounterHTOff": "2" + }, + { + "EventCode": "0x48", + "UMask": "0x1", + "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "2", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", + "CounterMask": "1", + "PublicDescription": "This event counts duration of L1D miss outstanding in cycles.", + "SampleAfterValue": "2000003", + "CounterHTOff": "2" + }, + { + "EventCode": "0x51", + "UMask": "0x1", + "BriefDescription": "L1D data line replacements", + "Counter": "0,1,2,3", + "EventName": "L1D.REPLACEMENT", + "PublicDescription": "This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "UMask": "0x1", + "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "Errata": "BDM76", + "PublicDescription": "This event counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.\nNote: A prefetch promoted to Demand is counted from the promotion point.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "UMask": "0x2", + "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", + "Errata": "BDM76", + "PublicDescription": "This event counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The \"Offcore outstanding\" state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "UMask": "0x4", + "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", + "Errata": "BDM76", + "PublicDescription": "This event counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "UMask": "0x8", + "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "Errata": "BDM76", + "PublicDescription": "This event counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "UMask": "0x1", + "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "CounterMask": "1", + "Errata": "BDM76", + "PublicDescription": "This event counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation).", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "UMask": "0x8", + "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "CounterMask": "1", + "Errata": "BDM76", + "PublicDescription": "This event counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "UMask": "0x4", + "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "CounterMask": "1", + "Errata": "BDM76", + "PublicDescription": "This event counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The \"Offcore outstanding\" state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x63", + "UMask": "0x2", + "BriefDescription": "Cycles when L1D is locked", + "Counter": "0,1,2,3", + "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", + "PublicDescription": "This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB0", + "UMask": "0x1", + "BriefDescription": "Demand Data Read requests sent to uncore", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "PublicDescription": "This event counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB0", + "UMask": "0x2", + "BriefDescription": "Cacheable and noncachaeble code read requests", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "PublicDescription": "This event counts both cacheable and noncachaeble code read requests.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB0", + "UMask": "0x4", + "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "PublicDescription": "This event counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB0", + "UMask": "0x8", + "BriefDescription": "Demand and prefetch data reads", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", + "PublicDescription": "This event counts the demand and prefetch data reads. All Core Data Reads include cacheable \"Demands\" and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xb2", + "UMask": "0x1", + "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", + "PublicDescription": "This event counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.\nNote: Writeback pending FIFO has six entries.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xD0", + "UMask": "0x11", + "BriefDescription": "Retired load uops that miss the STLB.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD0", + "UMask": "0x12", + "BriefDescription": "Retired store uops that miss the STLB.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts store uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.", + "SampleAfterValue": "100003", + "L1_Hit_Indication": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD0", + "UMask": "0x21", + "BriefDescription": "Retired load uops with locked access.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "Errata": "BDM35", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts load uops with locked access retired to the architected path.", + "SampleAfterValue": "100007", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD0", + "UMask": "0x41", + "BriefDescription": "Retired load uops that split across a cacheline boundary.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD0", + "UMask": "0x42", + "BriefDescription": "Retired store uops that split across a cacheline boundary.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "SampleAfterValue": "100003", + "L1_Hit_Indication": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD0", + "UMask": "0x81", + "BriefDescription": "All retired load uops.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "PublicDescription": "This event counts load uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD0", + "UMask": "0x82", + "BriefDescription": "All retired store uops.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "PublicDescription": "This event counts store uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement.", + "SampleAfterValue": "2000003", + "L1_Hit_Indication": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD1", + "UMask": "0x1", + "BriefDescription": "Retired load uops with L1 cache hits as data sources.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were hits in the nearest-level (L1) cache.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD1", + "UMask": "0x2", + "BriefDescription": "Retired load uops with L2 cache hits as data sources.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "Errata": "BDM35", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were hits in the mid-level (L2) cache.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD1", + "UMask": "0x4", + "BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", + "Errata": "BDM100", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required.", + "SampleAfterValue": "50021", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD1", + "UMask": "0x8", + "BriefDescription": "Retired load uops misses in L1 cache as data sources.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD1", + "UMask": "0x10", + "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source.", + "SampleAfterValue": "50021", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD1", + "UMask": "0x20", + "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS", + "Errata": "BDM100, BDE70", + "SampleAfterValue": "100007", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD1", + "UMask": "0x40", + "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD2", + "UMask": "0x1", + "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS", + "Errata": "BDM100", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache.", + "SampleAfterValue": "20011", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD2", + "UMask": "0x2", + "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT", + "Errata": "BDM100", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache.", + "SampleAfterValue": "20011", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD2", + "UMask": "0x4", + "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM", + "Errata": "BDM100", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were HitM responses from a core on same socket (shared L3).", + "SampleAfterValue": "20011", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD2", + "UMask": "0x8", + "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE", + "Errata": "BDM100", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD3", + "UMask": "0x1", + "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", + "Errata": "BDE70, BDM100", + "PublicDescription": "Retired load uop whose Data Source was: local DRAM either Snoop not needed or Snoop Miss (RspI).", + "SampleAfterValue": "100007", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD3", + "UMask": "0x4", + "BriefDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI)", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM", + "Errata": "BDE70", + "SampleAfterValue": "100007", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD3", + "UMask": "0x10", + "BriefDescription": "Retired load uop whose Data Source was: Remote cache HITM", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM", + "Errata": "BDE70", + "SampleAfterValue": "100007", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD3", + "UMask": "0x20", + "BriefDescription": "Retired load uop whose Data Source was: forwarded from remote cache", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD", + "Errata": "BDE70", + "SampleAfterValue": "100007", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xF0", + "UMask": "0x1", + "BriefDescription": "Demand Data Read requests that access L2 cache", + "Counter": "0,1,2,3", + "EventName": "L2_TRANS.DEMAND_DATA_RD", + "PublicDescription": "This event counts Demand Data Read requests that access L2 cache, including rejects.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF0", + "UMask": "0x2", + "BriefDescription": "RFO requests that access L2 cache", + "Counter": "0,1,2,3", + "EventName": "L2_TRANS.RFO", + "PublicDescription": "This event counts Read for Ownership (RFO) requests that access L2 cache.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF0", + "UMask": "0x4", + "BriefDescription": "L2 cache accesses when fetching instructions", + "Counter": "0,1,2,3", + "EventName": "L2_TRANS.CODE_RD", + "PublicDescription": "This event counts the number of L2 cache accesses when fetching instructions.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF0", + "UMask": "0x8", + "BriefDescription": "L2 or L3 HW prefetches that access L2 cache", + "Counter": "0,1,2,3", + "EventName": "L2_TRANS.ALL_PF", + "PublicDescription": "This event counts L2 or L3 HW prefetches that access L2 cache including rejects.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF0", + "UMask": "0x10", + "BriefDescription": "L1D writebacks that access L2 cache", + "Counter": "0,1,2,3", + "EventName": "L2_TRANS.L1D_WB", + "PublicDescription": "This event counts L1D writebacks that access L2 cache.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF0", + "UMask": "0x20", + "BriefDescription": "L2 fill requests that access L2 cache", + "Counter": "0,1,2,3", + "EventName": "L2_TRANS.L2_FILL", + "PublicDescription": "This event counts L2 fill requests that access L2 cache.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF0", + "UMask": "0x40", + "BriefDescription": "L2 writebacks that access L2 cache", + "Counter": "0,1,2,3", + "EventName": "L2_TRANS.L2_WB", + "PublicDescription": "This event counts L2 writebacks that access L2 cache.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF0", + "UMask": "0x80", + "BriefDescription": "Transactions accessing L2 pipe", + "Counter": "0,1,2,3", + "EventName": "L2_TRANS.ALL_REQUESTS", + "PublicDescription": "This event counts transactions that access the L2 pipe including snoops, pagewalks, and so on.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF1", + "UMask": "0x1", + "BriefDescription": "L2 cache lines in I state filling L2", + "Counter": "0,1,2,3", + "EventName": "L2_LINES_IN.I", + "PublicDescription": "This event counts the number of L2 cache lines in the Invalidate state filling the L2. Counting does not cover rejects.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF1", + "UMask": "0x2", + "BriefDescription": "L2 cache lines in S state filling L2", + "Counter": "0,1,2,3", + "EventName": "L2_LINES_IN.S", + "PublicDescription": "This event counts the number of L2 cache lines in the Shared state filling the L2. Counting does not cover rejects.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF1", + "UMask": "0x4", + "BriefDescription": "L2 cache lines in E state filling L2", + "Counter": "0,1,2,3", + "EventName": "L2_LINES_IN.E", + "PublicDescription": "This event counts the number of L2 cache lines in the Exclusive state filling the L2. Counting does not cover rejects.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF1", + "UMask": "0x7", + "BriefDescription": "L2 cache lines filling L2", + "Counter": "0,1,2,3", + "EventName": "L2_LINES_IN.ALL", + "PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does not cover rejects.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF2", + "UMask": "0x5", + "BriefDescription": "Clean L2 cache lines evicted by demand.", + "Counter": "0,1,2,3", + "EventName": "L2_LINES_OUT.DEMAND_CLEAN", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xf4", + "UMask": "0x10", + "BriefDescription": "Split locks in SQ", + "Counter": "0,1,2,3", + "EventName": "SQ_MISC.SPLIT_LOCK", + "PublicDescription": "This event counts the number of split locks in the super queue.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0x42", + "BriefDescription": "RFO requests that hit L2 cache.", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.RFO_HIT", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0x22", + "BriefDescription": "RFO requests that miss L2 cache.", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.RFO_MISS", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0x44", + "BriefDescription": "L2 cache hits when fetching instructions, code reads.", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.CODE_RD_HIT", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0x24", + "BriefDescription": "L2 cache misses when fetching instructions.", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.CODE_RD_MISS", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0x27", + "BriefDescription": "Demand requests that miss L2 cache.", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.ALL_DEMAND_MISS", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0xe7", + "BriefDescription": "Demand requests to L2 cache.", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0x3f", + "BriefDescription": "All requests that miss L2 cache.", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.MISS", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0xff", + "BriefDescription": "All L2 requests.", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.REFERENCES", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x60", + "UMask": "0x1", + "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", + "CounterMask": "6", + "Errata": "BDM76", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x48", + "UMask": "0x1", + "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", + "Counter": "2", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", + "AnyThread": "1", + "CounterMask": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "2" + }, + { + "EventCode": "0x48", + "UMask": "0x2", + "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", + "Counter": "0,1,2,3", + "EventName": "L1D_PEND_MISS.FB_FULL", + "CounterMask": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all requests that hit in the L3", + "MSRValue": "0x3f803c8fff", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "MSRValue": "0x10003c07f7", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "MSRValue": "0x04003c07f7", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all demand & prefetch code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "MSRValue": "0x04003c0244", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "MSRValue": "0x10003c0122", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "MSRValue": "0x04003c0122", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "MSRValue": "0x10003c0091", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "MSRValue": "0x04003c0091", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3", + "MSRValue": "0x3f803c0200", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3", + "MSRValue": "0x3f803c0100", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "MSRValue": "0x10003c0002", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/floating-point.json b/tools/perf/pmu-events/arch/x86/broadwellx/floating-point.json new file mode 100644 index 000000000000..4ae1ea24f22f --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/broadwellx/floating-point.json @@ -0,0 +1,171 @@ +[ + { + "EventCode": "0xC1", + "UMask": "0x8", + "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.", + "Counter": "0,1,2,3", + "EventName": "OTHER_ASSISTS.AVX_TO_SSE", + "Errata": "BDM30", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC1", + "UMask": "0x10", + "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.", + "Counter": "0,1,2,3", + "EventName": "OTHER_ASSISTS.SSE_TO_AVX", + "Errata": "BDM30", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC7", + "UMask": "0x1", + "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC7", + "UMask": "0x2", + "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC7", + "UMask": "0x4", + "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC7", + "UMask": "0x8", + "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC7", + "UMask": "0x10", + "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xCA", + "UMask": "0x2", + "BriefDescription": "Number of X87 assists due to output value.", + "Counter": "0,1,2,3", + "EventName": "FP_ASSIST.X87_OUTPUT", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xCA", + "UMask": "0x4", + "BriefDescription": "Number of X87 assists due to input value.", + "Counter": "0,1,2,3", + "EventName": "FP_ASSIST.X87_INPUT", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xCA", + "UMask": "0x8", + "BriefDescription": "Number of SIMD FP assists due to Output values", + "Counter": "0,1,2,3", + "EventName": "FP_ASSIST.SIMD_OUTPUT", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xCA", + "UMask": "0x10", + "BriefDescription": "Number of SIMD FP assists due to input values", + "Counter": "0,1,2,3", + "EventName": "FP_ASSIST.SIMD_INPUT", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xCA", + "UMask": "0x1e", + "BriefDescription": "Cycles with any input/output SSE or FP assist", + "Counter": "0,1,2,3", + "EventName": "FP_ASSIST.ANY", + "CounterMask": "1", + "PublicDescription": "This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xc7", + "UMask": "0x20", + "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC7", + "UMask": "0x3", + "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "Counter": "0,1,2,3", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC7", + "UMask": "0x3c", + "BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "Counter": "0,1,2,3", + "EventName": "FP_ARITH_INST_RETIRED.PACKED", + "SampleAfterValue": "2000004", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC7", + "UMask": "0x2a", + "BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.", + "Counter": "0,1,2,3", + "EventName": "FP_ARITH_INST_RETIRED.SINGLE", + "SampleAfterValue": "2000005", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC7", + "UMask": "0x15", + "BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.", + "Counter": "0,1,2,3", + "EventName": "FP_ARITH_INST_RETIRED.DOUBLE", + "SampleAfterValue": "2000006", + "CounterHTOff": "0,1,2,3" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/frontend.json b/tools/perf/pmu-events/arch/x86/broadwellx/frontend.json new file mode 100644 index 000000000000..06bf0a40e568 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/broadwellx/frontend.json @@ -0,0 +1,286 @@ +[ + { + "EventCode": "0x79", + "UMask": "0x2", + "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", + "Counter": "0,1,2,3", + "EventName": "IDQ.EMPTY", + "PublicDescription": "This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x79", + "UMask": "0x4", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "Counter": "0,1,2,3", + "EventName": "IDQ.MITE_UOPS", + "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may \"bypass\" the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "UMask": "0x8", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", + "EventName": "IDQ.DSB_UOPS", + "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may \"bypass\" the IDQ.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "UMask": "0x10", + "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "EventName": "IDQ.MS_DSB_UOPS", + "PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may \"bypass\" the IDQ.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "UMask": "0x20", + "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "EventName": "IDQ.MS_MITE_UOPS", + "PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may \"bypass\" the IDQ.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "UMask": "0x30", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "EventName": "IDQ.MS_UOPS", + "PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may \"bypass\" the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "UMask": "0x30", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "EventName": "IDQ.MS_CYCLES", + "CounterMask": "1", + "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may \"bypass\" the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "UMask": "0x4", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path", + "Counter": "0,1,2,3", + "EventName": "IDQ.MITE_CYCLES", + "CounterMask": "1", + "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may \"bypass\" the IDQ.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "UMask": "0x8", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", + "EventName": "IDQ.DSB_CYCLES", + "CounterMask": "1", + "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may \"bypass\" the IDQ.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "UMask": "0x10", + "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "EventName": "IDQ.MS_DSB_CYCLES", + "CounterMask": "1", + "PublicDescription": "This event counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may \"bypass\" the IDQ.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EdgeDetect": "1", + "EventCode": "0x79", + "UMask": "0x10", + "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "EventName": "IDQ.MS_DSB_OCCUR", + "CounterMask": "1", + "PublicDescription": "This event counts the number of deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) is busy. Counting includes uops that may \"bypass\" the IDQ.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "UMask": "0x18", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", + "Counter": "0,1,2,3", + "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", + "CounterMask": "4", + "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may \"bypass\" the IDQ.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "UMask": "0x18", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", + "Counter": "0,1,2,3", + "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", + "CounterMask": "1", + "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may \"bypass\" the IDQ.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "UMask": "0x24", + "BriefDescription": "Cycles MITE is delivering 4 Uops", + "Counter": "0,1,2,3", + "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", + "CounterMask": "4", + "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may \"bypass\" the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "UMask": "0x24", + "BriefDescription": "Cycles MITE is delivering any Uop", + "Counter": "0,1,2,3", + "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", + "CounterMask": "1", + "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may \"bypass\" the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "UMask": "0x3c", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "Counter": "0,1,2,3", + "EventName": "IDQ.MITE_ALL_UOPS", + "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may \"bypass\" the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x80", + "UMask": "0x1", + "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches", + "Counter": "0,1,2,3", + "EventName": "ICACHE.HIT", + "PublicDescription": "This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x80", + "UMask": "0x2", + "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.", + "Counter": "0,1,2,3", + "EventName": "ICACHE.MISSES", + "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x80", + "UMask": "0x4", + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", + "Counter": "0,1,2,3", + "EventName": "ICACHE.IFDATA_STALL", + "PublicDescription": "This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x9C", + "UMask": "0x1", + "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled", + "Counter": "0,1,2,3", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "PublicDescription": "This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding ?4 ? x? when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); \n c. Instruction Decode Queue (IDQ) delivers four uops.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "UMask": "0x1", + "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled", + "Counter": "0,1,2,3", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "CounterMask": "4", + "PublicDescription": "This event counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "UMask": "0x1", + "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled", + "Counter": "0,1,2,3", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", + "CounterMask": "3", + "PublicDescription": "This event counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >=3.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "UMask": "0x1", + "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", + "Counter": "0,1,2,3", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", + "CounterMask": "2", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "UMask": "0x1", + "BriefDescription": "Cycles with less than 3 uops delivered by the front end.", + "Counter": "0,1,2,3", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", + "CounterMask": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "Invert": "1", + "EventCode": "0x9C", + "UMask": "0x1", + "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.", + "Counter": "0,1,2,3", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "CounterMask": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xAB", + "UMask": "0x2", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", + "Counter": "0,1,2,3", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 0?2 cycles.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EdgeDetect": "1", + "EventCode": "0x79", + "UMask": "0x30", + "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "Counter": "0,1,2,3", + "EventName": "IDQ.MS_SWITCHES", + "CounterMask": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/memory.json b/tools/perf/pmu-events/arch/x86/broadwellx/memory.json new file mode 100644 index 000000000000..1204ea8ff30d --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/broadwellx/memory.json @@ -0,0 +1,649 @@ +[ + { + "EventCode": "0x05", + "UMask": "0x1", + "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", + "Counter": "0,1,2,3", + "EventName": "MISALIGN_MEM_REF.LOADS", + "PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x05", + "UMask": "0x2", + "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", + "Counter": "0,1,2,3", + "EventName": "MISALIGN_MEM_REF.STORES", + "PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x54", + "UMask": "0x1", + "BriefDescription": "Number of times a TSX line had a cache conflict", + "Counter": "0,1,2,3", + "EventName": "TX_MEM.ABORT_CONFLICT", + "PublicDescription": "Number of times a TSX line had a cache conflict.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x54", + "UMask": "0x2", + "BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow", + "Counter": "0,1,2,3", + "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", + "PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x54", + "UMask": "0x4", + "BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock", + "Counter": "0,1,2,3", + "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", + "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x54", + "UMask": "0x8", + "BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty", + "Counter": "0,1,2,3", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", + "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x54", + "UMask": "0x10", + "BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch", + "Counter": "0,1,2,3", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", + "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x54", + "UMask": "0x20", + "BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer", + "Counter": "0,1,2,3", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", + "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x54", + "UMask": "0x40", + "BriefDescription": "Number of times we could not allocate Lock Buffer", + "Counter": "0,1,2,3", + "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", + "PublicDescription": "Number of times we could not allocate Lock Buffer.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5d", + "UMask": "0x1", + "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", + "Counter": "0,1,2,3", + "EventName": "TX_EXEC.MISC1", + "PublicDescription": "Unfriendly TSX abort triggered by a flowmarker.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5d", + "UMask": "0x2", + "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", + "Counter": "0,1,2,3", + "EventName": "TX_EXEC.MISC2", + "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5d", + "UMask": "0x4", + "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", + "Counter": "0,1,2,3", + "EventName": "TX_EXEC.MISC3", + "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5d", + "UMask": "0x8", + "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", + "Counter": "0,1,2,3", + "EventName": "TX_EXEC.MISC4", + "PublicDescription": "RTM region detected inside HLE.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5d", + "UMask": "0x10", + "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", + "Counter": "0,1,2,3", + "EventName": "TX_EXEC.MISC5", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC3", + "UMask": "0x2", + "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", + "Counter": "0,1,2,3", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xc8", + "UMask": "0x1", + "BriefDescription": "Number of times we entered an HLE region; does not count nested transactions", + "Counter": "0,1,2,3", + "EventName": "HLE_RETIRED.START", + "PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xc8", + "UMask": "0x2", + "BriefDescription": "Number of times HLE commit succeeded", + "Counter": "0,1,2,3", + "EventName": "HLE_RETIRED.COMMIT", + "PublicDescription": "Number of times HLE commit succeeded.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xc8", + "UMask": "0x4", + "BriefDescription": "Number of times HLE abort was triggered", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "HLE_RETIRED.ABORTED", + "PublicDescription": "Number of times HLE abort was triggered.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xc8", + "UMask": "0x8", + "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", + "Counter": "0,1,2,3", + "EventName": "HLE_RETIRED.ABORTED_MISC1", + "PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xc8", + "UMask": "0x10", + "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions", + "Counter": "0,1,2,3", + "EventName": "HLE_RETIRED.ABORTED_MISC2", + "PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xc8", + "UMask": "0x20", + "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions", + "Counter": "0,1,2,3", + "EventName": "HLE_RETIRED.ABORTED_MISC3", + "PublicDescription": "Number of times a disallowed operation caused an HLE abort.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xc8", + "UMask": "0x40", + "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", + "Counter": "0,1,2,3", + "EventName": "HLE_RETIRED.ABORTED_MISC4", + "PublicDescription": "Number of times HLE caused a fault.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xc8", + "UMask": "0x80", + "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)", + "Counter": "0,1,2,3", + "EventName": "HLE_RETIRED.ABORTED_MISC5", + "PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xc9", + "UMask": "0x1", + "BriefDescription": "Number of times we entered an RTM region; does not count nested transactions", + "Counter": "0,1,2,3", + "EventName": "RTM_RETIRED.START", + "PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xc9", + "UMask": "0x2", + "BriefDescription": "Number of times RTM commit succeeded", + "Counter": "0,1,2,3", + "EventName": "RTM_RETIRED.COMMIT", + "PublicDescription": "Number of times RTM commit succeeded.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xc9", + "UMask": "0x4", + "BriefDescription": "Number of times RTM abort was triggered", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "RTM_RETIRED.ABORTED", + "PublicDescription": "Number of times RTM abort was triggered .", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xc9", + "UMask": "0x8", + "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", + "Counter": "0,1,2,3", + "EventName": "RTM_RETIRED.ABORTED_MISC1", + "PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xc9", + "UMask": "0x10", + "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).", + "Counter": "0,1,2,3", + "EventName": "RTM_RETIRED.ABORTED_MISC2", + "PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xc9", + "UMask": "0x20", + "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", + "Counter": "0,1,2,3", + "EventName": "RTM_RETIRED.ABORTED_MISC3", + "PublicDescription": "Number of times a disallowed operation caused an RTM abort.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xc9", + "UMask": "0x40", + "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", + "Counter": "0,1,2,3", + "EventName": "RTM_RETIRED.ABORTED_MISC4", + "PublicDescription": "Number of times a RTM caused a fault.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xc9", + "UMask": "0x80", + "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", + "Counter": "0,1,2,3", + "EventName": "RTM_RETIRED.ABORTED_MISC5", + "PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xCD", + "UMask": "0x1", + "BriefDescription": "Loads with latency value being above 4", + "PEBS": "2", + "MSRValue": "0x4", + "Counter": "3", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "Errata": "BDM100, BDM35", + "PublicDescription": "This event counts loads with latency value being above four.", + "TakenAlone": "1", + "SampleAfterValue": "100003", + "CounterHTOff": "3" + }, + { + "EventCode": "0xCD", + "UMask": "0x1", + "BriefDescription": "Loads with latency value being above 8", + "PEBS": "2", + "MSRValue": "0x8", + "Counter": "3", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "MSRIndex": "0x3F6", + "Errata": "BDM100, BDM35", + "PublicDescription": "This event counts loads with latency value being above eight.", + "TakenAlone": "1", + "SampleAfterValue": "50021", + "CounterHTOff": "3" + }, + { + "EventCode": "0xCD", + "UMask": "0x1", + "BriefDescription": "Loads with latency value being above 16", + "PEBS": "2", + "MSRValue": "0x10", + "Counter": "3", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "MSRIndex": "0x3F6", + "Errata": "BDM100, BDM35", + "PublicDescription": "This event counts loads with latency value being above 16.", + "TakenAlone": "1", + "SampleAfterValue": "20011", + "CounterHTOff": "3" + }, + { + "EventCode": "0xCD", + "UMask": "0x1", + "BriefDescription": "Loads with latency value being above 32", + "PEBS": "2", + "MSRValue": "0x20", + "Counter": "3", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "MSRIndex": "0x3F6", + "Errata": "BDM100, BDM35", + "PublicDescription": "This event counts loads with latency value being above 32.", + "TakenAlone": "1", + "SampleAfterValue": "100007", + "CounterHTOff": "3" + }, + { + "EventCode": "0xCD", + "UMask": "0x1", + "BriefDescription": "Loads with latency value being above 64", + "PEBS": "2", + "MSRValue": "0x40", + "Counter": "3", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "MSRIndex": "0x3F6", + "Errata": "BDM100, BDM35", + "PublicDescription": "This event counts loads with latency value being above 64.", + "TakenAlone": "1", + "SampleAfterValue": "2003", + "CounterHTOff": "3" + }, + { + "EventCode": "0xCD", + "UMask": "0x1", + "BriefDescription": "Loads with latency value being above 128", + "PEBS": "2", + "MSRValue": "0x80", + "Counter": "3", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "MSRIndex": "0x3F6", + "Errata": "BDM100, BDM35", + "PublicDescription": "This event counts loads with latency value being above 128.", + "TakenAlone": "1", + "SampleAfterValue": "1009", + "CounterHTOff": "3" + }, + { + "EventCode": "0xCD", + "UMask": "0x1", + "BriefDescription": "Loads with latency value being above 256", + "PEBS": "2", + "MSRValue": "0x100", + "Counter": "3", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "MSRIndex": "0x3F6", + "Errata": "BDM100, BDM35", + "PublicDescription": "This event counts loads with latency value being above 256.", + "TakenAlone": "1", + "SampleAfterValue": "503", + "CounterHTOff": "3" + }, + { + "EventCode": "0xCD", + "UMask": "0x1", + "BriefDescription": "Loads with latency value being above 512", + "PEBS": "2", + "MSRValue": "0x200", + "Counter": "3", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "MSRIndex": "0x3F6", + "Errata": "BDM100, BDM35", + "PublicDescription": "This event counts loads with latency value being above 512.", + "TakenAlone": "1", + "SampleAfterValue": "101", + "CounterHTOff": "3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all requests that miss in the L3", + "MSRValue": "0x3fbfc08fff", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and clean or shared data is transferred from remote cache", + "MSRValue": "0x087fc007f7", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the modified data is transferred from remote cache", + "MSRValue": "0x103fc007f7", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from remote dram", + "MSRValue": "0x063bc007f7", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from local dram", + "MSRValue": "0x06040007f7", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss in the L3", + "MSRValue": "0x3fbfc007f7", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all demand & prefetch code reads that miss the L3 and the data is returned from local dram", + "MSRValue": "0x0604000244", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all demand & prefetch code reads that miss in the L3", + "MSRValue": "0x3fbfc00244", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram", + "MSRValue": "0x0604000122", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all demand & prefetch RFOs that miss in the L3", + "MSRValue": "0x3fbfc00122", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache", + "MSRValue": "0x087fc00091", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache", + "MSRValue": "0x103fc00091", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram", + "MSRValue": "0x063bc00091", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram", + "MSRValue": "0x0604000091", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all demand & prefetch data reads that miss in the L3", + "MSRValue": "0x3fbfc00091", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that miss in the L3", + "MSRValue": "0x3fbfc00200", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3", + "MSRValue": "0x3fbfc00100", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache", + "MSRValue": "0x103fc00002", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/other.json b/tools/perf/pmu-events/arch/x86/broadwellx/other.json new file mode 100644 index 000000000000..718fcb1db2ee --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/broadwellx/other.json @@ -0,0 +1,44 @@ +[ + { + "EventCode": "0x5C", + "UMask": "0x1", + "BriefDescription": "Unhalted core cycles when the thread is in ring 0", + "Counter": "0,1,2,3", + "EventName": "CPL_CYCLES.RING0", + "PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5C", + "UMask": "0x2", + "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", + "Counter": "0,1,2,3", + "EventName": "CPL_CYCLES.RING123", + "PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EdgeDetect": "1", + "EventCode": "0x5C", + "UMask": "0x1", + "BriefDescription": "Number of intervals between processor halts while thread is in ring 0", + "Counter": "0,1,2,3", + "EventName": "CPL_CYCLES.RING0_TRANS", + "CounterMask": "1", + "PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.", + "SampleAfterValue": "100007", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x63", + "UMask": "0x1", + "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", + "Counter": "0,1,2,3", + "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", + "PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/pipeline.json b/tools/perf/pmu-events/arch/x86/broadwellx/pipeline.json new file mode 100644 index 000000000000..02b4e1035f2d --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/broadwellx/pipeline.json @@ -0,0 +1,1417 @@ +[ + { + "EventCode": "0x00", + "UMask": "0x1", + "BriefDescription": "Instructions retired from execution.", + "Counter": "Fixed counter 1", + "EventName": "INST_RETIRED.ANY", + "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. \nNotes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. \nCounting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.", + "SampleAfterValue": "2000003", + "CounterHTOff": "Fixed counter 1" + }, + { + "EventCode": "0x00", + "UMask": "0x2", + "BriefDescription": "Core cycles when the thread is not in halt state", + "Counter": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.", + "SampleAfterValue": "2000003", + "CounterHTOff": "Fixed counter 2" + }, + { + "EventCode": "0x00", + "UMask": "0x3", + "BriefDescription": "Reference cycles when the core is not in halt state.", + "Counter": "Fixed counter 3", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. \nNote: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", + "SampleAfterValue": "2000003", + "CounterHTOff": "Fixed counter 3" + }, + { + "EventCode": "0x03", + "UMask": "0x2", + "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding", + "Counter": "0,1,2,3", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "PublicDescription": "This event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:\n - preceding store conflicts with the load (incomplete overlap);\n - store forwarding is impossible due to u-arch limitations;\n - preceding lock RMW operations are not forwarded;\n - store has the no-forward bit set (uncacheable/page-split/masked stores);\n - all-blocking stores are used (mostly, fences and port I/O);\nand others.\nThe most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events.\nSee the table of not supported store forwards in the Optimization Guide.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x03", + "UMask": "0x8", + "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "Counter": "0,1,2,3", + "EventName": "LD_BLOCKS.NO_SR", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x07", + "UMask": "0x1", + "BriefDescription": "False dependencies in MOB due to partial compare", + "Counter": "0,1,2,3", + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "PublicDescription": "This event counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0D", + "UMask": "0x8", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread", + "Counter": "0,1,2,3", + "EventName": "INT_MISC.RAT_STALL_CYCLES", + "PublicDescription": "This event counts the number of cycles during which Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the current thread. This also includes the cycles during which the Allocator is serving another thread.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0D", + "UMask": "0x3", + "BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)", + "Counter": "0,1,2,3", + "EventName": "INT_MISC.RECOVERY_CYCLES", + "CounterMask": "1", + "PublicDescription": "Cycles checkpoints in Resource Allocation Table (RAT) are recovering from JEClear or machine clear.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0E", + "UMask": "0x1", + "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)", + "Counter": "0,1,2,3", + "EventName": "UOPS_ISSUED.ANY", + "PublicDescription": "This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS).", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0E", + "UMask": "0x10", + "BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.", + "Counter": "0,1,2,3", + "EventName": "UOPS_ISSUED.FLAGS_MERGE", + "PublicDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive\n added by GSR u-arch.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0E", + "UMask": "0x20", + "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", + "Counter": "0,1,2,3", + "EventName": "UOPS_ISSUED.SLOW_LEA", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0E", + "UMask": "0x40", + "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated.", + "Counter": "0,1,2,3", + "EventName": "UOPS_ISSUED.SINGLE_MUL", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "Invert": "1", + "EventCode": "0x0E", + "UMask": "0x1", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread", + "Counter": "0,1,2,3", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "CounterMask": "1", + "PublicDescription": "This event counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x14", + "UMask": "0x1", + "BriefDescription": "Cycles when divider is busy executing divide operations", + "Counter": "0,1,2,3", + "EventName": "ARITH.FPU_DIV_ACTIVE", + "PublicDescription": "This event counts the number of the divide operations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DIV_ACTIVE to get the number of the divide operations executed.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "UMask": "0x1", + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", + "Counter": "0,1,2,3", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", + "PublicDescription": "This is a fixed-frequency event programmed to general counters. It counts when the core is unhalted at 100 Mhz.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3c", + "UMask": "0x2", + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", + "Counter": "0,1,2,3", + "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x4c", + "UMask": "0x1", + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch", + "Counter": "0,1,2,3", + "EventName": "LOAD_HIT_PRE.SW_PF", + "PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by asm inspection of the nearby instructions.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x4C", + "UMask": "0x2", + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch", + "Counter": "0,1,2,3", + "EventName": "LOAD_HIT_PRE.HW_PF", + "PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the hardware prefetch.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x58", + "UMask": "0x1", + "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.", + "Counter": "0,1,2,3", + "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", + "SampleAfterValue": "1000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x58", + "UMask": "0x2", + "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.", + "Counter": "0,1,2,3", + "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", + "SampleAfterValue": "1000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x58", + "UMask": "0x4", + "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.", + "Counter": "0,1,2,3", + "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", + "SampleAfterValue": "1000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x58", + "UMask": "0x8", + "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.", + "Counter": "0,1,2,3", + "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", + "SampleAfterValue": "1000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5E", + "UMask": "0x1", + "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", + "Counter": "0,1,2,3", + "EventName": "RS_EVENTS.EMPTY_CYCLES", + "PublicDescription": "This event counts cycles during which the reservation station (RS) is empty for the thread.\nNote: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x87", + "UMask": "0x1", + "BriefDescription": "Stalls caused by changing prefix length of the instruction.", + "Counter": "0,1,2,3", + "EventName": "ILD_STALL.LCP", + "PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "UMask": "0x41", + "BriefDescription": "Not taken macro-conditional branches", + "Counter": "0,1,2,3", + "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", + "PublicDescription": "This event counts not taken macro-conditional branch instructions.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "UMask": "0x81", + "BriefDescription": "Taken speculative and retired macro-conditional branches", + "Counter": "0,1,2,3", + "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", + "PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "UMask": "0x82", + "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects", + "Counter": "0,1,2,3", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", + "PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions excluding calls and indirect branches.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "UMask": "0x84", + "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns", + "Counter": "0,1,2,3", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "This event counts taken speculative and retired indirect branches excluding calls and return branches.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "UMask": "0x88", + "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic", + "Counter": "0,1,2,3", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", + "PublicDescription": "This event counts taken speculative and retired indirect branches that have a return mnemonic.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "UMask": "0x90", + "BriefDescription": "Taken speculative and retired direct near calls", + "Counter": "0,1,2,3", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", + "PublicDescription": "This event counts taken speculative and retired direct near calls.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "UMask": "0xa0", + "BriefDescription": "Taken speculative and retired indirect calls", + "Counter": "0,1,2,3", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "PublicDescription": "This event counts taken speculative and retired indirect calls including both register and memory indirect.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "UMask": "0xc1", + "BriefDescription": "Speculative and retired macro-conditional branches", + "Counter": "0,1,2,3", + "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", + "PublicDescription": "This event counts both taken and not taken speculative and retired macro-conditional branch instructions.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "UMask": "0xc2", + "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects", + "Counter": "0,1,2,3", + "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", + "PublicDescription": "This event counts both taken and not taken speculative and retired macro-unconditional branch instructions, excluding calls and indirects.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "UMask": "0xc4", + "BriefDescription": "Speculative and retired indirect branches excluding calls and returns", + "Counter": "0,1,2,3", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches excluding calls and return branches.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "UMask": "0xc8", + "BriefDescription": "Speculative and retired indirect return branches.", + "Counter": "0,1,2,3", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", + "PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches that have a return mnemonic.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "UMask": "0xd0", + "BriefDescription": "Speculative and retired direct near calls", + "Counter": "0,1,2,3", + "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", + "PublicDescription": "This event counts both taken and not taken speculative and retired direct near calls.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "UMask": "0xff", + "BriefDescription": "Speculative and retired branches", + "Counter": "0,1,2,3", + "EventName": "BR_INST_EXEC.ALL_BRANCHES", + "PublicDescription": "This event counts both taken and not taken speculative and retired branch instructions.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "UMask": "0x41", + "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches", + "Counter": "0,1,2,3", + "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", + "PublicDescription": "This event counts not taken speculative and retired mispredicted macro conditional branch instructions.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "UMask": "0x81", + "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches", + "Counter": "0,1,2,3", + "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", + "PublicDescription": "This event counts taken speculative and retired mispredicted macro conditional branch instructions.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "UMask": "0x84", + "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns", + "Counter": "0,1,2,3", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches excluding calls and returns.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "UMask": "0x88", + "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic", + "Counter": "0,1,2,3", + "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", + "PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches that have a return mnemonic.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "UMask": "0xc1", + "BriefDescription": "Speculative and retired mispredicted macro conditional branches", + "Counter": "0,1,2,3", + "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", + "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted macro conditional branch instructions.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "UMask": "0xc4", + "BriefDescription": "Mispredicted indirect branches excluding calls and returns", + "Counter": "0,1,2,3", + "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "This event counts both taken and not taken mispredicted indirect branches excluding calls and returns.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "UMask": "0xff", + "BriefDescription": "Speculative and retired mispredicted macro conditional branches", + "Counter": "0,1,2,3", + "EventName": "BR_MISP_EXEC.ALL_BRANCHES", + "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted branch instructions.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x1", + "BriefDescription": "Cycles per thread when uops are executed in port 0", + "Counter": "0,1,2,3", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x2", + "BriefDescription": "Cycles per thread when uops are executed in port 1", + "Counter": "0,1,2,3", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x4", + "BriefDescription": "Cycles per thread when uops are executed in port 2", + "Counter": "0,1,2,3", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x8", + "BriefDescription": "Cycles per thread when uops are executed in port 3", + "Counter": "0,1,2,3", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x10", + "BriefDescription": "Cycles per thread when uops are executed in port 4", + "Counter": "0,1,2,3", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x20", + "BriefDescription": "Cycles per thread when uops are executed in port 5", + "Counter": "0,1,2,3", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x40", + "BriefDescription": "Cycles per thread when uops are executed in port 6", + "Counter": "0,1,2,3", + "EventName": "UOPS_DISPATCHED_PORT.PORT_6", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x80", + "BriefDescription": "Cycles per thread when uops are executed in port 7", + "Counter": "0,1,2,3", + "EventName": "UOPS_DISPATCHED_PORT.PORT_7", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA2", + "UMask": "0x1", + "BriefDescription": "Resource-related stall cycles", + "Counter": "0,1,2,3", + "EventName": "RESOURCE_STALLS.ANY", + "PublicDescription": "This event counts resource-related stall cycles. Reasons for stalls can be as follows:\n - *any* u-arch structure got full (LB, SB, RS, ROB, BOB, LM, Physical Register Reclaim Table (PRRT), or Physical History Table (PHT) slots)\n - *any* u-arch structure got empty (like INT/SIMD FreeLists)\n - FPU control word (FPCW), MXCSR\nand others. This counts cycles that the pipeline backend blocked uop delivery from the front end.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA2", + "UMask": "0x4", + "BriefDescription": "Cycles stalled due to no eligible RS entry available.", + "Counter": "0,1,2,3", + "EventName": "RESOURCE_STALLS.RS", + "PublicDescription": "This event counts stall cycles caused by absence of eligible entries in the reservation station (RS). This may result from RS overflow, or from RS deallocation because of the RS array Write Port allocation scheme (each RS entry has two write ports instead of four. As a result, empty entries could not be used, although RS is not really full). This counts cycles that the pipeline backend blocked uop delivery from the front end.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA2", + "UMask": "0x8", + "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", + "Counter": "0,1,2,3", + "EventName": "RESOURCE_STALLS.SB", + "PublicDescription": "This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front end.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA2", + "UMask": "0x10", + "BriefDescription": "Cycles stalled due to re-order buffer full.", + "Counter": "0,1,2,3", + "EventName": "RESOURCE_STALLS.ROB", + "PublicDescription": "This event counts ROB full stall cycles. This counts cycles that the pipeline backend blocked uop delivery from the front end.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA3", + "UMask": "0x1", + "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", + "CounterMask": "1", + "PublicDescription": "Counts number of cycles the CPU has at least one pending demand* load request missing the L2 cache.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA3", + "UMask": "0x8", + "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", + "Counter": "2", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", + "CounterMask": "8", + "PublicDescription": "Counts number of cycles the CPU has at least one pending demand load request missing the L1 data cache.", + "SampleAfterValue": "2000003", + "CounterHTOff": "2" + }, + { + "EventCode": "0xA3", + "UMask": "0x2", + "BriefDescription": "Cycles while memory subsystem has an outstanding load.", + "Counter": "0,1,2,3", + "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", + "CounterMask": "2", + "PublicDescription": "Counts number of cycles the CPU has at least one pending demand load request (that is cycles with non-completed load waiting for its data from memory subsystem).", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA3", + "UMask": "0x4", + "BriefDescription": "Total execution stalls", + "Counter": "0,1,2,3", + "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", + "CounterMask": "4", + "PublicDescription": "Counts number of cycles nothing is executed on any execution port.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xA3", + "UMask": "0x5", + "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", + "CounterMask": "5", + "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand* load request missing the L2 cache.(as a footprint) * includes also L1 HW prefetch requests that may or may not be required by demands.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xA3", + "UMask": "0x6", + "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", + "Counter": "0,1,2,3", + "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", + "CounterMask": "6", + "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xA3", + "UMask": "0xc", + "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "Counter": "2", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", + "CounterMask": "12", + "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request missing the L1 data cache.", + "SampleAfterValue": "2000003", + "CounterHTOff": "2" + }, + { + "EventCode": "0xA8", + "UMask": "0x1", + "BriefDescription": "Number of Uops delivered by the LSD.", + "Counter": "0,1,2,3", + "EventName": "LSD.UOPS", + "PublicDescription": "Number of Uops delivered by the LSD. ", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB1", + "UMask": "0x1", + "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED.THREAD", + "PublicDescription": "Number of uops to be executed per-thread each cycle.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB1", + "UMask": "0x2", + "BriefDescription": "Number of uops executed on the core.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED.CORE", + "PublicDescription": "Number of uops executed from any thread.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "Invert": "1", + "EventCode": "0xB1", + "UMask": "0x1", + "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED.STALL_CYCLES", + "CounterMask": "1", + "PublicDescription": "This event counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC0", + "UMask": "0x0", + "BriefDescription": "Number of instructions retired. General Counter - architectural event", + "Counter": "0,1,2,3", + "EventName": "INST_RETIRED.ANY_P", + "Errata": "BDM61", + "PublicDescription": "This event counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two).", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC0", + "UMask": "0x2", + "BriefDescription": "FP operations retired. X87 FP operations that have no exceptions:", + "Counter": "0,1,2,3", + "EventName": "INST_RETIRED.X87", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC0", + "UMask": "0x1", + "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution", + "PEBS": "2", + "Counter": "1", + "EventName": "INST_RETIRED.PREC_DIST", + "Errata": "BDM11, BDM55", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts instructions retired.", + "SampleAfterValue": "2000003", + "CounterHTOff": "1" + }, + { + "EventCode": "0xC1", + "UMask": "0x40", + "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.", + "Counter": "0,1,2,3", + "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC2", + "UMask": "0x1", + "BriefDescription": "Actually retired uops.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "UOPS_RETIRED.ALL", + "PublicDescription": "This event counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC2", + "UMask": "0x2", + "BriefDescription": "Retirement slots used.", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts the number of retirement slots used.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "Invert": "1", + "EventCode": "0xC2", + "UMask": "0x1", + "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "CounterMask": "1", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts cycles without actually retired uops.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "Invert": "1", + "EventCode": "0xC2", + "UMask": "0x1", + "BriefDescription": "Cycles with less than 10 actually retired uops.", + "Counter": "0,1,2,3", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "CounterMask": "10", + "PublicDescription": "Number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC3", + "UMask": "0x1", + "BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.", + "Counter": "0,1,2,3", + "EventName": "MACHINE_CLEARS.CYCLES", + "PublicDescription": "This event counts both thread-specific (TS) and all-thread (AT) nukes.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC3", + "UMask": "0x4", + "BriefDescription": "Self-modifying code (SMC) detected.", + "Counter": "0,1,2,3", + "EventName": "MACHINE_CLEARS.SMC", + "PublicDescription": "This event counts self-modifying code (SMC) detected, which causes a machine clear.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC3", + "UMask": "0x20", + "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.", + "Counter": "0,1,2,3", + "EventName": "MACHINE_CLEARS.MASKMOV", + "PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC4", + "UMask": "0x1", + "BriefDescription": "Conditional branch instructions retired.", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "BR_INST_RETIRED.CONDITIONAL", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts conditional branch instructions retired.", + "SampleAfterValue": "400009", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC4", + "UMask": "0x2", + "BriefDescription": "Direct and indirect near call instructions retired.", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts both direct and indirect near call instructions retired.", + "SampleAfterValue": "100007", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC4", + "UMask": "0x0", + "BriefDescription": "All (macro) branch instructions retired.", + "Counter": "0,1,2,3", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "PublicDescription": "This event counts all (macro) branch instructions retired.", + "SampleAfterValue": "400009", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC4", + "UMask": "0x8", + "BriefDescription": "Return instructions retired.", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts return instructions retired.", + "SampleAfterValue": "100007", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC4", + "UMask": "0x10", + "BriefDescription": "Not taken branch instructions retired.", + "Counter": "0,1,2,3", + "EventName": "BR_INST_RETIRED.NOT_TAKEN", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts not taken branch instructions retired.", + "SampleAfterValue": "400009", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC4", + "UMask": "0x20", + "BriefDescription": "Taken branch instructions retired.", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts taken branch instructions retired.", + "SampleAfterValue": "400009", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC4", + "UMask": "0x40", + "BriefDescription": "Far branch instructions retired.", + "Counter": "0,1,2,3", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "Errata": "BDW98", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts far branch instructions retired.", + "SampleAfterValue": "100007", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC4", + "UMask": "0x4", + "BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS)", + "PEBS": "2", + "Counter": "0,1,2,3", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", + "Errata": "BDW98", + "PublicDescription": "This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired.", + "SampleAfterValue": "400009", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC5", + "UMask": "0x1", + "BriefDescription": "Mispredicted conditional branch instructions retired.", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "BR_MISP_RETIRED.CONDITIONAL", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted conditional branch instructions retired.", + "SampleAfterValue": "400009", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC5", + "UMask": "0x0", + "BriefDescription": "All mispredicted macro branch instructions retired.", + "Counter": "0,1,2,3", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PublicDescription": "This event counts all mispredicted macro branch instructions retired.", + "SampleAfterValue": "400009", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC5", + "UMask": "0x8", + "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "BR_MISP_RETIRED.RET", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired.", + "SampleAfterValue": "100007", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC5", + "UMask": "0x4", + "BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)", + "PEBS": "2", + "Counter": "0,1,2,3", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", + "PublicDescription": "This is a precise version of BR_MISP_RETIRED.ALL_BRANCHES that counts all mispredicted macro branch instructions retired.", + "SampleAfterValue": "400009", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xCC", + "UMask": "0x20", + "BriefDescription": "Count cases of saving new LBR", + "Counter": "0,1,2,3", + "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", + "PublicDescription": "This event counts cases of saving new LBR records by hardware. This assumes proper enabling of LBRs and takes into account LBR filtering done by the LBR_SELECT register.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "UMask": "0x0", + "BriefDescription": "Thread cycles when thread is not in halt state", + "Counter": "0,1,2,3", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "UMask": "0xa0", + "BriefDescription": "Taken speculative and retired mispredicted indirect calls.", + "Counter": "0,1,2,3", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x1", + "BriefDescription": "Cycles per core when uops are exectuted in port 0.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", + "AnyThread": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x2", + "BriefDescription": "Cycles per core when uops are exectuted in port 1.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", + "AnyThread": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x4", + "BriefDescription": "Cycles per core when uops are dispatched to port 2.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE", + "AnyThread": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x8", + "BriefDescription": "Cycles per core when uops are dispatched to port 3.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE", + "AnyThread": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x10", + "BriefDescription": "Cycles per core when uops are exectuted in port 4.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", + "AnyThread": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x20", + "BriefDescription": "Cycles per core when uops are exectuted in port 5.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", + "AnyThread": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x40", + "BriefDescription": "Cycles per core when uops are exectuted in port 6.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", + "AnyThread": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x80", + "BriefDescription": "Cycles per core when uops are dispatched to port 7.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE", + "AnyThread": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC5", + "UMask": "0x20", + "BriefDescription": "number of near branch instructions retired that were mispredicted and taken.", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "PublicDescription": "Number of near branch instructions retired that were mispredicted and taken.", + "SampleAfterValue": "400009", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB1", + "UMask": "0x1", + "BriefDescription": "Cycles where at least 1 uop was executed per-thread.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", + "CounterMask": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB1", + "UMask": "0x1", + "BriefDescription": "Cycles where at least 2 uops were executed per-thread.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", + "CounterMask": "2", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB1", + "UMask": "0x1", + "BriefDescription": "Cycles where at least 3 uops were executed per-thread.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", + "CounterMask": "3", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB1", + "UMask": "0x1", + "BriefDescription": "Cycles where at least 4 uops were executed per-thread.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", + "CounterMask": "4", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xe6", + "UMask": "0x1f", + "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", + "Counter": "0,1,2,3", + "EventName": "BACLEARS.ANY", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA3", + "UMask": "0x8", + "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", + "Counter": "2", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", + "CounterMask": "8", + "SampleAfterValue": "2000003", + "CounterHTOff": "2" + }, + { + "EventCode": "0xA3", + "UMask": "0x1", + "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", + "CounterMask": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA3", + "UMask": "0x2", + "BriefDescription": "Cycles while memory subsystem has an outstanding load.", + "Counter": "0,1,2,3", + "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "CounterMask": "2", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xA3", + "UMask": "0x4", + "BriefDescription": "Total execution stalls.", + "Counter": "0,1,2,3", + "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", + "CounterMask": "4", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA3", + "UMask": "0xc", + "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "Counter": "2", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", + "CounterMask": "12", + "SampleAfterValue": "2000003", + "CounterHTOff": "2" + }, + { + "EventCode": "0xA3", + "UMask": "0x5", + "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", + "CounterMask": "5", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA3", + "UMask": "0x6", + "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", + "Counter": "0,1,2,3", + "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "CounterMask": "6", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EdgeDetect": "1", + "EventCode": "0xC3", + "UMask": "0x1", + "BriefDescription": "Number of machine clears (nukes) of any type.", + "Counter": "0,1,2,3", + "EventName": "MACHINE_CLEARS.COUNT", + "CounterMask": "1", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA8", + "UMask": "0x1", + "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", + "Counter": "0,1,2,3", + "EventName": "LSD.CYCLES_4_UOPS", + "CounterMask": "4", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EdgeDetect": "1", + "Invert": "1", + "EventCode": "0x5E", + "UMask": "0x1", + "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.", + "Counter": "0,1,2,3", + "EventName": "RS_EVENTS.EMPTY_END", + "CounterMask": "1", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA8", + "UMask": "0x1", + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", + "Counter": "0,1,2,3", + "EventName": "LSD.CYCLES_ACTIVE", + "CounterMask": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x1", + "BriefDescription": "Cycles per thread when uops are executed in port 0", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_0", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x2", + "BriefDescription": "Cycles per thread when uops are executed in port 1", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_1", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x4", + "BriefDescription": "Cycles per thread when uops are executed in port 2", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_2", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x8", + "BriefDescription": "Cycles per thread when uops are executed in port 3", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_3", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x10", + "BriefDescription": "Cycles per thread when uops are executed in port 4", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_4", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x20", + "BriefDescription": "Cycles per thread when uops are executed in port 5", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_5", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x40", + "BriefDescription": "Cycles per thread when uops are executed in port 6", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_6", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x80", + "BriefDescription": "Cycles per thread when uops are executed in port 7", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_7", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA0", + "UMask": "0x3", + "BriefDescription": "Micro-op dispatches cancelled due to insufficient SIMD physical register file read ports", + "Counter": "0,1,2,3", + "EventName": "UOP_DISPATCHES_CANCELLED.SIMD_PRF", + "PublicDescription": "This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file. The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more information.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x00", + "UMask": "0x2", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "Counter": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", + "AnyThread": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "Fixed counter 2" + }, + { + "EventCode": "0x3C", + "UMask": "0x0", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "Counter": "0,1,2,3", + "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", + "AnyThread": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "UMask": "0x1", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", + "Counter": "0,1,2,3", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", + "AnyThread": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0D", + "UMask": "0x3", + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).", + "Counter": "0,1,2,3", + "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", + "AnyThread": "1", + "CounterMask": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xb1", + "UMask": "0x2", + "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "CounterMask": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xb1", + "UMask": "0x2", + "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "CounterMask": "2", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xb1", + "UMask": "0x2", + "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "CounterMask": "3", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xb1", + "UMask": "0x2", + "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "CounterMask": "4", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "Invert": "1", + "EventCode": "0xb1", + "UMask": "0x2", + "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "UMask": "0x1", + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", + "Counter": "0,1,2,3", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "UMask": "0x1", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", + "Counter": "0,1,2,3", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", + "AnyThread": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "UMask": "0x2", + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", + "Counter": "0,1,2,3", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/virtual-memory.json b/tools/perf/pmu-events/arch/x86/broadwellx/virtual-memory.json new file mode 100644 index 000000000000..5ce8b67ba076 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/broadwellx/virtual-memory.json @@ -0,0 +1,388 @@ +[ + { + "EventCode": "0x08", + "UMask": "0x1", + "BriefDescription": "Load misses in all DTLB levels that cause page walks", + "Counter": "0,1,2,3", + "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", + "Errata": "BDM69", + "PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x08", + "UMask": "0x2", + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).", + "Counter": "0,1,2,3", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "Errata": "BDM69", + "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x08", + "UMask": "0x4", + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).", + "Counter": "0,1,2,3", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "Errata": "BDM69", + "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x08", + "UMask": "0x8", + "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)", + "Counter": "0,1,2,3", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", + "Errata": "BDM69", + "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x08", + "UMask": "0x10", + "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", + "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", + "Errata": "BDM69", + "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x08", + "UMask": "0x20", + "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).", + "Counter": "0,1,2,3", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x08", + "UMask": "0x40", + "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).", + "Counter": "0,1,2,3", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "UMask": "0x1", + "BriefDescription": "Store misses in all DTLB levels that cause page walks", + "Counter": "0,1,2,3", + "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", + "Errata": "BDM69", + "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "UMask": "0x2", + "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)", + "Counter": "0,1,2,3", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "Errata": "BDM69", + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "UMask": "0x4", + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)", + "Counter": "0,1,2,3", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "Errata": "BDM69", + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "UMask": "0x8", + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (1G)", + "Counter": "0,1,2,3", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", + "Errata": "BDM69", + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "UMask": "0x10", + "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", + "EventName": "DTLB_STORE_MISSES.WALK_DURATION", + "Errata": "BDM69", + "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "UMask": "0x20", + "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K).", + "Counter": "0,1,2,3", + "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "UMask": "0x40", + "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M).", + "Counter": "0,1,2,3", + "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x4F", + "UMask": "0x10", + "BriefDescription": "Cycle count for an Extended Page table walk.", + "Counter": "0,1,2,3", + "EventName": "EPT.WALK_CYCLES", + "PublicDescription": "This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "UMask": "0x1", + "BriefDescription": "Misses at all ITLB levels that cause page walks", + "Counter": "0,1,2,3", + "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", + "Errata": "BDM69", + "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "UMask": "0x2", + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", + "Counter": "0,1,2,3", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "Errata": "BDM69", + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "UMask": "0x4", + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", + "Counter": "0,1,2,3", + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "Errata": "BDM69", + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "UMask": "0x8", + "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)", + "Counter": "0,1,2,3", + "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", + "Errata": "BDM69", + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "UMask": "0x10", + "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", + "EventName": "ITLB_MISSES.WALK_DURATION", + "Errata": "BDM69", + "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "UMask": "0x20", + "BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K).", + "Counter": "0,1,2,3", + "EventName": "ITLB_MISSES.STLB_HIT_4K", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "UMask": "0x40", + "BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M).", + "Counter": "0,1,2,3", + "EventName": "ITLB_MISSES.STLB_HIT_2M", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xAE", + "UMask": "0x1", + "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", + "Counter": "0,1,2,3", + "EventName": "ITLB.ITLB_FLUSH", + "PublicDescription": "This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).", + "SampleAfterValue": "100007", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xBC", + "UMask": "0x11", + "BriefDescription": "Number of DTLB page walker hits in the L1+FB.", + "Counter": "0,1,2,3", + "EventName": "PAGE_WALKER_LOADS.DTLB_L1", + "Errata": "BDM69, BDM98", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBC", + "UMask": "0x21", + "BriefDescription": "Number of ITLB page walker hits in the L1+FB.", + "Counter": "0,1,2,3", + "EventName": "PAGE_WALKER_LOADS.ITLB_L1", + "Errata": "BDM69, BDM98", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBC", + "UMask": "0x12", + "BriefDescription": "Number of DTLB page walker hits in the L2.", + "Counter": "0,1,2,3", + "EventName": "PAGE_WALKER_LOADS.DTLB_L2", + "Errata": "BDM69, BDM98", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBC", + "UMask": "0x22", + "BriefDescription": "Number of ITLB page walker hits in the L2.", + "Counter": "0,1,2,3", + "EventName": "PAGE_WALKER_LOADS.ITLB_L2", + "Errata": "BDM69, BDM98", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBC", + "UMask": "0x14", + "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP.", + "Counter": "0,1,2,3", + "EventName": "PAGE_WALKER_LOADS.DTLB_L3", + "Errata": "BDM69, BDM98", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBC", + "UMask": "0x24", + "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP.", + "Counter": "0,1,2,3", + "EventName": "PAGE_WALKER_LOADS.ITLB_L3", + "Errata": "BDM69, BDM98", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBC", + "UMask": "0x18", + "BriefDescription": "Number of DTLB page walker hits in Memory.", + "Counter": "0,1,2,3", + "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY", + "Errata": "BDM69, BDM98", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBD", + "UMask": "0x1", + "BriefDescription": "DTLB flush attempts of the thread-specific entries", + "Counter": "0,1,2,3", + "EventName": "TLB_FLUSH.DTLB_THREAD", + "PublicDescription": "This event counts the number of DTLB flush attempts of the thread-specific entries.", + "SampleAfterValue": "100007", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xBD", + "UMask": "0x20", + "BriefDescription": "STLB flush attempts", + "Counter": "0,1,2,3", + "EventName": "TLB_FLUSH.STLB_ANY", + "PublicDescription": "This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).", + "SampleAfterValue": "100007", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x08", + "UMask": "0xe", + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", + "Counter": "0,1,2,3", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "Errata": "BDM69", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x08", + "UMask": "0x60", + "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.", + "Counter": "0,1,2,3", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "UMask": "0xe", + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.", + "Counter": "0,1,2,3", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "Errata": "BDM69", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "UMask": "0x60", + "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", + "Counter": "0,1,2,3", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "UMask": "0xe", + "BriefDescription": "Misses in all ITLB levels that cause completed page walks.", + "Counter": "0,1,2,3", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "Errata": "BDM69", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "UMask": "0x60", + "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.", + "Counter": "0,1,2,3", + "EventName": "ITLB_MISSES.STLB_HIT", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/goldmont/cache.json b/tools/perf/pmu-events/arch/x86/goldmont/cache.json new file mode 100644 index 000000000000..4e02e1e5e70d --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/goldmont/cache.json @@ -0,0 +1,1127 @@ +[ + { + "CollectPEBSRecord": "1", + "PublicDescription": "Counts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the intra-die interconnect (IDI) fabric. The XQ may reject transactions from the L2Q (non-cacheable requests), L2 misses and L2 write-back victims.", + "EventCode": "0x30", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "L2_REJECT_XQ.ALL", + "SampleAfterValue": "200003", + "BriefDescription": "Requests rejected by the XQ" + }, + { + "CollectPEBSRecord": "1", + "PublicDescription": "Counts the number of demand and L1 prefetcher requests rejected by the L2Q due to a full or nearly full condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to insure fairness between cores, or to delay a core's dirty eviction when the address conflicts with incoming external snoops.", + "EventCode": "0x31", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "CORE_REJECT_L2Q.ALL", + "SampleAfterValue": "200003", + "BriefDescription": "Requests rejected by the L2Q " + }, + { + "CollectPEBSRecord": "1", + "PublicDescription": "Counts memory requests originating from the core that reference a cache line in the L2 cache.", + "EventCode": "0x2E", + "Counter": "0,1,2,3", + "UMask": "0x4f", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "SampleAfterValue": "200003", + "BriefDescription": "L2 cache requests" + }, + { + "CollectPEBSRecord": "1", + "PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.", + "EventCode": "0x2E", + "Counter": "0,1,2,3", + "UMask": "0x41", + "EventName": "LONGEST_LAT_CACHE.MISS", + "SampleAfterValue": "200003", + "BriefDescription": "L2 cache request misses" + }, + { + "CollectPEBSRecord": "1", + "PublicDescription": "Counts cycles that an ICache miss is outstanding, and instruction fetch is stalled. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes, while an Icache miss outstanding. Note this event is not the same as cycles to retrieve an instruction due to an Icache miss. Rather, it is the part of the Instruction Cache (ICache) miss time where no bytes are available for the decoder.", + "EventCode": "0x86", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES", + "SampleAfterValue": "200003", + "BriefDescription": "Cycles where code-fetch is stalled and an ICache miss is outstanding. This is not the same as an ICache Miss." + }, + { + "PEBS": "2", + "CollectPEBSRecord": "2", + "PublicDescription": "Counts the number of load uops retired.", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x81", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "SampleAfterValue": "200003", + "BriefDescription": "Load uops retired (Precise event capable)" + }, + { + "PEBS": "2", + "CollectPEBSRecord": "2", + "PublicDescription": "Counts the number of store uops retired.", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x82", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "SampleAfterValue": "200003", + "BriefDescription": "Store uops retired (Precise event capable)" + }, + { + "PEBS": "2", + "CollectPEBSRecord": "2", + "PublicDescription": "Counts the number of memory uops retired that is either a loads or a store or both.", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x83", + "EventName": "MEM_UOPS_RETIRED.ALL", + "SampleAfterValue": "200003", + "BriefDescription": "Memory uops retired (Precise event capable)" + }, + { + "PEBS": "2", + "CollectPEBSRecord": "2", + "PublicDescription": "Counts locked memory uops retired. This includes \"regular\" locks and bus locks. (To specifically count bus locks only, see the Offcore response event.) A locked access is one with a lock prefix, or an exchange to memory. See the SDM for a complete description of which memory load accesses are locks.", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x21", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "SampleAfterValue": "200003", + "BriefDescription": "Locked load uops retired (Precise event capable)" + }, + { + "PEBS": "2", + "CollectPEBSRecord": "2", + "PublicDescription": "Counts load uops retired where the data requested spans a 64 byte cache line boundary.", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x41", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "SampleAfterValue": "200003", + "BriefDescription": "Load uops retired that split a cache-line (Precise event capable)" + }, + { + "PEBS": "2", + "CollectPEBSRecord": "2", + "PublicDescription": "Counts store uops retired where the data requested spans a 64 byte cache line boundary.", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x42", + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "SampleAfterValue": "200003", + "BriefDescription": "Stores uops retired that split a cache-line (Precise event capable)" + }, + { + "PEBS": "2", + "CollectPEBSRecord": "2", + "PublicDescription": "Counts memory uops retired where the data requested spans a 64 byte cache line boundary.", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x43", + "EventName": "MEM_UOPS_RETIRED.SPLIT", + "SampleAfterValue": "200003", + "BriefDescription": "Memory uops retired that split a cache-line (Precise event capable)" + }, + { + "PEBS": "2", + "CollectPEBSRecord": "2", + "PublicDescription": "Counts load uops retired that hit the L1 data cache.", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "SampleAfterValue": "200003", + "BriefDescription": "Load uops retired that hit L1 data cache (Precise event capable)" + }, + { + "PEBS": "2", + "CollectPEBSRecord": "2", + "PublicDescription": "Counts load uops retired that miss the L1 data cache.", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", + "SampleAfterValue": "200003", + "BriefDescription": "Load uops retired that missed L1 data cache (Precise event capable)" + }, + { + "PEBS": "2", + "CollectPEBSRecord": "2", + "PublicDescription": "Counts load uops retired that hit in the L2 cache.", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "SampleAfterValue": "200003", + "BriefDescription": "Load uops retired that hit L2 (Precise event capable)" + }, + { + "PEBS": "2", + "CollectPEBSRecord": "2", + "PublicDescription": "Counts load uops retired that miss in the L2 cache.", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "SampleAfterValue": "200003", + "BriefDescription": "Load uops retired that missed L2 (Precise event capable)" + }, + { + "PEBS": "2", + "CollectPEBSRecord": "2", + "PublicDescription": "Counts load uops retired where the cache line containing the data was in the modified state of another core or modules cache (HITM). More specifically, this means that when the load address was checked by other caching agents (typically another processor) in the system, one of those caching agents indicated that they had a dirty copy of the data. Loads that obtain a HITM response incur greater latency than most is typical for a load. In addition, since HITM indicates that some other processor had this data in its cache, it implies that the data was shared between processors, or potentially was a lock or semaphore value. This event is useful for locating sharing, false sharing, and contended locks.", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "MEM_LOAD_UOPS_RETIRED.HITM", + "SampleAfterValue": "200003", + "BriefDescription": "Memory uop retired where cross core or cross module HITM occurred (Precise event capable)" + }, + { + "PEBS": "2", + "CollectPEBSRecord": "2", + "PublicDescription": "Counts memory load uops retired where the data is retrieved from the WCB (or fill buffer), indicating that the load found its data while that data was in the process of being brought into the L1 cache. Typically a load will receive this indication when some other load or prefetch missed the L1 cache and was in the process of retrieving the cache line containing the data, but that process had not yet finished (and written the data back to the cache). For example, consider load X and Y, both referencing the same cache line that is not in the L1 cache. If load X misses cache first, it obtains and WCB (or fill buffer) and begins the process of requesting the data. When load Y requests the data, it will either hit the WCB, or the L1 cache, depending on exactly what time the request to Y occurs.", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "MEM_LOAD_UOPS_RETIRED.WCB_HIT", + "SampleAfterValue": "200003", + "BriefDescription": "Loads retired that hit WCB (Precise event capable)" + }, + { + "PEBS": "2", + "CollectPEBSRecord": "2", + "PublicDescription": "Counts memory load uops retired where the data is retrieved from DRAM. Event is counted at retirement, so the speculative loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit DRAM, hit in the WCB or receive a HITM response.", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT", + "SampleAfterValue": "200003", + "BriefDescription": "Loads retired that came from DRAM (Precise event capable)" + }, + { + "CollectPEBSRecord": "1", + "PublicDescription": "Counts when a modified (dirty) cache line is evicted from the data L1 cache and needs to be written back to memory. No count will occur if the evicted line is clean, and hence does not require a writeback.", + "EventCode": "0x51", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "DL1.DIRTY_EVICTION", + "SampleAfterValue": "200003", + "BriefDescription": "L1 Cache evictions for dirty data" + }, + { + "CollectPEBSRecord": "1", + "EventCode": "0xB7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE", + "SampleAfterValue": "100007", + "BriefDescription": "Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x36000032b7 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x10000032b7 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x04000032b7 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x02000032b7 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x00000432b7 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that hit the L2 cache.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3600000022 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000000022 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0400000022 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0200000022 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000040022 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that hit the L2 cache.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3600003091", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts data reads (demand & prefetch) that miss the L2 cache.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000003091", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0400003091", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0200003091", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts data reads (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000043091", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts data reads (demand & prefetch) that hit the L2 cache.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3600003010 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000003010 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0400003010 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0200003010 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers that true miss for the L2 cache with a snoop miss in the other processor module. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000043010 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers that hit the L2 cache.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000008000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0400008000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0200008000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts requests to the uncore subsystem that true miss for the L2 cache with a snoop miss in the other processor module. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000048000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts requests to the uncore subsystem that hit the L2 cache.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000018000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts requests to the uncore subsystem that have any transaction responses from the uncore subsystem.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3600004800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region that miss the L2 cache.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000044800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region that hit the L2 cache.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3600004000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000004000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0400004000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0200004000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region that true miss for the L2 cache with a snoop miss in the other processor module. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000044000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region that hit the L2 cache.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3600002000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000002000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0400002000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0200002000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000042000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that hit the L2 cache.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3600001000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts data cache lines requests by software prefetch instructions that miss the L2 cache.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000001000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0400001000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0200001000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts data cache lines requests by software prefetch instructions that true miss for the L2 cache with a snoop miss in the other processor module. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000041000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts data cache lines requests by software prefetch instructions that hit the L2 cache.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3600000800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000000800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0400000800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0200000800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that true miss for the L2 cache with a snoop miss in the other processor module. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000040800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that hit the L2 cache.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000010400 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts bus lock and split lock requests that have any transaction responses from the uncore subsystem.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3600000100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts the number of demand write requests (RFO) generated by a write to partial data cache line, including the writes to uncacheable (UC) and write through (WT), and write protected (WP) types of memory that miss the L2 cache.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3600000080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand data partial reads, including data in uncacheable (UC) or uncacheable write combining (USWC) memory types that miss the L2 cache.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3600000020 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000000020 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0400000020 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0200000020 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that true miss for the L2 cache with a snoop miss in the other processor module. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000040020 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that hit the L2 cache.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3600000010 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000000010 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0400000010 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0200000010 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000040010 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that hit the L2 cache.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3600000008 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.ANY", + "MSRIndex": "0x1a6", + "SampleAfterValue": "100007", + "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000000008 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6", + "SampleAfterValue": "100007", + "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0400000008 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6", + "SampleAfterValue": "100007", + "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0200000008 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6", + "SampleAfterValue": "100007", + "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that true miss for the L2 cache with a snoop miss in the other processor module. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000040008 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.L2_HIT", + "MSRIndex": "0x1a6", + "SampleAfterValue": "100007", + "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that hit the L2 cache.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4000000004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that are outstanding, per cycle, from the time of the L2 miss to when any response is received.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3600000004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0400000004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0200000004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that true miss for the L2 cache with a snoop miss in the other processor module. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000040004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that hit the L2 cache.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4000000002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING", + "MSRIndex": "0x1a6", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that are outstanding, per cycle, from the time of the L2 miss to when any response is received.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3600000002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000000002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0400000002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0200000002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that true miss for the L2 cache with a snoop miss in the other processor module. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000040002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that hit the L2 cache.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4000000001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand cacheable data reads of full cache lines that are outstanding, per cycle, from the time of the L2 miss to when any response is received.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3600000001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cache.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000000001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0400000001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0200000001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand cacheable data reads of full cache lines that true miss for the L2 cache with a snoop miss in the other processor module. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000040001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand cacheable data reads of full cache lines that hit the L2 cache.", + "Offcore": "1" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/goldmont/frontend.json b/tools/perf/pmu-events/arch/x86/goldmont/frontend.json new file mode 100644 index 000000000000..9ba08518649e --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/goldmont/frontend.json @@ -0,0 +1,52 @@ +[ + { + "CollectPEBSRecord": "1", + "PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is in the ICache (hit). The event strives to count on a cache line basis, so that multiple accesses which hit in a single cache line count as one ICACHE.HIT. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture.", + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ICACHE.HIT", + "SampleAfterValue": "200003", + "BriefDescription": "References per ICache line that are available in the ICache (hit). This event counts differently than Intel processors based on Silvermont microarchitecture" + }, + { + "CollectPEBSRecord": "1", + "PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is not in the ICache (miss). The event strives to count on a cache line basis, so that multiple accesses which miss in a single cache line count as one ICACHE.MISS. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is not in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture.", + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "ICACHE.MISSES", + "SampleAfterValue": "200003", + "BriefDescription": "References per ICache line that are not available in the ICache (miss). This event counts differently than Intel processors based on Silvermont microarchitecture" + }, + { + "CollectPEBSRecord": "1", + "PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line. The event strives to count on a cache line basis, so that multiple fetches to a single cache line count as one ICACHE.ACCESS. Specifically, the event counts when accesses from straight line code crosses the cache line boundary, or when a branch target is to a new line.\r\nThis event counts differently than Intel processors based on Silvermont microarchitecture.", + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x3", + "EventName": "ICACHE.ACCESSES", + "SampleAfterValue": "200003", + "BriefDescription": "References per ICache line. This event counts differently than Intel processors based on Silvermont microarchitecture" + }, + { + "CollectPEBSRecord": "1", + "PublicDescription": "Counts the number of times the Microcode Sequencer (MS) starts a flow of uops from the MSROM. It does not count every time a uop is read from the MSROM. The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine. Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort that initiates a flow of uops. The event will count MS startups for uops that are speculative, and subsequently cleared by branch mispredict or a machine clear.", + "EventCode": "0xE7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MS_DECODED.MS_ENTRY", + "SampleAfterValue": "200003", + "BriefDescription": "MS decode starts" + }, + { + "CollectPEBSRecord": "1", + "PublicDescription": "Counts the number of times the prediction (from the predecode cache) for instruction length is incorrect.", + "EventCode": "0xE9", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "DECODE_RESTRICTION.PREDECODE_WRONG", + "SampleAfterValue": "200003", + "BriefDescription": "Decode restrictions due to predicting wrong instruction length" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/goldmont/memory.json b/tools/perf/pmu-events/arch/x86/goldmont/memory.json new file mode 100644 index 000000000000..ac8b0d365a19 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/goldmont/memory.json @@ -0,0 +1,34 @@ +[ + { + "CollectPEBSRecord": "1", + "PublicDescription": "Counts machine clears due to memory ordering issues. This occurs when a snoop request happens and the machine is uncertain if memory ordering will be preserved - as another core is in the process of modifying the data.", + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "SampleAfterValue": "200003", + "BriefDescription": "Machine clears due to memory ordering issue" + }, + { + "PEBS": "2", + "CollectPEBSRecord": "2", + "PublicDescription": "Counts when a memory load of a uop spans a page boundary (a split) is retired.", + "EventCode": "0x13", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT", + "SampleAfterValue": "200003", + "BriefDescription": "Load uops that split a page (Precise event capable)" + }, + { + "PEBS": "2", + "CollectPEBSRecord": "2", + "PublicDescription": "Counts when a memory store of a uop spans a page boundary (a split) is retired.", + "EventCode": "0x13", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT", + "SampleAfterValue": "200003", + "BriefDescription": "Store uops that split a page (Precise event capable)" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/goldmont/other.json b/tools/perf/pmu-events/arch/x86/goldmont/other.json new file mode 100644 index 000000000000..df25ca9542f1 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/goldmont/other.json @@ -0,0 +1,52 @@ +[ + { + "CollectPEBSRecord": "1", + "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed because of a full resource in the backend. Including but not limited to resources such as the Re-order Buffer (ROB), reservation stations (RS), load/store buffers, physical registers, or any other needed machine resource that is currently unavailable. Note that uops must be available for consumption in order for this event to fire. If a uop is not available (Instruction Queue is empty), this event will not count.", + "EventCode": "0xCA", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RESOURCE_FULL", + "SampleAfterValue": "200003", + "BriefDescription": "Unfilled issue slots per cycle because of a full resource in the backend" + }, + { + "CollectPEBSRecord": "1", + "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by the backend because allocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g. the event is relevant during certain microcode flows). Counts all issue slots blocked while within this window including slots where uops were not available in the Instruction Queue.", + "EventCode": "0xCA", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RECOVERY", + "SampleAfterValue": "200003", + "BriefDescription": "Unfilled issue slots per cycle to recover" + }, + { + "CollectPEBSRecord": "1", + "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by the backend due to either a full resource in the backend (RESOURCE_FULL) or due to the processor recovering from some event (RECOVERY).", + "EventCode": "0xCA", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "ISSUE_SLOTS_NOT_CONSUMED.ANY", + "SampleAfterValue": "200003", + "BriefDescription": "Unfilled issue slots per cycle" + }, + { + "CollectPEBSRecord": "2", + "PublicDescription": "Counts hardware interrupts received by the processor.", + "EventCode": "0xCB", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "HW_INTERRUPTS.RECEIVED", + "SampleAfterValue": "200003", + "BriefDescription": "Hardware interrupts received (Precise event capable)" + }, + { + "CollectPEBSRecord": "2", + "PublicDescription": "Counts core cycles during which there are pending interrupts, but interrupts are masked (EFLAGS.IF = 0).", + "EventCode": "0xCB", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "HW_INTERRUPTS.PENDING_AND_MASKED", + "SampleAfterValue": "200003", + "BriefDescription": "Cycles pending interrupts are masked (Precise event capable)" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/goldmont/pipeline.json b/tools/perf/pmu-events/arch/x86/goldmont/pipeline.json new file mode 100644 index 000000000000..07f00041f56f --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/goldmont/pipeline.json @@ -0,0 +1,433 @@ +[ + { + "PEBS": "2", + "CollectPEBSRecord": "2", + "PublicDescription": "Counts branch instructions retired for all branch types. This is an architectural performance event.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "SampleAfterValue": "200003", + "BriefDescription": "Retired branch instructions (Precise event capable)" + }, + { + "PEBS": "2", + "CollectPEBSRecord": "2", + "PublicDescription": "Counts retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was taken and when it was not taken.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x7e", + "EventName": "BR_INST_RETIRED.JCC", + "SampleAfterValue": "200003", + "BriefDescription": "Retired conditional branch instructions (Precise event capable)" + }, + { + "PEBS": "2", + "CollectPEBSRecord": "2", + "PublicDescription": "Counts Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were taken and does not count when the Jcc branch instruction were not taken.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0xfe", + "EventName": "BR_INST_RETIRED.TAKEN_JCC", + "SampleAfterValue": "200003", + "BriefDescription": "Retired conditional branch instructions that were taken (Precise event capable)" + }, + { + "PEBS": "2", + "CollectPEBSRecord": "2", + "PublicDescription": "Counts near CALL branch instructions retired.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0xf9", + "EventName": "BR_INST_RETIRED.CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Retired near call instructions (Precise event capable)" + }, + { + "PEBS": "2", + "CollectPEBSRecord": "2", + "PublicDescription": "Counts near relative CALL branch instructions retired.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0xfd", + "EventName": "BR_INST_RETIRED.REL_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Retired near relative call instructions (Precise event capable)" + }, + { + "PEBS": "2", + "CollectPEBSRecord": "2", + "PublicDescription": "Counts near indirect CALL branch instructions retired.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0xfb", + "EventName": "BR_INST_RETIRED.IND_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Retired near indirect call instructions (Precise event capable)" + }, + { + "PEBS": "2", + "CollectPEBSRecord": "2", + "PublicDescription": "Counts near return branch instructions retired.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0xf7", + "EventName": "BR_INST_RETIRED.RETURN", + "SampleAfterValue": "200003", + "BriefDescription": "Retired near return instructions (Precise event capable)" + }, + { + "PEBS": "2", + "CollectPEBSRecord": "2", + "PublicDescription": "Counts near indirect call or near indirect jmp branch instructions retired.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0xeb", + "EventName": "BR_INST_RETIRED.NON_RETURN_IND", + "SampleAfterValue": "200003", + "BriefDescription": "Retired instructions of near indirect Jmp or call (Precise event capable)" + }, + { + "PEBS": "2", + "CollectPEBSRecord": "2", + "PublicDescription": "Counts far branch instructions retired. This includes far jump, far call and return, and Interrupt call and return.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0xbf", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "SampleAfterValue": "200003", + "BriefDescription": "Retired far branch instructions (Precise event capable)" + }, + { + "PEBS": "2", + "CollectPEBSRecord": "2", + "PublicDescription": "Counts mispredicted branch instructions retired including all branch types.", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "SampleAfterValue": "200003", + "BriefDescription": "Retired mispredicted branch instructions (Precise event capable)" + }, + { + "PEBS": "2", + "CollectPEBSRecord": "2", + "PublicDescription": "Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was supposed to be taken and when it was not supposed to be taken (but the processor predicted the opposite condition).", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x7e", + "EventName": "BR_MISP_RETIRED.JCC", + "SampleAfterValue": "200003", + "BriefDescription": "Retired mispredicted conditional branch instructions (Precise event capable)" + }, + { + "PEBS": "2", + "CollectPEBSRecord": "2", + "PublicDescription": "Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were supposed to be taken but the processor predicted that it would not be taken.", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0xfe", + "EventName": "BR_MISP_RETIRED.TAKEN_JCC", + "SampleAfterValue": "200003", + "BriefDescription": "Retired mispredicted conditional branch instructions that were taken (Precise event capable)" + }, + { + "PEBS": "2", + "CollectPEBSRecord": "2", + "PublicDescription": "Counts mispredicted near indirect CALL branch instructions retired, where the target address taken was not what the processor predicted.", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0xfb", + "EventName": "BR_MISP_RETIRED.IND_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Retired mispredicted near indirect call instructions (Precise event capable)" + }, + { + "PEBS": "2", + "CollectPEBSRecord": "2", + "PublicDescription": "Counts mispredicted near RET branch instructions retired, where the return address taken was not what the processor predicted.", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0xf7", + "EventName": "BR_MISP_RETIRED.RETURN", + "SampleAfterValue": "200003", + "BriefDescription": "Retired mispredicted near return instructions (Precise event capable)" + }, + { + "PEBS": "2", + "CollectPEBSRecord": "2", + "PublicDescription": "Counts mispredicted branch instructions retired that were near indirect call or near indirect jmp, where the target address taken was not what the processor predicted.", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0xeb", + "EventName": "BR_MISP_RETIRED.NON_RETURN_IND", + "SampleAfterValue": "200003", + "BriefDescription": "Retired mispredicted instructions of near indirect Jmp or near indirect call. (Precise event capable)" + }, + { + "PEBS": "2", + "CollectPEBSRecord": "2", + "PublicDescription": "Counts uops which retired.", + "EventCode": "0xC2", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "UOPS_RETIRED.ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops retired (Precise event capable)" + }, + { + "PEBS": "2", + "CollectPEBSRecord": "2", + "PublicDescription": "Counts uops retired that are from the complex flows issued by the micro-sequencer (MS). Counts both the uops from a micro-coded instruction, and the uops that might be generated from a micro-coded assist.", + "EventCode": "0xC2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.MS", + "SampleAfterValue": "2000003", + "BriefDescription": "MS uops retired (Precise event capable)" + }, + { + "CollectPEBSRecord": "1", + "PublicDescription": "Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification. Self-modifying code (SMC) causes a severe penalty in all Intel? architecture processors.", + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MACHINE_CLEARS.SMC", + "SampleAfterValue": "200003", + "BriefDescription": "Self-Modifying Code detected" + }, + { + "CollectPEBSRecord": "1", + "PublicDescription": "Counts machine clears due to floating point (FP) operations needing assists. For instance, if the result was a floating point denormal, the hardware clears the pipeline and reissues uops to produce the correct IEEE compliant denormal result.", + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "MACHINE_CLEARS.FP_ASSIST", + "SampleAfterValue": "200003", + "BriefDescription": "Machine clears due to FP assists" + }, + { + "CollectPEBSRecord": "1", + "PublicDescription": "Counts machine clears due to memory disambiguation. Memory disambiguation happens when a load which has been issued conflicts with a previous unretired store in the pipeline whose address was not known at issue time, but is later resolved to be the same as the load address.", + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "MACHINE_CLEARS.DISAMBIGUATION", + "SampleAfterValue": "200003", + "BriefDescription": "Machine clears due to memory disambiguation" + }, + { + "CollectPEBSRecord": "1", + "PublicDescription": "Counts machine clears for any reason.", + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "MACHINE_CLEARS.ALL", + "SampleAfterValue": "200003", + "BriefDescription": "All machine clears" + }, + { + "PEBS": "2", + "CollectPEBSRecord": "1", + "PublicDescription": "Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The event continues counting during hardware interrupts, traps, and inside interrupt handlers. This is an architectural performance event. This event uses a (_P)rogrammable general purpose performance counter. *This event is Precise Event capable: The EventingRIP field in the PEBS record is precise to the address of the instruction which caused the event. Note: Because PEBS records can be collected only on IA32_PMC0, only one event can use the PEBS facility at a time.", + "EventCode": "0xC0", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "INST_RETIRED.ANY_P", + "SampleAfterValue": "2000003", + "BriefDescription": "Instructions retired (Precise event capable)" + }, + { + "CollectPEBSRecord": "1", + "PublicDescription": "This event used to measure front-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-end and the back-end has is not stalled. This event can be used to identify if the machine is truly front-end bound. When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance. Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into uops in machine understandable format and putting them into a uop queue to be consumed by back end. The back-end then takes these uops, allocates the required resources. When all resources are ready, uops are executed. If the back-end is not ready to accept uops from the front-end, then we do not want to count these as front-end bottlenecks. However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more uops. This event counts only when back-end is requesting more uops and front-end is not able to provide them. When 3 uops are requested and no uops are delivered, the event counts 3. When 3 are requested, and only 1 is delivered, the event counts 2. When only 2 are delivered, the event counts 1. Alternatively stated, the event will not count if 3 uops are delivered, or if the back end is stalled and not requesting any uops at all. Counts indicate missed opportunities for the front-end to deliver a uop to the back end. Some examples of conditions that cause front-end efficiencies are: ICache misses, ITLB misses, and decoder restrictions that limit the front-end bandwidth. Known Issues: Some uops require multiple allocation slots. These uops will not be charged as a front end 'not delivered' opportunity, and will be regarded as a back end problem. For example, the INC instruction has one uop that requires 2 issue slots. A stream of INC instructions will not count as UOPS_NOT_DELIVERED, even though only one instruction can be issued per clock. The low uop issue rate for a stream of INC instructions is considered to be a back end issue.", + "EventCode": "0x9C", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "UOPS_NOT_DELIVERED.ANY", + "SampleAfterValue": "200003", + "BriefDescription": "Uops requested but not-delivered to the back-end per cycle" + }, + { + "CollectPEBSRecord": "1", + "PublicDescription": "Counts uops issued by the front end and allocated into the back end of the machine. This event counts uops that retire as well as uops that were speculatively executed but didn't retire. The sort of speculative uops that might be counted includes, but is not limited to those uops issued in the shadow of a miss-predicted branch, those uops that are inserted during an assist (such as for a denormal floating point result), and (previously allocated) uops that might be canceled during a machine clear.", + "EventCode": "0x0E", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "UOPS_ISSUED.ANY", + "SampleAfterValue": "200003", + "BriefDescription": "Uops issued to the back end per cycle" + }, + { + "CollectPEBSRecord": "1", + "PublicDescription": "Counts core cycles if either divide unit is busy.", + "EventCode": "0xCD", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "CYCLES_DIV_BUSY.ALL", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles a divider is busy" + }, + { + "CollectPEBSRecord": "1", + "PublicDescription": "Counts core cycles the integer divide unit is busy.", + "EventCode": "0xCD", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CYCLES_DIV_BUSY.IDIV", + "SampleAfterValue": "200003", + "BriefDescription": "Cycles the integer divide unit is busy" + }, + { + "CollectPEBSRecord": "1", + "PublicDescription": "Counts core cycles the floating point divide unit is busy.", + "EventCode": "0xCD", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "CYCLES_DIV_BUSY.FPDIV", + "SampleAfterValue": "200003", + "BriefDescription": "Cycles the FP divide unit is busy" + }, + { + "PublicDescription": "Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0. You cannot collect a PEBs record for this event.", + "EventCode": "0x00", + "Counter": "Fixed counter 1", + "UMask": "0x1", + "EventName": "INST_RETIRED.ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Instructions retired (Fixed event)" + }, + { + "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1. You cannot collect a PEBs record for this event.", + "EventCode": "0x00", + "Counter": "Fixed counter 2", + "UMask": "0x2", + "EventName": "CPU_CLK_UNHALTED.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Core cycles when core is not halted (Fixed event)" + }, + { + "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. This event uses fixed counter 2. You cannot collect a PEBs record for this event.", + "EventCode": "0x00", + "Counter": "Fixed counter 3", + "UMask": "0x3", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "SampleAfterValue": "2000003", + "BriefDescription": "Reference cycles when core is not halted (Fixed event)" + }, + { + "CollectPEBSRecord": "1", + "PublicDescription": "Core cycles when core is not halted. This event uses a (_P)rogrammable general purpose performance counter.", + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "CPU_CLK_UNHALTED.CORE_P", + "SampleAfterValue": "2000003", + "BriefDescription": "Core cycles when core is not halted" + }, + { + "CollectPEBSRecord": "1", + "PublicDescription": "Reference cycles when core is not halted. This event uses a (_P)rogrammable general purpose performance counter.", + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CPU_CLK_UNHALTED.REF", + "SampleAfterValue": "2000003", + "BriefDescription": "Reference cycles when core is not halted" + }, + { + "CollectPEBSRecord": "1", + "PublicDescription": "Counts the number of times a BACLEAR is signaled for any reason, including, but not limited to indirect branch/call, Jcc (Jump on Conditional Code/Jump if Condition is Met) branch, unconditional branch/call, and returns.", + "EventCode": "0xE6", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BACLEARS.ALL", + "SampleAfterValue": "200003", + "BriefDescription": "BACLEARs asserted for any branch type" + }, + { + "CollectPEBSRecord": "1", + "PublicDescription": "Counts BACLEARS on return instructions.", + "EventCode": "0xE6", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "BACLEARS.RETURN", + "SampleAfterValue": "200003", + "BriefDescription": "BACLEARs asserted for return branch" + }, + { + "CollectPEBSRecord": "1", + "PublicDescription": "Counts BACLEARS on Jcc (Jump on Conditional Code/Jump if Condition is Met) branches.", + "EventCode": "0xE6", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "BACLEARS.COND", + "SampleAfterValue": "200003", + "BriefDescription": "BACLEARs asserted for conditional branch" + }, + { + "PEBS": "2", + "CollectPEBSRecord": "2", + "PublicDescription": "Counts anytime a load that retires is blocked for any reason.", + "EventCode": "0x03", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "LD_BLOCKS.ALL_BLOCK", + "SampleAfterValue": "200003", + "BriefDescription": "Loads blocked (Precise event capable)" + }, + { + "PEBS": "2", + "CollectPEBSRecord": "2", + "PublicDescription": "Counts loads blocked because they are unable to find their physical address in the micro TLB (UTLB).", + "EventCode": "0x03", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "LD_BLOCKS.UTLB_MISS", + "SampleAfterValue": "200003", + "BriefDescription": "Loads blocked because address in not in the UTLB (Precise event capable)" + }, + { + "PEBS": "2", + "CollectPEBSRecord": "2", + "PublicDescription": "Counts a load blocked from using a store forward because of an address/size mismatch, only one of the loads blocked from each store will be counted.", + "EventCode": "0x03", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "SampleAfterValue": "200003", + "BriefDescription": "Loads blocked due to store forward restriction (Precise event capable)" + }, + { + "PEBS": "2", + "CollectPEBSRecord": "2", + "PublicDescription": "Counts a load blocked from using a store forward, but did not occur because the store data was not available at the right time. The forward might occur subsequently when the data is available.", + "EventCode": "0x03", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LD_BLOCKS.DATA_UNKNOWN", + "SampleAfterValue": "200003", + "BriefDescription": "Loads blocked due to store data not ready (Precise event capable)" + }, + { + "PEBS": "2", + "CollectPEBSRecord": "2", + "PublicDescription": "Counts loads that block because their address modulo 4K matches a pending store.", + "EventCode": "0x03", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "LD_BLOCKS.4K_ALIAS", + "SampleAfterValue": "200003", + "BriefDescription": "Loads blocked because address has 4k partial address false dependence (Precise event capable)" + }, + { + "PEBS": "2", + "CollectPEBSRecord": "1", + "PublicDescription": "Counts the number of taken branch instructions retired.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "BR_INST_RETIRED.ALL_TAKEN_BRANCHES", + "SampleAfterValue": "200003", + "BriefDescription": "Retired taken branch instructions (Precise event capable)" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json b/tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json new file mode 100644 index 000000000000..3202c4478836 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json @@ -0,0 +1,75 @@ +[ + { + "CollectPEBSRecord": "1", + "PublicDescription": "Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) for a linear address of an instruction fetch. It counts when new translation are filled into the ITLB. The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB.", + "EventCode": "0x81", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "ITLB.MISS", + "SampleAfterValue": "200003", + "BriefDescription": "ITLB misses" + }, + { + "PEBS": "2", + "CollectPEBSRecord": "2", + "PublicDescription": "Counts load uops retired that caused a DTLB miss.", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x11", + "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS", + "SampleAfterValue": "200003", + "BriefDescription": "Load uops retired that missed the DTLB (Precise event capable)" + }, + { + "PEBS": "2", + "CollectPEBSRecord": "2", + "PublicDescription": "Counts store uops retired that caused a DTLB miss.", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x12", + "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_STORES", + "SampleAfterValue": "200003", + "BriefDescription": "Store uops retired that missed the DTLB (Precise event capable)" + }, + { + "PEBS": "2", + "CollectPEBSRecord": "2", + "PublicDescription": "Counts uops retired that had a DTLB miss on load, store or either. Note that when two distinct memory operations to the same page miss the DTLB, only one of them will be recorded as a DTLB miss.", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x13", + "EventName": "MEM_UOPS_RETIRED.DTLB_MISS", + "SampleAfterValue": "200003", + "BriefDescription": "Memory uops retired that missed the DTLB (Precise event capable)" + }, + { + "CollectPEBSRecord": "1", + "PublicDescription": "Counts every core cycle when a Data-side (walks due to a data operation) page walk is in progress.", + "EventCode": "0x05", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "PAGE_WALKS.D_SIDE_CYCLES", + "SampleAfterValue": "200003", + "BriefDescription": "Duration of D-side page-walks in cycles" + }, + { + "CollectPEBSRecord": "1", + "PublicDescription": "Counts every core cycle when a Instruction-side (walks due to an instruction fetch) page walk is in progress.", + "EventCode": "0x05", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "PAGE_WALKS.I_SIDE_CYCLES", + "SampleAfterValue": "200003", + "BriefDescription": "Duration of I-side pagewalks in cycles" + }, + { + "CollectPEBSRecord": "1", + "PublicDescription": "Counts every core cycle a page-walk is in progress due to either a data memory operation or an instruction fetch.", + "EventCode": "0x05", + "Counter": "0,1,2,3", + "UMask": "0x3", + "EventName": "PAGE_WALKS.CYCLES", + "SampleAfterValue": "200003", + "BriefDescription": "Duration of page-walks in cycles" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswell/cache.json b/tools/perf/pmu-events/arch/x86/haswell/cache.json new file mode 100644 index 000000000000..bfb5ebf48c54 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/haswell/cache.json @@ -0,0 +1,1041 @@ +[ + { + "PublicDescription": "Demand data read requests that missed L2, no rejects.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x21", + "Errata": "HSD78", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", + "SampleAfterValue": "200003", + "BriefDescription": "Demand Data Read miss L2, no rejects", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Demand data read requests that hit L2 cache.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x41", + "Errata": "HSD78", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "SampleAfterValue": "200003", + "BriefDescription": "Demand Data Read requests that hit L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "L2_RQSTS.L2_PF_MISS", + "SampleAfterValue": "200003", + "BriefDescription": "L2 prefetch requests that miss L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x50", + "EventName": "L2_RQSTS.L2_PF_HIT", + "SampleAfterValue": "200003", + "BriefDescription": "L2 prefetch requests that hit L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xe1", + "Errata": "HSD78", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "SampleAfterValue": "200003", + "BriefDescription": "Demand Data Read requests", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts all L2 store RFO requests.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xe2", + "EventName": "L2_RQSTS.ALL_RFO", + "SampleAfterValue": "200003", + "BriefDescription": "RFO requests to L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts all L2 code requests.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xe4", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "SampleAfterValue": "200003", + "BriefDescription": "L2 code requests", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts all L2 HW prefetcher requests.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xf8", + "EventName": "L2_RQSTS.ALL_PF", + "SampleAfterValue": "200003", + "BriefDescription": "Requests from L2 hardware prefetchers", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Not rejected writebacks that hit L2 cache.", + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x50", + "EventName": "L2_DEMAND_RQSTS.WB_HIT", + "SampleAfterValue": "200003", + "BriefDescription": "Not rejected writebacks that hit L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts each cache miss condition for references to the last level cache.", + "EventCode": "0x2E", + "Counter": "0,1,2,3", + "UMask": "0x41", + "EventName": "LONGEST_LAT_CACHE.MISS", + "SampleAfterValue": "100003", + "BriefDescription": "Core-originated cacheable demand requests missed L3", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.", + "EventCode": "0x2E", + "Counter": "0,1,2,3", + "UMask": "0x4f", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "SampleAfterValue": "100003", + "BriefDescription": "Core-originated cacheable demand requests that refer to L3", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.", + "EventCode": "0x48", + "Counter": "2", + "UMask": "0x1", + "EventName": "L1D_PEND_MISS.PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "L1D miss oustandings duration in cycles", + "CounterHTOff": "2" + }, + { + "EventCode": "0x48", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L1D_PEND_MISS.REQUEST_FB_FULL", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x48", + "Counter": "2", + "UMask": "0x1", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with L1D load Misses outstanding.", + "CounterMask": "1", + "CounterHTOff": "2" + }, + { + "PublicDescription": "This event counts when new data lines are brought into the L1 Data cache, which cause other lines to be evicted from the cache.", + "EventCode": "0x51", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L1D.REPLACEMENT", + "SampleAfterValue": "2000003", + "BriefDescription": "L1D data line replacements", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Offcore outstanding demand data read transactions in SQ to uncore. Set Cmask=1 to count cycles.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Errata": "HSD78, HSD62, HSD61", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Offcore outstanding Demand code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x2", + "Errata": "HSD62, HSD61", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x4", + "Errata": "HSD62, HSD61", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x8", + "Errata": "HSD62, HSD61", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Errata": "HSD78, HSD62, HSD61", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x8", + "Errata": "HSD62, HSD61", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x4", + "Errata": "HSD62, HSD61", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles in which the L1D is locked.", + "EventCode": "0x63", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when L1D is locked", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Demand data read requests sent to uncore.", + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Errata": "HSD78", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "SampleAfterValue": "100003", + "BriefDescription": "Demand Data Read requests sent to uncore", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Demand code read requests sent to uncore.", + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "SampleAfterValue": "100003", + "BriefDescription": "Cacheable and noncachaeble code read requests", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.", + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "SampleAfterValue": "100003", + "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Data read requests sent to uncore (demand and prefetch).", + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", + "SampleAfterValue": "100003", + "BriefDescription": "Demand and prefetch data reads", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xb2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x11", + "Errata": "HSD29, HSM30", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load uops that miss the STLB.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x12", + "Errata": "HSD29, HSM30", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", + "SampleAfterValue": "100003", + "BriefDescription": "Retired store uops that miss the STLB.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "L1_Hit_Indication": "1" + }, + { + "PEBS": "1", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x21", + "Errata": "HSD76, HSD29, HSM30", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load uops with locked access.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x41", + "Errata": "HSD29, HSM30", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load uops that split across a cacheline boundary.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x42", + "Errata": "HSD29, HSM30", + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "SampleAfterValue": "100003", + "BriefDescription": "Retired store uops that split across a cacheline boundary.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "L1_Hit_Indication": "1" + }, + { + "PEBS": "1", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x81", + "Errata": "HSD29, HSM30", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "SampleAfterValue": "2000003", + "BriefDescription": "All retired load uops.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x82", + "Errata": "HSD29, HSM30", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "SampleAfterValue": "2000003", + "BriefDescription": "All retired store uops.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "L1_Hit_Indication": "1" + }, + { + "PEBS": "1", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Errata": "HSD29, HSM30", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "SampleAfterValue": "2000003", + "BriefDescription": "Retired load uops with L1 cache hits as data sources.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "Errata": "HSD76, HSD29, HSM30", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load uops with L2 cache hits as data sources.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "PublicDescription": "Retired load uops with L3 cache hits as data sources.", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x4", + "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", + "SampleAfterValue": "50021", + "BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "PublicDescription": "Retired load uops missed L1 cache as data sources.", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x8", + "Errata": "HSM30", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load uops misses in L1 cache as data sources.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "PublicDescription": "Retired load uops missed L2. Unknown data source excluded.", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x10", + "Errata": "HSD29, HSM30", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "SampleAfterValue": "50021", + "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "PublicDescription": "Retired load uops missed L3. Excludes unknown data source .", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x20", + "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS", + "SampleAfterValue": "100003", + "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x40", + "Errata": "HSM30", + "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Errata": "HSD29, HSD25, HSM26, HSM30", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS", + "SampleAfterValue": "20011", + "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "Errata": "HSD29, HSD25, HSM26, HSM30", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT", + "SampleAfterValue": "20011", + "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "Errata": "HSD29, HSD25, HSM26, HSM30", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM", + "SampleAfterValue": "20011", + "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x8", + "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "PublicDescription": "This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches.", + "EventCode": "0xD3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Errata": "HSD74, HSD29, HSD25, HSM30", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", + "SampleAfterValue": "100003", + "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PublicDescription": "Demand data read requests that access L2 cache.", + "EventCode": "0xf0", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_TRANS.DEMAND_DATA_RD", + "SampleAfterValue": "200003", + "BriefDescription": "Demand Data Read requests that access L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "RFO requests that access L2 cache.", + "EventCode": "0xf0", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_TRANS.RFO", + "SampleAfterValue": "200003", + "BriefDescription": "RFO requests that access L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "L2 cache accesses when fetching instructions.", + "EventCode": "0xf0", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_TRANS.CODE_RD", + "SampleAfterValue": "200003", + "BriefDescription": "L2 cache accesses when fetching instructions", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Any MLC or L3 HW prefetch accessing L2, including rejects.", + "EventCode": "0xf0", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_TRANS.ALL_PF", + "SampleAfterValue": "200003", + "BriefDescription": "L2 or L3 HW prefetches that access L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "L1D writebacks that access L2 cache.", + "EventCode": "0xf0", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "L2_TRANS.L1D_WB", + "SampleAfterValue": "200003", + "BriefDescription": "L1D writebacks that access L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "L2 fill requests that access L2 cache.", + "EventCode": "0xf0", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "L2_TRANS.L2_FILL", + "SampleAfterValue": "200003", + "BriefDescription": "L2 fill requests that access L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "L2 writebacks that access L2 cache.", + "EventCode": "0xf0", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "L2_TRANS.L2_WB", + "SampleAfterValue": "200003", + "BriefDescription": "L2 writebacks that access L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Transactions accessing L2 pipe.", + "EventCode": "0xf0", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "L2_TRANS.ALL_REQUESTS", + "SampleAfterValue": "200003", + "BriefDescription": "Transactions accessing L2 pipe", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "L2 cache lines in I state filling L2.", + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_LINES_IN.I", + "SampleAfterValue": "100003", + "BriefDescription": "L2 cache lines in I state filling L2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "L2 cache lines in S state filling L2.", + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_LINES_IN.S", + "SampleAfterValue": "100003", + "BriefDescription": "L2 cache lines in S state filling L2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "L2 cache lines in E state filling L2.", + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_LINES_IN.E", + "SampleAfterValue": "100003", + "BriefDescription": "L2 cache lines in E state filling L2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss.", + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x7", + "EventName": "L2_LINES_IN.ALL", + "SampleAfterValue": "100003", + "BriefDescription": "L2 cache lines filling L2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Clean L2 cache lines evicted by demand.", + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x5", + "EventName": "L2_LINES_OUT.DEMAND_CLEAN", + "SampleAfterValue": "100003", + "BriefDescription": "Clean L2 cache lines evicted by demand", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Dirty L2 cache lines evicted by demand.", + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x6", + "EventName": "L2_LINES_OUT.DEMAND_DIRTY", + "SampleAfterValue": "100003", + "BriefDescription": "Dirty L2 cache lines evicted by demand", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xf4", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "SQ_MISC.SPLIT_LOCK", + "SampleAfterValue": "100003", + "BriefDescription": "Split locks in SQ", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x42", + "EventName": "L2_RQSTS.RFO_HIT", + "SampleAfterValue": "200003", + "BriefDescription": "RFO requests that hit L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x22", + "EventName": "L2_RQSTS.RFO_MISS", + "SampleAfterValue": "200003", + "BriefDescription": "RFO requests that miss L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of instruction fetches that hit the L2 cache.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x44", + "EventName": "L2_RQSTS.CODE_RD_HIT", + "SampleAfterValue": "200003", + "BriefDescription": "L2 cache hits when fetching instructions, code reads.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of instruction fetches that missed the L2 cache.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x24", + "EventName": "L2_RQSTS.CODE_RD_MISS", + "SampleAfterValue": "200003", + "BriefDescription": "L2 cache misses when fetching instructions", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Demand requests that miss L2 cache.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x27", + "Errata": "HSD78", + "EventName": "L2_RQSTS.ALL_DEMAND_MISS", + "SampleAfterValue": "200003", + "BriefDescription": "Demand requests that miss L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Demand requests to L2 cache.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xe7", + "Errata": "HSD78", + "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", + "SampleAfterValue": "200003", + "BriefDescription": "Demand requests to L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "All requests that missed L2.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x3f", + "Errata": "HSD78", + "EventName": "L2_RQSTS.MISS", + "SampleAfterValue": "200003", + "BriefDescription": "All requests that miss L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "All requests to L2 cache.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xff", + "Errata": "HSD78", + "EventName": "L2_RQSTS.REFERENCES", + "SampleAfterValue": "200003", + "BriefDescription": "All L2 requests", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB7, 0xBB", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE", + "SampleAfterValue": "100003", + "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Errata": "HSD78, HSD62, HSD61", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", + "CounterMask": "6", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x48", + "Counter": "2", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", + "CounterMask": "1", + "CounterHTOff": "2" + }, + { + "EventCode": "0x48", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L1D_PEND_MISS.FB_FULL", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c8fff", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.L3_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all requests that hit in the L3", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c07f7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x04003c07f7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x04003c0244", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0122", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x04003c0122", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0091", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x04003c0091", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0200", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0100", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0080", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0040", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0020", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x04003c0004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0002", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x04003c0002", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x04003c0001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswell/floating-point.json b/tools/perf/pmu-events/arch/x86/haswell/floating-point.json new file mode 100644 index 000000000000..1732fa49c6d2 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/haswell/floating-point.json @@ -0,0 +1,83 @@ +[ + { + "EventCode": "0xC1", + "Counter": "0,1,2,3", + "UMask": "0x8", + "Errata": "HSD56, HSM57", + "EventName": "OTHER_ASSISTS.AVX_TO_SSE", + "SampleAfterValue": "100003", + "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC1", + "Counter": "0,1,2,3", + "UMask": "0x10", + "Errata": "HSD56, HSM57", + "EventName": "OTHER_ASSISTS.SSE_TO_AVX", + "SampleAfterValue": "100003", + "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of X87 FP assists due to output values.", + "EventCode": "0xCA", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "FP_ASSIST.X87_OUTPUT", + "SampleAfterValue": "100003", + "BriefDescription": "Number of X87 assists due to output value.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of X87 FP assists due to input values.", + "EventCode": "0xCA", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "FP_ASSIST.X87_INPUT", + "SampleAfterValue": "100003", + "BriefDescription": "Number of X87 assists due to input value.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of SIMD FP assists due to output values.", + "EventCode": "0xCA", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "FP_ASSIST.SIMD_OUTPUT", + "SampleAfterValue": "100003", + "BriefDescription": "Number of SIMD FP assists due to Output values", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of SIMD FP assists due to input values.", + "EventCode": "0xCA", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "FP_ASSIST.SIMD_INPUT", + "SampleAfterValue": "100003", + "BriefDescription": "Number of SIMD FP assists due to input values", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles with any input/output SSE* or FP assists.", + "EventCode": "0xCA", + "Counter": "0,1,2,3", + "UMask": "0x1e", + "EventName": "FP_ASSIST.ANY", + "SampleAfterValue": "100003", + "BriefDescription": "Cycles with any input/output SSE or FP assist", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Note that a whole rep string only counts AVX_INST.ALL once.", + "EventCode": "0xC6", + "Counter": "0,1,2,3", + "UMask": "0x7", + "EventName": "AVX_INSTS.ALL", + "SampleAfterValue": "2000003", + "BriefDescription": "Approximate counts of AVX & AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores. May count non-AVX instructions that employ 256-bit operations, including (but not necessarily limited to) rep string instructions that use 256-bit loads and stores for optimized performance, XSAVE* and XRSTOR*, and operations that transition the x87 FPU data registers between x87 and MMX.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswell/frontend.json b/tools/perf/pmu-events/arch/x86/haswell/frontend.json new file mode 100644 index 000000000000..57a1ce46971f --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/haswell/frontend.json @@ -0,0 +1,294 @@ +[ + { + "PublicDescription": "Counts cycles the IDQ is empty.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x2", + "Errata": "HSD135", + "EventName": "IDQ.EMPTY", + "SampleAfterValue": "2000003", + "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "IDQ.MITE_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "IDQ.DSB_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "IDQ.MS_DSB_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "IDQ.MS_MITE_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts uops delivered by the Front-end with the assistance of the microcode sequencer. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "IDQ.MS_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts cycles during which the microcode sequencer assisted the Front-end in delivering uops. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "IDQ.MS_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "IDQ.MITE_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "IDQ.DSB_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "IDQ.MS_DSB_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EdgeDetect": "1", + "EventName": "IDQ.MS_DSB_OCCUR", + "SampleAfterValue": "2000003", + "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x18", + "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x18", + "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts cycles MITE is delivered four uops. Set Cmask = 4.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x24", + "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles MITE is delivering 4 Uops", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts cycles MITE is delivered at least one uop. Set Cmask = 1.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x24", + "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles MITE is delivering any Uop", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of uops delivered to IDQ from any path.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x3c", + "EventName": "IDQ.MITE_ALL_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ICACHE.HIT", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts Instruction Cache (ICACHE) misses.", + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "ICACHE.MISSES", + "SampleAfterValue": "200003", + "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "ICACHE.IFETCH_STALL", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event count the number of undelivered (unallocated) uops from the Front-end to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled. The Front-end can allocate up to 4 uops per cycle so this event can increment 0-4 times per cycle depending on the number of unallocated uops. This event is counted on a per-core basis.", + "EventCode": "0x9C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Errata": "HSD135", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "This event counts the number cycles during which the Front-end allocated exactly zero uops to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled. This event is counted on a per-core basis.", + "EventCode": "0x9C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Errata": "HSD135", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Errata": "HSD135", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", + "CounterMask": "3", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Errata": "HSD135", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", + "CounterMask": "2", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Errata": "HSD135", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with less than 3 uops delivered by the front end.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Errata": "HSD135", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xAB", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EdgeDetect": "1", + "EventName": "IDQ.MS_SWITCHES", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "ICACHE.IFDATA_STALL", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswell/memory.json b/tools/perf/pmu-events/arch/x86/haswell/memory.json new file mode 100644 index 000000000000..aab981b42339 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/haswell/memory.json @@ -0,0 +1,655 @@ +[ + { + "PublicDescription": "Speculative cache-line split load uops dispatched to L1D.", + "EventCode": "0x05", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MISALIGN_MEM_REF.LOADS", + "SampleAfterValue": "2000003", + "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Speculative cache-line split store-address uops dispatched to L1D.", + "EventCode": "0x05", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MISALIGN_MEM_REF.STORES", + "SampleAfterValue": "2000003", + "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x54", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "TX_MEM.ABORT_CONFLICT", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x54", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional writes.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x54", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x54", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x54", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x54", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x54", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5d", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "TX_EXEC.MISC1", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5d", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "TX_EXEC.MISC2", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5d", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "TX_EXEC.MISC3", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5d", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "TX_EXEC.MISC4", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5d", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "TX_EXEC.MISC5", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data inflight in the pipeline. Machine clears can have a significant performance impact if they are happening frequently.", + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "SampleAfterValue": "100003", + "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "HLE_RETIRED.START", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an HLE execution started.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xc8", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "HLE_RETIRED.COMMIT", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an HLE execution successfully committed.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "EventCode": "0xc8", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "HLE_RETIRED.ABORTED", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xc8", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "HLE_RETIRED.ABORTED_MISC1", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xc8", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "HLE_RETIRED.ABORTED_MISC2", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xc8", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "HLE_RETIRED.ABORTED_MISC3", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xc8", + "Counter": "0,1,2,3", + "UMask": "0x40", + "Errata": "HSD65", + "EventName": "HLE_RETIRED.ABORTED_MISC4", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts).", + "EventCode": "0xc8", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "HLE_RETIRED.ABORTED_MISC5", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC9", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "RTM_RETIRED.START", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an RTM execution started.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xc9", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "RTM_RETIRED.COMMIT", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an RTM execution successfully committed.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xc9", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "RTM_RETIRED.ABORTED", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", + "EventCode": "0xc9", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "RTM_RETIRED.ABORTED_MISC1", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xc9", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "RTM_RETIRED.ABORTED_MISC2", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xc9", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "RTM_RETIRED.ABORTED_MISC3", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xc9", + "Counter": "0,1,2,3", + "UMask": "0x40", + "Errata": "HSD65", + "EventName": "RTM_RETIRED.ABORTED_MISC4", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type.", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", + "EventCode": "0xc9", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "RTM_RETIRED.ABORTED_MISC5", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "2", + "EventCode": "0xCD", + "MSRValue": "0x4", + "Counter": "3", + "UMask": "0x1", + "Errata": "HSD76, HSD25, HSM26", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "SampleAfterValue": "100003", + "BriefDescription": "Loads with latency value being above 4.", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "EventCode": "0xCD", + "MSRValue": "0x8", + "Counter": "3", + "UMask": "0x1", + "Errata": "HSD76, HSD25, HSM26", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "MSRIndex": "0x3F6", + "SampleAfterValue": "50021", + "BriefDescription": "Loads with latency value being above 8.", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "EventCode": "0xCD", + "MSRValue": "0x10", + "Counter": "3", + "UMask": "0x1", + "Errata": "HSD76, HSD25, HSM26", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "MSRIndex": "0x3F6", + "SampleAfterValue": "20011", + "BriefDescription": "Loads with latency value being above 16.", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "EventCode": "0xCD", + "MSRValue": "0x20", + "Counter": "3", + "UMask": "0x1", + "Errata": "HSD76, HSD25, HSM26", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "MSRIndex": "0x3F6", + "SampleAfterValue": "100003", + "BriefDescription": "Loads with latency value being above 32.", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "EventCode": "0xCD", + "MSRValue": "0x40", + "Counter": "3", + "UMask": "0x1", + "Errata": "HSD76, HSD25, HSM26", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "MSRIndex": "0x3F6", + "SampleAfterValue": "2003", + "BriefDescription": "Loads with latency value being above 64.", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "EventCode": "0xCD", + "MSRValue": "0x80", + "Counter": "3", + "UMask": "0x1", + "Errata": "HSD76, HSD25, HSM26", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "MSRIndex": "0x3F6", + "SampleAfterValue": "1009", + "BriefDescription": "Loads with latency value being above 128.", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "EventCode": "0xCD", + "MSRValue": "0x100", + "Counter": "3", + "UMask": "0x1", + "Errata": "HSD76, HSD25, HSM26", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "MSRIndex": "0x3F6", + "SampleAfterValue": "503", + "BriefDescription": "Loads with latency value being above 256.", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "EventCode": "0xCD", + "MSRValue": "0x200", + "Counter": "3", + "UMask": "0x1", + "Errata": "HSD76, HSD25, HSM26", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "MSRIndex": "0x3F6", + "SampleAfterValue": "101", + "BriefDescription": "Loads with latency value being above 512.", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fffc08fff", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.L3_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all requests that miss in the L3", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x01004007f7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from local dram", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fffc007f7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss in the L3", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100400244", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch code reads that miss the L3 and the data is returned from local dram", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fffc00244", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch code reads that miss in the L3", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100400122", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fffc00122", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch RFOs that miss in the L3", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100400091", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fffc00091", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch data reads that miss in the L3", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fffc00200", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that miss in the L3", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fffc00100", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fffc00080", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss in the L3", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fffc00040", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the L3", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fffc00020", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss in the L3", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fffc00010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the L3", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100400004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local dram", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fffc00004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand code reads that miss in the L3", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100400002", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fffc00002", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand data writes (RFOs) that miss in the L3", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100400001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local dram", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fffc00001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that miss in the L3", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswell/other.json b/tools/perf/pmu-events/arch/x86/haswell/other.json new file mode 100644 index 000000000000..85d6a14baf9d --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/haswell/other.json @@ -0,0 +1,43 @@ +[ + { + "PublicDescription": "Unhalted core cycles when the thread is in ring 0.", + "EventCode": "0x5C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CPL_CYCLES.RING0", + "SampleAfterValue": "2000003", + "BriefDescription": "Unhalted core cycles when the thread is in ring 0", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.", + "EventCode": "0x5C", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "CPL_CYCLES.RING123", + "SampleAfterValue": "2000003", + "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EdgeDetect": "1", + "EventName": "CPL_CYCLES.RING0_TRANS", + "SampleAfterValue": "100003", + "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.", + "EventCode": "0x63", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswell/pipeline.json b/tools/perf/pmu-events/arch/x86/haswell/pipeline.json new file mode 100644 index 000000000000..0099848607ad --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/haswell/pipeline.json @@ -0,0 +1,1329 @@ +[ + { + "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. INST_RETIRED.ANY is counted by a designated fixed counter, leaving the programmable counters available for other events. Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.", + "EventCode": "0x00", + "Counter": "Fixed counter 1", + "UMask": "0x1", + "Errata": "HSD140, HSD143", + "EventName": "INST_RETIRED.ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Instructions retired from execution.", + "CounterHTOff": "Fixed counter 1" + }, + { + "PublicDescription": "This event counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.", + "EventCode": "0x00", + "Counter": "Fixed counter 2", + "UMask": "0x2", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "SampleAfterValue": "2000003", + "BriefDescription": "Core cycles when the thread is not in halt state.", + "CounterHTOff": "Fixed counter 2" + }, + { + "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state.", + "EventCode": "0x00", + "Counter": "Fixed counter 3", + "UMask": "0x3", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "SampleAfterValue": "2000003", + "BriefDescription": "Reference cycles when the core is not in halt state.", + "CounterHTOff": "Fixed counter 3" + }, + { + "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. The penalty for blocked store forwarding is that the load must wait for the store to write its value to the cache before it can be issued.", + "EventCode": "0x03", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "SampleAfterValue": "100003", + "BriefDescription": "loads blocked by overlapping with store buffer that cannot be forwarded", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "EventCode": "0x03", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "LD_BLOCKS.NO_SR", + "SampleAfterValue": "100003", + "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K. This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline which can have a performance impact.", + "EventCode": "0x07", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "SampleAfterValue": "100003", + "BriefDescription": "False dependencies in MOB due to partial compare on address.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of cycles spent waiting for a recovery after an event such as a processor nuke, JEClear, assist, hle/rtm abort etc.", + "EventCode": "0x0D", + "Counter": "0,1,2,3", + "UMask": "0x3", + "EventName": "INT_MISC.RECOVERY_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of uops issued by the Front-end of the pipeline to the Back-end. This event is counted at the allocation stage and will count both retired and non-retired uops.", + "EventCode": "0x0E", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_ISSUED.ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of flags-merge uops allocated. Such uops add delay.", + "EventCode": "0x0E", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "UOPS_ISSUED.FLAGS_MERGE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of slow LEA or similar uops allocated. Such uop has 3 sources (for example, 2 sources + immediate) regardless of whether it is a result of LEA instruction or not.", + "EventCode": "0x0E", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "UOPS_ISSUED.SLOW_LEA", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of multiply packed/scalar single precision uops allocated.", + "EventCode": "0x0E", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "UOPS_ISSUED.SINGLE_MUL", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0E", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x0E", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x14", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "ARITH.DIVIDER_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Any uop executed by the Divider. (This includes all divide uops, sqrt, ...)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Increments at the frequency of XCLK (100 MHz) when not halted.", + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", + "SampleAfterValue": "2000003", + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3c", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "2000003", + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.", + "EventCode": "0x4c", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LOAD_HIT_PRE.SW_PF", + "SampleAfterValue": "100003", + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.", + "EventCode": "0x4c", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "LOAD_HIT_PRE.HW_PF", + "SampleAfterValue": "100003", + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of integer move elimination candidate uops that were eliminated.", + "EventCode": "0x58", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", + "SampleAfterValue": "1000003", + "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of SIMD move elimination candidate uops that were eliminated.", + "EventCode": "0x58", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", + "SampleAfterValue": "1000003", + "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of integer move elimination candidate uops that were not eliminated.", + "EventCode": "0x58", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", + "SampleAfterValue": "1000003", + "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of SIMD move elimination candidate uops that were not eliminated.", + "EventCode": "0x58", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", + "SampleAfterValue": "1000003", + "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts cycles when the Reservation Station ( RS ) is empty for the thread. The RS is a structure that buffers allocated micro-ops from the Front-end. If there are many cycles when the RS is empty, it may represent an underflow of instructions delivered from the Front-end.", + "EventCode": "0x5E", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "RS_EVENTS.EMPTY_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts cycles where the decoder is stalled on an instruction with a length changing prefix (LCP).", + "EventCode": "0x87", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ILD_STALL.LCP", + "SampleAfterValue": "2000003", + "BriefDescription": "Stalls caused by changing prefix length of the instruction.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Stall cycles due to IQ is full.", + "EventCode": "0x87", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "ILD_STALL.IQ_FULL", + "SampleAfterValue": "2000003", + "BriefDescription": "Stall cycles because IQ is full", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x41", + "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Not taken macro-conditional branches.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x81", + "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired macro-conditional branches.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x82", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x84", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x90", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired direct near calls.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xa0", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired indirect calls.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xc1", + "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired macro-conditional branches.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xc2", + "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xc4", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired indirect branches excluding calls and returns.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xc8", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired indirect return branches.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xd0", + "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired direct near calls.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts all near executed branches (not necessarily retired).", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xff", + "EventName": "BR_INST_EXEC.ALL_BRANCHES", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired branches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x41", + "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x81", + "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x84", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x88", + "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0xc1", + "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired mispredicted macro conditional branches.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0xc4", + "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "BriefDescription": "Mispredicted indirect branches excluding calls and returns.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts all near executed branches (not necessarily retired).", + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0xff", + "EventName": "BR_MISP_EXEC.ALL_BRANCHES", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired mispredicted macro conditional branches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles which a uop is dispatched on port 0 in this thread.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_EXECUTED_PORT.PORT_0", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are executed in port 0", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles which a uop is dispatched on port 1 in this thread.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED_PORT.PORT_1", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are executed in port 1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles which a uop is dispatched on port 2 in this thread.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "UOPS_EXECUTED_PORT.PORT_2", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are executed in port 2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles which a uop is dispatched on port 3 in this thread.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "UOPS_EXECUTED_PORT.PORT_3", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are executed in port 3", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles which a uop is dispatched on port 4 in this thread.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "UOPS_EXECUTED_PORT.PORT_4", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are executed in port 4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles which a uop is dispatched on port 5 in this thread.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "UOPS_EXECUTED_PORT.PORT_5", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are executed in port 5", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles which a uop is dispatched on port 6 in this thread.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "UOPS_EXECUTED_PORT.PORT_6", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are executed in port 6", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles which a uop is dispatched on port 7 in this thread.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "UOPS_EXECUTED_PORT.PORT_7", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are executed in port 7", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles allocation is stalled due to resource related reason.", + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Errata": "HSD135", + "EventName": "RESOURCE_STALLS.ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Resource-related stall cycles", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "RESOURCE_STALLS.RS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles stalled due to no eligible RS entry available.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts cycles during which no instructions were allocated because no Store Buffers (SB) were available.", + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "RESOURCE_STALLS.SB", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "RESOURCE_STALLS.ROB", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles stalled due to re-order buffer full.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles with pending L2 miss loads. Set Cmask=2 to count cycle.", + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Errata": "HSD78", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with pending L2 cache miss loads.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles with pending L1 data cache miss loads. Set Cmask=8 to count cycle.", + "EventCode": "0xA3", + "Counter": "2", + "UMask": "0x8", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with pending L1 cache miss loads.", + "CounterMask": "8", + "CounterHTOff": "2" + }, + { + "PublicDescription": "Cycles with pending memory loads. Set Cmask=2 to count cycle.", + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with pending memory loads.", + "CounterMask": "2", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "This event counts cycles during which no instructions were executed in the execution stage of the pipeline.", + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", + "SampleAfterValue": "2000003", + "BriefDescription": "Total execution stalls", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Number of loads missed L2.", + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x5", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "Execution stalls due to L2 cache misses.", + "CounterMask": "5", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "This event counts cycles during which no instructions were executed in the execution stage of the pipeline and there were memory instructions pending (waiting for data).", + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x6", + "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "Execution stalls due to memory subsystem.", + "CounterMask": "6", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Execution stalls due to L1 data cache miss loads. Set Cmask=0CH.", + "EventCode": "0xA3", + "Counter": "2", + "UMask": "0xc", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "Execution stalls due to L1 data cache misses", + "CounterMask": "12", + "CounterHTOff": "2" + }, + { + "PublicDescription": "Number of uops delivered by the LSD.", + "EventCode": "0xa8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LSD.UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of Uops delivered by the LSD.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts total number of uops to be executed per-core each cycle.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "Errata": "HSD30, HSM31", + "EventName": "UOPS_EXECUTED.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of uops executed on the core.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Errata": "HSD144, HSD30, HSM31", + "EventName": "UOPS_EXECUTED.STALL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Number of instructions at retirement.", + "EventCode": "0xC0", + "Counter": "0,1,2,3", + "UMask": "0x0", + "Errata": "HSD11, HSD140", + "EventName": "INST_RETIRED.ANY_P", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of instructions retired. General Counter - architectural event", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.", + "EventCode": "0xC0", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "INST_RETIRED.X87", + "SampleAfterValue": "2000003", + "BriefDescription": "FP operations retired. X87 FP operations that have no exceptions: Counts also flows that have several X87 or flows that use X87 uops in the exception handling.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "2", + "PublicDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution.", + "EventCode": "0xC0", + "Counter": "1", + "UMask": "0x1", + "Errata": "HSD140", + "EventName": "INST_RETIRED.PREC_DIST", + "SampleAfterValue": "2000003", + "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution", + "CounterHTOff": "1" + }, + { + "PublicDescription": "Number of microcode assists invoked by HW upon uop writeback.", + "EventCode": "0xC1", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", + "SampleAfterValue": "100003", + "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "PublicDescription": "Counts the number of micro-ops retired. Use Cmask=1 and invert to count active cycles or stalled cycles.", + "EventCode": "0xC2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.ALL", + "SampleAfterValue": "2000003", + "BriefDescription": "Actually retired uops.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Data_LA": "1" + }, + { + "PEBS": "1", + "PublicDescription": "This event counts the number of retirement slots used each cycle. There are potentially 4 slots that can be used each cycle - meaning, 4 uops or 4 instructions could retire each cycle.", + "EventCode": "0xC2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "SampleAfterValue": "2000003", + "BriefDescription": "Retirement slots used.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC2", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles without actually retired uops.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC2", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with less than 10 actually retired uops.", + "CounterMask": "10", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC2", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles without actually retired uops.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MACHINE_CLEARS.CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear. Machine clears can have a significant performance impact if they are happening frequently.", + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "MACHINE_CLEARS.SMC", + "SampleAfterValue": "100003", + "BriefDescription": "Self-modifying code (SMC) detected.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "MACHINE_CLEARS.MASKMOV", + "SampleAfterValue": "100003", + "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "PublicDescription": "Counts the number of conditional branch instructions retired.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BR_INST_RETIRED.CONDITIONAL", + "SampleAfterValue": "400009", + "BriefDescription": "Conditional branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "SampleAfterValue": "100003", + "BriefDescription": "Direct and indirect near call instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Branch instructions at retirement.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "SampleAfterValue": "400009", + "BriefDescription": "All (macro) branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "PublicDescription": "Counts the number of near return instructions retired.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "SampleAfterValue": "100003", + "BriefDescription": "Return instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts the number of not taken branch instructions retired.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "BR_INST_RETIRED.NOT_TAKEN", + "SampleAfterValue": "400009", + "BriefDescription": "Not taken branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "PublicDescription": "Number of near taken branches retired.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "SampleAfterValue": "400009", + "BriefDescription": "Taken branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of far branches retired.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "SampleAfterValue": "100003", + "BriefDescription": "Far branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "2", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", + "SampleAfterValue": "400009", + "BriefDescription": "All (macro) branch instructions retired.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BR_MISP_RETIRED.CONDITIONAL", + "SampleAfterValue": "400009", + "BriefDescription": "Mispredicted conditional branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Mispredicted branch instructions at retirement.", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "SampleAfterValue": "400009", + "BriefDescription": "All mispredicted macro branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "2", + "PublicDescription": "This event counts all mispredicted branch instructions retired. This is a precise event.", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", + "SampleAfterValue": "400009", + "BriefDescription": "Mispredicted macro branch instructions retired. ", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Count cases of saving new LBR records by hardware.", + "EventCode": "0xCC", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", + "SampleAfterValue": "2000003", + "BriefDescription": "Count cases of saving new LBR", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.", + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "SampleAfterValue": "2000003", + "BriefDescription": "Thread cycles when thread is not in halt state", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0xa0", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired mispredicted indirect calls.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when uops are exectuted in port 0.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when uops are exectuted in port 1.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x4", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when uops are dispatched to port 2.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x8", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when uops are dispatched to port 3.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x10", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when uops are exectuted in port 4.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x20", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when uops are exectuted in port 5.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x40", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when uops are exectuted in port 6.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x80", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when uops are dispatched to port 7.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "PublicDescription": "Number of near branch instructions retired that were taken but mispredicted.", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "SampleAfterValue": "400009", + "BriefDescription": "number of near branch instructions retired that were mispredicted and taken.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This events counts the cycles where at least one uop was executed. It is counted per thread.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Errata": "HSD144, HSD30, HSM31", + "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles where at least 1 uop was executed per-thread", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "This events counts the cycles where at least two uop were executed. It is counted per thread.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Errata": "HSD144, HSD30, HSM31", + "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles where at least 2 uops were executed per-thread", + "CounterMask": "2", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "This events counts the cycles where at least three uop were executed. It is counted per thread.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Errata": "HSD144, HSD30, HSM31", + "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles where at least 3 uops were executed per-thread", + "CounterMask": "3", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Errata": "HSD144, HSD30, HSM31", + "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles where at least 4 uops were executed per-thread.", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Number of front end re-steers due to BPU misprediction.", + "EventCode": "0xe6", + "Counter": "0,1,2,3", + "UMask": "0x1f", + "EventName": "BACLEARS.ANY", + "SampleAfterValue": "100003", + "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EdgeDetect": "1", + "EventName": "MACHINE_CLEARS.COUNT", + "SampleAfterValue": "100003", + "BriefDescription": "Number of machine clears (nukes) of any type.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LSD.CYCLES_ACTIVE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LSD.CYCLES_4_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5E", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EdgeDetect": "1", + "EventName": "RS_EVENTS.EMPTY_END", + "SampleAfterValue": "200003", + "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are executed in port 0.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are executed in port 1.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are executed in port 2.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are executed in port 3.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are executed in port 4.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are executed in port 5.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "UOPS_DISPATCHED_PORT.PORT_6", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are executed in port 6.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "UOPS_DISPATCHED_PORT.PORT_7", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are executed in port 7.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x00", + "Counter": "Fixed counter 2", + "UMask": "0x2", + "AnyThread": "1", + "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "CounterHTOff": "Fixed counter 2" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x0", + "AnyThread": "1", + "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).", + "EventCode": "0x0D", + "Counter": "0,1,2,3", + "UMask": "0x3", + "AnyThread": "1", + "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xb1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "Errata": "HSD30, HSM31", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xb1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "Errata": "HSD30, HSM31", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", + "CounterMask": "2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xb1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "Errata": "HSD30, HSM31", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", + "CounterMask": "3", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xb1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "Errata": "HSD30, HSM31", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xb1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "Errata": "HSD30, HSM31", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)", + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "SampleAfterValue": "2000003", + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "2000003", + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswell/virtual-memory.json b/tools/perf/pmu-events/arch/x86/haswell/virtual-memory.json new file mode 100644 index 000000000000..ce80a08d0f08 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/haswell/virtual-memory.json @@ -0,0 +1,484 @@ +[ + { + "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.", + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", + "SampleAfterValue": "100003", + "BriefDescription": "Load misses in all DTLB levels that cause page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Completed page walks due to demand load misses that caused 4K page walks in any TLB levels.", + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "SampleAfterValue": "2000003", + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels.", + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "SampleAfterValue": "2000003", + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", + "SampleAfterValue": "2000003", + "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.", + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when PMH is busy with page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts load operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.", + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", + "SampleAfterValue": "2000003", + "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts load operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.", + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", + "SampleAfterValue": "2000003", + "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed.", + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS", + "SampleAfterValue": "100003", + "BriefDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).", + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", + "SampleAfterValue": "100003", + "BriefDescription": "Store misses in all DTLB levels that cause page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 4K page structure.", + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "SampleAfterValue": "100003", + "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 2M/4M page structure.", + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "SampleAfterValue": "100003", + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", + "SampleAfterValue": "100003", + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks. (1G)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB store misses.", + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "DTLB_STORE_MISSES.WALK_DURATION", + "SampleAfterValue": "100003", + "BriefDescription": "Cycles when PMH is busy with page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts store operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.", + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", + "SampleAfterValue": "100003", + "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts store operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.", + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", + "SampleAfterValue": "100003", + "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "DTLB store misses with low part of linear-to-physical address translation missed.", + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS", + "SampleAfterValue": "100003", + "BriefDescription": "DTLB store misses with low part of linear-to-physical address translation missed", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x4f", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "EPT.WALK_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycle count for an Extended Page table walk.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Misses in ITLB that causes a page walk of any page size.", + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", + "SampleAfterValue": "100003", + "BriefDescription": "Misses at all ITLB levels that cause page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Completed page walks due to misses in ITLB 4K page entries.", + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "SampleAfterValue": "100003", + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Completed page walks due to misses in ITLB 2M/4M page entries.", + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "SampleAfterValue": "100003", + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", + "SampleAfterValue": "100003", + "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by ITLB misses.", + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "ITLB_MISSES.WALK_DURATION", + "SampleAfterValue": "100003", + "BriefDescription": "Cycles when PMH is busy with page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "ITLB misses that hit STLB (4K).", + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "ITLB_MISSES.STLB_HIT_4K", + "SampleAfterValue": "100003", + "BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "ITLB misses that hit STLB (2M).", + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "ITLB_MISSES.STLB_HIT_2M", + "SampleAfterValue": "100003", + "BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts the number of ITLB flushes, includes 4k/2M/4M pages.", + "EventCode": "0xae", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ITLB.ITLB_FLUSH", + "SampleAfterValue": "100003", + "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of DTLB page walker loads that hit in the L1+FB.", + "EventCode": "0xBC", + "Counter": "0,1,2,3", + "UMask": "0x11", + "EventName": "PAGE_WALKER_LOADS.DTLB_L1", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of DTLB page walker hits in the L1+FB", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Number of ITLB page walker loads that hit in the L1+FB.", + "EventCode": "0xBC", + "Counter": "0,1,2,3", + "UMask": "0x21", + "EventName": "PAGE_WALKER_LOADS.ITLB_L1", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of ITLB page walker hits in the L1+FB", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBC", + "Counter": "0,1,2,3", + "UMask": "0x41", + "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L1", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBC", + "Counter": "0,1,2,3", + "UMask": "0x81", + "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L1", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB.", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Number of DTLB page walker loads that hit in the L2.", + "EventCode": "0xBC", + "Counter": "0,1,2,3", + "UMask": "0x12", + "EventName": "PAGE_WALKER_LOADS.DTLB_L2", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of DTLB page walker hits in the L2", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Number of ITLB page walker loads that hit in the L2.", + "EventCode": "0xBC", + "Counter": "0,1,2,3", + "UMask": "0x22", + "EventName": "PAGE_WALKER_LOADS.ITLB_L2", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of ITLB page walker hits in the L2", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBC", + "Counter": "0,1,2,3", + "UMask": "0x42", + "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L2", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L2.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBC", + "Counter": "0,1,2,3", + "UMask": "0x82", + "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L2", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Number of DTLB page walker loads that hit in the L3.", + "EventCode": "0xBC", + "Counter": "0,1,2,3", + "UMask": "0x14", + "Errata": "HSD25", + "EventName": "PAGE_WALKER_LOADS.DTLB_L3", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Number of ITLB page walker loads that hit in the L3.", + "EventCode": "0xBC", + "Counter": "0,1,2,3", + "UMask": "0x24", + "Errata": "HSD25", + "EventName": "PAGE_WALKER_LOADS.ITLB_L3", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBC", + "Counter": "0,1,2,3", + "UMask": "0x44", + "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L3", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L3.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBC", + "Counter": "0,1,2,3", + "UMask": "0x84", + "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L3", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Number of DTLB page walker loads from memory.", + "EventCode": "0xBC", + "Counter": "0,1,2,3", + "UMask": "0x18", + "Errata": "HSD25", + "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of DTLB page walker hits in Memory", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Number of ITLB page walker loads from memory.", + "EventCode": "0xBC", + "Counter": "0,1,2,3", + "UMask": "0x28", + "Errata": "HSD25", + "EventName": "PAGE_WALKER_LOADS.ITLB_MEMORY", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of ITLB page walker hits in Memory", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBC", + "Counter": "0,1,2,3", + "UMask": "0x48", + "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_MEMORY", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in memory.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBC", + "Counter": "0,1,2,3", + "UMask": "0x88", + "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_MEMORY", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in memory.", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "DTLB flush attempts of the thread-specific entries.", + "EventCode": "0xBD", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "TLB_FLUSH.DTLB_THREAD", + "SampleAfterValue": "100003", + "BriefDescription": "DTLB flush attempts of the thread-specific entries", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Count number of STLB flush attempts.", + "EventCode": "0xBD", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "TLB_FLUSH.STLB_ANY", + "SampleAfterValue": "100003", + "BriefDescription": "STLB flush attempts", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Completed page walks in any TLB of any page size due to demand load misses.", + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0xe", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "SampleAfterValue": "100003", + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of cache load STLB hits. No page walk.", + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x60", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "SampleAfterValue": "2000003", + "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G).", + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0xe", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "SampleAfterValue": "100003", + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x60", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "SampleAfterValue": "100003", + "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Completed page walks in ITLB of any page size.", + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0xe", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "SampleAfterValue": "100003", + "BriefDescription": "Misses in all ITLB levels that cause completed page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "ITLB misses that hit STLB. No page walk.", + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x60", + "EventName": "ITLB_MISSES.STLB_HIT", + "SampleAfterValue": "100003", + "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswellx/cache.json b/tools/perf/pmu-events/arch/x86/haswellx/cache.json new file mode 100644 index 000000000000..f1bae0817a6f --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/haswellx/cache.json @@ -0,0 +1,1077 @@ +[ + { + "EventCode": "0x24", + "UMask": "0x21", + "BriefDescription": "Demand Data Read miss L2, no rejects", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", + "Errata": "HSD78", + "PublicDescription": "Demand data read requests that missed L2, no rejects.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0x41", + "BriefDescription": "Demand Data Read requests that hit L2 cache", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "Errata": "HSD78", + "PublicDescription": "Demand data read requests that hit L2 cache.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0x30", + "BriefDescription": "L2 prefetch requests that miss L2 cache", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.L2_PF_MISS", + "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0x50", + "BriefDescription": "L2 prefetch requests that hit L2 cache", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.L2_PF_HIT", + "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0xe1", + "BriefDescription": "Demand Data Read requests", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "Errata": "HSD78", + "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0xe2", + "BriefDescription": "RFO requests to L2 cache", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.ALL_RFO", + "PublicDescription": "Counts all L2 store RFO requests.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0xe4", + "BriefDescription": "L2 code requests", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "PublicDescription": "Counts all L2 code requests.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0xf8", + "BriefDescription": "Requests from L2 hardware prefetchers", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.ALL_PF", + "PublicDescription": "Counts all L2 HW prefetcher requests.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x27", + "UMask": "0x50", + "BriefDescription": "Not rejected writebacks that hit L2 cache", + "Counter": "0,1,2,3", + "EventName": "L2_DEMAND_RQSTS.WB_HIT", + "PublicDescription": "Not rejected writebacks that hit L2 cache.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x2E", + "UMask": "0x41", + "BriefDescription": "Core-originated cacheable demand requests missed L3", + "Counter": "0,1,2,3", + "EventName": "LONGEST_LAT_CACHE.MISS", + "PublicDescription": "This event counts each cache miss condition for references to the last level cache.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x2E", + "UMask": "0x4f", + "BriefDescription": "Core-originated cacheable demand requests that refer to L3", + "Counter": "0,1,2,3", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x48", + "UMask": "0x1", + "BriefDescription": "L1D miss oustandings duration in cycles", + "Counter": "2", + "EventName": "L1D_PEND_MISS.PENDING", + "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.", + "SampleAfterValue": "2000003", + "CounterHTOff": "2" + }, + { + "EventCode": "0x48", + "UMask": "0x2", + "BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e.", + "Counter": "0,1,2,3", + "EventName": "L1D_PEND_MISS.REQUEST_FB_FULL", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x48", + "UMask": "0x1", + "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "2", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", + "CounterMask": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "2" + }, + { + "EventCode": "0x51", + "UMask": "0x1", + "BriefDescription": "L1D data line replacements", + "Counter": "0,1,2,3", + "EventName": "L1D.REPLACEMENT", + "PublicDescription": "This event counts when new data lines are brought into the L1 Data cache, which cause other lines to be evicted from the cache.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "UMask": "0x1", + "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "Errata": "HSD78, HSD62, HSD61", + "PublicDescription": "Offcore outstanding demand data read transactions in SQ to uncore. Set Cmask=1 to count cycles.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "UMask": "0x2", + "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", + "Errata": "HSD62, HSD61", + "PublicDescription": "Offcore outstanding Demand code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "UMask": "0x4", + "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", + "Errata": "HSD62, HSD61", + "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "UMask": "0x8", + "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "Errata": "HSD62, HSD61", + "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "UMask": "0x1", + "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "CounterMask": "1", + "Errata": "HSD78, HSD62, HSD61", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "UMask": "0x8", + "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "CounterMask": "1", + "Errata": "HSD62, HSD61", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "UMask": "0x4", + "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "CounterMask": "1", + "Errata": "HSD62, HSD61", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x63", + "UMask": "0x2", + "BriefDescription": "Cycles when L1D is locked", + "Counter": "0,1,2,3", + "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", + "PublicDescription": "Cycles in which the L1D is locked.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB0", + "UMask": "0x1", + "BriefDescription": "Demand Data Read requests sent to uncore", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "Errata": "HSD78", + "PublicDescription": "Demand data read requests sent to uncore.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB0", + "UMask": "0x2", + "BriefDescription": "Cacheable and noncachaeble code read requests", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "PublicDescription": "Demand code read requests sent to uncore.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB0", + "UMask": "0x4", + "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB0", + "UMask": "0x8", + "BriefDescription": "Demand and prefetch data reads", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", + "PublicDescription": "Data read requests sent to uncore (demand and prefetch).", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xb2", + "UMask": "0x1", + "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xD0", + "UMask": "0x11", + "BriefDescription": "Retired load uops that miss the STLB.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", + "Errata": "HSD29, HSM30", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD0", + "UMask": "0x12", + "BriefDescription": "Retired store uops that miss the STLB.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", + "Errata": "HSD29, HSM30", + "SampleAfterValue": "100003", + "L1_Hit_Indication": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD0", + "UMask": "0x21", + "BriefDescription": "Retired load uops with locked access.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "Errata": "HSD76, HSD29, HSM30", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD0", + "UMask": "0x41", + "BriefDescription": "Retired load uops that split across a cacheline boundary.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "Errata": "HSD29, HSM30", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD0", + "UMask": "0x42", + "BriefDescription": "Retired store uops that split across a cacheline boundary.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "Errata": "HSD29, HSM30", + "SampleAfterValue": "100003", + "L1_Hit_Indication": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD0", + "UMask": "0x81", + "BriefDescription": "All retired load uops.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "Errata": "HSD29, HSM30", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD0", + "UMask": "0x82", + "BriefDescription": "All retired store uops.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "Errata": "HSD29, HSM30", + "SampleAfterValue": "2000003", + "L1_Hit_Indication": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD1", + "UMask": "0x1", + "BriefDescription": "Retired load uops with L1 cache hits as data sources.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "Errata": "HSD29, HSM30", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD1", + "UMask": "0x2", + "BriefDescription": "Retired load uops with L2 cache hits as data sources.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "Errata": "HSD76, HSD29, HSM30", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD1", + "UMask": "0x4", + "BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", + "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", + "PublicDescription": "Retired load uops with L3 cache hits as data sources.", + "SampleAfterValue": "50021", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD1", + "UMask": "0x8", + "BriefDescription": "Retired load uops misses in L1 cache as data sources.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", + "Errata": "HSM30", + "PublicDescription": "Retired load uops missed L1 cache as data sources.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD1", + "UMask": "0x10", + "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "Errata": "HSD29, HSM30", + "PublicDescription": "Retired load uops missed L2. Unknown data source excluded.", + "SampleAfterValue": "50021", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD1", + "UMask": "0x20", + "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS", + "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", + "PublicDescription": "Retired load uops missed L3. Excludes unknown data source .", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD1", + "UMask": "0x40", + "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", + "Errata": "HSM30", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD2", + "UMask": "0x1", + "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS", + "Errata": "HSD29, HSD25, HSM26, HSM30", + "SampleAfterValue": "20011", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD2", + "UMask": "0x2", + "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT", + "Errata": "HSD29, HSD25, HSM26, HSM30", + "SampleAfterValue": "20011", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD2", + "UMask": "0x4", + "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM", + "Errata": "HSD29, HSD25, HSM26, HSM30", + "SampleAfterValue": "20011", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD2", + "UMask": "0x8", + "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE", + "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD3", + "UMask": "0x1", + "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", + "Errata": "HSD74, HSD29, HSD25, HSM30", + "PublicDescription": "This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD3", + "UMask": "0x4", + "BriefDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI)", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM", + "Errata": "HSD29, HSM30", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD3", + "UMask": "0x10", + "BriefDescription": "Retired load uop whose Data Source was: Remote cache HITM", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM", + "Errata": "HSM30", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD3", + "UMask": "0x20", + "BriefDescription": "Retired load uop whose Data Source was: forwarded from remote cache", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD", + "Errata": "HSM30", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xf0", + "UMask": "0x1", + "BriefDescription": "Demand Data Read requests that access L2 cache", + "Counter": "0,1,2,3", + "EventName": "L2_TRANS.DEMAND_DATA_RD", + "PublicDescription": "Demand data read requests that access L2 cache.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xf0", + "UMask": "0x2", + "BriefDescription": "RFO requests that access L2 cache", + "Counter": "0,1,2,3", + "EventName": "L2_TRANS.RFO", + "PublicDescription": "RFO requests that access L2 cache.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xf0", + "UMask": "0x4", + "BriefDescription": "L2 cache accesses when fetching instructions", + "Counter": "0,1,2,3", + "EventName": "L2_TRANS.CODE_RD", + "PublicDescription": "L2 cache accesses when fetching instructions.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xf0", + "UMask": "0x8", + "BriefDescription": "L2 or L3 HW prefetches that access L2 cache", + "Counter": "0,1,2,3", + "EventName": "L2_TRANS.ALL_PF", + "PublicDescription": "Any MLC or L3 HW prefetch accessing L2, including rejects.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xf0", + "UMask": "0x10", + "BriefDescription": "L1D writebacks that access L2 cache", + "Counter": "0,1,2,3", + "EventName": "L2_TRANS.L1D_WB", + "PublicDescription": "L1D writebacks that access L2 cache.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xf0", + "UMask": "0x20", + "BriefDescription": "L2 fill requests that access L2 cache", + "Counter": "0,1,2,3", + "EventName": "L2_TRANS.L2_FILL", + "PublicDescription": "L2 fill requests that access L2 cache.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xf0", + "UMask": "0x40", + "BriefDescription": "L2 writebacks that access L2 cache", + "Counter": "0,1,2,3", + "EventName": "L2_TRANS.L2_WB", + "PublicDescription": "L2 writebacks that access L2 cache.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xf0", + "UMask": "0x80", + "BriefDescription": "Transactions accessing L2 pipe", + "Counter": "0,1,2,3", + "EventName": "L2_TRANS.ALL_REQUESTS", + "PublicDescription": "Transactions accessing L2 pipe.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF1", + "UMask": "0x1", + "BriefDescription": "L2 cache lines in I state filling L2", + "Counter": "0,1,2,3", + "EventName": "L2_LINES_IN.I", + "PublicDescription": "L2 cache lines in I state filling L2.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF1", + "UMask": "0x2", + "BriefDescription": "L2 cache lines in S state filling L2", + "Counter": "0,1,2,3", + "EventName": "L2_LINES_IN.S", + "PublicDescription": "L2 cache lines in S state filling L2.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF1", + "UMask": "0x4", + "BriefDescription": "L2 cache lines in E state filling L2", + "Counter": "0,1,2,3", + "EventName": "L2_LINES_IN.E", + "PublicDescription": "L2 cache lines in E state filling L2.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF1", + "UMask": "0x7", + "BriefDescription": "L2 cache lines filling L2", + "Counter": "0,1,2,3", + "EventName": "L2_LINES_IN.ALL", + "PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF2", + "UMask": "0x5", + "BriefDescription": "Clean L2 cache lines evicted by demand", + "Counter": "0,1,2,3", + "EventName": "L2_LINES_OUT.DEMAND_CLEAN", + "PublicDescription": "Clean L2 cache lines evicted by demand.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF2", + "UMask": "0x6", + "BriefDescription": "Dirty L2 cache lines evicted by demand", + "Counter": "0,1,2,3", + "EventName": "L2_LINES_OUT.DEMAND_DIRTY", + "PublicDescription": "Dirty L2 cache lines evicted by demand.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xf4", + "UMask": "0x10", + "BriefDescription": "Split locks in SQ", + "Counter": "0,1,2,3", + "EventName": "SQ_MISC.SPLIT_LOCK", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0x42", + "BriefDescription": "RFO requests that hit L2 cache", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.RFO_HIT", + "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0x22", + "BriefDescription": "RFO requests that miss L2 cache", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.RFO_MISS", + "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0x44", + "BriefDescription": "L2 cache hits when fetching instructions, code reads.", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.CODE_RD_HIT", + "PublicDescription": "Number of instruction fetches that hit the L2 cache.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0x24", + "BriefDescription": "L2 cache misses when fetching instructions", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.CODE_RD_MISS", + "PublicDescription": "Number of instruction fetches that missed the L2 cache.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0x27", + "BriefDescription": "Demand requests that miss L2 cache", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.ALL_DEMAND_MISS", + "Errata": "HSD78", + "PublicDescription": "Demand requests that miss L2 cache.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0xe7", + "BriefDescription": "Demand requests to L2 cache", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", + "Errata": "HSD78", + "PublicDescription": "Demand requests to L2 cache.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0x3f", + "BriefDescription": "All requests that miss L2 cache", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.MISS", + "Errata": "HSD78", + "PublicDescription": "All requests that missed L2.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "UMask": "0xff", + "BriefDescription": "All L2 requests", + "Counter": "0,1,2,3", + "EventName": "L2_RQSTS.REFERENCES", + "Errata": "HSD78", + "PublicDescription": "All requests to L2 cache.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x60", + "UMask": "0x1", + "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", + "CounterMask": "6", + "Errata": "HSD78, HSD62, HSD61", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x48", + "UMask": "0x1", + "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", + "Counter": "2", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", + "AnyThread": "1", + "CounterMask": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "2" + }, + { + "EventCode": "0x48", + "UMask": "0x2", + "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", + "Counter": "0,1,2,3", + "EventName": "L1D_PEND_MISS.FB_FULL", + "CounterMask": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "MSRValue": "0x04003c0001", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "MSRValue": "0x10003c0001", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "MSRValue": "0x04003c0002", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "MSRValue": "0x10003c0002", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all demand code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "MSRValue": "0x04003c0004", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "MSRValue": "0x10003c0004", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3", + "MSRValue": "0x3f803c0010", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3", + "MSRValue": "0x3f803c0020", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3", + "MSRValue": "0x3f803c0040", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3", + "MSRValue": "0x3f803c0080", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3", + "MSRValue": "0x3f803c0100", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3", + "MSRValue": "0x3f803c0200", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "MSRValue": "0x04003c0091", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "MSRValue": "0x10003c0091", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "MSRValue": "0x04003c0122", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "MSRValue": "0x10003c0122", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all demand & prefetch code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "MSRValue": "0x04003c0244", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "MSRValue": "0x04003c07f7", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "MSRValue": "0x10003c07f7", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all requests that hit in the L3", + "MSRValue": "0x3f803c8fff", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswellx/floating-point.json b/tools/perf/pmu-events/arch/x86/haswellx/floating-point.json new file mode 100644 index 000000000000..6282aed6e090 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/haswellx/floating-point.json @@ -0,0 +1,83 @@ +[ + { + "EventCode": "0xC1", + "UMask": "0x8", + "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.", + "Counter": "0,1,2,3", + "EventName": "OTHER_ASSISTS.AVX_TO_SSE", + "Errata": "HSD56, HSM57", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC1", + "UMask": "0x10", + "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.", + "Counter": "0,1,2,3", + "EventName": "OTHER_ASSISTS.SSE_TO_AVX", + "Errata": "HSD56, HSM57", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xCA", + "UMask": "0x2", + "BriefDescription": "Number of X87 assists due to output value.", + "Counter": "0,1,2,3", + "EventName": "FP_ASSIST.X87_OUTPUT", + "PublicDescription": "Number of X87 FP assists due to output values.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xCA", + "UMask": "0x4", + "BriefDescription": "Number of X87 assists due to input value.", + "Counter": "0,1,2,3", + "EventName": "FP_ASSIST.X87_INPUT", + "PublicDescription": "Number of X87 FP assists due to input values.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xCA", + "UMask": "0x8", + "BriefDescription": "Number of SIMD FP assists due to Output values", + "Counter": "0,1,2,3", + "EventName": "FP_ASSIST.SIMD_OUTPUT", + "PublicDescription": "Number of SIMD FP assists due to output values.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xCA", + "UMask": "0x10", + "BriefDescription": "Number of SIMD FP assists due to input values", + "Counter": "0,1,2,3", + "EventName": "FP_ASSIST.SIMD_INPUT", + "PublicDescription": "Number of SIMD FP assists due to input values.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xCA", + "UMask": "0x1e", + "BriefDescription": "Cycles with any input/output SSE or FP assist", + "Counter": "0,1,2,3", + "EventName": "FP_ASSIST.ANY", + "CounterMask": "1", + "PublicDescription": "Cycles with any input/output SSE* or FP assists.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC6", + "UMask": "0x7", + "BriefDescription": "Approximate counts of AVX & AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores. May count non-AVX instructions that employ 256-bit operations, including (but not necessarily limited to) rep string instructions that use 256-bit loads and stores for optimized performance, XSAVE* and XRSTOR*, and operations that transition the x87 FPU data registers between x87 and MMX.", + "Counter": "0,1,2,3", + "EventName": "AVX_INSTS.ALL", + "PublicDescription": "Note that a whole rep string only counts AVX_INST.ALL once.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswellx/frontend.json b/tools/perf/pmu-events/arch/x86/haswellx/frontend.json new file mode 100644 index 000000000000..2d0c7aac1e61 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/haswellx/frontend.json @@ -0,0 +1,294 @@ +[ + { + "EventCode": "0x79", + "UMask": "0x2", + "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", + "Counter": "0,1,2,3", + "EventName": "IDQ.EMPTY", + "Errata": "HSD135", + "PublicDescription": "Counts cycles the IDQ is empty.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x79", + "UMask": "0x4", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "Counter": "0,1,2,3", + "EventName": "IDQ.MITE_UOPS", + "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "UMask": "0x8", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", + "EventName": "IDQ.DSB_UOPS", + "PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "UMask": "0x10", + "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "EventName": "IDQ.MS_DSB_UOPS", + "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "UMask": "0x20", + "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "EventName": "IDQ.MS_MITE_UOPS", + "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "UMask": "0x30", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "EventName": "IDQ.MS_UOPS", + "PublicDescription": "This event counts uops delivered by the Front-end with the assistance of the microcode sequencer. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "UMask": "0x30", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "EventName": "IDQ.MS_CYCLES", + "CounterMask": "1", + "PublicDescription": "This event counts cycles during which the microcode sequencer assisted the Front-end in delivering uops. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "UMask": "0x4", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.", + "Counter": "0,1,2,3", + "EventName": "IDQ.MITE_CYCLES", + "CounterMask": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "UMask": "0x8", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", + "Counter": "0,1,2,3", + "EventName": "IDQ.DSB_CYCLES", + "CounterMask": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "UMask": "0x10", + "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "Counter": "0,1,2,3", + "EventName": "IDQ.MS_DSB_CYCLES", + "CounterMask": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EdgeDetect": "1", + "EventCode": "0x79", + "UMask": "0x10", + "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.", + "Counter": "0,1,2,3", + "EventName": "IDQ.MS_DSB_OCCUR", + "CounterMask": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "UMask": "0x18", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", + "Counter": "0,1,2,3", + "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", + "CounterMask": "4", + "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "UMask": "0x18", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", + "Counter": "0,1,2,3", + "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", + "CounterMask": "1", + "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "UMask": "0x24", + "BriefDescription": "Cycles MITE is delivering 4 Uops", + "Counter": "0,1,2,3", + "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", + "CounterMask": "4", + "PublicDescription": "Counts cycles MITE is delivered four uops. Set Cmask = 4.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "UMask": "0x24", + "BriefDescription": "Cycles MITE is delivering any Uop", + "Counter": "0,1,2,3", + "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", + "CounterMask": "1", + "PublicDescription": "Counts cycles MITE is delivered at least one uop. Set Cmask = 1.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "UMask": "0x3c", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "Counter": "0,1,2,3", + "EventName": "IDQ.MITE_ALL_UOPS", + "PublicDescription": "Number of uops delivered to IDQ from any path.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x80", + "UMask": "0x1", + "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.", + "Counter": "0,1,2,3", + "EventName": "ICACHE.HIT", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x80", + "UMask": "0x2", + "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.", + "Counter": "0,1,2,3", + "EventName": "ICACHE.MISSES", + "PublicDescription": "This event counts Instruction Cache (ICACHE) misses.", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x80", + "UMask": "0x4", + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", + "Counter": "0,1,2,3", + "EventName": "ICACHE.IFETCH_STALL", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x9C", + "UMask": "0x1", + "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled", + "Counter": "0,1,2,3", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "Errata": "HSD135", + "PublicDescription": "This event count the number of undelivered (unallocated) uops from the Front-end to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled. The Front-end can allocate up to 4 uops per cycle so this event can increment 0-4 times per cycle depending on the number of unallocated uops. This event is counted on a per-core basis.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "UMask": "0x1", + "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled", + "Counter": "0,1,2,3", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "CounterMask": "4", + "Errata": "HSD135", + "PublicDescription": "This event counts the number cycles during which the Front-end allocated exactly zero uops to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled. This event is counted on a per-core basis.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "UMask": "0x1", + "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", + "Counter": "0,1,2,3", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", + "CounterMask": "3", + "Errata": "HSD135", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "UMask": "0x1", + "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", + "Counter": "0,1,2,3", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", + "CounterMask": "2", + "Errata": "HSD135", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "UMask": "0x1", + "BriefDescription": "Cycles with less than 3 uops delivered by the front end.", + "Counter": "0,1,2,3", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", + "CounterMask": "1", + "Errata": "HSD135", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "Invert": "1", + "EventCode": "0x9C", + "UMask": "0x1", + "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.", + "Counter": "0,1,2,3", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "CounterMask": "1", + "Errata": "HSD135", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xAB", + "UMask": "0x2", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", + "Counter": "0,1,2,3", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EdgeDetect": "1", + "EventCode": "0x79", + "UMask": "0x30", + "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "Counter": "0,1,2,3", + "EventName": "IDQ.MS_SWITCHES", + "CounterMask": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x80", + "UMask": "0x4", + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", + "Counter": "0,1,2,3", + "EventName": "ICACHE.IFDATA_STALL", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswellx/memory.json b/tools/perf/pmu-events/arch/x86/haswellx/memory.json new file mode 100644 index 000000000000..0886cc000d22 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/haswellx/memory.json @@ -0,0 +1,739 @@ +[ + { + "EventCode": "0x05", + "UMask": "0x1", + "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", + "Counter": "0,1,2,3", + "EventName": "MISALIGN_MEM_REF.LOADS", + "PublicDescription": "Speculative cache-line split load uops dispatched to L1D.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x05", + "UMask": "0x2", + "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", + "Counter": "0,1,2,3", + "EventName": "MISALIGN_MEM_REF.STORES", + "PublicDescription": "Speculative cache-line split store-address uops dispatched to L1D.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x54", + "UMask": "0x1", + "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address.", + "Counter": "0,1,2,3", + "EventName": "TX_MEM.ABORT_CONFLICT", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x54", + "UMask": "0x2", + "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional writes.", + "Counter": "0,1,2,3", + "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x54", + "UMask": "0x4", + "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer.", + "Counter": "0,1,2,3", + "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x54", + "UMask": "0x8", + "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.", + "Counter": "0,1,2,3", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x54", + "UMask": "0x10", + "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer.", + "Counter": "0,1,2,3", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x54", + "UMask": "0x20", + "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.", + "Counter": "0,1,2,3", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x54", + "UMask": "0x40", + "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.", + "Counter": "0,1,2,3", + "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5d", + "UMask": "0x1", + "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", + "Counter": "0,1,2,3", + "EventName": "TX_EXEC.MISC1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5d", + "UMask": "0x2", + "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region.", + "Counter": "0,1,2,3", + "EventName": "TX_EXEC.MISC2", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5d", + "UMask": "0x4", + "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded.", + "Counter": "0,1,2,3", + "EventName": "TX_EXEC.MISC3", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5d", + "UMask": "0x8", + "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", + "Counter": "0,1,2,3", + "EventName": "TX_EXEC.MISC4", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5d", + "UMask": "0x10", + "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", + "Counter": "0,1,2,3", + "EventName": "TX_EXEC.MISC5", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC3", + "UMask": "0x2", + "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", + "Counter": "0,1,2,3", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "PublicDescription": "This event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data inflight in the pipeline. Machine clears can have a significant performance impact if they are happening frequently.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC8", + "UMask": "0x1", + "BriefDescription": "Number of times an HLE execution started.", + "Counter": "0,1,2,3", + "EventName": "HLE_RETIRED.START", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xc8", + "UMask": "0x2", + "BriefDescription": "Number of times an HLE execution successfully committed.", + "Counter": "0,1,2,3", + "EventName": "HLE_RETIRED.COMMIT", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xc8", + "UMask": "0x4", + "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "HLE_RETIRED.ABORTED", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xc8", + "UMask": "0x8", + "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", + "Counter": "0,1,2,3", + "EventName": "HLE_RETIRED.ABORTED_MISC1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xc8", + "UMask": "0x10", + "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions.", + "Counter": "0,1,2,3", + "EventName": "HLE_RETIRED.ABORTED_MISC2", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xc8", + "UMask": "0x20", + "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions.", + "Counter": "0,1,2,3", + "EventName": "HLE_RETIRED.ABORTED_MISC3", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xc8", + "UMask": "0x40", + "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type.", + "Counter": "0,1,2,3", + "EventName": "HLE_RETIRED.ABORTED_MISC4", + "Errata": "HSD65", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xc8", + "UMask": "0x80", + "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)", + "Counter": "0,1,2,3", + "EventName": "HLE_RETIRED.ABORTED_MISC5", + "PublicDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts).", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC9", + "UMask": "0x1", + "BriefDescription": "Number of times an RTM execution started.", + "Counter": "0,1,2,3", + "EventName": "RTM_RETIRED.START", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xc9", + "UMask": "0x2", + "BriefDescription": "Number of times an RTM execution successfully committed.", + "Counter": "0,1,2,3", + "EventName": "RTM_RETIRED.COMMIT", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xc9", + "UMask": "0x4", + "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "RTM_RETIRED.ABORTED", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xc9", + "UMask": "0x8", + "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", + "Counter": "0,1,2,3", + "EventName": "RTM_RETIRED.ABORTED_MISC1", + "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xc9", + "UMask": "0x10", + "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).", + "Counter": "0,1,2,3", + "EventName": "RTM_RETIRED.ABORTED_MISC2", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xc9", + "UMask": "0x20", + "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.", + "Counter": "0,1,2,3", + "EventName": "RTM_RETIRED.ABORTED_MISC3", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xc9", + "UMask": "0x40", + "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type.", + "Counter": "0,1,2,3", + "EventName": "RTM_RETIRED.ABORTED_MISC4", + "Errata": "HSD65", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xc9", + "UMask": "0x80", + "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", + "Counter": "0,1,2,3", + "EventName": "RTM_RETIRED.ABORTED_MISC5", + "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xCD", + "UMask": "0x1", + "BriefDescription": "Loads with latency value being above 4.", + "PEBS": "2", + "MSRValue": "0x4", + "Counter": "3", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "Errata": "HSD76, HSD25, HSM26", + "TakenAlone": "1", + "SampleAfterValue": "100003", + "CounterHTOff": "3" + }, + { + "EventCode": "0xCD", + "UMask": "0x1", + "BriefDescription": "Loads with latency value being above 8.", + "PEBS": "2", + "MSRValue": "0x8", + "Counter": "3", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "MSRIndex": "0x3F6", + "Errata": "HSD76, HSD25, HSM26", + "TakenAlone": "1", + "SampleAfterValue": "50021", + "CounterHTOff": "3" + }, + { + "EventCode": "0xCD", + "UMask": "0x1", + "BriefDescription": "Loads with latency value being above 16.", + "PEBS": "2", + "MSRValue": "0x10", + "Counter": "3", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "MSRIndex": "0x3F6", + "Errata": "HSD76, HSD25, HSM26", + "TakenAlone": "1", + "SampleAfterValue": "20011", + "CounterHTOff": "3" + }, + { + "EventCode": "0xCD", + "UMask": "0x1", + "BriefDescription": "Loads with latency value being above 32.", + "PEBS": "2", + "MSRValue": "0x20", + "Counter": "3", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "MSRIndex": "0x3F6", + "Errata": "HSD76, HSD25, HSM26", + "TakenAlone": "1", + "SampleAfterValue": "100003", + "CounterHTOff": "3" + }, + { + "EventCode": "0xCD", + "UMask": "0x1", + "BriefDescription": "Loads with latency value being above 64.", + "PEBS": "2", + "MSRValue": "0x40", + "Counter": "3", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "MSRIndex": "0x3F6", + "Errata": "HSD76, HSD25, HSM26", + "TakenAlone": "1", + "SampleAfterValue": "2003", + "CounterHTOff": "3" + }, + { + "EventCode": "0xCD", + "UMask": "0x1", + "BriefDescription": "Loads with latency value being above 128.", + "PEBS": "2", + "MSRValue": "0x80", + "Counter": "3", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "MSRIndex": "0x3F6", + "Errata": "HSD76, HSD25, HSM26", + "TakenAlone": "1", + "SampleAfterValue": "1009", + "CounterHTOff": "3" + }, + { + "EventCode": "0xCD", + "UMask": "0x1", + "BriefDescription": "Loads with latency value being above 256.", + "PEBS": "2", + "MSRValue": "0x100", + "Counter": "3", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "MSRIndex": "0x3F6", + "Errata": "HSD76, HSD25, HSM26", + "TakenAlone": "1", + "SampleAfterValue": "503", + "CounterHTOff": "3" + }, + { + "EventCode": "0xCD", + "UMask": "0x1", + "BriefDescription": "Loads with latency value being above 512.", + "PEBS": "2", + "MSRValue": "0x200", + "Counter": "3", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "MSRIndex": "0x3F6", + "Errata": "HSD76, HSD25, HSM26", + "TakenAlone": "1", + "SampleAfterValue": "101", + "CounterHTOff": "3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts demand data reads that miss in the L3", + "MSRValue": "0x3fbfc00001", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local dram", + "MSRValue": "0x0600400001", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all demand data writes (RFOs) that miss in the L3", + "MSRValue": "0x3fbfc00002", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram", + "MSRValue": "0x0600400002", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache", + "MSRValue": "0x103fc00002", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all demand code reads that miss in the L3", + "MSRValue": "0x3fbfc00004", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local dram", + "MSRValue": "0x0600400004", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the L3", + "MSRValue": "0x3fbfc00010", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss in the L3", + "MSRValue": "0x3fbfc00020", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the L3", + "MSRValue": "0x3fbfc00040", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss in the L3", + "MSRValue": "0x3fbfc00080", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3", + "MSRValue": "0x3fbfc00100", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that miss in the L3", + "MSRValue": "0x3fbfc00200", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all demand & prefetch data reads that miss in the L3", + "MSRValue": "0x3fbfc00091", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram", + "MSRValue": "0x0600400091", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram", + "MSRValue": "0x063f800091", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache", + "MSRValue": "0x103fc00091", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache", + "MSRValue": "0x083fc00091", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all demand & prefetch RFOs that miss in the L3", + "MSRValue": "0x3fbfc00122", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram", + "MSRValue": "0x0600400122", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all demand & prefetch code reads that miss in the L3", + "MSRValue": "0x3fbfc00244", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all demand & prefetch code reads that miss the L3 and the data is returned from local dram", + "MSRValue": "0x0600400244", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss in the L3", + "MSRValue": "0x3fbfc007f7", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from local dram", + "MSRValue": "0x06004007f7", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from remote dram", + "MSRValue": "0x063f8007f7", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the modified data is transferred from remote cache", + "MSRValue": "0x103fc007f7", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and clean or shared data is transferred from remote cache", + "MSRValue": "0x083fc007f7", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + }, + { + "Offcore": "1", + "EventCode": "0xB7, 0xBB", + "UMask": "0x1", + "BriefDescription": "Counts all requests that miss in the L3", + "MSRValue": "0x3fbfc08fff", + "Counter": "0,1,2,3", + "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswellx/other.json b/tools/perf/pmu-events/arch/x86/haswellx/other.json new file mode 100644 index 000000000000..4e1b6ce96ca3 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/haswellx/other.json @@ -0,0 +1,43 @@ +[ + { + "EventCode": "0x5C", + "UMask": "0x1", + "BriefDescription": "Unhalted core cycles when the thread is in ring 0", + "Counter": "0,1,2,3", + "EventName": "CPL_CYCLES.RING0", + "PublicDescription": "Unhalted core cycles when the thread is in ring 0.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5C", + "UMask": "0x2", + "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", + "Counter": "0,1,2,3", + "EventName": "CPL_CYCLES.RING123", + "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EdgeDetect": "1", + "EventCode": "0x5C", + "UMask": "0x1", + "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.", + "Counter": "0,1,2,3", + "EventName": "CPL_CYCLES.RING0_TRANS", + "CounterMask": "1", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x63", + "UMask": "0x1", + "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", + "Counter": "0,1,2,3", + "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", + "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswellx/pipeline.json b/tools/perf/pmu-events/arch/x86/haswellx/pipeline.json new file mode 100644 index 000000000000..c3a163d34bd7 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/haswellx/pipeline.json @@ -0,0 +1,1329 @@ +[ + { + "EventCode": "0x00", + "UMask": "0x1", + "BriefDescription": "Instructions retired from execution.", + "Counter": "Fixed counter 1", + "EventName": "INST_RETIRED.ANY", + "Errata": "HSD140, HSD143", + "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. INST_RETIRED.ANY is counted by a designated fixed counter, leaving the programmable counters available for other events. Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.", + "SampleAfterValue": "2000003", + "CounterHTOff": "Fixed counter 1" + }, + { + "EventCode": "0x00", + "UMask": "0x2", + "BriefDescription": "Core cycles when the thread is not in halt state.", + "Counter": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "PublicDescription": "This event counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.", + "SampleAfterValue": "2000003", + "CounterHTOff": "Fixed counter 2" + }, + { + "EventCode": "0x00", + "UMask": "0x3", + "BriefDescription": "Reference cycles when the core is not in halt state.", + "Counter": "Fixed counter 3", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state.", + "SampleAfterValue": "2000003", + "CounterHTOff": "Fixed counter 3" + }, + { + "EventCode": "0x03", + "UMask": "0x2", + "BriefDescription": "loads blocked by overlapping with store buffer that cannot be forwarded", + "Counter": "0,1,2,3", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. The penalty for blocked store forwarding is that the load must wait for the store to write its value to the cache before it can be issued.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x03", + "UMask": "0x8", + "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use", + "Counter": "0,1,2,3", + "EventName": "LD_BLOCKS.NO_SR", + "PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x07", + "UMask": "0x1", + "BriefDescription": "False dependencies in MOB due to partial compare on address.", + "Counter": "0,1,2,3", + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "PublicDescription": "Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K. This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline which can have a performance impact.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0D", + "UMask": "0x3", + "BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)", + "Counter": "0,1,2,3", + "EventName": "INT_MISC.RECOVERY_CYCLES", + "CounterMask": "1", + "PublicDescription": "This event counts the number of cycles spent waiting for a recovery after an event such as a processor nuke, JEClear, assist, hle/rtm abort etc.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0E", + "UMask": "0x1", + "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)", + "Counter": "0,1,2,3", + "EventName": "UOPS_ISSUED.ANY", + "PublicDescription": "This event counts the number of uops issued by the Front-end of the pipeline to the Back-end. This event is counted at the allocation stage and will count both retired and non-retired uops.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0E", + "UMask": "0x10", + "BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.", + "Counter": "0,1,2,3", + "EventName": "UOPS_ISSUED.FLAGS_MERGE", + "PublicDescription": "Number of flags-merge uops allocated. Such uops add delay.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0E", + "UMask": "0x20", + "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", + "Counter": "0,1,2,3", + "EventName": "UOPS_ISSUED.SLOW_LEA", + "PublicDescription": "Number of slow LEA or similar uops allocated. Such uop has 3 sources (for example, 2 sources + immediate) regardless of whether it is a result of LEA instruction or not.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0E", + "UMask": "0x40", + "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated", + "Counter": "0,1,2,3", + "EventName": "UOPS_ISSUED.SINGLE_MUL", + "PublicDescription": "Number of multiply packed/scalar single precision uops allocated.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "Invert": "1", + "EventCode": "0x0E", + "UMask": "0x1", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.", + "Counter": "0,1,2,3", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "CounterMask": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "Invert": "1", + "EventCode": "0x0E", + "UMask": "0x1", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.", + "Counter": "0,1,2,3", + "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", + "AnyThread": "1", + "CounterMask": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x14", + "UMask": "0x2", + "BriefDescription": "Any uop executed by the Divider. (This includes all divide uops, sqrt, ...)", + "Counter": "0,1,2,3", + "EventName": "ARITH.DIVIDER_UOPS", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "UMask": "0x1", + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", + "Counter": "0,1,2,3", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", + "PublicDescription": "Increments at the frequency of XCLK (100 MHz) when not halted.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3c", + "UMask": "0x2", + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", + "Counter": "0,1,2,3", + "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x4c", + "UMask": "0x1", + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch", + "Counter": "0,1,2,3", + "EventName": "LOAD_HIT_PRE.SW_PF", + "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x4c", + "UMask": "0x2", + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch", + "Counter": "0,1,2,3", + "EventName": "LOAD_HIT_PRE.HW_PF", + "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x58", + "UMask": "0x1", + "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.", + "Counter": "0,1,2,3", + "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", + "PublicDescription": "Number of integer move elimination candidate uops that were eliminated.", + "SampleAfterValue": "1000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x58", + "UMask": "0x2", + "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.", + "Counter": "0,1,2,3", + "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", + "PublicDescription": "Number of SIMD move elimination candidate uops that were eliminated.", + "SampleAfterValue": "1000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x58", + "UMask": "0x4", + "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.", + "Counter": "0,1,2,3", + "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", + "PublicDescription": "Number of integer move elimination candidate uops that were not eliminated.", + "SampleAfterValue": "1000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x58", + "UMask": "0x8", + "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.", + "Counter": "0,1,2,3", + "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", + "PublicDescription": "Number of SIMD move elimination candidate uops that were not eliminated.", + "SampleAfterValue": "1000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5E", + "UMask": "0x1", + "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", + "Counter": "0,1,2,3", + "EventName": "RS_EVENTS.EMPTY_CYCLES", + "PublicDescription": "This event counts cycles when the Reservation Station ( RS ) is empty for the thread. The RS is a structure that buffers allocated micro-ops from the Front-end. If there are many cycles when the RS is empty, it may represent an underflow of instructions delivered from the Front-end.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x87", + "UMask": "0x1", + "BriefDescription": "Stalls caused by changing prefix length of the instruction.", + "Counter": "0,1,2,3", + "EventName": "ILD_STALL.LCP", + "PublicDescription": "This event counts cycles where the decoder is stalled on an instruction with a length changing prefix (LCP).", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x87", + "UMask": "0x4", + "BriefDescription": "Stall cycles because IQ is full", + "Counter": "0,1,2,3", + "EventName": "ILD_STALL.IQ_FULL", + "PublicDescription": "Stall cycles due to IQ is full.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "UMask": "0x41", + "BriefDescription": "Not taken macro-conditional branches.", + "Counter": "0,1,2,3", + "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "UMask": "0x81", + "BriefDescription": "Taken speculative and retired macro-conditional branches.", + "Counter": "0,1,2,3", + "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "UMask": "0x82", + "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.", + "Counter": "0,1,2,3", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "UMask": "0x84", + "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns.", + "Counter": "0,1,2,3", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "UMask": "0x88", + "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic.", + "Counter": "0,1,2,3", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "UMask": "0x90", + "BriefDescription": "Taken speculative and retired direct near calls.", + "Counter": "0,1,2,3", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "UMask": "0xa0", + "BriefDescription": "Taken speculative and retired indirect calls.", + "Counter": "0,1,2,3", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "UMask": "0xc1", + "BriefDescription": "Speculative and retired macro-conditional branches.", + "Counter": "0,1,2,3", + "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "UMask": "0xc2", + "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.", + "Counter": "0,1,2,3", + "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "UMask": "0xc4", + "BriefDescription": "Speculative and retired indirect branches excluding calls and returns.", + "Counter": "0,1,2,3", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "UMask": "0xc8", + "BriefDescription": "Speculative and retired indirect return branches.", + "Counter": "0,1,2,3", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "UMask": "0xd0", + "BriefDescription": "Speculative and retired direct near calls.", + "Counter": "0,1,2,3", + "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "UMask": "0xff", + "BriefDescription": "Speculative and retired branches", + "Counter": "0,1,2,3", + "EventName": "BR_INST_EXEC.ALL_BRANCHES", + "PublicDescription": "Counts all near executed branches (not necessarily retired).", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "UMask": "0x41", + "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches.", + "Counter": "0,1,2,3", + "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "UMask": "0x81", + "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches.", + "Counter": "0,1,2,3", + "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "UMask": "0x84", + "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns.", + "Counter": "0,1,2,3", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "UMask": "0x88", + "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic.", + "Counter": "0,1,2,3", + "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "UMask": "0xc1", + "BriefDescription": "Speculative and retired mispredicted macro conditional branches.", + "Counter": "0,1,2,3", + "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "UMask": "0xc4", + "BriefDescription": "Mispredicted indirect branches excluding calls and returns.", + "Counter": "0,1,2,3", + "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "UMask": "0xff", + "BriefDescription": "Speculative and retired mispredicted macro conditional branches", + "Counter": "0,1,2,3", + "EventName": "BR_MISP_EXEC.ALL_BRANCHES", + "PublicDescription": "Counts all near executed branches (not necessarily retired).", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x1", + "BriefDescription": "Cycles per thread when uops are executed in port 0", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_0", + "PublicDescription": "Cycles which a uop is dispatched on port 0 in this thread.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x2", + "BriefDescription": "Cycles per thread when uops are executed in port 1", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_1", + "PublicDescription": "Cycles which a uop is dispatched on port 1 in this thread.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x4", + "BriefDescription": "Cycles per thread when uops are executed in port 2", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_2", + "PublicDescription": "Cycles which a uop is dispatched on port 2 in this thread.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x8", + "BriefDescription": "Cycles per thread when uops are executed in port 3", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_3", + "PublicDescription": "Cycles which a uop is dispatched on port 3 in this thread.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x10", + "BriefDescription": "Cycles per thread when uops are executed in port 4", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_4", + "PublicDescription": "Cycles which a uop is dispatched on port 4 in this thread.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x20", + "BriefDescription": "Cycles per thread when uops are executed in port 5", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_5", + "PublicDescription": "Cycles which a uop is dispatched on port 5 in this thread.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x40", + "BriefDescription": "Cycles per thread when uops are executed in port 6", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_6", + "PublicDescription": "Cycles which a uop is dispatched on port 6 in this thread.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x80", + "BriefDescription": "Cycles per thread when uops are executed in port 7", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_7", + "PublicDescription": "Cycles which a uop is dispatched on port 7 in this thread.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA2", + "UMask": "0x1", + "BriefDescription": "Resource-related stall cycles", + "Counter": "0,1,2,3", + "EventName": "RESOURCE_STALLS.ANY", + "Errata": "HSD135", + "PublicDescription": "Cycles allocation is stalled due to resource related reason.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA2", + "UMask": "0x4", + "BriefDescription": "Cycles stalled due to no eligible RS entry available.", + "Counter": "0,1,2,3", + "EventName": "RESOURCE_STALLS.RS", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA2", + "UMask": "0x8", + "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", + "Counter": "0,1,2,3", + "EventName": "RESOURCE_STALLS.SB", + "PublicDescription": "This event counts cycles during which no instructions were allocated because no Store Buffers (SB) were available.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA2", + "UMask": "0x10", + "BriefDescription": "Cycles stalled due to re-order buffer full.", + "Counter": "0,1,2,3", + "EventName": "RESOURCE_STALLS.ROB", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA3", + "UMask": "0x1", + "BriefDescription": "Cycles with pending L2 cache miss loads.", + "Counter": "0,1,2,3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", + "CounterMask": "1", + "Errata": "HSD78", + "PublicDescription": "Cycles with pending L2 miss loads. Set Cmask=2 to count cycle.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA3", + "UMask": "0x8", + "BriefDescription": "Cycles with pending L1 cache miss loads.", + "Counter": "2", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", + "CounterMask": "8", + "PublicDescription": "Cycles with pending L1 data cache miss loads. Set Cmask=8 to count cycle.", + "SampleAfterValue": "2000003", + "CounterHTOff": "2" + }, + { + "EventCode": "0xA3", + "UMask": "0x2", + "BriefDescription": "Cycles with pending memory loads.", + "Counter": "0,1,2,3", + "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", + "CounterMask": "2", + "PublicDescription": "Cycles with pending memory loads. Set Cmask=2 to count cycle.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xA3", + "UMask": "0x4", + "BriefDescription": "Total execution stalls", + "Counter": "0,1,2,3", + "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", + "CounterMask": "4", + "PublicDescription": "This event counts cycles during which no instructions were executed in the execution stage of the pipeline.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xA3", + "UMask": "0x5", + "BriefDescription": "Execution stalls due to L2 cache misses.", + "Counter": "0,1,2,3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", + "CounterMask": "5", + "PublicDescription": "Number of loads missed L2.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xA3", + "UMask": "0x6", + "BriefDescription": "Execution stalls due to memory subsystem.", + "Counter": "0,1,2,3", + "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", + "CounterMask": "6", + "PublicDescription": "This event counts cycles during which no instructions were executed in the execution stage of the pipeline and there were memory instructions pending (waiting for data).", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xA3", + "UMask": "0xc", + "BriefDescription": "Execution stalls due to L1 data cache misses", + "Counter": "2", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", + "CounterMask": "12", + "PublicDescription": "Execution stalls due to L1 data cache miss loads. Set Cmask=0CH.", + "SampleAfterValue": "2000003", + "CounterHTOff": "2" + }, + { + "EventCode": "0xa8", + "UMask": "0x1", + "BriefDescription": "Number of Uops delivered by the LSD.", + "Counter": "0,1,2,3", + "EventName": "LSD.UOPS", + "PublicDescription": "Number of uops delivered by the LSD.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB1", + "UMask": "0x2", + "BriefDescription": "Number of uops executed on the core.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED.CORE", + "Errata": "HSD30, HSM31", + "PublicDescription": "Counts total number of uops to be executed per-core each cycle.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "Invert": "1", + "EventCode": "0xB1", + "UMask": "0x1", + "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED.STALL_CYCLES", + "CounterMask": "1", + "Errata": "HSD144, HSD30, HSM31", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC0", + "UMask": "0x0", + "BriefDescription": "Number of instructions retired. General Counter - architectural event", + "Counter": "0,1,2,3", + "EventName": "INST_RETIRED.ANY_P", + "Errata": "HSD11, HSD140", + "PublicDescription": "Number of instructions at retirement.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC0", + "UMask": "0x2", + "BriefDescription": "FP operations retired. X87 FP operations that have no exceptions: Counts also flows that have several X87 or flows that use X87 uops in the exception handling.", + "Counter": "0,1,2,3", + "EventName": "INST_RETIRED.X87", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC0", + "UMask": "0x1", + "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution", + "PEBS": "2", + "Counter": "1", + "EventName": "INST_RETIRED.PREC_DIST", + "Errata": "HSD140", + "PublicDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution.", + "SampleAfterValue": "2000003", + "CounterHTOff": "1" + }, + { + "EventCode": "0xC1", + "UMask": "0x40", + "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.", + "Counter": "0,1,2,3", + "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", + "PublicDescription": "Number of microcode assists invoked by HW upon uop writeback.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC2", + "UMask": "0x1", + "BriefDescription": "Actually retired uops.", + "Data_LA": "1", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "UOPS_RETIRED.ALL", + "PublicDescription": "Counts the number of micro-ops retired. Use Cmask=1 and invert to count active cycles or stalled cycles.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC2", + "UMask": "0x2", + "BriefDescription": "Retirement slots used.", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "PublicDescription": "This event counts the number of retirement slots used each cycle. There are potentially 4 slots that can be used each cycle - meaning, 4 uops or 4 instructions could retire each cycle.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "Invert": "1", + "EventCode": "0xC2", + "UMask": "0x1", + "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "CounterMask": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "Invert": "1", + "EventCode": "0xC2", + "UMask": "0x1", + "BriefDescription": "Cycles with less than 10 actually retired uops.", + "Counter": "0,1,2,3", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "CounterMask": "10", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "Invert": "1", + "EventCode": "0xC2", + "UMask": "0x1", + "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3", + "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", + "AnyThread": "1", + "CounterMask": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC3", + "UMask": "0x1", + "BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.", + "Counter": "0,1,2,3", + "EventName": "MACHINE_CLEARS.CYCLES", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC3", + "UMask": "0x4", + "BriefDescription": "Self-modifying code (SMC) detected.", + "Counter": "0,1,2,3", + "EventName": "MACHINE_CLEARS.SMC", + "PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear. Machine clears can have a significant performance impact if they are happening frequently.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC3", + "UMask": "0x20", + "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.", + "Counter": "0,1,2,3", + "EventName": "MACHINE_CLEARS.MASKMOV", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC4", + "UMask": "0x1", + "BriefDescription": "Conditional branch instructions retired.", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "BR_INST_RETIRED.CONDITIONAL", + "PublicDescription": "Counts the number of conditional branch instructions retired.", + "SampleAfterValue": "400009", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC4", + "UMask": "0x2", + "BriefDescription": "Direct and indirect near call instructions retired.", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC4", + "UMask": "0x0", + "BriefDescription": "All (macro) branch instructions retired.", + "Counter": "0,1,2,3", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "PublicDescription": "Branch instructions at retirement.", + "SampleAfterValue": "400009", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC4", + "UMask": "0x8", + "BriefDescription": "Return instructions retired.", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "PublicDescription": "Counts the number of near return instructions retired.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC4", + "UMask": "0x10", + "BriefDescription": "Not taken branch instructions retired.", + "Counter": "0,1,2,3", + "EventName": "BR_INST_RETIRED.NOT_TAKEN", + "PublicDescription": "Counts the number of not taken branch instructions retired.", + "SampleAfterValue": "400009", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC4", + "UMask": "0x20", + "BriefDescription": "Taken branch instructions retired.", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "PublicDescription": "Number of near taken branches retired.", + "SampleAfterValue": "400009", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC4", + "UMask": "0x40", + "BriefDescription": "Far branch instructions retired.", + "Counter": "0,1,2,3", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "PublicDescription": "Number of far branches retired.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC4", + "UMask": "0x4", + "BriefDescription": "All (macro) branch instructions retired.", + "PEBS": "2", + "Counter": "0,1,2,3", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", + "SampleAfterValue": "400009", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC5", + "UMask": "0x1", + "BriefDescription": "Mispredicted conditional branch instructions retired.", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "BR_MISP_RETIRED.CONDITIONAL", + "SampleAfterValue": "400009", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC5", + "UMask": "0x0", + "BriefDescription": "All mispredicted macro branch instructions retired.", + "Counter": "0,1,2,3", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PublicDescription": "Mispredicted branch instructions at retirement.", + "SampleAfterValue": "400009", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC5", + "UMask": "0x4", + "BriefDescription": "Mispredicted macro branch instructions retired. ", + "PEBS": "2", + "Counter": "0,1,2,3", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", + "PublicDescription": "This event counts all mispredicted branch instructions retired. This is a precise event.", + "SampleAfterValue": "400009", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xCC", + "UMask": "0x20", + "BriefDescription": "Count cases of saving new LBR", + "Counter": "0,1,2,3", + "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", + "PublicDescription": "Count cases of saving new LBR records by hardware.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "UMask": "0x0", + "BriefDescription": "Thread cycles when thread is not in halt state", + "Counter": "0,1,2,3", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "PublicDescription": "Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "UMask": "0xa0", + "BriefDescription": "Taken speculative and retired mispredicted indirect calls.", + "Counter": "0,1,2,3", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x1", + "BriefDescription": "Cycles per core when uops are exectuted in port 0.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", + "AnyThread": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x2", + "BriefDescription": "Cycles per core when uops are exectuted in port 1.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", + "AnyThread": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x4", + "BriefDescription": "Cycles per core when uops are dispatched to port 2.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE", + "AnyThread": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x8", + "BriefDescription": "Cycles per core when uops are dispatched to port 3.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE", + "AnyThread": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x10", + "BriefDescription": "Cycles per core when uops are exectuted in port 4.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", + "AnyThread": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x20", + "BriefDescription": "Cycles per core when uops are exectuted in port 5.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", + "AnyThread": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x40", + "BriefDescription": "Cycles per core when uops are exectuted in port 6.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", + "AnyThread": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x80", + "BriefDescription": "Cycles per core when uops are dispatched to port 7.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE", + "AnyThread": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC5", + "UMask": "0x20", + "BriefDescription": "number of near branch instructions retired that were mispredicted and taken.", + "PEBS": "1", + "Counter": "0,1,2,3", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "PublicDescription": "Number of near branch instructions retired that were taken but mispredicted.", + "SampleAfterValue": "400009", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB1", + "UMask": "0x1", + "BriefDescription": "Cycles where at least 1 uop was executed per-thread", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", + "CounterMask": "1", + "Errata": "HSD144, HSD30, HSM31", + "PublicDescription": "This events counts the cycles where at least one uop was executed. It is counted per thread.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB1", + "UMask": "0x1", + "BriefDescription": "Cycles where at least 2 uops were executed per-thread", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", + "CounterMask": "2", + "Errata": "HSD144, HSD30, HSM31", + "PublicDescription": "This events counts the cycles where at least two uop were executed. It is counted per thread.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB1", + "UMask": "0x1", + "BriefDescription": "Cycles where at least 3 uops were executed per-thread", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", + "CounterMask": "3", + "Errata": "HSD144, HSD30, HSM31", + "PublicDescription": "This events counts the cycles where at least three uop were executed. It is counted per thread.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB1", + "UMask": "0x1", + "BriefDescription": "Cycles where at least 4 uops were executed per-thread.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", + "CounterMask": "4", + "Errata": "HSD144, HSD30, HSM31", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xe6", + "UMask": "0x1f", + "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", + "Counter": "0,1,2,3", + "EventName": "BACLEARS.ANY", + "PublicDescription": "Number of front end re-steers due to BPU misprediction.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EdgeDetect": "1", + "EventCode": "0xC3", + "UMask": "0x1", + "BriefDescription": "Number of machine clears (nukes) of any type.", + "Counter": "0,1,2,3", + "EventName": "MACHINE_CLEARS.COUNT", + "CounterMask": "1", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA8", + "UMask": "0x1", + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", + "Counter": "0,1,2,3", + "EventName": "LSD.CYCLES_ACTIVE", + "CounterMask": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA8", + "UMask": "0x1", + "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", + "Counter": "0,1,2,3", + "EventName": "LSD.CYCLES_4_UOPS", + "CounterMask": "4", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EdgeDetect": "1", + "Invert": "1", + "EventCode": "0x5E", + "UMask": "0x1", + "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.", + "Counter": "0,1,2,3", + "EventName": "RS_EVENTS.EMPTY_END", + "CounterMask": "1", + "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x1", + "BriefDescription": "Cycles per thread when uops are executed in port 0.", + "Counter": "0,1,2,3", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x2", + "BriefDescription": "Cycles per thread when uops are executed in port 1.", + "Counter": "0,1,2,3", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x4", + "BriefDescription": "Cycles per thread when uops are executed in port 2.", + "Counter": "0,1,2,3", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x8", + "BriefDescription": "Cycles per thread when uops are executed in port 3.", + "Counter": "0,1,2,3", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x10", + "BriefDescription": "Cycles per thread when uops are executed in port 4.", + "Counter": "0,1,2,3", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x20", + "BriefDescription": "Cycles per thread when uops are executed in port 5.", + "Counter": "0,1,2,3", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x40", + "BriefDescription": "Cycles per thread when uops are executed in port 6.", + "Counter": "0,1,2,3", + "EventName": "UOPS_DISPATCHED_PORT.PORT_6", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "UMask": "0x80", + "BriefDescription": "Cycles per thread when uops are executed in port 7.", + "Counter": "0,1,2,3", + "EventName": "UOPS_DISPATCHED_PORT.PORT_7", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x00", + "UMask": "0x2", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "Counter": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", + "AnyThread": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "Fixed counter 2" + }, + { + "EventCode": "0x3C", + "UMask": "0x0", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "Counter": "0,1,2,3", + "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", + "AnyThread": "1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "UMask": "0x1", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)", + "Counter": "0,1,2,3", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", + "AnyThread": "1", + "PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0D", + "UMask": "0x3", + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)", + "Counter": "0,1,2,3", + "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", + "AnyThread": "1", + "CounterMask": "1", + "PublicDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xb1", + "UMask": "0x2", + "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "CounterMask": "1", + "Errata": "HSD30, HSM31", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xb1", + "UMask": "0x2", + "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "CounterMask": "2", + "Errata": "HSD30, HSM31", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xb1", + "UMask": "0x2", + "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "CounterMask": "3", + "Errata": "HSD30, HSM31", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xb1", + "UMask": "0x2", + "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "CounterMask": "4", + "Errata": "HSD30, HSM31", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "Invert": "1", + "EventCode": "0xb1", + "UMask": "0x2", + "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.", + "Counter": "0,1,2,3", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", + "Errata": "HSD30, HSM31", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "UMask": "0x1", + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", + "Counter": "0,1,2,3", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "UMask": "0x1", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)", + "Counter": "0,1,2,3", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", + "AnyThread": "1", + "PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "UMask": "0x2", + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", + "Counter": "0,1,2,3", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswellx/virtual-memory.json b/tools/perf/pmu-events/arch/x86/haswellx/virtual-memory.json new file mode 100644 index 000000000000..9c00f8ef6a07 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/haswellx/virtual-memory.json @@ -0,0 +1,484 @@ +[ + { + "EventCode": "0x08", + "UMask": "0x1", + "BriefDescription": "Load misses in all DTLB levels that cause page walks", + "Counter": "0,1,2,3", + "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", + "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x08", + "UMask": "0x2", + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).", + "Counter": "0,1,2,3", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "Completed page walks due to demand load misses that caused 4K page walks in any TLB levels.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x08", + "UMask": "0x4", + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).", + "Counter": "0,1,2,3", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x08", + "UMask": "0x8", + "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)", + "Counter": "0,1,2,3", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x08", + "UMask": "0x10", + "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", + "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", + "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x08", + "UMask": "0x20", + "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)", + "Counter": "0,1,2,3", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", + "PublicDescription": "This event counts load operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x08", + "UMask": "0x40", + "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)", + "Counter": "0,1,2,3", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", + "PublicDescription": "This event counts load operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x08", + "UMask": "0x80", + "BriefDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed", + "Counter": "0,1,2,3", + "EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS", + "PublicDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "UMask": "0x1", + "BriefDescription": "Store misses in all DTLB levels that cause page walks", + "Counter": "0,1,2,3", + "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", + "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "UMask": "0x2", + "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)", + "Counter": "0,1,2,3", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 4K page structure.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "UMask": "0x4", + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)", + "Counter": "0,1,2,3", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 2M/4M page structure.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "UMask": "0x8", + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks. (1G)", + "Counter": "0,1,2,3", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "UMask": "0x10", + "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", + "EventName": "DTLB_STORE_MISSES.WALK_DURATION", + "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB store misses.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "UMask": "0x20", + "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K)", + "Counter": "0,1,2,3", + "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", + "PublicDescription": "This event counts store operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "UMask": "0x40", + "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M)", + "Counter": "0,1,2,3", + "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", + "PublicDescription": "This event counts store operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "UMask": "0x80", + "BriefDescription": "DTLB store misses with low part of linear-to-physical address translation missed", + "Counter": "0,1,2,3", + "EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS", + "PublicDescription": "DTLB store misses with low part of linear-to-physical address translation missed.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x4f", + "UMask": "0x10", + "BriefDescription": "Cycle count for an Extended Page table walk.", + "Counter": "0,1,2,3", + "EventName": "EPT.WALK_CYCLES", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "UMask": "0x1", + "BriefDescription": "Misses at all ITLB levels that cause page walks", + "Counter": "0,1,2,3", + "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", + "PublicDescription": "Misses in ITLB that causes a page walk of any page size.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "UMask": "0x2", + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", + "Counter": "0,1,2,3", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "Completed page walks due to misses in ITLB 4K page entries.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "UMask": "0x4", + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", + "Counter": "0,1,2,3", + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "Completed page walks due to misses in ITLB 2M/4M page entries.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "UMask": "0x8", + "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)", + "Counter": "0,1,2,3", + "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "UMask": "0x10", + "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", + "EventName": "ITLB_MISSES.WALK_DURATION", + "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by ITLB misses.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "UMask": "0x20", + "BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K)", + "Counter": "0,1,2,3", + "EventName": "ITLB_MISSES.STLB_HIT_4K", + "PublicDescription": "ITLB misses that hit STLB (4K).", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "UMask": "0x40", + "BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M)", + "Counter": "0,1,2,3", + "EventName": "ITLB_MISSES.STLB_HIT_2M", + "PublicDescription": "ITLB misses that hit STLB (2M).", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xae", + "UMask": "0x1", + "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", + "Counter": "0,1,2,3", + "EventName": "ITLB.ITLB_FLUSH", + "PublicDescription": "Counts the number of ITLB flushes, includes 4k/2M/4M pages.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xBC", + "UMask": "0x11", + "BriefDescription": "Number of DTLB page walker hits in the L1+FB", + "Counter": "0,1,2,3", + "EventName": "PAGE_WALKER_LOADS.DTLB_L1", + "PublicDescription": "Number of DTLB page walker loads that hit in the L1+FB.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBC", + "UMask": "0x21", + "BriefDescription": "Number of ITLB page walker hits in the L1+FB", + "Counter": "0,1,2,3", + "EventName": "PAGE_WALKER_LOADS.ITLB_L1", + "PublicDescription": "Number of ITLB page walker loads that hit in the L1+FB.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBC", + "UMask": "0x41", + "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB.", + "Counter": "0,1,2,3", + "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBC", + "UMask": "0x81", + "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB.", + "Counter": "0,1,2,3", + "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L1", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBC", + "UMask": "0x12", + "BriefDescription": "Number of DTLB page walker hits in the L2", + "Counter": "0,1,2,3", + "EventName": "PAGE_WALKER_LOADS.DTLB_L2", + "PublicDescription": "Number of DTLB page walker loads that hit in the L2.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBC", + "UMask": "0x22", + "BriefDescription": "Number of ITLB page walker hits in the L2", + "Counter": "0,1,2,3", + "EventName": "PAGE_WALKER_LOADS.ITLB_L2", + "PublicDescription": "Number of ITLB page walker loads that hit in the L2.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBC", + "UMask": "0x42", + "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L2.", + "Counter": "0,1,2,3", + "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L2", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBC", + "UMask": "0x82", + "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.", + "Counter": "0,1,2,3", + "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L2", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBC", + "UMask": "0x14", + "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP", + "Counter": "0,1,2,3", + "EventName": "PAGE_WALKER_LOADS.DTLB_L3", + "Errata": "HSD25", + "PublicDescription": "Number of DTLB page walker loads that hit in the L3.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBC", + "UMask": "0x24", + "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP", + "Counter": "0,1,2,3", + "EventName": "PAGE_WALKER_LOADS.ITLB_L3", + "Errata": "HSD25", + "PublicDescription": "Number of ITLB page walker loads that hit in the L3.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBC", + "UMask": "0x44", + "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L3.", + "Counter": "0,1,2,3", + "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L3", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBC", + "UMask": "0x84", + "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.", + "Counter": "0,1,2,3", + "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L3", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBC", + "UMask": "0x18", + "BriefDescription": "Number of DTLB page walker hits in Memory", + "Counter": "0,1,2,3", + "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY", + "Errata": "HSD25", + "PublicDescription": "Number of DTLB page walker loads from memory.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBC", + "UMask": "0x28", + "BriefDescription": "Number of ITLB page walker hits in Memory", + "Counter": "0,1,2,3", + "EventName": "PAGE_WALKER_LOADS.ITLB_MEMORY", + "Errata": "HSD25", + "PublicDescription": "Number of ITLB page walker loads from memory.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBC", + "UMask": "0x48", + "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in memory.", + "Counter": "0,1,2,3", + "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_MEMORY", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBC", + "UMask": "0x88", + "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in memory.", + "Counter": "0,1,2,3", + "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_MEMORY", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xBD", + "UMask": "0x1", + "BriefDescription": "DTLB flush attempts of the thread-specific entries", + "Counter": "0,1,2,3", + "EventName": "TLB_FLUSH.DTLB_THREAD", + "PublicDescription": "DTLB flush attempts of the thread-specific entries.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xBD", + "UMask": "0x20", + "BriefDescription": "STLB flush attempts", + "Counter": "0,1,2,3", + "EventName": "TLB_FLUSH.STLB_ANY", + "PublicDescription": "Count number of STLB flush attempts.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x08", + "UMask": "0xe", + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", + "Counter": "0,1,2,3", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "PublicDescription": "Completed page walks in any TLB of any page size due to demand load misses.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x08", + "UMask": "0x60", + "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks", + "Counter": "0,1,2,3", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "PublicDescription": "Number of cache load STLB hits. No page walk.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "UMask": "0xe", + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks", + "Counter": "0,1,2,3", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "PublicDescription": "Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G).", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "UMask": "0x60", + "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks", + "Counter": "0,1,2,3", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "UMask": "0xe", + "BriefDescription": "Misses in all ITLB levels that cause completed page walks", + "Counter": "0,1,2,3", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "PublicDescription": "Completed page walks in ITLB of any page size.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "UMask": "0x60", + "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks", + "Counter": "0,1,2,3", + "EventName": "ITLB_MISSES.STLB_HIT", + "PublicDescription": "ITLB misses that hit STLB. No page walk.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/cache.json b/tools/perf/pmu-events/arch/x86/ivybridge/cache.json new file mode 100644 index 000000000000..f1ee6d4853c5 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/ivybridge/cache.json @@ -0,0 +1,1123 @@ +[ + { + "PublicDescription": "Demand Data Read requests that hit L2 cache.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "SampleAfterValue": "200003", + "BriefDescription": "Demand Data Read requests that hit L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "RFO requests that hit L2 cache.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_RQSTS.RFO_HIT", + "SampleAfterValue": "200003", + "BriefDescription": "RFO requests that hit L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_RQSTS.RFO_MISS", + "SampleAfterValue": "200003", + "BriefDescription": "RFO requests that miss L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of instruction fetches that hit the L2 cache.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "L2_RQSTS.CODE_RD_HIT", + "SampleAfterValue": "200003", + "BriefDescription": "L2 cache hits when fetching instructions, code reads.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of instruction fetches that missed the L2 cache.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "L2_RQSTS.CODE_RD_MISS", + "SampleAfterValue": "200003", + "BriefDescription": "L2 cache misses when fetching instructions", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "L2_RQSTS.PF_HIT", + "SampleAfterValue": "200003", + "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "L2_RQSTS.PF_MISS", + "SampleAfterValue": "200003", + "BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x3", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "SampleAfterValue": "200003", + "BriefDescription": "Demand Data Read requests", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts all L2 store RFO requests.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xc", + "EventName": "L2_RQSTS.ALL_RFO", + "SampleAfterValue": "200003", + "BriefDescription": "RFO requests to L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts all L2 code requests.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "SampleAfterValue": "200003", + "BriefDescription": "L2 code requests", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts all L2 HW prefetcher requests.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xc0", + "EventName": "L2_RQSTS.ALL_PF", + "SampleAfterValue": "200003", + "BriefDescription": "Requests from L2 hardware prefetchers", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "RFOs that miss cache lines.", + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_STORE_LOCK_RQSTS.MISS", + "SampleAfterValue": "200003", + "BriefDescription": "RFOs that miss cache lines", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "RFOs that hit cache lines in M state.", + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_STORE_LOCK_RQSTS.HIT_M", + "SampleAfterValue": "200003", + "BriefDescription": "RFOs that hit cache lines in M state", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "RFOs that access cache lines in any state.", + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "L2_STORE_LOCK_RQSTS.ALL", + "SampleAfterValue": "200003", + "BriefDescription": "RFOs that access cache lines in any state", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Not rejected writebacks that missed LLC.", + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_L1D_WB_RQSTS.MISS", + "SampleAfterValue": "200003", + "BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.", + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_L1D_WB_RQSTS.HIT_E", + "SampleAfterValue": "200003", + "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.", + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_L1D_WB_RQSTS.HIT_M", + "SampleAfterValue": "200003", + "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "L2_L1D_WB_RQSTS.ALL", + "SampleAfterValue": "200003", + "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts each cache miss condition for references to the last level cache.", + "EventCode": "0x2E", + "Counter": "0,1,2,3", + "UMask": "0x41", + "EventName": "LONGEST_LAT_CACHE.MISS", + "SampleAfterValue": "100003", + "BriefDescription": "Core-originated cacheable demand requests missed LLC", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.", + "EventCode": "0x2E", + "Counter": "0,1,2,3", + "UMask": "0x4f", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "SampleAfterValue": "100003", + "BriefDescription": "Core-originated cacheable demand requests that refer to LLC", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.", + "EventCode": "0x48", + "Counter": "2", + "UMask": "0x1", + "EventName": "L1D_PEND_MISS.PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "L1D miss oustandings duration in cycles", + "CounterHTOff": "2" + }, + { + "EventCode": "0x48", + "Counter": "2", + "UMask": "0x1", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with L1D load Misses outstanding.", + "CounterMask": "1", + "CounterHTOff": "2" + }, + { + "PublicDescription": "Counts the number of lines brought into the L1 data cache.", + "EventCode": "0x51", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L1D.REPLACEMENT", + "SampleAfterValue": "2000003", + "BriefDescription": "L1D data line replacements", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles in which the L1D is locked.", + "EventCode": "0x63", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when L1D is locked", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Demand data read requests sent to uncore.", + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "SampleAfterValue": "100003", + "BriefDescription": "Demand Data Read requests sent to uncore", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Demand code read requests sent to uncore.", + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "SampleAfterValue": "100003", + "BriefDescription": "Cacheable and noncachaeble code read requests", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.", + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "SampleAfterValue": "100003", + "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Data read requests sent to uncore (demand and prefetch).", + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", + "SampleAfterValue": "100003", + "BriefDescription": "Demand and prefetch data reads", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cases when offcore requests buffer cannot take more entries for core.", + "EventCode": "0xB2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", + "SampleAfterValue": "2000003", + "BriefDescription": "Cases when offcore requests buffer cannot take more entries for core", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x11", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load uops that miss the STLB.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x12", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", + "SampleAfterValue": "100003", + "BriefDescription": "Retired store uops that miss the STLB.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x21", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "SampleAfterValue": "100007", + "BriefDescription": "Retired load uops with locked access.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x41", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load uops that split across a cacheline boundary.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x42", + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "SampleAfterValue": "100003", + "BriefDescription": "Retired store uops that split across a cacheline boundary.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x81", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "SampleAfterValue": "2000003", + "BriefDescription": "All retired load uops.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x82", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "SampleAfterValue": "2000003", + "BriefDescription": "All retired store uops.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "PublicDescription": "Retired load uops with L1 cache hits as data sources.", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "SampleAfterValue": "2000003", + "BriefDescription": "Retired load uops with L1 cache hits as data sources. ", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "PublicDescription": "Retired load uops with L2 cache hits as data sources.", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load uops with L2 cache hits as data sources. ", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "PublicDescription": "Retired load uops whose data source was LLC hit with no snoop required.", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT", + "SampleAfterValue": "50021", + "BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required. ", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "PublicDescription": "Retired load uops whose data source followed an L1 miss.", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load uops which data sources following L1 data-cache miss", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "PublicDescription": "Retired load uops that missed L2, excluding unknown sources.", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "SampleAfterValue": "50021", + "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "PublicDescription": "Retired load uops whose data source is LLC miss.", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS", + "SampleAfterValue": "100007", + "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "PublicDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. ", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "PublicDescription": "Retired load uops whose data source was an on-package core cache LLC hit and cross-core snoop missed.", + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", + "SampleAfterValue": "20011", + "BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. ", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "PublicDescription": "Retired load uops whose data source was an on-package LLC hit and cross-core snoop hits.", + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", + "SampleAfterValue": "20011", + "BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. ", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "PublicDescription": "Retired load uops whose data source was an on-package core cache with HitM responses.", + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", + "SampleAfterValue": "20011", + "BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC. ", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "PublicDescription": "Retired load uops whose data source was LLC hit with no snoop required.", + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required. ", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Retired load uop whose Data Source was: local DRAM either Snoop not needed or Snoop Miss (RspI)", + "EventCode": "0xD3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", + "SampleAfterValue": "100007", + "BriefDescription": "Retired load uops which data sources missed LLC but serviced from local dram.", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Demand Data Read requests that access L2 cache.", + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_TRANS.DEMAND_DATA_RD", + "SampleAfterValue": "200003", + "BriefDescription": "Demand Data Read requests that access L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "RFO requests that access L2 cache.", + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_TRANS.RFO", + "SampleAfterValue": "200003", + "BriefDescription": "RFO requests that access L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "L2 cache accesses when fetching instructions.", + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_TRANS.CODE_RD", + "SampleAfterValue": "200003", + "BriefDescription": "L2 cache accesses when fetching instructions", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Any MLC or LLC HW prefetch accessing L2, including rejects.", + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_TRANS.ALL_PF", + "SampleAfterValue": "200003", + "BriefDescription": "L2 or LLC HW prefetches that access L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "L1D writebacks that access L2 cache.", + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "L2_TRANS.L1D_WB", + "SampleAfterValue": "200003", + "BriefDescription": "L1D writebacks that access L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "L2 fill requests that access L2 cache.", + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "L2_TRANS.L2_FILL", + "SampleAfterValue": "200003", + "BriefDescription": "L2 fill requests that access L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "L2 writebacks that access L2 cache.", + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "L2_TRANS.L2_WB", + "SampleAfterValue": "200003", + "BriefDescription": "L2 writebacks that access L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Transactions accessing L2 pipe.", + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "L2_TRANS.ALL_REQUESTS", + "SampleAfterValue": "200003", + "BriefDescription": "Transactions accessing L2 pipe", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "L2 cache lines in I state filling L2.", + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_LINES_IN.I", + "SampleAfterValue": "100003", + "BriefDescription": "L2 cache lines in I state filling L2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "L2 cache lines in S state filling L2.", + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_LINES_IN.S", + "SampleAfterValue": "100003", + "BriefDescription": "L2 cache lines in S state filling L2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "L2 cache lines in E state filling L2.", + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_LINES_IN.E", + "SampleAfterValue": "100003", + "BriefDescription": "L2 cache lines in E state filling L2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "L2 cache lines filling L2.", + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x7", + "EventName": "L2_LINES_IN.ALL", + "SampleAfterValue": "100003", + "BriefDescription": "L2 cache lines filling L2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Clean L2 cache lines evicted by demand.", + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_LINES_OUT.DEMAND_CLEAN", + "SampleAfterValue": "100003", + "BriefDescription": "Clean L2 cache lines evicted by demand", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Dirty L2 cache lines evicted by demand.", + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_LINES_OUT.DEMAND_DIRTY", + "SampleAfterValue": "100003", + "BriefDescription": "Dirty L2 cache lines evicted by demand", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Clean L2 cache lines evicted by the MLC prefetcher.", + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_LINES_OUT.PF_CLEAN", + "SampleAfterValue": "100003", + "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Dirty L2 cache lines evicted by the MLC prefetcher.", + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_LINES_OUT.PF_DIRTY", + "SampleAfterValue": "100003", + "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Dirty L2 cache lines filling the L2.", + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0xa", + "EventName": "L2_LINES_OUT.DIRTY_ALL", + "SampleAfterValue": "100003", + "BriefDescription": "Dirty L2 cache lines filling the L2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF4", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "SQ_MISC.SPLIT_LOCK", + "SampleAfterValue": "100003", + "BriefDescription": "Split locks in SQ", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Retired load uops whose data source was local memory (cross-socket snoop not needed or missed).", + "EventCode": "0xD3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", + "SampleAfterValue": "100007", + "BriefDescription": "Retired load uops which data sources missed LLC but serviced from local dram.", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue", + "CounterMask": "6", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", + "EventCode": "0x48", + "Counter": "2", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core", + "CounterMask": "1", + "CounterHTOff": "2" + }, + { + "PublicDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", + "EventCode": "0x48", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L1D_PEND_MISS.FB_FULL", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0244", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch code reads that hit in the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003c0244", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0091", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch data reads that hit in the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4003c0091", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0091", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003c0091", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0122", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch RFOs that hit in the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003c0122", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10008", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all writebacks from the core to the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand code reads that hit in the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003c0004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand data reads that hit in the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4003c0001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003c0001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0002", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand data writes (RFOs) that hit in the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0002", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003c0002", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x18000", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10400", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address ", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10800", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts non-temporal stores", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00010001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand data reads ", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00010002", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand rfo's ", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00010004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand code reads", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x000105B3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch data reads", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00010122", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch prefetch RFOs ", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x000107F7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all data/code/rfo references (demand & prefetch) ", + "CounterHTOff": "0,1,2,3" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/floating-point.json b/tools/perf/pmu-events/arch/x86/ivybridge/floating-point.json new file mode 100644 index 000000000000..950b62c0908e --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/ivybridge/floating-point.json @@ -0,0 +1,151 @@ +[ + { + "PublicDescription": "Counts number of X87 uops executed.", + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "FP_COMP_OPS_EXE.X87", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.", + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.", + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.", + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts number of SSE* or AVX-128 double precision FP scalar uops executed.", + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts 256-bit packed single-precision floating-point instructions.", + "EventCode": "0x11", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "SIMD_FP_256.PACKED_SINGLE", + "SampleAfterValue": "2000003", + "BriefDescription": "number of GSSE-256 Computational FP single precision uops issued this cycle", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts 256-bit packed double-precision floating-point instructions.", + "EventCode": "0x11", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "SIMD_FP_256.PACKED_DOUBLE", + "SampleAfterValue": "2000003", + "BriefDescription": "number of AVX-256 Computational FP double precision uops issued this cycle", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of assists associated with 256-bit AVX store operations.", + "EventCode": "0xC1", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "OTHER_ASSISTS.AVX_STORE", + "SampleAfterValue": "100003", + "BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC1", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "OTHER_ASSISTS.AVX_TO_SSE", + "SampleAfterValue": "100003", + "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC1", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "OTHER_ASSISTS.SSE_TO_AVX", + "SampleAfterValue": "100003", + "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of X87 FP assists due to output values.", + "EventCode": "0xCA", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "FP_ASSIST.X87_OUTPUT", + "SampleAfterValue": "100003", + "BriefDescription": "Number of X87 assists due to output value.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of X87 FP assists due to input values.", + "EventCode": "0xCA", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "FP_ASSIST.X87_INPUT", + "SampleAfterValue": "100003", + "BriefDescription": "Number of X87 assists due to input value.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of SIMD FP assists due to output values.", + "EventCode": "0xCA", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "FP_ASSIST.SIMD_OUTPUT", + "SampleAfterValue": "100003", + "BriefDescription": "Number of SIMD FP assists due to Output values", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of SIMD FP assists due to input values.", + "EventCode": "0xCA", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "FP_ASSIST.SIMD_INPUT", + "SampleAfterValue": "100003", + "BriefDescription": "Number of SIMD FP assists due to input values", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles with any input/output SSE* or FP assists.", + "EventCode": "0xCA", + "Counter": "0,1,2,3", + "UMask": "0x1e", + "EventName": "FP_ASSIST.ANY", + "SampleAfterValue": "100003", + "BriefDescription": "Cycles with any input/output SSE or FP assist", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/frontend.json b/tools/perf/pmu-events/arch/x86/ivybridge/frontend.json new file mode 100644 index 000000000000..de72b84b3536 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/ivybridge/frontend.json @@ -0,0 +1,305 @@ +[ + { + "PublicDescription": "Counts cycles the IDQ is empty.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "IDQ.EMPTY", + "SampleAfterValue": "2000003", + "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "IDQ.MITE_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "IDQ.DSB_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "IDQ.MS_DSB_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "IDQ.MS_MITE_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "IDQ.MS_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "IDQ.MS_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "IDQ.MITE_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "IDQ.DSB_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "IDQ.MS_DSB_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EdgeDetect": "1", + "EventName": "IDQ.MS_DSB_OCCUR", + "SampleAfterValue": "2000003", + "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x18", + "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x18", + "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts cycles MITE is delivered four uops. Set Cmask = 4.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x24", + "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles MITE is delivering 4 Uops", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts cycles MITE is delivered at least one uops. Set Cmask = 1.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x24", + "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles MITE is delivering any Uop", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of uops delivered to IDQ from any path.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x3c", + "EventName": "IDQ.MITE_ALL_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.", + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ICACHE.HIT", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses.", + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "ICACHE.MISSES", + "SampleAfterValue": "200003", + "BriefDescription": "Instruction cache, streaming buffer and victim cache misses", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss.", + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "ICACHE.IFETCH_STALL", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Count issue pipeline slots where no uop was delivered from the front end to the back end when there is no back-end stall.", + "EventCode": "0x9C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled ", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", + "CounterMask": "3", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", + "CounterMask": "2", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with less than 3 uops delivered by the front end.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Number of DSB to MITE switches.", + "EventCode": "0xAB", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "DSB2MITE_SWITCHES.COUNT", + "SampleAfterValue": "2000003", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles DSB to MITE switches caused delay.", + "EventCode": "0xAB", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "DSB Fill encountered > 3 DSB lines.", + "EventCode": "0xAC", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "DSB_FILL.EXCEED_DSB_LINES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EdgeDetect": "1", + "EventName": "IDQ.MS_SWITCHES", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/memory.json b/tools/perf/pmu-events/arch/x86/ivybridge/memory.json new file mode 100644 index 000000000000..e1c6a1d4a4d5 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/ivybridge/memory.json @@ -0,0 +1,236 @@ +[ + { + "PublicDescription": "Speculative cache-line split load uops dispatched to L1D.", + "EventCode": "0x05", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MISALIGN_MEM_REF.LOADS", + "SampleAfterValue": "2000003", + "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Speculative cache-line split Store-address uops dispatched to L1D.", + "EventCode": "0x05", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MISALIGN_MEM_REF.STORES", + "SampleAfterValue": "2000003", + "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xBE", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "PAGE_WALKS.LLC_MISS", + "SampleAfterValue": "100003", + "BriefDescription": "Number of any page walk that had a miss in LLC.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "SampleAfterValue": "100003", + "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "2", + "EventCode": "0xCD", + "Counter": "3", + "UMask": "0x2", + "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only.", + "PRECISE_STORE": "1", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 4.", + "EventCode": "0xCD", + "MSRValue": "0x4", + "Counter": "3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "SampleAfterValue": "100003", + "BriefDescription": "Loads with latency value being above 4", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 8.", + "EventCode": "0xCD", + "MSRValue": "0x8", + "Counter": "3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "MSRIndex": "0x3F6", + "SampleAfterValue": "50021", + "BriefDescription": "Loads with latency value being above 8", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 16.", + "EventCode": "0xCD", + "MSRValue": "0x10", + "Counter": "3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "MSRIndex": "0x3F6", + "SampleAfterValue": "20011", + "BriefDescription": "Loads with latency value being above 16", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 32.", + "EventCode": "0xCD", + "MSRValue": "0x20", + "Counter": "3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "MSRIndex": "0x3F6", + "SampleAfterValue": "100007", + "BriefDescription": "Loads with latency value being above 32", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 64.", + "EventCode": "0xCD", + "MSRValue": "0x40", + "Counter": "3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "MSRIndex": "0x3F6", + "SampleAfterValue": "2003", + "BriefDescription": "Loads with latency value being above 64", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 128.", + "EventCode": "0xCD", + "MSRValue": "0x80", + "Counter": "3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "MSRIndex": "0x3F6", + "SampleAfterValue": "1009", + "BriefDescription": "Loads with latency value being above 128", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 256.", + "EventCode": "0xCD", + "MSRValue": "0x100", + "Counter": "3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "MSRIndex": "0x3F6", + "SampleAfterValue": "503", + "BriefDescription": "Loads with latency value being above 256", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 512.", + "EventCode": "0xCD", + "MSRValue": "0x200", + "Counter": "3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "MSRIndex": "0x3F6", + "SampleAfterValue": "101", + "BriefDescription": "Loads with latency value being above 512", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x300400244", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC and the data returned from dram", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x300400091", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch data reads that miss the LLC and the data returned from dram", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3004003f7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from dram", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x300400004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand code reads that miss the LLC and the data returned from dram", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x300400001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from dram", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x6004001b3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts LLC replacements", + "CounterHTOff": "0,1,2,3" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/other.json b/tools/perf/pmu-events/arch/x86/ivybridge/other.json new file mode 100644 index 000000000000..9c2dd0511a32 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/ivybridge/other.json @@ -0,0 +1,44 @@ +[ + { + "PublicDescription": "Unhalted core cycles when the thread is in ring 0.", + "EventCode": "0x5C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CPL_CYCLES.RING0", + "SampleAfterValue": "2000003", + "BriefDescription": "Unhalted core cycles when the thread is in ring 0", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.", + "EventCode": "0x5C", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "CPL_CYCLES.RING123", + "SampleAfterValue": "2000003", + "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of intervals between processor halts while thread is in ring 0.", + "EventCode": "0x5C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EdgeDetect": "1", + "EventName": "CPL_CYCLES.RING0_TRANS", + "SampleAfterValue": "100007", + "BriefDescription": "Number of intervals between processor halts while thread is in ring 0", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.", + "EventCode": "0x63", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/pipeline.json b/tools/perf/pmu-events/arch/x86/ivybridge/pipeline.json new file mode 100644 index 000000000000..2145c28193f7 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/ivybridge/pipeline.json @@ -0,0 +1,1307 @@ +[ + { + "EventCode": "0x00", + "Counter": "Fixed counter 1", + "UMask": "0x1", + "EventName": "INST_RETIRED.ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Instructions retired from execution.", + "CounterHTOff": "Fixed counter 1" + }, + { + "EventCode": "0x00", + "Counter": "Fixed counter 2", + "UMask": "0x2", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "SampleAfterValue": "2000003", + "BriefDescription": "Core cycles when the thread is not in halt state.", + "CounterHTOff": "Fixed counter 2" + }, + { + "EventCode": "0x00", + "Counter": "Fixed counter 3", + "UMask": "0x3", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "SampleAfterValue": "2000003", + "BriefDescription": "Reference cycles when the core is not in halt state.", + "CounterHTOff": "Fixed counter 3" + }, + { + "PublicDescription": "Loads blocked by overlapping with store buffer that cannot be forwarded.", + "EventCode": "0x03", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "SampleAfterValue": "100003", + "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "EventCode": "0x03", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "LD_BLOCKS.NO_SR", + "SampleAfterValue": "100003", + "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "False dependencies in MOB due to partial compare on address.", + "EventCode": "0x07", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "SampleAfterValue": "100003", + "BriefDescription": "False dependencies in MOB due to partial compare on address", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0D", + "Counter": "0,1,2,3", + "UMask": "0x3", + "EventName": "INT_MISC.RECOVERY_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.)", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0D", + "Counter": "0,1,2,3", + "UMask": "0x3", + "EdgeDetect": "1", + "EventName": "INT_MISC.RECOVERY_STALLS_COUNT", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.)", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Increments each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core.", + "EventCode": "0x0E", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_ISSUED.ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.", + "EventCode": "0x0E", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.", + "EventCode": "0x0E", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Number of flags-merge uops allocated. Such uops adds delay.", + "EventCode": "0x0E", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "UOPS_ISSUED.FLAGS_MERGE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of flags-merge uops being allocated.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", + "EventCode": "0x0E", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "UOPS_ISSUED.SLOW_LEA", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of multiply packed/scalar single precision uops allocated.", + "EventCode": "0x0E", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "UOPS_ISSUED.SINGLE_MUL", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=1' to count the number of divides.", + "EventCode": "0x14", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ARITH.FPU_DIV_ACTIVE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when divider is busy executing divide operations", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Divide operations executed.", + "EventCode": "0x14", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EdgeDetect": "1", + "EventName": "ARITH.FPU_DIV", + "SampleAfterValue": "100003", + "BriefDescription": "Divide operations executed", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.", + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "SampleAfterValue": "2000003", + "BriefDescription": "Thread cycles when thread is not in halt state", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Increments at the frequency of XCLK (100 MHz) when not halted.", + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", + "SampleAfterValue": "2000003", + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "2000003", + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other is halted.", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.", + "EventCode": "0x4C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LOAD_HIT_PRE.SW_PF", + "SampleAfterValue": "100003", + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.", + "EventCode": "0x4C", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "LOAD_HIT_PRE.HW_PF", + "SampleAfterValue": "100003", + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x58", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", + "SampleAfterValue": "1000003", + "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x58", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", + "SampleAfterValue": "1000003", + "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x58", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", + "SampleAfterValue": "1000003", + "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x58", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", + "SampleAfterValue": "1000003", + "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles the RS is empty for the thread.", + "EventCode": "0x5E", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "RS_EVENTS.EMPTY_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x87", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ILD_STALL.LCP", + "SampleAfterValue": "2000003", + "BriefDescription": "Stalls caused by changing prefix length of the instruction.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Stall cycles due to IQ is full.", + "EventCode": "0x87", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "ILD_STALL.IQ_FULL", + "SampleAfterValue": "2000003", + "BriefDescription": "Stall cycles because IQ is full", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Not taken macro-conditional branches.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x41", + "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Not taken macro-conditional branches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Taken speculative and retired macro-conditional branches.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x81", + "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired macro-conditional branches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x82", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Taken speculative and retired indirect branches excluding calls and returns.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x84", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Taken speculative and retired indirect branches with return mnemonic.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Taken speculative and retired direct near calls.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x90", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired direct near calls", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Taken speculative and retired indirect calls.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xa0", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired indirect calls", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Speculative and retired macro-conditional branches.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xc1", + "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired macro-conditional branches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xc2", + "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Speculative and retired indirect branches excluding calls and returns.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xc4", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired indirect branches excluding calls and returns", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xc8", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired indirect return branches.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Speculative and retired direct near calls.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xd0", + "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired direct near calls", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts all near executed branches (not necessarily retired).", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xff", + "EventName": "BR_INST_EXEC.ALL_BRANCHES", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired branches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Not taken speculative and retired mispredicted macro conditional branches.", + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x41", + "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Taken speculative and retired mispredicted macro conditional branches.", + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x81", + "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns.", + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x84", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic.", + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x88", + "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Taken speculative and retired mispredicted indirect calls.", + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0xa0", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired mispredicted indirect calls", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Speculative and retired mispredicted macro conditional branches.", + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0xc1", + "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired mispredicted macro conditional branches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Mispredicted indirect branches excluding calls and returns.", + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0xc4", + "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "BriefDescription": "Mispredicted indirect branches excluding calls and returns", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts all near executed branches (not necessarily retired).", + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0xff", + "EventName": "BR_MISP_EXEC.ALL_BRANCHES", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired mispredicted macro conditional branches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles which a Uop is dispatched on port 0.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are dispatched to port 0", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles which a Uop is dispatched on port 1.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are dispatched to port 1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles which a Uop is dispatched on port 4.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are dispatched to port 4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles which a Uop is dispatched on port 5.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are dispatched to port 5", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles per core when uops are dispatched to port 0.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when uops are dispatched to port 0", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles per core when uops are dispatched to port 1.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "AnyThread": "1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when uops are dispatched to port 1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles per core when uops are dispatched to port 4.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x40", + "AnyThread": "1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when uops are dispatched to port 4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles per core when uops are dispatched to port 5.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x80", + "AnyThread": "1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when uops are dispatched to port 5", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles which a Uop is dispatched on port 2.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0xc", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles which a Uop is dispatched on port 3.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0xc", + "AnyThread": "1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops dispatched to port 2, loads and stores per core (speculative and retired).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles per core when load or STA uops are dispatched to port 3.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x30", + "AnyThread": "1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles Allocation is stalled due to Resource Related reason.", + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "RESOURCE_STALLS.ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Resource-related stall cycles", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "RESOURCE_STALLS.RS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles stalled due to no eligible RS entry available.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles stalled due to no store buffers available (not including draining form sync).", + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "RESOURCE_STALLS.SB", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "RESOURCE_STALLS.ROB", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles stalled due to re-order buffer full.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles with pending L2 miss loads. Set AnyThread to count per core.", + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with pending L2 cache miss loads.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles with pending L1 cache miss loads. Set AnyThread to count per core.", + "EventCode": "0xA3", + "Counter": "2", + "UMask": "0x8", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with pending L1 cache miss loads.", + "CounterMask": "8", + "CounterHTOff": "2" + }, + { + "PublicDescription": "Cycles with pending memory loads. Set AnyThread to count per core.", + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with pending memory loads.", + "CounterMask": "2", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Total execution stalls.", + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", + "SampleAfterValue": "2000003", + "BriefDescription": "Total execution stalls", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Number of loads missed L2.", + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x5", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "Execution stalls due to L2 cache misses.", + "CounterMask": "5", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x6", + "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "Execution stalls due to memory subsystem.", + "CounterMask": "6", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Execution stalls due to L1 data cache miss loads. Set Cmask=0CH.", + "EventCode": "0xA3", + "Counter": "2", + "UMask": "0xc", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "Execution stalls due to L1 data cache misses", + "CounterMask": "12", + "CounterHTOff": "2" + }, + { + "EventCode": "0xA8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LSD.UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of Uops delivered by the LSD.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", + "EventCode": "0xA8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LSD.CYCLES_ACTIVE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts total number of uops to be executed per-thread each cycle. Set Cmask = 1, INV =1 to count stall cycles.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_EXECUTED.THREAD", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts total number of uops to be executed per-core each cycle.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of uops executed on the core.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_EXECUTED.STALL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Number of instructions at retirement.", + "EventCode": "0xC0", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "INST_RETIRED.ANY_P", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of instructions retired. General Counter - architectural event", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "2", + "PublicDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution.", + "EventCode": "0xC0", + "Counter": "1", + "UMask": "0x1", + "EventName": "INST_RETIRED.PREC_DIST", + "SampleAfterValue": "2000003", + "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution", + "CounterHTOff": "1" + }, + { + "EventCode": "0xC1", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", + "SampleAfterValue": "100003", + "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "PublicDescription": "Counts the number of micro-ops retired, Use cmask=1 and invert to count active cycles or stalled cycles.", + "EventCode": "0xC2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.ALL", + "SampleAfterValue": "2000003", + "BriefDescription": "Actually retired uops. ", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "PublicDescription": "Counts the number of retirement slots used each cycle.", + "EventCode": "0xC2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "SampleAfterValue": "2000003", + "BriefDescription": "Retirement slots used. ", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC2", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles without actually retired uops.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC2", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with less than 10 actually retired uops.", + "CounterMask": "10", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC2", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles without actually retired uops.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Number of self-modifying-code machine clears detected.", + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "MACHINE_CLEARS.SMC", + "SampleAfterValue": "100003", + "BriefDescription": "Self-modifying code (SMC) detected.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0.", + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "MACHINE_CLEARS.MASKMOV", + "SampleAfterValue": "100003", + "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0. ", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "PublicDescription": "Counts the number of conditional branch instructions retired.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BR_INST_RETIRED.CONDITIONAL", + "SampleAfterValue": "400009", + "BriefDescription": "Conditional branch instructions retired. ", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "PublicDescription": "Direct and indirect near call instructions retired.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "SampleAfterValue": "100007", + "BriefDescription": "Direct and indirect near call instructions retired. ", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Branch instructions at retirement.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "SampleAfterValue": "400009", + "BriefDescription": "All (macro) branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "PublicDescription": "Counts the number of near return instructions retired.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "SampleAfterValue": "100007", + "BriefDescription": "Return instructions retired. ", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts the number of not taken branch instructions retired.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "BR_INST_RETIRED.NOT_TAKEN", + "SampleAfterValue": "400009", + "BriefDescription": "Not taken branch instructions retired. ", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "PublicDescription": "Number of near taken branches retired.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "SampleAfterValue": "400009", + "BriefDescription": "Taken branch instructions retired. ", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of far branches retired.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "SampleAfterValue": "100007", + "BriefDescription": "Far branch instructions retired. ", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "2", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", + "SampleAfterValue": "400009", + "BriefDescription": "All (macro) branch instructions retired.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "PublicDescription": "Mispredicted conditional branch instructions retired.", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BR_MISP_RETIRED.CONDITIONAL", + "SampleAfterValue": "400009", + "BriefDescription": "Mispredicted conditional branch instructions retired. ", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Mispredicted branch instructions at retirement.", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "SampleAfterValue": "400009", + "BriefDescription": "All mispredicted macro branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "PublicDescription": "Mispredicted taken branch instructions retired.", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "SampleAfterValue": "400009", + "BriefDescription": "number of near branch instructions retired that were mispredicted and taken. ", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "2", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", + "SampleAfterValue": "400009", + "BriefDescription": "Mispredicted macro branch instructions retired.", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Count cases of saving new LBR records by hardware.", + "EventCode": "0xCC", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", + "SampleAfterValue": "2000003", + "BriefDescription": "Count cases of saving new LBR", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of front end re-steers due to BPU misprediction.", + "EventCode": "0xE6", + "Counter": "0,1,2,3", + "UMask": "0x1f", + "EventName": "BACLEARS.ANY", + "SampleAfterValue": "100003", + "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles where at least 1 uop was executed per-thread.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles where at least 1 uop was executed per-thread", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles where at least 2 uops were executed per-thread.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles where at least 2 uops were executed per-thread", + "CounterMask": "2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles where at least 3 uops were executed per-thread.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles where at least 3 uops were executed per-thread", + "CounterMask": "3", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles where at least 4 uops were executed per-thread.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles where at least 4 uops were executed per-thread", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5E", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EdgeDetect": "1", + "EventName": "RS_EVENTS.EMPTY_END", + "SampleAfterValue": "200003", + "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EdgeDetect": "1", + "EventName": "MACHINE_CLEARS.COUNT", + "SampleAfterValue": "100003", + "BriefDescription": "Number of machine clears (nukes) of any type.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", + "EventCode": "0xA8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LSD.CYCLES_4_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA3", + "Counter": "2", + "UMask": "0x8", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", + "CounterMask": "8", + "CounterHTOff": "2" + }, + { + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles while L2 cache miss load* is outstanding.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles while memory subsystem has an outstanding load.", + "CounterMask": "2", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", + "SampleAfterValue": "2000003", + "BriefDescription": "Total execution stalls.", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xA3", + "Counter": "2", + "UMask": "0xc", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", + "SampleAfterValue": "2000003", + "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "CounterMask": "12", + "CounterHTOff": "2" + }, + { + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x5", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", + "SampleAfterValue": "2000003", + "BriefDescription": "Execution stalls while L2 cache miss load* is outstanding.", + "CounterMask": "5", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x6", + "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", + "CounterMask": "6", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "EventCode": "0x00", + "Counter": "Fixed counter 2", + "UMask": "0x2", + "AnyThread": "1", + "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state", + "CounterHTOff": "Fixed counter 2" + }, + { + "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x0", + "AnyThread": "1", + "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0D", + "Counter": "0,1,2,3", + "UMask": "0x3", + "AnyThread": "1", + "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core", + "CounterMask": "2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core", + "CounterMask": "3", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles with no micro-ops executed from any thread on physical core.", + "EventCode": "0xB1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)", + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "SampleAfterValue": "2000003", + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "2000003", + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/virtual-memory.json b/tools/perf/pmu-events/arch/x86/ivybridge/virtual-memory.json new file mode 100644 index 000000000000..f036f5398906 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/ivybridge/virtual-memory.json @@ -0,0 +1,180 @@ +[ + { + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x88", + "EventName": "DTLB_LOAD_MISSES.LARGE_PAGE_WALK_COMPLETED", + "SampleAfterValue": "100003", + "BriefDescription": "Page walk for a large page completed for Demand load.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).", + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", + "SampleAfterValue": "100003", + "BriefDescription": "Store misses in all DTLB levels that cause page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G).", + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "SampleAfterValue": "100003", + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles PMH is busy with this walk.", + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "DTLB_STORE_MISSES.WALK_DURATION", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when PMH is busy with page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "SampleAfterValue": "100003", + "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x4F", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "EPT.WALK_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts load operations that missed 1st level DTLB but hit the 2nd level.", + "EventCode": "0x5F", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "SampleAfterValue": "100003", + "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Misses in all ITLB levels that cause page walks.", + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", + "SampleAfterValue": "100003", + "BriefDescription": "Misses at all ITLB levels that cause page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Misses in all ITLB levels that cause completed page walks.", + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "SampleAfterValue": "100003", + "BriefDescription": "Misses in all ITLB levels that cause completed page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycle PMH is busy with a walk.", + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "ITLB_MISSES.WALK_DURATION", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when PMH is busy with page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of cache load STLB hits. No page walk.", + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "ITLB_MISSES.STLB_HIT", + "SampleAfterValue": "100003", + "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Completed page walks in ITLB due to STLB load misses for large pages.", + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "ITLB_MISSES.LARGE_PAGE_WALK_COMPLETED", + "SampleAfterValue": "100003", + "BriefDescription": "Completed page walks in ITLB due to STLB load misses for large pages", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts the number of ITLB flushes, includes 4k/2M/4M pages.", + "EventCode": "0xAE", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ITLB.ITLB_FLUSH", + "SampleAfterValue": "100007", + "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "DTLB flush attempts of the thread-specific entries.", + "EventCode": "0xBD", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "TLB_FLUSH.DTLB_THREAD", + "SampleAfterValue": "100007", + "BriefDescription": "DTLB flush attempts of the thread-specific entries", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Count number of STLB flush attempts.", + "EventCode": "0xBD", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "TLB_FLUSH.STLB_ANY", + "SampleAfterValue": "100007", + "BriefDescription": "STLB flush attempts", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand loads.", + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x81", + "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", + "SampleAfterValue": "100003", + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Misses in all TLB levels that caused page walk completed of any size by demand loads.", + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x82", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "SampleAfterValue": "100003", + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycle PMH is busy with a walk due to demand loads.", + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x84", + "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", + "SampleAfterValue": "2000003", + "BriefDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivytown/cache.json b/tools/perf/pmu-events/arch/x86/ivytown/cache.json new file mode 100644 index 000000000000..ff27a620edd8 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/ivytown/cache.json @@ -0,0 +1,1272 @@ +[ + { + "PublicDescription": "Demand Data Read requests that hit L2 cache.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "SampleAfterValue": "200003", + "BriefDescription": "Demand Data Read requests that hit L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "RFO requests that hit L2 cache.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_RQSTS.RFO_HIT", + "SampleAfterValue": "200003", + "BriefDescription": "RFO requests that hit L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_RQSTS.RFO_MISS", + "SampleAfterValue": "200003", + "BriefDescription": "RFO requests that miss L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of instruction fetches that hit the L2 cache.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "L2_RQSTS.CODE_RD_HIT", + "SampleAfterValue": "200003", + "BriefDescription": "L2 cache hits when fetching instructions, code reads.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of instruction fetches that missed the L2 cache.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "L2_RQSTS.CODE_RD_MISS", + "SampleAfterValue": "200003", + "BriefDescription": "L2 cache misses when fetching instructions", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "L2_RQSTS.PF_HIT", + "SampleAfterValue": "200003", + "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "L2_RQSTS.PF_MISS", + "SampleAfterValue": "200003", + "BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x3", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "SampleAfterValue": "200003", + "BriefDescription": "Demand Data Read requests", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts all L2 store RFO requests.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xc", + "EventName": "L2_RQSTS.ALL_RFO", + "SampleAfterValue": "200003", + "BriefDescription": "RFO requests to L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts all L2 code requests.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "SampleAfterValue": "200003", + "BriefDescription": "L2 code requests", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts all L2 HW prefetcher requests.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xc0", + "EventName": "L2_RQSTS.ALL_PF", + "SampleAfterValue": "200003", + "BriefDescription": "Requests from L2 hardware prefetchers", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "RFOs that miss cache lines.", + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_STORE_LOCK_RQSTS.MISS", + "SampleAfterValue": "200003", + "BriefDescription": "RFOs that miss cache lines", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "RFOs that hit cache lines in M state.", + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_STORE_LOCK_RQSTS.HIT_M", + "SampleAfterValue": "200003", + "BriefDescription": "RFOs that hit cache lines in M state", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "RFOs that access cache lines in any state.", + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "L2_STORE_LOCK_RQSTS.ALL", + "SampleAfterValue": "200003", + "BriefDescription": "RFOs that access cache lines in any state", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Not rejected writebacks that missed LLC.", + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_L1D_WB_RQSTS.MISS", + "SampleAfterValue": "200003", + "BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.", + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_L1D_WB_RQSTS.HIT_E", + "SampleAfterValue": "200003", + "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.", + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_L1D_WB_RQSTS.HIT_M", + "SampleAfterValue": "200003", + "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "L2_L1D_WB_RQSTS.ALL", + "SampleAfterValue": "200003", + "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts each cache miss condition for references to the last level cache.", + "EventCode": "0x2E", + "Counter": "0,1,2,3", + "UMask": "0x41", + "EventName": "LONGEST_LAT_CACHE.MISS", + "SampleAfterValue": "100003", + "BriefDescription": "Core-originated cacheable demand requests missed LLC", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.", + "EventCode": "0x2E", + "Counter": "0,1,2,3", + "UMask": "0x4f", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "SampleAfterValue": "100003", + "BriefDescription": "Core-originated cacheable demand requests that refer to LLC", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.", + "EventCode": "0x48", + "Counter": "2", + "UMask": "0x1", + "EventName": "L1D_PEND_MISS.PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "L1D miss oustandings duration in cycles", + "CounterHTOff": "2" + }, + { + "EventCode": "0x48", + "Counter": "2", + "UMask": "0x1", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with L1D load Misses outstanding.", + "CounterMask": "1", + "CounterHTOff": "2" + }, + { + "PublicDescription": "Counts the number of lines brought into the L1 data cache.", + "EventCode": "0x51", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L1D.REPLACEMENT", + "SampleAfterValue": "2000003", + "BriefDescription": "L1D data line replacements", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles in which the L1D is locked.", + "EventCode": "0x63", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when L1D is locked", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Demand data read requests sent to uncore.", + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "SampleAfterValue": "100003", + "BriefDescription": "Demand Data Read requests sent to uncore", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Demand code read requests sent to uncore.", + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "SampleAfterValue": "100003", + "BriefDescription": "Cacheable and noncachaeble code read requests", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.", + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "SampleAfterValue": "100003", + "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Data read requests sent to uncore (demand and prefetch).", + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", + "SampleAfterValue": "100003", + "BriefDescription": "Demand and prefetch data reads", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cases when offcore requests buffer cannot take more entries for core.", + "EventCode": "0xB2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", + "SampleAfterValue": "2000003", + "BriefDescription": "Cases when offcore requests buffer cannot take more entries for core", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x11", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load uops that miss the STLB.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x12", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", + "SampleAfterValue": "100003", + "BriefDescription": "Retired store uops that miss the STLB.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x21", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "SampleAfterValue": "100007", + "BriefDescription": "Retired load uops with locked access.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x41", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load uops that split across a cacheline boundary.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x42", + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "SampleAfterValue": "100003", + "BriefDescription": "Retired store uops that split across a cacheline boundary.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x81", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "SampleAfterValue": "2000003", + "BriefDescription": "All retired load uops.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x82", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "SampleAfterValue": "2000003", + "BriefDescription": "All retired store uops.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "PublicDescription": "Retired load uops with L1 cache hits as data sources.", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "SampleAfterValue": "2000003", + "BriefDescription": "Retired load uops with L1 cache hits as data sources. ", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "PublicDescription": "Retired load uops with L2 cache hits as data sources.", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load uops with L2 cache hits as data sources. ", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "PublicDescription": "Retired load uops whose data source was LLC hit with no snoop required.", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT", + "SampleAfterValue": "50021", + "BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required. ", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "PublicDescription": "Retired load uops whose data source followed an L1 miss.", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load uops which data sources following L1 data-cache miss", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "PublicDescription": "Retired load uops that missed L2, excluding unknown sources.", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "SampleAfterValue": "50021", + "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "PublicDescription": "Retired load uops whose data source is LLC miss.", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS", + "SampleAfterValue": "100007", + "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "PublicDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. ", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "PublicDescription": "Retired load uops whose data source was an on-package core cache LLC hit and cross-core snoop missed.", + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", + "SampleAfterValue": "20011", + "BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. ", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "PublicDescription": "Retired load uops whose data source was an on-package LLC hit and cross-core snoop hits.", + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", + "SampleAfterValue": "20011", + "BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. ", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "PublicDescription": "Retired load uops whose data source was an on-package core cache with HitM responses.", + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", + "SampleAfterValue": "20011", + "BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC. ", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "PublicDescription": "Retired load uops whose data source was LLC hit with no snoop required.", + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required. ", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Retired load uop whose Data Source was: local DRAM either Snoop not needed or Snoop Miss (RspI)", + "EventCode": "0xD3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", + "SampleAfterValue": "100007", + "BriefDescription": "Retired load uops which data sources missed LLC but serviced from local dram.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD3", + "Counter": "0,1,2,3", + "UMask": "0xc", + "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM", + "SampleAfterValue": "100007", + "BriefDescription": "Retired load uops whose data source was remote DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded).", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD3", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM", + "SampleAfterValue": "100007", + "BriefDescription": "Remote cache HITM.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD3", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD", + "SampleAfterValue": "100007", + "BriefDescription": "Data forwarded from remote cache.", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Demand Data Read requests that access L2 cache.", + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_TRANS.DEMAND_DATA_RD", + "SampleAfterValue": "200003", + "BriefDescription": "Demand Data Read requests that access L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "RFO requests that access L2 cache.", + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_TRANS.RFO", + "SampleAfterValue": "200003", + "BriefDescription": "RFO requests that access L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "L2 cache accesses when fetching instructions.", + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_TRANS.CODE_RD", + "SampleAfterValue": "200003", + "BriefDescription": "L2 cache accesses when fetching instructions", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Any MLC or LLC HW prefetch accessing L2, including rejects.", + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_TRANS.ALL_PF", + "SampleAfterValue": "200003", + "BriefDescription": "L2 or LLC HW prefetches that access L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "L1D writebacks that access L2 cache.", + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "L2_TRANS.L1D_WB", + "SampleAfterValue": "200003", + "BriefDescription": "L1D writebacks that access L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "L2 fill requests that access L2 cache.", + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "L2_TRANS.L2_FILL", + "SampleAfterValue": "200003", + "BriefDescription": "L2 fill requests that access L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "L2 writebacks that access L2 cache.", + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "L2_TRANS.L2_WB", + "SampleAfterValue": "200003", + "BriefDescription": "L2 writebacks that access L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Transactions accessing L2 pipe.", + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "L2_TRANS.ALL_REQUESTS", + "SampleAfterValue": "200003", + "BriefDescription": "Transactions accessing L2 pipe", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "L2 cache lines in I state filling L2.", + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_LINES_IN.I", + "SampleAfterValue": "100003", + "BriefDescription": "L2 cache lines in I state filling L2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "L2 cache lines in S state filling L2.", + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_LINES_IN.S", + "SampleAfterValue": "100003", + "BriefDescription": "L2 cache lines in S state filling L2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "L2 cache lines in E state filling L2.", + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_LINES_IN.E", + "SampleAfterValue": "100003", + "BriefDescription": "L2 cache lines in E state filling L2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "L2 cache lines filling L2.", + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x7", + "EventName": "L2_LINES_IN.ALL", + "SampleAfterValue": "100003", + "BriefDescription": "L2 cache lines filling L2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Clean L2 cache lines evicted by demand.", + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_LINES_OUT.DEMAND_CLEAN", + "SampleAfterValue": "100003", + "BriefDescription": "Clean L2 cache lines evicted by demand", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Dirty L2 cache lines evicted by demand.", + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_LINES_OUT.DEMAND_DIRTY", + "SampleAfterValue": "100003", + "BriefDescription": "Dirty L2 cache lines evicted by demand", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Clean L2 cache lines evicted by the MLC prefetcher.", + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_LINES_OUT.PF_CLEAN", + "SampleAfterValue": "100003", + "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Dirty L2 cache lines evicted by the MLC prefetcher.", + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_LINES_OUT.PF_DIRTY", + "SampleAfterValue": "100003", + "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Dirty L2 cache lines filling the L2.", + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0xa", + "EventName": "L2_LINES_OUT.DIRTY_ALL", + "SampleAfterValue": "100003", + "BriefDescription": "Dirty L2 cache lines filling the L2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF4", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "SQ_MISC.SPLIT_LOCK", + "SampleAfterValue": "100003", + "BriefDescription": "Split locks in SQ", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue", + "CounterMask": "6", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", + "EventCode": "0x48", + "Counter": "2", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core", + "CounterMask": "1", + "CounterHTOff": "2" + }, + { + "PublicDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", + "EventCode": "0x48", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L1D_PEND_MISS.FB_FULL", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4003c0091", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0091", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003c0091", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2003c0091", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoop returned a clean response", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0090", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch data reads that hit the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4003c0090", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0090", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003c0090", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2003c0090", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoop returned a clean response", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c03f7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4003c03f7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c03f7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003c03f7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2003c03f7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoop returned a clean response", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10008", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all writebacks from the core to the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand code reads that hit in the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand data reads that hit in the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4003c0001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003c0001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2003c0001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoop returned a clean response", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0002", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x803c8000", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.OTHER.LRU_HINTS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x23ffc08000", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0040", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that hit in the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4003c0010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003c0010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2003c0010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0200", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0080", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4003c0080", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0080", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003c0080", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2003c0080", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10400", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10800", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts non-temporal stores", + "CounterHTOff": "0,1,2,3" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivytown/floating-point.json b/tools/perf/pmu-events/arch/x86/ivytown/floating-point.json new file mode 100644 index 000000000000..950b62c0908e --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/ivytown/floating-point.json @@ -0,0 +1,151 @@ +[ + { + "PublicDescription": "Counts number of X87 uops executed.", + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "FP_COMP_OPS_EXE.X87", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.", + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.", + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.", + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts number of SSE* or AVX-128 double precision FP scalar uops executed.", + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts 256-bit packed single-precision floating-point instructions.", + "EventCode": "0x11", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "SIMD_FP_256.PACKED_SINGLE", + "SampleAfterValue": "2000003", + "BriefDescription": "number of GSSE-256 Computational FP single precision uops issued this cycle", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts 256-bit packed double-precision floating-point instructions.", + "EventCode": "0x11", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "SIMD_FP_256.PACKED_DOUBLE", + "SampleAfterValue": "2000003", + "BriefDescription": "number of AVX-256 Computational FP double precision uops issued this cycle", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of assists associated with 256-bit AVX store operations.", + "EventCode": "0xC1", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "OTHER_ASSISTS.AVX_STORE", + "SampleAfterValue": "100003", + "BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC1", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "OTHER_ASSISTS.AVX_TO_SSE", + "SampleAfterValue": "100003", + "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC1", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "OTHER_ASSISTS.SSE_TO_AVX", + "SampleAfterValue": "100003", + "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of X87 FP assists due to output values.", + "EventCode": "0xCA", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "FP_ASSIST.X87_OUTPUT", + "SampleAfterValue": "100003", + "BriefDescription": "Number of X87 assists due to output value.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of X87 FP assists due to input values.", + "EventCode": "0xCA", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "FP_ASSIST.X87_INPUT", + "SampleAfterValue": "100003", + "BriefDescription": "Number of X87 assists due to input value.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of SIMD FP assists due to output values.", + "EventCode": "0xCA", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "FP_ASSIST.SIMD_OUTPUT", + "SampleAfterValue": "100003", + "BriefDescription": "Number of SIMD FP assists due to Output values", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of SIMD FP assists due to input values.", + "EventCode": "0xCA", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "FP_ASSIST.SIMD_INPUT", + "SampleAfterValue": "100003", + "BriefDescription": "Number of SIMD FP assists due to input values", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles with any input/output SSE* or FP assists.", + "EventCode": "0xCA", + "Counter": "0,1,2,3", + "UMask": "0x1e", + "EventName": "FP_ASSIST.ANY", + "SampleAfterValue": "100003", + "BriefDescription": "Cycles with any input/output SSE or FP assist", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivytown/frontend.json b/tools/perf/pmu-events/arch/x86/ivytown/frontend.json new file mode 100644 index 000000000000..de72b84b3536 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/ivytown/frontend.json @@ -0,0 +1,305 @@ +[ + { + "PublicDescription": "Counts cycles the IDQ is empty.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "IDQ.EMPTY", + "SampleAfterValue": "2000003", + "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "IDQ.MITE_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "IDQ.DSB_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "IDQ.MS_DSB_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "IDQ.MS_MITE_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "IDQ.MS_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "IDQ.MS_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "IDQ.MITE_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "IDQ.DSB_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "IDQ.MS_DSB_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EdgeDetect": "1", + "EventName": "IDQ.MS_DSB_OCCUR", + "SampleAfterValue": "2000003", + "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x18", + "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x18", + "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts cycles MITE is delivered four uops. Set Cmask = 4.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x24", + "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles MITE is delivering 4 Uops", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts cycles MITE is delivered at least one uops. Set Cmask = 1.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x24", + "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles MITE is delivering any Uop", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of uops delivered to IDQ from any path.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x3c", + "EventName": "IDQ.MITE_ALL_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.", + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ICACHE.HIT", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses.", + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "ICACHE.MISSES", + "SampleAfterValue": "200003", + "BriefDescription": "Instruction cache, streaming buffer and victim cache misses", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss.", + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "ICACHE.IFETCH_STALL", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Count issue pipeline slots where no uop was delivered from the front end to the back end when there is no back-end stall.", + "EventCode": "0x9C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled ", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", + "CounterMask": "3", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", + "CounterMask": "2", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with less than 3 uops delivered by the front end.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Number of DSB to MITE switches.", + "EventCode": "0xAB", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "DSB2MITE_SWITCHES.COUNT", + "SampleAfterValue": "2000003", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles DSB to MITE switches caused delay.", + "EventCode": "0xAB", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "DSB Fill encountered > 3 DSB lines.", + "EventCode": "0xAC", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "DSB_FILL.EXCEED_DSB_LINES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EdgeDetect": "1", + "EventName": "IDQ.MS_SWITCHES", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivytown/memory.json b/tools/perf/pmu-events/arch/x86/ivytown/memory.json new file mode 100644 index 000000000000..437d98f3e344 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/ivytown/memory.json @@ -0,0 +1,503 @@ +[ + { + "PublicDescription": "Speculative cache-line split load uops dispatched to L1D.", + "EventCode": "0x05", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MISALIGN_MEM_REF.LOADS", + "SampleAfterValue": "2000003", + "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Speculative cache-line split Store-address uops dispatched to L1D.", + "EventCode": "0x05", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MISALIGN_MEM_REF.STORES", + "SampleAfterValue": "2000003", + "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "SampleAfterValue": "100003", + "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "2", + "EventCode": "0xCD", + "Counter": "3", + "UMask": "0x2", + "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only.", + "PRECISE_STORE": "1", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 4.", + "EventCode": "0xCD", + "MSRValue": "0x4", + "Counter": "3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "SampleAfterValue": "100003", + "BriefDescription": "Loads with latency value being above 4", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 8.", + "EventCode": "0xCD", + "MSRValue": "0x8", + "Counter": "3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "MSRIndex": "0x3F6", + "SampleAfterValue": "50021", + "BriefDescription": "Loads with latency value being above 8", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 16.", + "EventCode": "0xCD", + "MSRValue": "0x10", + "Counter": "3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "MSRIndex": "0x3F6", + "SampleAfterValue": "20011", + "BriefDescription": "Loads with latency value being above 16", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 32.", + "EventCode": "0xCD", + "MSRValue": "0x20", + "Counter": "3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "MSRIndex": "0x3F6", + "SampleAfterValue": "100007", + "BriefDescription": "Loads with latency value being above 32", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 64.", + "EventCode": "0xCD", + "MSRValue": "0x40", + "Counter": "3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "MSRIndex": "0x3F6", + "SampleAfterValue": "2003", + "BriefDescription": "Loads with latency value being above 64", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 128.", + "EventCode": "0xCD", + "MSRValue": "0x80", + "Counter": "3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "MSRIndex": "0x3F6", + "SampleAfterValue": "1009", + "BriefDescription": "Loads with latency value being above 128", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 256.", + "EventCode": "0xCD", + "MSRValue": "0x100", + "Counter": "3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "MSRIndex": "0x3F6", + "SampleAfterValue": "503", + "BriefDescription": "Loads with latency value being above 256", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 512.", + "EventCode": "0xCD", + "MSRValue": "0x200", + "Counter": "3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "MSRIndex": "0x3F6", + "SampleAfterValue": "101", + "BriefDescription": "Loads with latency value being above 512", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fffc00244", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x67f800244", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC and the data returned from remote dram", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x87f800244", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC and the data forwarded from remote cache", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fffc20091", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch data reads that hits the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fffc203f7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x6004003f7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from local dram", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x87f8203f7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data forwarded from remote cache", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x107fc003f7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC the data is found in M state in remote cache and forwarded from there", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fffc20004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand code reads that miss the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x600400004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from local dram", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x67f800004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from remote dram", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x87f820004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand code reads that miss the LLC and the data forwarded from remote cache", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x107fc00004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand code reads that miss the LLC the data is found in M state in remote cache and forwarded from there", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x67fc00001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote & local dram", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fffc20001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that miss in the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x600400001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from local dram", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x67f800001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote dram", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x87f820001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that miss the LLC and the data forwarded from remote cache", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x107fc00001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that miss the LLC the data is found in M state in remote cache and forwarded from there", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x107fc20002", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand data writes (RFOs) that miss the LLC and the data is found in M state in remote cache and forwarded from there.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fffc20040", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from remote & local dram", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x67fc00010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote & local dram", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fffc20010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x600400010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from local dram", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x67f800010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote dram", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x87f820010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data forwarded from remote cache", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x107fc00010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC the data is found in M state in remote cache and forwarded from there", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fffc20200", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fffc20080", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that miss in the LLC", + "CounterHTOff": "0,1,2,3" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivytown/other.json b/tools/perf/pmu-events/arch/x86/ivytown/other.json new file mode 100644 index 000000000000..9c2dd0511a32 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/ivytown/other.json @@ -0,0 +1,44 @@ +[ + { + "PublicDescription": "Unhalted core cycles when the thread is in ring 0.", + "EventCode": "0x5C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CPL_CYCLES.RING0", + "SampleAfterValue": "2000003", + "BriefDescription": "Unhalted core cycles when the thread is in ring 0", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.", + "EventCode": "0x5C", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "CPL_CYCLES.RING123", + "SampleAfterValue": "2000003", + "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of intervals between processor halts while thread is in ring 0.", + "EventCode": "0x5C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EdgeDetect": "1", + "EventName": "CPL_CYCLES.RING0_TRANS", + "SampleAfterValue": "100007", + "BriefDescription": "Number of intervals between processor halts while thread is in ring 0", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.", + "EventCode": "0x63", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivytown/pipeline.json b/tools/perf/pmu-events/arch/x86/ivytown/pipeline.json new file mode 100644 index 000000000000..2145c28193f7 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/ivytown/pipeline.json @@ -0,0 +1,1307 @@ +[ + { + "EventCode": "0x00", + "Counter": "Fixed counter 1", + "UMask": "0x1", + "EventName": "INST_RETIRED.ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Instructions retired from execution.", + "CounterHTOff": "Fixed counter 1" + }, + { + "EventCode": "0x00", + "Counter": "Fixed counter 2", + "UMask": "0x2", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "SampleAfterValue": "2000003", + "BriefDescription": "Core cycles when the thread is not in halt state.", + "CounterHTOff": "Fixed counter 2" + }, + { + "EventCode": "0x00", + "Counter": "Fixed counter 3", + "UMask": "0x3", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "SampleAfterValue": "2000003", + "BriefDescription": "Reference cycles when the core is not in halt state.", + "CounterHTOff": "Fixed counter 3" + }, + { + "PublicDescription": "Loads blocked by overlapping with store buffer that cannot be forwarded.", + "EventCode": "0x03", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "SampleAfterValue": "100003", + "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "EventCode": "0x03", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "LD_BLOCKS.NO_SR", + "SampleAfterValue": "100003", + "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "False dependencies in MOB due to partial compare on address.", + "EventCode": "0x07", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "SampleAfterValue": "100003", + "BriefDescription": "False dependencies in MOB due to partial compare on address", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0D", + "Counter": "0,1,2,3", + "UMask": "0x3", + "EventName": "INT_MISC.RECOVERY_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.)", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0D", + "Counter": "0,1,2,3", + "UMask": "0x3", + "EdgeDetect": "1", + "EventName": "INT_MISC.RECOVERY_STALLS_COUNT", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.)", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Increments each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core.", + "EventCode": "0x0E", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_ISSUED.ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.", + "EventCode": "0x0E", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.", + "EventCode": "0x0E", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Number of flags-merge uops allocated. Such uops adds delay.", + "EventCode": "0x0E", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "UOPS_ISSUED.FLAGS_MERGE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of flags-merge uops being allocated.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", + "EventCode": "0x0E", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "UOPS_ISSUED.SLOW_LEA", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of multiply packed/scalar single precision uops allocated.", + "EventCode": "0x0E", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "UOPS_ISSUED.SINGLE_MUL", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=1' to count the number of divides.", + "EventCode": "0x14", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ARITH.FPU_DIV_ACTIVE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when divider is busy executing divide operations", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Divide operations executed.", + "EventCode": "0x14", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EdgeDetect": "1", + "EventName": "ARITH.FPU_DIV", + "SampleAfterValue": "100003", + "BriefDescription": "Divide operations executed", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.", + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "SampleAfterValue": "2000003", + "BriefDescription": "Thread cycles when thread is not in halt state", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Increments at the frequency of XCLK (100 MHz) when not halted.", + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", + "SampleAfterValue": "2000003", + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "2000003", + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other is halted.", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.", + "EventCode": "0x4C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LOAD_HIT_PRE.SW_PF", + "SampleAfterValue": "100003", + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.", + "EventCode": "0x4C", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "LOAD_HIT_PRE.HW_PF", + "SampleAfterValue": "100003", + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x58", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", + "SampleAfterValue": "1000003", + "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x58", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", + "SampleAfterValue": "1000003", + "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x58", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", + "SampleAfterValue": "1000003", + "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x58", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", + "SampleAfterValue": "1000003", + "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles the RS is empty for the thread.", + "EventCode": "0x5E", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "RS_EVENTS.EMPTY_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x87", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ILD_STALL.LCP", + "SampleAfterValue": "2000003", + "BriefDescription": "Stalls caused by changing prefix length of the instruction.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Stall cycles due to IQ is full.", + "EventCode": "0x87", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "ILD_STALL.IQ_FULL", + "SampleAfterValue": "2000003", + "BriefDescription": "Stall cycles because IQ is full", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Not taken macro-conditional branches.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x41", + "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Not taken macro-conditional branches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Taken speculative and retired macro-conditional branches.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x81", + "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired macro-conditional branches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x82", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Taken speculative and retired indirect branches excluding calls and returns.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x84", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Taken speculative and retired indirect branches with return mnemonic.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Taken speculative and retired direct near calls.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x90", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired direct near calls", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Taken speculative and retired indirect calls.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xa0", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired indirect calls", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Speculative and retired macro-conditional branches.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xc1", + "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired macro-conditional branches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xc2", + "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Speculative and retired indirect branches excluding calls and returns.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xc4", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired indirect branches excluding calls and returns", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xc8", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired indirect return branches.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Speculative and retired direct near calls.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xd0", + "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired direct near calls", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts all near executed branches (not necessarily retired).", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xff", + "EventName": "BR_INST_EXEC.ALL_BRANCHES", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired branches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Not taken speculative and retired mispredicted macro conditional branches.", + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x41", + "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Taken speculative and retired mispredicted macro conditional branches.", + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x81", + "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns.", + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x84", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic.", + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x88", + "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Taken speculative and retired mispredicted indirect calls.", + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0xa0", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired mispredicted indirect calls", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Speculative and retired mispredicted macro conditional branches.", + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0xc1", + "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired mispredicted macro conditional branches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Mispredicted indirect branches excluding calls and returns.", + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0xc4", + "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "BriefDescription": "Mispredicted indirect branches excluding calls and returns", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts all near executed branches (not necessarily retired).", + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0xff", + "EventName": "BR_MISP_EXEC.ALL_BRANCHES", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired mispredicted macro conditional branches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles which a Uop is dispatched on port 0.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are dispatched to port 0", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles which a Uop is dispatched on port 1.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are dispatched to port 1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles which a Uop is dispatched on port 4.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are dispatched to port 4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles which a Uop is dispatched on port 5.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are dispatched to port 5", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles per core when uops are dispatched to port 0.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when uops are dispatched to port 0", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles per core when uops are dispatched to port 1.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "AnyThread": "1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when uops are dispatched to port 1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles per core when uops are dispatched to port 4.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x40", + "AnyThread": "1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when uops are dispatched to port 4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles per core when uops are dispatched to port 5.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x80", + "AnyThread": "1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when uops are dispatched to port 5", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles which a Uop is dispatched on port 2.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0xc", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles which a Uop is dispatched on port 3.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0xc", + "AnyThread": "1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops dispatched to port 2, loads and stores per core (speculative and retired).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles per core when load or STA uops are dispatched to port 3.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x30", + "AnyThread": "1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles Allocation is stalled due to Resource Related reason.", + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "RESOURCE_STALLS.ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Resource-related stall cycles", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "RESOURCE_STALLS.RS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles stalled due to no eligible RS entry available.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles stalled due to no store buffers available (not including draining form sync).", + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "RESOURCE_STALLS.SB", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "RESOURCE_STALLS.ROB", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles stalled due to re-order buffer full.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles with pending L2 miss loads. Set AnyThread to count per core.", + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with pending L2 cache miss loads.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles with pending L1 cache miss loads. Set AnyThread to count per core.", + "EventCode": "0xA3", + "Counter": "2", + "UMask": "0x8", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with pending L1 cache miss loads.", + "CounterMask": "8", + "CounterHTOff": "2" + }, + { + "PublicDescription": "Cycles with pending memory loads. Set AnyThread to count per core.", + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with pending memory loads.", + "CounterMask": "2", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Total execution stalls.", + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", + "SampleAfterValue": "2000003", + "BriefDescription": "Total execution stalls", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Number of loads missed L2.", + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x5", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "Execution stalls due to L2 cache misses.", + "CounterMask": "5", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x6", + "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "Execution stalls due to memory subsystem.", + "CounterMask": "6", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Execution stalls due to L1 data cache miss loads. Set Cmask=0CH.", + "EventCode": "0xA3", + "Counter": "2", + "UMask": "0xc", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "Execution stalls due to L1 data cache misses", + "CounterMask": "12", + "CounterHTOff": "2" + }, + { + "EventCode": "0xA8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LSD.UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of Uops delivered by the LSD.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", + "EventCode": "0xA8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LSD.CYCLES_ACTIVE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts total number of uops to be executed per-thread each cycle. Set Cmask = 1, INV =1 to count stall cycles.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_EXECUTED.THREAD", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts total number of uops to be executed per-core each cycle.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of uops executed on the core.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_EXECUTED.STALL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Number of instructions at retirement.", + "EventCode": "0xC0", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "INST_RETIRED.ANY_P", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of instructions retired. General Counter - architectural event", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "2", + "PublicDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution.", + "EventCode": "0xC0", + "Counter": "1", + "UMask": "0x1", + "EventName": "INST_RETIRED.PREC_DIST", + "SampleAfterValue": "2000003", + "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution", + "CounterHTOff": "1" + }, + { + "EventCode": "0xC1", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", + "SampleAfterValue": "100003", + "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "PublicDescription": "Counts the number of micro-ops retired, Use cmask=1 and invert to count active cycles or stalled cycles.", + "EventCode": "0xC2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.ALL", + "SampleAfterValue": "2000003", + "BriefDescription": "Actually retired uops. ", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "PublicDescription": "Counts the number of retirement slots used each cycle.", + "EventCode": "0xC2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "SampleAfterValue": "2000003", + "BriefDescription": "Retirement slots used. ", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC2", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles without actually retired uops.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC2", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with less than 10 actually retired uops.", + "CounterMask": "10", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC2", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles without actually retired uops.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Number of self-modifying-code machine clears detected.", + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "MACHINE_CLEARS.SMC", + "SampleAfterValue": "100003", + "BriefDescription": "Self-modifying code (SMC) detected.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0.", + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "MACHINE_CLEARS.MASKMOV", + "SampleAfterValue": "100003", + "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0. ", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "PublicDescription": "Counts the number of conditional branch instructions retired.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BR_INST_RETIRED.CONDITIONAL", + "SampleAfterValue": "400009", + "BriefDescription": "Conditional branch instructions retired. ", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "PublicDescription": "Direct and indirect near call instructions retired.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "SampleAfterValue": "100007", + "BriefDescription": "Direct and indirect near call instructions retired. ", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Branch instructions at retirement.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "SampleAfterValue": "400009", + "BriefDescription": "All (macro) branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "PublicDescription": "Counts the number of near return instructions retired.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "SampleAfterValue": "100007", + "BriefDescription": "Return instructions retired. ", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts the number of not taken branch instructions retired.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "BR_INST_RETIRED.NOT_TAKEN", + "SampleAfterValue": "400009", + "BriefDescription": "Not taken branch instructions retired. ", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "PublicDescription": "Number of near taken branches retired.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "SampleAfterValue": "400009", + "BriefDescription": "Taken branch instructions retired. ", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of far branches retired.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "SampleAfterValue": "100007", + "BriefDescription": "Far branch instructions retired. ", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "2", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", + "SampleAfterValue": "400009", + "BriefDescription": "All (macro) branch instructions retired.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "PublicDescription": "Mispredicted conditional branch instructions retired.", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BR_MISP_RETIRED.CONDITIONAL", + "SampleAfterValue": "400009", + "BriefDescription": "Mispredicted conditional branch instructions retired. ", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Mispredicted branch instructions at retirement.", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "SampleAfterValue": "400009", + "BriefDescription": "All mispredicted macro branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "PublicDescription": "Mispredicted taken branch instructions retired.", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "SampleAfterValue": "400009", + "BriefDescription": "number of near branch instructions retired that were mispredicted and taken. ", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "2", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", + "SampleAfterValue": "400009", + "BriefDescription": "Mispredicted macro branch instructions retired.", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Count cases of saving new LBR records by hardware.", + "EventCode": "0xCC", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", + "SampleAfterValue": "2000003", + "BriefDescription": "Count cases of saving new LBR", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of front end re-steers due to BPU misprediction.", + "EventCode": "0xE6", + "Counter": "0,1,2,3", + "UMask": "0x1f", + "EventName": "BACLEARS.ANY", + "SampleAfterValue": "100003", + "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles where at least 1 uop was executed per-thread.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles where at least 1 uop was executed per-thread", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles where at least 2 uops were executed per-thread.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles where at least 2 uops were executed per-thread", + "CounterMask": "2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles where at least 3 uops were executed per-thread.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles where at least 3 uops were executed per-thread", + "CounterMask": "3", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles where at least 4 uops were executed per-thread.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles where at least 4 uops were executed per-thread", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5E", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EdgeDetect": "1", + "EventName": "RS_EVENTS.EMPTY_END", + "SampleAfterValue": "200003", + "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EdgeDetect": "1", + "EventName": "MACHINE_CLEARS.COUNT", + "SampleAfterValue": "100003", + "BriefDescription": "Number of machine clears (nukes) of any type.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", + "EventCode": "0xA8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LSD.CYCLES_4_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA3", + "Counter": "2", + "UMask": "0x8", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", + "CounterMask": "8", + "CounterHTOff": "2" + }, + { + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles while L2 cache miss load* is outstanding.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles while memory subsystem has an outstanding load.", + "CounterMask": "2", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", + "SampleAfterValue": "2000003", + "BriefDescription": "Total execution stalls.", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xA3", + "Counter": "2", + "UMask": "0xc", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", + "SampleAfterValue": "2000003", + "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "CounterMask": "12", + "CounterHTOff": "2" + }, + { + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x5", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", + "SampleAfterValue": "2000003", + "BriefDescription": "Execution stalls while L2 cache miss load* is outstanding.", + "CounterMask": "5", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x6", + "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", + "CounterMask": "6", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "EventCode": "0x00", + "Counter": "Fixed counter 2", + "UMask": "0x2", + "AnyThread": "1", + "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state", + "CounterHTOff": "Fixed counter 2" + }, + { + "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x0", + "AnyThread": "1", + "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0D", + "Counter": "0,1,2,3", + "UMask": "0x3", + "AnyThread": "1", + "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core", + "CounterMask": "2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core", + "CounterMask": "3", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles with no micro-ops executed from any thread on physical core.", + "EventCode": "0xB1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)", + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "SampleAfterValue": "2000003", + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "2000003", + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivytown/virtual-memory.json b/tools/perf/pmu-events/arch/x86/ivytown/virtual-memory.json new file mode 100644 index 000000000000..c8de548b78fa --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/ivytown/virtual-memory.json @@ -0,0 +1,198 @@ +[ + { + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x82", + "EventName": "DTLB_LOAD_MISSES.DEMAND_LD_WALK_COMPLETED", + "SampleAfterValue": "100003", + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x84", + "EventName": "DTLB_LOAD_MISSES.DEMAND_LD_WALK_DURATION", + "SampleAfterValue": "2000003", + "BriefDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x88", + "EventName": "DTLB_LOAD_MISSES.LARGE_PAGE_WALK_COMPLETED", + "SampleAfterValue": "100003", + "BriefDescription": "Page walk for a large page completed for Demand load.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).", + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", + "SampleAfterValue": "100003", + "BriefDescription": "Store misses in all DTLB levels that cause page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G).", + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "SampleAfterValue": "100003", + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles PMH is busy with this walk.", + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "DTLB_STORE_MISSES.WALK_DURATION", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when PMH is busy with page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "SampleAfterValue": "100003", + "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x4F", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "EPT.WALK_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts load operations that missed 1st level DTLB but hit the 2nd level.", + "EventCode": "0x5F", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "SampleAfterValue": "100003", + "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Misses in all ITLB levels that cause page walks.", + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", + "SampleAfterValue": "100003", + "BriefDescription": "Misses at all ITLB levels that cause page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Misses in all ITLB levels that cause completed page walks.", + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "SampleAfterValue": "100003", + "BriefDescription": "Misses in all ITLB levels that cause completed page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycle PMH is busy with a walk.", + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "ITLB_MISSES.WALK_DURATION", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when PMH is busy with page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of cache load STLB hits. No page walk.", + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "ITLB_MISSES.STLB_HIT", + "SampleAfterValue": "100003", + "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Completed page walks in ITLB due to STLB load misses for large pages.", + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "ITLB_MISSES.LARGE_PAGE_WALK_COMPLETED", + "SampleAfterValue": "100003", + "BriefDescription": "Completed page walks in ITLB due to STLB load misses for large pages", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts the number of ITLB flushes, includes 4k/2M/4M pages.", + "EventCode": "0xAE", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ITLB.ITLB_FLUSH", + "SampleAfterValue": "100007", + "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "DTLB flush attempts of the thread-specific entries.", + "EventCode": "0xBD", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "TLB_FLUSH.DTLB_THREAD", + "SampleAfterValue": "100007", + "BriefDescription": "DTLB flush attempts of the thread-specific entries", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Count number of STLB flush attempts.", + "EventCode": "0xBD", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "TLB_FLUSH.STLB_ANY", + "SampleAfterValue": "100007", + "BriefDescription": "STLB flush attempts", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand loads.", + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x81", + "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", + "SampleAfterValue": "100003", + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Misses in all TLB levels that caused page walk completed of any size by demand loads.", + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x82", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "SampleAfterValue": "100003", + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycle PMH is busy with a walk due to demand loads.", + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x84", + "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", + "SampleAfterValue": "2000003", + "BriefDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/jaketown/cache.json b/tools/perf/pmu-events/arch/x86/jaketown/cache.json new file mode 100644 index 000000000000..f723e8f7bb09 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/jaketown/cache.json @@ -0,0 +1,1290 @@ +[ + { + "PEBS": "1", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x11", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load uops that miss the STLB.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x12", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", + "SampleAfterValue": "100003", + "BriefDescription": "Retired store uops that miss the STLB.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x21", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "SampleAfterValue": "100007", + "BriefDescription": "Retired load uops with locked access.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "PublicDescription": "This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x41", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load uops that split across a cacheline boundary.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "PublicDescription": "This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x42", + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "SampleAfterValue": "100003", + "BriefDescription": "Retired store uops that split across a cacheline boundary.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "PublicDescription": "This event counts the number of load uops retired", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x81", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "SampleAfterValue": "2000003", + "BriefDescription": "All retired load uops.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "PublicDescription": "This event counts the number of store uops retired.", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x82", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "SampleAfterValue": "2000003", + "BriefDescription": "All retired store uops.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "SampleAfterValue": "2000003", + "BriefDescription": "Retired load uops with L1 cache hits as data sources.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load uops with L2 cache hits as data sources.", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "This event counts retired load uops that hit in the last-level (L3) cache without snoops required.", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT", + "SampleAfterValue": "50021", + "BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS", + "SampleAfterValue": "100007", + "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", + "SampleAfterValue": "20011", + "BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a non-modified state.", + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", + "SampleAfterValue": "20011", + "BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a modified state, so the line had to be invalidated in that L2 cache and transferred to the requesting L2.", + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", + "SampleAfterValue": "20011", + "BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", + "SampleAfterValue": "100007", + "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xD3", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM", + "SampleAfterValue": "100007", + "BriefDescription": "Data from remote DRAM either Snoop not needed or Snoop Miss (RspI)", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "This event counts L1D data line replacements. Replacements occur when a new line is brought into the cache, causing eviction of a line loaded earlier. ", + "EventCode": "0x51", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L1D.REPLACEMENT", + "SampleAfterValue": "2000003", + "BriefDescription": "L1D data line replacements.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x51", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L1D.ALLOCATED_IN_M", + "SampleAfterValue": "2000003", + "BriefDescription": "Allocated L1D data cache lines in M state.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x51", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L1D.EVICTION", + "SampleAfterValue": "2000003", + "BriefDescription": "L1D data cache lines in M state evicted due to replacement.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x51", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L1D.ALL_M_REPLACEMENT", + "SampleAfterValue": "2000003", + "BriefDescription": "Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x48", + "Counter": "2", + "UMask": "0x1", + "EventName": "L1D_PEND_MISS.PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "L1D miss oustandings duration in cycles.", + "CounterHTOff": "2" + }, + { + "EventCode": "0x48", + "Counter": "2", + "UMask": "0x1", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with L1D load Misses outstanding.", + "CounterMask": "1", + "CounterHTOff": "2" + }, + { + "EventCode": "0x63", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when L1D is locked.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "SampleAfterValue": "100003", + "BriefDescription": "Demand Data Read requests sent to uncore.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "SampleAfterValue": "100003", + "BriefDescription": "Cacheable and noncachaeble code read requests.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "SampleAfterValue": "100003", + "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", + "SampleAfterValue": "100003", + "BriefDescription": "Demand and prefetch data reads.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", + "SampleAfterValue": "2000003", + "BriefDescription": "Cases when offcore requests buffer cannot take more entries for core.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "SampleAfterValue": "200003", + "BriefDescription": "Demand Data Read requests that hit L2 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_RQSTS.RFO_HIT", + "SampleAfterValue": "200003", + "BriefDescription": "RFO requests that hit L2 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_RQSTS.RFO_MISS", + "SampleAfterValue": "200003", + "BriefDescription": "RFO requests that miss L2 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "L2_RQSTS.CODE_RD_HIT", + "SampleAfterValue": "200003", + "BriefDescription": "L2 cache hits when fetching instructions, code reads.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "L2_RQSTS.CODE_RD_MISS", + "SampleAfterValue": "200003", + "BriefDescription": "L2 cache misses when fetching instructions.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "L2_RQSTS.PF_HIT", + "SampleAfterValue": "200003", + "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "L2_RQSTS.PF_MISS", + "SampleAfterValue": "200003", + "BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_STORE_LOCK_RQSTS.MISS", + "SampleAfterValue": "200003", + "BriefDescription": "RFOs that miss cache lines.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_STORE_LOCK_RQSTS.HIT_E", + "SampleAfterValue": "200003", + "BriefDescription": "RFOs that hit cache lines in E state.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_STORE_LOCK_RQSTS.HIT_M", + "SampleAfterValue": "200003", + "BriefDescription": "RFOs that hit cache lines in M state.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "L2_STORE_LOCK_RQSTS.ALL", + "SampleAfterValue": "200003", + "BriefDescription": "RFOs that access cache lines in any state.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_L1D_WB_RQSTS.MISS", + "SampleAfterValue": "200003", + "BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_L1D_WB_RQSTS.HIT_S", + "SampleAfterValue": "200003", + "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in S state.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_L1D_WB_RQSTS.HIT_E", + "SampleAfterValue": "200003", + "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_L1D_WB_RQSTS.HIT_M", + "SampleAfterValue": "200003", + "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "L2_L1D_WB_RQSTS.ALL", + "SampleAfterValue": "200003", + "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_TRANS.DEMAND_DATA_RD", + "SampleAfterValue": "200003", + "BriefDescription": "Demand Data Read requests that access L2 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_TRANS.RFO", + "SampleAfterValue": "200003", + "BriefDescription": "RFO requests that access L2 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_TRANS.CODE_RD", + "SampleAfterValue": "200003", + "BriefDescription": "L2 cache accesses when fetching instructions.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_TRANS.ALL_PF", + "SampleAfterValue": "200003", + "BriefDescription": "L2 or LLC HW prefetches that access L2 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "L2_TRANS.L1D_WB", + "SampleAfterValue": "200003", + "BriefDescription": "L1D writebacks that access L2 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "L2_TRANS.L2_FILL", + "SampleAfterValue": "200003", + "BriefDescription": "L2 fill requests that access L2 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "L2_TRANS.L2_WB", + "SampleAfterValue": "200003", + "BriefDescription": "L2 writebacks that access L2 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "L2_TRANS.ALL_REQUESTS", + "SampleAfterValue": "200003", + "BriefDescription": "Transactions accessing L2 pipe.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_LINES_IN.I", + "SampleAfterValue": "100003", + "BriefDescription": "L2 cache lines in I state filling L2.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_LINES_IN.S", + "SampleAfterValue": "100003", + "BriefDescription": "L2 cache lines in S state filling L2.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_LINES_IN.E", + "SampleAfterValue": "100003", + "BriefDescription": "L2 cache lines in E state filling L2.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss.", + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x7", + "EventName": "L2_LINES_IN.ALL", + "SampleAfterValue": "100003", + "BriefDescription": "L2 cache lines filling L2.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_LINES_OUT.DEMAND_CLEAN", + "SampleAfterValue": "100003", + "BriefDescription": "Clean L2 cache lines evicted by demand.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_LINES_OUT.DEMAND_DIRTY", + "SampleAfterValue": "100003", + "BriefDescription": "Dirty L2 cache lines evicted by demand.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_LINES_OUT.PF_CLEAN", + "SampleAfterValue": "100003", + "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_LINES_OUT.PF_DIRTY", + "SampleAfterValue": "100003", + "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0xa", + "EventName": "L2_LINES_OUT.DIRTY_ALL", + "SampleAfterValue": "100003", + "BriefDescription": "Dirty L2 cache lines filling the L2.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x2E", + "Counter": "0,1,2,3", + "UMask": "0x41", + "EventName": "LONGEST_LAT_CACHE.MISS", + "SampleAfterValue": "100003", + "BriefDescription": "Core-originated cacheable demand requests missed LLC.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x2E", + "Counter": "0,1,2,3", + "UMask": "0x4f", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "SampleAfterValue": "100003", + "BriefDescription": "Core-originated cacheable demand requests that refer to LLC.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF4", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "SQ_MISC.SPLIT_LOCK", + "SampleAfterValue": "100003", + "BriefDescription": "Split locks in SQ.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x3", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "SampleAfterValue": "200003", + "BriefDescription": "Demand Data Read requests.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xc", + "EventName": "L2_RQSTS.ALL_RFO", + "SampleAfterValue": "200003", + "BriefDescription": "RFO requests to L2 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "SampleAfterValue": "200003", + "BriefDescription": "L2 code requests.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xc0", + "EventName": "L2_RQSTS.ALL_PF", + "SampleAfterValue": "200003", + "BriefDescription": "Requests from L2 hardware prefetchers.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xBF", + "Counter": "0,1,2,3", + "UMask": "0x5", + "EventName": "L1D_BLOCKS.BANK_CONFLICT_CYCLES", + "SampleAfterValue": "100003", + "BriefDescription": "Cycles when dispatched loads are cancelled due to L1D bank conflicts with other load ports.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_C6", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", + "CounterMask": "6", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x48", + "Counter": "2", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", + "CounterMask": "1", + "CounterHTOff": "2" + }, + { + "EventCode": "0x48", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L1D_PEND_MISS.FB_FULL", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4003c0091", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0091", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003c0091", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2003c0091", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoop returned a clean response", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0090", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch data reads that hit the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4003c0090", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0090", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003c0090", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2003c0090", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoop returned a clean response", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c03f7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4003c03f7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c03f7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003c03f7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2003c03f7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoop returned a clean response", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10008", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all writebacks from the core to the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand code reads that hit in the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand data reads that hit in the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4003c0001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003c0001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2003c0001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoop returned a clean response", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x803c8000", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.OTHER.LRU_HINTS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x23ffc08000", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0040", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that hit in the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4003c0010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003c0010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2003c0010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0200", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0080", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4003c0080", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0080", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003c0080", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2003c0080", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10400", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10800", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts non-temporal stores", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00010008", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00010001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand data reads", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00010002", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand rfo's", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00010004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand code reads", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00010008", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x000105B3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch data reads", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00010122", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch prefetch RFOs", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x000107F7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all data/code/rfo references (demand & prefetch)", + "CounterHTOff": "0,1,2,3" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/jaketown/floating-point.json b/tools/perf/pmu-events/arch/x86/jaketown/floating-point.json new file mode 100644 index 000000000000..982eda48785e --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/jaketown/floating-point.json @@ -0,0 +1,138 @@ +[ + { + "EventCode": "0xC1", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "OTHER_ASSISTS.AVX_STORE", + "SampleAfterValue": "100003", + "BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC1", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "OTHER_ASSISTS.AVX_TO_SSE", + "SampleAfterValue": "100003", + "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC1", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "OTHER_ASSISTS.SSE_TO_AVX", + "SampleAfterValue": "100003", + "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xCA", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "FP_ASSIST.X87_OUTPUT", + "SampleAfterValue": "100003", + "BriefDescription": "Number of X87 assists due to output value.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xCA", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "FP_ASSIST.X87_INPUT", + "SampleAfterValue": "100003", + "BriefDescription": "Number of X87 assists due to input value.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xCA", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "FP_ASSIST.SIMD_OUTPUT", + "SampleAfterValue": "100003", + "BriefDescription": "Number of SIMD FP assists due to Output values.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xCA", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "FP_ASSIST.SIMD_INPUT", + "SampleAfterValue": "100003", + "BriefDescription": "Number of SIMD FP assists due to input values.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "FP_COMP_OPS_EXE.X87", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x11", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "SIMD_FP_256.PACKED_SINGLE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of GSSE-256 Computational FP single precision uops issued this cycle.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x11", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "SIMD_FP_256.PACKED_DOUBLE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of AVX-256 Computational FP double precision uops issued this cycle.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xCA", + "Counter": "0,1,2,3", + "UMask": "0x1e", + "EventName": "FP_ASSIST.ANY", + "SampleAfterValue": "100003", + "BriefDescription": "Cycles with any input/output SSE or FP assist.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/jaketown/frontend.json b/tools/perf/pmu-events/arch/x86/jaketown/frontend.json new file mode 100644 index 000000000000..1b7b1dd36c68 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/jaketown/frontend.json @@ -0,0 +1,305 @@ +[ + { + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ICACHE.HIT", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes unchacheable accesses.", + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "ICACHE.MISSES", + "SampleAfterValue": "200003", + "BriefDescription": "Instruction cache, streaming buffer and victim cache misses.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "IDQ.EMPTY", + "SampleAfterValue": "2000003", + "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "IDQ.MITE_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "IDQ.DSB_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "IDQ.MS_DSB_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "IDQ.MS_MITE_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "IDQ.MS_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts cycles during which the microcode sequencer assisted the front-end in delivering uops. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance. See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more information.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "IDQ.MS_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of uops not delivered to the back-end per cycle, per thread, when the back-end was not stalled. In the ideal case 4 uops can be delivered each cycle. The event counts the undelivered uops - so if 3 were delivered in one cycle, the counter would be incremented by 1 for that cycle (4 - 3). If the back-end is stalled, the count for this event is not incremented even when uops were not delivered, because the back-end would not have been able to accept them. This event is used in determining the front-end bound category of the top-down pipeline slots characterization.", + "EventCode": "0x9C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled .", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", + "CounterMask": "3", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xAB", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "DSB2MITE_SWITCHES.COUNT", + "SampleAfterValue": "2000003", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline. It excludes cycles when the back-end cannot accept new micro-ops. The penalty for these switches is potentially several cycles of instruction starvation, where no micro-ops are delivered to the back-end.", + "EventCode": "0xAB", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xAC", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "DSB_FILL.OTHER_CANCEL", + "SampleAfterValue": "2000003", + "BriefDescription": "Cases of cancelling valid DSB fill not because of exceeding way limit.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xAC", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "DSB_FILL.EXCEED_DSB_LINES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "IDQ.MITE_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "IDQ.DSB_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "IDQ.MS_DSB_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EdgeDetect": "1", + "EventName": "IDQ.MS_DSB_OCCUR", + "SampleAfterValue": "2000003", + "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x9C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", + "CounterMask": "2", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with less than 3 uops delivered by the front end.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_GE_1_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when 1 or more uops were delivered to the by the front end.", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x18", + "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x18", + "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x24", + "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles MITE is delivering 4 Uops.", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x24", + "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles MITE is delivering any Uop.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xAC", + "Counter": "0,1,2,3", + "UMask": "0xa", + "EventName": "DSB_FILL.ALL_CANCEL", + "SampleAfterValue": "2000003", + "BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x9C", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x3c", + "EventName": "IDQ.MITE_ALL_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EdgeDetect": "1", + "EventName": "IDQ.MS_SWITCHES", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/jaketown/memory.json b/tools/perf/pmu-events/arch/x86/jaketown/memory.json new file mode 100644 index 000000000000..27e636428f4f --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/jaketown/memory.json @@ -0,0 +1,422 @@ +[ + { + "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers. Machine clears can have a significant performance impact if they are happening frequently.", + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "SampleAfterValue": "100003", + "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "2", + "EventCode": "0xCD", + "MSRValue": "0x4", + "Counter": "3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "SampleAfterValue": "100003", + "BriefDescription": "Loads with latency value being above 4 .", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "EventCode": "0xCD", + "MSRValue": "0x8", + "Counter": "3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "MSRIndex": "0x3F6", + "SampleAfterValue": "50021", + "BriefDescription": "Loads with latency value being above 8.", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "EventCode": "0xCD", + "MSRValue": "0x10", + "Counter": "3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "MSRIndex": "0x3F6", + "SampleAfterValue": "20011", + "BriefDescription": "Loads with latency value being above 16.", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "EventCode": "0xCD", + "MSRValue": "0x20", + "Counter": "3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "MSRIndex": "0x3F6", + "SampleAfterValue": "100007", + "BriefDescription": "Loads with latency value being above 32.", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "EventCode": "0xCD", + "MSRValue": "0x40", + "Counter": "3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "MSRIndex": "0x3F6", + "SampleAfterValue": "2003", + "BriefDescription": "Loads with latency value being above 64.", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "EventCode": "0xCD", + "MSRValue": "0x80", + "Counter": "3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "MSRIndex": "0x3F6", + "SampleAfterValue": "1009", + "BriefDescription": "Loads with latency value being above 128.", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "EventCode": "0xCD", + "MSRValue": "0x100", + "Counter": "3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "MSRIndex": "0x3F6", + "SampleAfterValue": "503", + "BriefDescription": "Loads with latency value being above 256.", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "EventCode": "0xCD", + "MSRValue": "0x200", + "Counter": "3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "MSRIndex": "0x3F6", + "SampleAfterValue": "101", + "BriefDescription": "Loads with latency value being above 512.", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "EventCode": "0xCD", + "Counter": "3", + "UMask": "0x2", + "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).", + "PRECISE_STORE": "1", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "EventCode": "0x05", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MISALIGN_MEM_REF.LOADS", + "SampleAfterValue": "2000003", + "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x05", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MISALIGN_MEM_REF.STORES", + "SampleAfterValue": "2000003", + "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fffc20004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand code reads that miss the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x600400004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from local dram", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x67f800004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from remote dram", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x87f820004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand code reads that miss the LLC and the data forwarded from remote cache", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x107fc00004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand code reads that miss the LLC the data is found in M state in remote cache and forwarded from there", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x67fc00001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote & local dram", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fffc20001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that miss in the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x600400001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from local dram", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x67f800001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote dram", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x87f820001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that miss the LLC and the data forwarded from remote cache", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x107fc00001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that miss the LLC the data is found in M state in remote cache and forwarded from there", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fffc20040", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from remote & local dram", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x67fc00010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote & local dram", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fffc20010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x600400010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from local dram", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x67f800010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote dram", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x87f820010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data forwarded from remote cache", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x107fc00010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC the data is found in M state in remote cache and forwarded from there", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fffc20200", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fffc20080", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x600400077", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all local dram accesses for all demand and L2 prefetches. LLC prefetches are excluded.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3FFFC20077", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "This event counts all LLC misses for all demand and L2 prefetches. LLC prefetches are excluded.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x187FC20077", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.REMOTE_HITM_HIT_FORWARD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "This event counts all remote cache-to-cache transfers (includes HITM and HIT-Forward) for all demand and L2 prefetches. LLC prefetches are excluded.", + "CounterHTOff": "0,1,2,3" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/jaketown/other.json b/tools/perf/pmu-events/arch/x86/jaketown/other.json new file mode 100644 index 000000000000..64b195b82c50 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/jaketown/other.json @@ -0,0 +1,58 @@ +[ + { + "EventCode": "0x17", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "INSTS_WRITTEN_TO_IQ.INSTS", + "SampleAfterValue": "2000003", + "BriefDescription": "Valid instructions written to IQ per cycle.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CPL_CYCLES.RING0", + "SampleAfterValue": "2000003", + "BriefDescription": "Unhalted core cycles when the thread is in ring 0.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EdgeDetect": "1", + "EventName": "CPL_CYCLES.RING0_TRANS", + "SampleAfterValue": "100007", + "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5C", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "CPL_CYCLES.RING123", + "SampleAfterValue": "2000003", + "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x4E", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "HW_PRE_REQ.DL1_MISS", + "SampleAfterValue": "2000003", + "BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x63", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json b/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json new file mode 100644 index 000000000000..8a597e45ed84 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json @@ -0,0 +1,1220 @@ +[ + { + "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. ", + "EventCode": "0x00", + "Counter": "Fixed counter 1", + "UMask": "0x1", + "EventName": "INST_RETIRED.ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Instructions retired from execution.", + "CounterHTOff": "Fixed counter 1" + }, + { + "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. ", + "EventCode": "0x00", + "Counter": "Fixed counter 2", + "UMask": "0x2", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "SampleAfterValue": "2000003", + "BriefDescription": "Core cycles when the thread is not in halt state.", + "CounterHTOff": "Fixed counter 2" + }, + { + "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. ", + "EventCode": "0x00", + "Counter": "Fixed counter 3", + "UMask": "0x3", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "SampleAfterValue": "2000003", + "BriefDescription": "Reference cycles when the core is not in halt state.", + "CounterHTOff": "Fixed counter 3" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x41", + "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Not taken macro-conditional branches.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x81", + "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired macro-conditional branches.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x82", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x84", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x90", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired direct near calls.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xa0", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired indirect calls.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xc1", + "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired macro-conditional branches.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xc2", + "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xc4", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired indirect branches excluding calls and returns.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xc8", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired indirect return branches.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xd0", + "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired direct near calls.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x41", + "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x81", + "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x84", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x88", + "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x90", + "EventName": "BR_MISP_EXEC.TAKEN_DIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired mispredicted direct near calls.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0xa0", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired mispredicted indirect calls.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0xc1", + "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired mispredicted macro conditional branches.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0xc4", + "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "BriefDescription": "Mispredicted indirect branches excluding calls and returns.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0xd0", + "EventName": "BR_MISP_EXEC.ALL_DIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired mispredicted direct near calls.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "SampleAfterValue": "2000003", + "BriefDescription": "Thread cycles when thread is not in halt state.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LSD.UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of Uops delivered by the LSD.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LSD.CYCLES_ACTIVE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x87", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ILD_STALL.LCP", + "SampleAfterValue": "2000003", + "BriefDescription": "Stalls caused by changing prefix length of the instruction.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x87", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "ILD_STALL.IQ_FULL", + "SampleAfterValue": "2000003", + "BriefDescription": "Stall cycles because IQ is full.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0D", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "INT_MISC.RAT_STALL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x59", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP", + "SampleAfterValue": "2000003", + "BriefDescription": "Increments the number of flags-merge uops in flight each cycle.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index reqisters, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructions.", + "EventCode": "0x59", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with at least one slow LEA uop being allocated.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x59", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "PARTIAL_RAT_STALLS.MUL_SINGLE_UOP", + "SampleAfterValue": "2000003", + "BriefDescription": "Multiply packed/scalar single precision uops allocated.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "RESOURCE_STALLS.ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Resource-related stall cycles.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "RESOURCE_STALLS.LB", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts the cycles of stall due to lack of load buffers.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "RESOURCE_STALLS.RS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles stalled due to no eligible RS entry available.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "RESOURCE_STALLS.SB", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "RESOURCE_STALLS.ROB", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles stalled due to re-order buffer full.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5B", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "RESOURCE_STALLS2.BOB_FULL", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when Allocator is stalled if BOB is full and new branch needs it.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of Uops issued by the front-end of the pipeilne to the back-end.", + "EventCode": "0x0E", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_ISSUED.ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0E", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x0E", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x5E", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "RS_EVENTS.EMPTY_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xCC", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", + "SampleAfterValue": "2000003", + "BriefDescription": "Count cases of saving new LBR.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear. Machine clears can have a significant performance impact if they are happening frequently.", + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "MACHINE_CLEARS.SMC", + "SampleAfterValue": "100003", + "BriefDescription": "Self-modifying code (SMC) detected.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.", + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "MACHINE_CLEARS.MASKMOV", + "SampleAfterValue": "100003", + "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC0", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "INST_RETIRED.ANY_P", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of instructions retired. General Counter - architectural event.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "PublicDescription": "This event counts the number of micro-ops retired.", + "EventCode": "0xC2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.ALL", + "SampleAfterValue": "2000003", + "BriefDescription": "Actually retired uops.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "PublicDescription": "This event counts the number of retirement slots used each cycle. There are potentially 4 slots that can be used each cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle. This event is used in determining the 'Retiring' category of the Top-Down pipeline slots characterization.", + "EventCode": "0xC2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "SampleAfterValue": "2000003", + "BriefDescription": "Retirement slots used.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC2", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles without actually retired uops.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC2", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with less than 10 actually retired uops.", + "CounterMask": "10", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BR_INST_RETIRED.CONDITIONAL", + "SampleAfterValue": "400009", + "BriefDescription": "Conditional branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "SampleAfterValue": "100007", + "BriefDescription": "Direct and indirect near call instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "SampleAfterValue": "400009", + "BriefDescription": "All (macro) branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "SampleAfterValue": "100007", + "BriefDescription": "Return instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "BR_INST_RETIRED.NOT_TAKEN", + "SampleAfterValue": "400009", + "BriefDescription": "Not taken branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "SampleAfterValue": "400009", + "BriefDescription": "Taken branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "SampleAfterValue": "100007", + "BriefDescription": "Far branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "2", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", + "SampleAfterValue": "400009", + "BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS).", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BR_MISP_RETIRED.CONDITIONAL", + "SampleAfterValue": "400009", + "BriefDescription": "Mispredicted conditional branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "BR_MISP_RETIRED.NEAR_CALL", + "SampleAfterValue": "100007", + "BriefDescription": "Direct and indirect mispredicted near call instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "SampleAfterValue": "400009", + "BriefDescription": "All mispredicted macro branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "BR_MISP_RETIRED.NOT_TAKEN", + "SampleAfterValue": "400009", + "BriefDescription": "Mispredicted not taken branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "BR_MISP_RETIRED.TAKEN", + "SampleAfterValue": "400009", + "BriefDescription": "Mispredicted taken branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "2", + "PublicDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", + "SampleAfterValue": "400009", + "BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS).", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "OTHER_ASSISTS.ITLB_MISS_RETIRED", + "SampleAfterValue": "100003", + "BriefDescription": "Retired instructions experiencing ITLB misses.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x14", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ARITH.FPU_DIV_ACTIVE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when divider is busy executing divide operations.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of the divide operations executed.", + "EventCode": "0x14", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EdgeDetect": "1", + "EventName": "ARITH.FPU_DIV", + "SampleAfterValue": "100003", + "BriefDescription": "Divide operations executed.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_DISPATCHED.THREAD", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops dispatched per thread.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_DISPATCHED.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops dispatched from any thread.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are dispatched to port 0.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are dispatched to port 1.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are dispatched to port 4.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are dispatched to port 5.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "CYCLE_ACTIVITY.CYCLES_NO_DISPATCH", + "SampleAfterValue": "2000003", + "BriefDescription": "Each cycle there was no dispatch for this thread, increment by 1. Note this is connect to Umask 2. No dispatch can be deduced from the UOPS_EXECUTED event.", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xA3", + "Counter": "2", + "UMask": "0x2", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "Each cycle there was a miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.", + "CounterMask": "2", + "CounterHTOff": "2" + }, + { + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "Each cycle there was a MLC-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA3", + "Counter": "2", + "UMask": "0x6", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "Each cycle there was a miss-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and connected to Umask 1 and 2. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.", + "CounterMask": "6", + "CounterHTOff": "2" + }, + { + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x5", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "Each cycle there was a MLC-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 and 2.", + "CounterMask": "5", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x4C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LOAD_HIT_PRE.SW_PF", + "SampleAfterValue": "100003", + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x4C", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "LOAD_HIT_PRE.HW_PF", + "SampleAfterValue": "100003", + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x03", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LD_BLOCKS.DATA_UNKNOWN", + "SampleAfterValue": "100003", + "BriefDescription": "Loads delayed due to SB blocks, preceding store operations with known addresses but unknown data.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceeding smaller uncompleted store. See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.", + "EventCode": "0x03", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "SampleAfterValue": "100003", + "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x03", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "LD_BLOCKS.NO_SR", + "SampleAfterValue": "100003", + "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x03", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "LD_BLOCKS.ALL_BLOCK", + "SampleAfterValue": "100003", + "BriefDescription": "Number of cases where any load ends up with a valid block-code written to the load buffer (including blocks due to Memory Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K. This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline. The enhanced address check typically has a performance penalty of 5 cycles.", + "EventCode": "0x07", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "SampleAfterValue": "100003", + "BriefDescription": "False dependencies in MOB due to partial compare.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x07", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "LD_BLOCKS_PARTIAL.ALL_STA_BLOCK", + "SampleAfterValue": "100003", + "BriefDescription": "This event counts the number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB6", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "AGU_BYPASS_CANCEL.COUNT", + "SampleAfterValue": "100003", + "BriefDescription": "This event counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in an.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", + "SampleAfterValue": "2000003", + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "2000003", + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other is halted.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when uops are dispatched to port 0.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "AnyThread": "1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when uops are dispatched to port 1.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x40", + "AnyThread": "1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when uops are dispatched to port 4.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x80", + "AnyThread": "1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when uops are dispatched to port 5.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0xc", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 2.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0xc", + "AnyThread": "1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 2.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x30", + "AnyThread": "1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "2", + "EventCode": "0xC0", + "Counter": "1", + "UMask": "0x1", + "EventName": "INST_RETIRED.PREC_DIST", + "SampleAfterValue": "2000003", + "BriefDescription": "Instructions retired. (Precise Event - PEBS).", + "TakenAlone": "1", + "CounterHTOff": "1" + }, + { + "EventCode": "0x5B", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "RESOURCE_STALLS2.ALL_PRF_CONTROL", + "SampleAfterValue": "2000003", + "BriefDescription": "Resource stalls2 control structures full for physical registers.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5B", + "Counter": "0,1,2,3", + "UMask": "0xc", + "EventName": "RESOURCE_STALLS2.ALL_FL_EMPTY", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with either free list is empty.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0xe", + "EventName": "RESOURCE_STALLS.MEM_RS", + "SampleAfterValue": "2000003", + "BriefDescription": "Resource stalls due to memory buffers or Reservation Station (RS) being fully utilized.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0xf0", + "EventName": "RESOURCE_STALLS.OOO_RSRC", + "SampleAfterValue": "2000003", + "BriefDescription": "Resource stalls due to Rob being full, FCSW, MXCSR and OTHER.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5B", + "Counter": "0,1,2,3", + "UMask": "0x4f", + "EventName": "RESOURCE_STALLS2.OOO_RSRC", + "SampleAfterValue": "2000003", + "BriefDescription": "Resource stalls out of order resources full.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0xa", + "EventName": "RESOURCE_STALLS.LB_SB", + "SampleAfterValue": "2000003", + "BriefDescription": "Resource stalls due to load or store buffers all being in use.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0D", + "Counter": "0,1,2,3", + "UMask": "0x3", + "EventName": "INT_MISC.RECOVERY_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...).", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of cycles spent executing performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For more details, See the Intel? 64 and IA-32 Architectures Optimization Reference Manual.", + "EventCode": "0x59", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Performance sensitive flags-merging uops added by Sandy Bridge u-arch.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0D", + "Counter": "0,1,2,3", + "UMask": "0x3", + "EdgeDetect": "1", + "EventName": "INT_MISC.RECOVERY_STALLS_COUNT", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...).", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xE6", + "Counter": "0,1,2,3", + "UMask": "0x1f", + "EventName": "BACLEARS.ANY", + "SampleAfterValue": "100003", + "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xff", + "EventName": "BR_INST_EXEC.ALL_BRANCHES", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired branches.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0xff", + "EventName": "BR_MISP_EXEC.ALL_BRANCHES", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired mispredicted macro conditional branches.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC2", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles without actually retired uops.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xA8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LSD.CYCLES_4_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xc3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EdgeDetect": "1", + "EventName": "MACHINE_CLEARS.COUNT", + "SampleAfterValue": "100003", + "BriefDescription": "Number of machine clears (nukes) of any type.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5E", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EdgeDetect": "1", + "EventName": "RS_EVENTS.EMPTY_END", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x00", + "Counter": "Fixed counter 2", + "UMask": "0x2", + "AnyThread": "1", + "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "CounterHTOff": "Fixed counter 2" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x0", + "AnyThread": "1", + "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0D", + "Counter": "0,1,2,3", + "UMask": "0x3", + "AnyThread": "1", + "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", + "CounterMask": "2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", + "CounterMask": "3", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "SampleAfterValue": "2000003", + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "2000003", + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/jaketown/virtual-memory.json b/tools/perf/pmu-events/arch/x86/jaketown/virtual-memory.json new file mode 100644 index 000000000000..a654ab771fce --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/jaketown/virtual-memory.json @@ -0,0 +1,149 @@ +[ + { + "EventCode": "0xAE", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ITLB.ITLB_FLUSH", + "SampleAfterValue": "100007", + "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x4F", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "EPT.WALK_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", + "SampleAfterValue": "100003", + "BriefDescription": "Misses at all ITLB levels that cause page walks.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "SampleAfterValue": "100003", + "BriefDescription": "Misses in all ITLB levels that cause completed page walks.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses.", + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "ITLB_MISSES.WALK_DURATION", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when PMH is busy with page walks.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "ITLB_MISSES.STLB_HIT", + "SampleAfterValue": "100003", + "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", + "SampleAfterValue": "100003", + "BriefDescription": "Load misses in all DTLB levels that cause page walks.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "SampleAfterValue": "100003", + "BriefDescription": "Load misses at all DTLB levels that cause completed page walks.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.", + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when PMH is busy with page walks.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts load operations that miss the first DTLB level but hit the second and do not cause any page walks. The penalty in this case is approximately 7 cycles.", + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "SampleAfterValue": "100003", + "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", + "SampleAfterValue": "100003", + "BriefDescription": "Store misses in all DTLB levels that cause page walks.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "SampleAfterValue": "100003", + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "DTLB_STORE_MISSES.WALK_DURATION", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when PMH is busy with page walks.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "SampleAfterValue": "100003", + "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xBD", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "TLB_FLUSH.DTLB_THREAD", + "SampleAfterValue": "100007", + "BriefDescription": "DTLB flush attempts of the thread-specific entries.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xBD", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "TLB_FLUSH.STLB_ANY", + "SampleAfterValue": "100007", + "BriefDescription": "STLB flush attempts.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/cache.json b/tools/perf/pmu-events/arch/x86/knightslanding/cache.json new file mode 100644 index 000000000000..88ba5994b994 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/knightslanding/cache.json @@ -0,0 +1,2305 @@ +[ + { + "EventCode": "0x30", + "Counter": "0,1", + "UMask": "0x0", + "EventName": "L2_REQUESTS_REJECT.ALL", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of MEC requests from the L2Q that reference a cache line (cacheable requests) exlcuding SW prefetches filling only to L2 cache and L1 evictions (automatically exlcudes L2HWP, UC, WC) that were rejected - Multiple repeated rejects should be counted multiple times" + }, + { + "EventCode": "0x31", + "Counter": "0,1", + "UMask": "0x0", + "EventName": "CORE_REJECT_L2Q.ALL", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of MEC requests that were not accepted into the L2Q because of any L2 queue reject condition. There is no concept of at-ret here. It might include requests due to instructions in the speculative path." + }, + { + "EventCode": "0x2E", + "Counter": "0,1", + "UMask": "0x4f", + "EventName": "L2_REQUESTS.REFERENCE", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the total number of L2 cache references." + }, + { + "EventCode": "0x2E", + "Counter": "0,1", + "UMask": "0x41", + "EventName": "L2_REQUESTS.MISS", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of L2 cache misses" + }, + { + "PublicDescription": "This event counts the number of core cycles the fetch stalls because of an icache miss. This is a cumulative count of cycles the NIP stalled for all icache misses. ", + "EventCode": "0x86", + "Counter": "0,1", + "UMask": "0x4", + "EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of core cycles the fetch stalls because of an icache miss. This is a cummulative count of core cycles the fetch stalled for all icache misses. " + }, + { + "PublicDescription": "This event counts the number of load micro-ops retired that miss in L1 Data cache. Note that prefetch misses will not be counted. ", + "EventCode": "0x04", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "MEM_UOPS_RETIRED.L1_MISS_LOADS", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of load micro-ops retired that miss in L1 D cache" + }, + { + "PEBS": "1", + "EventCode": "0x04", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "MEM_UOPS_RETIRED.L2_HIT_LOADS", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of load micro-ops retired that hit in the L2", + "Data_LA": "1" + }, + { + "PEBS": "1", + "EventCode": "0x04", + "Counter": "0,1", + "UMask": "0x4", + "EventName": "MEM_UOPS_RETIRED.L2_MISS_LOADS", + "SampleAfterValue": "100007", + "BriefDescription": "Counts the number of load micro-ops retired that miss in the L2", + "Data_LA": "1" + }, + { + "EventCode": "0x04", + "Counter": "0,1", + "UMask": "0x10", + "EventName": "MEM_UOPS_RETIRED.UTLB_MISS_LOADS", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of load micro-ops retired that caused micro TLB miss" + }, + { + "PEBS": "1", + "EventCode": "0x04", + "Counter": "0,1", + "UMask": "0x20", + "EventName": "MEM_UOPS_RETIRED.HITM", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the loads retired that get the data from the other core in the same tile in M state", + "Data_LA": "1" + }, + { + "PublicDescription": "This event counts the number of load micro-ops retired.", + "EventCode": "0x04", + "Counter": "0,1", + "UMask": "0x40", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "SampleAfterValue": "200003", + "BriefDescription": "Counts all the load micro-ops retired" + }, + { + "PublicDescription": "This event counts the number of store micro-ops retired.", + "EventCode": "0x04", + "Counter": "0,1", + "UMask": "0x80", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "SampleAfterValue": "200003", + "BriefDescription": "Counts all the store micro-ops retired" + }, + { + "EventCode": "0xB7", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE", + "SampleAfterValue": "100007", + "BriefDescription": "Counts the matrix events specified by MSR_OFFCORE_RESPx" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4000000070 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.OUTSTANDING", + "MSRIndex": "0x1a6", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any Prefetch requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000400070 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_FAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0800400070 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_FAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000080070 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_NEAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0800080070 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_NEAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000010070 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any Prefetch requests that accounts for any response", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x40000032f7 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_READ.OUTSTANDING", + "MSRIndex": "0x1a6", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any Read request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x10004032f7 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_FAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any Read request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x08004032f7 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_FAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any Read request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x10000832f7 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_NEAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any Read request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x08000832f7 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_NEAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any Read request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x00000132f7 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_READ.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any Read request that accounts for any response", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4000000044 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand code reads and prefetch code read requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000400044 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_FAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0800400044 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_FAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000080044 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_NEAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0800080044 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_NEAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000010044 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for any response", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4000000022 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.OUTSTANDING", + "MSRIndex": "0x1a6", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data write requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000400022 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_FAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0800400022 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_FAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000080022 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_NEAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0800080022 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_NEAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000010022 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data write requests that accounts for any response", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4000003091 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000403091 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_FAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0800403091 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_FAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000083091 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_NEAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0800083091 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_NEAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000013091 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for any response", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4000008000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.OUTSTANDING", + "MSRIndex": "0x1a6", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000408000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_FAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0800408000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_FAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000088000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_NEAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0800088000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_NEAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000018000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any request that accounts for any response", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000014800 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", + "MSRIndex": "0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts all streaming stores (WC and should be programmed on PMC1) that accounts for any response", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000014000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.ANY_RESPONSE", + "MSRIndex": "0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Partial streaming stores (WC and should be programmed on PMC1) that accounts for any response", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4000002000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L1 data HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000402000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_FAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0800402000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_FAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000082000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_NEAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0800082000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_NEAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000012000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L1 data HW prefetches that accounts for any response", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4000001000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.OUTSTANDING", + "MSRIndex": "0x1a6", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Software Prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000401000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_FAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0800401000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_FAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000081000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_NEAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0800081000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_NEAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000011000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Software Prefetches that accounts for any response", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000010800 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Full streaming stores (WC and should be programmed on PMC1) that accounts for any response", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4000000400 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.OUTSTANDING", + "MSRIndex": "0x1a6", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Bus locks and split lock requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000400400 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_FAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0800400400 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_FAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000080400 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_NEAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0800080400 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_NEAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000010400 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Bus locks and split lock requests that accounts for any response", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4000000200 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.OUTSTANDING", + "MSRIndex": "0x1a6", + "SampleAfterValue": "100007", + "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000400200 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_FAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0800400200 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_FAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000080200 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_NEAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0800080200 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_NEAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000010200 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for any response", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000400100 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_FAR_TILE_M", + "MSRIndex": "0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0800400100 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_FAR_TILE_E_F", + "MSRIndex": "0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000080100 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_NEAR_TILE_M", + "MSRIndex": "0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0800080100 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_NEAR_TILE_E_F", + "MSRIndex": "0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000010100 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.ANY_RESPONSE", + "MSRIndex": "0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for any response", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4000000080 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.OUTSTANDING", + "MSRIndex": "0x1a6", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000400080 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_FAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0800400080 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_FAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000080080 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_NEAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0800080080 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_NEAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000010080 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for any response", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4000000040 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L2 code HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000400040 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_FAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0800400040 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_FAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000080040 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_NEAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0800080040 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_NEAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000010040 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L2 code HW prefetches that accounts for any response", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000400020 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_FAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0800400020 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_FAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000080020 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_NEAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0800080020 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_NEAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000020020 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that provides no supplier details", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000010020 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for any response", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4000000004 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand code reads and prefetch code reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000400004 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_FAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0800400004 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_FAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000080004 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_NEAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0800080004 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_NEAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000010004 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for any response", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4000000002 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING", + "MSRIndex": "0x1a6", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data writes that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000400002 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_FAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0800400002 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_FAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000080002 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_NEAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0800080002 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_NEAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000010002 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data writes that accounts for any response", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4000000001 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000400001 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_FAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0800400001 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_FAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000080001 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_NEAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0800080001 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_NEAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000010001 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for any response", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0002000001 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_THIS_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in M state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0002000002 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_THIS_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in M state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0002000004 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_THIS_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in M state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0002000020 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_THIS_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in M state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0002000080 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_THIS_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses which hit its own tile's L2 with data in M state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0002000100 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_THIS_TILE_M", + "MSRIndex": "0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in M state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0002000200 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_THIS_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses which hit its own tile's L2 with data in M state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0002000400 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_THIS_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in M state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0002001000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_THIS_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in M state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0002002000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_THIS_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in M state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0002008000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_THIS_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any request that accounts for responses which hit its own tile's L2 with data in M state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0002003091 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_THIS_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses which hit its own tile's L2 with data in M state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0002000022 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_THIS_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data write requests that accounts for responses which hit its own tile's L2 with data in M state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0002000044 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_THIS_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses which hit its own tile's L2 with data in M state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x00020032f7 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_THIS_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any Read request that accounts for responses which hit its own tile's L2 with data in M state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0002000070 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_THIS_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in M state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0004000001 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_THIS_TILE_E", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in E state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0004000002 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_THIS_TILE_E", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in E state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0004000004 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_THIS_TILE_E", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in E state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0004000020 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_THIS_TILE_E", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in E state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0004000040 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_THIS_TILE_E", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L2 code HW prefetches that accounts for responses which hit its own tile's L2 with data in E state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0004000080 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_THIS_TILE_E", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses which hit its own tile's L2 with data in E state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0004000100 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_THIS_TILE_E", + "MSRIndex": "0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in E state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0004000200 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_THIS_TILE_E", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses which hit its own tile's L2 with data in E state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0004000400 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_THIS_TILE_E", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in E state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0004001000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_THIS_TILE_E", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in E state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0004002000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_THIS_TILE_E", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in E state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0004008000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_THIS_TILE_E", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any request that accounts for responses which hit its own tile's L2 with data in E state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0004003091 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_THIS_TILE_E", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses which hit its own tile's L2 with data in E state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0004000022 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_THIS_TILE_E", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data write requests that accounts for responses which hit its own tile's L2 with data in E state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0004000044 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_THIS_TILE_E", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses which hit its own tile's L2 with data in E state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x00040032f7 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_THIS_TILE_E", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any Read request that accounts for responses which hit its own tile's L2 with data in E state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0004000070 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_THIS_TILE_E", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in E state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0008000001 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_THIS_TILE_S", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in S state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0008000002 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_THIS_TILE_S", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in S state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0008000004 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_THIS_TILE_S", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in S state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0008000020 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_THIS_TILE_S", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in S state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0008000080 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_THIS_TILE_S", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses which hit its own tile's L2 with data in S state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0008000100 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_THIS_TILE_S", + "MSRIndex": "0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in S state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0008000200 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_THIS_TILE_S", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses which hit its own tile's L2 with data in S state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0008000400 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_THIS_TILE_S", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in S state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0008001000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_THIS_TILE_S", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in S state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0008002000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_THIS_TILE_S", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in S state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0008008000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_THIS_TILE_S", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any request that accounts for responses which hit its own tile's L2 with data in S state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0008003091 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_THIS_TILE_S", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses which hit its own tile's L2 with data in S state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0008000022 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_THIS_TILE_S", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data write requests that accounts for responses which hit its own tile's L2 with data in S state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0008000044 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_THIS_TILE_S", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses which hit its own tile's L2 with data in S state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x00080032f7 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_THIS_TILE_S", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any Read request that accounts for responses which hit its own tile's L2 with data in S state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0010000001 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_THIS_TILE_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in F state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0010000002 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_THIS_TILE_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in F state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0010000004 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_THIS_TILE_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in F state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0010000020 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_THIS_TILE_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in F state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0010000040 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_THIS_TILE_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L2 code HW prefetches that accounts for responses which hit its own tile's L2 with data in F state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0010000080 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_THIS_TILE_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses which hit its own tile's L2 with data in F state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0010000100 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_THIS_TILE_F", + "MSRIndex": "0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in F state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0010000200 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_THIS_TILE_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses which hit its own tile's L2 with data in F state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0010000400 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_THIS_TILE_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in F state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0010001000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_THIS_TILE_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in F state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0010002000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_THIS_TILE_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in F state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0010008000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_THIS_TILE_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any request that accounts for responses which hit its own tile's L2 with data in F state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0010003091 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_THIS_TILE_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses which hit its own tile's L2 with data in F state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0010000022 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_THIS_TILE_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data write requests that accounts for responses which hit its own tile's L2 with data in F state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0010000044 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_THIS_TILE_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses which hit its own tile's L2 with data in F state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x00100032f7 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_THIS_TILE_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any Read request that accounts for responses which hit its own tile's L2 with data in F state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0010000070 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_THIS_TILE_F", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in F state ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1800180002 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_NEAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data writes that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1800180004 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_NEAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1800180020 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_NEAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1800180040 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_NEAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L2 code HW prefetches that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1800180080 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_NEAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1800180100 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_NEAR_TILE", + "MSRIndex": "0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1800180200 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_NEAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1800180400 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_NEAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Bus locks and split lock requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1800181000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_NEAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Software Prefetches that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1800182000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_NEAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L1 data HW prefetches that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1800188000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_NEAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any request that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1800183091 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_NEAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1800180022 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_NEAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data write requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1800180044 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_NEAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x18001832f7 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_NEAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any Read request that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1800180070 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_NEAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any Prefetch requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1800400002 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_FAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data writes that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1800400004 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_FAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1800400040 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_FAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L2 code HW prefetches that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1800400080 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_FAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1800400100 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_FAR_TILE", + "MSRIndex": "0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1800400400 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_FAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Bus locks and split lock requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1800401000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_FAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Software Prefetches that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1800402000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_FAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L1 data HW prefetches that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1800408000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_FAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any request that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1800403091 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_FAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1800400022 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_FAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data write requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1800400044 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_FAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x18004032f7 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_FAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any Read request that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1800400070 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_FAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any Prefetch requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "Offcore": "1" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/frontend.json b/tools/perf/pmu-events/arch/x86/knightslanding/frontend.json new file mode 100644 index 000000000000..6d38636689a4 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/knightslanding/frontend.json @@ -0,0 +1,34 @@ +[ + { + "EventCode": "0x80", + "Counter": "0,1", + "UMask": "0x3", + "EventName": "ICACHE.ACCESSES", + "SampleAfterValue": "200003", + "BriefDescription": "Counts all instruction fetches, including uncacheable fetches." + }, + { + "EventCode": "0x80", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "ICACHE.HIT", + "SampleAfterValue": "200003", + "BriefDescription": "Counts all instruction fetches that hit the instruction cache." + }, + { + "EventCode": "0x80", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "ICACHE.MISSES", + "SampleAfterValue": "200003", + "BriefDescription": "Counts all instruction fetches that miss the instruction cache or produce memory requests. An instruction fetch miss is counted only once and not once for every cycle it is outstanding." + }, + { + "EventCode": "0xE7", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "MS_DECODED.MS_ENTRY", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of times the MSROM starts a flow of uops." + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/memory.json b/tools/perf/pmu-events/arch/x86/knightslanding/memory.json new file mode 100644 index 000000000000..700652566200 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/knightslanding/memory.json @@ -0,0 +1,1110 @@ +[ + { + "EventCode": "0xC3", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of times the machine clears due to memory ordering hazards" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0100400070 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM_FAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any Prefetch requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0080200070 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any Prefetch requests that accounts for data responses from MCDRAM Local.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0101000070 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.DDR_FAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any Prefetch requests that accounts for data responses from DRAM Far. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0080800070 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.DDR_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any Prefetch requests that accounts for data responses from DRAM Local.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x01004032f7 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM_FAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any Read request that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x00802032f7 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any Read request that accounts for data responses from MCDRAM Local.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x01010032f7 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_READ.DDR_FAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any Read request that accounts for data responses from DRAM Far. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x00808032f7 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_READ.DDR_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any Read request that accounts for data responses from DRAM Local.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0100400044 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM_FAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0080200044 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for data responses from MCDRAM Local.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0101000044 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR_FAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for data responses from DRAM Far. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0080800044 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for data responses from DRAM Local.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0100400022 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM_FAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0080200022 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses from MCDRAM Local.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0101000022 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR_FAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses from DRAM Far. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0080800022 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses from DRAM Local.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0100403091 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM_FAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0080203091 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from MCDRAM Local.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0101003091 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR_FAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from DRAM Far. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0080803091 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from DRAM Local.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0100408000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM_FAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any request that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0080208000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any request that accounts for data responses from MCDRAM Local.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0101008000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR_FAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any request that accounts for data responses from DRAM Far. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0080808000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any request that accounts for data responses from DRAM Local.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0100402000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.MCDRAM_FAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0080202000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.MCDRAM_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from MCDRAM Local.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0101002000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR_FAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from DRAM Far. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0080802000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from DRAM Local.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0100401000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM_FAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Software Prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0080201000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Software Prefetches that accounts for data responses from MCDRAM Local.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0101001000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR_FAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Software Prefetches that accounts for data responses from DRAM Far. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0080801000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Software Prefetches that accounts for data responses from DRAM Local.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0100400400 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM_FAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0080200400 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Local.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0101000400 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR_FAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from DRAM Far. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0080800400 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from DRAM Local.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0100400200 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM_FAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0080200200 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from MCDRAM Local.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0101000200 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR_FAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from DRAM Far. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0080800200 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from DRAM Local.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0100400100 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM_FAR", + "MSRIndex": "0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0080200100 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM_NEAR", + "MSRIndex": "0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Local.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0101000100 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.DDR_FAR", + "MSRIndex": "0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Far. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0080800100 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.DDR_NEAR", + "MSRIndex": "0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Local.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2000020080 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from any NON_DRAM system address. This includes MMIO transactions", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0100400080 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM_FAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0080200080 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from MCDRAM Local.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0101000080 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR_FAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from DRAM Far. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0080800080 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from DRAM Local.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0100400040 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.MCDRAM_FAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0080200040 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.MCDRAM_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from MCDRAM Local.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0101000040 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR_FAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from DRAM Far. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0080800040 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from DRAM Local.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2000020020 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from any NON_DRAM system address. This includes MMIO transactions", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0100400020 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM_FAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0080200020 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Local.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0101000020 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR_FAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Far. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0080800020 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Local.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0100400004 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM_FAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0080200004 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Local.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0101000004 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR_FAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Far. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0080800004 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Local.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0100400002 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM_FAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0080200002 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from MCDRAM Local.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0101000002 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR_FAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from DRAM Far. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0080800002 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from DRAM Local.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0100400001 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM_FAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0080200001 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Local.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0101000001 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR_FAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Far. ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0080800001 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Local.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0180600001 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from MCDRAM (local and far)", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0180600002 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data writes that accounts for responses from MCDRAM (local and far)", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0180600004 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from MCDRAM (local and far)", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0180600020 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from MCDRAM (local and far)", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0180600080 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from MCDRAM (local and far)", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0180600100 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM", + "MSRIndex": "0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from MCDRAM (local and far)", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0180600200 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses from MCDRAM (local and far)", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0180600400 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from MCDRAM (local and far)", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0180601000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Software Prefetches that accounts for responses from MCDRAM (local and far)", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0180608000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any request that accounts for responses from MCDRAM (local and far)", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0180603091 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from MCDRAM (local and far)", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0180600022 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from MCDRAM (local and far)", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0180600044 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from MCDRAM (local and far)", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x01806032f7 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any Read request that accounts for responses from MCDRAM (local and far)", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0180600070 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any Prefetch requests that accounts for responses from MCDRAM (local and far)", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0181800001 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from DDR (local and far)", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0181800002 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data writes that accounts for responses from DDR (local and far)", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0181800004 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from DDR (local and far)", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0181800020 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from DDR (local and far)", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0181800040 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L2 code HW prefetches that accounts for responses from DDR (local and far)", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0181800080 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from DDR (local and far)", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0181800200 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses from DDR (local and far)", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0181800400 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from DDR (local and far)", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0181801000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Software Prefetches that accounts for responses from DDR (local and far)", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0181802000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts L1 data HW prefetches that accounts for responses from DDR (local and far)", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0181808000 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any request that accounts for responses from DDR (local and far)", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0181803091 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from DDR (local and far)", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0181800022 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from DDR (local and far)", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0181800044 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from DDR (local and far)", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x01818032f7 ", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_READ.DDR", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any Read request that accounts for responses from DDR (local and far)", + "Offcore": "1" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/pipeline.json b/tools/perf/pmu-events/arch/x86/knightslanding/pipeline.json new file mode 100644 index 000000000000..bb5494cfb5ae --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/knightslanding/pipeline.json @@ -0,0 +1,435 @@ +[ + { + "PEBS": "1", + "EventCode": "0xC4", + "Counter": "0,1", + "UMask": "0x0", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of branch instructions retired" + }, + { + "PEBS": "1", + "EventCode": "0xC4", + "Counter": "0,1", + "UMask": "0x7e", + "EventName": "BR_INST_RETIRED.JCC", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of branch instructions retired that were conditional jumps." + }, + { + "PEBS": "1", + "EventCode": "0xC4", + "Counter": "0,1", + "UMask": "0xfe", + "EventName": "BR_INST_RETIRED.TAKEN_JCC", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of branch instructions retired that were conditional jumps and predicted taken." + }, + { + "PEBS": "1", + "EventCode": "0xC4", + "Counter": "0,1", + "UMask": "0xf9", + "EventName": "BR_INST_RETIRED.CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of near CALL branch instructions retired." + }, + { + "PEBS": "1", + "EventCode": "0xC4", + "Counter": "0,1", + "UMask": "0xfd", + "EventName": "BR_INST_RETIRED.REL_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of near relative CALL branch instructions retired." + }, + { + "PEBS": "1", + "EventCode": "0xC4", + "Counter": "0,1", + "UMask": "0xfb", + "EventName": "BR_INST_RETIRED.IND_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of near indirect CALL branch instructions retired." + }, + { + "PEBS": "1", + "EventCode": "0xC4", + "Counter": "0,1", + "UMask": "0xf7", + "EventName": "BR_INST_RETIRED.RETURN", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of near RET branch instructions retired." + }, + { + "PEBS": "1", + "EventCode": "0xC4", + "Counter": "0,1", + "UMask": "0xeb", + "EventName": "BR_INST_RETIRED.NON_RETURN_IND", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of branch instructions retired that were near indirect CALL or near indirect JMP." + }, + { + "PEBS": "1", + "EventCode": "0xC4", + "Counter": "0,1", + "UMask": "0xbf", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of far branch instructions retired." + }, + { + "PEBS": "1", + "EventCode": "0xC5", + "Counter": "0,1", + "UMask": "0x0", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of mispredicted branch instructions retired" + }, + { + "PEBS": "1", + "EventCode": "0xC5", + "Counter": "0,1", + "UMask": "0x7e", + "EventName": "BR_MISP_RETIRED.JCC", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of mispredicted branch instructions retired that were conditional jumps." + }, + { + "PEBS": "1", + "EventCode": "0xC5", + "Counter": "0,1", + "UMask": "0xfe", + "EventName": "BR_MISP_RETIRED.TAKEN_JCC", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of mispredicted branch instructions retired that were conditional jumps and predicted taken." + }, + { + "PEBS": "1", + "EventCode": "0xC5", + "Counter": "0,1", + "UMask": "0xfb", + "EventName": "BR_MISP_RETIRED.IND_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of mispredicted near indirect CALL branch instructions retired." + }, + { + "PEBS": "1", + "EventCode": "0xC5", + "Counter": "0,1", + "UMask": "0xf7", + "EventName": "BR_MISP_RETIRED.RETURN", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of mispredicted near RET branch instructions retired." + }, + { + "PEBS": "1", + "EventCode": "0xC5", + "Counter": "0,1", + "UMask": "0xeb", + "EventName": "BR_MISP_RETIRED.NON_RETURN_IND", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of mispredicted branch instructions retired that were near indirect CALL or near indirect JMP." + }, + { + "PublicDescription": "This event counts the number of micro-ops retired that were supplied from MSROM.", + "EventCode": "0xC2", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.MS", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts the number of micro-ops retired that are from the complex flows issued by the micro-sequencer (MS)." + }, + { + "PublicDescription": "This event counts the number of micro-ops (uops) retired. The processor decodes complex macro instructions into a sequence of simpler uops. Most instructions are composed of one or two uops. Some instructions are decoded into longer sequences such as repeat instructions, floating point transcendental instructions, and assists. ", + "EventCode": "0xC2", + "Counter": "0,1", + "UMask": "0x10", + "EventName": "UOPS_RETIRED.ALL", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts the number of micro-ops retired" + }, + { + "PublicDescription": "This event counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops retired (floating point, integer and store) except for loads (memory-to-register mov-type micro ops), division, sqrt.", + "EventCode": "0xC2", + "Counter": "0,1", + "UMask": "0x20", + "EventName": "UOPS_RETIRED.SCALAR_SIMD", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops retired. More specifically, it counts scalar SSE, AVX, AVX2, AVX-512 micro-ops except for loads (memory-to-register mov-type micro ops), division, sqrt." + }, + { + "PublicDescription": "This event counts the number of packed vector SSE, AVX, AVX2, and AVX-512 micro-ops retired (floating point, integer and store) except for loads (memory-to-register mov-type micro-ops), packed byte and word multiplies.", + "EventCode": "0xC2", + "Counter": "0,1", + "UMask": "0x40", + "EventName": "UOPS_RETIRED.PACKED_SIMD", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of vector SSE, AVX, AVX2, AVX-512 micro-ops retired. More specifically, it counts packed SSE, AVX, AVX2, AVX-512 micro-ops (both floating point and integer) except for loads (memory-to-register mov-type micro-ops), packed byte and word multiplies." + }, + { + "EventCode": "0xC3", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "MACHINE_CLEARS.SMC", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of times that the machine clears due to program modifying data within 1K of a recently fetched code page" + }, + { + "PublicDescription": "This event counts the number of times that the pipeline stalled due to FP operations needing assists.", + "EventCode": "0xC3", + "Counter": "0,1", + "UMask": "0x4", + "EventName": "MACHINE_CLEARS.FP_ASSIST", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of floating operations retired that required microcode assists" + }, + { + "EventCode": "0xC3", + "Counter": "0,1", + "UMask": "0x8", + "EventName": "MACHINE_CLEARS.ALL", + "SampleAfterValue": "200003", + "BriefDescription": "Counts all nukes" + }, + { + "EventCode": "0xCA", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "NO_ALLOC_CYCLES.ROB_FULL", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of core cycles when no micro-ops are allocated and the ROB is full" + }, + { + "PublicDescription": "This event counts the number of core cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted branch to retire.", + "EventCode": "0xCA", + "Counter": "0,1", + "UMask": "0x4", + "EventName": "NO_ALLOC_CYCLES.MISPREDICTS", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of core cycles when no micro-ops are allocated and the alloc pipe is stalled waiting for a mispredicted branch to retire." + }, + { + "EventCode": "0xCA", + "Counter": "0,1", + "UMask": "0x20", + "EventName": "NO_ALLOC_CYCLES.RAT_STALL", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of core cycles when no micro-ops are allocated and a RATstall (caused by reservation station full) is asserted. " + }, + { + "PublicDescription": "This event counts the number of core cycles when no uops are allocated, the instruction queue is empty and the alloc pipe is stalled waiting for instructions to be fetched.", + "EventCode": "0xCA", + "Counter": "0,1", + "UMask": "0x90", + "EventName": "NO_ALLOC_CYCLES.NOT_DELIVERED", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of core cycles when no micro-ops are allocated, the IQ is empty, and no other condition is blocking allocation." + }, + { + "EventCode": "0xCA", + "Counter": "0,1", + "UMask": "0x7f", + "EventName": "NO_ALLOC_CYCLES.ALL", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the total number of core cycles when no micro-ops are allocated for any reason." + }, + { + "EventCode": "0xCB", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "RS_FULL_STALL.MEC", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of core cycles when allocation pipeline is stalled and is waiting for a free MEC reservation station entry." + }, + { + "EventCode": "0xCB", + "Counter": "0,1", + "UMask": "0x1f", + "EventName": "RS_FULL_STALL.ALL", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the total number of core cycles the Alloc pipeline is stalled when any one of the reservation stations is full. " + }, + { + "EventCode": "0xC0", + "Counter": "0,1", + "UMask": "0x0", + "EventName": "INST_RETIRED.ANY_P", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts the total number of instructions retired" + }, + { + "PublicDescription": "This event counts cycles when the divider is busy. More specifically cycles when the divide unit is unable to accept a new divide uop because it is busy processing a previously dispatched uop. The cycles will be counted irrespective of whether or not another divide uop is waiting to enter the divide unit (from the RS). This event counts integer divides, x87 divides, divss, divsd, sqrtss, sqrtsd event and does not count vector divides.", + "EventCode": "0xCD", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "CYCLES_DIV_BUSY.ALL", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles the number of core cycles when divider is busy. Does not imply a stall waiting for the divider. " + }, + { + "PublicDescription": "This event counts the number of instructions that retire. For instructions that consist of multiple micro-ops, this event counts exactly once, as the last micro-op of the instruction retires. The event continues counting while instructions retire, including during interrupt service routines caused by hardware interrupts, faults or traps.", + "EventCode": "0x00", + "Counter": "Fixed counter 1", + "UMask": "0x1", + "EventName": "INST_RETIRED.ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Fixed Counter: Counts the number of instructions retired" + }, + { + "EventCode": "0x3C", + "Counter": "0,1", + "UMask": "0x0", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts the number of unhalted core clock cycles" + }, + { + "EventCode": "0x3C", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "CPU_CLK_UNHALTED.REF", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts the number of unhalted reference clock cycles" + }, + { + "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter\r\n", + "EventCode": "0x00", + "Counter": "Fixed counter 2", + "UMask": "0x2", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "SampleAfterValue": "2000003", + "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles" + }, + { + "EventCode": "0x00", + "Counter": "Fixed counter 3", + "UMask": "0x3", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "SampleAfterValue": "2000003", + "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles" + }, + { + "EventCode": "0xE6", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "BACLEARS.ALL", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of times the front end resteers for any branch as a result of another branch handling mechanism in the front end." + }, + { + "EventCode": "0xE6", + "Counter": "0,1", + "UMask": "0x8", + "EventName": "BACLEARS.RETURN", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of times the front end resteers for RET branches as a result of another branch handling mechanism in the front end." + }, + { + "EventCode": "0xE6", + "Counter": "0,1", + "UMask": "0x10", + "EventName": "BACLEARS.COND", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of times the front end resteers for conditional branches as a result of another branch handling mechanism in the front end." + }, + { + "PEBS": "1", + "EventCode": "0x03", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "RECYCLEQ.LD_BLOCK_ST_FORWARD", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of occurences a retired load gets blocked because its address partially overlaps with a store ", + "Data_LA": "1" + }, + { + "EventCode": "0x03", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "RECYCLEQ.LD_BLOCK_STD_NOTREADY", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of occurences a retired load gets blocked because its address overlaps with a store whose data is not ready" + }, + { + "PublicDescription": "This event counts the number of retired store that experienced a cache line boundary split(Precise Event). Note that each spilt should be counted only once.", + "EventCode": "0x03", + "Counter": "0,1", + "UMask": "0x4", + "EventName": "RECYCLEQ.ST_SPLITS", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of occurences a retired store that is a cache line split. Each split should be counted only once." + }, + { + "PEBS": "1", + "EventCode": "0x03", + "Counter": "0,1", + "UMask": "0x8", + "EventName": "RECYCLEQ.LD_SPLITS", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of occurences a retired load that is a cache line split. Each split should be counted only once.", + "Data_LA": "1" + }, + { + "EventCode": "0x03", + "Counter": "0,1", + "UMask": "0x10", + "EventName": "RECYCLEQ.LOCK", + "SampleAfterValue": "200003", + "BriefDescription": "Counts all the retired locked loads. It does not include stores because we would double count if we count stores" + }, + { + "EventCode": "0x03", + "Counter": "0,1", + "UMask": "0x20", + "EventName": "RECYCLEQ.STA_FULL", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the store micro-ops retired that were pushed in the rehad queue because the store address buffer is full" + }, + { + "EventCode": "0x03", + "Counter": "0,1", + "UMask": "0x40", + "EventName": "RECYCLEQ.ANY_LD", + "SampleAfterValue": "200003", + "BriefDescription": "Counts any retired load that was pushed into the recycle queue for any reason." + }, + { + "EventCode": "0x03", + "Counter": "0,1", + "UMask": "0x80", + "EventName": "RECYCLEQ.ANY_ST", + "SampleAfterValue": "200003", + "BriefDescription": "Counts any retired store that was pushed into the recycle queue for any reason." + }, + { + "PEBS": "1", + "EventCode": "0xC5", + "Counter": "0,1", + "UMask": "0xf9", + "EventName": "BR_MISP_RETIRED.CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of mispredicted near CALL branch instructions retired." + }, + { + "PEBS": "1", + "EventCode": "0xC5", + "Counter": "0,1", + "UMask": "0xfd", + "EventName": "BR_MISP_RETIRED.REL_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of mispredicted near relative CALL branch instructions retired." + }, + { + "PEBS": "1", + "EventCode": "0xC5", + "Counter": "0,1", + "UMask": "0xbf", + "EventName": "BR_MISP_RETIRED.FAR_BRANCH", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of mispredicted far branch instructions retired." + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/virtual-memory.json b/tools/perf/pmu-events/arch/x86/knightslanding/virtual-memory.json new file mode 100644 index 000000000000..f31594507f8c --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/knightslanding/virtual-memory.json @@ -0,0 +1,65 @@ +[ + { + "PEBS": "1", + "EventCode": "0x04", + "Counter": "0,1", + "UMask": "0x8", + "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of load micro-ops retired that cause a DTLB miss", + "Data_LA": "1" + }, + { + "EventCode": "0x05", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "PAGE_WALKS.D_SIDE_WALKS", + "SampleAfterValue": "100003", + "BriefDescription": "Counts the total D-side page walks that are completed or started. The page walks started in the speculative path will also be counted", + "EdgeDetect": "1" + }, + { + "EventCode": "0x05", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "PAGE_WALKS.D_SIDE_CYCLES", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the total number of core cycles for all the D-side page walks. The cycles for page walks started in speculative path will also be included." + }, + { + "EventCode": "0x05", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "PAGE_WALKS.I_SIDE_WALKS", + "SampleAfterValue": "100003", + "BriefDescription": "Counts the total I-side page walks that are completed.", + "EdgeDetect": "1" + }, + { + "PublicDescription": "This event counts every cycle when an I-side (walks due to an instruction fetch) page walk is in progress. ", + "EventCode": "0x05", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "PAGE_WALKS.I_SIDE_CYCLES", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the total number of core cycles for all the I-side page walks. The cycles for page walks started in speculative path will also be included." + }, + { + "EventCode": "0x05", + "Counter": "0,1", + "UMask": "0x3", + "EventName": "PAGE_WALKS.WALKS", + "SampleAfterValue": "100003", + "BriefDescription": "Counts the total page walks that are completed (I-side and D-side)", + "EdgeDetect": "1" + }, + { + "PublicDescription": "This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress.", + "EventCode": "0x05", + "Counter": "0,1", + "UMask": "0x3", + "EventName": "PAGE_WALKS.CYCLES", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the total number of core cycles for all the page walks. The cycles for page walks started in speculative path will also be included." + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv new file mode 100644 index 000000000000..12181bb1da2a --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -0,0 +1,35 @@ +Family-model,Version,Filename,EventType +GenuineIntel-6-56,v5,broadwellde,core +GenuineIntel-6-3D,v17,broadwell,core +GenuineIntel-6-47,v17,broadwell,core +GenuineIntel-6-4F,v10,broadwellx,core +GenuineIntel-6-1C,v4,bonnell,core +GenuineIntel-6-26,v4,bonnell,core +GenuineIntel-6-27,v4,bonnell,core +GenuineIntel-6-36,v4,bonnell,core +GenuineIntel-6-35,v4,bonnell,core +GenuineIntel-6-5C,v8,goldmont,core +GenuineIntel-6-3C,v24,haswell,core +GenuineIntel-6-45,v24,haswell,core +GenuineIntel-6-46,v24,haswell,core +GenuineIntel-6-3F,v17,haswellx,core +GenuineIntel-6-3A,v18,ivybridge,core +GenuineIntel-6-3E,v19,ivytown,core +GenuineIntel-6-2D,v20,jaketown,core +GenuineIntel-6-57,v9,knightslanding,core +GenuineIntel-6-1E,v2,nehalemep,core +GenuineIntel-6-1F,v2,nehalemep,core +GenuineIntel-6-1A,v2,nehalemep,core +GenuineIntel-6-2E,v2,nehalemex,core +GenuineIntel-6-4E,v24,skylake,core +GenuineIntel-6-5E,v24,skylake,core +GenuineIntel-6-8E,v24,skylake,core +GenuineIntel-6-9E,v24,skylake,core +GenuineIntel-6-37,v13,silvermont,core +GenuineIntel-6-4D,v13,silvermont,core +GenuineIntel-6-4C,v13,silvermont,core +GenuineIntel-6-2A,v15,sandybridge,core +GenuineIntel-6-2C,v2,westmereep-dp,core +GenuineIntel-6-2C,v2,westmereep-dp,core +GenuineIntel-6-25,v2,westmereep-sp,core +GenuineIntel-6-2F,v2,westmereex,core diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/cache.json b/tools/perf/pmu-events/arch/x86/nehalemep/cache.json new file mode 100644 index 000000000000..a11029efda2f --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/nehalemep/cache.json @@ -0,0 +1,3229 @@ +[ + { + "EventCode": "0x63", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "CACHE_LOCK_CYCLES.L1D", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles L1D locked" + }, + { + "EventCode": "0x63", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "CACHE_LOCK_CYCLES.L1D_L2", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles L1D and L2 locked" + }, + { + "EventCode": "0x51", + "Counter": "0,1", + "UMask": "0x4", + "EventName": "L1D.M_EVICT", + "SampleAfterValue": "2000000", + "BriefDescription": "L1D cache lines replaced in M state" + }, + { + "EventCode": "0x51", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "L1D.M_REPL", + "SampleAfterValue": "2000000", + "BriefDescription": "L1D cache lines allocated in the M state" + }, + { + "EventCode": "0x51", + "Counter": "0,1", + "UMask": "0x8", + "EventName": "L1D.M_SNOOP_EVICT", + "SampleAfterValue": "2000000", + "BriefDescription": "L1D snoop eviction of cache lines in M state" + }, + { + "EventCode": "0x51", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "L1D.REPL", + "SampleAfterValue": "2000000", + "BriefDescription": "L1 data cache lines allocated" + }, + { + "EventCode": "0x43", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "L1D_ALL_REF.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "All references to the L1 data cache" + }, + { + "EventCode": "0x43", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "L1D_ALL_REF.CACHEABLE", + "SampleAfterValue": "2000000", + "BriefDescription": "L1 data cacheable reads and writes" + }, + { + "EventCode": "0x40", + "Counter": "0,1", + "UMask": "0x4", + "EventName": "L1D_CACHE_LD.E_STATE", + "SampleAfterValue": "2000000", + "BriefDescription": "L1 data cache read in E state" + }, + { + "EventCode": "0x40", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "L1D_CACHE_LD.I_STATE", + "SampleAfterValue": "2000000", + "BriefDescription": "L1 data cache read in I state (misses)" + }, + { + "EventCode": "0x40", + "Counter": "0,1", + "UMask": "0x8", + "EventName": "L1D_CACHE_LD.M_STATE", + "SampleAfterValue": "2000000", + "BriefDescription": "L1 data cache read in M state" + }, + { + "EventCode": "0x40", + "Counter": "0,1", + "UMask": "0xf", + "EventName": "L1D_CACHE_LD.MESI", + "SampleAfterValue": "2000000", + "BriefDescription": "L1 data cache reads" + }, + { + "EventCode": "0x40", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "L1D_CACHE_LD.S_STATE", + "SampleAfterValue": "2000000", + "BriefDescription": "L1 data cache read in S state" + }, + { + "EventCode": "0x42", + "Counter": "0,1", + "UMask": "0x4", + "EventName": "L1D_CACHE_LOCK.E_STATE", + "SampleAfterValue": "2000000", + "BriefDescription": "L1 data cache load locks in E state" + }, + { + "EventCode": "0x42", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "L1D_CACHE_LOCK.HIT", + "SampleAfterValue": "2000000", + "BriefDescription": "L1 data cache load lock hits" + }, + { + "EventCode": "0x42", + "Counter": "0,1", + "UMask": "0x8", + "EventName": "L1D_CACHE_LOCK.M_STATE", + "SampleAfterValue": "2000000", + "BriefDescription": "L1 data cache load locks in M state" + }, + { + "EventCode": "0x42", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "L1D_CACHE_LOCK.S_STATE", + "SampleAfterValue": "2000000", + "BriefDescription": "L1 data cache load locks in S state" + }, + { + "EventCode": "0x53", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "L1D_CACHE_LOCK_FB_HIT", + "SampleAfterValue": "2000000", + "BriefDescription": "L1D load lock accepted in fill buffer" + }, + { + "EventCode": "0x52", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT", + "SampleAfterValue": "2000000", + "BriefDescription": "L1D prefetch load lock accepted in fill buffer" + }, + { + "EventCode": "0x41", + "Counter": "0,1", + "UMask": "0x4", + "EventName": "L1D_CACHE_ST.E_STATE", + "SampleAfterValue": "2000000", + "BriefDescription": "L1 data cache stores in E state" + }, + { + "EventCode": "0x41", + "Counter": "0,1", + "UMask": "0x8", + "EventName": "L1D_CACHE_ST.M_STATE", + "SampleAfterValue": "2000000", + "BriefDescription": "L1 data cache stores in M state" + }, + { + "EventCode": "0x41", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "L1D_CACHE_ST.S_STATE", + "SampleAfterValue": "2000000", + "BriefDescription": "L1 data cache stores in S state" + }, + { + "EventCode": "0x4E", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "L1D_PREFETCH.MISS", + "SampleAfterValue": "200000", + "BriefDescription": "L1D hardware prefetch misses" + }, + { + "EventCode": "0x4E", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "L1D_PREFETCH.REQUESTS", + "SampleAfterValue": "200000", + "BriefDescription": "L1D hardware prefetch requests" + }, + { + "EventCode": "0x4E", + "Counter": "0,1", + "UMask": "0x4", + "EventName": "L1D_PREFETCH.TRIGGERS", + "SampleAfterValue": "200000", + "BriefDescription": "L1D hardware prefetch requests triggered" + }, + { + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L1D_WB_L2.E_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L1 writebacks to L2 in E state" + }, + { + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L1D_WB_L2.I_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L1 writebacks to L2 in I state (misses)" + }, + { + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L1D_WB_L2.M_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L1 writebacks to L2 in M state" + }, + { + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "L1D_WB_L2.MESI", + "SampleAfterValue": "100000", + "BriefDescription": "All L1 writebacks to L2" + }, + { + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L1D_WB_L2.S_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L1 writebacks to L2 in S state" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0xff", + "EventName": "L2_DATA_RQSTS.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "All L2 data requests" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data demand loads in E state" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data demand loads in I state (misses)" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data demand loads in M state" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "L2_DATA_RQSTS.DEMAND.MESI", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data demand requests" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data demand loads in S state" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data prefetches in E state" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data prefetches in the I state (misses)" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data prefetches in M state" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0xf0", + "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", + "SampleAfterValue": "200000", + "BriefDescription": "All L2 data prefetches" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data prefetches in the S state" + }, + { + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x7", + "EventName": "L2_LINES_IN.ANY", + "SampleAfterValue": "100000", + "BriefDescription": "L2 lines alloacated" + }, + { + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_LINES_IN.E_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 lines allocated in the E state" + }, + { + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_LINES_IN.S_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 lines allocated in the S state" + }, + { + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "L2_LINES_OUT.ANY", + "SampleAfterValue": "100000", + "BriefDescription": "L2 lines evicted" + }, + { + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_LINES_OUT.DEMAND_CLEAN", + "SampleAfterValue": "100000", + "BriefDescription": "L2 lines evicted by a demand request" + }, + { + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_LINES_OUT.DEMAND_DIRTY", + "SampleAfterValue": "100000", + "BriefDescription": "L2 modified lines evicted by a demand request" + }, + { + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_LINES_OUT.PREFETCH_CLEAN", + "SampleAfterValue": "100000", + "BriefDescription": "L2 lines evicted by a prefetch request" + }, + { + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_LINES_OUT.PREFETCH_DIRTY", + "SampleAfterValue": "100000", + "BriefDescription": "L2 modified lines evicted by a prefetch request" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "L2_RQSTS.IFETCH_HIT", + "SampleAfterValue": "200000", + "BriefDescription": "L2 instruction fetch hits" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "L2_RQSTS.IFETCH_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "L2 instruction fetch misses" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "L2_RQSTS.IFETCHES", + "SampleAfterValue": "200000", + "BriefDescription": "L2 instruction fetches" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_RQSTS.LD_HIT", + "SampleAfterValue": "200000", + "BriefDescription": "L2 load hits" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_RQSTS.LD_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "L2 load misses" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x3", + "EventName": "L2_RQSTS.LOADS", + "SampleAfterValue": "200000", + "BriefDescription": "L2 requests" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xaa", + "EventName": "L2_RQSTS.MISS", + "SampleAfterValue": "200000", + "BriefDescription": "All L2 misses" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "L2_RQSTS.PREFETCH_HIT", + "SampleAfterValue": "200000", + "BriefDescription": "L2 prefetch hits" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "L2_RQSTS.PREFETCH_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "L2 prefetch misses" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xc0", + "EventName": "L2_RQSTS.PREFETCHES", + "SampleAfterValue": "200000", + "BriefDescription": "All L2 prefetches" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xff", + "EventName": "L2_RQSTS.REFERENCES", + "SampleAfterValue": "200000", + "BriefDescription": "All L2 requests" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_RQSTS.RFO_HIT", + "SampleAfterValue": "200000", + "BriefDescription": "L2 RFO hits" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_RQSTS.RFO_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "L2 RFO misses" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xc", + "EventName": "L2_RQSTS.RFOS", + "SampleAfterValue": "200000", + "BriefDescription": "L2 RFO requests" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "L2_TRANSACTIONS.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "All L2 transactions" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "L2_TRANSACTIONS.FILL", + "SampleAfterValue": "200000", + "BriefDescription": "L2 fill transactions" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_TRANSACTIONS.IFETCH", + "SampleAfterValue": "200000", + "BriefDescription": "L2 instruction fetch transactions" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "L2_TRANSACTIONS.L1D_WB", + "SampleAfterValue": "200000", + "BriefDescription": "L1D writeback to L2 transactions" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_TRANSACTIONS.LOAD", + "SampleAfterValue": "200000", + "BriefDescription": "L2 Load transactions" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_TRANSACTIONS.PREFETCH", + "SampleAfterValue": "200000", + "BriefDescription": "L2 prefetch transactions" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_TRANSACTIONS.RFO", + "SampleAfterValue": "200000", + "BriefDescription": "L2 RFO transactions" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "L2_TRANSACTIONS.WB", + "SampleAfterValue": "200000", + "BriefDescription": "L2 writeback to LLC transactions" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "L2_WRITE.LOCK.E_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 demand lock RFOs in E state" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0xe0", + "EventName": "L2_WRITE.LOCK.HIT", + "SampleAfterValue": "100000", + "BriefDescription": "All demand L2 lock RFOs that hit the cache" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "L2_WRITE.LOCK.I_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 demand lock RFOs in I state (misses)" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "L2_WRITE.LOCK.M_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 demand lock RFOs in M state" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0xf0", + "EventName": "L2_WRITE.LOCK.MESI", + "SampleAfterValue": "100000", + "BriefDescription": "All demand L2 lock RFOs" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "L2_WRITE.LOCK.S_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 demand lock RFOs in S state" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0xe", + "EventName": "L2_WRITE.RFO.HIT", + "SampleAfterValue": "100000", + "BriefDescription": "All L2 demand store RFOs that hit the cache" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_WRITE.RFO.I_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 demand store RFOs in I state (misses)" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_WRITE.RFO.M_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 demand store RFOs in M state" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "L2_WRITE.RFO.MESI", + "SampleAfterValue": "100000", + "BriefDescription": "All L2 demand store RFOs" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_WRITE.RFO.S_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 demand store RFOs in S state" + }, + { + "EventCode": "0x2E", + "Counter": "0,1,2,3", + "UMask": "0x41", + "EventName": "LONGEST_LAT_CACHE.MISS", + "SampleAfterValue": "100000", + "BriefDescription": "Longest latency cache miss" + }, + { + "EventCode": "0x2E", + "Counter": "0,1,2,3", + "UMask": "0x4f", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "SampleAfterValue": "200000", + "BriefDescription": "Longest latency cache reference" + }, + { + "PEBS": "1", + "EventCode": "0xB", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_INST_RETIRED.LOADS", + "SampleAfterValue": "2000000", + "BriefDescription": "Instructions retired which contains a load (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xB", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MEM_INST_RETIRED.STORES", + "SampleAfterValue": "2000000", + "BriefDescription": "Instructions retired which contains a store (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xCB", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "MEM_LOAD_RETIRED.HIT_LFB", + "SampleAfterValue": "200000", + "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xCB", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_LOAD_RETIRED.L1D_HIT", + "SampleAfterValue": "2000000", + "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xCB", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MEM_LOAD_RETIRED.L2_HIT", + "SampleAfterValue": "200000", + "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xCB", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "MEM_LOAD_RETIRED.LLC_MISS", + "SampleAfterValue": "10000", + "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xCB", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", + "SampleAfterValue": "40000", + "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xCB", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", + "SampleAfterValue": "40000", + "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xF", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM", + "SampleAfterValue": "10000", + "BriefDescription": "Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xF", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM", + "SampleAfterValue": "40000", + "BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xF", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT", + "SampleAfterValue": "20000", + "BriefDescription": "Load instructions retired remote cache HIT data source (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xF", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM", + "SampleAfterValue": "10000", + "BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xF", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE", + "SampleAfterValue": "4000", + "BriefDescription": "Load instructions retired IO (Precise Event)" + }, + { + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore L1 data cache writebacks" + }, + { + "EventCode": "0xB2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS_SQ_FULL", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests blocked due to Super Queue full" + }, + { + "EventCode": "0xF4", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "SQ_MISC.SPLIT_LOCK", + "SampleAfterValue": "2000000", + "BriefDescription": "Super Queue lock splits across a cache line" + }, + { + "EventCode": "0x6", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "STORE_BLOCKS.AT_RET", + "SampleAfterValue": "200000", + "BriefDescription": "Loads delayed with at-Retirement block code" + }, + { + "EventCode": "0x6", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "STORE_BLOCKS.L1D_BLOCK", + "SampleAfterValue": "200000", + "BriefDescription": "Cacheable loads delayed with L1D block code" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x0", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", + "MSRIndex": "0x3F6", + "SampleAfterValue": "2000000", + "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x400", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", + "MSRIndex": "0x3F6", + "SampleAfterValue": "100", + "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x80", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", + "MSRIndex": "0x3F6", + "SampleAfterValue": "1000", + "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x10", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", + "MSRIndex": "0x3F6", + "SampleAfterValue": "10000", + "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x4000", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", + "MSRIndex": "0x3F6", + "SampleAfterValue": "5", + "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x800", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", + "MSRIndex": "0x3F6", + "SampleAfterValue": "50", + "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x100", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", + "MSRIndex": "0x3F6", + "SampleAfterValue": "500", + "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x20", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", + "MSRIndex": "0x3F6", + "SampleAfterValue": "5000", + "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x8000", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", + "MSRIndex": "0x3F6", + "SampleAfterValue": "3", + "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x4", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", + "MSRIndex": "0x3F6", + "SampleAfterValue": "50000", + "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x1000", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", + "MSRIndex": "0x3F6", + "SampleAfterValue": "20", + "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x200", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", + "MSRIndex": "0x3F6", + "SampleAfterValue": "200", + "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x40", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", + "MSRIndex": "0x3F6", + "SampleAfterValue": "2000", + "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x8", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", + "MSRIndex": "0x3F6", + "SampleAfterValue": "20000", + "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x2000", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", + "MSRIndex": "0x3F6", + "SampleAfterValue": "10", + "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F11", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by any cache or DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF11", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore data reads", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8011", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x111", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x211", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x411", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x711", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4711", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1811", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3811", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1011", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x811", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F44", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by any cache or DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF44", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore code reads", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8044", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x144", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x244", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x444", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x744", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4744", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1844", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3844", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1044", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x844", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7FFF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by any cache or DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFFFF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore requests", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x80FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x47FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x18FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x38FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x10FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F22", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF22", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore RFO requests", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8022", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x122", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x222", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x422", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x722", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4722", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1822", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3822", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1022", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x822", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F08", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to any cache or DRAM.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF08", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore writebacks", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8008", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x108", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x408", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x708", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4708", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1808", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3808", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1008", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x808", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F77", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF77", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore code or data read requests", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8077", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x177", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x277", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x477", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x777", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4777", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1877", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3877", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1077", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x877", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F33", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore request = all data, response = any cache_dram", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF33", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore request = all data, response = any location", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8033", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x133", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x233", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x433", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x733", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore request = all data, response = local cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4733", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore request = all data, response = local cache or dram", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1833", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore request = all data, response = remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3833", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore request = all data, response = remote cache or dram", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1033", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads, RFO's and prefetches that HIT in a remote cache ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x833", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads, RFO's and prefetches that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F03", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF03", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore demand data requests", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8003", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x103", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x203", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x403", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x703", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4703", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1803", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3803", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1003", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x803", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F01", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF01", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore demand data reads", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8001", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x101", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x201", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x401", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x701", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4701", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1801", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3801", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1001", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x801", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F04", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF04", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore demand code reads", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8004", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x104", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x204", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x404", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x704", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4704", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1804", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3804", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1004", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x804", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F02", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF02", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore demand RFO requests", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8002", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x102", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x202", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x402", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x702", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4702", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1802", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3802", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1002", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x802", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F80", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF80", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore other requests", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8080", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x180", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x280", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x480", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x780", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4780", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1880", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3880", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1080", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x880", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F30", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF30", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore prefetch data requests", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8030", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x130", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x230", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x430", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x730", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4730", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1830", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests satisfied by a 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"0xB7", + "MSRValue": "0x7F10", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF10", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore prefetch data reads", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8010", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x110", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x210", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x410", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x710", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4710", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1810", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3810", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1010", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x810", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F40", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF40", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore prefetch code reads", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8040", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x140", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, 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"0x4740", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1840", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3840", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1040", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x840", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F20", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF20", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore prefetch RFO requests", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8020", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x120", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x220", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x420", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x720", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4720", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1820", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3820", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1020", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x820", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F70", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF70", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore prefetch requests", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8070", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x170", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x270", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x470", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x770", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4770", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1870", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3870", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1070", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x870", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests that HITM in a remote cache", + "Offcore": "1" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/floating-point.json b/tools/perf/pmu-events/arch/x86/nehalemep/floating-point.json new file mode 100644 index 000000000000..7d2f71a9dee3 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/nehalemep/floating-point.json @@ -0,0 +1,229 @@ +[ + { + "PEBS": "1", + "EventCode": "0xF7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "FP_ASSIST.ALL", + "SampleAfterValue": "20000", + "BriefDescription": "X87 Floating point assists (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xF7", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "FP_ASSIST.INPUT", + "SampleAfterValue": "20000", + "BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xF7", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "FP_ASSIST.OUTPUT", + "SampleAfterValue": "20000", + "BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "FP_COMP_OPS_EXE.MMX", + "SampleAfterValue": "2000000", + "BriefDescription": "MMX Uops" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION", + "SampleAfterValue": "2000000", + "BriefDescription": "SSE* FP double precision Uops" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "FP_COMP_OPS_EXE.SSE_FP", + "SampleAfterValue": "2000000", + "BriefDescription": "SSE and SSE2 FP Uops" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED", + "SampleAfterValue": "2000000", + "BriefDescription": "SSE FP packed Uops" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR", + "SampleAfterValue": "2000000", + "BriefDescription": "SSE FP scalar Uops" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION", + "SampleAfterValue": "2000000", + "BriefDescription": "SSE* FP single precision Uops" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER", + "SampleAfterValue": "2000000", + "BriefDescription": "SSE2 integer Uops" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "FP_COMP_OPS_EXE.X87", + "SampleAfterValue": "2000000", + "BriefDescription": "Computational floating-point operations executed" + }, + { + "EventCode": "0xCC", + "Counter": "0,1,2,3", + "UMask": "0x3", + "EventName": "FP_MMX_TRANS.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "All Floating Point to and from MMX transitions" + }, + { + "EventCode": "0xCC", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "FP_MMX_TRANS.TO_FP", + "SampleAfterValue": "2000000", + "BriefDescription": "Transitions from MMX to Floating Point instructions" + }, + { + "EventCode": "0xCC", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "FP_MMX_TRANS.TO_MMX", + "SampleAfterValue": "2000000", + "BriefDescription": "Transitions from Floating Point to MMX instructions" + }, + { + "EventCode": "0x12", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "SIMD_INT_128.PACK", + "SampleAfterValue": "200000", + "BriefDescription": "128 bit SIMD integer pack operations" + }, + { + "EventCode": "0x12", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "SIMD_INT_128.PACKED_ARITH", + "SampleAfterValue": "200000", + "BriefDescription": "128 bit SIMD integer arithmetic operations" + }, + { + "EventCode": "0x12", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "SIMD_INT_128.PACKED_LOGICAL", + "SampleAfterValue": "200000", + "BriefDescription": "128 bit SIMD integer logical operations" + }, + { + "EventCode": "0x12", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "SIMD_INT_128.PACKED_MPY", + "SampleAfterValue": "200000", + "BriefDescription": "128 bit SIMD integer multiply operations" + }, + { + "EventCode": "0x12", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "SIMD_INT_128.PACKED_SHIFT", + "SampleAfterValue": "200000", + "BriefDescription": "128 bit SIMD integer shift operations" + }, + { + "EventCode": "0x12", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "SIMD_INT_128.SHUFFLE_MOVE", + "SampleAfterValue": "200000", + "BriefDescription": "128 bit SIMD integer shuffle/move operations" + }, + { + "EventCode": "0x12", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "SIMD_INT_128.UNPACK", + "SampleAfterValue": "200000", + "BriefDescription": "128 bit SIMD integer unpack operations" + }, + { + "EventCode": "0xFD", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "SIMD_INT_64.PACK", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD integer 64 bit pack operations" + }, + { + "EventCode": "0xFD", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "SIMD_INT_64.PACKED_ARITH", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD integer 64 bit arithmetic operations" + }, + { + "EventCode": "0xFD", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "SIMD_INT_64.PACKED_LOGICAL", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD integer 64 bit logical operations" + }, + { + "EventCode": "0xFD", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "SIMD_INT_64.PACKED_MPY", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD integer 64 bit packed multiply operations" + }, + { + "EventCode": "0xFD", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "SIMD_INT_64.PACKED_SHIFT", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD integer 64 bit shift operations" + }, + { + "EventCode": "0xFD", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "SIMD_INT_64.SHUFFLE_MOVE", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD integer 64 bit shuffle/move operations" + }, + { + "EventCode": "0xFD", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "SIMD_INT_64.UNPACK", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD integer 64 bit unpack operations" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/frontend.json b/tools/perf/pmu-events/arch/x86/nehalemep/frontend.json new file mode 100644 index 000000000000..e5e21e03444d --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/nehalemep/frontend.json @@ -0,0 +1,26 @@ +[ + { + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MACRO_INSTS.DECODED", + "SampleAfterValue": "2000000", + "BriefDescription": "Instructions decoded" + }, + { + "EventCode": "0xA6", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MACRO_INSTS.FUSIONS_DECODED", + "SampleAfterValue": "2000000", + "BriefDescription": "Macro-fused instructions decoded" + }, + { + "EventCode": "0x19", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "TWO_UOP_INSTS_DECODED", + "SampleAfterValue": "2000000", + "BriefDescription": "Two Uop instructions decoded" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/memory.json b/tools/perf/pmu-events/arch/x86/nehalemep/memory.json new file mode 100644 index 000000000000..f914a4525b65 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/nehalemep/memory.json @@ -0,0 +1,739 @@ +[ + { + "EventCode": "0xB7", + "MSRValue": "0x6011", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF811", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4011", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2011", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6044", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF844", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4044", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2044", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x60FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF8FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x40FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x20FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6022", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF822", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4022", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2022", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6008", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF808", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4008", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2008", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6077", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF877", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4077", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2077", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6033", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore request = all data, response = any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF833", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore request = all data, response = any LLC miss", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4033", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the local DRAM.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2033", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6003", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF803", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4003", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2003", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6001", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF801", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4001", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2001", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6004", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF804", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4004", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2004", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6002", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF802", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4002", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2002", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6080", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF880", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2080", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6030", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF830", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4030", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2030", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6010", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF810", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4010", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2010", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6040", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF840", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4040", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2040", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6020", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF820", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4020", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2020", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6070", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF870", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4070", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2070", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by a remote DRAM", + "Offcore": "1" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/other.json b/tools/perf/pmu-events/arch/x86/nehalemep/other.json new file mode 100644 index 000000000000..af0860622445 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/nehalemep/other.json @@ -0,0 +1,210 @@ +[ + { + "EventCode": "0xE8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BPU_CLEARS.EARLY", + "SampleAfterValue": "2000000", + "BriefDescription": "Early Branch Prediciton Unit clears" + }, + { + "EventCode": "0xE8", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "BPU_CLEARS.LATE", + "SampleAfterValue": "2000000", + "BriefDescription": "Late Branch Prediction Unit clears" + }, + { + "EventCode": "0xE5", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BPU_MISSED_CALL_RET", + "SampleAfterValue": "2000000", + "BriefDescription": "Branch prediction unit missed call or return" + }, + { + "EventCode": "0xD5", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ES_REG_RENAMES", + "SampleAfterValue": "2000000", + "BriefDescription": "ES segment renames" + }, + { + "EventCode": "0x6C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IO_TRANSACTIONS", + "SampleAfterValue": "2000000", + "BriefDescription": "I/O transactions" + }, + { + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L1I.CYCLES_STALLED", + "SampleAfterValue": "2000000", + "BriefDescription": "L1I instruction fetch stall cycles" + }, + { + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L1I.HITS", + "SampleAfterValue": "2000000", + "BriefDescription": "L1I instruction fetch hits" + }, + { + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L1I.MISSES", + "SampleAfterValue": "2000000", + "BriefDescription": "L1I instruction fetch misses" + }, + { + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x3", + "EventName": "L1I.READS", + "SampleAfterValue": "2000000", + "BriefDescription": "L1I Instruction fetches" + }, + { + "EventCode": "0x82", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LARGE_ITLB.HIT", + "SampleAfterValue": "200000", + "BriefDescription": "Large ITLB hit" + }, + { + "EventCode": "0x13", + "Counter": "0,1,2,3", + "UMask": "0x7", + "EventName": "LOAD_DISPATCH.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "All loads dispatched" + }, + { + "EventCode": "0x13", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "LOAD_DISPATCH.MOB", + "SampleAfterValue": "2000000", + "BriefDescription": "Loads dispatched from the MOB" + }, + { + "EventCode": "0x13", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LOAD_DISPATCH.RS", + "SampleAfterValue": "2000000", + "BriefDescription": "Loads dispatched that bypass the MOB" + }, + { + "EventCode": "0x13", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "LOAD_DISPATCH.RS_DELAYED", + "SampleAfterValue": "2000000", + "BriefDescription": "Loads dispatched from stage 305" + }, + { + "EventCode": "0x7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "PARTIAL_ADDRESS_ALIAS", + "SampleAfterValue": "200000", + "BriefDescription": "False dependencies due to partial address aliasing" + }, + { + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "RAT_STALLS.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "All RAT stall cycles" + }, + { + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "RAT_STALLS.FLAGS", + "SampleAfterValue": "2000000", + "BriefDescription": "Flag stall cycles" + }, + { + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "RAT_STALLS.REGISTERS", + "SampleAfterValue": "2000000", + "BriefDescription": "Partial register stall cycles" + }, + { + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "RAT_STALLS.ROB_READ_PORT", + "SampleAfterValue": "2000000", + "BriefDescription": "ROB read port stalls cycles" + }, + { + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "RAT_STALLS.SCOREBOARD", + "SampleAfterValue": "2000000", + "BriefDescription": "Scoreboard stall cycles" + }, + { + "EventCode": "0x4", + "Counter": "0,1,2,3", + "UMask": "0x7", + "EventName": "SB_DRAIN.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "All Store buffer stall cycles" + }, + { + "EventCode": "0xD4", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "SEG_RENAME_STALLS", + "SampleAfterValue": "2000000", + "BriefDescription": "Segment rename stall cycles" + }, + { + "EventCode": "0xB8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "SNOOP_RESPONSE.HIT", + "SampleAfterValue": "100000", + "BriefDescription": "Thread responded HIT to snoop" + }, + { + "EventCode": "0xB8", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "SNOOP_RESPONSE.HITE", + "SampleAfterValue": "100000", + "BriefDescription": "Thread responded HITE to snoop" + }, + { + "EventCode": "0xB8", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "SNOOP_RESPONSE.HITM", + "SampleAfterValue": "100000", + "BriefDescription": "Thread responded HITM to snoop" + }, + { + "EventCode": "0xF6", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "SQ_FULL_STALL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Super Queue full stall cycles" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/pipeline.json b/tools/perf/pmu-events/arch/x86/nehalemep/pipeline.json new file mode 100644 index 000000000000..41006ddcd893 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/nehalemep/pipeline.json @@ -0,0 +1,881 @@ +[ + { + "EventCode": "0x14", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ARITH.CYCLES_DIV_BUSY", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles the divider is busy" + }, + { + "EventCode": "0x14", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ARITH.DIV", + "SampleAfterValue": "2000000", + "BriefDescription": "Divide Operations executed", + "CounterMask": "1", + "EdgeDetect": "1" + }, + { + "EventCode": "0x14", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "ARITH.MUL", + "SampleAfterValue": "2000000", + "BriefDescription": "Multiply operations executed" + }, + { + "EventCode": "0xE6", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "BACLEAR.BAD_TARGET", + "SampleAfterValue": "2000000", + "BriefDescription": "BACLEAR asserted with bad target address" + }, + { + "EventCode": "0xE6", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BACLEAR.CLEAR", + "SampleAfterValue": "2000000", + "BriefDescription": "BACLEAR asserted, regardless of cause " + }, + { + "EventCode": "0xA7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BACLEAR_FORCE_IQ", + "SampleAfterValue": "2000000", + "BriefDescription": "Instruction queue forced BACLEAR" + }, + { + "EventCode": "0xE0", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BR_INST_DECODED", + "SampleAfterValue": "2000000", + "BriefDescription": "Branch instructions decoded" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x7f", + "EventName": "BR_INST_EXEC.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "Branch instructions executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BR_INST_EXEC.COND", + "SampleAfterValue": "200000", + "BriefDescription": "Conditional branch instructions executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "BR_INST_EXEC.DIRECT", + "SampleAfterValue": "200000", + "BriefDescription": "Unconditional branches executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL", + "SampleAfterValue": "20000", + "BriefDescription": "Unconditional call branches executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL", + "SampleAfterValue": "20000", + "BriefDescription": "Indirect call branches executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL", + "SampleAfterValue": "20000", + "BriefDescription": "Indirect non call branches executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "BR_INST_EXEC.NEAR_CALLS", + "SampleAfterValue": "20000", + "BriefDescription": "Call branches executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x7", + "EventName": "BR_INST_EXEC.NON_CALLS", + "SampleAfterValue": "200000", + "BriefDescription": "All non call branches executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "BR_INST_EXEC.RETURN_NEAR", + "SampleAfterValue": "20000", + "BriefDescription": "Indirect return branches executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "BR_INST_EXEC.TAKEN", + "SampleAfterValue": "200000", + "BriefDescription": "Taken branches executed" + }, + { + "PEBS": "1", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "SampleAfterValue": "200000", + "BriefDescription": "Retired branch instructions (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BR_INST_RETIRED.CONDITIONAL", + "SampleAfterValue": "200000", + "BriefDescription": "Retired conditional branch instructions (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "SampleAfterValue": "20000", + "BriefDescription": "Retired near call instructions (Precise Event)" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x7f", + "EventName": "BR_MISP_EXEC.ANY", + "SampleAfterValue": "20000", + "BriefDescription": "Mispredicted branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BR_MISP_EXEC.COND", + "SampleAfterValue": "20000", + "BriefDescription": "Mispredicted conditional branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "BR_MISP_EXEC.DIRECT", + "SampleAfterValue": "20000", + "BriefDescription": "Mispredicted unconditional branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL", + "SampleAfterValue": "2000", + "BriefDescription": "Mispredicted non call branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL", + "SampleAfterValue": "2000", + "BriefDescription": "Mispredicted indirect call branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL", + "SampleAfterValue": "2000", + "BriefDescription": "Mispredicted indirect non call branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "BR_MISP_EXEC.NEAR_CALLS", + "SampleAfterValue": "2000", + "BriefDescription": "Mispredicted call branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x7", + "EventName": "BR_MISP_EXEC.NON_CALLS", + "SampleAfterValue": "20000", + "BriefDescription": "Mispredicted non call branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "BR_MISP_EXEC.RETURN_NEAR", + "SampleAfterValue": "2000", + "BriefDescription": "Mispredicted return branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "BR_MISP_EXEC.TAKEN", + "SampleAfterValue": "20000", + "BriefDescription": "Mispredicted taken branches executed" + }, + { + "PEBS": "1", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "BR_MISP_RETIRED.NEAR_CALL", + "SampleAfterValue": "2000", + "BriefDescription": "Mispredicted near retired calls (Precise Event)" + }, + { + "EventCode": "0x0", + "Counter": "Fixed counter 3", + "UMask": "0x0", + "EventName": "CPU_CLK_UNHALTED.REF", + "SampleAfterValue": "2000000", + "BriefDescription": "Reference cycles when thread is not halted (fixed counter)" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CPU_CLK_UNHALTED.REF_P", + "SampleAfterValue": "100000", + "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)" + }, + { + "EventCode": "0x0", + "Counter": "Fixed counter 2", + "UMask": "0x0", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles when thread is not halted (fixed counter)" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles when thread is not halted (programmable counter)" + }, + { + "EventCode": "0x3C", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Total CPU cycles", + "CounterMask": "2" + }, + { + "EventCode": "0x87", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "ILD_STALL.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "Any Instruction Length Decoder stall cycles" + }, + { + "EventCode": "0x87", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "ILD_STALL.IQ_FULL", + "SampleAfterValue": "2000000", + "BriefDescription": "Instruction Queue full stall cycles" + }, + { + "EventCode": "0x87", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ILD_STALL.LCP", + "SampleAfterValue": "2000000", + "BriefDescription": "Length Change Prefix stall cycles" + }, + { + "EventCode": "0x87", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "ILD_STALL.MRU", + "SampleAfterValue": "2000000", + "BriefDescription": "Stall cycles due to BPU MRU bypass" + }, + { + "EventCode": "0x87", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "ILD_STALL.REGEN", + "SampleAfterValue": "2000000", + "BriefDescription": "Regen stall cycles" + }, + { + "EventCode": "0x18", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "INST_DECODED.DEC0", + "SampleAfterValue": "2000000", + "BriefDescription": "Instructions that must be decoded by decoder 0" + }, + { + "EventCode": "0x1E", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "INST_QUEUE_WRITE_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles instructions are written to the instruction queue" + }, + { + "EventCode": "0x17", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "INST_QUEUE_WRITES", + "SampleAfterValue": "2000000", + "BriefDescription": "Instructions written to instruction queue." + }, + { + "EventCode": "0x0", + "Counter": "Fixed counter 1", + "UMask": "0x0", + "EventName": "INST_RETIRED.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "Instructions retired (fixed counter)" + }, + { + "PEBS": "1", + "EventCode": "0xC0", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "INST_RETIRED.ANY_P", + "SampleAfterValue": "2000000", + "BriefDescription": "Instructions retired (Programmable counter and Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC0", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "INST_RETIRED.MMX", + "SampleAfterValue": "2000000", + "BriefDescription": "Retired MMX instructions (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC0", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "INST_RETIRED.TOTAL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Total cycles (Precise Event)", + "CounterMask": "16" + }, + { + "PEBS": "1", + "EventCode": "0xC0", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "INST_RETIRED.X87", + "SampleAfterValue": "2000000", + "BriefDescription": "Retired floating-point operations (Precise Event)" + }, + { + "EventCode": "0x4C", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "LOAD_HIT_PRE", + "SampleAfterValue": "200000", + "BriefDescription": "Load operations conflicting with software prefetches" + }, + { + "EventCode": "0xA8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LSD.ACTIVE", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles when uops were delivered by the LSD", + "CounterMask": "1" + }, + { + "EventCode": "0xA8", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LSD.INACTIVE", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles no uops were delivered by the LSD", + "CounterMask": "1" + }, + { + "EventCode": "0x20", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LSD_OVERFLOW", + "SampleAfterValue": "2000000", + "BriefDescription": "Loops that can't stream from the instruction queue" + }, + { + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MACHINE_CLEARS.CYCLES", + "SampleAfterValue": "20000", + "BriefDescription": "Cycles machine clear asserted" + }, + { + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MACHINE_CLEARS.MEM_ORDER", + "SampleAfterValue": "20000", + "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts" + }, + { + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "MACHINE_CLEARS.SMC", + "SampleAfterValue": "20000", + "BriefDescription": "Self-Modifying Code detected" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "RESOURCE_STALLS.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "Resource related stall cycles" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "RESOURCE_STALLS.FPCW", + "SampleAfterValue": "2000000", + "BriefDescription": "FPU control word write stall cycles" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "RESOURCE_STALLS.LOAD", + "SampleAfterValue": "2000000", + "BriefDescription": "Load buffer stall cycles" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "RESOURCE_STALLS.MXCSR", + "SampleAfterValue": "2000000", + "BriefDescription": "MXCSR rename stall cycles" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "RESOURCE_STALLS.OTHER", + "SampleAfterValue": "2000000", + "BriefDescription": "Other Resource related stall cycles" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "RESOURCE_STALLS.ROB_FULL", + "SampleAfterValue": "2000000", + "BriefDescription": "ROB full stall cycles" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "RESOURCE_STALLS.RS_FULL", + "SampleAfterValue": "2000000", + "BriefDescription": "Reservation Station full stall cycles" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "RESOURCE_STALLS.STORE", + "SampleAfterValue": "2000000", + "BriefDescription": "Store buffer stall cycles" + }, + { + "PEBS": "1", + "EventCode": "0xC7", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC7", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC7", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC7", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)" + }, + { + "EventCode": "0xDB", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOP_UNFUSION", + "SampleAfterValue": "2000000", + "BriefDescription": "Uop unfusions due to FP exceptions" + }, + { + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "UOPS_DECODED.ESP_FOLDING", + "SampleAfterValue": "2000000", + "BriefDescription": "Stack pointer instructions decoded" + }, + { + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "UOPS_DECODED.ESP_SYNC", + "SampleAfterValue": "2000000", + "BriefDescription": "Stack pointer sync operations" + }, + { + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops decoded by Microcode Sequencer", + "CounterMask": "1" + }, + { + "EventCode": "0xD1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_DECODED.STALL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles no Uops are decoded", + "CounterMask": "1" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x3f", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles Uops executed on any port (core count)", + "CounterMask": "1" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x1f", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)", + "CounterMask": "1" + }, + { + "EventCode": "0xB1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x3f", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops executed on any port (core count)", + "CounterMask": "1", + "EdgeDetect": "1" + }, + { + "EventCode": "0xB1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1f", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops executed on ports 0-4 (core count)", + "CounterMask": "1", + "EdgeDetect": "1" + }, + { + "EventCode": "0xB1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x3f", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles no Uops issued on any port (core count)", + "CounterMask": "1" + }, + { + "EventCode": "0xB1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1f", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)", + "CounterMask": "1" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_EXECUTED.PORT0", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops executed on port 0" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "UOPS_EXECUTED.PORT015", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops issued on ports 0, 1 or 5" + }, + { + "EventCode": "0xB1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5", + "CounterMask": "1" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.PORT1", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops executed on port 1" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x4", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.PORT2_CORE", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops executed on port 2 (core count)" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x80", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.PORT234_CORE", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops issued on ports 2, 3 or 4" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x8", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.PORT3_CORE", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops executed on port 3 (core count)" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x10", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.PORT4_CORE", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops executed on port 4 (core count)" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "UOPS_EXECUTED.PORT5", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops executed on port 5" + }, + { + "EventCode": "0xE", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_ISSUED.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops issued" + }, + { + "EventCode": "0xE", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles no Uops were issued on any thread", + "CounterMask": "1" + }, + { + "EventCode": "0xE", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles Uops were issued on either thread", + "CounterMask": "1" + }, + { + "EventCode": "0xE", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_ISSUED.FUSED", + "SampleAfterValue": "2000000", + "BriefDescription": "Fused Uops issued" + }, + { + "EventCode": "0xE", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles no Uops were issued", + "CounterMask": "1" + }, + { + "PEBS": "1", + "EventCode": "0xC2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.ACTIVE_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles Uops are being retired", + "CounterMask": "1" + }, + { + "PEBS": "1", + "EventCode": "0xC2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops retired (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "UOPS_RETIRED.MACRO_FUSED", + "SampleAfterValue": "2000000", + "BriefDescription": "Macro-fused Uops retired (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "SampleAfterValue": "2000000", + "BriefDescription": "Retirement slots used (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC2", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles Uops are not retiring (Precise Event)", + "CounterMask": "1" + }, + { + "PEBS": "1", + "EventCode": "0xC2", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Total cycles using precise uop retired event (Precise Event)", + "CounterMask": "16" + }, + { + "PEBS": "2", + "EventCode": "0xC0", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "INST_RETIRED.TOTAL_CYCLES_PS", + "SampleAfterValue": "2000000", + "BriefDescription": "Total cycles (Precise Event)", + "CounterMask": "16" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/virtual-memory.json b/tools/perf/pmu-events/arch/x86/nehalemep/virtual-memory.json new file mode 100644 index 000000000000..0596094e0ee9 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/nehalemep/virtual-memory.json @@ -0,0 +1,109 @@ +[ + { + "EventCode": "0x8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "DTLB_LOAD_MISSES.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB load misses" + }, + { + "EventCode": "0x8", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "DTLB_LOAD_MISSES.PDE_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB load miss caused by low part of address" + }, + { + "EventCode": "0x8", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "SampleAfterValue": "2000000", + "BriefDescription": "DTLB second level hit" + }, + { + "EventCode": "0x8", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB load miss page walks complete" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "DTLB_MISSES.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB misses" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "DTLB_MISSES.STLB_HIT", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB first level misses but second level hit" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "DTLB_MISSES.WALK_COMPLETED", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB miss page walks" + }, + { + "EventCode": "0xAE", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ITLB_FLUSH", + "SampleAfterValue": "2000000", + "BriefDescription": "ITLB flushes" + }, + { + "PEBS": "1", + "EventCode": "0xC8", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "ITLB_MISS_RETIRED", + "SampleAfterValue": "200000", + "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)" + }, + { + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ITLB_MISSES.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "ITLB miss" + }, + { + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "SampleAfterValue": "200000", + "BriefDescription": "ITLB miss page walks" + }, + { + "PEBS": "1", + "EventCode": "0xCB", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "MEM_LOAD_RETIRED.DTLB_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "Retired loads that miss the DTLB (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_STORE_RETIRED.DTLB_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "Retired stores that miss the DTLB (Precise Event)" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/cache.json b/tools/perf/pmu-events/arch/x86/nehalemex/cache.json new file mode 100644 index 000000000000..21a0f8fd057e --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/nehalemex/cache.json @@ -0,0 +1,3184 @@ +[ + { + "EventCode": "0x63", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "CACHE_LOCK_CYCLES.L1D", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles L1D locked" + }, + { + "EventCode": "0x63", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "CACHE_LOCK_CYCLES.L1D_L2", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles L1D and L2 locked" + }, + { + "EventCode": "0x51", + "Counter": "0,1", + "UMask": "0x4", + "EventName": "L1D.M_EVICT", + "SampleAfterValue": "2000000", + "BriefDescription": "L1D cache lines replaced in M state" + }, + { + "EventCode": "0x51", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "L1D.M_REPL", + "SampleAfterValue": "2000000", + "BriefDescription": "L1D cache lines allocated in the M state" + }, + { + "EventCode": "0x51", + "Counter": "0,1", + "UMask": "0x8", + "EventName": "L1D.M_SNOOP_EVICT", + "SampleAfterValue": "2000000", + "BriefDescription": "L1D snoop eviction of cache lines in M state" + }, + { + "EventCode": "0x51", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "L1D.REPL", + "SampleAfterValue": "2000000", + "BriefDescription": "L1 data cache lines allocated" + }, + { + "EventCode": "0x43", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "L1D_ALL_REF.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "All references to the L1 data cache" + }, + { + "EventCode": "0x43", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "L1D_ALL_REF.CACHEABLE", + "SampleAfterValue": "2000000", + "BriefDescription": "L1 data cacheable reads and writes" + }, + { + "EventCode": "0x40", + "Counter": "0,1", + "UMask": "0x4", + "EventName": "L1D_CACHE_LD.E_STATE", + "SampleAfterValue": "2000000", + "BriefDescription": "L1 data cache read in E state" + }, + { + "EventCode": "0x40", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "L1D_CACHE_LD.I_STATE", + "SampleAfterValue": "2000000", + "BriefDescription": "L1 data cache read in I state (misses)" + }, + { + "EventCode": "0x40", + "Counter": "0,1", + "UMask": "0x8", + "EventName": "L1D_CACHE_LD.M_STATE", + "SampleAfterValue": "2000000", + "BriefDescription": "L1 data cache read in M state" + }, + { + "EventCode": "0x40", + "Counter": "0,1", + "UMask": "0xf", + "EventName": "L1D_CACHE_LD.MESI", + "SampleAfterValue": "2000000", + "BriefDescription": "L1 data cache reads" + }, + { + "EventCode": "0x40", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "L1D_CACHE_LD.S_STATE", + "SampleAfterValue": "2000000", + "BriefDescription": "L1 data cache read in S state" + }, + { + "EventCode": "0x42", + "Counter": "0,1", + "UMask": "0x4", + "EventName": "L1D_CACHE_LOCK.E_STATE", + "SampleAfterValue": "2000000", + "BriefDescription": "L1 data cache load locks in E state" + }, + { + "EventCode": "0x42", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "L1D_CACHE_LOCK.HIT", + "SampleAfterValue": "2000000", + "BriefDescription": "L1 data cache load lock hits" + }, + { + "EventCode": "0x42", + "Counter": "0,1", + "UMask": "0x8", + "EventName": "L1D_CACHE_LOCK.M_STATE", + "SampleAfterValue": "2000000", + "BriefDescription": "L1 data cache load locks in M state" + }, + { + "EventCode": "0x42", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "L1D_CACHE_LOCK.S_STATE", + "SampleAfterValue": "2000000", + "BriefDescription": "L1 data cache load locks in S state" + }, + { + "EventCode": "0x53", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "L1D_CACHE_LOCK_FB_HIT", + "SampleAfterValue": "2000000", + "BriefDescription": "L1D load lock accepted in fill buffer" + }, + { + "EventCode": "0x52", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT", + "SampleAfterValue": "2000000", + "BriefDescription": "L1D prefetch load lock accepted in fill buffer" + }, + { + "EventCode": "0x41", + "Counter": "0,1", + "UMask": "0x4", + "EventName": "L1D_CACHE_ST.E_STATE", + "SampleAfterValue": "2000000", + "BriefDescription": "L1 data cache stores in E state" + }, + { + "EventCode": "0x41", + "Counter": "0,1", + "UMask": "0x8", + "EventName": "L1D_CACHE_ST.M_STATE", + "SampleAfterValue": "2000000", + "BriefDescription": "L1 data cache stores in M state" + }, + { + "EventCode": "0x41", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "L1D_CACHE_ST.S_STATE", + "SampleAfterValue": "2000000", + "BriefDescription": "L1 data cache stores in S state" + }, + { + "EventCode": "0x4E", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "L1D_PREFETCH.MISS", + "SampleAfterValue": "200000", + "BriefDescription": "L1D hardware prefetch misses" + }, + { + "EventCode": "0x4E", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "L1D_PREFETCH.REQUESTS", + "SampleAfterValue": "200000", + "BriefDescription": "L1D hardware prefetch requests" + }, + { + "EventCode": "0x4E", + "Counter": "0,1", + "UMask": "0x4", + "EventName": "L1D_PREFETCH.TRIGGERS", + "SampleAfterValue": "200000", + "BriefDescription": "L1D hardware prefetch requests triggered" + }, + { + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L1D_WB_L2.E_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L1 writebacks to L2 in E state" + }, + { + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L1D_WB_L2.I_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L1 writebacks to L2 in I state (misses)" + }, + { + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L1D_WB_L2.M_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L1 writebacks to L2 in M state" + }, + { + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "L1D_WB_L2.MESI", + "SampleAfterValue": "100000", + "BriefDescription": "All L1 writebacks to L2" + }, + { + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L1D_WB_L2.S_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L1 writebacks to L2 in S state" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0xff", + "EventName": "L2_DATA_RQSTS.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "All L2 data requests" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data demand loads in E state" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data demand loads in I state (misses)" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data demand loads in M state" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "L2_DATA_RQSTS.DEMAND.MESI", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data demand requests" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data demand loads in S state" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data prefetches in E state" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data prefetches in the I state (misses)" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data prefetches in M state" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0xf0", + "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", + "SampleAfterValue": "200000", + "BriefDescription": "All L2 data prefetches" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data prefetches in the S state" + }, + { + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x7", + "EventName": "L2_LINES_IN.ANY", + "SampleAfterValue": "100000", + "BriefDescription": "L2 lines alloacated" + }, + { + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_LINES_IN.E_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 lines allocated in the E state" + }, + { + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_LINES_IN.S_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 lines allocated in the S state" + }, + { + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "L2_LINES_OUT.ANY", + "SampleAfterValue": "100000", + "BriefDescription": "L2 lines evicted" + }, + { + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_LINES_OUT.DEMAND_CLEAN", + "SampleAfterValue": "100000", + "BriefDescription": "L2 lines evicted by a demand request" + }, + { + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_LINES_OUT.DEMAND_DIRTY", + "SampleAfterValue": "100000", + "BriefDescription": "L2 modified lines evicted by a demand request" + }, + { + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_LINES_OUT.PREFETCH_CLEAN", + "SampleAfterValue": "100000", + "BriefDescription": "L2 lines evicted by a prefetch request" + }, + { + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_LINES_OUT.PREFETCH_DIRTY", + "SampleAfterValue": "100000", + "BriefDescription": "L2 modified lines evicted by a prefetch request" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "L2_RQSTS.IFETCH_HIT", + "SampleAfterValue": "200000", + "BriefDescription": "L2 instruction fetch hits" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "L2_RQSTS.IFETCH_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "L2 instruction fetch misses" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "L2_RQSTS.IFETCHES", + "SampleAfterValue": "200000", + "BriefDescription": "L2 instruction fetches" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_RQSTS.LD_HIT", + "SampleAfterValue": "200000", + "BriefDescription": "L2 load hits" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_RQSTS.LD_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "L2 load misses" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x3", + "EventName": "L2_RQSTS.LOADS", + "SampleAfterValue": "200000", + "BriefDescription": "L2 requests" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xaa", + "EventName": "L2_RQSTS.MISS", + "SampleAfterValue": "200000", + "BriefDescription": "All L2 misses" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "L2_RQSTS.PREFETCH_HIT", + "SampleAfterValue": "200000", + "BriefDescription": "L2 prefetch hits" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "L2_RQSTS.PREFETCH_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "L2 prefetch misses" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xc0", + "EventName": "L2_RQSTS.PREFETCHES", + "SampleAfterValue": "200000", + "BriefDescription": "All L2 prefetches" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xff", + "EventName": "L2_RQSTS.REFERENCES", + "SampleAfterValue": "200000", + "BriefDescription": "All L2 requests" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_RQSTS.RFO_HIT", + "SampleAfterValue": "200000", + "BriefDescription": "L2 RFO hits" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_RQSTS.RFO_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "L2 RFO misses" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xc", + "EventName": "L2_RQSTS.RFOS", + "SampleAfterValue": "200000", + "BriefDescription": "L2 RFO requests" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "L2_TRANSACTIONS.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "All L2 transactions" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "L2_TRANSACTIONS.FILL", + "SampleAfterValue": "200000", + "BriefDescription": "L2 fill transactions" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_TRANSACTIONS.IFETCH", + "SampleAfterValue": "200000", + "BriefDescription": "L2 instruction fetch transactions" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "L2_TRANSACTIONS.L1D_WB", + "SampleAfterValue": "200000", + "BriefDescription": "L1D writeback to L2 transactions" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_TRANSACTIONS.LOAD", + "SampleAfterValue": "200000", + "BriefDescription": "L2 Load transactions" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_TRANSACTIONS.PREFETCH", + "SampleAfterValue": "200000", + "BriefDescription": "L2 prefetch transactions" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_TRANSACTIONS.RFO", + "SampleAfterValue": "200000", + "BriefDescription": "L2 RFO transactions" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "L2_TRANSACTIONS.WB", + "SampleAfterValue": "200000", + "BriefDescription": "L2 writeback to LLC transactions" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "L2_WRITE.LOCK.E_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 demand lock RFOs in E state" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0xe0", + "EventName": "L2_WRITE.LOCK.HIT", + "SampleAfterValue": "100000", + "BriefDescription": "All demand L2 lock RFOs that hit the cache" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "L2_WRITE.LOCK.I_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 demand lock RFOs in I state (misses)" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "L2_WRITE.LOCK.M_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 demand lock RFOs in M state" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0xf0", + "EventName": "L2_WRITE.LOCK.MESI", + "SampleAfterValue": "100000", + "BriefDescription": "All demand L2 lock RFOs" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "L2_WRITE.LOCK.S_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 demand lock RFOs in S state" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0xe", + "EventName": "L2_WRITE.RFO.HIT", + "SampleAfterValue": "100000", + "BriefDescription": "All L2 demand store RFOs that hit the cache" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_WRITE.RFO.I_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 demand store RFOs in I state (misses)" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_WRITE.RFO.M_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 demand store RFOs in M state" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "L2_WRITE.RFO.MESI", + "SampleAfterValue": "100000", + "BriefDescription": "All L2 demand store RFOs" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_WRITE.RFO.S_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 demand store RFOs in S state" + }, + { + "EventCode": "0x2E", + "Counter": "0,1,2,3", + "UMask": "0x41", + "EventName": "LONGEST_LAT_CACHE.MISS", + "SampleAfterValue": "100000", + "BriefDescription": "Longest latency cache miss" + }, + { + "EventCode": "0x2E", + "Counter": "0,1,2,3", + "UMask": "0x4f", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "SampleAfterValue": "200000", + "BriefDescription": "Longest latency cache reference" + }, + { + "PEBS": "1", + "EventCode": "0xB", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_INST_RETIRED.LOADS", + "SampleAfterValue": "2000000", + "BriefDescription": "Instructions retired which contains a load (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xB", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MEM_INST_RETIRED.STORES", + "SampleAfterValue": "2000000", + "BriefDescription": "Instructions retired which contains a store (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xCB", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "MEM_LOAD_RETIRED.HIT_LFB", + "SampleAfterValue": "200000", + "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xCB", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_LOAD_RETIRED.L1D_HIT", + "SampleAfterValue": "2000000", + "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xCB", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MEM_LOAD_RETIRED.L2_HIT", + "SampleAfterValue": "200000", + "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xCB", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "MEM_LOAD_RETIRED.LLC_MISS", + "SampleAfterValue": "10000", + "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xCB", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", + "SampleAfterValue": "40000", + "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xCB", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", + "SampleAfterValue": "40000", + "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)" + }, + { + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore L1 data cache writebacks" + }, + { + "EventCode": "0xB2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS_SQ_FULL", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests blocked due to Super Queue full" + }, + { + "EventCode": "0xF4", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "SQ_MISC.SPLIT_LOCK", + "SampleAfterValue": "2000000", + "BriefDescription": "Super Queue lock splits across a cache line" + }, + { + "EventCode": "0x6", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "STORE_BLOCKS.AT_RET", + "SampleAfterValue": "200000", + "BriefDescription": "Loads delayed with at-Retirement block code" + }, + { + "EventCode": "0x6", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "STORE_BLOCKS.L1D_BLOCK", + "SampleAfterValue": "200000", + "BriefDescription": "Cacheable loads delayed with L1D block code" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x0", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", + "MSRIndex": "0x3F6", + "SampleAfterValue": "2000000", + "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x400", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", + "MSRIndex": "0x3F6", + "SampleAfterValue": "100", + "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x80", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", + "MSRIndex": "0x3F6", + "SampleAfterValue": "1000", + "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x10", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", + "MSRIndex": "0x3F6", + "SampleAfterValue": "10000", + "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x4000", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", + "MSRIndex": "0x3F6", + "SampleAfterValue": "5", + "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x800", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", + "MSRIndex": "0x3F6", + "SampleAfterValue": "50", + "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x100", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", + "MSRIndex": "0x3F6", + "SampleAfterValue": "500", + "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x20", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", + "MSRIndex": "0x3F6", + "SampleAfterValue": "5000", + "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x8000", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", + "MSRIndex": "0x3F6", + "SampleAfterValue": "3", + "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x4", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", + "MSRIndex": "0x3F6", + "SampleAfterValue": "50000", + "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x1000", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", + "MSRIndex": "0x3F6", + "SampleAfterValue": "20", + "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x200", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", + "MSRIndex": "0x3F6", + "SampleAfterValue": "200", + "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x40", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", + "MSRIndex": "0x3F6", + "SampleAfterValue": "2000", + "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x8", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", + "MSRIndex": "0x3F6", + "SampleAfterValue": "20000", + "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x2000", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", + "MSRIndex": "0x3F6", + "SampleAfterValue": "10", + "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F11", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by any cache or DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF11", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore data reads", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8011", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x111", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x211", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x411", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x711", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4711", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1811", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3811", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1011", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x811", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F44", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by any cache or DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF44", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore code reads", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8044", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x144", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x244", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x444", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x744", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4744", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1844", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3844", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1044", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x844", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7FFF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by any cache or DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFFFF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore requests", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x80FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x47FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x18FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x38FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x10FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F22", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF22", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore RFO requests", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8022", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x122", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x222", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x422", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x722", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4722", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1822", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3822", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1022", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x822", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F08", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to any cache or DRAM.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF08", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore writebacks", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8008", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x108", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x408", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x708", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4708", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1808", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3808", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1008", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x808", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F77", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF77", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore code or data read requests", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8077", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x177", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x277", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x477", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x777", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4777", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1877", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3877", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1077", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x877", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F33", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore request = all data, response = any cache_dram", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF33", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore request = all data, response = any location", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8033", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x133", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x233", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x433", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x733", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore request = all data, response = local cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4733", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore request = all data, response = local cache or dram", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1833", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore request = all data, response = remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3833", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore request = all data, response = remote cache or dram", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1033", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads, RFO's and prefetches that HIT in a remote cache ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x833", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads, RFO's and prefetches that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F03", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF03", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore demand data requests", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8003", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x103", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x203", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x403", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x703", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4703", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1803", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3803", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1003", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x803", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F01", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF01", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore demand data reads", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8001", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x101", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x201", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x401", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x701", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4701", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1801", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3801", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1001", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x801", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F04", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF04", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore demand code reads", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8004", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x104", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x204", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x404", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x704", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4704", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1804", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3804", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1004", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x804", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F02", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF02", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore demand RFO requests", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8002", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x102", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x202", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x402", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x702", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4702", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1802", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3802", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1002", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x802", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F80", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF80", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore other requests", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8080", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x180", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x280", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x480", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x780", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4780", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1880", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3880", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1080", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x880", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F30", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF30", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore prefetch data requests", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8030", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x130", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x230", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x430", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x730", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4730", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1830", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3830", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1030", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x830", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F10", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF10", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore prefetch data reads", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8010", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x110", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x210", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x410", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x710", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4710", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1810", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3810", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1010", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x810", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F40", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF40", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore prefetch code reads", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8040", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x140", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x240", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x440", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x740", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4740", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1840", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3840", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1040", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x840", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F20", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF20", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore prefetch RFO requests", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8020", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x120", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x220", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x420", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x720", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4720", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1820", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3820", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1020", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x820", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F70", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF70", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore prefetch requests", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8070", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x170", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x270", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x470", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x770", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4770", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1870", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3870", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1070", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x870", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests that HITM in a remote cache", + "Offcore": "1" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/floating-point.json b/tools/perf/pmu-events/arch/x86/nehalemex/floating-point.json new file mode 100644 index 000000000000..7d2f71a9dee3 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/nehalemex/floating-point.json @@ -0,0 +1,229 @@ +[ + { + "PEBS": "1", + "EventCode": "0xF7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "FP_ASSIST.ALL", + "SampleAfterValue": "20000", + "BriefDescription": "X87 Floating point assists (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xF7", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "FP_ASSIST.INPUT", + "SampleAfterValue": "20000", + "BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xF7", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "FP_ASSIST.OUTPUT", + "SampleAfterValue": "20000", + "BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "FP_COMP_OPS_EXE.MMX", + "SampleAfterValue": "2000000", + "BriefDescription": "MMX Uops" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION", + "SampleAfterValue": "2000000", + "BriefDescription": "SSE* FP double precision Uops" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "FP_COMP_OPS_EXE.SSE_FP", + "SampleAfterValue": "2000000", + "BriefDescription": "SSE and SSE2 FP Uops" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED", + "SampleAfterValue": "2000000", + "BriefDescription": "SSE FP packed Uops" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR", + "SampleAfterValue": "2000000", + "BriefDescription": "SSE FP scalar Uops" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION", + "SampleAfterValue": "2000000", + "BriefDescription": "SSE* FP single precision Uops" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER", + "SampleAfterValue": "2000000", + "BriefDescription": "SSE2 integer Uops" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "FP_COMP_OPS_EXE.X87", + "SampleAfterValue": "2000000", + "BriefDescription": "Computational floating-point operations executed" + }, + { + "EventCode": "0xCC", + "Counter": "0,1,2,3", + "UMask": "0x3", + "EventName": "FP_MMX_TRANS.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "All Floating Point to and from MMX transitions" + }, + { + "EventCode": "0xCC", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "FP_MMX_TRANS.TO_FP", + "SampleAfterValue": "2000000", + "BriefDescription": "Transitions from MMX to Floating Point instructions" + }, + { + "EventCode": "0xCC", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "FP_MMX_TRANS.TO_MMX", + "SampleAfterValue": "2000000", + "BriefDescription": "Transitions from Floating Point to MMX instructions" + }, + { + "EventCode": "0x12", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "SIMD_INT_128.PACK", + "SampleAfterValue": "200000", + "BriefDescription": "128 bit SIMD integer pack operations" + }, + { + "EventCode": "0x12", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "SIMD_INT_128.PACKED_ARITH", + "SampleAfterValue": "200000", + "BriefDescription": "128 bit SIMD integer arithmetic operations" + }, + { + "EventCode": "0x12", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "SIMD_INT_128.PACKED_LOGICAL", + "SampleAfterValue": "200000", + "BriefDescription": "128 bit SIMD integer logical operations" + }, + { + "EventCode": "0x12", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "SIMD_INT_128.PACKED_MPY", + "SampleAfterValue": "200000", + "BriefDescription": "128 bit SIMD integer multiply operations" + }, + { + "EventCode": "0x12", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "SIMD_INT_128.PACKED_SHIFT", + "SampleAfterValue": "200000", + "BriefDescription": "128 bit SIMD integer shift operations" + }, + { + "EventCode": "0x12", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "SIMD_INT_128.SHUFFLE_MOVE", + "SampleAfterValue": "200000", + "BriefDescription": "128 bit SIMD integer shuffle/move operations" + }, + { + "EventCode": "0x12", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "SIMD_INT_128.UNPACK", + "SampleAfterValue": "200000", + "BriefDescription": "128 bit SIMD integer unpack operations" + }, + { + "EventCode": "0xFD", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "SIMD_INT_64.PACK", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD integer 64 bit pack operations" + }, + { + "EventCode": "0xFD", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "SIMD_INT_64.PACKED_ARITH", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD integer 64 bit arithmetic operations" + }, + { + "EventCode": "0xFD", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "SIMD_INT_64.PACKED_LOGICAL", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD integer 64 bit logical operations" + }, + { + "EventCode": "0xFD", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "SIMD_INT_64.PACKED_MPY", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD integer 64 bit packed multiply operations" + }, + { + "EventCode": "0xFD", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "SIMD_INT_64.PACKED_SHIFT", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD integer 64 bit shift operations" + }, + { + "EventCode": "0xFD", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "SIMD_INT_64.SHUFFLE_MOVE", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD integer 64 bit shuffle/move operations" + }, + { + "EventCode": "0xFD", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "SIMD_INT_64.UNPACK", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD integer 64 bit unpack operations" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/frontend.json b/tools/perf/pmu-events/arch/x86/nehalemex/frontend.json new file mode 100644 index 000000000000..e5e21e03444d --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/nehalemex/frontend.json @@ -0,0 +1,26 @@ +[ + { + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MACRO_INSTS.DECODED", + "SampleAfterValue": "2000000", + "BriefDescription": "Instructions decoded" + }, + { + "EventCode": "0xA6", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MACRO_INSTS.FUSIONS_DECODED", + "SampleAfterValue": "2000000", + "BriefDescription": "Macro-fused instructions decoded" + }, + { + "EventCode": "0x19", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "TWO_UOP_INSTS_DECODED", + "SampleAfterValue": "2000000", + "BriefDescription": "Two Uop instructions decoded" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/memory.json b/tools/perf/pmu-events/arch/x86/nehalemex/memory.json new file mode 100644 index 000000000000..f914a4525b65 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/nehalemex/memory.json @@ -0,0 +1,739 @@ +[ + { + "EventCode": "0xB7", + "MSRValue": "0x6011", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF811", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4011", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2011", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6044", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF844", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4044", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2044", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x60FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF8FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x40FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x20FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6022", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF822", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4022", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2022", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6008", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF808", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4008", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2008", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6077", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF877", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4077", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2077", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6033", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore request = all data, response = any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF833", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore request = all data, response = any LLC miss", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4033", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the local DRAM.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2033", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6003", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF803", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4003", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2003", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6001", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF801", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4001", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2001", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6004", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF804", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4004", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2004", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6002", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF802", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4002", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2002", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6080", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF880", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2080", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6030", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF830", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4030", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2030", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6010", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF810", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4010", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2010", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6040", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF840", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4040", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2040", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6020", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF820", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4020", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2020", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6070", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF870", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4070", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2070", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by a remote DRAM", + "Offcore": "1" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/other.json b/tools/perf/pmu-events/arch/x86/nehalemex/other.json new file mode 100644 index 000000000000..af0860622445 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/nehalemex/other.json @@ -0,0 +1,210 @@ +[ + { + "EventCode": "0xE8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BPU_CLEARS.EARLY", + "SampleAfterValue": "2000000", + "BriefDescription": "Early Branch Prediciton Unit clears" + }, + { + "EventCode": "0xE8", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "BPU_CLEARS.LATE", + "SampleAfterValue": "2000000", + "BriefDescription": "Late Branch Prediction Unit clears" + }, + { + "EventCode": "0xE5", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BPU_MISSED_CALL_RET", + "SampleAfterValue": "2000000", + "BriefDescription": "Branch prediction unit missed call or return" + }, + { + "EventCode": "0xD5", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ES_REG_RENAMES", + "SampleAfterValue": "2000000", + "BriefDescription": "ES segment renames" + }, + { + "EventCode": "0x6C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IO_TRANSACTIONS", + "SampleAfterValue": "2000000", + "BriefDescription": "I/O transactions" + }, + { + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L1I.CYCLES_STALLED", + "SampleAfterValue": "2000000", + "BriefDescription": "L1I instruction fetch stall cycles" + }, + { + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L1I.HITS", + "SampleAfterValue": "2000000", + "BriefDescription": "L1I instruction fetch hits" + }, + { + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L1I.MISSES", + "SampleAfterValue": "2000000", + "BriefDescription": "L1I instruction fetch misses" + }, + { + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x3", + "EventName": "L1I.READS", + "SampleAfterValue": "2000000", + "BriefDescription": "L1I Instruction fetches" + }, + { + "EventCode": "0x82", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LARGE_ITLB.HIT", + "SampleAfterValue": "200000", + "BriefDescription": "Large ITLB hit" + }, + { + "EventCode": "0x13", + "Counter": "0,1,2,3", + "UMask": "0x7", + "EventName": "LOAD_DISPATCH.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "All loads dispatched" + }, + { + "EventCode": "0x13", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "LOAD_DISPATCH.MOB", + "SampleAfterValue": "2000000", + "BriefDescription": "Loads dispatched from the MOB" + }, + { + "EventCode": "0x13", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LOAD_DISPATCH.RS", + "SampleAfterValue": "2000000", + "BriefDescription": "Loads dispatched that bypass the MOB" + }, + { + "EventCode": "0x13", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "LOAD_DISPATCH.RS_DELAYED", + "SampleAfterValue": "2000000", + "BriefDescription": "Loads dispatched from stage 305" + }, + { + "EventCode": "0x7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "PARTIAL_ADDRESS_ALIAS", + "SampleAfterValue": "200000", + "BriefDescription": "False dependencies due to partial address aliasing" + }, + { + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "RAT_STALLS.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "All RAT stall cycles" + }, + { + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "RAT_STALLS.FLAGS", + "SampleAfterValue": "2000000", + "BriefDescription": "Flag stall cycles" + }, + { + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "RAT_STALLS.REGISTERS", + "SampleAfterValue": "2000000", + "BriefDescription": "Partial register stall cycles" + }, + { + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "RAT_STALLS.ROB_READ_PORT", + "SampleAfterValue": "2000000", + "BriefDescription": "ROB read port stalls cycles" + }, + { + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "RAT_STALLS.SCOREBOARD", + "SampleAfterValue": "2000000", + "BriefDescription": "Scoreboard stall cycles" + }, + { + "EventCode": "0x4", + "Counter": "0,1,2,3", + "UMask": "0x7", + "EventName": "SB_DRAIN.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "All Store buffer stall cycles" + }, + { + "EventCode": "0xD4", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "SEG_RENAME_STALLS", + "SampleAfterValue": "2000000", + "BriefDescription": "Segment rename stall cycles" + }, + { + "EventCode": "0xB8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "SNOOP_RESPONSE.HIT", + "SampleAfterValue": "100000", + "BriefDescription": "Thread responded HIT to snoop" + }, + { + "EventCode": "0xB8", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "SNOOP_RESPONSE.HITE", + "SampleAfterValue": "100000", + "BriefDescription": "Thread responded HITE to snoop" + }, + { + "EventCode": "0xB8", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "SNOOP_RESPONSE.HITM", + "SampleAfterValue": "100000", + "BriefDescription": "Thread responded HITM to snoop" + }, + { + "EventCode": "0xF6", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "SQ_FULL_STALL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Super Queue full stall cycles" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/pipeline.json b/tools/perf/pmu-events/arch/x86/nehalemex/pipeline.json new file mode 100644 index 000000000000..41006ddcd893 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/nehalemex/pipeline.json @@ -0,0 +1,881 @@ +[ + { + "EventCode": "0x14", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ARITH.CYCLES_DIV_BUSY", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles the divider is busy" + }, + { + "EventCode": "0x14", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ARITH.DIV", + "SampleAfterValue": "2000000", + "BriefDescription": "Divide Operations executed", + "CounterMask": "1", + "EdgeDetect": "1" + }, + { + "EventCode": "0x14", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "ARITH.MUL", + "SampleAfterValue": "2000000", + "BriefDescription": "Multiply operations executed" + }, + { + "EventCode": "0xE6", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "BACLEAR.BAD_TARGET", + "SampleAfterValue": "2000000", + "BriefDescription": "BACLEAR asserted with bad target address" + }, + { + "EventCode": "0xE6", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BACLEAR.CLEAR", + "SampleAfterValue": "2000000", + "BriefDescription": "BACLEAR asserted, regardless of cause " + }, + { + "EventCode": "0xA7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BACLEAR_FORCE_IQ", + "SampleAfterValue": "2000000", + "BriefDescription": "Instruction queue forced BACLEAR" + }, + { + "EventCode": "0xE0", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BR_INST_DECODED", + "SampleAfterValue": "2000000", + "BriefDescription": "Branch instructions decoded" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x7f", + "EventName": "BR_INST_EXEC.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "Branch instructions executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BR_INST_EXEC.COND", + "SampleAfterValue": "200000", + "BriefDescription": "Conditional branch instructions executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "BR_INST_EXEC.DIRECT", + "SampleAfterValue": "200000", + "BriefDescription": "Unconditional branches executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL", + "SampleAfterValue": "20000", + "BriefDescription": "Unconditional call branches executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL", + "SampleAfterValue": "20000", + "BriefDescription": "Indirect call branches executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL", + "SampleAfterValue": "20000", + "BriefDescription": "Indirect non call branches executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "BR_INST_EXEC.NEAR_CALLS", + "SampleAfterValue": "20000", + "BriefDescription": "Call branches executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x7", + "EventName": "BR_INST_EXEC.NON_CALLS", + "SampleAfterValue": "200000", + "BriefDescription": "All non call branches executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "BR_INST_EXEC.RETURN_NEAR", + "SampleAfterValue": "20000", + "BriefDescription": "Indirect return branches executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "BR_INST_EXEC.TAKEN", + "SampleAfterValue": "200000", + "BriefDescription": "Taken branches executed" + }, + { + "PEBS": "1", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "SampleAfterValue": "200000", + "BriefDescription": "Retired branch instructions (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BR_INST_RETIRED.CONDITIONAL", + "SampleAfterValue": "200000", + "BriefDescription": "Retired conditional branch instructions (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "SampleAfterValue": "20000", + "BriefDescription": "Retired near call instructions (Precise Event)" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x7f", + "EventName": "BR_MISP_EXEC.ANY", + "SampleAfterValue": "20000", + "BriefDescription": "Mispredicted branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BR_MISP_EXEC.COND", + "SampleAfterValue": "20000", + "BriefDescription": "Mispredicted conditional branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "BR_MISP_EXEC.DIRECT", + "SampleAfterValue": "20000", + "BriefDescription": "Mispredicted unconditional branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL", + "SampleAfterValue": "2000", + "BriefDescription": "Mispredicted non call branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL", + "SampleAfterValue": "2000", + "BriefDescription": "Mispredicted indirect call branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL", + "SampleAfterValue": "2000", + "BriefDescription": "Mispredicted indirect non call branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "BR_MISP_EXEC.NEAR_CALLS", + "SampleAfterValue": "2000", + "BriefDescription": "Mispredicted call branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x7", + "EventName": "BR_MISP_EXEC.NON_CALLS", + "SampleAfterValue": "20000", + "BriefDescription": "Mispredicted non call branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "BR_MISP_EXEC.RETURN_NEAR", + "SampleAfterValue": "2000", + "BriefDescription": "Mispredicted return branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "BR_MISP_EXEC.TAKEN", + "SampleAfterValue": "20000", + "BriefDescription": "Mispredicted taken branches executed" + }, + { + "PEBS": "1", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "BR_MISP_RETIRED.NEAR_CALL", + "SampleAfterValue": "2000", + "BriefDescription": "Mispredicted near retired calls (Precise Event)" + }, + { + "EventCode": "0x0", + "Counter": "Fixed counter 3", + "UMask": "0x0", + "EventName": "CPU_CLK_UNHALTED.REF", + "SampleAfterValue": "2000000", + "BriefDescription": "Reference cycles when thread is not halted (fixed counter)" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CPU_CLK_UNHALTED.REF_P", + "SampleAfterValue": "100000", + "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)" + }, + { + "EventCode": "0x0", + "Counter": "Fixed counter 2", + "UMask": "0x0", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles when thread is not halted (fixed counter)" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles when thread is not halted (programmable counter)" + }, + { + "EventCode": "0x3C", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Total CPU cycles", + "CounterMask": "2" + }, + { + "EventCode": "0x87", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "ILD_STALL.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "Any Instruction Length Decoder stall cycles" + }, + { + "EventCode": "0x87", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "ILD_STALL.IQ_FULL", + "SampleAfterValue": "2000000", + "BriefDescription": "Instruction Queue full stall cycles" + }, + { + "EventCode": "0x87", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ILD_STALL.LCP", + "SampleAfterValue": "2000000", + "BriefDescription": "Length Change Prefix stall cycles" + }, + { + "EventCode": "0x87", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "ILD_STALL.MRU", + "SampleAfterValue": "2000000", + "BriefDescription": "Stall cycles due to BPU MRU bypass" + }, + { + "EventCode": "0x87", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "ILD_STALL.REGEN", + "SampleAfterValue": "2000000", + "BriefDescription": "Regen stall cycles" + }, + { + "EventCode": "0x18", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "INST_DECODED.DEC0", + "SampleAfterValue": "2000000", + "BriefDescription": "Instructions that must be decoded by decoder 0" + }, + { + "EventCode": "0x1E", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "INST_QUEUE_WRITE_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles instructions are written to the instruction queue" + }, + { + "EventCode": "0x17", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "INST_QUEUE_WRITES", + "SampleAfterValue": "2000000", + "BriefDescription": "Instructions written to instruction queue." + }, + { + "EventCode": "0x0", + "Counter": "Fixed counter 1", + "UMask": "0x0", + "EventName": "INST_RETIRED.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "Instructions retired (fixed counter)" + }, + { + "PEBS": "1", + "EventCode": "0xC0", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "INST_RETIRED.ANY_P", + "SampleAfterValue": "2000000", + "BriefDescription": "Instructions retired (Programmable counter and Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC0", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "INST_RETIRED.MMX", + "SampleAfterValue": "2000000", + "BriefDescription": "Retired MMX instructions (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC0", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "INST_RETIRED.TOTAL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Total cycles (Precise Event)", + "CounterMask": "16" + }, + { + "PEBS": "1", + "EventCode": "0xC0", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "INST_RETIRED.X87", + "SampleAfterValue": "2000000", + "BriefDescription": "Retired floating-point operations (Precise Event)" + }, + { + "EventCode": "0x4C", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "LOAD_HIT_PRE", + "SampleAfterValue": "200000", + "BriefDescription": "Load operations conflicting with software prefetches" + }, + { + "EventCode": "0xA8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LSD.ACTIVE", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles when uops were delivered by the LSD", + "CounterMask": "1" + }, + { + "EventCode": "0xA8", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LSD.INACTIVE", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles no uops were delivered by the LSD", + "CounterMask": "1" + }, + { + "EventCode": "0x20", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LSD_OVERFLOW", + "SampleAfterValue": "2000000", + "BriefDescription": "Loops that can't stream from the instruction queue" + }, + { + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MACHINE_CLEARS.CYCLES", + "SampleAfterValue": "20000", + "BriefDescription": "Cycles machine clear asserted" + }, + { + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MACHINE_CLEARS.MEM_ORDER", + "SampleAfterValue": "20000", + "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts" + }, + { + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "MACHINE_CLEARS.SMC", + "SampleAfterValue": "20000", + "BriefDescription": "Self-Modifying Code detected" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "RESOURCE_STALLS.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "Resource related stall cycles" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "RESOURCE_STALLS.FPCW", + "SampleAfterValue": "2000000", + "BriefDescription": "FPU control word write stall cycles" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "RESOURCE_STALLS.LOAD", + "SampleAfterValue": "2000000", + "BriefDescription": "Load buffer stall cycles" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "RESOURCE_STALLS.MXCSR", + "SampleAfterValue": "2000000", + "BriefDescription": "MXCSR rename stall cycles" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "RESOURCE_STALLS.OTHER", + "SampleAfterValue": "2000000", + "BriefDescription": "Other Resource related stall cycles" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "RESOURCE_STALLS.ROB_FULL", + "SampleAfterValue": "2000000", + "BriefDescription": "ROB full stall cycles" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "RESOURCE_STALLS.RS_FULL", + "SampleAfterValue": "2000000", + "BriefDescription": "Reservation Station full stall cycles" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "RESOURCE_STALLS.STORE", + "SampleAfterValue": "2000000", + "BriefDescription": "Store buffer stall cycles" + }, + { + "PEBS": "1", + "EventCode": "0xC7", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC7", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC7", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC7", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)" + }, + { + "EventCode": "0xDB", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOP_UNFUSION", + "SampleAfterValue": "2000000", + "BriefDescription": "Uop unfusions due to FP exceptions" + }, + { + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "UOPS_DECODED.ESP_FOLDING", + "SampleAfterValue": "2000000", + "BriefDescription": "Stack pointer instructions decoded" + }, + { + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "UOPS_DECODED.ESP_SYNC", + "SampleAfterValue": "2000000", + "BriefDescription": "Stack pointer sync operations" + }, + { + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops decoded by Microcode Sequencer", + "CounterMask": "1" + }, + { + "EventCode": "0xD1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_DECODED.STALL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles no Uops are decoded", + "CounterMask": "1" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x3f", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles Uops executed on any port (core count)", + "CounterMask": "1" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x1f", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)", + "CounterMask": "1" + }, + { + "EventCode": "0xB1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x3f", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops executed on any port (core count)", + "CounterMask": "1", + "EdgeDetect": "1" + }, + { + "EventCode": "0xB1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1f", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops executed on ports 0-4 (core count)", + "CounterMask": "1", + "EdgeDetect": "1" + }, + { + "EventCode": "0xB1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x3f", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles no Uops issued on any port (core count)", + "CounterMask": "1" + }, + { + "EventCode": "0xB1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1f", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)", + "CounterMask": "1" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_EXECUTED.PORT0", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops executed on port 0" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "UOPS_EXECUTED.PORT015", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops issued on ports 0, 1 or 5" + }, + { + "EventCode": "0xB1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5", + "CounterMask": "1" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.PORT1", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops executed on port 1" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x4", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.PORT2_CORE", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops executed on port 2 (core count)" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x80", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.PORT234_CORE", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops issued on ports 2, 3 or 4" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x8", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.PORT3_CORE", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops executed on port 3 (core count)" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x10", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.PORT4_CORE", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops executed on port 4 (core count)" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "UOPS_EXECUTED.PORT5", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops executed on port 5" + }, + { + "EventCode": "0xE", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_ISSUED.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops issued" + }, + { + "EventCode": "0xE", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles no Uops were issued on any thread", + "CounterMask": "1" + }, + { + "EventCode": "0xE", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles Uops were issued on either thread", + "CounterMask": "1" + }, + { + "EventCode": "0xE", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_ISSUED.FUSED", + "SampleAfterValue": "2000000", + "BriefDescription": "Fused Uops issued" + }, + { + "EventCode": "0xE", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles no Uops were issued", + "CounterMask": "1" + }, + { + "PEBS": "1", + "EventCode": "0xC2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.ACTIVE_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles Uops are being retired", + "CounterMask": "1" + }, + { + "PEBS": "1", + "EventCode": "0xC2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops retired (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "UOPS_RETIRED.MACRO_FUSED", + "SampleAfterValue": "2000000", + "BriefDescription": "Macro-fused Uops retired (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "SampleAfterValue": "2000000", + "BriefDescription": "Retirement slots used (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC2", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles Uops are not retiring (Precise Event)", + "CounterMask": "1" + }, + { + "PEBS": "1", + "EventCode": "0xC2", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Total cycles using precise uop retired event (Precise Event)", + "CounterMask": "16" + }, + { + "PEBS": "2", + "EventCode": "0xC0", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "INST_RETIRED.TOTAL_CYCLES_PS", + "SampleAfterValue": "2000000", + "BriefDescription": "Total cycles (Precise Event)", + "CounterMask": "16" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/virtual-memory.json b/tools/perf/pmu-events/arch/x86/nehalemex/virtual-memory.json new file mode 100644 index 000000000000..0596094e0ee9 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/nehalemex/virtual-memory.json @@ -0,0 +1,109 @@ +[ + { + "EventCode": "0x8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "DTLB_LOAD_MISSES.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB load misses" + }, + { + "EventCode": "0x8", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "DTLB_LOAD_MISSES.PDE_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB load miss caused by low part of address" + }, + { + "EventCode": "0x8", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "SampleAfterValue": "2000000", + "BriefDescription": "DTLB second level hit" + }, + { + "EventCode": "0x8", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB load miss page walks complete" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "DTLB_MISSES.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB misses" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "DTLB_MISSES.STLB_HIT", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB first level misses but second level hit" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "DTLB_MISSES.WALK_COMPLETED", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB miss page walks" + }, + { + "EventCode": "0xAE", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ITLB_FLUSH", + "SampleAfterValue": "2000000", + "BriefDescription": "ITLB flushes" + }, + { + "PEBS": "1", + "EventCode": "0xC8", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "ITLB_MISS_RETIRED", + "SampleAfterValue": "200000", + "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)" + }, + { + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ITLB_MISSES.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "ITLB miss" + }, + { + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "SampleAfterValue": "200000", + "BriefDescription": "ITLB miss page walks" + }, + { + "PEBS": "1", + "EventCode": "0xCB", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "MEM_LOAD_RETIRED.DTLB_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "Retired loads that miss the DTLB (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_STORE_RETIRED.DTLB_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "Retired stores that miss the DTLB (Precise Event)" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/cache.json b/tools/perf/pmu-events/arch/x86/sandybridge/cache.json new file mode 100644 index 000000000000..bef73c499f83 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/sandybridge/cache.json @@ -0,0 +1,1879 @@ +[ + { + "PEBS": "1", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x11", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load uops that miss the STLB.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x12", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", + "SampleAfterValue": "100003", + "BriefDescription": "Retired store uops that miss the STLB.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x21", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "SampleAfterValue": "100007", + "BriefDescription": "Retired load uops with locked access.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "PublicDescription": "This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x41", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load uops that split across a cacheline boundary.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "PublicDescription": "This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x42", + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "SampleAfterValue": "100003", + "BriefDescription": "Retired store uops that split across a cacheline boundary.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "PublicDescription": "This event counts the number of load uops retired", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x81", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "SampleAfterValue": "2000003", + "BriefDescription": "All retired load uops.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "PublicDescription": "This event counts the number of store uops retired.", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x82", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "SampleAfterValue": "2000003", + "BriefDescription": "All retired store uops.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "SampleAfterValue": "2000003", + "BriefDescription": "Retired load uops with L1 cache hits as data sources.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load uops with L2 cache hits as data sources.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "PublicDescription": "This event counts retired load uops that hit in the last-level (L3) cache without snoops required.", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT", + "SampleAfterValue": "50021", + "BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", + "SampleAfterValue": "20011", + "BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a non-modified state.", + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", + "SampleAfterValue": "20011", + "BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a modified state, so the line had to be invalidated in that L2 cache and transferred to the requesting L2.", + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", + "SampleAfterValue": "20011", + "BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "PublicDescription": "This event counts retired demand loads that missed the last-level (L3) cache. This means that the load is usually satisfied from memory in a client system or possibly from the remote socket in a server. Demand loads are non speculative load uops.", + "EventCode": "0xD4", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS", + "SampleAfterValue": "100007", + "BriefDescription": "Retired load uops with unknown information as data source in cache serviced the load.", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "This event counts L1D data line replacements. Replacements occur when a new line is brought into the cache, causing eviction of a line loaded earlier. ", + "EventCode": "0x51", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L1D.REPLACEMENT", + "SampleAfterValue": "2000003", + "BriefDescription": "L1D data line replacements.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x51", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L1D.ALLOCATED_IN_M", + "SampleAfterValue": "2000003", + "BriefDescription": "Allocated L1D data cache lines in M state.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x51", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L1D.EVICTION", + "SampleAfterValue": "2000003", + "BriefDescription": "L1D data cache lines in M state evicted due to replacement.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x51", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L1D.ALL_M_REPLACEMENT", + "SampleAfterValue": "2000003", + "BriefDescription": "Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x48", + "Counter": "2", + "UMask": "0x1", + "EventName": "L1D_PEND_MISS.PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "L1D miss oustandings duration in cycles.", + "CounterHTOff": "2" + }, + { + "EventCode": "0x48", + "Counter": "2", + "UMask": "0x1", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with L1D load Misses outstanding.", + "CounterMask": "1", + "CounterHTOff": "2" + }, + { + "EventCode": "0x63", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when L1D is locked.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "SampleAfterValue": "100003", + "BriefDescription": "Demand Data Read requests sent to uncore.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "SampleAfterValue": "100003", + "BriefDescription": "Cacheable and noncachaeble code read requests.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "SampleAfterValue": "100003", + "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", + "SampleAfterValue": "100003", + "BriefDescription": "Demand and prefetch data reads.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", + "SampleAfterValue": "2000003", + "BriefDescription": "Cases when offcore requests buffer cannot take more entries for core.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "SampleAfterValue": "200003", + "BriefDescription": "Demand Data Read requests that hit L2 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_RQSTS.RFO_HIT", + "SampleAfterValue": "200003", + "BriefDescription": "RFO requests that hit L2 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_RQSTS.RFO_MISS", + "SampleAfterValue": "200003", + "BriefDescription": "RFO requests that miss L2 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "L2_RQSTS.CODE_RD_HIT", + "SampleAfterValue": "200003", + "BriefDescription": "L2 cache hits when fetching instructions, code reads.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "L2_RQSTS.CODE_RD_MISS", + "SampleAfterValue": "200003", + "BriefDescription": "L2 cache misses when fetching instructions.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "L2_RQSTS.PF_HIT", + "SampleAfterValue": "200003", + "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "L2_RQSTS.PF_MISS", + "SampleAfterValue": "200003", + "BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_STORE_LOCK_RQSTS.MISS", + "SampleAfterValue": "200003", + "BriefDescription": "RFOs that miss cache lines.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_STORE_LOCK_RQSTS.HIT_E", + "SampleAfterValue": "200003", + "BriefDescription": "RFOs that hit cache lines in E state.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_STORE_LOCK_RQSTS.HIT_M", + "SampleAfterValue": "200003", + "BriefDescription": "RFOs that hit cache lines in M state.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "L2_STORE_LOCK_RQSTS.ALL", + "SampleAfterValue": "200003", + "BriefDescription": "RFOs that access cache lines in any state.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_L1D_WB_RQSTS.MISS", + "SampleAfterValue": "200003", + "BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_L1D_WB_RQSTS.HIT_S", + "SampleAfterValue": "200003", + "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in S state.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_L1D_WB_RQSTS.HIT_E", + "SampleAfterValue": "200003", + "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_L1D_WB_RQSTS.HIT_M", + "SampleAfterValue": "200003", + "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "L2_L1D_WB_RQSTS.ALL", + "SampleAfterValue": "200003", + "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_TRANS.DEMAND_DATA_RD", + "SampleAfterValue": "200003", + "BriefDescription": "Demand Data Read requests that access L2 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_TRANS.RFO", + "SampleAfterValue": "200003", + "BriefDescription": "RFO requests that access L2 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_TRANS.CODE_RD", + "SampleAfterValue": "200003", + "BriefDescription": "L2 cache accesses when fetching instructions.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_TRANS.ALL_PF", + "SampleAfterValue": "200003", + "BriefDescription": "L2 or LLC HW prefetches that access L2 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "L2_TRANS.L1D_WB", + "SampleAfterValue": "200003", + "BriefDescription": "L1D writebacks that access L2 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "L2_TRANS.L2_FILL", + "SampleAfterValue": "200003", + "BriefDescription": "L2 fill requests that access L2 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "L2_TRANS.L2_WB", + "SampleAfterValue": "200003", + "BriefDescription": "L2 writebacks that access L2 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "L2_TRANS.ALL_REQUESTS", + "SampleAfterValue": "200003", + "BriefDescription": "Transactions accessing L2 pipe.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_LINES_IN.I", + "SampleAfterValue": "100003", + "BriefDescription": "L2 cache lines in I state filling L2.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_LINES_IN.S", + "SampleAfterValue": "100003", + "BriefDescription": "L2 cache lines in S state filling L2.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_LINES_IN.E", + "SampleAfterValue": "100003", + "BriefDescription": "L2 cache lines in E state filling L2.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss.", + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x7", + "EventName": "L2_LINES_IN.ALL", + "SampleAfterValue": "100003", + "BriefDescription": "L2 cache lines filling L2.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_LINES_OUT.DEMAND_CLEAN", + "SampleAfterValue": "100003", + "BriefDescription": "Clean L2 cache lines evicted by demand.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_LINES_OUT.DEMAND_DIRTY", + "SampleAfterValue": "100003", + "BriefDescription": "Dirty L2 cache lines evicted by demand.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_LINES_OUT.PF_CLEAN", + "SampleAfterValue": "100003", + "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_LINES_OUT.PF_DIRTY", + "SampleAfterValue": "100003", + "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0xa", + "EventName": "L2_LINES_OUT.DIRTY_ALL", + "SampleAfterValue": "100003", + "BriefDescription": "Dirty L2 cache lines filling the L2.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x2E", + "Counter": "0,1,2,3", + "UMask": "0x41", + "EventName": "LONGEST_LAT_CACHE.MISS", + "SampleAfterValue": "100003", + "BriefDescription": "Core-originated cacheable demand requests missed LLC.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x2E", + "Counter": "0,1,2,3", + "UMask": "0x4f", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "SampleAfterValue": "100003", + "BriefDescription": "Core-originated cacheable demand requests that refer to LLC.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF4", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "SQ_MISC.SPLIT_LOCK", + "SampleAfterValue": "100003", + "BriefDescription": "Split locks in SQ.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x3", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "SampleAfterValue": "200003", + "BriefDescription": "Demand Data Read requests.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xc", + "EventName": "L2_RQSTS.ALL_RFO", + "SampleAfterValue": "200003", + "BriefDescription": "RFO requests to L2 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "SampleAfterValue": "200003", + "BriefDescription": "L2 code requests.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xc0", + "EventName": "L2_RQSTS.ALL_PF", + "SampleAfterValue": "200003", + "BriefDescription": "Requests from L2 hardware prefetchers.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xBF", + "Counter": "0,1,2,3", + "UMask": "0x5", + "EventName": "L1D_BLOCKS.BANK_CONFLICT_CYCLES", + "SampleAfterValue": "100003", + "BriefDescription": "Cycles when dispatched loads are cancelled due to L1D bank conflicts with other load ports.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_C6", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", + "CounterMask": "6", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x48", + "Counter": "2", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", + "CounterMask": "1", + "CounterHTOff": "2" + }, + { + "EventCode": "0x48", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L1D_PEND_MISS.FB_FULL", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0244", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand & prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003c0244", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2003c0244", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand & prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean response.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0091", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch data reads that hit in the LLC.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4003c0091", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0091", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003c0091", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2003c0091", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0240", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch code reads that hit in the LLC.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4003c0240", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0240", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003c0240", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2003c0240", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean response.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0090", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch data reads that hit in the LLC.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4003c0090", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0090", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003c0090", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2003c0090", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0120", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch RFOs that hit in the LLC.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4003c0120", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0120", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003c0120", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2003c0120", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean response.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c03f7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4003c03f7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c03f7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003c03f7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2003c03f7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops sent to sibling cores return clean response.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0122", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch RFOs that hit in the LLC.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4003c0122", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0122", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003c0122", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2003c0122", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean response.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10008", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "COREWB & ANY_RESPONSE", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand code reads that hit in the LLC.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4003c0004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003c0004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2003c0004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand code reads that hit in the LLC and the snoops sent to sibling cores return clean response.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand data reads that hit in the LLC.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4003c0001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003c0001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2003c0001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops sent to sibling cores return clean response.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0002", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand data writes (RFOs) that hit in the LLC.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4003c0002", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0002", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003c0002", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2003c0002", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoops sent to sibling cores return clean response.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x18000", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x803c8000", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.OTHER.LRU_HINTS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2380408000", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0040", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that hit in the LLC.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4003c0040", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0040", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003c0040", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2003c0040", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops sent to sibling cores return clean response.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to L2) data reads that hit in the LLC.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4003c0010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003c0010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2003c0010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0020", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the LLC.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4003c0020", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0020", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003c0020", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2003c0020", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops sent to sibling cores return clean response.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0200", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4003c0200", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0200", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003c0200", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2003c0200", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops sent to sibling cores return clean response.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0080", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the LLC.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4003c0080", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0080", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003c0080", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2003c0080", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0100", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the LLC.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4003c0100", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0100", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003c0100", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2003c0100", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops sent to sibling cores return clean response.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10400", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10800", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts non-temporal stores.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00010001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand data reads .", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00010002", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand rfo's .", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00010004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand code reads.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x000105B3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch data reads.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00010122", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch prefetch RFOs .", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x000107F7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all data/code/rfo references (demand & prefetch) .", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10433", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": " REQUEST = DATA_INTO_CORE and RESPONSE = ANY_RESPONSE", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000040002", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_M.HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": " REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_M and SNOOP = HITM", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10040", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": " REQUEST = PF_RFO and RESPONSE = ANY_RESPONSE", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10080", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": " REQUEST = PF_LLC_DATA_RD and RESPONSE = ANY_RESPONSE", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10200", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L_IFETCH.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": " REQUEST = PF_LLC_IFETCH and RESPONSE = ANY_RESPONSE", + "CounterHTOff": "0,1,2,3" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/floating-point.json b/tools/perf/pmu-events/arch/x86/sandybridge/floating-point.json new file mode 100644 index 000000000000..982eda48785e --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/sandybridge/floating-point.json @@ -0,0 +1,138 @@ +[ + { + "EventCode": "0xC1", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "OTHER_ASSISTS.AVX_STORE", + "SampleAfterValue": "100003", + "BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC1", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "OTHER_ASSISTS.AVX_TO_SSE", + "SampleAfterValue": "100003", + "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC1", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "OTHER_ASSISTS.SSE_TO_AVX", + "SampleAfterValue": "100003", + "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xCA", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "FP_ASSIST.X87_OUTPUT", + "SampleAfterValue": "100003", + "BriefDescription": "Number of X87 assists due to output value.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xCA", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "FP_ASSIST.X87_INPUT", + "SampleAfterValue": "100003", + "BriefDescription": "Number of X87 assists due to input value.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xCA", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "FP_ASSIST.SIMD_OUTPUT", + "SampleAfterValue": "100003", + "BriefDescription": "Number of SIMD FP assists due to Output values.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xCA", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "FP_ASSIST.SIMD_INPUT", + "SampleAfterValue": "100003", + "BriefDescription": "Number of SIMD FP assists due to input values.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "FP_COMP_OPS_EXE.X87", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x11", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "SIMD_FP_256.PACKED_SINGLE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of GSSE-256 Computational FP single precision uops issued this cycle.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x11", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "SIMD_FP_256.PACKED_DOUBLE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of AVX-256 Computational FP double precision uops issued this cycle.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xCA", + "Counter": "0,1,2,3", + "UMask": "0x1e", + "EventName": "FP_ASSIST.ANY", + "SampleAfterValue": "100003", + "BriefDescription": "Cycles with any input/output SSE or FP assist.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/frontend.json b/tools/perf/pmu-events/arch/x86/sandybridge/frontend.json new file mode 100644 index 000000000000..1b7b1dd36c68 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/sandybridge/frontend.json @@ -0,0 +1,305 @@ +[ + { + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ICACHE.HIT", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes unchacheable accesses.", + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "ICACHE.MISSES", + "SampleAfterValue": "200003", + "BriefDescription": "Instruction cache, streaming buffer and victim cache misses.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "IDQ.EMPTY", + "SampleAfterValue": "2000003", + "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "IDQ.MITE_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "IDQ.DSB_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "IDQ.MS_DSB_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "IDQ.MS_MITE_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "IDQ.MS_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts cycles during which the microcode sequencer assisted the front-end in delivering uops. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance. See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more information.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "IDQ.MS_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of uops not delivered to the back-end per cycle, per thread, when the back-end was not stalled. In the ideal case 4 uops can be delivered each cycle. The event counts the undelivered uops - so if 3 were delivered in one cycle, the counter would be incremented by 1 for that cycle (4 - 3). If the back-end is stalled, the count for this event is not incremented even when uops were not delivered, because the back-end would not have been able to accept them. This event is used in determining the front-end bound category of the top-down pipeline slots characterization.", + "EventCode": "0x9C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled .", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", + "CounterMask": "3", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xAB", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "DSB2MITE_SWITCHES.COUNT", + "SampleAfterValue": "2000003", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline. It excludes cycles when the back-end cannot accept new micro-ops. The penalty for these switches is potentially several cycles of instruction starvation, where no micro-ops are delivered to the back-end.", + "EventCode": "0xAB", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xAC", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "DSB_FILL.OTHER_CANCEL", + "SampleAfterValue": "2000003", + "BriefDescription": "Cases of cancelling valid DSB fill not because of exceeding way limit.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xAC", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "DSB_FILL.EXCEED_DSB_LINES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "IDQ.MITE_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "IDQ.DSB_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "IDQ.MS_DSB_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EdgeDetect": "1", + "EventName": "IDQ.MS_DSB_OCCUR", + "SampleAfterValue": "2000003", + "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x9C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", + "CounterMask": "2", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with less than 3 uops delivered by the front end.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_GE_1_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when 1 or more uops were delivered to the by the front end.", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x18", + "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x18", + "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x24", + "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles MITE is delivering 4 Uops.", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x24", + "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles MITE is delivering any Uop.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xAC", + "Counter": "0,1,2,3", + "UMask": "0xa", + "EventName": "DSB_FILL.ALL_CANCEL", + "SampleAfterValue": "2000003", + "BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x9C", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x3c", + "EventName": "IDQ.MITE_ALL_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EdgeDetect": "1", + "EventName": "IDQ.MS_SWITCHES", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/memory.json b/tools/perf/pmu-events/arch/x86/sandybridge/memory.json new file mode 100644 index 000000000000..e6dfa89d00f3 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/sandybridge/memory.json @@ -0,0 +1,445 @@ +[ + { + "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers. Machine clears can have a significant performance impact if they are happening frequently.", + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "SampleAfterValue": "100003", + "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "2", + "EventCode": "0xCD", + "MSRValue": "0x4", + "Counter": "3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "SampleAfterValue": "100003", + "BriefDescription": "Loads with latency value being above 4 .", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "EventCode": "0xCD", + "MSRValue": "0x8", + "Counter": "3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "MSRIndex": "0x3F6", + "SampleAfterValue": "50021", + "BriefDescription": "Loads with latency value being above 8.", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "EventCode": "0xCD", + "MSRValue": "0x10", + "Counter": "3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "MSRIndex": "0x3F6", + "SampleAfterValue": "20011", + "BriefDescription": "Loads with latency value being above 16.", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "EventCode": "0xCD", + "MSRValue": "0x20", + "Counter": "3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "MSRIndex": "0x3F6", + "SampleAfterValue": "100007", + "BriefDescription": "Loads with latency value being above 32.", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "EventCode": "0xCD", + "MSRValue": "0x40", + "Counter": "3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "MSRIndex": "0x3F6", + "SampleAfterValue": "2003", + "BriefDescription": "Loads with latency value being above 64.", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "EventCode": "0xCD", + "MSRValue": "0x80", + "Counter": "3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "MSRIndex": "0x3F6", + "SampleAfterValue": "1009", + "BriefDescription": "Loads with latency value being above 128.", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "EventCode": "0xCD", + "MSRValue": "0x100", + "Counter": "3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "MSRIndex": "0x3F6", + "SampleAfterValue": "503", + "BriefDescription": "Loads with latency value being above 256.", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "EventCode": "0xCD", + "MSRValue": "0x200", + "Counter": "3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "MSRIndex": "0x3F6", + "SampleAfterValue": "101", + "BriefDescription": "Loads with latency value being above 512.", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "EventCode": "0xCD", + "Counter": "3", + "UMask": "0x2", + "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).", + "PRECISE_STORE": "1", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "EventCode": "0xBE", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "PAGE_WALKS.LLC_MISS", + "SampleAfterValue": "100003", + "BriefDescription": "Number of any page walk that had a miss in LLC. Does not necessary cause a SUSPEND.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x05", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MISALIGN_MEM_REF.LOADS", + "SampleAfterValue": "2000003", + "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x05", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MISALIGN_MEM_REF.STORES", + "SampleAfterValue": "2000003", + "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x300400244", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC and the data returned from dram.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x300400091", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch data reads that miss the LLC and the data returned from dram.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x300400240", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_MISS.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch code reads that miss the LLC and the data returned from dram.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x300400090", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_MISS.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch data reads that miss the LLC and the data returned from dram.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x300400120", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_MISS.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch RFOs that miss the LLC and the data returned from dram.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3004003f7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from dram.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x300400122", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch RFOs that miss the LLC and the data returned from dram.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x300400004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand code reads that miss the LLC and the data returned from dram.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x300400001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from dram.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x300400002", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data writes (RFOs) that miss the LLC and the data returned from dram.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x300400040", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from dram.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x300400010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from dram.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x300400020", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_MISS.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the LLC and the data returned from dram.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x300400200", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss the LLC and the data returned from dram.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x300400080", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the LLC and the data returned from dram.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x300400100", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the LLC and the data returned from dram.", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "This event counts all data requests (demand/prefetch data reads and demand data writes (RFOs) that miss the LLC where the data is returned from local DRAM", + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x6004001b3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts LLC replacements.", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "This event counts any requests that miss the LLC where the data was returned from local DRAM", + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1f80408fff", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_MISS_LOCAL.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": " REQUEST = ANY_REQUEST and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x17004001b3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS_LOCAL.ANY_LLC_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": " REQUEST = DATA_IN_SOCKET and RESPONSE = LLC_MISS_LOCAL and SNOOP = ANY_LLC_HIT", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1f80400004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_MISS_LOCAL.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": " REQUEST = DEMAND_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1f80400010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_MISS_LOCAL.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": " REQUEST = PF_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1f80400040", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_MISS_LOCAL.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": " REQUEST = PF_RFO and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1f80400080", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L_DATA_RD.LLC_MISS_LOCAL.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": " REQUEST = PF_LLC_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1f80400200", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.PF_L_IFETCH.LLC_MISS_LOCAL.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": " REQUEST = PF_LLC_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", + "CounterHTOff": "0,1,2,3" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/other.json b/tools/perf/pmu-events/arch/x86/sandybridge/other.json new file mode 100644 index 000000000000..64b195b82c50 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/sandybridge/other.json @@ -0,0 +1,58 @@ +[ + { + "EventCode": "0x17", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "INSTS_WRITTEN_TO_IQ.INSTS", + "SampleAfterValue": "2000003", + "BriefDescription": "Valid instructions written to IQ per cycle.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CPL_CYCLES.RING0", + "SampleAfterValue": "2000003", + "BriefDescription": "Unhalted core cycles when the thread is in ring 0.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EdgeDetect": "1", + "EventName": "CPL_CYCLES.RING0_TRANS", + "SampleAfterValue": "100007", + "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5C", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "CPL_CYCLES.RING123", + "SampleAfterValue": "2000003", + "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x4E", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "HW_PRE_REQ.DL1_MISS", + "SampleAfterValue": "2000003", + "BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x63", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json b/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json new file mode 100644 index 000000000000..8a597e45ed84 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json @@ -0,0 +1,1220 @@ +[ + { + "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. ", + "EventCode": "0x00", + "Counter": "Fixed counter 1", + "UMask": "0x1", + "EventName": "INST_RETIRED.ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Instructions retired from execution.", + "CounterHTOff": "Fixed counter 1" + }, + { + "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. ", + "EventCode": "0x00", + "Counter": "Fixed counter 2", + "UMask": "0x2", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "SampleAfterValue": "2000003", + "BriefDescription": "Core cycles when the thread is not in halt state.", + "CounterHTOff": "Fixed counter 2" + }, + { + "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. ", + "EventCode": "0x00", + "Counter": "Fixed counter 3", + "UMask": "0x3", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "SampleAfterValue": "2000003", + "BriefDescription": "Reference cycles when the core is not in halt state.", + "CounterHTOff": "Fixed counter 3" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x41", + "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Not taken macro-conditional branches.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x81", + "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired macro-conditional branches.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x82", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x84", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x90", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired direct near calls.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xa0", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired indirect calls.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xc1", + "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired macro-conditional branches.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xc2", + "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xc4", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired indirect branches excluding calls and returns.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xc8", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired indirect return branches.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xd0", + "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired direct near calls.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x41", + "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x81", + "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x84", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x88", + "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x90", + "EventName": "BR_MISP_EXEC.TAKEN_DIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired mispredicted direct near calls.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0xa0", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired mispredicted indirect calls.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0xc1", + "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired mispredicted macro conditional branches.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0xc4", + "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "BriefDescription": "Mispredicted indirect branches excluding calls and returns.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0xd0", + "EventName": "BR_MISP_EXEC.ALL_DIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired mispredicted direct near calls.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "SampleAfterValue": "2000003", + "BriefDescription": "Thread cycles when thread is not in halt state.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LSD.UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of Uops delivered by the LSD.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LSD.CYCLES_ACTIVE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x87", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ILD_STALL.LCP", + "SampleAfterValue": "2000003", + "BriefDescription": "Stalls caused by changing prefix length of the instruction.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x87", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "ILD_STALL.IQ_FULL", + "SampleAfterValue": "2000003", + "BriefDescription": "Stall cycles because IQ is full.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0D", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "INT_MISC.RAT_STALL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x59", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP", + "SampleAfterValue": "2000003", + "BriefDescription": "Increments the number of flags-merge uops in flight each cycle.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index reqisters, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructions.", + "EventCode": "0x59", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with at least one slow LEA uop being allocated.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x59", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "PARTIAL_RAT_STALLS.MUL_SINGLE_UOP", + "SampleAfterValue": "2000003", + "BriefDescription": "Multiply packed/scalar single precision uops allocated.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "RESOURCE_STALLS.ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Resource-related stall cycles.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "RESOURCE_STALLS.LB", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts the cycles of stall due to lack of load buffers.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "RESOURCE_STALLS.RS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles stalled due to no eligible RS entry available.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "RESOURCE_STALLS.SB", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "RESOURCE_STALLS.ROB", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles stalled due to re-order buffer full.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5B", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "RESOURCE_STALLS2.BOB_FULL", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when Allocator is stalled if BOB is full and new branch needs it.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of Uops issued by the front-end of the pipeilne to the back-end.", + "EventCode": "0x0E", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_ISSUED.ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0E", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x0E", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x5E", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "RS_EVENTS.EMPTY_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xCC", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", + "SampleAfterValue": "2000003", + "BriefDescription": "Count cases of saving new LBR.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear. Machine clears can have a significant performance impact if they are happening frequently.", + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "MACHINE_CLEARS.SMC", + "SampleAfterValue": "100003", + "BriefDescription": "Self-modifying code (SMC) detected.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.", + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "MACHINE_CLEARS.MASKMOV", + "SampleAfterValue": "100003", + "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC0", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "INST_RETIRED.ANY_P", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of instructions retired. General Counter - architectural event.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "PublicDescription": "This event counts the number of micro-ops retired.", + "EventCode": "0xC2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.ALL", + "SampleAfterValue": "2000003", + "BriefDescription": "Actually retired uops.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "PublicDescription": "This event counts the number of retirement slots used each cycle. There are potentially 4 slots that can be used each cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle. This event is used in determining the 'Retiring' category of the Top-Down pipeline slots characterization.", + "EventCode": "0xC2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "SampleAfterValue": "2000003", + "BriefDescription": "Retirement slots used.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC2", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles without actually retired uops.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC2", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with less than 10 actually retired uops.", + "CounterMask": "10", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BR_INST_RETIRED.CONDITIONAL", + "SampleAfterValue": "400009", + "BriefDescription": "Conditional branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "SampleAfterValue": "100007", + "BriefDescription": "Direct and indirect near call instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "SampleAfterValue": "400009", + "BriefDescription": "All (macro) branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "SampleAfterValue": "100007", + "BriefDescription": "Return instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "BR_INST_RETIRED.NOT_TAKEN", + "SampleAfterValue": "400009", + "BriefDescription": "Not taken branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "SampleAfterValue": "400009", + "BriefDescription": "Taken branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "SampleAfterValue": "100007", + "BriefDescription": "Far branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "2", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", + "SampleAfterValue": "400009", + "BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS).", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BR_MISP_RETIRED.CONDITIONAL", + "SampleAfterValue": "400009", + "BriefDescription": "Mispredicted conditional branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "BR_MISP_RETIRED.NEAR_CALL", + "SampleAfterValue": "100007", + "BriefDescription": "Direct and indirect mispredicted near call instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "SampleAfterValue": "400009", + "BriefDescription": "All mispredicted macro branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "BR_MISP_RETIRED.NOT_TAKEN", + "SampleAfterValue": "400009", + "BriefDescription": "Mispredicted not taken branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "BR_MISP_RETIRED.TAKEN", + "SampleAfterValue": "400009", + "BriefDescription": "Mispredicted taken branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "2", + "PublicDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", + "SampleAfterValue": "400009", + "BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS).", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "OTHER_ASSISTS.ITLB_MISS_RETIRED", + "SampleAfterValue": "100003", + "BriefDescription": "Retired instructions experiencing ITLB misses.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x14", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ARITH.FPU_DIV_ACTIVE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when divider is busy executing divide operations.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of the divide operations executed.", + "EventCode": "0x14", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EdgeDetect": "1", + "EventName": "ARITH.FPU_DIV", + "SampleAfterValue": "100003", + "BriefDescription": "Divide operations executed.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_DISPATCHED.THREAD", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops dispatched per thread.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_DISPATCHED.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops dispatched from any thread.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are dispatched to port 0.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are dispatched to port 1.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are dispatched to port 4.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are dispatched to port 5.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "CYCLE_ACTIVITY.CYCLES_NO_DISPATCH", + "SampleAfterValue": "2000003", + "BriefDescription": "Each cycle there was no dispatch for this thread, increment by 1. Note this is connect to Umask 2. No dispatch can be deduced from the UOPS_EXECUTED event.", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xA3", + "Counter": "2", + "UMask": "0x2", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "Each cycle there was a miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.", + "CounterMask": "2", + "CounterHTOff": "2" + }, + { + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "Each cycle there was a MLC-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA3", + "Counter": "2", + "UMask": "0x6", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "Each cycle there was a miss-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and connected to Umask 1 and 2. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.", + "CounterMask": "6", + "CounterHTOff": "2" + }, + { + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x5", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "Each cycle there was a MLC-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 and 2.", + "CounterMask": "5", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x4C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LOAD_HIT_PRE.SW_PF", + "SampleAfterValue": "100003", + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x4C", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "LOAD_HIT_PRE.HW_PF", + "SampleAfterValue": "100003", + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x03", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LD_BLOCKS.DATA_UNKNOWN", + "SampleAfterValue": "100003", + "BriefDescription": "Loads delayed due to SB blocks, preceding store operations with known addresses but unknown data.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceeding smaller uncompleted store. See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.", + "EventCode": "0x03", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "SampleAfterValue": "100003", + "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x03", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "LD_BLOCKS.NO_SR", + "SampleAfterValue": "100003", + "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x03", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "LD_BLOCKS.ALL_BLOCK", + "SampleAfterValue": "100003", + "BriefDescription": "Number of cases where any load ends up with a valid block-code written to the load buffer (including blocks due to Memory Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K. This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline. The enhanced address check typically has a performance penalty of 5 cycles.", + "EventCode": "0x07", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "SampleAfterValue": "100003", + "BriefDescription": "False dependencies in MOB due to partial compare.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x07", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "LD_BLOCKS_PARTIAL.ALL_STA_BLOCK", + "SampleAfterValue": "100003", + "BriefDescription": "This event counts the number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB6", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "AGU_BYPASS_CANCEL.COUNT", + "SampleAfterValue": "100003", + "BriefDescription": "This event counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in an.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", + "SampleAfterValue": "2000003", + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "2000003", + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other is halted.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when uops are dispatched to port 0.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "AnyThread": "1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when uops are dispatched to port 1.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x40", + "AnyThread": "1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when uops are dispatched to port 4.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x80", + "AnyThread": "1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when uops are dispatched to port 5.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0xc", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 2.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0xc", + "AnyThread": "1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 2.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x30", + "AnyThread": "1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "2", + "EventCode": "0xC0", + "Counter": "1", + "UMask": "0x1", + "EventName": "INST_RETIRED.PREC_DIST", + "SampleAfterValue": "2000003", + "BriefDescription": "Instructions retired. (Precise Event - PEBS).", + "TakenAlone": "1", + "CounterHTOff": "1" + }, + { + "EventCode": "0x5B", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "RESOURCE_STALLS2.ALL_PRF_CONTROL", + "SampleAfterValue": "2000003", + "BriefDescription": "Resource stalls2 control structures full for physical registers.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5B", + "Counter": "0,1,2,3", + "UMask": "0xc", + "EventName": "RESOURCE_STALLS2.ALL_FL_EMPTY", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with either free list is empty.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0xe", + "EventName": "RESOURCE_STALLS.MEM_RS", + "SampleAfterValue": "2000003", + "BriefDescription": "Resource stalls due to memory buffers or Reservation Station (RS) being fully utilized.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0xf0", + "EventName": "RESOURCE_STALLS.OOO_RSRC", + "SampleAfterValue": "2000003", + "BriefDescription": "Resource stalls due to Rob being full, FCSW, MXCSR and OTHER.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5B", + "Counter": "0,1,2,3", + "UMask": "0x4f", + "EventName": "RESOURCE_STALLS2.OOO_RSRC", + "SampleAfterValue": "2000003", + "BriefDescription": "Resource stalls out of order resources full.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0xa", + "EventName": "RESOURCE_STALLS.LB_SB", + "SampleAfterValue": "2000003", + "BriefDescription": "Resource stalls due to load or store buffers all being in use.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0D", + "Counter": "0,1,2,3", + "UMask": "0x3", + "EventName": "INT_MISC.RECOVERY_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...).", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of cycles spent executing performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For more details, See the Intel? 64 and IA-32 Architectures Optimization Reference Manual.", + "EventCode": "0x59", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Performance sensitive flags-merging uops added by Sandy Bridge u-arch.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0D", + "Counter": "0,1,2,3", + "UMask": "0x3", + "EdgeDetect": "1", + "EventName": "INT_MISC.RECOVERY_STALLS_COUNT", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...).", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xE6", + "Counter": "0,1,2,3", + "UMask": "0x1f", + "EventName": "BACLEARS.ANY", + "SampleAfterValue": "100003", + "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xff", + "EventName": "BR_INST_EXEC.ALL_BRANCHES", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired branches.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0xff", + "EventName": "BR_MISP_EXEC.ALL_BRANCHES", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired mispredicted macro conditional branches.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC2", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles without actually retired uops.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xA8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LSD.CYCLES_4_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xc3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EdgeDetect": "1", + "EventName": "MACHINE_CLEARS.COUNT", + "SampleAfterValue": "100003", + "BriefDescription": "Number of machine clears (nukes) of any type.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5E", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EdgeDetect": "1", + "EventName": "RS_EVENTS.EMPTY_END", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x00", + "Counter": "Fixed counter 2", + "UMask": "0x2", + "AnyThread": "1", + "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "CounterHTOff": "Fixed counter 2" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x0", + "AnyThread": "1", + "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0D", + "Counter": "0,1,2,3", + "UMask": "0x3", + "AnyThread": "1", + "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", + "CounterMask": "2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", + "CounterMask": "3", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "SampleAfterValue": "2000003", + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "2000003", + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/virtual-memory.json b/tools/perf/pmu-events/arch/x86/sandybridge/virtual-memory.json new file mode 100644 index 000000000000..a654ab771fce --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/sandybridge/virtual-memory.json @@ -0,0 +1,149 @@ +[ + { + "EventCode": "0xAE", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ITLB.ITLB_FLUSH", + "SampleAfterValue": "100007", + "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x4F", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "EPT.WALK_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", + "SampleAfterValue": "100003", + "BriefDescription": "Misses at all ITLB levels that cause page walks.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "SampleAfterValue": "100003", + "BriefDescription": "Misses in all ITLB levels that cause completed page walks.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses.", + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "ITLB_MISSES.WALK_DURATION", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when PMH is busy with page walks.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "ITLB_MISSES.STLB_HIT", + "SampleAfterValue": "100003", + "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", + "SampleAfterValue": "100003", + "BriefDescription": "Load misses in all DTLB levels that cause page walks.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "SampleAfterValue": "100003", + "BriefDescription": "Load misses at all DTLB levels that cause completed page walks.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.", + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when PMH is busy with page walks.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts load operations that miss the first DTLB level but hit the second and do not cause any page walks. The penalty in this case is approximately 7 cycles.", + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "SampleAfterValue": "100003", + "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", + "SampleAfterValue": "100003", + "BriefDescription": "Store misses in all DTLB levels that cause page walks.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "SampleAfterValue": "100003", + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "DTLB_STORE_MISSES.WALK_DURATION", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when PMH is busy with page walks.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "SampleAfterValue": "100003", + "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xBD", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "TLB_FLUSH.DTLB_THREAD", + "SampleAfterValue": "100007", + "BriefDescription": "DTLB flush attempts of the thread-specific entries.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xBD", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "TLB_FLUSH.STLB_ANY", + "SampleAfterValue": "100007", + "BriefDescription": "STLB flush attempts.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/silvermont/cache.json b/tools/perf/pmu-events/arch/x86/silvermont/cache.json new file mode 100644 index 000000000000..0bd1bc5302de --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/silvermont/cache.json @@ -0,0 +1,811 @@ +[ + { + "PublicDescription": "This event counts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the IDI link. The XQ may reject transactions from the L2Q (non-cacheable requests), BBS (L2 misses) and WOB (L2 write-back victims).", + "EventCode": "0x30", + "Counter": "0,1", + "UMask": "0x0", + "EventName": "L2_REJECT_XQ.ALL", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of request from the L2 that were not accepted into the XQ" + }, + { + "PublicDescription": "Counts the number of (demand and L1 prefetchers) core requests rejected by the L2Q due to a full or nearly full w condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to insure fairness between cores, or to delay a core?s dirty eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests that are dropped are not counted by this event.)", + "EventCode": "0x31", + "Counter": "0,1", + "UMask": "0x0", + "EventName": "CORE_REJECT_L2Q.ALL", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of request that were not accepted into the L2Q because the L2Q is FULL." + }, + { + "PublicDescription": "This event counts requests originating from the core that references a cache line in the L2 cache.", + "EventCode": "0x2E", + "Counter": "0,1", + "UMask": "0x4f", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "SampleAfterValue": "200003", + "BriefDescription": "L2 cache requests from this core" + }, + { + "PublicDescription": "This event counts the total number of L2 cache references and the number of L2 cache misses respectively.", + "EventCode": "0x2E", + "Counter": "0,1", + "UMask": "0x41", + "EventName": "LONGEST_LAT_CACHE.MISS", + "SampleAfterValue": "200003", + "BriefDescription": "L2 cache request misses" + }, + { + "EventCode": "0x86", + "Counter": "0,1", + "UMask": "0x4", + "EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of cycles the NIP stalls because of an icache miss. This is a cumulative count of cycles the NIP stalled for all icache misses." + }, + { + "PEBS": "1", + "PublicDescription": "This event counts the number of retired loads that were prohibited from receiving forwarded data from the store because of address mismatch.", + "EventCode": "0x03", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "REHABQ.LD_BLOCK_ST_FORWARD", + "SampleAfterValue": "200003", + "BriefDescription": "Loads blocked due to store forward restriction" + }, + { + "PublicDescription": "This event counts the cases where a forward was technically possible, but did not occur because the store data was not available at the right time.", + "EventCode": "0x03", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "REHABQ.LD_BLOCK_STD_NOTREADY", + "SampleAfterValue": "200003", + "BriefDescription": "Loads blocked due to store data not ready" + }, + { + "PublicDescription": "This event counts the number of retire stores that experienced cache line boundary splits.", + "EventCode": "0x03", + "Counter": "0,1", + "UMask": "0x4", + "EventName": "REHABQ.ST_SPLITS", + "SampleAfterValue": "200003", + "BriefDescription": "Store uops that split cache line boundary" + }, + { + "PEBS": "1", + "PublicDescription": "This event counts the number of retire loads that experienced cache line boundary splits.", + "EventCode": "0x03", + "Counter": "0,1", + "UMask": "0x8", + "EventName": "REHABQ.LD_SPLITS", + "SampleAfterValue": "200003", + "BriefDescription": "Load uops that split cache line boundary" + }, + { + "PublicDescription": "This event counts the number of retired memory operations with lock semantics. These are either implicit locked instructions such as the XCHG instruction or instructions with an explicit LOCK prefix (0xF0).", + "EventCode": "0x03", + "Counter": "0,1", + "UMask": "0x10", + "EventName": "REHABQ.LOCK", + "SampleAfterValue": "200003", + "BriefDescription": "Uops with lock semantics" + }, + { + "PublicDescription": "This event counts the number of retired stores that are delayed because there is not a store address buffer available.", + "EventCode": "0x03", + "Counter": "0,1", + "UMask": "0x20", + "EventName": "REHABQ.STA_FULL", + "SampleAfterValue": "200003", + "BriefDescription": "Store address buffer full" + }, + { + "PublicDescription": "This event counts the number of load uops reissued from Rehabq.", + "EventCode": "0x03", + "Counter": "0,1", + "UMask": "0x40", + "EventName": "REHABQ.ANY_LD", + "SampleAfterValue": "200003", + "BriefDescription": "Any reissued load uops" + }, + { + "PublicDescription": "This event counts the number of store uops reissued from Rehabq.", + "EventCode": "0x03", + "Counter": "0,1", + "UMask": "0x80", + "EventName": "REHABQ.ANY_ST", + "SampleAfterValue": "200003", + "BriefDescription": "Any reissued store uops" + }, + { + "PublicDescription": "This event counts the number of load ops retired that miss in L1 Data cache. Note that prefetch misses will not be counted.", + "EventCode": "0x04", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "MEM_UOPS_RETIRED.L1_MISS_LOADS", + "SampleAfterValue": "200003", + "BriefDescription": "Loads missed L1" + }, + { + "PEBS": "1", + "PublicDescription": "This event counts the number of load ops retired that hit in the L2.", + "EventCode": "0x04", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "MEM_UOPS_RETIRED.L2_HIT_LOADS", + "SampleAfterValue": "200003", + "BriefDescription": "Loads hit L2" + }, + { + "PEBS": "1", + "PublicDescription": "This event counts the number of load ops retired that miss in the L2.", + "EventCode": "0x04", + "Counter": "0,1", + "UMask": "0x4", + "EventName": "MEM_UOPS_RETIRED.L2_MISS_LOADS", + "SampleAfterValue": "100007", + "BriefDescription": "Loads missed L2" + }, + { + "PublicDescription": "This event counts the number of load ops retired that had UTLB miss.", + "EventCode": "0x04", + "Counter": "0,1", + "UMask": "0x10", + "EventName": "MEM_UOPS_RETIRED.UTLB_MISS", + "SampleAfterValue": "200003", + "BriefDescription": "Loads missed UTLB" + }, + { + "PEBS": "1", + "PublicDescription": "This event counts the number of load ops retired that got data from the other core or from the other module.", + "EventCode": "0x04", + "Counter": "0,1", + "UMask": "0x20", + "EventName": "MEM_UOPS_RETIRED.HITM", + "SampleAfterValue": "200003", + "BriefDescription": "Cross core or cross module hitm" + }, + { + "PublicDescription": "This event counts the number of load ops retired.", + "EventCode": "0x04", + "Counter": "0,1", + "UMask": "0x40", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "SampleAfterValue": "200003", + "BriefDescription": "All Loads" + }, + { + "PublicDescription": "This event counts the number of store ops retired.", + "EventCode": "0x04", + "Counter": "0,1", + "UMask": "0x80", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "SampleAfterValue": "200003", + "BriefDescription": "All Stores" + }, + { + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "EventCode": "0xB7", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE", + "SampleAfterValue": "100007", + "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1680000044", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any code reads (demand & prefetch) that miss L2.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000000044", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any code reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0400000044", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any code reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0200000044", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any code reads (demand & prefetch) that miss L2 with a snoop miss response.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000010044", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any code reads (demand & prefetch) that have any response type.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1680000022", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any rfo reads (demand & prefetch) that miss L2.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000000022", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any rfo reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0400000022", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any rfo reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0200000022", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any rfo reads (demand & prefetch) that miss L2 with a snoop miss response.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000010022", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any rfo reads (demand & prefetch) that have any response type.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1680003091", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any data read (demand & prefetch) that miss L2.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000003091", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any data read (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0400003091", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any data read (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0200003091", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any data read (demand & prefetch) that miss L2 with a snoop miss response.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000013091", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any data read (demand & prefetch) that have any response type.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1680004800", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts streaming store that miss L2.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000008008", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any request that hit in the other module where modified copies were found in other core's L1 cache.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0400008008", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any request that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0200008008", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any request that miss L2 with a snoop miss response.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000018008", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts any request that have any response type.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1680002000", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts DCU hardware prefetcher data read that miss L2.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000002000", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts DCU hardware prefetcher data read that hit in the other module where modified copies were found in other core's L1 cache.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0400002000", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts DCU hardware prefetcher data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0200002000", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts DCU hardware prefetcher data read that miss L2 with a snoop miss response.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000012000", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts DCU hardware prefetcher data read that have any response type.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1680000100", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Countsof demand RFO requests to write to partial cache lines that miss L2.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1680000080", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand reads of partial cache lines (including UC and WC) that miss L2.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1680000040", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts code reads generated by L2 prefetchers that miss L2.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0400000040", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts code reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0200000040", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts code reads generated by L2 prefetchers that miss L2 with a snoop miss response.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1680000020", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts RFO requests generated by L2 prefetchers that miss L2.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000000020", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts RFO requests generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cache.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0400000020", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts RFO requests generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0200000020", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts RFO requests generated by L2 prefetchers that miss L2 with a snoop miss response.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1680000010", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts data cacheline reads generated by L2 prefetchers that miss L2.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000000010", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts data cacheline reads generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cache.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0400000010", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts data cacheline reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0200000010", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts data cacheline reads generated by L2 prefetchers that miss L2 with a snoop miss response.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1680000008", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts writeback (modified to exclusive) that miss L2.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0080000008", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts writeback (modified to exclusive) that miss L2 with no details on snoop-related information.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4000000004", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand and DCU prefetch instruction cacheline that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1680000004", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand and DCU prefetch instruction cacheline that miss L2.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0400000004", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand and DCU prefetch instruction cacheline that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0200000004", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand and DCU prefetch instruction cacheline that miss L2 with a snoop miss response.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000010004", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand and DCU prefetch instruction cacheline that have any response type.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4000000002", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING", + "MSRIndex": "0x1a6", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand and DCU prefetch RFOs that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1680000002", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand and DCU prefetch RFOs that miss L2.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000000002", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand and DCU prefetch RFOs that hit in the other module where modified copies were found in other core's L1 cache.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0400000002", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand and DCU prefetch RFOs that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0200000002", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand and DCU prefetch RFOs that miss L2 with a snoop miss response.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4000000001", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand and DCU prefetch data read that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1680000001", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand and DCU prefetch data read that miss L2.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1000000001", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand and DCU prefetch data read that hit in the other module where modified copies were found in other core's L1 cache.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0400000001", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand and DCU prefetch data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0200000001", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand and DCU prefetch data read that miss L2 with a snoop miss response.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x0000010001", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100007", + "BriefDescription": "Counts demand and DCU prefetch data read that have any response type.", + "Offcore": "1" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/silvermont/frontend.json b/tools/perf/pmu-events/arch/x86/silvermont/frontend.json new file mode 100644 index 000000000000..204473badf5a --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/silvermont/frontend.json @@ -0,0 +1,47 @@ +[ + { + "PublicDescription": "This event counts all instruction fetches, not including most uncacheable\r\nfetches.", + "EventCode": "0x80", + "Counter": "0,1", + "UMask": "0x3", + "EventName": "ICACHE.ACCESSES", + "SampleAfterValue": "200003", + "BriefDescription": "Instruction fetches" + }, + { + "PublicDescription": "This event counts all instruction fetches from the instruction cache.", + "EventCode": "0x80", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "ICACHE.HIT", + "SampleAfterValue": "200003", + "BriefDescription": "Instruction fetches from Icache" + }, + { + "PublicDescription": "This event counts all instruction fetches that miss the Instruction cache or produce memory requests. This includes uncacheable fetches. An instruction fetch miss is counted only once and not once for every cycle it is outstanding.", + "EventCode": "0x80", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "ICACHE.MISSES", + "SampleAfterValue": "200003", + "BriefDescription": "Icache miss" + }, + { + "PublicDescription": "Counts the number of times the MSROM starts a flow of UOPS. It does not count every time a UOP is read from the microcode ROM. The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine. Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort. The event will count MSROM startups for UOPS that are speculative, and subsequently cleared by branch mispredict or machine clear. Background: UOPS are produced by two mechanisms. Either they are generated by hardware that decodes instructions into UOPS, or they are delivered by a ROM (called the MSROM) that holds UOPS associated with a specific instruction. MSROM UOPS might also be delivered in response to some condition such as a fault or other exceptional condition. This event is an excellent mechanism for detecting instructions that require the use of MSROM instructions.", + "EventCode": "0xE7", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "MS_DECODED.MS_ENTRY", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of times entered into a ucode flow in the FEC. Includes inserted flows due to front-end detected faults or assists. Speculative count." + }, + { + "PublicDescription": "Counts the number of times a decode restriction reduced the decode throughput due to wrong instruction length prediction.", + "EventCode": "0xE9", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "DECODE_RESTRICTION.PREDECODE_WRONG", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of times a decode restriction reduced the decode throughput due to wrong instruction length prediction" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/silvermont/memory.json b/tools/perf/pmu-events/arch/x86/silvermont/memory.json new file mode 100644 index 000000000000..d72e09a5f929 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/silvermont/memory.json @@ -0,0 +1,11 @@ +[ + { + "PublicDescription": "This event counts the number of times that pipeline was cleared due to memory ordering issues.", + "EventCode": "0xC3", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "SampleAfterValue": "200003", + "BriefDescription": "Stalls due to Memory ordering" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/silvermont/pipeline.json b/tools/perf/pmu-events/arch/x86/silvermont/pipeline.json new file mode 100644 index 000000000000..7468af99190a --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/silvermont/pipeline.json @@ -0,0 +1,359 @@ +[ + { + "PEBS": "1", + "PublicDescription": "ALL_BRANCHES counts the number of any branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.", + "EventCode": "0xC4", + "Counter": "0,1", + "UMask": "0x0", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of branch instructions retired..." + }, + { + "PEBS": "1", + "PublicDescription": "JCC counts the number of conditional branch (JCC) instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.", + "EventCode": "0xC4", + "Counter": "0,1", + "UMask": "0x7e", + "EventName": "BR_INST_RETIRED.JCC", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of JCC branch instructions retired" + }, + { + "PEBS": "1", + "PublicDescription": "TAKEN_JCC counts the number of taken conditional branch (JCC) instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.", + "EventCode": "0xC4", + "Counter": "0,1", + "UMask": "0xfe", + "EventName": "BR_INST_RETIRED.TAKEN_JCC", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of taken JCC branch instructions retired" + }, + { + "PEBS": "1", + "PublicDescription": "CALL counts the number of near CALL branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.", + "EventCode": "0xC4", + "Counter": "0,1", + "UMask": "0xf9", + "EventName": "BR_INST_RETIRED.CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of near CALL branch instructions retired" + }, + { + "PEBS": "1", + "PublicDescription": "REL_CALL counts the number of near relative CALL branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.", + "EventCode": "0xC4", + "Counter": "0,1", + "UMask": "0xfd", + "EventName": "BR_INST_RETIRED.REL_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of near relative CALL branch instructions retired" + }, + { + "PEBS": "1", + "PublicDescription": "IND_CALL counts the number of near indirect CALL branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.", + "EventCode": "0xC4", + "Counter": "0,1", + "UMask": "0xfb", + "EventName": "BR_INST_RETIRED.IND_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of near indirect CALL branch instructions retired" + }, + { + "PEBS": "1", + "PublicDescription": "RETURN counts the number of near RET branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.", + "EventCode": "0xC4", + "Counter": "0,1", + "UMask": "0xf7", + "EventName": "BR_INST_RETIRED.RETURN", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of near RET branch instructions retired" + }, + { + "PEBS": "1", + "PublicDescription": "NON_RETURN_IND counts the number of near indirect JMP and near indirect CALL branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.", + "EventCode": "0xC4", + "Counter": "0,1", + "UMask": "0xeb", + "EventName": "BR_INST_RETIRED.NON_RETURN_IND", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of near indirect JMP and near indirect CALL branch instructions retired" + }, + { + "PEBS": "1", + "PublicDescription": "FAR counts the number of far branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.", + "EventCode": "0xC4", + "Counter": "0,1", + "UMask": "0xbf", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of far branch instructions retired" + }, + { + "PEBS": "1", + "PublicDescription": "ALL_BRANCHES counts the number of any mispredicted branch instructions retired. This umask is an architecturally defined event. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.", + "EventCode": "0xC5", + "Counter": "0,1", + "UMask": "0x0", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of mispredicted branch instructions retired" + }, + { + "PEBS": "1", + "PublicDescription": "JCC counts the number of mispredicted conditional branches (JCC) instructions retired. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.", + "EventCode": "0xC5", + "Counter": "0,1", + "UMask": "0x7e", + "EventName": "BR_MISP_RETIRED.JCC", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of mispredicted JCC branch instructions retired" + }, + { + "PEBS": "1", + "PublicDescription": "TAKEN_JCC counts the number of mispredicted taken conditional branch (JCC) instructions retired. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.", + "EventCode": "0xC5", + "Counter": "0,1", + "UMask": "0xfe", + "EventName": "BR_MISP_RETIRED.TAKEN_JCC", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of mispredicted taken JCC branch instructions retired" + }, + { + "PEBS": "1", + "PublicDescription": "IND_CALL counts the number of mispredicted near indirect CALL branch instructions retired. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.", + "EventCode": "0xC5", + "Counter": "0,1", + "UMask": "0xfb", + "EventName": "BR_MISP_RETIRED.IND_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of mispredicted near indirect CALL branch instructions retired" + }, + { + "PEBS": "1", + "PublicDescription": "RETURN counts the number of mispredicted near RET branch instructions retired. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.", + "EventCode": "0xC5", + "Counter": "0,1", + "UMask": "0xf7", + "EventName": "BR_MISP_RETIRED.RETURN", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of mispredicted near RET branch instructions retired" + }, + { + "PEBS": "1", + "PublicDescription": "NON_RETURN_IND counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.", + "EventCode": "0xC5", + "Counter": "0,1", + "UMask": "0xeb", + "EventName": "BR_MISP_RETIRED.NON_RETURN_IND", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired" + }, + { + "PublicDescription": "This event counts the number of micro-ops retired that were supplied from MSROM.", + "EventCode": "0xC2", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.MS", + "SampleAfterValue": "2000003", + "BriefDescription": "MSROM micro-ops retired" + }, + { + "PublicDescription": "This event counts the number of micro-ops retired. The processor decodes complex macro instructions into a sequence of simpler micro-ops. Most instructions are composed of one or two micro-ops. Some instructions are decoded into longer sequences such as repeat instructions, floating point transcendental instructions, and assists. In some cases micro-op sequences are fused or whole instructions are fused into one micro-op. See other UOPS_RETIRED events for differentiating retired fused and non-fused micro-ops.", + "EventCode": "0xC2", + "Counter": "0,1", + "UMask": "0x10", + "EventName": "UOPS_RETIRED.ALL", + "SampleAfterValue": "2000003", + "BriefDescription": "Micro-ops retired" + }, + { + "PublicDescription": "This event counts the number of times that a program writes to a code section. Self-modifying code causes a severe penalty in all Intel? architecture processors.", + "EventCode": "0xC3", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "MACHINE_CLEARS.SMC", + "SampleAfterValue": "200003", + "BriefDescription": "Self-Modifying Code detected" + }, + { + "PublicDescription": "This event counts the number of times that pipeline stalled due to FP operations needing assists.", + "EventCode": "0xC3", + "Counter": "0,1", + "UMask": "0x4", + "EventName": "MACHINE_CLEARS.FP_ASSIST", + "SampleAfterValue": "200003", + "BriefDescription": "Stalls due to FP assists" + }, + { + "PublicDescription": "Machine clears happen when something happens in the machine that causes the hardware to need to take special care to get the right answer. When such a condition is signaled on an instruction, the front end of the machine is notified that it must restart, so no more instructions will be decoded from the current path. All instructions \"older\" than this one will be allowed to finish. This instruction and all \"younger\" instructions must be cleared, since they must not be allowed to complete. Essentially, the hardware waits until the problematic instruction is the oldest instruction in the machine. This means all older instructions are retired, and all pending stores (from older instructions) are completed. Then the new path of instructions from the front end are allowed to start into the machine. There are many conditions that might cause a machine clear (including the receipt of an interrupt, or a trap or a fault). All those conditions (including but not limited to MACHINE_CLEARS.MEMORY_ORDERING, MACHINE_CLEARS.SMC, and MACHINE_CLEARS.FP_ASSIST) are captured in the ANY event. In addition, some conditions can be specifically counted (i.e. SMC, MEMORY_ORDERING, FP_ASSIST). However, the sum of SMC, MEMORY_ORDERING, and FP_ASSIST machine clears will not necessarily equal the number of ANY.", + "EventCode": "0xC3", + "Counter": "0,1", + "UMask": "0x8", + "EventName": "MACHINE_CLEARS.ALL", + "SampleAfterValue": "200003", + "BriefDescription": "Counts all machine clears" + }, + { + "PublicDescription": "Counts the number of cycles when no uops are allocated and the ROB is full (less than 2 entries available).", + "EventCode": "0xCA", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "NO_ALLOC_CYCLES.ROB_FULL", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of cycles when no uops are allocated and the ROB is full (less than 2 entries available)" + }, + { + "PublicDescription": "Counts the number of cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted jump to retire. After the misprediction is detected, the front end will start immediately but the allocate pipe stalls until the mispredicted.", + "EventCode": "0xCA", + "Counter": "0,1", + "UMask": "0x4", + "EventName": "NO_ALLOC_CYCLES.MISPREDICTS", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted jump to retire. After the misprediction is detected, the front end will start immediately but the allocate pipe stalls until the mispredicted " + }, + { + "EventCode": "0xCA", + "Counter": "0,1", + "UMask": "0x20", + "EventName": "NO_ALLOC_CYCLES.RAT_STALL", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of cycles when no uops are allocated and a RATstall is asserted." + }, + { + "PublicDescription": "The NO_ALLOC_CYCLES.NOT_DELIVERED event is used to measure front-end inefficiencies, i.e. when front-end of the machine is not delivering micro-ops to the back-end and the back-end is not stalled. This event can be used to identify if the machine is truly front-end bound. When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance. Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into micro-ops (uops) in machine understandable format and putting them into a micro-op queue to be consumed by back end. The back-end then takes these micro-ops, allocates the required resources. When all resources are ready, micro-ops are executed. If the back-end is not ready to accept micro-ops from the front-end, then we do not want to count these as front-end bottlenecks. However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more UOPS. This event counts the cycles only when back-end is requesting more uops and front-end is not able to provide them. Some examples of conditions that cause front-end efficiencies are: Icache misses, ITLB misses, and decoder restrictions that limit the the front-end bandwidth.", + "EventCode": "0xCA", + "Counter": "0,1", + "UMask": "0x50", + "EventName": "NO_ALLOC_CYCLES.NOT_DELIVERED", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of cycles when no uops are allocated, the IQ is empty, and no other condition is blocking allocation." + }, + { + "PublicDescription": "The NO_ALLOC_CYCLES.ALL event counts the number of cycles when the front-end does not provide any instructions to be allocated for any reason. This event indicates the cycles where an allocation stalls occurs, and no UOPS are allocated in that cycle.", + "EventCode": "0xCA", + "Counter": "0,1", + "UMask": "0x3f", + "EventName": "NO_ALLOC_CYCLES.ALL", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of cycles when no uops are allocated for any reason." + }, + { + "PublicDescription": "Counts the number of cycles and allocation pipeline is stalled and is waiting for a free MEC reservation station entry. The cycles should be appropriately counted in case of the cracked ops e.g. In case of a cracked load-op, the load portion is sent to M.", + "EventCode": "0xCB", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "RS_FULL_STALL.MEC", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of cycles and allocation pipeline is stalled and is waiting for a free MEC reservation station entry. The cycles should be appropriately counted in case of the cracked ops e.g. In case of a cracked load-op, the load portion is sent to M" + }, + { + "EventCode": "0xCB", + "Counter": "0,1", + "UMask": "0x1f", + "EventName": "RS_FULL_STALL.ALL", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of cycles the Alloc pipeline is stalled when any one of the RSs (IEC, FPC and MEC) is full. This event is a superset of all the individual RS stall event counts." + }, + { + "PublicDescription": "This event counts the number of instructions that retire execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers.", + "EventCode": "0xC0", + "Counter": "0,1", + "UMask": "0x0", + "EventName": "INST_RETIRED.ANY_P", + "SampleAfterValue": "2000003", + "BriefDescription": "Instructions retired" + }, + { + "PublicDescription": "Cycles the divider is busy.This event counts the cycles when the divide unit is unable to accept a new divide UOP because it is busy processing a previously dispatched UOP. The cycles will be counted irrespective of whether or not another divide UOP is waiting to enter the divide unit (from the RS). This event might count cycles while a divide is in progress even if the RS is empty. The divide instruction is one of the longest latency instructions in the machine. Hence, it has a special event associated with it to help determine if divides are delaying the retirement of instructions.", + "EventCode": "0xCD", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "CYCLES_DIV_BUSY.ALL", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles the divider is busy. Does not imply a stall waiting for the divider." + }, + { + "PublicDescription": "This event counts the number of instructions that retire. For instructions that consist of multiple micro-ops, this event counts exactly once, as the last micro-op of the instruction retires. The event continues counting while instructions retire, including during interrupt service routines caused by hardware interrupts, faults or traps. Background: Modern microprocessors employ extensive pipelining and speculative techniques. Since sometimes an instruction is started but never completed, the notion of \"retirement\" is introduced. A retired instruction is one that commits its states. Or stated differently, an instruction might be abandoned at some point. No instruction is truly finished until it retires. This counter measures the number of completed instructions. The fixed event is INST_RETIRED.ANY and the programmable event is INST_RETIRED.ANY_P.", + "EventCode": "0x00", + "Counter": "Fixed counter 1", + "UMask": "0x1", + "EventName": "INST_RETIRED.ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Fixed Counter: Counts the number of instructions retired" + }, + { + "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. In systems with a constant core frequency, this event can give you a measurement of the elapsed time while the core was not in halt state by dividing the event count by the core frequency. This event is architecturally defined and is a designated fixed counter. CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.CORE_P use the core frequency which may change from time to time. CPU_CLK_UNHALTE.REF_TSC and CPU_CLK_UNHALTED.REF are not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. The fixed events are CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.REF_TSC and the programmable events are CPU_CLK_UNHALTED.CORE_P and CPU_CLK_UNHALTED.REF.", + "EventCode": "0x00", + "Counter": "Fixed counter 2", + "UMask": "0x2", + "EventName": "CPU_CLK_UNHALTED.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles" + }, + { + "PublicDescription": "Counts the number of reference cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. Divide this event count by core frequency to determine the elapsed time while the core was not in halt state. Divide this event count by core frequency to determine the elapsed time while the core was not in halt state. This event is architecturally defined and is a designated fixed counter. CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.CORE_P use the core frequency which may change from time to time. CPU_CLK_UNHALTE.REF_TSC and CPU_CLK_UNHALTED.REF are not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. The fixed events are CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.REF_TSC and the programmable events are CPU_CLK_UNHALTED.CORE_P and CPU_CLK_UNHALTED.REF.", + "EventCode": "0x00", + "Counter": "Fixed counter 3", + "UMask": "0x3", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "SampleAfterValue": "2000003", + "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles" + }, + { + "PublicDescription": "This event counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time.", + "EventCode": "0x3C", + "Counter": "0,1", + "UMask": "0x0", + "EventName": "CPU_CLK_UNHALTED.CORE_P", + "SampleAfterValue": "2000003", + "BriefDescription": "Core cycles when core is not halted" + }, + { + "PublicDescription": "This event counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time.", + "EventCode": "0x3C", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "CPU_CLK_UNHALTED.REF", + "SampleAfterValue": "2000003", + "BriefDescription": "Reference cycles when core is not halted" + }, + { + "PublicDescription": "The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end. The BACLEARS.ANY event counts the number of baclears for any type of branch.", + "EventCode": "0xE6", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "BACLEARS.ALL", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of baclears" + }, + { + "PublicDescription": "The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end. The BACLEARS.RETURN event counts the number of RETURN baclears.", + "EventCode": "0xE6", + "Counter": "0,1", + "UMask": "0x8", + "EventName": "BACLEARS.RETURN", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of RETURN baclears" + }, + { + "PublicDescription": "The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end. The BACLEARS.COND event counts the number of JCC (Jump on Condtional Code) baclears.", + "EventCode": "0xE6", + "Counter": "0,1", + "UMask": "0x10", + "EventName": "BACLEARS.COND", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of JCC baclears" + }, + { + "PEBS": "2", + "PublicDescription": "ALL_TAKEN_BRANCHES counts the number of all taken branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.", + "EventCode": "0xC4", + "Counter": "0,1", + "UMask": "0x80", + "PEBScounters": "0,1", + "EventName": "BR_INST_RETIRED.ALL_TAKEN_BRANCHES", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of taken branch instructions retired" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/silvermont/virtual-memory.json b/tools/perf/pmu-events/arch/x86/silvermont/virtual-memory.json new file mode 100644 index 000000000000..ad31479f8f60 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/silvermont/virtual-memory.json @@ -0,0 +1,69 @@ +[ + { + "PEBS": "1", + "PublicDescription": "This event counts the number of load ops retired that had DTLB miss.", + "EventCode": "0x04", + "Counter": "0,1", + "UMask": "0x8", + "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS", + "SampleAfterValue": "200003", + "BriefDescription": "Loads missed DTLB" + }, + { + "PublicDescription": "This event counts when a data (D) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.", + "EventCode": "0x05", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "PAGE_WALKS.D_SIDE_WALKS", + "SampleAfterValue": "100003", + "BriefDescription": "D-side page-walks", + "EdgeDetect": "1" + }, + { + "PublicDescription": "This event counts every cycle when a D-side (walks due to a load) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks.", + "EventCode": "0x05", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "PAGE_WALKS.D_SIDE_CYCLES", + "SampleAfterValue": "200003", + "BriefDescription": "Duration of D-side page-walks in core cycles" + }, + { + "PublicDescription": "This event counts when an instruction (I) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.", + "EventCode": "0x05", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "PAGE_WALKS.I_SIDE_WALKS", + "SampleAfterValue": "100003", + "BriefDescription": "I-side page-walks", + "EdgeDetect": "1" + }, + { + "PublicDescription": "This event counts every cycle when a I-side (walks due to an instruction fetch) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks.", + "EventCode": "0x05", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "PAGE_WALKS.I_SIDE_CYCLES", + "SampleAfterValue": "200003", + "BriefDescription": "Duration of I-side page-walks in core cycles" + }, + { + "PublicDescription": "This event counts when a data (D) page walk or an instruction (I) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.", + "EventCode": "0x05", + "Counter": "0,1", + "UMask": "0x3", + "EventName": "PAGE_WALKS.WALKS", + "SampleAfterValue": "100003", + "BriefDescription": "Total page walks that are completed (I-side and D-side)", + "EdgeDetect": "1" + }, + { + "PublicDescription": "This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress. Since a pagewalk implies a TLB miss, the approximate cost of a TLB miss can be determined from this event.", + "EventCode": "0x05", + "Counter": "0,1", + "UMask": "0x3", + "EventName": "PAGE_WALKS.CYCLES", + "SampleAfterValue": "200003", + "BriefDescription": "Total cycles for all the page walks. (I-side and D-side)" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/skylake/cache.json b/tools/perf/pmu-events/arch/x86/skylake/cache.json new file mode 100644 index 000000000000..0551a9ba865d --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/skylake/cache.json @@ -0,0 +1,4299 @@ +[ + { + "PEBS": "1", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x11", + "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load instructions that miss the STLB.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x12", + "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", + "SampleAfterValue": "100003", + "BriefDescription": "Retired store instructions that miss the STLB.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "L1_Hit_Indication": "1" + }, + { + "PEBS": "1", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x21", + "EventName": "MEM_INST_RETIRED.LOCK_LOADS", + "SampleAfterValue": "100007", + "BriefDescription": "Retired load instructions with locked access.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x41", + "EventName": "MEM_INST_RETIRED.SPLIT_LOADS", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load instructions that split across a cacheline boundary.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x42", + "EventName": "MEM_INST_RETIRED.SPLIT_STORES", + "SampleAfterValue": "100003", + "BriefDescription": "Retired store instructions that split across a cacheline boundary.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "L1_Hit_Indication": "1" + }, + { + "PEBS": "1", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x81", + "EventName": "MEM_INST_RETIRED.ALL_LOADS", + "SampleAfterValue": "2000003", + "BriefDescription": "All retired load instructions.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x82", + "EventName": "MEM_INST_RETIRED.ALL_STORES", + "SampleAfterValue": "2000003", + "BriefDescription": "All retired store instructions.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "L1_Hit_Indication": "1" + }, + { + "PEBS": "1", + "PublicDescription": "Retired load instructions with L1 cache hits as data sources.", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_LOAD_RETIRED.L1_HIT", + "SampleAfterValue": "2000003", + "BriefDescription": "Retired load instructions with L1 cache hits as data sources", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "PublicDescription": "Retired load instructions with L2 cache hits as data sources.", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MEM_LOAD_RETIRED.L2_HIT", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load instructions with L2 cache hits as data sources", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "PublicDescription": "Retired load instructions with L3 cache hits as data sources.", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "MEM_LOAD_RETIRED.L3_HIT", + "SampleAfterValue": "50021", + "BriefDescription": "Retired load instructions with L3 cache hits as data sources", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "PublicDescription": "Retired load instructions missed L1 cache as data sources.", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "MEM_LOAD_RETIRED.L1_MISS", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load instructions missed L1 cache as data sources", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "PublicDescription": "Retired load instructions missed L2 cache as data sources.", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "MEM_LOAD_RETIRED.L2_MISS", + "SampleAfterValue": "50021", + "BriefDescription": "Retired load instructions missed L2 cache as data sources", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "PublicDescription": "Retired load instructions missed L3 cache as data sources.", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "MEM_LOAD_RETIRED.L3_MISS", + "SampleAfterValue": "100007", + "BriefDescription": "Retired load instructions missed L3 cache as data sources", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "PublicDescription": "Retired load instructions which data sources were load missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "MEM_LOAD_RETIRED.FB_HIT", + "SampleAfterValue": "100007", + "BriefDescription": "Retired load instructions which data sources were load missed L1 but hit FB due to preceding miss to the same cache line with data not ready", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "SampleAfterValue": "20011", + "BriefDescription": "Retired load instructions which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "PublicDescription": "Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache.", + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", + "SampleAfterValue": "20011", + "BriefDescription": "Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "PublicDescription": "Retired load instructions which data sources were HitM responses from shared L3.", + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", + "SampleAfterValue": "20011", + "BriefDescription": "Retired load instructions which data sources were HitM responses from shared L3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "PublicDescription": "Retired load instructions which data sources were hits in L3 without snoops required.", + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load instructions which data sources were hits in L3 without snoops required", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PEBS": "1", + "EventCode": "0xD4", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "MEM_LOAD_MISC_RETIRED.UC", + "SampleAfterValue": "100007", + "BriefDescription": "Retired instructions with at least 1 uncacheable load or lock.", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1" + }, + { + "PublicDescription": "This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", + "EventCode": "0x51", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L1D.REPLACEMENT", + "SampleAfterValue": "2000003", + "BriefDescription": "L1D data line replacements", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand\n from the demand Hit FB, if it is allocated by hardware or software prefetch.\nNote: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", + "EventCode": "0x48", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L1D_PEND_MISS.PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "L1D miss outstandings duration in cycles", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x48", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L1D_PEND_MISS.FB_FULL", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts duration of L1D miss outstanding in cycles.", + "EventCode": "0x48", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with L1D load Misses outstanding.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.", + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "SampleAfterValue": "100003", + "BriefDescription": "Demand Data Read requests sent to uncore", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts both cacheable and noncachaeble code read requests.", + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "SampleAfterValue": "100003", + "BriefDescription": "Cacheable and noncachaeble code read requests", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.", + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "SampleAfterValue": "100003", + "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.", + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", + "SampleAfterValue": "100003", + "BriefDescription": "Demand and prefetch data reads", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, and so on.", + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", + "SampleAfterValue": "100003", + "BriefDescription": "Any memory transaction that reached the SQ.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.\nNote: A prefetch promoted to Demand is counted from the promotion point.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle. ", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation).", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.\nNote: Writeback pending FIFO has six entries.", + "EventCode": "0xB2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts L2 writebacks that access L2 cache.", + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "L2_TRANS.L2_WB", + "SampleAfterValue": "200003", + "BriefDescription": "L2 writebacks that access L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.", + "EventCode": "0x2E", + "Counter": "0,1,2,3", + "UMask": "0x41", + "Errata": "SKL057", + "EventName": "LONGEST_LAT_CACHE.MISS", + "SampleAfterValue": "100003", + "BriefDescription": "Core-originated cacheable demand requests missed L3", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.", + "EventCode": "0x2E", + "Counter": "0,1,2,3", + "UMask": "0x4f", + "Errata": "SKL057", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "SampleAfterValue": "100003", + "BriefDescription": "Core-originated cacheable demand requests that refer to L3", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of cache line split locks sent to the uncore.", + "EventCode": "0xF4", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "SQ_MISC.SPLIT_LOCK", + "SampleAfterValue": "100003", + "BriefDescription": "Number of cache line split locks sent to uncore.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "EventCode": "0xB7, 0xBB", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE", + "SampleAfterValue": "100003", + "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "This event counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x21", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", + "SampleAfterValue": "200003", + "BriefDescription": "Demand Data Read miss L2, no rejects", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of demand Data Read requests that hit L2 cache. Only not rejected loads are counted.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x41", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "SampleAfterValue": "200003", + "BriefDescription": "Demand Data Read requests that hit L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xe1", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "SampleAfterValue": "200003", + "BriefDescription": "Demand Data Read requests", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xe2", + "EventName": "L2_RQSTS.ALL_RFO", + "SampleAfterValue": "200003", + "BriefDescription": "RFO requests to L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the total number of L2 code requests.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xe4", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "SampleAfterValue": "200003", + "BriefDescription": "L2 code requests", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the total number of requests from the L2 hardware prefetchers.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xf8", + "EventName": "L2_RQSTS.ALL_PF", + "SampleAfterValue": "200003", + "BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x38", + "EventName": "L2_RQSTS.PF_MISS", + "SampleAfterValue": "200003", + "BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xd8", + "EventName": "L2_RQSTS.PF_HIT", + "SampleAfterValue": "200003", + "BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "RFO requests that hit L2 cache.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x42", + "EventName": "L2_RQSTS.RFO_HIT", + "SampleAfterValue": "200003", + "BriefDescription": "RFO requests that hit L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "RFO requests that miss L2 cache.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x22", + "EventName": "L2_RQSTS.RFO_MISS", + "SampleAfterValue": "200003", + "BriefDescription": "RFO requests that miss L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x44", + "EventName": "L2_RQSTS.CODE_RD_HIT", + "SampleAfterValue": "200003", + "BriefDescription": "L2 cache hits when fetching instructions, code reads.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "L2 cache misses when fetching instructions.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x24", + "EventName": "L2_RQSTS.CODE_RD_MISS", + "SampleAfterValue": "200003", + "BriefDescription": "L2 cache misses when fetching instructions", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Demand requests that miss L2 cache.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x27", + "EventName": "L2_RQSTS.ALL_DEMAND_MISS", + "SampleAfterValue": "200003", + "BriefDescription": "Demand requests that miss L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Demand requests to L2 cache.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xe7", + "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", + "SampleAfterValue": "200003", + "BriefDescription": "Demand requests to L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "All requests that miss L2 cache.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x3f", + "EventName": "L2_RQSTS.MISS", + "SampleAfterValue": "200003", + "BriefDescription": "All requests that miss L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "All L2 requests.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xff", + "EventName": "L2_RQSTS.REFERENCES", + "SampleAfterValue": "200003", + "BriefDescription": "All L2 requests", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_LINES_OUT.SILENT", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_LINES_OUT.NON_SILENT", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts the number of lines that have been hardware prefetched but not used and now evicted by L2 cache.", + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_LINES_OUT.USELESS_PREF", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of lines that have been hardware prefetched but not used and now evicted by L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does not cover rejects.", + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x1f", + "EventName": "L2_LINES_IN.ALL", + "SampleAfterValue": "100003", + "BriefDescription": "L2 cache lines filling L2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x48", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", + "CounterMask": "6", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_LINES_OUT.USELESS_HWPF", + "SampleAfterValue": "200003", + "BriefDescription": "Counts the number of lines that have been hardware prefetched but not used and now evicted by L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc0408000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L4_HIT_LOCAL_L4 & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000408000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L4_HIT_LOCAL_L4 & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400408000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L4_HIT_LOCAL_L4 & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200408000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L4_HIT_LOCAL_L4 & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100408000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L4_HIT_LOCAL_L4 & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080408000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L4_HIT_LOCAL_L4 & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0040408000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L4_HIT_LOCAL_L4 & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc01c8000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_HIT & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10001c8000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_HIT & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x04001c8000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts any other requests that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x02001c8000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts any other requests that hit in the L3 and the snoops sent to sibling cores return clean response.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x01001c8000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts any other requests that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00801c8000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_HIT & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00401c8000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_HIT & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc0108000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_HIT_S & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000108000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_HIT_S & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400108000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_HIT_S & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200108000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_HIT_S & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100108000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_HIT_S & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080108000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_HIT_S & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0040108000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_HIT_S & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc0088000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_HIT_E & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000088000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_HIT_E & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400088000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_HIT_E & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200088000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_HIT_E & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100088000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_HIT_E & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080088000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_HIT_E & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0040088000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_HIT_E & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc0048000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_HIT_M & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000048000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_HIT_M & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400048000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_HIT_M & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200048000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_HIT_M & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100048000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_HIT_M & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080048000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_HIT_M & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0040048000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_HIT_M & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc0028000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & SUPPLIER_NONE & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000028000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & SUPPLIER_NONE & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400028000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & SUPPLIER_NONE & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200028000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & SUPPLIER_NONE & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100028000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & SUPPLIER_NONE & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080028000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & SUPPLIER_NONE & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0040028000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & SUPPLIER_NONE & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0000018000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts any other requests that have any response type.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc0400800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L4_HIT_LOCAL_L4.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & L4_HIT_LOCAL_L4 & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000400800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L4_HIT_LOCAL_L4.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & L4_HIT_LOCAL_L4 & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400400800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & L4_HIT_LOCAL_L4 & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200400800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L4_HIT_LOCAL_L4.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & L4_HIT_LOCAL_L4 & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100400800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & L4_HIT_LOCAL_L4 & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080400800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L4_HIT_LOCAL_L4.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & L4_HIT_LOCAL_L4 & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0040400800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L4_HIT_LOCAL_L4.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & L4_HIT_LOCAL_L4 & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc01c0800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & L3_HIT & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10001c0800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & L3_HIT & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x04001c0800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts streaming stores that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x02001c0800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts streaming stores that hit in the L3 and the snoops sent to sibling cores return clean response.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x01001c0800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts streaming stores that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00801c0800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & L3_HIT & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00401c0800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & L3_HIT & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc0100800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_S.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & L3_HIT_S & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000100800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_S.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & L3_HIT_S & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400100800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_S.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & L3_HIT_S & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200100800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_S.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & L3_HIT_S & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100100800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_S.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & L3_HIT_S & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080100800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_S.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & L3_HIT_S & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0040100800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_S.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & L3_HIT_S & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc0080800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_E.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & L3_HIT_E & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000080800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_E.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & L3_HIT_E & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400080800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_E.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & L3_HIT_E & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200080800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_E.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & L3_HIT_E & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100080800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_E.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & L3_HIT_E & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080080800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_E.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & L3_HIT_E & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0040080800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_E.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & L3_HIT_E & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc0040800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_M.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & L3_HIT_M & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000040800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_M.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & L3_HIT_M & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400040800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_M.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & L3_HIT_M & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200040800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_M.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & L3_HIT_M & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100040800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_M.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & L3_HIT_M & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080040800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_M.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & L3_HIT_M & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0040040800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_M.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & L3_HIT_M & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc0020800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.SUPPLIER_NONE.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & SUPPLIER_NONE & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000020800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.SUPPLIER_NONE.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & SUPPLIER_NONE & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400020800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & SUPPLIER_NONE & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200020800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.SUPPLIER_NONE.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & SUPPLIER_NONE & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100020800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.SUPPLIER_NONE.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & SUPPLIER_NONE & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080020800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.SUPPLIER_NONE.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & SUPPLIER_NONE & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0040020800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.SUPPLIER_NONE.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & SUPPLIER_NONE & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0000010800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts streaming stores that have any response type.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc0400100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L4_HIT_LOCAL_L4.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L4_HIT_LOCAL_L4 & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000400100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L4_HIT_LOCAL_L4.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L4_HIT_LOCAL_L4 & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400400100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L4_HIT_LOCAL_L4 & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200400100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L4_HIT_LOCAL_L4.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L4_HIT_LOCAL_L4 & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100400100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L4_HIT_LOCAL_L4 & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080400100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L4_HIT_LOCAL_L4.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L4_HIT_LOCAL_L4 & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0040400100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L4_HIT_LOCAL_L4.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L4_HIT_LOCAL_L4 & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc01c0100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L3_HIT & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10001c0100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L3_HIT & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x04001c0100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x02001c0100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoops sent to sibling cores return clean response.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x01001c0100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00801c0100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L3_HIT & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00401c0100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L3_HIT & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc0100100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L3_HIT_S & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000100100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L3_HIT_S & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400100100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L3_HIT_S & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200100100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L3_HIT_S & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100100100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L3_HIT_S & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080100100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L3_HIT_S & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0040100100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L3_HIT_S & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc0080100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L3_HIT_E & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000080100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L3_HIT_E & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400080100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L3_HIT_E & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200080100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L3_HIT_E & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100080100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L3_HIT_E & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080080100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L3_HIT_E & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0040080100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L3_HIT_E & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc0040100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L3_HIT_M & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000040100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L3_HIT_M & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400040100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L3_HIT_M & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200040100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L3_HIT_M & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100040100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L3_HIT_M & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080040100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L3_HIT_M & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0040040100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & L3_HIT_M & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc0020100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & SUPPLIER_NONE & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000020100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & SUPPLIER_NONE & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400020100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & SUPPLIER_NONE & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200020100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & SUPPLIER_NONE & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100020100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & SUPPLIER_NONE & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080020100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & SUPPLIER_NONE & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0040020100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_RFO & SUPPLIER_NONE & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0000010100 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that have any response type.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc0400080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L4_HIT_LOCAL_L4.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L4_HIT_LOCAL_L4 & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000400080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L4_HIT_LOCAL_L4 & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400400080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L4_HIT_LOCAL_L4 & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200400080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L4_HIT_LOCAL_L4 & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100400080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L4_HIT_LOCAL_L4 & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080400080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L4_HIT_LOCAL_L4 & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0040400080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L4_HIT_LOCAL_L4.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L4_HIT_LOCAL_L4 & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc01c0080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L3_HIT & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10001c0080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L3_HIT & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x04001c0080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x02001c0080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoops sent to sibling cores return clean response.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x01001c0080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00801c0080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L3_HIT & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00401c0080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L3_HIT & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc0100080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L3_HIT_S & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000100080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L3_HIT_S & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400100080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L3_HIT_S & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200100080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L3_HIT_S & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100100080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L3_HIT_S & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080100080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L3_HIT_S & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0040100080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L3_HIT_S & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc0080080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L3_HIT_E & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000080080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L3_HIT_E & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400080080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L3_HIT_E & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200080080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L3_HIT_E & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100080080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L3_HIT_E & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080080080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L3_HIT_E & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0040080080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L3_HIT_E & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc0040080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L3_HIT_M & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000040080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L3_HIT_M & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400040080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L3_HIT_M & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200040080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L3_HIT_M & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100040080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L3_HIT_M & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080040080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L3_HIT_M & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0040040080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & L3_HIT_M & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc0020080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & SUPPLIER_NONE & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000020080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & SUPPLIER_NONE & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400020080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & SUPPLIER_NONE & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200020080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & SUPPLIER_NONE & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100020080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & SUPPLIER_NONE & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080020080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & SUPPLIER_NONE & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0040020080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "PF_L3_DATA_RD & SUPPLIER_NONE & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0000010080 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that have any response type.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc0400004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L4_HIT_LOCAL_L4 & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000400004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L4_HIT_LOCAL_L4 & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400400004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L4_HIT_LOCAL_L4 & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200400004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L4_HIT_LOCAL_L4 & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100400004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L4_HIT_LOCAL_L4 & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080400004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L4_HIT_LOCAL_L4 & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0040400004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L4_HIT_LOCAL_L4 & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc01c0004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L3_HIT & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10001c0004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L3_HIT & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x04001c0004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x02001c0004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand code reads that hit in the L3 and the snoops sent to sibling cores return clean response.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x01001c0004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00801c0004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L3_HIT & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00401c0004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L3_HIT & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc0100004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L3_HIT_S & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000100004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L3_HIT_S & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400100004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L3_HIT_S & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200100004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L3_HIT_S & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100100004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L3_HIT_S & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080100004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L3_HIT_S & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0040100004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L3_HIT_S & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc0080004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L3_HIT_E & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000080004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L3_HIT_E & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400080004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L3_HIT_E & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200080004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L3_HIT_E & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100080004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L3_HIT_E & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080080004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L3_HIT_E & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0040080004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L3_HIT_E & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc0040004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L3_HIT_M & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000040004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L3_HIT_M & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400040004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L3_HIT_M & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200040004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L3_HIT_M & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100040004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L3_HIT_M & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080040004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L3_HIT_M & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0040040004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & L3_HIT_M & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc0020004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & SUPPLIER_NONE & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000020004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & SUPPLIER_NONE & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400020004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & SUPPLIER_NONE & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200020004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & SUPPLIER_NONE & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100020004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & SUPPLIER_NONE & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080020004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & SUPPLIER_NONE & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0040020004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_CODE_RD & SUPPLIER_NONE & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0000010004 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand code reads that have any response type.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc0400002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & L4_HIT_LOCAL_L4 & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000400002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & L4_HIT_LOCAL_L4 & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400400002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & L4_HIT_LOCAL_L4 & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200400002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & L4_HIT_LOCAL_L4 & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100400002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & L4_HIT_LOCAL_L4 & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080400002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & L4_HIT_LOCAL_L4 & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0040400002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & L4_HIT_LOCAL_L4 & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc01c0002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & L3_HIT & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10001c0002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & L3_HIT & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x04001c0002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x02001c0002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoops sent to sibling cores return clean response.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x01001c0002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00801c0002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & L3_HIT & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00401c0002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & L3_HIT & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc0100002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & L3_HIT_S & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000100002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & L3_HIT_S & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400100002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & L3_HIT_S & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200100002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & L3_HIT_S & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100100002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & L3_HIT_S & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080100002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & L3_HIT_S & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0040100002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & L3_HIT_S & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc0080002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & L3_HIT_E & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000080002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & L3_HIT_E & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400080002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & L3_HIT_E & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200080002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & L3_HIT_E & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100080002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & L3_HIT_E & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080080002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & L3_HIT_E & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0040080002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & L3_HIT_E & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc0040002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & L3_HIT_M & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000040002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & L3_HIT_M & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400040002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & L3_HIT_M & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200040002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & L3_HIT_M & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100040002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & L3_HIT_M & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080040002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & L3_HIT_M & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0040040002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & L3_HIT_M & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc0020002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & SUPPLIER_NONE & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000020002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & SUPPLIER_NONE & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400020002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & SUPPLIER_NONE & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200020002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & SUPPLIER_NONE & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100020002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & SUPPLIER_NONE & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080020002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & SUPPLIER_NONE & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0040020002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_RFO & SUPPLIER_NONE & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0000010002 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand data writes (RFOs) that have any response type.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc0400001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L4_HIT_LOCAL_L4 & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000400001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L4_HIT_LOCAL_L4 & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400400001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L4_HIT_LOCAL_L4 & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200400001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L4_HIT_LOCAL_L4 & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100400001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L4_HIT_LOCAL_L4 & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080400001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L4_HIT_LOCAL_L4 & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0040400001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L4_HIT_LOCAL_L4 & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc01c0001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L3_HIT & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10001c0001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L3_HIT & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x04001c0001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x02001c0001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that hit in the L3 and the snoops sent to sibling cores return clean response.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x01001c0001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00801c0001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L3_HIT & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00401c0001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L3_HIT & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc0100001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L3_HIT_S & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000100001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L3_HIT_S & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400100001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L3_HIT_S & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200100001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L3_HIT_S & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100100001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L3_HIT_S & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080100001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L3_HIT_S & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0040100001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L3_HIT_S & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc0080001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L3_HIT_E & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000080001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L3_HIT_E & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400080001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L3_HIT_E & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200080001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L3_HIT_E & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100080001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L3_HIT_E & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080080001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L3_HIT_E & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0040080001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L3_HIT_E & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc0040001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L3_HIT_M & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000040001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L3_HIT_M & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400040001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L3_HIT_M & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200040001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L3_HIT_M & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100040001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L3_HIT_M & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080040001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L3_HIT_M & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0040040001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L3_HIT_M & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc0020001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1000020001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0400020001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0200020001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0100020001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0080020001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0040020001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0000010001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that have any response type.", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/skylake/floating-point.json b/tools/perf/pmu-events/arch/x86/skylake/floating-point.json new file mode 100644 index 000000000000..3c6b59af5d54 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/skylake/floating-point.json @@ -0,0 +1,68 @@ +[ + { + "EventCode": "0xC7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC7", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC7", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "EventCode": "0xC7", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC7", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC7", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.", + "EventCode": "0xCA", + "Counter": "0,1,2,3", + "UMask": "0x1e", + "EventName": "FP_ASSIST.ANY", + "SampleAfterValue": "100003", + "BriefDescription": "Cycles with any input/output SSE or FP assist", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/skylake/frontend.json b/tools/perf/pmu-events/arch/x86/skylake/frontend.json new file mode 100644 index 000000000000..e697dbd63e6e --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/skylake/frontend.json @@ -0,0 +1,472 @@ +[ + { + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "ICACHE_16B.IFDATA_STALL", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x83", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ICACHE_64B.IFTAG_HIT", + "SampleAfterValue": "200003", + "BriefDescription": "Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x83", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "ICACHE_64B.IFTAG_MISS", + "SampleAfterValue": "200003", + "BriefDescription": "Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x83", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "ICACHE_64B.IFTAG_STALL", + "SampleAfterValue": "200003", + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "IDQ.MITE_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "IDQ.DSB_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may 'bypass' the IDQ.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "IDQ.MS_MITE_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may 'bypass' the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "IDQ.MS_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "IDQ.MITE_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "IDQ.DSB_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "IDQ.MS_DSB_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x18", + "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x18", + "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x24", + "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles MITE is delivering 4 Uops", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x24", + "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles MITE is delivering any Uop", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding ?4 ? x? when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread\n\n b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions)\n \n c. Instruction Decode Queue (IDQ) delivers four uops.", + "EventCode": "0x9C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4.", + "EventCode": "0x9C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >=3.", + "EventCode": "0x9C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled", + "CounterMask": "3", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x9C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", + "CounterMask": "2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x9C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with less than 3 uops delivered by the front end.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x9C", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 0?2 cycles.", + "EventCode": "0xAB", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "EventCode": "0xC6", + "MSRValue": "0x11", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "FRONTEND_RETIRED.DSB_MISS", + "MSRIndex": "0x3F7", + "SampleAfterValue": "100007", + "BriefDescription": "Retired Instructions who experienced decode stream buffer (DSB - the decoded instruction-cache) miss.", + "TakenAlone": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xC6", + "MSRValue": "0x12", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "FRONTEND_RETIRED.L1I_MISS", + "MSRIndex": "0x3F7", + "SampleAfterValue": "100007", + "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", + "TakenAlone": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xC6", + "MSRValue": "0x13", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "FRONTEND_RETIRED.L2_MISS", + "MSRIndex": "0x3F7", + "SampleAfterValue": "100007", + "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.", + "TakenAlone": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xC6", + "MSRValue": "0x14", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "FRONTEND_RETIRED.ITLB_MISS", + "MSRIndex": "0x3F7", + "SampleAfterValue": "100007", + "BriefDescription": "Retired Instructions who experienced iTLB true miss.", + "TakenAlone": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xC6", + "MSRValue": "0x15", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "FRONTEND_RETIRED.STLB_MISS", + "MSRIndex": "0x3F7", + "SampleAfterValue": "100007", + "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.", + "TakenAlone": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xC6", + "MSRValue": "0x400206", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_2", + "MSRIndex": "0x3F7", + "SampleAfterValue": "100007", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall.", + "TakenAlone": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xC6", + "MSRValue": "0x200206", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_2", + "MSRIndex": "0x3F7", + "SampleAfterValue": "100007", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.", + "TakenAlone": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xC6", + "MSRValue": "0x400406", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_4", + "MSRIndex": "0x3F7", + "SampleAfterValue": "100007", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.", + "TakenAlone": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EdgeDetect": "1", + "EventName": "IDQ.MS_SWITCHES", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may 'bypass' the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "IDQ.MS_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "EventCode": "0xC6", + "MSRValue": "0x400806", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_8", + "MSRIndex": "0x3F7", + "SampleAfterValue": "100007", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.", + "TakenAlone": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xC6", + "MSRValue": "0x401006", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_16", + "MSRIndex": "0x3F7", + "SampleAfterValue": "100007", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.", + "TakenAlone": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xC6", + "MSRValue": "0x402006", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_32", + "MSRIndex": "0x3F7", + "SampleAfterValue": "100007", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.", + "TakenAlone": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xC6", + "MSRValue": "0x404006", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_64", + "MSRIndex": "0x3F7", + "SampleAfterValue": "100007", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.", + "TakenAlone": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xC6", + "MSRValue": "0x408006", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", + "MSRIndex": "0x3F7", + "SampleAfterValue": "100007", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.", + "TakenAlone": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xC6", + "MSRValue": "0x410006", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_256", + "MSRIndex": "0x3F7", + "SampleAfterValue": "100007", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.", + "TakenAlone": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xC6", + "MSRValue": "0x420006", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", + "MSRIndex": "0x3F7", + "SampleAfterValue": "100007", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.", + "TakenAlone": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xC6", + "MSRValue": "0x100206", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", + "MSRIndex": "0x3F7", + "SampleAfterValue": "100007", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.", + "TakenAlone": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xC6", + "MSRValue": "0x300206", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_3", + "MSRIndex": "0x3F7", + "SampleAfterValue": "100007", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.", + "TakenAlone": "1", + "CounterHTOff": "0,1,2,3" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/skylake/memory.json b/tools/perf/pmu-events/arch/x86/skylake/memory.json new file mode 100644 index 000000000000..d7fd5b06825b --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/skylake/memory.json @@ -0,0 +1,2309 @@ +[ + { + "PublicDescription": "Unfriendly TSX abort triggered by a flowmarker.", + "EventCode": "0x5d", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "TX_EXEC.MISC1", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", + "EventCode": "0x5d", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "TX_EXEC.MISC2", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", + "EventCode": "0x5d", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "TX_EXEC.MISC3", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "RTM region detected inside HLE.", + "EventCode": "0x5d", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "TX_EXEC.MISC4", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", + "EventCode": "0x5d", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "TX_EXEC.MISC5", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.", + "EventCode": "0xC8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "HLE_RETIRED.START", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an HLE execution started.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of times HLE commit succeeded.", + "EventCode": "0xC8", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "HLE_RETIRED.COMMIT", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an HLE execution successfully committed", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "PublicDescription": "Number of times HLE abort was triggered.", + "EventCode": "0xC8", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "HLE_RETIRED.ABORTED", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one). ", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC8", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "HLE_RETIRED.ABORTED_MEM", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC8", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "HLE_RETIRED.ABORTED_TIMER", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", + "EventCode": "0xC8", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.). ", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type.", + "EventCode": "0xC8", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "HLE_RETIRED.ABORTED_MEMTYPE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC8", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "HLE_RETIRED.ABORTED_EVENTS", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.", + "EventCode": "0xC9", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "RTM_RETIRED.START", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an RTM execution started.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of times RTM commit succeeded.", + "EventCode": "0xC9", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "RTM_RETIRED.COMMIT", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an RTM execution successfully committed", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "PublicDescription": "Number of times RTM abort was triggered.", + "EventCode": "0xC9", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "RTM_RETIRED.ABORTED", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one). ", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", + "EventCode": "0xC9", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "RTM_RETIRED.ABORTED_MEM", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC9", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "RTM_RETIRED.ABORTED_TIMER", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.", + "EventCode": "0xC9", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type.", + "EventCode": "0xC9", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", + "EventCode": "0xC9", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "RTM_RETIRED.ABORTED_EVENTS", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.", + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x2", + "Errata": "SKL089", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "SampleAfterValue": "100003", + "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "2", + "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", + "EventCode": "0xCD", + "MSRValue": "0x4", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "SampleAfterValue": "100003", + "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 4 cycles.", + "TakenAlone": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "2", + "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", + "EventCode": "0xCD", + "MSRValue": "0x8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "MSRIndex": "0x3F6", + "SampleAfterValue": "50021", + "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 8 cycles.", + "TakenAlone": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "2", + "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", + "EventCode": "0xCD", + "MSRValue": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "MSRIndex": "0x3F6", + "SampleAfterValue": "20011", + "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 16 cycles.", + "TakenAlone": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "2", + "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", + "EventCode": "0xCD", + "MSRValue": "0x20", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "MSRIndex": "0x3F6", + "SampleAfterValue": "100007", + "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 32 cycles.", + "TakenAlone": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "2", + "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", + "EventCode": "0xCD", + "MSRValue": "0x40", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "MSRIndex": "0x3F6", + "SampleAfterValue": "2003", + "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 64 cycles.", + "TakenAlone": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "2", + "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", + "EventCode": "0xCD", + "MSRValue": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "MSRIndex": "0x3F6", + "SampleAfterValue": "1009", + "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 128 cycles.", + "TakenAlone": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "2", + "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", + "EventCode": "0xCD", + "MSRValue": "0x100", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "MSRIndex": "0x3F6", + "SampleAfterValue": "503", + "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 256 cycles.", + "TakenAlone": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "2", + "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", + "EventCode": "0xCD", + "MSRValue": "0x200", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "MSRIndex": "0x3F6", + "SampleAfterValue": "101", + "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 512 cycles.", + "TakenAlone": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Number of times a TSX line had a cache conflict.", + "EventCode": "0x54", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "TX_MEM.ABORT_CONFLICT", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x54", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "TX_MEM.ABORT_CAPACITY", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", + "EventCode": "0x54", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", + "EventCode": "0x54", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", + "EventCode": "0x54", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", + "EventCode": "0x54", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of times we could not allocate Lock Buffer.", + "EventCode": "0x54", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Demand Data Read requests who miss L3 cache.", + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", + "SampleAfterValue": "100003", + "BriefDescription": "Demand Data Read requests who miss L3 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.", + "CounterMask": "2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x6", + "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", + "SampleAfterValue": "2000003", + "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", + "CounterMask": "6", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ.", + "CounterMask": "6", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3ffc008000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_MISS & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x203c008000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_MISS & SNOOP_NON_DRAM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x103c008000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_MISS & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x043c008000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_MISS & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x023c008000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_MISS & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x013c008000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_MISS & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00bc008000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_MISS & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x007c008000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_MISS & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3fc4008000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_MISS_LOCAL_DRAM & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2004008000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_MISS_LOCAL_DRAM & SNOOP_NON_DRAM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1004008000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_MISS_LOCAL_DRAM & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0404008000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_MISS_LOCAL_DRAM & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0204008000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_MISS_LOCAL_DRAM & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0104008000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_MISS_LOCAL_DRAM & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0084008000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_MISS_LOCAL_DRAM & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0044008000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_MISS_LOCAL_DRAM & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2000408000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L4_HIT_LOCAL_L4 & SNOOP_NON_DRAM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x20001c8000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_HIT & SNOOP_NON_DRAM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2000108000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_HIT_S & SNOOP_NON_DRAM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2000088000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_HIT_E & SNOOP_NON_DRAM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2000048000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & L3_HIT_M & SNOOP_NON_DRAM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2000028000 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "OTHER & SUPPLIER_NONE & SNOOP_NON_DRAM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3ffc000800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & L3_MISS & ANY_SNOOP", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x203c000800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & L3_MISS & SNOOP_NON_DRAM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x103c000800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & L3_MISS & SNOOP_HITM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x043c000800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & L3_MISS & SNOOP_HIT_NO_FWD", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x023c000800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & L3_MISS & SNOOP_MISS", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x013c000800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & L3_MISS & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00bc000800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & L3_MISS & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x007c000800 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "STREAMING_STORES & L3_MISS & SPL_HIT", + "Offcore": "1", + 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"0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0104000001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NOT_NEEDED", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0084000001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NONE", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x0044000001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & SPL_HIT", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2000400001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L4_HIT_LOCAL_L4 & SNOOP_NON_DRAM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x20001c0001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L3_HIT & SNOOP_NON_DRAM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2000100001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L3_HIT_S & SNOOP_NON_DRAM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2000080001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L3_HIT_E & SNOOP_NON_DRAM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2000040001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & L3_HIT_M & SNOOP_NON_DRAM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2000020001 ", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & SNOOP_NON_DRAM", + "Offcore": "1", + "CounterHTOff": "0,1,2,3" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/skylake/other.json b/tools/perf/pmu-events/arch/x86/skylake/other.json new file mode 100644 index 000000000000..cfdc323acc82 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/skylake/other.json @@ -0,0 +1,12 @@ +[ + { + "PublicDescription": "This event counts the number of hardware interruptions received by the processor.", + "EventCode": "0xCB", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "HW_INTERRUPTS.RECEIVED", + "SampleAfterValue": "100003", + "BriefDescription": "Number of hardware interrupts received by the processor.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/skylake/pipeline.json b/tools/perf/pmu-events/arch/x86/skylake/pipeline.json new file mode 100644 index 000000000000..0f7adb809be3 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/skylake/pipeline.json @@ -0,0 +1,939 @@ +[ + { + "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. \nNotes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. \nCounting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.", + "EventCode": "0x00", + "Counter": "Fixed counter 1", + "UMask": "0x1", + "EventName": "INST_RETIRED.ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Instructions retired from execution.", + "CounterHTOff": "Fixed counter 1" + }, + { + "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.", + "EventCode": "0x00", + "Counter": "Fixed counter 2", + "UMask": "0x2", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "SampleAfterValue": "2000003", + "BriefDescription": "Core cycles when the thread is not in halt state", + "CounterHTOff": "Fixed counter 2" + }, + { + "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", + "EventCode": "0x00", + "Counter": "Fixed counter 3", + "UMask": "0x3", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "SampleAfterValue": "2000003", + "BriefDescription": "Reference cycles when the core is not in halt state.", + "CounterHTOff": "Fixed counter 3" + }, + { + "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.", + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "SampleAfterValue": "2000003", + "BriefDescription": "Thread cycles when thread is not in halt state", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xE6", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BACLEARS.ANY", + "SampleAfterValue": "100003", + "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LSD.UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of Uops delivered by the LSD.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", + "EventCode": "0x87", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ILD_STALL.LCP", + "SampleAfterValue": "2000003", + "BriefDescription": "Stalls caused by changing prefix length of the instruction.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles checkpoints in Resource Allocation Table (RAT) are recovering from JEClear or machine clear.", + "EventCode": "0x0D", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "INT_MISC.RECOVERY_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0D", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles the issue-stage is waiting for front-end to fetch from resteered path following branch misprediction or machine clear events.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts resource-related stall cycles. Reasons for stalls can be as follows:\n - *any* u-arch structure got full (LB, SB, RS, ROB, BOB, LM, Physical Register Reclaim Table (PRRT), or Physical History Table (PHT) slots)\n - *any* u-arch structure got empty (like INT/SIMD FreeLists)\n - FPU control word (FPCW), MXCSR\nand others. This counts cycles that the pipeline backend blocked uop delivery from the front end.", + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "RESOURCE_STALLS.ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Resource-related stall cycles", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front end.", + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "RESOURCE_STALLS.SB", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS).", + "EventCode": "0x0E", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_ISSUED.ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0E", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "UOPS_ISSUED.SLOW_LEA", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.", + "EventCode": "0x0E", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts cycles during which the reservation station (RS) is empty for the thread.\nNote: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.", + "EventCode": "0x5E", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "RS_EVENTS.EMPTY_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5E", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EdgeDetect": "1", + "EventName": "RS_EVENTS.EMPTY_END", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT.", + "EventCode": "0xCC", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", + "SampleAfterValue": "2000003", + "BriefDescription": "Increments whenever there is an update to the LBR array.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of machine clears (nukes) of any type.", + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EdgeDetect": "1", + "EventName": "MACHINE_CLEARS.COUNT", + "SampleAfterValue": "100003", + "BriefDescription": "Number of machine clears (nukes) of any type. ", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts self-modifying code (SMC) detected, which causes a machine clear.", + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "MACHINE_CLEARS.SMC", + "SampleAfterValue": "100003", + "BriefDescription": "Self-modifying code (SMC) detected.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two).", + "EventCode": "0xC0", + "Counter": "0,1,2,3", + "UMask": "0x0", + "Errata": "SKL091, SKL044", + "EventName": "INST_RETIRED.ANY_P", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of instructions retired. General Counter - architectural event", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "2", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts instructions retired.", + "EventCode": "0xC0", + "Counter": "1", + "UMask": "0x1", + "Errata": "SKL091, SKL044", + "EventName": "INST_RETIRED.PREC_DIST", + "SampleAfterValue": "2000003", + "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution", + "CounterHTOff": "1" + }, + { + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts the number of retirement slots used.", + "EventCode": "0xC2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "SampleAfterValue": "2000003", + "BriefDescription": "Retirement slots used.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts cycles without actually retired uops.", + "EventCode": "0xC2", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles without actually retired uops.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.", + "EventCode": "0xC2", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with less than 10 actually retired uops.", + "CounterMask": "10", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts conditional branch instructions retired.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Errata": "SKL091", + "EventName": "BR_INST_RETIRED.CONDITIONAL", + "SampleAfterValue": "400009", + "BriefDescription": "Conditional branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts both direct and indirect near call instructions retired.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x2", + "Errata": "SKL091", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "SampleAfterValue": "100007", + "BriefDescription": "Direct and indirect near call instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts all (macro) branch instructions retired.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x0", + "Errata": "SKL091", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "SampleAfterValue": "400009", + "BriefDescription": "All (macro) branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts return instructions retired.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x8", + "Errata": "SKL091", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "SampleAfterValue": "100007", + "BriefDescription": "Return instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts not taken branch instructions retired.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x10", + "Errata": "SKL091", + "EventName": "BR_INST_RETIRED.NOT_TAKEN", + "SampleAfterValue": "400009", + "BriefDescription": "Not taken branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts taken branch instructions retired.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x20", + "Errata": "SKL091", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "SampleAfterValue": "400009", + "BriefDescription": "Taken branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts far branch instructions retired.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x40", + "Errata": "SKL091", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "SampleAfterValue": "100007", + "BriefDescription": "Far branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "2", + "PublicDescription": "This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x4", + "Errata": "SKL091", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", + "SampleAfterValue": "400009", + "BriefDescription": "All (macro) branch instructions retired. ", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted conditional branch instructions retired.", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BR_MISP_RETIRED.CONDITIONAL", + "SampleAfterValue": "400009", + "BriefDescription": "Mispredicted conditional branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "PublicDescription": "This event counts both taken and not taken retired mispredicted direct and indirect near calls, including both register and memory indirect.", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "BR_MISP_RETIRED.NEAR_CALL", + "SampleAfterValue": "400009", + "BriefDescription": "Mispredicted direct and indirect near call instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts all mispredicted macro branch instructions retired.", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "SampleAfterValue": "400009", + "BriefDescription": "All mispredicted macro branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "SampleAfterValue": "400009", + "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "2", + "PublicDescription": "This is a precise version of BR_MISP_RETIRED.ALL_BRANCHES that counts all mispredicted macro branch instructions retired.", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", + "SampleAfterValue": "400009", + "BriefDescription": "Mispredicted macro branch instructions retired. ", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Number of uops to be executed per-thread each cycle.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_EXECUTED.THREAD", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of uops executed from any thread.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of uops executed on the core.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "UOPS_EXECUTED.X87", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts the number of x87 uops dispatched.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.", + "EventCode": "0xB1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_EXECUTED.STALL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles where at least 1 uop was executed per-thread.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles where at least 1 uop was executed per-thread", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles where at least 2 uops were executed per-thread.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles where at least 2 uops were executed per-thread", + "CounterMask": "2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles where at least 3 uops were executed per-thread.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles where at least 3 uops were executed per-thread", + "CounterMask": "3", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles where at least 4 uops were executed per-thread.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles where at least 4 uops were executed per-thread", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA6", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles where no uops were executed, the Reservation Station was not empty, the Store Buffer was full and there was no outstanding load.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA6", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA6", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA6", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "EXE_ACTIVITY.3_PORTS_UTIL", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA6", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA6", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles where the Store Buffer was full and no outstanding load.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are executed in port 0", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are executed in port 1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are executed in port 2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are executed in port 3", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are executed in port 4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are executed in port 5", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "UOPS_DISPATCHED_PORT.PORT_6", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are executed in port 6", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "UOPS_DISPATCHED_PORT.PORT_7", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are executed in port 7", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", + "SampleAfterValue": "2000003", + "BriefDescription": "Total execution stalls.", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", + "CounterMask": "8", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0xc", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", + "SampleAfterValue": "2000003", + "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "CounterMask": "12", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by asm inspection of the nearby instructions.", + "EventCode": "0x4C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LOAD_HIT_PRE.SW_PF", + "SampleAfterValue": "100003", + "BriefDescription": "Demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:\n - preceding store conflicts with the load (incomplete overlap)\n\n - store forwarding is impossible due to u-arch limitations\n\n - preceding lock RMW operations are not forwarded\n\n - store has the no-forward bit set (uncacheable/page-split/masked stores)\n\n - all-blocking stores are used (mostly, fences and port I/O)\n\nand others.\nThe most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events.\nSee the table of not supported store forwards in the Optimization Guide.", + "EventCode": "0x03", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "SampleAfterValue": "100003", + "BriefDescription": "Loads blocked by overlapping with store buffer that cannot be forwarded .", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "EventCode": "0x03", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "LD_BLOCKS.NO_SR", + "SampleAfterValue": "100003", + "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.", + "EventCode": "0x07", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "SampleAfterValue": "100003", + "BriefDescription": "False dependencies in MOB due to partial compare on address.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x5", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", + "SampleAfterValue": "2000003", + "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", + "CounterMask": "5", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles while memory subsystem has an outstanding load.", + "CounterMask": "16", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x14", + "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", + "CounterMask": "20", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", + "SampleAfterValue": "2503", + "BriefDescription": "Core crystal clock cycles when the thread is unhalted.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "2000003", + "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "2", + "PublicDescription": "Number of cycles using an always true condition applied to PEBS instructions retired event. (inst_ret< 16)", + "EventCode": "0xC0", + "Invert": "1", + "Counter": "0,2,3", + "UMask": "0x1", + "Errata": "SKL091, SKL044", + "EventName": "INST_RETIRED.TOTAL_CYCLES_PS", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of cycles using always true condition applied to PEBS instructions retired event.", + "CounterMask": "10", + "CounterHTOff": "0,2,3" + }, + { + "EventCode": "0x14", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ARITH.DIVIDER_ACTIVE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LSD.CYCLES_ACTIVE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LSD.CYCLES_4_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC1", + "Counter": "0,1,2,3", + "UMask": "0x3f", + "EventName": "OTHER_ASSISTS.ANY", + "SampleAfterValue": "100003", + "BriefDescription": "Number of times a microcode assist is invoked by HW other than FP-assist. Examples include AD (page Access Dirty) and AVX* related assists.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register.\r\nFor more information, refer to ?Mixing Intel AVX and Intel SSE Code? section of the Optimization Guide.", + "EventCode": "0x0E", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector registers.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x00", + "Counter": "Fixed counter 2", + "UMask": "0x2", + "AnyThread": "1", + "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "CounterHTOff": "Fixed counter 2" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x0", + "AnyThread": "1", + "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "2503", + "BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0D", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", + "CounterMask": "2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", + "CounterMask": "3", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts when the Current Privilege Level (CPL) transitions from ring 1, 2 or 3 to ring 0 (Kernel).", + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EdgeDetect": "1", + "EventName": "CPU_CLK_UNHALTED.RING0_TRANS", + "SampleAfterValue": "100007", + "BriefDescription": "Counts when there is a transition from ring 1, 2 or 3 to ring 0.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "SampleAfterValue": "2503", + "BriefDescription": "Core crystal clock cycles when the thread is unhalted.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "2503", + "BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "2503", + "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/skylake/virtual-memory.json b/tools/perf/pmu-events/arch/x86/skylake/virtual-memory.json new file mode 100644 index 000000000000..02f32cbf6789 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/skylake/virtual-memory.json @@ -0,0 +1,272 @@ +[ + { + "PublicDescription": "This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).", + "EventCode": "0xAE", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ITLB.ITLB_FLUSH", + "SampleAfterValue": "100007", + "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x4F", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "EPT.WALK_PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request type.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", + "SampleAfterValue": "100003", + "BriefDescription": "Misses at all ITLB levels that cause page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "SampleAfterValue": "100003", + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "SampleAfterValue": "100003", + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", + "SampleAfterValue": "100003", + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (1G)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "ITLB_MISSES.WALK_PENDING", + "SampleAfterValue": "100003", + "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake. ", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "ITLB_MISSES.STLB_HIT", + "SampleAfterValue": "100003", + "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", + "SampleAfterValue": "100003", + "BriefDescription": "Load misses in all DTLB levels that cause page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "SampleAfterValue": "2000003", + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "SampleAfterValue": "2000003", + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", + "SampleAfterValue": "2000003", + "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake. ", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "SampleAfterValue": "2000003", + "BriefDescription": "Loads that miss the DTLB and hit the STLB.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", + "SampleAfterValue": "100003", + "BriefDescription": "Store misses in all DTLB levels that cause page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "SampleAfterValue": "100003", + "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "SampleAfterValue": "100003", + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", + "SampleAfterValue": "100003", + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (1G)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "DTLB_STORE_MISSES.WALK_PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake. ", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "SampleAfterValue": "100003", + "BriefDescription": "Stores that miss the DTLB and hit the STLB.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of DTLB flush attempts of the thread-specific entries.", + "EventCode": "0xBD", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "TLB_FLUSH.DTLB_THREAD", + "SampleAfterValue": "100007", + "BriefDescription": "DTLB flush attempts of the thread-specific entries", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).", + "EventCode": "0xBD", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "TLB_FLUSH.STLB_ANY", + "SampleAfterValue": "100007", + "BriefDescription": "STLB flush attempts", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0xe", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "SampleAfterValue": "100003", + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0xe", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "SampleAfterValue": "100003", + "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0xe", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "SampleAfterValue": "100003", + "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", + "SampleAfterValue": "100003", + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store. EPT page walk duration are excluded in Skylake. ", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "SampleAfterValue": "100003", + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page walk duration are excluded in Skylake. ", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "ITLB_MISSES.WALK_ACTIVE", + "SampleAfterValue": "100003", + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json b/tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json new file mode 100644 index 000000000000..6e61ae20d01a --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json @@ -0,0 +1,2817 @@ +[ + { + "EventCode": "0x63", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "CACHE_LOCK_CYCLES.L1D", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles L1D locked" + }, + { + "EventCode": "0x63", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "CACHE_LOCK_CYCLES.L1D_L2", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles L1D and L2 locked" + }, + { + "EventCode": "0x51", + "Counter": "0,1", + "UMask": "0x4", + "EventName": "L1D.M_EVICT", + "SampleAfterValue": "2000000", + "BriefDescription": "L1D cache lines replaced in M state" + }, + { + "EventCode": "0x51", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "L1D.M_REPL", + "SampleAfterValue": "2000000", + "BriefDescription": "L1D cache lines allocated in the M state" + }, + { + "EventCode": "0x51", + "Counter": "0,1", + "UMask": "0x8", + "EventName": "L1D.M_SNOOP_EVICT", + "SampleAfterValue": "2000000", + "BriefDescription": "L1D snoop eviction of cache lines in M state" + }, + { + "EventCode": "0x51", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "L1D.REPL", + "SampleAfterValue": "2000000", + "BriefDescription": "L1 data cache lines allocated" + }, + { + "EventCode": "0x52", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT", + "SampleAfterValue": "2000000", + "BriefDescription": "L1D prefetch load lock accepted in fill buffer" + }, + { + "EventCode": "0x4E", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "L1D_PREFETCH.MISS", + "SampleAfterValue": "200000", + "BriefDescription": "L1D hardware prefetch misses" + }, + { + "EventCode": "0x4E", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "L1D_PREFETCH.REQUESTS", + "SampleAfterValue": "200000", + "BriefDescription": "L1D hardware prefetch requests" + }, + { + "EventCode": "0x4E", + "Counter": "0,1", + "UMask": "0x4", + "EventName": "L1D_PREFETCH.TRIGGERS", + "SampleAfterValue": "200000", + "BriefDescription": "L1D hardware prefetch requests triggered" + }, + { + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L1D_WB_L2.E_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L1 writebacks to L2 in E state" + }, + { + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L1D_WB_L2.I_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L1 writebacks to L2 in I state (misses)" + }, + { + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L1D_WB_L2.M_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L1 writebacks to L2 in M state" + }, + { + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "L1D_WB_L2.MESI", + "SampleAfterValue": "100000", + "BriefDescription": "All L1 writebacks to L2" + }, + { + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L1D_WB_L2.S_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L1 writebacks to L2 in S state" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0xff", + "EventName": "L2_DATA_RQSTS.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "All L2 data requests" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data demand loads in E state" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data demand loads in I state (misses)" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data demand loads in M state" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "L2_DATA_RQSTS.DEMAND.MESI", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data demand requests" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data demand loads in S state" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data prefetches in E state" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data prefetches in the I state (misses)" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data prefetches in M state" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0xf0", + "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", + "SampleAfterValue": "200000", + "BriefDescription": "All L2 data prefetches" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data prefetches in the S state" + }, + { + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x7", + "EventName": "L2_LINES_IN.ANY", + "SampleAfterValue": "100000", + "BriefDescription": "L2 lines alloacated" + }, + { + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_LINES_IN.E_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 lines allocated in the E state" + }, + { + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_LINES_IN.S_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 lines allocated in the S state" + }, + { + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "L2_LINES_OUT.ANY", + "SampleAfterValue": "100000", + "BriefDescription": "L2 lines evicted" + }, + { + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_LINES_OUT.DEMAND_CLEAN", + "SampleAfterValue": "100000", + "BriefDescription": "L2 lines evicted by a demand request" + }, + { + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_LINES_OUT.DEMAND_DIRTY", + "SampleAfterValue": "100000", + "BriefDescription": "L2 modified lines evicted by a demand request" + }, + { + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_LINES_OUT.PREFETCH_CLEAN", + "SampleAfterValue": "100000", + "BriefDescription": "L2 lines evicted by a prefetch request" + }, + { + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_LINES_OUT.PREFETCH_DIRTY", + "SampleAfterValue": "100000", + "BriefDescription": "L2 modified lines evicted by a prefetch request" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "L2_RQSTS.IFETCH_HIT", + "SampleAfterValue": "200000", + "BriefDescription": "L2 instruction fetch hits" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "L2_RQSTS.IFETCH_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "L2 instruction fetch misses" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "L2_RQSTS.IFETCHES", + "SampleAfterValue": "200000", + "BriefDescription": "L2 instruction fetches" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_RQSTS.LD_HIT", + "SampleAfterValue": "200000", + "BriefDescription": "L2 load hits" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_RQSTS.LD_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "L2 load misses" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x3", + "EventName": "L2_RQSTS.LOADS", + "SampleAfterValue": "200000", + "BriefDescription": "L2 requests" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xaa", + "EventName": "L2_RQSTS.MISS", + "SampleAfterValue": "200000", + "BriefDescription": "All L2 misses" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "L2_RQSTS.PREFETCH_HIT", + "SampleAfterValue": "200000", + "BriefDescription": "L2 prefetch hits" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "L2_RQSTS.PREFETCH_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "L2 prefetch misses" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xc0", + "EventName": "L2_RQSTS.PREFETCHES", + "SampleAfterValue": "200000", + "BriefDescription": "All L2 prefetches" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xff", + "EventName": "L2_RQSTS.REFERENCES", + "SampleAfterValue": "200000", + "BriefDescription": "All L2 requests" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_RQSTS.RFO_HIT", + "SampleAfterValue": "200000", + "BriefDescription": "L2 RFO hits" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_RQSTS.RFO_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "L2 RFO misses" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xc", + "EventName": "L2_RQSTS.RFOS", + "SampleAfterValue": "200000", + "BriefDescription": "L2 RFO requests" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "L2_TRANSACTIONS.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "All L2 transactions" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "L2_TRANSACTIONS.FILL", + "SampleAfterValue": "200000", + "BriefDescription": "L2 fill transactions" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_TRANSACTIONS.IFETCH", + "SampleAfterValue": "200000", + "BriefDescription": "L2 instruction fetch transactions" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "L2_TRANSACTIONS.L1D_WB", + "SampleAfterValue": "200000", + "BriefDescription": "L1D writeback to L2 transactions" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_TRANSACTIONS.LOAD", + "SampleAfterValue": "200000", + "BriefDescription": "L2 Load transactions" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_TRANSACTIONS.PREFETCH", + "SampleAfterValue": "200000", + "BriefDescription": "L2 prefetch transactions" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_TRANSACTIONS.RFO", + "SampleAfterValue": "200000", + "BriefDescription": "L2 RFO transactions" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "L2_TRANSACTIONS.WB", + "SampleAfterValue": "200000", + "BriefDescription": "L2 writeback to LLC transactions" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "L2_WRITE.LOCK.E_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 demand lock RFOs in E state" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0xe0", + "EventName": "L2_WRITE.LOCK.HIT", + "SampleAfterValue": "100000", + "BriefDescription": "All demand L2 lock RFOs that hit the cache" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "L2_WRITE.LOCK.I_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 demand lock RFOs in I state (misses)" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "L2_WRITE.LOCK.M_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 demand lock RFOs in M state" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0xf0", + "EventName": "L2_WRITE.LOCK.MESI", + "SampleAfterValue": "100000", + "BriefDescription": "All demand L2 lock RFOs" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "L2_WRITE.LOCK.S_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 demand lock RFOs in S state" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0xe", + "EventName": "L2_WRITE.RFO.HIT", + "SampleAfterValue": "100000", + "BriefDescription": "All L2 demand store RFOs that hit the cache" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_WRITE.RFO.I_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 demand store RFOs in I state (misses)" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_WRITE.RFO.M_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 demand store RFOs in M state" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "L2_WRITE.RFO.MESI", + "SampleAfterValue": "100000", + "BriefDescription": "All L2 demand store RFOs" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_WRITE.RFO.S_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 demand store RFOs in S state" + }, + { + "EventCode": "0x2E", + "Counter": "0,1,2,3", + "UMask": "0x41", + "EventName": "LONGEST_LAT_CACHE.MISS", + "SampleAfterValue": "100000", + "BriefDescription": "Longest latency cache miss" + }, + { + "EventCode": "0x2E", + "Counter": "0,1,2,3", + "UMask": "0x4f", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "SampleAfterValue": "200000", + "BriefDescription": "Longest latency cache reference" + }, + { + "PEBS": "1", + "EventCode": "0xB", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_INST_RETIRED.LOADS", + "SampleAfterValue": "2000000", + "BriefDescription": "Instructions retired which contains a load (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xB", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MEM_INST_RETIRED.STORES", + "SampleAfterValue": "2000000", + "BriefDescription": "Instructions retired which contains a store (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xCB", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "MEM_LOAD_RETIRED.HIT_LFB", + "SampleAfterValue": "200000", + "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xCB", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_LOAD_RETIRED.L1D_HIT", + "SampleAfterValue": "2000000", + "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xCB", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MEM_LOAD_RETIRED.L2_HIT", + "SampleAfterValue": "200000", + "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xCB", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "MEM_LOAD_RETIRED.LLC_MISS", + "SampleAfterValue": "10000", + "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xCB", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", + "SampleAfterValue": "40000", + "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xCB", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", + "SampleAfterValue": "40000", + "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)" + }, + { + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "OFFCORE_REQUESTS.ANY", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore requests" + }, + { + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "OFFCORE_REQUESTS.ANY.READ", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore read requests" + }, + { + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "OFFCORE_REQUESTS.ANY.RFO", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests" + }, + { + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code read requests" + }, + { + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data read requests" + }, + { + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "OFFCORE_REQUESTS.DEMAND.RFO", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests" + }, + { + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore L1 data cache writebacks" + }, + { + "EventCode": "0x60", + "UMask": "0x8", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ", + "SampleAfterValue": "2000000", + "BriefDescription": "Outstanding offcore reads" + }, + { + "EventCode": "0x60", + "UMask": "0x8", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles offcore reads busy", + "CounterMask": "1" + }, + { + "EventCode": "0x60", + "UMask": "0x2", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE", + "SampleAfterValue": "2000000", + "BriefDescription": "Outstanding offcore demand code reads" + }, + { + "EventCode": "0x60", + "UMask": "0x2", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles offcore demand code read busy", + "CounterMask": "1" + }, + { + "EventCode": "0x60", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA", + "SampleAfterValue": "2000000", + "BriefDescription": "Outstanding offcore demand data reads" + }, + { + "EventCode": "0x60", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles offcore demand data read busy", + "CounterMask": "1" + }, + { + "EventCode": "0x60", + "UMask": "0x4", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO", + "SampleAfterValue": "2000000", + "BriefDescription": "Outstanding offcore demand RFOs" + }, + { + "EventCode": "0x60", + "UMask": "0x4", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles offcore demand RFOs busy", + "CounterMask": "1" + }, + { + "EventCode": "0xB2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS_SQ_FULL", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests blocked due to Super Queue full" + }, + { + "EventCode": "0xF4", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "SQ_MISC.LRU_HINTS", + "SampleAfterValue": "2000000", + "BriefDescription": "Super Queue LRU hints sent to LLC" + }, + { + "EventCode": "0xF4", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "SQ_MISC.SPLIT_LOCK", + "SampleAfterValue": "2000000", + "BriefDescription": "Super Queue lock splits across a cache line" + }, + { + "EventCode": "0x6", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "STORE_BLOCKS.AT_RET", + "SampleAfterValue": "200000", + "BriefDescription": "Loads delayed with at-Retirement block code" + }, + { + "EventCode": "0x6", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "STORE_BLOCKS.L1D_BLOCK", + "SampleAfterValue": "200000", + "BriefDescription": "Cacheable loads delayed with L1D block code" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x0", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", + "MSRIndex": "0x3F6", + "SampleAfterValue": "2000000", + "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x400", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", + "MSRIndex": "0x3F6", + "SampleAfterValue": "100", + "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x80", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", + "MSRIndex": "0x3F6", + "SampleAfterValue": "1000", + "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x10", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", + "MSRIndex": "0x3F6", + "SampleAfterValue": "10000", + "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x4000", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", + "MSRIndex": "0x3F6", + "SampleAfterValue": "5", + "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x800", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", + "MSRIndex": "0x3F6", + "SampleAfterValue": "50", + "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x100", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", + "MSRIndex": "0x3F6", + "SampleAfterValue": "500", + "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x20", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", + "MSRIndex": "0x3F6", + "SampleAfterValue": "5000", + "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x8000", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", + "MSRIndex": "0x3F6", + "SampleAfterValue": "3", + "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x4", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", + "MSRIndex": "0x3F6", + "SampleAfterValue": "50000", + "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x1000", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", + "MSRIndex": "0x3F6", + "SampleAfterValue": "20", + "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x200", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", + "MSRIndex": "0x3F6", + "SampleAfterValue": "200", + "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x40", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", + "MSRIndex": "0x3F6", + "SampleAfterValue": "2000", + "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x8", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", + "MSRIndex": "0x3F6", + "SampleAfterValue": "20000", + "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x2000", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", + "MSRIndex": "0x3F6", + "SampleAfterValue": "10", + "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x5011", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x7f11", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_CACHE_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xff11", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_LOCATION", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x8011", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = IO_CSR_MMIO", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x111", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_NO_OTHER_CORE", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x211", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x411", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HITM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x711", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LOCAL_CACHE", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1011", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x811", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = REMOTE_CACHE_HITM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x5044", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x7f44", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_CACHE_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xff44", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_LOCATION", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x8044", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = IO_CSR_MMIO", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x144", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x244", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x444", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x744", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LOCAL_CACHE", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1044", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x844", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = REMOTE_CACHE_HITM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x50ff", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x7fff", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_CACHE_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xffff", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_LOCATION", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x80ff", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = IO_CSR_MMIO", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1ff", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_NO_OTHER_CORE", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2ff", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4ff", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HITM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x7ff", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LOCAL_CACHE", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10ff", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x8ff", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = REMOTE_CACHE_HITM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x5022", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x7f22", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_CACHE_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xff22", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_LOCATION", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x8022", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY RFO and RESPONSE = IO_CSR_MMIO", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x122", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x222", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x422", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x722", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LOCAL_CACHE", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1022", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x822", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY RFO and RESPONSE = REMOTE_CACHE_HITM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x5008", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x7f08", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_CACHE_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xff08", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_LOCATION", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x8008", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = CORE_WB and RESPONSE = IO_CSR_MMIO", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x108", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_NO_OTHER_CORE", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x208", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x408", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HITM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x708", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LOCAL_CACHE", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1008", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x808", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = CORE_WB and RESPONSE = REMOTE_CACHE_HITM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x5077", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x7f77", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_CACHE_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xff77", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_LOCATION", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x8077", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = IO_CSR_MMIO", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x177", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x277", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x477", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x777", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LOCAL_CACHE", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1077", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x877", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = REMOTE_CACHE_HITM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x5033", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x7f33", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_CACHE_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xff33", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_LOCATION", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x8033", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DATA_IN and RESPONSE = IO_CSR_MMIO", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x133", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_NO_OTHER_CORE", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x233", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x433", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HITM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x733", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LOCAL_CACHE", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1033", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x833", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DATA_IN and RESPONSE = REMOTE_CACHE_HITM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x5003", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x7f03", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_CACHE_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xff03", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_LOCATION", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x8003", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = IO_CSR_MMIO", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x103", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x203", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x403", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x703", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LOCAL_CACHE", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x803", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = REMOTE_CACHE_HITM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x5001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x7f01", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_CACHE_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xff01", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LOCATION", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x8001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = IO_CSR_MMIO", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x101", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x201", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x401", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x701", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_CACHE", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x801", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_CACHE_HITM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x5004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x7f04", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_CACHE_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xff04", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LOCATION", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x8004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = IO_CSR_MMIO", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x104", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x204", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x404", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x704", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_CACHE", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x804", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_CACHE_HITM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x5002", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x7f02", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_CACHE_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xff02", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_LOCATION", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x8002", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = IO_CSR_MMIO", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x102", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x202", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x402", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x702", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LOCAL_CACHE", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1002", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x802", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = REMOTE_CACHE_HITM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x5080", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = OTHER and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x7f80", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_CACHE_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xff80", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_LOCATION", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x8080", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = OTHER and RESPONSE = IO_CSR_MMIO", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x180", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_NO_OTHER_CORE", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x280", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x480", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HITM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x780", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = OTHER and RESPONSE = LOCAL_CACHE", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1080", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = OTHER and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x880", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = OTHER and RESPONSE = REMOTE_CACHE_HITM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x5050", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x7f50", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_CACHE_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xff50", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_LOCATION", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x8050", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_DATA and RESPONSE = IO_CSR_MMIO", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x150", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x250", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x450", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x750", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LOCAL_CACHE", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1050", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x850", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_DATA and RESPONSE = REMOTE_CACHE_HITM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x5010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x7f10", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_CACHE_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xff10", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_LOCATION", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x8010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = IO_CSR_MMIO", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x110", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x210", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x410", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x710", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LOCAL_CACHE", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x810", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = REMOTE_CACHE_HITM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x5040", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x7f40", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_CACHE_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xff40", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_LOCATION", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x8040", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_RFO and RESPONSE = IO_CSR_MMIO", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x140", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x240", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x440", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x740", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LOCAL_CACHE", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1040", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x840", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_RFO and RESPONSE = REMOTE_CACHE_HITM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x5020", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x7f20", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_CACHE_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xff20", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_LOCATION", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x8020", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = IO_CSR_MMIO", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x120", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x220", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x420", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x720", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LOCAL_CACHE", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1020", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x820", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = REMOTE_CACHE_HITM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x5070", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x7f70", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_CACHE_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xff70", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_LOCATION", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x8070", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PREFETCH and RESPONSE = IO_CSR_MMIO", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x170", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x270", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x470", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x770", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LOCAL_CACHE", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1070", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x870", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PREFETCH and RESPONSE = REMOTE_CACHE_HITM", + "Offcore": "1" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/floating-point.json b/tools/perf/pmu-events/arch/x86/westmereep-dp/floating-point.json new file mode 100644 index 000000000000..7d2f71a9dee3 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/floating-point.json @@ -0,0 +1,229 @@ +[ + { + "PEBS": "1", + "EventCode": "0xF7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "FP_ASSIST.ALL", + "SampleAfterValue": "20000", + "BriefDescription": "X87 Floating point assists (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xF7", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "FP_ASSIST.INPUT", + "SampleAfterValue": "20000", + "BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xF7", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "FP_ASSIST.OUTPUT", + "SampleAfterValue": "20000", + "BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "FP_COMP_OPS_EXE.MMX", + "SampleAfterValue": "2000000", + "BriefDescription": "MMX Uops" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION", + "SampleAfterValue": "2000000", + "BriefDescription": "SSE* FP double precision Uops" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "FP_COMP_OPS_EXE.SSE_FP", + "SampleAfterValue": "2000000", + "BriefDescription": "SSE and SSE2 FP Uops" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED", + "SampleAfterValue": "2000000", + "BriefDescription": "SSE FP packed Uops" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR", + "SampleAfterValue": "2000000", + "BriefDescription": "SSE FP scalar Uops" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION", + "SampleAfterValue": "2000000", + "BriefDescription": "SSE* FP single precision Uops" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER", + "SampleAfterValue": "2000000", + "BriefDescription": "SSE2 integer Uops" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "FP_COMP_OPS_EXE.X87", + "SampleAfterValue": "2000000", + "BriefDescription": "Computational floating-point operations executed" + }, + { + "EventCode": "0xCC", + "Counter": "0,1,2,3", + "UMask": "0x3", + "EventName": "FP_MMX_TRANS.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "All Floating Point to and from MMX transitions" + }, + { + "EventCode": "0xCC", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "FP_MMX_TRANS.TO_FP", + "SampleAfterValue": "2000000", + "BriefDescription": "Transitions from MMX to Floating Point instructions" + }, + { + "EventCode": "0xCC", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "FP_MMX_TRANS.TO_MMX", + "SampleAfterValue": "2000000", + "BriefDescription": "Transitions from Floating Point to MMX instructions" + }, + { + "EventCode": "0x12", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "SIMD_INT_128.PACK", + "SampleAfterValue": "200000", + "BriefDescription": "128 bit SIMD integer pack operations" + }, + { + "EventCode": "0x12", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "SIMD_INT_128.PACKED_ARITH", + "SampleAfterValue": "200000", + "BriefDescription": "128 bit SIMD integer arithmetic operations" + }, + { + "EventCode": "0x12", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "SIMD_INT_128.PACKED_LOGICAL", + "SampleAfterValue": "200000", + "BriefDescription": "128 bit SIMD integer logical operations" + }, + { + "EventCode": "0x12", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "SIMD_INT_128.PACKED_MPY", + "SampleAfterValue": "200000", + "BriefDescription": "128 bit SIMD integer multiply operations" + }, + { + "EventCode": "0x12", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "SIMD_INT_128.PACKED_SHIFT", + "SampleAfterValue": "200000", + "BriefDescription": "128 bit SIMD integer shift operations" + }, + { + "EventCode": "0x12", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "SIMD_INT_128.SHUFFLE_MOVE", + "SampleAfterValue": "200000", + "BriefDescription": "128 bit SIMD integer shuffle/move operations" + }, + { + "EventCode": "0x12", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "SIMD_INT_128.UNPACK", + "SampleAfterValue": "200000", + "BriefDescription": "128 bit SIMD integer unpack operations" + }, + { + "EventCode": "0xFD", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "SIMD_INT_64.PACK", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD integer 64 bit pack operations" + }, + { + "EventCode": "0xFD", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "SIMD_INT_64.PACKED_ARITH", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD integer 64 bit arithmetic operations" + }, + { + "EventCode": "0xFD", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "SIMD_INT_64.PACKED_LOGICAL", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD integer 64 bit logical operations" + }, + { + "EventCode": "0xFD", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "SIMD_INT_64.PACKED_MPY", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD integer 64 bit packed multiply operations" + }, + { + "EventCode": "0xFD", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "SIMD_INT_64.PACKED_SHIFT", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD integer 64 bit shift operations" + }, + { + "EventCode": "0xFD", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "SIMD_INT_64.SHUFFLE_MOVE", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD integer 64 bit shuffle/move operations" + }, + { + "EventCode": "0xFD", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "SIMD_INT_64.UNPACK", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD integer 64 bit unpack operations" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/frontend.json b/tools/perf/pmu-events/arch/x86/westmereep-dp/frontend.json new file mode 100644 index 000000000000..e5e21e03444d --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/frontend.json @@ -0,0 +1,26 @@ +[ + { + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MACRO_INSTS.DECODED", + "SampleAfterValue": "2000000", + "BriefDescription": "Instructions decoded" + }, + { + "EventCode": "0xA6", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MACRO_INSTS.FUSIONS_DECODED", + "SampleAfterValue": "2000000", + "BriefDescription": "Macro-fused instructions decoded" + }, + { + "EventCode": "0x19", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "TWO_UOP_INSTS_DECODED", + "SampleAfterValue": "2000000", + "BriefDescription": "Two Uop instructions decoded" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/memory.json b/tools/perf/pmu-events/arch/x86/westmereep-dp/memory.json new file mode 100644 index 000000000000..6e0829b7617f --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/memory.json @@ -0,0 +1,758 @@ +[ + { + "EventCode": "0x5", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MISALIGN_MEM_REF.STORE", + "SampleAfterValue": "200000", + "BriefDescription": "Misaligned store references" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3011", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM_AND_REMOTE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_DRAM AND REMOTE_FWD", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xf811", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_LLC_MISS", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4011", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.OTHER_LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = OTHER_LOCAL_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2011", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = REMOTE_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3044", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM_AND_REMOTE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xf844", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_LLC_MISS", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4044", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.OTHER_LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = OTHER_LOCAL_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2044", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = REMOTE_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x30ff", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM_AND_REMOTE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_DRAM AND REMOTE_FWD", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xf8ff", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_LLC_MISS", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x40ff", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.OTHER_LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = OTHER_LOCAL_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x20ff", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = REMOTE_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3022", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM_AND_REMOTE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xf822", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_LLC_MISS", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4022", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.OTHER_LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY RFO and RESPONSE = OTHER_LOCAL_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2022", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = ANY RFO and RESPONSE = REMOTE_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3008", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM_AND_REMOTE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_DRAM AND REMOTE_FWD", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xf808", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_LLC_MISS", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4008", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.OTHER_LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = CORE_WB and RESPONSE = OTHER_LOCAL_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2008", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = CORE_WB and RESPONSE = REMOTE_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3077", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM_AND_REMOTE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xf877", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_LLC_MISS", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4077", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.OTHER_LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = OTHER_LOCAL_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2077", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = REMOTE_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3033", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM_AND_REMOTE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_DRAM AND REMOTE_FWD", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xf833", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_LLC_MISS", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4033", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.OTHER_LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DATA_IN and RESPONSE = OTHER_LOCAL_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2033", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DATA_IN and RESPONSE = REMOTE_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3003", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM_AND_REMOTE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_DRAM AND REMOTE_FWD", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xf803", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_LLC_MISS", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4003", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.OTHER_LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = OTHER_LOCAL_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2003", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = REMOTE_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM_AND_REMOTE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_DRAM AND REMOTE_FWD", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xf801", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LLC_MISS", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OTHER_LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = OTHER_LOCAL_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM_AND_REMOTE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xf804", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LLC_MISS", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.OTHER_LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = OTHER_LOCAL_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3002", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM_AND_REMOTE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xf802", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_LLC_MISS", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4002", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OTHER_LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = OTHER_LOCAL_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2002", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = REMOTE_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3080", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM_AND_REMOTE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_DRAM AND REMOTE_FWD", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xf880", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_LLC_MISS", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4080", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.OTHER_LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = OTHER and RESPONSE = OTHER_LOCAL_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2080", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = OTHER and RESPONSE = REMOTE_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3050", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM_AND_REMOTE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_DRAM AND REMOTE_FWD", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xf850", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_LLC_MISS", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4050", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.OTHER_LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_DATA and RESPONSE = OTHER_LOCAL_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2050", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_DATA and RESPONSE = REMOTE_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM_AND_REMOTE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_DRAM AND REMOTE_FWD", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xf810", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_LLC_MISS", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.OTHER_LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = OTHER_LOCAL_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = REMOTE_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3040", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM_AND_REMOTE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xf840", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_LLC_MISS", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4040", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.OTHER_LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_RFO and RESPONSE = OTHER_LOCAL_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2040", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_RFO and RESPONSE = REMOTE_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3020", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM_AND_REMOTE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xf820", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_LLC_MISS", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4020", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.OTHER_LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = OTHER_LOCAL_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2020", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = REMOTE_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3070", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM_AND_REMOTE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xf870", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_LLC_MISS", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4070", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.OTHER_LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PREFETCH and RESPONSE = OTHER_LOCAL_DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2070", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "REQUEST = PREFETCH and RESPONSE = REMOTE_DRAM", + "Offcore": "1" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/other.json b/tools/perf/pmu-events/arch/x86/westmereep-dp/other.json new file mode 100644 index 000000000000..85133d6a5ce0 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/other.json @@ -0,0 +1,287 @@ +[ + { + "EventCode": "0xE8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BPU_CLEARS.EARLY", + "SampleAfterValue": "2000000", + "BriefDescription": "Early Branch Prediciton Unit clears" + }, + { + "EventCode": "0xE8", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "BPU_CLEARS.LATE", + "SampleAfterValue": "2000000", + "BriefDescription": "Late Branch Prediction Unit clears" + }, + { + "EventCode": "0xE5", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BPU_MISSED_CALL_RET", + "SampleAfterValue": "2000000", + "BriefDescription": "Branch prediction unit missed call or return" + }, + { + "EventCode": "0xD5", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ES_REG_RENAMES", + "SampleAfterValue": "2000000", + "BriefDescription": "ES segment renames" + }, + { + "EventCode": "0x6C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IO_TRANSACTIONS", + "SampleAfterValue": "2000000", + "BriefDescription": "I/O transactions" + }, + { + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L1I.CYCLES_STALLED", + "SampleAfterValue": "2000000", + "BriefDescription": "L1I instruction fetch stall cycles" + }, + { + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L1I.HITS", + "SampleAfterValue": "2000000", + "BriefDescription": "L1I instruction fetch hits" + }, + { + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L1I.MISSES", + "SampleAfterValue": "2000000", + "BriefDescription": "L1I instruction fetch misses" + }, + { + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x3", + "EventName": "L1I.READS", + "SampleAfterValue": "2000000", + "BriefDescription": "L1I Instruction fetches" + }, + { + "EventCode": "0x82", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LARGE_ITLB.HIT", + "SampleAfterValue": "200000", + "BriefDescription": "Large ITLB hit" + }, + { + "EventCode": "0x3", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "LOAD_BLOCK.OVERLAP_STORE", + "SampleAfterValue": "200000", + "BriefDescription": "Loads that partially overlap an earlier store" + }, + { + "EventCode": "0x13", + "Counter": "0,1,2,3", + "UMask": "0x7", + "EventName": "LOAD_DISPATCH.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "All loads dispatched" + }, + { + "EventCode": "0x13", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "LOAD_DISPATCH.MOB", + "SampleAfterValue": "2000000", + "BriefDescription": "Loads dispatched from the MOB" + }, + { + "EventCode": "0x13", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LOAD_DISPATCH.RS", + "SampleAfterValue": "2000000", + "BriefDescription": "Loads dispatched that bypass the MOB" + }, + { + "EventCode": "0x13", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "LOAD_DISPATCH.RS_DELAYED", + "SampleAfterValue": "2000000", + "BriefDescription": "Loads dispatched from stage 305" + }, + { + "EventCode": "0x7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "PARTIAL_ADDRESS_ALIAS", + "SampleAfterValue": "200000", + "BriefDescription": "False dependencies due to partial address aliasing" + }, + { + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "RAT_STALLS.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "All RAT stall cycles" + }, + { + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "RAT_STALLS.FLAGS", + "SampleAfterValue": "2000000", + "BriefDescription": "Flag stall cycles" + }, + { + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "RAT_STALLS.REGISTERS", + "SampleAfterValue": "2000000", + "BriefDescription": "Partial register stall cycles" + }, + { + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "RAT_STALLS.ROB_READ_PORT", + "SampleAfterValue": "2000000", + "BriefDescription": "ROB read port stalls cycles" + }, + { + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "RAT_STALLS.SCOREBOARD", + "SampleAfterValue": "2000000", + "BriefDescription": "Scoreboard stall cycles" + }, + { + "EventCode": "0x4", + "Counter": "0,1,2,3", + "UMask": "0x7", + "EventName": "SB_DRAIN.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "All Store buffer stall cycles" + }, + { + "EventCode": "0xD4", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "SEG_RENAME_STALLS", + "SampleAfterValue": "2000000", + "BriefDescription": "Segment rename stall cycles" + }, + { + "EventCode": "0xB8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "SNOOP_RESPONSE.HIT", + "SampleAfterValue": "100000", + "BriefDescription": "Thread responded HIT to snoop" + }, + { + "EventCode": "0xB8", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "SNOOP_RESPONSE.HITE", + "SampleAfterValue": "100000", + "BriefDescription": "Thread responded HITE to snoop" + }, + { + "EventCode": "0xB8", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "SNOOP_RESPONSE.HITM", + "SampleAfterValue": "100000", + "BriefDescription": "Thread responded HITM to snoop" + }, + { + "EventCode": "0xB4", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "SNOOPQ_REQUESTS.CODE", + "SampleAfterValue": "100000", + "BriefDescription": "Snoop code requests" + }, + { + "EventCode": "0xB4", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "SNOOPQ_REQUESTS.DATA", + "SampleAfterValue": "100000", + "BriefDescription": "Snoop data requests" + }, + { + "EventCode": "0xB4", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "SNOOPQ_REQUESTS.INVALIDATE", + "SampleAfterValue": "100000", + "BriefDescription": "Snoop invalidate requests" + }, + { + "EventCode": "0xB3", + "UMask": "0x4", + "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE", + "SampleAfterValue": "2000000", + "BriefDescription": "Outstanding snoop code requests" + }, + { + "EventCode": "0xB3", + "UMask": "0x4", + "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE_NOT_EMPTY", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles snoop code requests queued", + "CounterMask": "1" + }, + { + "EventCode": "0xB3", + "UMask": "0x1", + "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA", + "SampleAfterValue": "2000000", + "BriefDescription": "Outstanding snoop data requests" + }, + { + "EventCode": "0xB3", + "UMask": "0x1", + "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA_NOT_EMPTY", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles snoop data requests queued", + "CounterMask": "1" + }, + { + "EventCode": "0xB3", + "UMask": "0x2", + "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE", + "SampleAfterValue": "2000000", + "BriefDescription": "Outstanding snoop invalidate requests" + }, + { + "EventCode": "0xB3", + "UMask": "0x2", + "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE_NOT_EMPTY", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles snoop invalidate requests queued", + "CounterMask": "1" + }, + { + "EventCode": "0xF6", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "SQ_FULL_STALL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Super Queue full stall cycles" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/pipeline.json b/tools/perf/pmu-events/arch/x86/westmereep-dp/pipeline.json new file mode 100644 index 000000000000..f130510f7616 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/pipeline.json @@ -0,0 +1,899 @@ +[ + { + "EventCode": "0x14", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ARITH.CYCLES_DIV_BUSY", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles the divider is busy" + }, + { + "EventCode": "0x14", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ARITH.DIV", + "SampleAfterValue": "2000000", + "BriefDescription": "Divide Operations executed", + "CounterMask": "1", + "EdgeDetect": "1" + }, + { + "EventCode": "0x14", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "ARITH.MUL", + "SampleAfterValue": "2000000", + "BriefDescription": "Multiply operations executed" + }, + { + "EventCode": "0xE6", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "BACLEAR.BAD_TARGET", + "SampleAfterValue": "2000000", + "BriefDescription": "BACLEAR asserted with bad target address" + }, + { + "EventCode": "0xE6", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BACLEAR.CLEAR", + "SampleAfterValue": "2000000", + "BriefDescription": "BACLEAR asserted, regardless of cause " + }, + { + "EventCode": "0xA7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BACLEAR_FORCE_IQ", + "SampleAfterValue": "2000000", + "BriefDescription": "Instruction queue forced BACLEAR" + }, + { + "EventCode": "0xE0", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BR_INST_DECODED", + "SampleAfterValue": "2000000", + "BriefDescription": "Branch instructions decoded" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x7f", + "EventName": "BR_INST_EXEC.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "Branch instructions executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BR_INST_EXEC.COND", + "SampleAfterValue": "200000", + "BriefDescription": "Conditional branch instructions executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "BR_INST_EXEC.DIRECT", + "SampleAfterValue": "200000", + "BriefDescription": "Unconditional branches executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL", + "SampleAfterValue": "20000", + "BriefDescription": "Unconditional call branches executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL", + "SampleAfterValue": "20000", + "BriefDescription": "Indirect call branches executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL", + "SampleAfterValue": "20000", + "BriefDescription": "Indirect non call branches executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "BR_INST_EXEC.NEAR_CALLS", + "SampleAfterValue": "20000", + "BriefDescription": "Call branches executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x7", + "EventName": "BR_INST_EXEC.NON_CALLS", + "SampleAfterValue": "200000", + "BriefDescription": "All non call branches executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "BR_INST_EXEC.RETURN_NEAR", + "SampleAfterValue": "20000", + "BriefDescription": "Indirect return branches executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "BR_INST_EXEC.TAKEN", + "SampleAfterValue": "200000", + "BriefDescription": "Taken branches executed" + }, + { + "PEBS": "1", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "SampleAfterValue": "200000", + "BriefDescription": "Retired branch instructions (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BR_INST_RETIRED.CONDITIONAL", + "SampleAfterValue": "200000", + "BriefDescription": "Retired conditional branch instructions (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "SampleAfterValue": "20000", + "BriefDescription": "Retired near call instructions (Precise Event)" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x7f", + "EventName": "BR_MISP_EXEC.ANY", + "SampleAfterValue": "20000", + "BriefDescription": "Mispredicted branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BR_MISP_EXEC.COND", + "SampleAfterValue": "20000", + "BriefDescription": "Mispredicted conditional branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "BR_MISP_EXEC.DIRECT", + "SampleAfterValue": "20000", + "BriefDescription": "Mispredicted unconditional branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL", + "SampleAfterValue": "2000", + "BriefDescription": "Mispredicted non call branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL", + "SampleAfterValue": "2000", + "BriefDescription": "Mispredicted indirect call branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL", + "SampleAfterValue": "2000", + "BriefDescription": "Mispredicted indirect non call branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "BR_MISP_EXEC.NEAR_CALLS", + "SampleAfterValue": "2000", + "BriefDescription": "Mispredicted call branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x7", + "EventName": "BR_MISP_EXEC.NON_CALLS", + "SampleAfterValue": "20000", + "BriefDescription": "Mispredicted non call branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "BR_MISP_EXEC.RETURN_NEAR", + "SampleAfterValue": "2000", + "BriefDescription": "Mispredicted return branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "BR_MISP_EXEC.TAKEN", + "SampleAfterValue": "20000", + "BriefDescription": "Mispredicted taken branches executed" + }, + { + "PEBS": "1", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "SampleAfterValue": "20000", + "BriefDescription": "Mispredicted retired branch instructions (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BR_MISP_RETIRED.CONDITIONAL", + "SampleAfterValue": "20000", + "BriefDescription": "Mispredicted conditional retired branches (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "BR_MISP_RETIRED.NEAR_CALL", + "SampleAfterValue": "2000", + "BriefDescription": "Mispredicted near retired calls (Precise Event)" + }, + { + "EventCode": "0x0", + "Counter": "Fixed counter 3", + "UMask": "0x0", + "EventName": "CPU_CLK_UNHALTED.REF", + "SampleAfterValue": "2000000", + "BriefDescription": "Reference cycles when thread is not halted (fixed counter)" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CPU_CLK_UNHALTED.REF_P", + "SampleAfterValue": "100000", + "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)" + }, + { + "EventCode": "0x0", + "Counter": "Fixed counter 2", + "UMask": "0x0", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles when thread is not halted (fixed counter)" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles when thread is not halted (programmable counter)" + }, + { + "EventCode": "0x3C", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Total CPU cycles", + "CounterMask": "2" + }, + { + "EventCode": "0x87", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "ILD_STALL.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "Any Instruction Length Decoder stall cycles" + }, + { + "EventCode": "0x87", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "ILD_STALL.IQ_FULL", + "SampleAfterValue": "2000000", + "BriefDescription": "Instruction Queue full stall cycles" + }, + { + "EventCode": "0x87", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ILD_STALL.LCP", + "SampleAfterValue": "2000000", + "BriefDescription": "Length Change Prefix stall cycles" + }, + { + "EventCode": "0x87", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "ILD_STALL.MRU", + "SampleAfterValue": "2000000", + "BriefDescription": "Stall cycles due to BPU MRU bypass" + }, + { + "EventCode": "0x87", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "ILD_STALL.REGEN", + "SampleAfterValue": "2000000", + "BriefDescription": "Regen stall cycles" + }, + { + "EventCode": "0x18", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "INST_DECODED.DEC0", + "SampleAfterValue": "2000000", + "BriefDescription": "Instructions that must be decoded by decoder 0" + }, + { + "EventCode": "0x1E", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "INST_QUEUE_WRITE_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles instructions are written to the instruction queue" + }, + { + "EventCode": "0x17", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "INST_QUEUE_WRITES", + "SampleAfterValue": "2000000", + "BriefDescription": "Instructions written to instruction queue." + }, + { + "EventCode": "0x0", + "Counter": "Fixed counter 1", + "UMask": "0x0", + "EventName": "INST_RETIRED.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "Instructions retired (fixed counter)" + }, + { + "PEBS": "1", + "EventCode": "0xC0", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "INST_RETIRED.ANY_P", + "SampleAfterValue": "2000000", + "BriefDescription": "Instructions retired (Programmable counter and Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC0", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "INST_RETIRED.MMX", + "SampleAfterValue": "2000000", + "BriefDescription": "Retired MMX instructions (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC0", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "INST_RETIRED.TOTAL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Total cycles (Precise Event)", + "CounterMask": "16" + }, + { + "PEBS": "1", + "EventCode": "0xC0", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "INST_RETIRED.X87", + "SampleAfterValue": "2000000", + "BriefDescription": "Retired floating-point operations (Precise Event)" + }, + { + "EventCode": "0x4C", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "LOAD_HIT_PRE", + "SampleAfterValue": "200000", + "BriefDescription": "Load operations conflicting with software prefetches" + }, + { + "EventCode": "0xA8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LSD.ACTIVE", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles when uops were delivered by the LSD", + "CounterMask": "1" + }, + { + "EventCode": "0xA8", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LSD.INACTIVE", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles no uops were delivered by the LSD", + "CounterMask": "1" + }, + { + "EventCode": "0x20", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LSD_OVERFLOW", + "SampleAfterValue": "2000000", + "BriefDescription": "Loops that can't stream from the instruction queue" + }, + { + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MACHINE_CLEARS.CYCLES", + "SampleAfterValue": "20000", + "BriefDescription": "Cycles machine clear asserted" + }, + { + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MACHINE_CLEARS.MEM_ORDER", + "SampleAfterValue": "20000", + "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts" + }, + { + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "MACHINE_CLEARS.SMC", + "SampleAfterValue": "20000", + "BriefDescription": "Self-Modifying Code detected" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "RESOURCE_STALLS.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "Resource related stall cycles" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "RESOURCE_STALLS.FPCW", + "SampleAfterValue": "2000000", + "BriefDescription": "FPU control word write stall cycles" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "RESOURCE_STALLS.LOAD", + "SampleAfterValue": "2000000", + "BriefDescription": "Load buffer stall cycles" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "RESOURCE_STALLS.MXCSR", + "SampleAfterValue": "2000000", + "BriefDescription": "MXCSR rename stall cycles" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "RESOURCE_STALLS.OTHER", + "SampleAfterValue": "2000000", + "BriefDescription": "Other Resource related stall cycles" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "RESOURCE_STALLS.ROB_FULL", + "SampleAfterValue": "2000000", + "BriefDescription": "ROB full stall cycles" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "RESOURCE_STALLS.RS_FULL", + "SampleAfterValue": "2000000", + "BriefDescription": "Reservation Station full stall cycles" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "RESOURCE_STALLS.STORE", + "SampleAfterValue": "2000000", + "BriefDescription": "Store buffer stall cycles" + }, + { + "PEBS": "1", + "EventCode": "0xC7", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC7", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC7", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC7", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)" + }, + { + "EventCode": "0xDB", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOP_UNFUSION", + "SampleAfterValue": "2000000", + "BriefDescription": "Uop unfusions due to FP exceptions" + }, + { + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "UOPS_DECODED.ESP_FOLDING", + "SampleAfterValue": "2000000", + "BriefDescription": "Stack pointer instructions decoded" + }, + { + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "UOPS_DECODED.ESP_SYNC", + "SampleAfterValue": "2000000", + "BriefDescription": "Stack pointer sync operations" + }, + { + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops decoded by Microcode Sequencer", + "CounterMask": "1" + }, + { + "EventCode": "0xD1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_DECODED.STALL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles no Uops are decoded", + "CounterMask": "1" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x3f", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles Uops executed on any port (core count)", + "CounterMask": "1" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x1f", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)", + "CounterMask": "1" + }, + { + "EventCode": "0xB1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x3f", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops executed on any port (core count)", + "CounterMask": "1", + "EdgeDetect": "1" + }, + { + "EventCode": "0xB1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1f", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops executed on ports 0-4 (core count)", + "CounterMask": "1", + "EdgeDetect": "1" + }, + { + "EventCode": "0xB1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x3f", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles no Uops issued on any port (core count)", + "CounterMask": "1" + }, + { + "EventCode": "0xB1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1f", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)", + "CounterMask": "1" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_EXECUTED.PORT0", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops executed on port 0" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "UOPS_EXECUTED.PORT015", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops issued on ports 0, 1 or 5" + }, + { + "EventCode": "0xB1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5", + "CounterMask": "1" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.PORT1", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops executed on port 1" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x4", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.PORT2_CORE", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops executed on port 2 (core count)" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x80", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.PORT234_CORE", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops issued on ports 2, 3 or 4" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x8", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.PORT3_CORE", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops executed on port 3 (core count)" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x10", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.PORT4_CORE", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops executed on port 4 (core count)" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "UOPS_EXECUTED.PORT5", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops executed on port 5" + }, + { + "EventCode": "0xE", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_ISSUED.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops issued" + }, + { + "EventCode": "0xE", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles no Uops were issued on any thread", + "CounterMask": "1" + }, + { + "EventCode": "0xE", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles Uops were issued on either thread", + "CounterMask": "1" + }, + { + "EventCode": "0xE", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_ISSUED.FUSED", + "SampleAfterValue": "2000000", + "BriefDescription": "Fused Uops issued" + }, + { + "EventCode": "0xE", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles no Uops were issued", + "CounterMask": "1" + }, + { + "PEBS": "1", + "EventCode": "0xC2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.ACTIVE_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles Uops are being retired", + "CounterMask": "1" + }, + { + "PEBS": "1", + "EventCode": "0xC2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops retired (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "UOPS_RETIRED.MACRO_FUSED", + "SampleAfterValue": "2000000", + "BriefDescription": "Macro-fused Uops retired (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "SampleAfterValue": "2000000", + "BriefDescription": "Retirement slots used (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC2", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles Uops are not retiring (Precise Event)", + "CounterMask": "1" + }, + { + "PEBS": "1", + "EventCode": "0xC2", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Total cycles using precise uop retired event (Precise Event)", + "CounterMask": "16" + }, + { + "PEBS": "2", + "EventCode": "0xC0", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "INST_RETIRED.TOTAL_CYCLES_PS", + "SampleAfterValue": "2000000", + "BriefDescription": "Total cycles (Precise Event)", + "CounterMask": "16" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json b/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json new file mode 100644 index 000000000000..57b53562e2bd --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json @@ -0,0 +1,173 @@ +[ + { + "EventCode": "0x8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "DTLB_LOAD_MISSES.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB load misses" + }, + { + "EventCode": "0x8", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB load miss large page walks" + }, + { + "EventCode": "0x8", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "DTLB_LOAD_MISSES.PDE_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB load miss caused by low part of address" + }, + { + "EventCode": "0x8", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "SampleAfterValue": "2000000", + "BriefDescription": "DTLB second level hit" + }, + { + "EventCode": "0x8", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB load miss page walks complete" + }, + { + "EventCode": "0x8", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "DTLB_LOAD_MISSES.WALK_CYCLES", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB load miss page walk cycles" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "DTLB_MISSES.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB misses" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB miss large page walks" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "DTLB_MISSES.PDE_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB misses casued by low part of address" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "DTLB_MISSES.STLB_HIT", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB first level misses but second level hit" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "DTLB_MISSES.WALK_COMPLETED", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB miss page walks" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "DTLB_MISSES.WALK_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "DTLB miss page walk cycles" + }, + { + "EventCode": "0x4F", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "EPT.WALK_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Extended Page Table walk cycles" + }, + { + "EventCode": "0xAE", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ITLB_FLUSH", + "SampleAfterValue": "2000000", + "BriefDescription": "ITLB flushes" + }, + { + "PEBS": "1", + "EventCode": "0xC8", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "ITLB_MISS_RETIRED", + "SampleAfterValue": "200000", + "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)" + }, + { + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ITLB_MISSES.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "ITLB miss" + }, + { + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "ITLB_MISSES.LARGE_WALK_COMPLETED", + "SampleAfterValue": "200000", + "BriefDescription": "ITLB miss large page walks" + }, + { + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "SampleAfterValue": "200000", + "BriefDescription": "ITLB miss page walks" + }, + { + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "ITLB_MISSES.WALK_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "ITLB miss page walk cycles" + }, + { + "PEBS": "1", + "EventCode": "0xCB", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "MEM_LOAD_RETIRED.DTLB_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "Retired loads that miss the DTLB (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_STORE_RETIRED.DTLB_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "Retired stores that miss the DTLB (Precise Event)" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json new file mode 100644 index 000000000000..dad20f0e3cac --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json @@ -0,0 +1,3233 @@ +[ + { + "EventCode": "0x63", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "CACHE_LOCK_CYCLES.L1D", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles L1D locked" + }, + { + "EventCode": "0x63", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "CACHE_LOCK_CYCLES.L1D_L2", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles L1D and L2 locked" + }, + { + "EventCode": "0x51", + "Counter": "0,1", + "UMask": "0x4", + "EventName": "L1D.M_EVICT", + "SampleAfterValue": "2000000", + "BriefDescription": "L1D cache lines replaced in M state" + }, + { + "EventCode": "0x51", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "L1D.M_REPL", + "SampleAfterValue": "2000000", + "BriefDescription": "L1D cache lines allocated in the M state" + }, + { + "EventCode": "0x51", + "Counter": "0,1", + "UMask": "0x8", + "EventName": "L1D.M_SNOOP_EVICT", + "SampleAfterValue": "2000000", + "BriefDescription": "L1D snoop eviction of cache lines in M state" + }, + { + "EventCode": "0x51", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "L1D.REPL", + "SampleAfterValue": "2000000", + "BriefDescription": "L1 data cache lines allocated" + }, + { + "EventCode": "0x52", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT", + "SampleAfterValue": "2000000", + "BriefDescription": "L1D prefetch load lock accepted in fill buffer" + }, + { + "EventCode": "0x4E", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "L1D_PREFETCH.MISS", + "SampleAfterValue": "200000", + "BriefDescription": "L1D hardware prefetch misses" + }, + { + "EventCode": "0x4E", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "L1D_PREFETCH.REQUESTS", + "SampleAfterValue": "200000", + "BriefDescription": "L1D hardware prefetch requests" + }, + { + "EventCode": "0x4E", + "Counter": "0,1", + "UMask": "0x4", + "EventName": "L1D_PREFETCH.TRIGGERS", + "SampleAfterValue": "200000", + "BriefDescription": "L1D hardware prefetch requests triggered" + }, + { + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L1D_WB_L2.E_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L1 writebacks to L2 in E state" + }, + { + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L1D_WB_L2.I_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L1 writebacks to L2 in I state (misses)" + }, + { + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L1D_WB_L2.M_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L1 writebacks to L2 in M state" + }, + { + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "L1D_WB_L2.MESI", + "SampleAfterValue": "100000", + "BriefDescription": "All L1 writebacks to L2" + }, + { + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L1D_WB_L2.S_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L1 writebacks to L2 in S state" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0xff", + "EventName": "L2_DATA_RQSTS.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "All L2 data requests" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data demand loads in E state" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data demand loads in I state (misses)" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data demand loads in M state" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "L2_DATA_RQSTS.DEMAND.MESI", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data demand requests" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data demand loads in S state" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data prefetches in E state" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data prefetches in the I state (misses)" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data prefetches in M state" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0xf0", + "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", + "SampleAfterValue": "200000", + "BriefDescription": "All L2 data prefetches" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data prefetches in the S state" + }, + { + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x7", + "EventName": "L2_LINES_IN.ANY", + "SampleAfterValue": "100000", + "BriefDescription": "L2 lines alloacated" + }, + { + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_LINES_IN.E_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 lines allocated in the E state" + }, + { + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_LINES_IN.S_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 lines allocated in the S state" + }, + { + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "L2_LINES_OUT.ANY", + "SampleAfterValue": "100000", + "BriefDescription": "L2 lines evicted" + }, + { + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_LINES_OUT.DEMAND_CLEAN", + "SampleAfterValue": "100000", + "BriefDescription": "L2 lines evicted by a demand request" + }, + { + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_LINES_OUT.DEMAND_DIRTY", + "SampleAfterValue": "100000", + "BriefDescription": "L2 modified lines evicted by a demand request" + }, + { + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_LINES_OUT.PREFETCH_CLEAN", + "SampleAfterValue": "100000", + "BriefDescription": "L2 lines evicted by a prefetch request" + }, + { + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_LINES_OUT.PREFETCH_DIRTY", + "SampleAfterValue": "100000", + "BriefDescription": "L2 modified lines evicted by a prefetch request" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "L2_RQSTS.IFETCH_HIT", + "SampleAfterValue": "200000", + "BriefDescription": "L2 instruction fetch hits" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "L2_RQSTS.IFETCH_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "L2 instruction fetch misses" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "L2_RQSTS.IFETCHES", + "SampleAfterValue": "200000", + "BriefDescription": "L2 instruction fetches" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_RQSTS.LD_HIT", + "SampleAfterValue": "200000", + "BriefDescription": "L2 load hits" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_RQSTS.LD_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "L2 load misses" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x3", + "EventName": "L2_RQSTS.LOADS", + "SampleAfterValue": "200000", + "BriefDescription": "L2 requests" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xaa", + "EventName": "L2_RQSTS.MISS", + "SampleAfterValue": "200000", + "BriefDescription": "All L2 misses" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "L2_RQSTS.PREFETCH_HIT", + "SampleAfterValue": "200000", + "BriefDescription": "L2 prefetch hits" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "L2_RQSTS.PREFETCH_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "L2 prefetch misses" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xc0", + "EventName": "L2_RQSTS.PREFETCHES", + "SampleAfterValue": "200000", + "BriefDescription": "All L2 prefetches" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xff", + "EventName": "L2_RQSTS.REFERENCES", + "SampleAfterValue": "200000", + "BriefDescription": "All L2 requests" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_RQSTS.RFO_HIT", + "SampleAfterValue": "200000", + "BriefDescription": "L2 RFO hits" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_RQSTS.RFO_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "L2 RFO misses" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xc", + "EventName": "L2_RQSTS.RFOS", + "SampleAfterValue": "200000", + "BriefDescription": "L2 RFO requests" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "L2_TRANSACTIONS.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "All L2 transactions" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "L2_TRANSACTIONS.FILL", + "SampleAfterValue": "200000", + "BriefDescription": "L2 fill transactions" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_TRANSACTIONS.IFETCH", + "SampleAfterValue": "200000", + "BriefDescription": "L2 instruction fetch transactions" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "L2_TRANSACTIONS.L1D_WB", + "SampleAfterValue": "200000", + "BriefDescription": "L1D writeback to L2 transactions" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_TRANSACTIONS.LOAD", + "SampleAfterValue": "200000", + "BriefDescription": "L2 Load transactions" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_TRANSACTIONS.PREFETCH", + "SampleAfterValue": "200000", + "BriefDescription": "L2 prefetch transactions" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_TRANSACTIONS.RFO", + "SampleAfterValue": "200000", + "BriefDescription": "L2 RFO transactions" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "L2_TRANSACTIONS.WB", + "SampleAfterValue": "200000", + "BriefDescription": "L2 writeback to LLC transactions" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "L2_WRITE.LOCK.E_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 demand lock RFOs in E state" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0xe0", + "EventName": "L2_WRITE.LOCK.HIT", + "SampleAfterValue": "100000", + "BriefDescription": "All demand L2 lock RFOs that hit the cache" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "L2_WRITE.LOCK.I_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 demand lock RFOs in I state (misses)" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "L2_WRITE.LOCK.M_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 demand lock RFOs in M state" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0xf0", + "EventName": "L2_WRITE.LOCK.MESI", + "SampleAfterValue": "100000", + "BriefDescription": "All demand L2 lock RFOs" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "L2_WRITE.LOCK.S_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 demand lock RFOs in S state" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0xe", + "EventName": "L2_WRITE.RFO.HIT", + "SampleAfterValue": "100000", + "BriefDescription": "All L2 demand store RFOs that hit the cache" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_WRITE.RFO.I_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 demand store RFOs in I state (misses)" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_WRITE.RFO.M_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 demand store RFOs in M state" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "L2_WRITE.RFO.MESI", + "SampleAfterValue": "100000", + "BriefDescription": "All L2 demand store RFOs" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_WRITE.RFO.S_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 demand store RFOs in S state" + }, + { + "EventCode": "0x2E", + "Counter": "0,1,2,3", + "UMask": "0x41", + "EventName": "LONGEST_LAT_CACHE.MISS", + "SampleAfterValue": "100000", + "BriefDescription": "Longest latency cache miss" + }, + { + "EventCode": "0x2E", + "Counter": "0,1,2,3", + "UMask": "0x4f", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "SampleAfterValue": "200000", + "BriefDescription": "Longest latency cache reference" + }, + { + "PEBS": "1", + "EventCode": "0xB", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_INST_RETIRED.LOADS", + "SampleAfterValue": "2000000", + "BriefDescription": "Instructions retired which contains a load (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xB", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MEM_INST_RETIRED.STORES", + "SampleAfterValue": "2000000", + "BriefDescription": "Instructions retired which contains a store (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xCB", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "MEM_LOAD_RETIRED.HIT_LFB", + "SampleAfterValue": "200000", + "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xCB", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_LOAD_RETIRED.L1D_HIT", + "SampleAfterValue": "2000000", + "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xCB", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MEM_LOAD_RETIRED.L2_HIT", + "SampleAfterValue": "200000", + "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xCB", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "MEM_LOAD_RETIRED.LLC_MISS", + "SampleAfterValue": "10000", + "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xCB", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", + "SampleAfterValue": "40000", + "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xCB", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", + "SampleAfterValue": "40000", + "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xF", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM", + "SampleAfterValue": "10000", + "BriefDescription": "Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xF", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM", + "SampleAfterValue": "40000", + "BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xF", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT", + "SampleAfterValue": "20000", + "BriefDescription": "Load instructions retired remote cache HIT data source (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xF", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM", + "SampleAfterValue": "10000", + "BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xF", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE", + "SampleAfterValue": "4000", + "BriefDescription": "Load instructions retired IO (Precise Event)" + }, + { + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "OFFCORE_REQUESTS.ANY", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore requests" + }, + { + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "OFFCORE_REQUESTS.ANY.READ", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore read requests" + }, + { + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "OFFCORE_REQUESTS.ANY.RFO", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests" + }, + { + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code read requests" + }, + { + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data read requests" + }, + { + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "OFFCORE_REQUESTS.DEMAND.RFO", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests" + }, + { + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore L1 data cache writebacks" + }, + { + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "OFFCORE_REQUESTS.UNCACHED_MEM", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore uncached memory accesses" + }, + { + "EventCode": "0x60", + "UMask": "0x8", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ", + "SampleAfterValue": "2000000", + "BriefDescription": "Outstanding offcore reads" + }, + { + "EventCode": "0x60", + "UMask": "0x8", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles offcore reads busy", + "CounterMask": "1" + }, + { + "EventCode": "0x60", + "UMask": "0x2", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE", + "SampleAfterValue": "2000000", + "BriefDescription": "Outstanding offcore demand code reads" + }, + { + "EventCode": "0x60", + "UMask": "0x2", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles offcore demand code read busy", + "CounterMask": "1" + }, + { + "EventCode": "0x60", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA", + "SampleAfterValue": "2000000", + "BriefDescription": "Outstanding offcore demand data reads" + }, + { + "EventCode": "0x60", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles offcore demand data read busy", + "CounterMask": "1" + }, + { + "EventCode": "0x60", + "UMask": "0x4", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO", + "SampleAfterValue": "2000000", + "BriefDescription": "Outstanding offcore demand RFOs" + }, + { + "EventCode": "0x60", + "UMask": "0x4", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles offcore demand RFOs busy", + "CounterMask": "1" + }, + { + "EventCode": "0xB2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS_SQ_FULL", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests blocked due to Super Queue full" + }, + { + "EventCode": "0xF4", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "SQ_MISC.LRU_HINTS", + "SampleAfterValue": "2000000", + "BriefDescription": "Super Queue LRU hints sent to LLC" + }, + { + "EventCode": "0xF4", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "SQ_MISC.SPLIT_LOCK", + "SampleAfterValue": "2000000", + "BriefDescription": "Super Queue lock splits across a cache line" + }, + { + "EventCode": "0x6", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "STORE_BLOCKS.AT_RET", + "SampleAfterValue": "200000", + "BriefDescription": "Loads delayed with at-Retirement block code" + }, + { + "EventCode": "0x6", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "STORE_BLOCKS.L1D_BLOCK", + "SampleAfterValue": "200000", + "BriefDescription": "Cacheable loads delayed with L1D block code" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x0", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", + "MSRIndex": "0x3F6", + "SampleAfterValue": "2000000", + "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x400", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", + "MSRIndex": "0x3F6", + "SampleAfterValue": "100", + "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x80", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", + "MSRIndex": "0x3F6", + "SampleAfterValue": "1000", + "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x10", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", + "MSRIndex": "0x3F6", + "SampleAfterValue": "10000", + "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x4000", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", + "MSRIndex": "0x3F6", + "SampleAfterValue": "5", + "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x800", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", + "MSRIndex": "0x3F6", + "SampleAfterValue": "50", + "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x100", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", + "MSRIndex": "0x3F6", + "SampleAfterValue": "500", + "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x20", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", + "MSRIndex": "0x3F6", + "SampleAfterValue": "5000", + "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x8000", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", + "MSRIndex": "0x3F6", + "SampleAfterValue": "3", + "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x4", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", + "MSRIndex": "0x3F6", + "SampleAfterValue": "50000", + "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x1000", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", + "MSRIndex": "0x3F6", + "SampleAfterValue": "20", + "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x200", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", + "MSRIndex": "0x3F6", + "SampleAfterValue": "200", + "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x40", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", + "MSRIndex": "0x3F6", + "SampleAfterValue": "2000", + "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x8", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", + "MSRIndex": "0x3F6", + "SampleAfterValue": "20000", + "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x2000", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", + "MSRIndex": "0x3F6", + "SampleAfterValue": "10", + "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x7F11", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by any cache or DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xFF11", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore data reads", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x8011", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x111", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x211", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x411", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x711", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2711", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1811", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x5811", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1011", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x811", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x7F44", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by any cache or DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xFF44", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore code reads", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x8044", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x144", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x244", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x444", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x744", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2744", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1844", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x5844", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1044", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x844", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x7FFF", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by any cache or DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xFFFF", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore requests", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x80FF", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1FF", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2FF", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4FF", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x7FF", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x27FF", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x18FF", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x58FF", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10FF", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x8FF", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x7F22", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xFF22", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore RFO requests", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x8022", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x122", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x222", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x422", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x722", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2722", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1822", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x5822", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1022", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x822", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x7F08", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to any cache or DRAM.", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xFF08", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore writebacks", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x8008", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x108", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x408", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x708", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2708", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1808", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x5808", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1008", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x808", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x7F77", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xFF77", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore code or data read requests", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x8077", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x177", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x277", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x477", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x777", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2777", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1877", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x5877", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1077", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x877", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x7F33", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore request = all data, response = any cache_dram", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xFF33", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore request = all data, response = any location", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x8033", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x133", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x233", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x433", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x733", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore request = all data, response = local cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2733", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore request = all data, response = local cache or dram", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1833", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore request = all data, response = remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x5833", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore request = all data, response = remote cache or dram", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1033", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads, RFO's and prefetches that HIT in a remote cache ", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x833", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads, RFO's and prefetches that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x7F03", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xFF03", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore demand data requests", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x8003", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x103", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x203", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x403", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x703", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2703", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1803", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x5803", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x803", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x7F01", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xFF01", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore demand data reads", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x8001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x101", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x201", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x401", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x701", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2701", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1801", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x5801", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x801", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x7F04", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xFF04", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore demand code reads", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x8004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x104", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x204", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x404", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x704", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2704", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1804", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x5804", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x804", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x7F02", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xFF02", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore demand RFO requests", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x8002", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x102", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x202", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x402", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x702", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2702", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1802", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x5802", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1002", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x802", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x7F80", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xFF80", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore other requests", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x8080", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x180", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x280", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x480", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x780", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2780", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1880", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x5880", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1080", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x880", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x7F50", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xFF50", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore prefetch data requests", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x8050", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x150", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x250", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x450", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x750", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2750", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1850", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x5850", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1050", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x850", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x7F10", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xFF10", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore prefetch data reads", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x8010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x110", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x210", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x410", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x710", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2710", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1810", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x5810", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x810", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x7F40", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xFF40", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore prefetch code reads", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x8040", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x140", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x240", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x440", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x740", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2740", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1840", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x5840", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1040", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x840", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x7F20", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xFF20", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore prefetch RFO requests", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x8020", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x120", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x220", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x420", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x720", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2720", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1820", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x5820", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1020", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x820", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x7F70", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xFF70", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore prefetch requests", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x8070", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x170", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x270", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x470", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x770", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2770", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1870", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x5870", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1070", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x870", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests that HITM in a remote cache", + "Offcore": "1" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/floating-point.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/floating-point.json new file mode 100644 index 000000000000..7d2f71a9dee3 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/floating-point.json @@ -0,0 +1,229 @@ +[ + { + "PEBS": "1", + "EventCode": "0xF7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "FP_ASSIST.ALL", + "SampleAfterValue": "20000", + "BriefDescription": "X87 Floating point assists (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xF7", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "FP_ASSIST.INPUT", + "SampleAfterValue": "20000", + "BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xF7", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "FP_ASSIST.OUTPUT", + "SampleAfterValue": "20000", + "BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "FP_COMP_OPS_EXE.MMX", + "SampleAfterValue": "2000000", + "BriefDescription": "MMX Uops" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION", + "SampleAfterValue": "2000000", + "BriefDescription": "SSE* FP double precision Uops" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "FP_COMP_OPS_EXE.SSE_FP", + "SampleAfterValue": "2000000", + "BriefDescription": "SSE and SSE2 FP Uops" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED", + "SampleAfterValue": "2000000", + "BriefDescription": "SSE FP packed Uops" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR", + "SampleAfterValue": "2000000", + "BriefDescription": "SSE FP scalar Uops" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION", + "SampleAfterValue": "2000000", + "BriefDescription": "SSE* FP single precision Uops" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER", + "SampleAfterValue": "2000000", + "BriefDescription": "SSE2 integer Uops" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "FP_COMP_OPS_EXE.X87", + "SampleAfterValue": "2000000", + "BriefDescription": "Computational floating-point operations executed" + }, + { + "EventCode": "0xCC", + "Counter": "0,1,2,3", + "UMask": "0x3", + "EventName": "FP_MMX_TRANS.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "All Floating Point to and from MMX transitions" + }, + { + "EventCode": "0xCC", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "FP_MMX_TRANS.TO_FP", + "SampleAfterValue": "2000000", + "BriefDescription": "Transitions from MMX to Floating Point instructions" + }, + { + "EventCode": "0xCC", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "FP_MMX_TRANS.TO_MMX", + "SampleAfterValue": "2000000", + "BriefDescription": "Transitions from Floating Point to MMX instructions" + }, + { + "EventCode": "0x12", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "SIMD_INT_128.PACK", + "SampleAfterValue": "200000", + "BriefDescription": "128 bit SIMD integer pack operations" + }, + { + "EventCode": "0x12", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "SIMD_INT_128.PACKED_ARITH", + "SampleAfterValue": "200000", + "BriefDescription": "128 bit SIMD integer arithmetic operations" + }, + { + "EventCode": "0x12", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "SIMD_INT_128.PACKED_LOGICAL", + "SampleAfterValue": "200000", + "BriefDescription": "128 bit SIMD integer logical operations" + }, + { + "EventCode": "0x12", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "SIMD_INT_128.PACKED_MPY", + "SampleAfterValue": "200000", + "BriefDescription": "128 bit SIMD integer multiply operations" + }, + { + "EventCode": "0x12", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "SIMD_INT_128.PACKED_SHIFT", + "SampleAfterValue": "200000", + "BriefDescription": "128 bit SIMD integer shift operations" + }, + { + "EventCode": "0x12", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "SIMD_INT_128.SHUFFLE_MOVE", + "SampleAfterValue": "200000", + "BriefDescription": "128 bit SIMD integer shuffle/move operations" + }, + { + "EventCode": "0x12", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "SIMD_INT_128.UNPACK", + "SampleAfterValue": "200000", + "BriefDescription": "128 bit SIMD integer unpack operations" + }, + { + "EventCode": "0xFD", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "SIMD_INT_64.PACK", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD integer 64 bit pack operations" + }, + { + "EventCode": "0xFD", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "SIMD_INT_64.PACKED_ARITH", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD integer 64 bit arithmetic operations" + }, + { + "EventCode": "0xFD", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "SIMD_INT_64.PACKED_LOGICAL", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD integer 64 bit logical operations" + }, + { + "EventCode": "0xFD", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "SIMD_INT_64.PACKED_MPY", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD integer 64 bit packed multiply operations" + }, + { + "EventCode": "0xFD", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "SIMD_INT_64.PACKED_SHIFT", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD integer 64 bit shift operations" + }, + { + "EventCode": "0xFD", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "SIMD_INT_64.SHUFFLE_MOVE", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD integer 64 bit shuffle/move operations" + }, + { + "EventCode": "0xFD", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "SIMD_INT_64.UNPACK", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD integer 64 bit unpack operations" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/frontend.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/frontend.json new file mode 100644 index 000000000000..e5e21e03444d --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/frontend.json @@ -0,0 +1,26 @@ +[ + { + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MACRO_INSTS.DECODED", + "SampleAfterValue": "2000000", + "BriefDescription": "Instructions decoded" + }, + { + "EventCode": "0xA6", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MACRO_INSTS.FUSIONS_DECODED", + "SampleAfterValue": "2000000", + "BriefDescription": "Macro-fused instructions decoded" + }, + { + "EventCode": "0x19", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "TWO_UOP_INSTS_DECODED", + "SampleAfterValue": "2000000", + "BriefDescription": "Two Uop instructions decoded" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/memory.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/memory.json new file mode 100644 index 000000000000..90eb6aac357b --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/memory.json @@ -0,0 +1,739 @@ +[ + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x6011", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xF811", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2011", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4011", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x6044", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xF844", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2044", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4044", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x60FF", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xF8FF", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x20FF", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x40FF", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x6022", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xF822", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2022", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4022", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x6008", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xF808", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2008", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4008", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x6077", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xF877", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2077", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4077", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x6033", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore request = all data, response = any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xF833", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore request = all data, response = any LLC miss", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2033", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the local DRAM.", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4033", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x6003", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xF803", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2003", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4003", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x6001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xF801", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x6004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xF804", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x6002", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xF802", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2002", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4002", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x6080", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xF880", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4080", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x6050", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xF850", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2050", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4050", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x6010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xF810", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4010", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x6040", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xF840", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2040", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4040", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x6020", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xF820", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2020", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4020", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x6070", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0xF870", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x2070", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4070", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by a remote DRAM", + "Offcore": "1" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/other.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/other.json new file mode 100644 index 000000000000..85133d6a5ce0 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/other.json @@ -0,0 +1,287 @@ +[ + { + "EventCode": "0xE8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BPU_CLEARS.EARLY", + "SampleAfterValue": "2000000", + "BriefDescription": "Early Branch Prediciton Unit clears" + }, + { + "EventCode": "0xE8", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "BPU_CLEARS.LATE", + "SampleAfterValue": "2000000", + "BriefDescription": "Late Branch Prediction Unit clears" + }, + { + "EventCode": "0xE5", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BPU_MISSED_CALL_RET", + "SampleAfterValue": "2000000", + "BriefDescription": "Branch prediction unit missed call or return" + }, + { + "EventCode": "0xD5", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ES_REG_RENAMES", + "SampleAfterValue": "2000000", + "BriefDescription": "ES segment renames" + }, + { + "EventCode": "0x6C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IO_TRANSACTIONS", + "SampleAfterValue": "2000000", + "BriefDescription": "I/O transactions" + }, + { + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L1I.CYCLES_STALLED", + "SampleAfterValue": "2000000", + "BriefDescription": "L1I instruction fetch stall cycles" + }, + { + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L1I.HITS", + "SampleAfterValue": "2000000", + "BriefDescription": "L1I instruction fetch hits" + }, + { + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L1I.MISSES", + "SampleAfterValue": "2000000", + "BriefDescription": "L1I instruction fetch misses" + }, + { + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x3", + "EventName": "L1I.READS", + "SampleAfterValue": "2000000", + "BriefDescription": "L1I Instruction fetches" + }, + { + "EventCode": "0x82", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LARGE_ITLB.HIT", + "SampleAfterValue": "200000", + "BriefDescription": "Large ITLB hit" + }, + { + "EventCode": "0x3", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "LOAD_BLOCK.OVERLAP_STORE", + "SampleAfterValue": "200000", + "BriefDescription": "Loads that partially overlap an earlier store" + }, + { + "EventCode": "0x13", + "Counter": "0,1,2,3", + "UMask": "0x7", + "EventName": "LOAD_DISPATCH.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "All loads dispatched" + }, + { + "EventCode": "0x13", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "LOAD_DISPATCH.MOB", + "SampleAfterValue": "2000000", + "BriefDescription": "Loads dispatched from the MOB" + }, + { + "EventCode": "0x13", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LOAD_DISPATCH.RS", + "SampleAfterValue": "2000000", + "BriefDescription": "Loads dispatched that bypass the MOB" + }, + { + "EventCode": "0x13", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "LOAD_DISPATCH.RS_DELAYED", + "SampleAfterValue": "2000000", + "BriefDescription": "Loads dispatched from stage 305" + }, + { + "EventCode": "0x7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "PARTIAL_ADDRESS_ALIAS", + "SampleAfterValue": "200000", + "BriefDescription": "False dependencies due to partial address aliasing" + }, + { + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "RAT_STALLS.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "All RAT stall cycles" + }, + { + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "RAT_STALLS.FLAGS", + "SampleAfterValue": "2000000", + "BriefDescription": "Flag stall cycles" + }, + { + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "RAT_STALLS.REGISTERS", + "SampleAfterValue": "2000000", + "BriefDescription": "Partial register stall cycles" + }, + { + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "RAT_STALLS.ROB_READ_PORT", + "SampleAfterValue": "2000000", + "BriefDescription": "ROB read port stalls cycles" + }, + { + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "RAT_STALLS.SCOREBOARD", + "SampleAfterValue": "2000000", + "BriefDescription": "Scoreboard stall cycles" + }, + { + "EventCode": "0x4", + "Counter": "0,1,2,3", + "UMask": "0x7", + "EventName": "SB_DRAIN.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "All Store buffer stall cycles" + }, + { + "EventCode": "0xD4", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "SEG_RENAME_STALLS", + "SampleAfterValue": "2000000", + "BriefDescription": "Segment rename stall cycles" + }, + { + "EventCode": "0xB8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "SNOOP_RESPONSE.HIT", + "SampleAfterValue": "100000", + "BriefDescription": "Thread responded HIT to snoop" + }, + { + "EventCode": "0xB8", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "SNOOP_RESPONSE.HITE", + "SampleAfterValue": "100000", + "BriefDescription": "Thread responded HITE to snoop" + }, + { + "EventCode": "0xB8", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "SNOOP_RESPONSE.HITM", + "SampleAfterValue": "100000", + "BriefDescription": "Thread responded HITM to snoop" + }, + { + "EventCode": "0xB4", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "SNOOPQ_REQUESTS.CODE", + "SampleAfterValue": "100000", + "BriefDescription": "Snoop code requests" + }, + { + "EventCode": "0xB4", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "SNOOPQ_REQUESTS.DATA", + "SampleAfterValue": "100000", + "BriefDescription": "Snoop data requests" + }, + { + "EventCode": "0xB4", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "SNOOPQ_REQUESTS.INVALIDATE", + "SampleAfterValue": "100000", + "BriefDescription": "Snoop invalidate requests" + }, + { + "EventCode": "0xB3", + "UMask": "0x4", + "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE", + "SampleAfterValue": "2000000", + "BriefDescription": "Outstanding snoop code requests" + }, + { + "EventCode": "0xB3", + "UMask": "0x4", + "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE_NOT_EMPTY", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles snoop code requests queued", + "CounterMask": "1" + }, + { + "EventCode": "0xB3", + "UMask": "0x1", + "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA", + "SampleAfterValue": "2000000", + "BriefDescription": "Outstanding snoop data requests" + }, + { + "EventCode": "0xB3", + "UMask": "0x1", + "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA_NOT_EMPTY", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles snoop data requests queued", + "CounterMask": "1" + }, + { + "EventCode": "0xB3", + "UMask": "0x2", + "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE", + "SampleAfterValue": "2000000", + "BriefDescription": "Outstanding snoop invalidate requests" + }, + { + "EventCode": "0xB3", + "UMask": "0x2", + "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE_NOT_EMPTY", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles snoop invalidate requests queued", + "CounterMask": "1" + }, + { + "EventCode": "0xF6", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "SQ_FULL_STALL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Super Queue full stall cycles" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/pipeline.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/pipeline.json new file mode 100644 index 000000000000..f130510f7616 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/pipeline.json @@ -0,0 +1,899 @@ +[ + { + "EventCode": "0x14", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ARITH.CYCLES_DIV_BUSY", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles the divider is busy" + }, + { + "EventCode": "0x14", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ARITH.DIV", + "SampleAfterValue": "2000000", + "BriefDescription": "Divide Operations executed", + "CounterMask": "1", + "EdgeDetect": "1" + }, + { + "EventCode": "0x14", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "ARITH.MUL", + "SampleAfterValue": "2000000", + "BriefDescription": "Multiply operations executed" + }, + { + "EventCode": "0xE6", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "BACLEAR.BAD_TARGET", + "SampleAfterValue": "2000000", + "BriefDescription": "BACLEAR asserted with bad target address" + }, + { + "EventCode": "0xE6", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BACLEAR.CLEAR", + "SampleAfterValue": "2000000", + "BriefDescription": "BACLEAR asserted, regardless of cause " + }, + { + "EventCode": "0xA7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BACLEAR_FORCE_IQ", + "SampleAfterValue": "2000000", + "BriefDescription": "Instruction queue forced BACLEAR" + }, + { + "EventCode": "0xE0", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BR_INST_DECODED", + "SampleAfterValue": "2000000", + "BriefDescription": "Branch instructions decoded" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x7f", + "EventName": "BR_INST_EXEC.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "Branch instructions executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BR_INST_EXEC.COND", + "SampleAfterValue": "200000", + "BriefDescription": "Conditional branch instructions executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "BR_INST_EXEC.DIRECT", + "SampleAfterValue": "200000", + "BriefDescription": "Unconditional branches executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL", + "SampleAfterValue": "20000", + "BriefDescription": "Unconditional call branches executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL", + "SampleAfterValue": "20000", + "BriefDescription": "Indirect call branches executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL", + "SampleAfterValue": "20000", + "BriefDescription": "Indirect non call branches executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "BR_INST_EXEC.NEAR_CALLS", + "SampleAfterValue": "20000", + "BriefDescription": "Call branches executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x7", + "EventName": "BR_INST_EXEC.NON_CALLS", + "SampleAfterValue": "200000", + "BriefDescription": "All non call branches executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "BR_INST_EXEC.RETURN_NEAR", + "SampleAfterValue": "20000", + "BriefDescription": "Indirect return branches executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "BR_INST_EXEC.TAKEN", + "SampleAfterValue": "200000", + "BriefDescription": "Taken branches executed" + }, + { + "PEBS": "1", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "SampleAfterValue": "200000", + "BriefDescription": "Retired branch instructions (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BR_INST_RETIRED.CONDITIONAL", + "SampleAfterValue": "200000", + "BriefDescription": "Retired conditional branch instructions (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "SampleAfterValue": "20000", + "BriefDescription": "Retired near call instructions (Precise Event)" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x7f", + "EventName": "BR_MISP_EXEC.ANY", + "SampleAfterValue": "20000", + "BriefDescription": "Mispredicted branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BR_MISP_EXEC.COND", + "SampleAfterValue": "20000", + "BriefDescription": "Mispredicted conditional branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "BR_MISP_EXEC.DIRECT", + "SampleAfterValue": "20000", + "BriefDescription": "Mispredicted unconditional branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL", + "SampleAfterValue": "2000", + "BriefDescription": "Mispredicted non call branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL", + "SampleAfterValue": "2000", + "BriefDescription": "Mispredicted indirect call branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL", + "SampleAfterValue": "2000", + "BriefDescription": "Mispredicted indirect non call branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "BR_MISP_EXEC.NEAR_CALLS", + "SampleAfterValue": "2000", + "BriefDescription": "Mispredicted call branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x7", + "EventName": "BR_MISP_EXEC.NON_CALLS", + "SampleAfterValue": "20000", + "BriefDescription": "Mispredicted non call branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "BR_MISP_EXEC.RETURN_NEAR", + "SampleAfterValue": "2000", + "BriefDescription": "Mispredicted return branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "BR_MISP_EXEC.TAKEN", + "SampleAfterValue": "20000", + "BriefDescription": "Mispredicted taken branches executed" + }, + { + "PEBS": "1", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "SampleAfterValue": "20000", + "BriefDescription": "Mispredicted retired branch instructions (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BR_MISP_RETIRED.CONDITIONAL", + "SampleAfterValue": "20000", + "BriefDescription": "Mispredicted conditional retired branches (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "BR_MISP_RETIRED.NEAR_CALL", + "SampleAfterValue": "2000", + "BriefDescription": "Mispredicted near retired calls (Precise Event)" + }, + { + "EventCode": "0x0", + "Counter": "Fixed counter 3", + "UMask": "0x0", + "EventName": "CPU_CLK_UNHALTED.REF", + "SampleAfterValue": "2000000", + "BriefDescription": "Reference cycles when thread is not halted (fixed counter)" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CPU_CLK_UNHALTED.REF_P", + "SampleAfterValue": "100000", + "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)" + }, + { + "EventCode": "0x0", + "Counter": "Fixed counter 2", + "UMask": "0x0", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles when thread is not halted (fixed counter)" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles when thread is not halted (programmable counter)" + }, + { + "EventCode": "0x3C", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Total CPU cycles", + "CounterMask": "2" + }, + { + "EventCode": "0x87", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "ILD_STALL.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "Any Instruction Length Decoder stall cycles" + }, + { + "EventCode": "0x87", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "ILD_STALL.IQ_FULL", + "SampleAfterValue": "2000000", + "BriefDescription": "Instruction Queue full stall cycles" + }, + { + "EventCode": "0x87", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ILD_STALL.LCP", + "SampleAfterValue": "2000000", + "BriefDescription": "Length Change Prefix stall cycles" + }, + { + "EventCode": "0x87", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "ILD_STALL.MRU", + "SampleAfterValue": "2000000", + "BriefDescription": "Stall cycles due to BPU MRU bypass" + }, + { + "EventCode": "0x87", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "ILD_STALL.REGEN", + "SampleAfterValue": "2000000", + "BriefDescription": "Regen stall cycles" + }, + { + "EventCode": "0x18", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "INST_DECODED.DEC0", + "SampleAfterValue": "2000000", + "BriefDescription": "Instructions that must be decoded by decoder 0" + }, + { + "EventCode": "0x1E", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "INST_QUEUE_WRITE_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles instructions are written to the instruction queue" + }, + { + "EventCode": "0x17", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "INST_QUEUE_WRITES", + "SampleAfterValue": "2000000", + "BriefDescription": "Instructions written to instruction queue." + }, + { + "EventCode": "0x0", + "Counter": "Fixed counter 1", + "UMask": "0x0", + "EventName": "INST_RETIRED.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "Instructions retired (fixed counter)" + }, + { + "PEBS": "1", + "EventCode": "0xC0", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "INST_RETIRED.ANY_P", + "SampleAfterValue": "2000000", + "BriefDescription": "Instructions retired (Programmable counter and Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC0", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "INST_RETIRED.MMX", + "SampleAfterValue": "2000000", + "BriefDescription": "Retired MMX instructions (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC0", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "INST_RETIRED.TOTAL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Total cycles (Precise Event)", + "CounterMask": "16" + }, + { + "PEBS": "1", + "EventCode": "0xC0", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "INST_RETIRED.X87", + "SampleAfterValue": "2000000", + "BriefDescription": "Retired floating-point operations (Precise Event)" + }, + { + "EventCode": "0x4C", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "LOAD_HIT_PRE", + "SampleAfterValue": "200000", + "BriefDescription": "Load operations conflicting with software prefetches" + }, + { + "EventCode": "0xA8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LSD.ACTIVE", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles when uops were delivered by the LSD", + "CounterMask": "1" + }, + { + "EventCode": "0xA8", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LSD.INACTIVE", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles no uops were delivered by the LSD", + "CounterMask": "1" + }, + { + "EventCode": "0x20", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LSD_OVERFLOW", + "SampleAfterValue": "2000000", + "BriefDescription": "Loops that can't stream from the instruction queue" + }, + { + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MACHINE_CLEARS.CYCLES", + "SampleAfterValue": "20000", + "BriefDescription": "Cycles machine clear asserted" + }, + { + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MACHINE_CLEARS.MEM_ORDER", + "SampleAfterValue": "20000", + "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts" + }, + { + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "MACHINE_CLEARS.SMC", + "SampleAfterValue": "20000", + "BriefDescription": "Self-Modifying Code detected" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "RESOURCE_STALLS.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "Resource related stall cycles" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "RESOURCE_STALLS.FPCW", + "SampleAfterValue": "2000000", + "BriefDescription": "FPU control word write stall cycles" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "RESOURCE_STALLS.LOAD", + "SampleAfterValue": "2000000", + "BriefDescription": "Load buffer stall cycles" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "RESOURCE_STALLS.MXCSR", + "SampleAfterValue": "2000000", + "BriefDescription": "MXCSR rename stall cycles" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "RESOURCE_STALLS.OTHER", + "SampleAfterValue": "2000000", + "BriefDescription": "Other Resource related stall cycles" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "RESOURCE_STALLS.ROB_FULL", + "SampleAfterValue": "2000000", + "BriefDescription": "ROB full stall cycles" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "RESOURCE_STALLS.RS_FULL", + "SampleAfterValue": "2000000", + "BriefDescription": "Reservation Station full stall cycles" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "RESOURCE_STALLS.STORE", + "SampleAfterValue": "2000000", + "BriefDescription": "Store buffer stall cycles" + }, + { + "PEBS": "1", + "EventCode": "0xC7", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC7", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC7", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC7", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)" + }, + { + "EventCode": "0xDB", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOP_UNFUSION", + "SampleAfterValue": "2000000", + "BriefDescription": "Uop unfusions due to FP exceptions" + }, + { + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "UOPS_DECODED.ESP_FOLDING", + "SampleAfterValue": "2000000", + "BriefDescription": "Stack pointer instructions decoded" + }, + { + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "UOPS_DECODED.ESP_SYNC", + "SampleAfterValue": "2000000", + "BriefDescription": "Stack pointer sync operations" + }, + { + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops decoded by Microcode Sequencer", + "CounterMask": "1" + }, + { + "EventCode": "0xD1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_DECODED.STALL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles no Uops are decoded", + "CounterMask": "1" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x3f", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles Uops executed on any port (core count)", + "CounterMask": "1" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x1f", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)", + "CounterMask": "1" + }, + { + "EventCode": "0xB1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x3f", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops executed on any port (core count)", + "CounterMask": "1", + "EdgeDetect": "1" + }, + { + "EventCode": "0xB1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1f", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops executed on ports 0-4 (core count)", + "CounterMask": "1", + "EdgeDetect": "1" + }, + { + "EventCode": "0xB1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x3f", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles no Uops issued on any port (core count)", + "CounterMask": "1" + }, + { + "EventCode": "0xB1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1f", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)", + "CounterMask": "1" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_EXECUTED.PORT0", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops executed on port 0" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "UOPS_EXECUTED.PORT015", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops issued on ports 0, 1 or 5" + }, + { + "EventCode": "0xB1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5", + "CounterMask": "1" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.PORT1", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops executed on port 1" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x4", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.PORT2_CORE", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops executed on port 2 (core count)" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x80", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.PORT234_CORE", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops issued on ports 2, 3 or 4" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x8", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.PORT3_CORE", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops executed on port 3 (core count)" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x10", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.PORT4_CORE", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops executed on port 4 (core count)" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "UOPS_EXECUTED.PORT5", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops executed on port 5" + }, + { + "EventCode": "0xE", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_ISSUED.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops issued" + }, + { + "EventCode": "0xE", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles no Uops were issued on any thread", + "CounterMask": "1" + }, + { + "EventCode": "0xE", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles Uops were issued on either thread", + "CounterMask": "1" + }, + { + "EventCode": "0xE", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_ISSUED.FUSED", + "SampleAfterValue": "2000000", + "BriefDescription": "Fused Uops issued" + }, + { + "EventCode": "0xE", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles no Uops were issued", + "CounterMask": "1" + }, + { + "PEBS": "1", + "EventCode": "0xC2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.ACTIVE_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles Uops are being retired", + "CounterMask": "1" + }, + { + "PEBS": "1", + "EventCode": "0xC2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops retired (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "UOPS_RETIRED.MACRO_FUSED", + "SampleAfterValue": "2000000", + "BriefDescription": "Macro-fused Uops retired (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "SampleAfterValue": "2000000", + "BriefDescription": "Retirement slots used (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC2", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles Uops are not retiring (Precise Event)", + "CounterMask": "1" + }, + { + "PEBS": "1", + "EventCode": "0xC2", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Total cycles using precise uop retired event (Precise Event)", + "CounterMask": "16" + }, + { + "PEBS": "2", + "EventCode": "0xC0", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "INST_RETIRED.TOTAL_CYCLES_PS", + "SampleAfterValue": "2000000", + "BriefDescription": "Total cycles (Precise Event)", + "CounterMask": "16" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/virtual-memory.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/virtual-memory.json new file mode 100644 index 000000000000..2153b3f5d7b0 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/virtual-memory.json @@ -0,0 +1,149 @@ +[ + { + "EventCode": "0x8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "DTLB_LOAD_MISSES.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB load misses" + }, + { + "EventCode": "0x8", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "DTLB_LOAD_MISSES.PDE_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB load miss caused by low part of address" + }, + { + "EventCode": "0x8", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "SampleAfterValue": "2000000", + "BriefDescription": "DTLB second level hit" + }, + { + "EventCode": "0x8", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB load miss page walks complete" + }, + { + "EventCode": "0x8", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "DTLB_LOAD_MISSES.WALK_CYCLES", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB load miss page walk cycles" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "DTLB_MISSES.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB misses" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB miss large page walks" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "DTLB_MISSES.STLB_HIT", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB first level misses but second level hit" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "DTLB_MISSES.WALK_COMPLETED", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB miss page walks" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "DTLB_MISSES.WALK_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "DTLB miss page walk cycles" + }, + { + "EventCode": "0x4F", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "EPT.WALK_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Extended Page Table walk cycles" + }, + { + "EventCode": "0xAE", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ITLB_FLUSH", + "SampleAfterValue": "2000000", + "BriefDescription": "ITLB flushes" + }, + { + "PEBS": "1", + "EventCode": "0xC8", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "ITLB_MISS_RETIRED", + "SampleAfterValue": "200000", + "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)" + }, + { + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ITLB_MISSES.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "ITLB miss" + }, + { + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "SampleAfterValue": "200000", + "BriefDescription": "ITLB miss page walks" + }, + { + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "ITLB_MISSES.WALK_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "ITLB miss page walk cycles" + }, + { + "PEBS": "1", + "EventCode": "0xCB", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "MEM_LOAD_RETIRED.DTLB_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "Retired loads that miss the DTLB (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_STORE_RETIRED.DTLB_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "Retired stores that miss the DTLB (Precise Event)" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereex/cache.json b/tools/perf/pmu-events/arch/x86/westmereex/cache.json new file mode 100644 index 000000000000..f9bc7fdd48d6 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/westmereex/cache.json @@ -0,0 +1,3225 @@ +[ + { + "EventCode": "0x63", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "CACHE_LOCK_CYCLES.L1D", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles L1D locked" + }, + { + "EventCode": "0x63", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "CACHE_LOCK_CYCLES.L1D_L2", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles L1D and L2 locked" + }, + { + "EventCode": "0x51", + "Counter": "0,1", + "UMask": "0x4", + "EventName": "L1D.M_EVICT", + "SampleAfterValue": "2000000", + "BriefDescription": "L1D cache lines replaced in M state" + }, + { + "EventCode": "0x51", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "L1D.M_REPL", + "SampleAfterValue": "2000000", + "BriefDescription": "L1D cache lines allocated in the M state" + }, + { + "EventCode": "0x51", + "Counter": "0,1", + "UMask": "0x8", + "EventName": "L1D.M_SNOOP_EVICT", + "SampleAfterValue": "2000000", + "BriefDescription": "L1D snoop eviction of cache lines in M state" + }, + { + "EventCode": "0x51", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "L1D.REPL", + "SampleAfterValue": "2000000", + "BriefDescription": "L1 data cache lines allocated" + }, + { + "EventCode": "0x52", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT", + "SampleAfterValue": "2000000", + "BriefDescription": "L1D prefetch load lock accepted in fill buffer" + }, + { + "EventCode": "0x4E", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "L1D_PREFETCH.MISS", + "SampleAfterValue": "200000", + "BriefDescription": "L1D hardware prefetch misses" + }, + { + "EventCode": "0x4E", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "L1D_PREFETCH.REQUESTS", + "SampleAfterValue": "200000", + "BriefDescription": "L1D hardware prefetch requests" + }, + { + "EventCode": "0x4E", + "Counter": "0,1", + "UMask": "0x4", + "EventName": "L1D_PREFETCH.TRIGGERS", + "SampleAfterValue": "200000", + "BriefDescription": "L1D hardware prefetch requests triggered" + }, + { + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L1D_WB_L2.E_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L1 writebacks to L2 in E state" + }, + { + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L1D_WB_L2.I_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L1 writebacks to L2 in I state (misses)" + }, + { + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L1D_WB_L2.M_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L1 writebacks to L2 in M state" + }, + { + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "L1D_WB_L2.MESI", + "SampleAfterValue": "100000", + "BriefDescription": "All L1 writebacks to L2" + }, + { + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L1D_WB_L2.S_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L1 writebacks to L2 in S state" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0xff", + "EventName": "L2_DATA_RQSTS.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "All L2 data requests" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data demand loads in E state" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data demand loads in I state (misses)" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data demand loads in M state" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "L2_DATA_RQSTS.DEMAND.MESI", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data demand requests" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data demand loads in S state" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data prefetches in E state" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data prefetches in the I state (misses)" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data prefetches in M state" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0xf0", + "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", + "SampleAfterValue": "200000", + "BriefDescription": "All L2 data prefetches" + }, + { + "EventCode": "0x26", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE", + "SampleAfterValue": "200000", + "BriefDescription": "L2 data prefetches in the S state" + }, + { + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x7", + "EventName": "L2_LINES_IN.ANY", + "SampleAfterValue": "100000", + "BriefDescription": "L2 lines alloacated" + }, + { + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_LINES_IN.E_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 lines allocated in the E state" + }, + { + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_LINES_IN.S_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 lines allocated in the S state" + }, + { + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "L2_LINES_OUT.ANY", + "SampleAfterValue": "100000", + "BriefDescription": "L2 lines evicted" + }, + { + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_LINES_OUT.DEMAND_CLEAN", + "SampleAfterValue": "100000", + "BriefDescription": "L2 lines evicted by a demand request" + }, + { + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_LINES_OUT.DEMAND_DIRTY", + "SampleAfterValue": "100000", + "BriefDescription": "L2 modified lines evicted by a demand request" + }, + { + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_LINES_OUT.PREFETCH_CLEAN", + "SampleAfterValue": "100000", + "BriefDescription": "L2 lines evicted by a prefetch request" + }, + { + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_LINES_OUT.PREFETCH_DIRTY", + "SampleAfterValue": "100000", + "BriefDescription": "L2 modified lines evicted by a prefetch request" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "L2_RQSTS.IFETCH_HIT", + "SampleAfterValue": "200000", + "BriefDescription": "L2 instruction fetch hits" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "L2_RQSTS.IFETCH_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "L2 instruction fetch misses" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "L2_RQSTS.IFETCHES", + "SampleAfterValue": "200000", + "BriefDescription": "L2 instruction fetches" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_RQSTS.LD_HIT", + "SampleAfterValue": "200000", + "BriefDescription": "L2 load hits" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_RQSTS.LD_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "L2 load misses" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x3", + "EventName": "L2_RQSTS.LOADS", + "SampleAfterValue": "200000", + "BriefDescription": "L2 requests" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xaa", + "EventName": "L2_RQSTS.MISS", + "SampleAfterValue": "200000", + "BriefDescription": "All L2 misses" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "L2_RQSTS.PREFETCH_HIT", + "SampleAfterValue": "200000", + "BriefDescription": "L2 prefetch hits" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "L2_RQSTS.PREFETCH_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "L2 prefetch misses" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xc0", + "EventName": "L2_RQSTS.PREFETCHES", + "SampleAfterValue": "200000", + "BriefDescription": "All L2 prefetches" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xff", + "EventName": "L2_RQSTS.REFERENCES", + "SampleAfterValue": "200000", + "BriefDescription": "All L2 requests" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_RQSTS.RFO_HIT", + "SampleAfterValue": "200000", + "BriefDescription": "L2 RFO hits" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_RQSTS.RFO_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "L2 RFO misses" + }, + { + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xc", + "EventName": "L2_RQSTS.RFOS", + "SampleAfterValue": "200000", + "BriefDescription": "L2 RFO requests" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "L2_TRANSACTIONS.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "All L2 transactions" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "L2_TRANSACTIONS.FILL", + "SampleAfterValue": "200000", + "BriefDescription": "L2 fill transactions" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_TRANSACTIONS.IFETCH", + "SampleAfterValue": "200000", + "BriefDescription": "L2 instruction fetch transactions" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "L2_TRANSACTIONS.L1D_WB", + "SampleAfterValue": "200000", + "BriefDescription": "L1D writeback to L2 transactions" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_TRANSACTIONS.LOAD", + "SampleAfterValue": "200000", + "BriefDescription": "L2 Load transactions" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_TRANSACTIONS.PREFETCH", + "SampleAfterValue": "200000", + "BriefDescription": "L2 prefetch transactions" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_TRANSACTIONS.RFO", + "SampleAfterValue": "200000", + "BriefDescription": "L2 RFO transactions" + }, + { + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "L2_TRANSACTIONS.WB", + "SampleAfterValue": "200000", + "BriefDescription": "L2 writeback to LLC transactions" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "L2_WRITE.LOCK.E_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 demand lock RFOs in E state" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0xe0", + "EventName": "L2_WRITE.LOCK.HIT", + "SampleAfterValue": "100000", + "BriefDescription": "All demand L2 lock RFOs that hit the cache" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "L2_WRITE.LOCK.I_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 demand lock RFOs in I state (misses)" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "L2_WRITE.LOCK.M_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 demand lock RFOs in M state" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0xf0", + "EventName": "L2_WRITE.LOCK.MESI", + "SampleAfterValue": "100000", + "BriefDescription": "All demand L2 lock RFOs" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "L2_WRITE.LOCK.S_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 demand lock RFOs in S state" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0xe", + "EventName": "L2_WRITE.RFO.HIT", + "SampleAfterValue": "100000", + "BriefDescription": "All L2 demand store RFOs that hit the cache" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_WRITE.RFO.I_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 demand store RFOs in I state (misses)" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_WRITE.RFO.M_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 demand store RFOs in M state" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "L2_WRITE.RFO.MESI", + "SampleAfterValue": "100000", + "BriefDescription": "All L2 demand store RFOs" + }, + { + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_WRITE.RFO.S_STATE", + "SampleAfterValue": "100000", + "BriefDescription": "L2 demand store RFOs in S state" + }, + { + "EventCode": "0x2E", + "Counter": "0,1,2,3", + "UMask": "0x41", + "EventName": "LONGEST_LAT_CACHE.MISS", + "SampleAfterValue": "100000", + "BriefDescription": "Longest latency cache miss" + }, + { + "EventCode": "0x2E", + "Counter": "0,1,2,3", + "UMask": "0x4f", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "SampleAfterValue": "200000", + "BriefDescription": "Longest latency cache reference" + }, + { + "PEBS": "1", + "EventCode": "0xB", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_INST_RETIRED.LOADS", + "SampleAfterValue": "2000000", + "BriefDescription": "Instructions retired which contains a load (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xB", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MEM_INST_RETIRED.STORES", + "SampleAfterValue": "2000000", + "BriefDescription": "Instructions retired which contains a store (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xCB", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "MEM_LOAD_RETIRED.HIT_LFB", + "SampleAfterValue": "200000", + "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xCB", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_LOAD_RETIRED.L1D_HIT", + "SampleAfterValue": "2000000", + "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xCB", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MEM_LOAD_RETIRED.L2_HIT", + "SampleAfterValue": "200000", + "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xCB", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "MEM_LOAD_RETIRED.LLC_MISS", + "SampleAfterValue": "10000", + "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xCB", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", + "SampleAfterValue": "40000", + "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xCB", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", + "SampleAfterValue": "40000", + "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xF", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MEM_UNCORE_RETIRED.LOCAL_HITM", + "SampleAfterValue": "40000", + "BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xF", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", + "SampleAfterValue": "20000", + "BriefDescription": "Load instructions retired local dram and remote cache HIT data sources (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xF", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM", + "SampleAfterValue": "10000", + "BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xF", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE", + "SampleAfterValue": "4000", + "BriefDescription": "Load instructions retired IO (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xF", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "MEM_UNCORE_RETIRED.REMOTE_HITM", + "SampleAfterValue": "40000", + "BriefDescription": "Retired loads that hit remote socket in modified state (Precise Event)" + }, + { + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "OFFCORE_REQUESTS.ANY", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore requests" + }, + { + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "OFFCORE_REQUESTS.ANY.READ", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore read requests" + }, + { + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "OFFCORE_REQUESTS.ANY.RFO", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests" + }, + { + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code read requests" + }, + { + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data read requests" + }, + { + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "OFFCORE_REQUESTS.DEMAND.RFO", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests" + }, + { + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore L1 data cache writebacks" + }, + { + "EventCode": "0x60", + "UMask": "0x8", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ", + "SampleAfterValue": "2000000", + "BriefDescription": "Outstanding offcore reads" + }, + { + "EventCode": "0x60", + "UMask": "0x8", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles offcore reads busy", + "CounterMask": "1" + }, + { + "EventCode": "0x60", + "UMask": "0x2", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE", + "SampleAfterValue": "2000000", + "BriefDescription": "Outstanding offcore demand code reads" + }, + { + "EventCode": "0x60", + "UMask": "0x2", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles offcore demand code read busy", + "CounterMask": "1" + }, + { + "EventCode": "0x60", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA", + "SampleAfterValue": "2000000", + "BriefDescription": "Outstanding offcore demand data reads" + }, + { + "EventCode": "0x60", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles offcore demand data read busy", + "CounterMask": "1" + }, + { + "EventCode": "0x60", + "UMask": "0x4", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO", + "SampleAfterValue": "2000000", + "BriefDescription": "Outstanding offcore demand RFOs" + }, + { + "EventCode": "0x60", + "UMask": "0x4", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles offcore demand RFOs busy", + "CounterMask": "1" + }, + { + "EventCode": "0xB2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS_SQ_FULL", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests blocked due to Super Queue full" + }, + { + "EventCode": "0xF4", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "SQ_MISC.LRU_HINTS", + "SampleAfterValue": "2000000", + "BriefDescription": "Super Queue LRU hints sent to LLC" + }, + { + "EventCode": "0xF4", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "SQ_MISC.SPLIT_LOCK", + "SampleAfterValue": "2000000", + "BriefDescription": "Super Queue lock splits across a cache line" + }, + { + "EventCode": "0x6", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "STORE_BLOCKS.AT_RET", + "SampleAfterValue": "200000", + "BriefDescription": "Loads delayed with at-Retirement block code" + }, + { + "EventCode": "0x6", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "STORE_BLOCKS.L1D_BLOCK", + "SampleAfterValue": "200000", + "BriefDescription": "Cacheable loads delayed with L1D block code" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x0", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", + "MSRIndex": "0x3F6", + "SampleAfterValue": "2000000", + "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x400", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", + "MSRIndex": "0x3F6", + "SampleAfterValue": "100", + "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x80", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", + "MSRIndex": "0x3F6", + "SampleAfterValue": "1000", + "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x10", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", + "MSRIndex": "0x3F6", + "SampleAfterValue": "10000", + "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x4000", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", + "MSRIndex": "0x3F6", + "SampleAfterValue": "5", + "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x800", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", + "MSRIndex": "0x3F6", + "SampleAfterValue": "50", + "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x100", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", + "MSRIndex": "0x3F6", + "SampleAfterValue": "500", + "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x20", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", + "MSRIndex": "0x3F6", + "SampleAfterValue": "5000", + "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x8000", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", + "MSRIndex": "0x3F6", + "SampleAfterValue": "3", + "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x4", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", + "MSRIndex": "0x3F6", + "SampleAfterValue": "50000", + "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x1000", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", + "MSRIndex": "0x3F6", + "SampleAfterValue": "20", + "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x200", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", + "MSRIndex": "0x3F6", + "SampleAfterValue": "200", + "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x40", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", + "MSRIndex": "0x3F6", + "SampleAfterValue": "2000", + "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x8", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", + "MSRIndex": "0x3F6", + "SampleAfterValue": "20000", + "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)" + }, + { + "PEBS": "2", + "EventCode": "0xB", + "MSRValue": "0x2000", + "Counter": "3", + "UMask": "0x10", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", + "MSRIndex": "0x3F6", + "SampleAfterValue": "10", + "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F11", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by any cache or DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF11", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore data reads", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8011", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x111", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x211", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x411", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x711", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4711", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1811", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3811", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1011", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x811", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F44", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by any cache or DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF44", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore code reads", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8044", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x144", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x244", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x444", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x744", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4744", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1844", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3844", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1044", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x844", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7FFF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by any cache or DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFFFF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore requests", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x80FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x47FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x18FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x38FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x10FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F22", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF22", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore RFO requests", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8022", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x122", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x222", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x422", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x722", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4722", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1822", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3822", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1022", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x822", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F08", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to any cache or DRAM.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF08", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore writebacks", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8008", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x108", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x408", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x708", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4708", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1808", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3808", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1008", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x808", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F77", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF77", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore code or data read requests", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8077", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x177", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x277", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x477", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x777", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4777", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1877", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3877", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1077", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x877", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F33", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore request = all data, response = any cache_dram", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF33", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore request = all data, response = any location", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8033", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x133", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x233", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x433", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x733", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore request = all data, response = local cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4733", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore request = all data, response = local cache or dram", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1833", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore request = all data, response = remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3833", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore request = all data, response = remote cache or dram", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1033", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads, RFO's and prefetches that HIT in a remote cache ", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x833", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads, RFO's and prefetches that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F03", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF03", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore demand data requests", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8003", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x103", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x203", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x403", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x703", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4703", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1803", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3803", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1003", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x803", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F01", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF01", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore demand data reads", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8001", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x101", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x201", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x401", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x701", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4701", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1801", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3801", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1001", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x801", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F04", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF04", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore demand code reads", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8004", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x104", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x204", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x404", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x704", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4704", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1804", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3804", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1004", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x804", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F02", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF02", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore demand RFO requests", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8002", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x102", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x202", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x402", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x702", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4702", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1802", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3802", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1002", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x802", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x7F80", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xFF80", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "All offcore other requests", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x8080", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x180", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x280", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x480", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x780", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4780", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1880", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3880", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by a remote cache or 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"MSRValue": "0x270", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x470", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x770", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4770", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1870", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x3870", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x1070", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests that HIT in a remote cache", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x870", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests that HITM in a remote cache", + "Offcore": "1" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereex/floating-point.json b/tools/perf/pmu-events/arch/x86/westmereex/floating-point.json new file mode 100644 index 000000000000..7d2f71a9dee3 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/westmereex/floating-point.json @@ -0,0 +1,229 @@ +[ + { + "PEBS": "1", + "EventCode": "0xF7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "FP_ASSIST.ALL", + "SampleAfterValue": "20000", + "BriefDescription": "X87 Floating point assists (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xF7", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "FP_ASSIST.INPUT", + "SampleAfterValue": "20000", + "BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xF7", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "FP_ASSIST.OUTPUT", + "SampleAfterValue": "20000", + "BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "FP_COMP_OPS_EXE.MMX", + "SampleAfterValue": "2000000", + "BriefDescription": "MMX Uops" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION", + "SampleAfterValue": "2000000", + "BriefDescription": "SSE* FP double precision Uops" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "FP_COMP_OPS_EXE.SSE_FP", + "SampleAfterValue": "2000000", + "BriefDescription": "SSE and SSE2 FP Uops" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED", + "SampleAfterValue": "2000000", + "BriefDescription": "SSE FP packed Uops" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR", + "SampleAfterValue": "2000000", + "BriefDescription": "SSE FP scalar Uops" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION", + "SampleAfterValue": "2000000", + "BriefDescription": "SSE* FP single precision Uops" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER", + "SampleAfterValue": "2000000", + "BriefDescription": "SSE2 integer Uops" + }, + { + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "FP_COMP_OPS_EXE.X87", + "SampleAfterValue": "2000000", + "BriefDescription": "Computational floating-point operations executed" + }, + { + "EventCode": "0xCC", + "Counter": "0,1,2,3", + "UMask": "0x3", + "EventName": "FP_MMX_TRANS.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "All Floating Point to and from MMX transitions" + }, + { + "EventCode": "0xCC", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "FP_MMX_TRANS.TO_FP", + "SampleAfterValue": "2000000", + "BriefDescription": "Transitions from MMX to Floating Point instructions" + }, + { + "EventCode": "0xCC", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "FP_MMX_TRANS.TO_MMX", + "SampleAfterValue": "2000000", + "BriefDescription": "Transitions from Floating Point to MMX instructions" + }, + { + "EventCode": "0x12", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "SIMD_INT_128.PACK", + "SampleAfterValue": "200000", + "BriefDescription": "128 bit SIMD integer pack operations" + }, + { + "EventCode": "0x12", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "SIMD_INT_128.PACKED_ARITH", + "SampleAfterValue": "200000", + "BriefDescription": "128 bit SIMD integer arithmetic operations" + }, + { + "EventCode": "0x12", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "SIMD_INT_128.PACKED_LOGICAL", + "SampleAfterValue": "200000", + "BriefDescription": "128 bit SIMD integer logical operations" + }, + { + "EventCode": "0x12", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "SIMD_INT_128.PACKED_MPY", + "SampleAfterValue": "200000", + "BriefDescription": "128 bit SIMD integer multiply operations" + }, + { + "EventCode": "0x12", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "SIMD_INT_128.PACKED_SHIFT", + "SampleAfterValue": "200000", + "BriefDescription": "128 bit SIMD integer shift operations" + }, + { + "EventCode": "0x12", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "SIMD_INT_128.SHUFFLE_MOVE", + "SampleAfterValue": "200000", + "BriefDescription": "128 bit SIMD integer shuffle/move operations" + }, + { + "EventCode": "0x12", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "SIMD_INT_128.UNPACK", + "SampleAfterValue": "200000", + "BriefDescription": "128 bit SIMD integer unpack operations" + }, + { + "EventCode": "0xFD", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "SIMD_INT_64.PACK", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD integer 64 bit pack operations" + }, + { + "EventCode": "0xFD", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "SIMD_INT_64.PACKED_ARITH", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD integer 64 bit arithmetic operations" + }, + { + "EventCode": "0xFD", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "SIMD_INT_64.PACKED_LOGICAL", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD integer 64 bit logical operations" + }, + { + "EventCode": "0xFD", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "SIMD_INT_64.PACKED_MPY", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD integer 64 bit packed multiply operations" + }, + { + "EventCode": "0xFD", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "SIMD_INT_64.PACKED_SHIFT", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD integer 64 bit shift operations" + }, + { + "EventCode": "0xFD", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "SIMD_INT_64.SHUFFLE_MOVE", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD integer 64 bit shuffle/move operations" + }, + { + "EventCode": "0xFD", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "SIMD_INT_64.UNPACK", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD integer 64 bit unpack operations" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereex/frontend.json b/tools/perf/pmu-events/arch/x86/westmereex/frontend.json new file mode 100644 index 000000000000..e5e21e03444d --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/westmereex/frontend.json @@ -0,0 +1,26 @@ +[ + { + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MACRO_INSTS.DECODED", + "SampleAfterValue": "2000000", + "BriefDescription": "Instructions decoded" + }, + { + "EventCode": "0xA6", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MACRO_INSTS.FUSIONS_DECODED", + "SampleAfterValue": "2000000", + "BriefDescription": "Macro-fused instructions decoded" + }, + { + "EventCode": "0x19", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "TWO_UOP_INSTS_DECODED", + "SampleAfterValue": "2000000", + "BriefDescription": "Two Uop instructions decoded" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereex/memory.json b/tools/perf/pmu-events/arch/x86/westmereex/memory.json new file mode 100644 index 000000000000..3ba555e73cbd --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/westmereex/memory.json @@ -0,0 +1,747 @@ +[ + { + "EventCode": "0x5", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MISALIGN_MEM_REF.STORE", + "SampleAfterValue": "200000", + "BriefDescription": "Misaligned store references" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6011", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF811", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4011", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2011", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6044", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF844", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4044", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2044", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code reads satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x60FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF8FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x40FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x20FF", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore requests satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6022", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF822", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4022", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2022", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore RFO requests satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6008", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF808", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4008", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2008", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore writebacks to a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6077", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF877", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4077", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2077", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore code or data read requests satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6033", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore request = all data, response = any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF833", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore request = all data, response = any LLC miss", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4033", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the local DRAM.", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2033", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6003", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF803", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4003", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2003", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data requests satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6001", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF801", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4001", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2001", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand data reads satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6004", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF804", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4004", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2004", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand code reads satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6002", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF802", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4002", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2002", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore demand RFO requests satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6080", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF880", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2080", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore other requests satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6030", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF830", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4030", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2030", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data requests satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6010", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF810", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4010", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2010", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch data reads satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6040", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF840", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4040", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2040", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch code reads satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6020", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF820", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4020", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2020", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x6070", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by any DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0xF870", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests that missed the LLC", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x4070", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by the local DRAM", + "Offcore": "1" + }, + { + "EventCode": "0xB7", + "MSRValue": "0x2070", + "Counter": "2", + "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM", + "MSRIndex": "0x1A6", + "SampleAfterValue": "100000", + "BriefDescription": "Offcore prefetch requests satisfied by a remote DRAM", + "Offcore": "1" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereex/other.json b/tools/perf/pmu-events/arch/x86/westmereex/other.json new file mode 100644 index 000000000000..85133d6a5ce0 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/westmereex/other.json @@ -0,0 +1,287 @@ +[ + { + "EventCode": "0xE8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BPU_CLEARS.EARLY", + "SampleAfterValue": "2000000", + "BriefDescription": "Early Branch Prediciton Unit clears" + }, + { + "EventCode": "0xE8", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "BPU_CLEARS.LATE", + "SampleAfterValue": "2000000", + "BriefDescription": "Late Branch Prediction Unit clears" + }, + { + "EventCode": "0xE5", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BPU_MISSED_CALL_RET", + "SampleAfterValue": "2000000", + "BriefDescription": "Branch prediction unit missed call or return" + }, + { + "EventCode": "0xD5", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ES_REG_RENAMES", + "SampleAfterValue": "2000000", + "BriefDescription": "ES segment renames" + }, + { + "EventCode": "0x6C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IO_TRANSACTIONS", + "SampleAfterValue": "2000000", + "BriefDescription": "I/O transactions" + }, + { + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L1I.CYCLES_STALLED", + "SampleAfterValue": "2000000", + "BriefDescription": "L1I instruction fetch stall cycles" + }, + { + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L1I.HITS", + "SampleAfterValue": "2000000", + "BriefDescription": "L1I instruction fetch hits" + }, + { + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L1I.MISSES", + "SampleAfterValue": "2000000", + "BriefDescription": "L1I instruction fetch misses" + }, + { + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x3", + "EventName": "L1I.READS", + "SampleAfterValue": "2000000", + "BriefDescription": "L1I Instruction fetches" + }, + { + "EventCode": "0x82", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LARGE_ITLB.HIT", + "SampleAfterValue": "200000", + "BriefDescription": "Large ITLB hit" + }, + { + "EventCode": "0x3", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "LOAD_BLOCK.OVERLAP_STORE", + "SampleAfterValue": "200000", + "BriefDescription": "Loads that partially overlap an earlier store" + }, + { + "EventCode": "0x13", + "Counter": "0,1,2,3", + "UMask": "0x7", + "EventName": "LOAD_DISPATCH.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "All loads dispatched" + }, + { + "EventCode": "0x13", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "LOAD_DISPATCH.MOB", + "SampleAfterValue": "2000000", + "BriefDescription": "Loads dispatched from the MOB" + }, + { + "EventCode": "0x13", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LOAD_DISPATCH.RS", + "SampleAfterValue": "2000000", + "BriefDescription": "Loads dispatched that bypass the MOB" + }, + { + "EventCode": "0x13", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "LOAD_DISPATCH.RS_DELAYED", + "SampleAfterValue": "2000000", + "BriefDescription": "Loads dispatched from stage 305" + }, + { + "EventCode": "0x7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "PARTIAL_ADDRESS_ALIAS", + "SampleAfterValue": "200000", + "BriefDescription": "False dependencies due to partial address aliasing" + }, + { + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "RAT_STALLS.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "All RAT stall cycles" + }, + { + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "RAT_STALLS.FLAGS", + "SampleAfterValue": "2000000", + "BriefDescription": "Flag stall cycles" + }, + { + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "RAT_STALLS.REGISTERS", + "SampleAfterValue": "2000000", + "BriefDescription": "Partial register stall cycles" + }, + { + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "RAT_STALLS.ROB_READ_PORT", + "SampleAfterValue": "2000000", + "BriefDescription": "ROB read port stalls cycles" + }, + { + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "RAT_STALLS.SCOREBOARD", + "SampleAfterValue": "2000000", + "BriefDescription": "Scoreboard stall cycles" + }, + { + "EventCode": "0x4", + "Counter": "0,1,2,3", + "UMask": "0x7", + "EventName": "SB_DRAIN.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "All Store buffer stall cycles" + }, + { + "EventCode": "0xD4", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "SEG_RENAME_STALLS", + "SampleAfterValue": "2000000", + "BriefDescription": "Segment rename stall cycles" + }, + { + "EventCode": "0xB8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "SNOOP_RESPONSE.HIT", + "SampleAfterValue": "100000", + "BriefDescription": "Thread responded HIT to snoop" + }, + { + "EventCode": "0xB8", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "SNOOP_RESPONSE.HITE", + "SampleAfterValue": "100000", + "BriefDescription": "Thread responded HITE to snoop" + }, + { + "EventCode": "0xB8", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "SNOOP_RESPONSE.HITM", + "SampleAfterValue": "100000", + "BriefDescription": "Thread responded HITM to snoop" + }, + { + "EventCode": "0xB4", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "SNOOPQ_REQUESTS.CODE", + "SampleAfterValue": "100000", + "BriefDescription": "Snoop code requests" + }, + { + "EventCode": "0xB4", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "SNOOPQ_REQUESTS.DATA", + "SampleAfterValue": "100000", + "BriefDescription": "Snoop data requests" + }, + { + "EventCode": "0xB4", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "SNOOPQ_REQUESTS.INVALIDATE", + "SampleAfterValue": "100000", + "BriefDescription": "Snoop invalidate requests" + }, + { + "EventCode": "0xB3", + "UMask": "0x4", + "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE", + "SampleAfterValue": "2000000", + "BriefDescription": "Outstanding snoop code requests" + }, + { + "EventCode": "0xB3", + "UMask": "0x4", + "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE_NOT_EMPTY", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles snoop code requests queued", + "CounterMask": "1" + }, + { + "EventCode": "0xB3", + "UMask": "0x1", + "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA", + "SampleAfterValue": "2000000", + "BriefDescription": "Outstanding snoop data requests" + }, + { + "EventCode": "0xB3", + "UMask": "0x1", + "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA_NOT_EMPTY", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles snoop data requests queued", + "CounterMask": "1" + }, + { + "EventCode": "0xB3", + "UMask": "0x2", + "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE", + "SampleAfterValue": "2000000", + "BriefDescription": "Outstanding snoop invalidate requests" + }, + { + "EventCode": "0xB3", + "UMask": "0x2", + "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE_NOT_EMPTY", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles snoop invalidate requests queued", + "CounterMask": "1" + }, + { + "EventCode": "0xF6", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "SQ_FULL_STALL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Super Queue full stall cycles" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereex/pipeline.json b/tools/perf/pmu-events/arch/x86/westmereex/pipeline.json new file mode 100644 index 000000000000..799c57d94c39 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/westmereex/pipeline.json @@ -0,0 +1,905 @@ +[ + { + "EventCode": "0x14", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ARITH.CYCLES_DIV_BUSY", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles the divider is busy" + }, + { + "EventCode": "0x14", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ARITH.DIV", + "SampleAfterValue": "2000000", + "BriefDescription": "Divide Operations executed", + "CounterMask": "1", + "EdgeDetect": "1" + }, + { + "EventCode": "0x14", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "ARITH.MUL", + "SampleAfterValue": "2000000", + "BriefDescription": "Multiply operations executed" + }, + { + "EventCode": "0xE6", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "BACLEAR.BAD_TARGET", + "SampleAfterValue": "2000000", + "BriefDescription": "BACLEAR asserted with bad target address" + }, + { + "EventCode": "0xE6", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BACLEAR.CLEAR", + "SampleAfterValue": "2000000", + "BriefDescription": "BACLEAR asserted, regardless of cause " + }, + { + "EventCode": "0xA7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BACLEAR_FORCE_IQ", + "SampleAfterValue": "2000000", + "BriefDescription": "Instruction queue forced BACLEAR" + }, + { + "EventCode": "0xE0", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BR_INST_DECODED", + "SampleAfterValue": "2000000", + "BriefDescription": "Branch instructions decoded" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x7f", + "EventName": "BR_INST_EXEC.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "Branch instructions executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BR_INST_EXEC.COND", + "SampleAfterValue": "200000", + "BriefDescription": "Conditional branch instructions executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "BR_INST_EXEC.DIRECT", + "SampleAfterValue": "200000", + "BriefDescription": "Unconditional branches executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL", + "SampleAfterValue": "20000", + "BriefDescription": "Unconditional call branches executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL", + "SampleAfterValue": "20000", + "BriefDescription": "Indirect call branches executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL", + "SampleAfterValue": "20000", + "BriefDescription": "Indirect non call branches executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "BR_INST_EXEC.NEAR_CALLS", + "SampleAfterValue": "20000", + "BriefDescription": "Call branches executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x7", + "EventName": "BR_INST_EXEC.NON_CALLS", + "SampleAfterValue": "200000", + "BriefDescription": "All non call branches executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "BR_INST_EXEC.RETURN_NEAR", + "SampleAfterValue": "20000", + "BriefDescription": "Indirect return branches executed" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "BR_INST_EXEC.TAKEN", + "SampleAfterValue": "200000", + "BriefDescription": "Taken branches executed" + }, + { + "PEBS": "1", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "SampleAfterValue": "200000", + "BriefDescription": "Retired branch instructions (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BR_INST_RETIRED.CONDITIONAL", + "SampleAfterValue": "200000", + "BriefDescription": "Retired conditional branch instructions (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "SampleAfterValue": "20000", + "BriefDescription": "Retired near call instructions (Precise Event)" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x7f", + "EventName": "BR_MISP_EXEC.ANY", + "SampleAfterValue": "20000", + "BriefDescription": "Mispredicted branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BR_MISP_EXEC.COND", + "SampleAfterValue": "20000", + "BriefDescription": "Mispredicted conditional branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "BR_MISP_EXEC.DIRECT", + "SampleAfterValue": "20000", + "BriefDescription": "Mispredicted unconditional branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL", + "SampleAfterValue": "2000", + "BriefDescription": "Mispredicted non call branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL", + "SampleAfterValue": "2000", + "BriefDescription": "Mispredicted indirect call branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL", + "SampleAfterValue": "2000", + "BriefDescription": "Mispredicted indirect non call branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "BR_MISP_EXEC.NEAR_CALLS", + "SampleAfterValue": "2000", + "BriefDescription": "Mispredicted call branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x7", + "EventName": "BR_MISP_EXEC.NON_CALLS", + "SampleAfterValue": "20000", + "BriefDescription": "Mispredicted non call branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "BR_MISP_EXEC.RETURN_NEAR", + "SampleAfterValue": "2000", + "BriefDescription": "Mispredicted return branches executed" + }, + { + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "BR_MISP_EXEC.TAKEN", + "SampleAfterValue": "20000", + "BriefDescription": "Mispredicted taken branches executed" + }, + { + "PEBS": "1", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "SampleAfterValue": "20000", + "BriefDescription": "Mispredicted retired branch instructions (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BR_MISP_RETIRED.CONDITIONAL", + "SampleAfterValue": "20000", + "BriefDescription": "Mispredicted conditional retired branches (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "BR_MISP_RETIRED.NEAR_CALL", + "SampleAfterValue": "2000", + "BriefDescription": "Mispredicted near retired calls (Precise Event)" + }, + { + "EventCode": "0x0", + "Counter": "Fixed counter 3", + "UMask": "0x0", + "EventName": "CPU_CLK_UNHALTED.REF", + "SampleAfterValue": "2000000", + "BriefDescription": "Reference cycles when thread is not halted (fixed counter)" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CPU_CLK_UNHALTED.REF_P", + "SampleAfterValue": "100000", + "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)" + }, + { + "EventCode": "0x0", + "Counter": "Fixed counter 2", + "UMask": "0x0", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles when thread is not halted (fixed counter)" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles when thread is not halted (programmable counter)" + }, + { + "EventCode": "0x3C", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Total CPU cycles", + "CounterMask": "2" + }, + { + "EventCode": "0x87", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "ILD_STALL.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "Any Instruction Length Decoder stall cycles" + }, + { + "EventCode": "0x87", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "ILD_STALL.IQ_FULL", + "SampleAfterValue": "2000000", + "BriefDescription": "Instruction Queue full stall cycles" + }, + { + "EventCode": "0x87", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ILD_STALL.LCP", + "SampleAfterValue": "2000000", + "BriefDescription": "Length Change Prefix stall cycles" + }, + { + "EventCode": "0x87", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "ILD_STALL.MRU", + "SampleAfterValue": "2000000", + "BriefDescription": "Stall cycles due to BPU MRU bypass" + }, + { + "EventCode": "0x87", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "ILD_STALL.REGEN", + "SampleAfterValue": "2000000", + "BriefDescription": "Regen stall cycles" + }, + { + "EventCode": "0x18", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "INST_DECODED.DEC0", + "SampleAfterValue": "2000000", + "BriefDescription": "Instructions that must be decoded by decoder 0" + }, + { + "EventCode": "0x1E", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "INST_QUEUE_WRITE_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles instructions are written to the instruction queue" + }, + { + "EventCode": "0x17", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "INST_QUEUE_WRITES", + "SampleAfterValue": "2000000", + "BriefDescription": "Instructions written to instruction queue." + }, + { + "EventCode": "0x0", + "Counter": "Fixed counter 1", + "UMask": "0x0", + "EventName": "INST_RETIRED.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "Instructions retired (fixed counter)" + }, + { + "PEBS": "1", + "EventCode": "0xC0", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "INST_RETIRED.ANY_P", + "SampleAfterValue": "2000000", + "BriefDescription": "Instructions retired (Programmable counter and Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC0", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "INST_RETIRED.MMX", + "SampleAfterValue": "2000000", + "BriefDescription": "Retired MMX instructions (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC0", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "INST_RETIRED.TOTAL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Total cycles (Precise Event)", + "CounterMask": "16" + }, + { + "PEBS": "1", + "EventCode": "0xC0", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "INST_RETIRED.X87", + "SampleAfterValue": "2000000", + "BriefDescription": "Retired floating-point operations (Precise Event)" + }, + { + "EventCode": "0x4C", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "LOAD_HIT_PRE", + "SampleAfterValue": "200000", + "BriefDescription": "Load operations conflicting with software prefetches" + }, + { + "EventCode": "0xA8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LSD.ACTIVE", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles when uops were delivered by the LSD", + "CounterMask": "1" + }, + { + "EventCode": "0xA8", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LSD.INACTIVE", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles no uops were delivered by the LSD", + "CounterMask": "1" + }, + { + "EventCode": "0x20", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LSD_OVERFLOW", + "SampleAfterValue": "2000000", + "BriefDescription": "Loops that can't stream from the instruction queue" + }, + { + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MACHINE_CLEARS.CYCLES", + "SampleAfterValue": "20000", + "BriefDescription": "Cycles machine clear asserted" + }, + { + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MACHINE_CLEARS.MEM_ORDER", + "SampleAfterValue": "20000", + "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts" + }, + { + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "MACHINE_CLEARS.SMC", + "SampleAfterValue": "20000", + "BriefDescription": "Self-Modifying Code detected" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "RESOURCE_STALLS.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "Resource related stall cycles" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "RESOURCE_STALLS.FPCW", + "SampleAfterValue": "2000000", + "BriefDescription": "FPU control word write stall cycles" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "RESOURCE_STALLS.LOAD", + "SampleAfterValue": "2000000", + "BriefDescription": "Load buffer stall cycles" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "RESOURCE_STALLS.MXCSR", + "SampleAfterValue": "2000000", + "BriefDescription": "MXCSR rename stall cycles" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "RESOURCE_STALLS.OTHER", + "SampleAfterValue": "2000000", + "BriefDescription": "Other Resource related stall cycles" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "RESOURCE_STALLS.ROB_FULL", + "SampleAfterValue": "2000000", + "BriefDescription": "ROB full stall cycles" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "RESOURCE_STALLS.RS_FULL", + "SampleAfterValue": "2000000", + "BriefDescription": "Reservation Station full stall cycles" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "RESOURCE_STALLS.STORE", + "SampleAfterValue": "2000000", + "BriefDescription": "Store buffer stall cycles" + }, + { + "PEBS": "1", + "EventCode": "0xC7", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC7", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC7", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC7", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER", + "SampleAfterValue": "200000", + "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles thread is active" + }, + { + "EventCode": "0xDB", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOP_UNFUSION", + "SampleAfterValue": "2000000", + "BriefDescription": "Uop unfusions due to FP exceptions" + }, + { + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "UOPS_DECODED.ESP_FOLDING", + "SampleAfterValue": "2000000", + "BriefDescription": "Stack pointer instructions decoded" + }, + { + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "UOPS_DECODED.ESP_SYNC", + "SampleAfterValue": "2000000", + "BriefDescription": "Stack pointer sync operations" + }, + { + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops decoded by Microcode Sequencer", + "CounterMask": "1" + }, + { + "EventCode": "0xD1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_DECODED.STALL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles no Uops are decoded", + "CounterMask": "1" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x3f", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles Uops executed on any port (core count)", + "CounterMask": "1" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x1f", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)", + "CounterMask": "1" + }, + { + "EventCode": "0xB1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x3f", + "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops executed on any port (core count)", + "CounterMask": "1", + "EdgeDetect": "1" + }, + { + "EventCode": "0xB1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1f", + "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops executed on ports 0-4 (core count)", + "CounterMask": "1", + "EdgeDetect": "1" + }, + { + "EventCode": "0xB1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x3f", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles no Uops issued on any port (core count)", + "CounterMask": "1" + }, + { + "EventCode": "0xB1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1f", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)", + "CounterMask": "1" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_EXECUTED.PORT0", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops executed on port 0" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "UOPS_EXECUTED.PORT015", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops issued on ports 0, 1 or 5" + }, + { + "EventCode": "0xB1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5", + "CounterMask": "1" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.PORT1", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops executed on port 1" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x4", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.PORT2_CORE", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops executed on port 2 (core count)" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x80", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.PORT234_CORE", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops issued on ports 2, 3 or 4" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x8", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.PORT3_CORE", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops executed on port 3 (core count)" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x10", + "AnyThread": "1", + "EventName": "UOPS_EXECUTED.PORT4_CORE", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops executed on port 4 (core count)" + }, + { + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "UOPS_EXECUTED.PORT5", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops executed on port 5" + }, + { + "EventCode": "0xE", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_ISSUED.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops issued" + }, + { + "EventCode": "0xE", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles no Uops were issued on any thread", + "CounterMask": "1" + }, + { + "EventCode": "0xE", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles Uops were issued on either thread", + "CounterMask": "1" + }, + { + "EventCode": "0xE", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_ISSUED.FUSED", + "SampleAfterValue": "2000000", + "BriefDescription": "Fused Uops issued" + }, + { + "EventCode": "0xE", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles no Uops were issued", + "CounterMask": "1" + }, + { + "PEBS": "1", + "EventCode": "0xC2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.ACTIVE_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles Uops are being retired", + "CounterMask": "1" + }, + { + "PEBS": "1", + "EventCode": "0xC2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.ANY", + "SampleAfterValue": "2000000", + "BriefDescription": "Uops retired (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "UOPS_RETIRED.MACRO_FUSED", + "SampleAfterValue": "2000000", + "BriefDescription": "Macro-fused Uops retired (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "SampleAfterValue": "2000000", + "BriefDescription": "Retirement slots used (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC2", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles Uops are not retiring (Precise Event)", + "CounterMask": "1" + }, + { + "PEBS": "1", + "EventCode": "0xC2", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Total cycles using precise uop retired event (Precise Event)", + "CounterMask": "16" + }, + { + "PEBS": "2", + "EventCode": "0xC0", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "INST_RETIRED.TOTAL_CYCLES_PS", + "SampleAfterValue": "2000000", + "BriefDescription": "Total cycles (Precise Event)", + "CounterMask": "16" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json b/tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json new file mode 100644 index 000000000000..ad989207e8f8 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json @@ -0,0 +1,173 @@ +[ + { + "EventCode": "0x8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "DTLB_LOAD_MISSES.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB load misses" + }, + { + "EventCode": "0x8", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB load miss large page walks" + }, + { + "EventCode": "0x8", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "DTLB_LOAD_MISSES.PDE_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB load miss caused by low part of address" + }, + { + "EventCode": "0x8", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "SampleAfterValue": "2000000", + "BriefDescription": "DTLB second level hit" + }, + { + "EventCode": "0x8", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB load miss page walks complete" + }, + { + "EventCode": "0x8", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "DTLB_LOAD_MISSES.WALK_CYCLES", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB load miss page walk cycles" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "DTLB_MISSES.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB misses" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB miss large page walks" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "DTLB_MISSES.PDE_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB misses caused by low part of address. Count also includes 2M page references because 2M pages do not use the PDE." + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "DTLB_MISSES.STLB_HIT", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB first level misses but second level hit" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "DTLB_MISSES.WALK_COMPLETED", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB miss page walks" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "DTLB_MISSES.WALK_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "DTLB miss page walk cycles" + }, + { + "EventCode": "0x4F", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "EPT.WALK_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Extended Page Table walk cycles" + }, + { + "EventCode": "0xAE", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ITLB_FLUSH", + "SampleAfterValue": "2000000", + "BriefDescription": "ITLB flushes" + }, + { + "PEBS": "1", + "EventCode": "0xC8", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "ITLB_MISS_RETIRED", + "SampleAfterValue": "200000", + "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)" + }, + { + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ITLB_MISSES.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "ITLB miss" + }, + { + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "ITLB_MISSES.LARGE_WALK_COMPLETED", + "SampleAfterValue": "200000", + "BriefDescription": "ITLB miss large page walks" + }, + { + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "SampleAfterValue": "200000", + "BriefDescription": "ITLB miss page walks" + }, + { + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "ITLB_MISSES.WALK_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "ITLB miss page walk cycles" + }, + { + "PEBS": "1", + "EventCode": "0xCB", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "MEM_LOAD_RETIRED.DTLB_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "Retired loads that miss the DTLB (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_STORE_RETIRED.DTLB_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "Retired stores that miss the DTLB (Precise Event)" + } +]
\ No newline at end of file diff --git a/tools/perf/tests/Build b/tools/perf/tests/Build index 8a4ce492f7b2..6676c2dd6dcb 100644 --- a/tools/perf/tests/Build +++ b/tools/perf/tests/Build @@ -42,6 +42,8 @@ perf-y += backward-ring-buffer.o perf-y += sdt.o perf-y += is_printable_array.o perf-y += bitmap.o +perf-y += perf-hooks.o +perf-y += clang.o $(OUTPUT)tests/llvm-src-base.c: tests/bpf-script-example.c tests/Build $(call rule_mkdir) diff --git a/tools/perf/tests/backward-ring-buffer.c b/tools/perf/tests/backward-ring-buffer.c index e6d1816e431a..42e892b1e979 100644 --- a/tools/perf/tests/backward-ring-buffer.c +++ b/tools/perf/tests/backward-ring-buffer.c @@ -97,7 +97,7 @@ int test__backward_ring_buffer(int subtest __maybe_unused) evlist = perf_evlist__new(); if (!evlist) { - pr_debug("No enough memory to create evlist\n"); + pr_debug("Not enough memory to create evlist\n"); return TEST_FAIL; } diff --git a/tools/perf/tests/bpf.c b/tools/perf/tests/bpf.c index 2673e86ed50f..92343f43e44a 100644 --- a/tools/perf/tests/bpf.c +++ b/tools/perf/tests/bpf.c @@ -57,7 +57,7 @@ static struct { } bpf_testcase_table[] = { { LLVM_TESTCASE_BASE, - "Test basic BPF filtering", + "Basic BPF filtering", "[basic_bpf_test]", "fix 'perf test LLVM' first", "load bpf object failed", @@ -67,7 +67,7 @@ static struct { #ifdef HAVE_BPF_PROLOGUE { LLVM_TESTCASE_BPF_PROLOGUE, - "Test BPF prologue generation", + "BPF prologue generation", "[bpf_prologue_test]", "fix kbuild first", "check your vmlinux setting?", @@ -77,7 +77,7 @@ static struct { #endif { LLVM_TESTCASE_BPF_RELOCATION, - "Test BPF relocation checker", + "BPF relocation checker", "[bpf_relocation_test]", "fix 'perf test LLVM' first", "libbpf error when dealing with relocation", @@ -125,7 +125,7 @@ static int do_test(struct bpf_object *obj, int (*func)(void), /* Instead of perf_evlist__new_default, don't add default events */ evlist = perf_evlist__new(); if (!evlist) { - pr_debug("No enough memory to create evlist\n"); + pr_debug("Not enough memory to create evlist\n"); return TEST_FAIL; } diff --git a/tools/perf/tests/builtin-test.c b/tools/perf/tests/builtin-test.c index 778668a2a966..23605202d4a1 100644 --- a/tools/perf/tests/builtin-test.c +++ b/tools/perf/tests/builtin-test.c @@ -28,119 +28,119 @@ static struct test generic_tests[] = { .func = test__vmlinux_matches_kallsyms, }, { - .desc = "detect openat syscall event", + .desc = "Detect openat syscall event", .func = test__openat_syscall_event, }, { - .desc = "detect openat syscall event on all cpus", + .desc = "Detect openat syscall event on all cpus", .func = test__openat_syscall_event_on_all_cpus, }, { - .desc = "read samples using the mmap interface", + .desc = "Read samples using the mmap interface", .func = test__basic_mmap, }, { - .desc = "parse events tests", + .desc = "Parse event definition strings", .func = test__parse_events, }, { - .desc = "Validate PERF_RECORD_* events & perf_sample fields", + .desc = "PERF_RECORD_* events & perf_sample fields", .func = test__PERF_RECORD, }, { - .desc = "Test perf pmu format parsing", + .desc = "Parse perf pmu format", .func = test__pmu, }, { - .desc = "Test dso data read", + .desc = "DSO data read", .func = test__dso_data, }, { - .desc = "Test dso data cache", + .desc = "DSO data cache", .func = test__dso_data_cache, }, { - .desc = "Test dso data reopen", + .desc = "DSO data reopen", .func = test__dso_data_reopen, }, { - .desc = "roundtrip evsel->name check", + .desc = "Roundtrip evsel->name", .func = test__perf_evsel__roundtrip_name_test, }, { - .desc = "Check parsing of sched tracepoints fields", + .desc = "Parse sched tracepoints fields", .func = test__perf_evsel__tp_sched_test, }, { - .desc = "Generate and check syscalls:sys_enter_openat event fields", + .desc = "syscalls:sys_enter_openat event fields", .func = test__syscall_openat_tp_fields, }, { - .desc = "struct perf_event_attr setup", + .desc = "Setup struct perf_event_attr", .func = test__attr, }, { - .desc = "Test matching and linking multiple hists", + .desc = "Match and link multiple hists", .func = test__hists_link, }, { - .desc = "Try 'import perf' in python, checking link problems", + .desc = "'import perf' in python", .func = test__python_use, }, { - .desc = "Test breakpoint overflow signal handler", + .desc = "Breakpoint overflow signal handler", .func = test__bp_signal, }, { - .desc = "Test breakpoint overflow sampling", + .desc = "Breakpoint overflow sampling", .func = test__bp_signal_overflow, }, { - .desc = "Test number of exit event of a simple workload", + .desc = "Number of exit events of a simple workload", .func = test__task_exit, }, { - .desc = "Test software clock events have valid period values", + .desc = "Software clock events period values", .func = test__sw_clock_freq, }, { - .desc = "Test object code reading", + .desc = "Object code reading", .func = test__code_reading, }, { - .desc = "Test sample parsing", + .desc = "Sample parsing", .func = test__sample_parsing, }, { - .desc = "Test using a dummy software event to keep tracking", + .desc = "Use a dummy software event to keep tracking", .func = test__keep_tracking, }, { - .desc = "Test parsing with no sample_id_all bit set", + .desc = "Parse with no sample_id_all bit set", .func = test__parse_no_sample_id_all, }, { - .desc = "Test filtering hist entries", + .desc = "Filter hist entries", .func = test__hists_filter, }, { - .desc = "Test mmap thread lookup", + .desc = "Lookup mmap thread", .func = test__mmap_thread_lookup, }, { - .desc = "Test thread mg sharing", + .desc = "Share thread mg", .func = test__thread_mg_share, }, { - .desc = "Test output sorting of hist entries", + .desc = "Sort output of hist entries", .func = test__hists_output, }, { - .desc = "Test cumulation of child hist entries", + .desc = "Cumulate child hist entries", .func = test__hists_cumulate, }, { - .desc = "Test tracking with sched_switch", + .desc = "Track with sched_switch", .func = test__switch_tracking, }, { @@ -152,15 +152,15 @@ static struct test generic_tests[] = { .func = test__fdarray__add, }, { - .desc = "Test kmod_path__parse function", + .desc = "kmod_path__parse", .func = test__kmod_path__parse, }, { - .desc = "Test thread map", + .desc = "Thread map", .func = test__thread_map, }, { - .desc = "Test LLVM searching and compiling", + .desc = "LLVM search and compile", .func = test__llvm, .subtest = { .skip_if_fail = true, @@ -169,11 +169,11 @@ static struct test generic_tests[] = { }, }, { - .desc = "Test topology in session", + .desc = "Session topology", .func = test_session_topology, }, { - .desc = "Test BPF filter", + .desc = "BPF filter", .func = test__bpf, .subtest = { .skip_if_fail = true, @@ -182,54 +182,67 @@ static struct test generic_tests[] = { }, }, { - .desc = "Test thread map synthesize", + .desc = "Synthesize thread map", .func = test__thread_map_synthesize, }, { - .desc = "Test cpu map synthesize", + .desc = "Synthesize cpu map", .func = test__cpu_map_synthesize, }, { - .desc = "Test stat config synthesize", + .desc = "Synthesize stat config", .func = test__synthesize_stat_config, }, { - .desc = "Test stat synthesize", + .desc = "Synthesize stat", .func = test__synthesize_stat, }, { - .desc = "Test stat round synthesize", + .desc = "Synthesize stat round", .func = test__synthesize_stat_round, }, { - .desc = "Test attr update synthesize", + .desc = "Synthesize attr update", .func = test__event_update, }, { - .desc = "Test events times", + .desc = "Event times", .func = test__event_times, }, { - .desc = "Test backward reading from ring buffer", + .desc = "Read backward ring buffer", .func = test__backward_ring_buffer, }, { - .desc = "Test cpu map print", + .desc = "Print cpu map", .func = test__cpu_map_print, }, { - .desc = "Test SDT event probing", + .desc = "Probe SDT events", .func = test__sdt_event, }, { - .desc = "Test is_printable_array function", + .desc = "is_printable_array", .func = test__is_printable_array, }, { - .desc = "Test bitmap print", + .desc = "Print bitmap", .func = test__bitmap_print, }, { + .desc = "perf hooks", + .func = test__perf_hooks, + }, + { + .desc = "builtin clang support", + .func = test__clang, + .subtest = { + .skip_if_fail = true, + .get_nr = test__clang_subtest_get_nr, + .get_desc = test__clang_subtest_get_desc, + } + }, + { .func = NULL, }, }; diff --git a/tools/perf/tests/clang.c b/tools/perf/tests/clang.c new file mode 100644 index 000000000000..f853e242a86c --- /dev/null +++ b/tools/perf/tests/clang.c @@ -0,0 +1,46 @@ +#include "tests.h" +#include "debug.h" +#include "util.h" +#include "c++/clang-c.h" + +static struct { + int (*func)(void); + const char *desc; +} clang_testcase_table[] = { +#ifdef HAVE_LIBCLANGLLVM_SUPPORT + { + .func = test__clang_to_IR, + .desc = "builtin clang compile C source to IR", + }, + { + .func = test__clang_to_obj, + .desc = "builtin clang compile C source to ELF object", + }, +#endif +}; + +int test__clang_subtest_get_nr(void) +{ + return (int)ARRAY_SIZE(clang_testcase_table); +} + +const char *test__clang_subtest_get_desc(int i) +{ + if (i < 0 || i >= (int)ARRAY_SIZE(clang_testcase_table)) + return NULL; + return clang_testcase_table[i].desc; +} + +#ifndef HAVE_LIBCLANGLLVM_SUPPORT +int test__clang(int i __maybe_unused) +{ + return TEST_SKIP; +} +#else +int test__clang(int i) +{ + if (i < 0 || i >= (int)ARRAY_SIZE(clang_testcase_table)) + return TEST_FAIL; + return clang_testcase_table[i].func(); +} +#endif diff --git a/tools/perf/tests/llvm.c b/tools/perf/tests/llvm.c index b798a4bfd238..02a33ebcd992 100644 --- a/tools/perf/tests/llvm.c +++ b/tools/perf/tests/llvm.c @@ -34,19 +34,19 @@ static struct { } bpf_source_table[__LLVM_TESTCASE_MAX] = { [LLVM_TESTCASE_BASE] = { .source = test_llvm__bpf_base_prog, - .desc = "Basic BPF llvm compiling test", + .desc = "Basic BPF llvm compile", }, [LLVM_TESTCASE_KBUILD] = { .source = test_llvm__bpf_test_kbuild_prog, - .desc = "Test kbuild searching", + .desc = "kbuild searching", }, [LLVM_TESTCASE_BPF_PROLOGUE] = { .source = test_llvm__bpf_test_prologue_prog, - .desc = "Compile source for BPF prologue generation test", + .desc = "Compile source for BPF prologue generation", }, [LLVM_TESTCASE_BPF_RELOCATION] = { .source = test_llvm__bpf_test_relocation, - .desc = "Compile source for BPF relocation test", + .desc = "Compile source for BPF relocation", .should_load_fail = true, }, }; diff --git a/tools/perf/tests/llvm.h b/tools/perf/tests/llvm.h index 0eaa604be99d..b83571758d83 100644 --- a/tools/perf/tests/llvm.h +++ b/tools/perf/tests/llvm.h @@ -1,6 +1,10 @@ #ifndef PERF_TEST_LLVM_H #define PERF_TEST_LLVM_H +#ifdef __cplusplus +extern "C" { +#endif + #include <stddef.h> /* for size_t */ #include <stdbool.h> /* for bool */ @@ -20,4 +24,7 @@ enum test_llvm__testcase { int test_llvm__fetch_bpf_obj(void **p_obj_buf, size_t *p_obj_buf_sz, enum test_llvm__testcase index, bool force, bool *should_load_fail); +#ifdef __cplusplus +} +#endif #endif diff --git a/tools/perf/tests/make b/tools/perf/tests/make index 143f4d549769..0784748f1670 100644 --- a/tools/perf/tests/make +++ b/tools/perf/tests/make @@ -83,6 +83,7 @@ make_no_libbpf := NO_LIBBPF=1 make_no_libcrypto := NO_LIBCRYPTO=1 make_with_babeltrace:= LIBBABELTRACE=1 make_no_sdt := NO_SDT=1 +make_with_clangllvm := LIBCLANGLLVM=1 make_tags := tags make_cscope := cscope make_help := help @@ -106,7 +107,7 @@ make_minimal := NO_LIBPERL=1 NO_LIBPYTHON=1 NO_NEWT=1 NO_GTK2=1 make_minimal += NO_DEMANGLE=1 NO_LIBELF=1 NO_LIBUNWIND=1 NO_BACKTRACE=1 make_minimal += NO_LIBNUMA=1 NO_LIBAUDIT=1 NO_LIBBIONIC=1 make_minimal += NO_LIBDW_DWARF_UNWIND=1 NO_AUXTRACE=1 NO_LIBBPF=1 -make_minimal += NO_LIBCRYPTO=1 NO_SDT=1 +make_minimal += NO_LIBCRYPTO=1 NO_SDT=1 NO_JVMTI=1 # $(run) contains all available tests run := make_pure @@ -139,6 +140,7 @@ run += make_no_libbionic run += make_no_auxtrace run += make_no_libbpf run += make_with_babeltrace +run += make_with_clangllvm run += make_help run += make_doc run += make_perf_o @@ -278,7 +280,7 @@ endif MAKEFLAGS := --no-print-directory -clean := @(cd $(PERF); $(MAKE_F) -s $(O_OPT) clean >/dev/null) +clean := @(cd $(PERF); $(MAKE_F) -s $(O_OPT) clean >/dev/null && $(MAKE) -s $(O_OPT) -C ../build clean >/dev/null) $(run): $(call clean) diff --git a/tools/perf/tests/perf-hooks.c b/tools/perf/tests/perf-hooks.c new file mode 100644 index 000000000000..665ecc19671c --- /dev/null +++ b/tools/perf/tests/perf-hooks.c @@ -0,0 +1,48 @@ +#include <signal.h> +#include <stdlib.h> + +#include "tests.h" +#include "debug.h" +#include "util.h" +#include "perf-hooks.h" + +static void sigsegv_handler(int sig __maybe_unused) +{ + pr_debug("SIGSEGV is observed as expected, try to recover.\n"); + perf_hooks__recover(); + signal(SIGSEGV, SIG_DFL); + raise(SIGSEGV); + exit(-1); +} + + +static void the_hook(void *_hook_flags) +{ + int *hook_flags = _hook_flags; + int *p = NULL; + + *hook_flags = 1234; + + /* Generate a segfault, test perf_hooks__recover */ + *p = 0; +} + +int test__perf_hooks(int subtest __maybe_unused) +{ + int hook_flags = 0; + + signal(SIGSEGV, sigsegv_handler); + perf_hooks__set_hook("test", the_hook, &hook_flags); + perf_hooks__invoke_test(); + + /* hook is triggered? */ + if (hook_flags != 1234) { + pr_debug("Setting failed: %d (%p)\n", hook_flags, &hook_flags); + return TEST_FAIL; + } + + /* the buggy hook is removed? */ + if (perf_hooks__get_hook("test")) + return TEST_FAIL; + return TEST_OK; +} diff --git a/tools/perf/tests/tests.h b/tools/perf/tests/tests.h index 7c196c585472..0d7b251305af 100644 --- a/tools/perf/tests/tests.h +++ b/tools/perf/tests/tests.h @@ -91,6 +91,10 @@ int test__cpu_map_print(int subtest); int test__sdt_event(int subtest); int test__is_printable_array(int subtest); int test__bitmap_print(int subtest); +int test__perf_hooks(int subtest); +int test__clang(int subtest); +const char *test__clang_subtest_get_desc(int subtest); +int test__clang_subtest_get_nr(void); #if defined(__arm__) || defined(__aarch64__) #ifdef HAVE_DWARF_UNWIND_SUPPORT diff --git a/tools/perf/ui/browsers/annotate.c b/tools/perf/ui/browsers/annotate.c index 4c18271c71c9..ec7a30fad149 100644 --- a/tools/perf/ui/browsers/annotate.c +++ b/tools/perf/ui/browsers/annotate.c @@ -213,17 +213,17 @@ static void annotate_browser__write(struct ui_browser *browser, void *entry, int ui_browser__write_nstring(browser, bf, printed); if (change_color) ui_browser__set_color(browser, color); - if (dl->ins && dl->ins->ops->scnprintf) { - if (ins__is_jump(dl->ins)) { + if (dl->ins.ops && dl->ins.ops->scnprintf) { + if (ins__is_jump(&dl->ins)) { bool fwd = dl->ops.target.offset > (u64)dl->offset; ui_browser__write_graph(browser, fwd ? SLSMG_DARROW_CHAR : SLSMG_UARROW_CHAR); SLsmg_write_char(' '); - } else if (ins__is_call(dl->ins)) { + } else if (ins__is_call(&dl->ins)) { ui_browser__write_graph(browser, SLSMG_RARROW_CHAR); SLsmg_write_char(' '); - } else if (ins__is_ret(dl->ins)) { + } else if (ins__is_ret(&dl->ins)) { ui_browser__write_graph(browser, SLSMG_LARROW_CHAR); SLsmg_write_char(' '); } else { @@ -243,7 +243,7 @@ static void annotate_browser__write(struct ui_browser *browser, void *entry, int static bool disasm_line__is_valid_jump(struct disasm_line *dl, struct symbol *sym) { - if (!dl || !dl->ins || !ins__is_jump(dl->ins) + if (!dl || !dl->ins.ops || !ins__is_jump(&dl->ins) || !disasm_line__has_offset(dl) || dl->ops.target.offset >= symbol__size(sym)) return false; @@ -492,7 +492,7 @@ static bool annotate_browser__callq(struct annotate_browser *browser, }; char title[SYM_TITLE_MAX_SIZE]; - if (!ins__is_call(dl->ins)) + if (!ins__is_call(&dl->ins)) return false; if (map_groups__find_ams(&target) || @@ -543,14 +543,16 @@ struct disasm_line *annotate_browser__find_offset(struct annotate_browser *brows static bool annotate_browser__jump(struct annotate_browser *browser) { struct disasm_line *dl = browser->selection; + u64 offset; s64 idx; - if (!ins__is_jump(dl->ins)) + if (!ins__is_jump(&dl->ins)) return false; - dl = annotate_browser__find_offset(browser, dl->ops.target.offset, &idx); + offset = dl->ops.target.offset; + dl = annotate_browser__find_offset(browser, offset, &idx); if (dl == NULL) { - ui_helpline__puts("Invalid jump offset"); + ui_helpline__printf("Invalid jump offset: %" PRIx64, offset); return true; } @@ -841,9 +843,9 @@ show_help: ui_helpline__puts("Huh? No selection. Report to linux-kernel@vger.kernel.org"); else if (browser->selection->offset == -1) ui_helpline__puts("Actions are only available for assembly lines."); - else if (!browser->selection->ins) + else if (!browser->selection->ins.ops) goto show_sup_ins; - else if (ins__is_ret(browser->selection->ins)) + else if (ins__is_ret(&browser->selection->ins)) goto out; else if (!(annotate_browser__jump(browser) || annotate_browser__callq(browser, evsel, hbt))) { @@ -1050,7 +1052,7 @@ int symbol__tui_annotate(struct symbol *sym, struct map *map, (nr_pcnt - 1); } - err = symbol__disassemble(sym, map, sizeof_bdl); + err = symbol__disassemble(sym, map, perf_evsel__env_arch(evsel), sizeof_bdl); if (err) { char msg[BUFSIZ]; symbol__strerror_disassemble(sym, map, err, msg, sizeof(msg)); diff --git a/tools/perf/ui/browsers/hists.c b/tools/perf/ui/browsers/hists.c index a53fef0c673b..641b40234a9d 100644 --- a/tools/perf/ui/browsers/hists.c +++ b/tools/perf/ui/browsers/hists.c @@ -30,7 +30,7 @@ static struct rb_node *hists__filter_entries(struct rb_node *nd, static bool hist_browser__has_filter(struct hist_browser *hb) { - return hists__has_filter(hb->hists) || hb->min_pcnt || symbol_conf.has_filter; + return hists__has_filter(hb->hists) || hb->min_pcnt || symbol_conf.has_filter || hb->c2c_filter; } static int hist_browser__get_folding(struct hist_browser *browser) @@ -738,6 +738,7 @@ static int hist_browser__show_callchain_list(struct hist_browser *browser, struct callchain_print_arg *arg) { char bf[1024], *alloc_str; + char buf[64], *alloc_str2; const char *str; if (arg->row_offset != 0) { @@ -746,12 +747,26 @@ static int hist_browser__show_callchain_list(struct hist_browser *browser, } alloc_str = NULL; + alloc_str2 = NULL; + str = callchain_list__sym_name(chain, bf, sizeof(bf), browser->show_dso); - if (need_percent) { - char buf[64]; + if (symbol_conf.show_branchflag_count) { + if (need_percent) + callchain_list_counts__printf_value(node, chain, NULL, + buf, sizeof(buf)); + else + callchain_list_counts__printf_value(NULL, chain, NULL, + buf, sizeof(buf)); + + if (asprintf(&alloc_str2, "%s%s", str, buf) < 0) + str = "Not enough memory!"; + else + str = alloc_str2; + } + if (need_percent) { callchain_node__scnprintf_value(node, buf, sizeof(buf), total); @@ -764,6 +779,7 @@ static int hist_browser__show_callchain_list(struct hist_browser *browser, print(browser, chain, str, offset, row, arg); free(alloc_str); + free(alloc_str2); return 1; } @@ -2833,7 +2849,10 @@ static int perf_evsel__hists_browse(struct perf_evsel *evsel, int nr_events, do_zoom_dso(browser, actions); continue; case 'V': - browser->show_dso = !browser->show_dso; + verbose = (verbose + 1) % 4; + browser->show_dso = verbose > 0; + ui_helpline__fpush("Verbosity level set to %d\n", + verbose); continue; case 't': actions->thread = thread; diff --git a/tools/perf/ui/browsers/hists.h b/tools/perf/ui/browsers/hists.h index 39bd0f28f211..23d6acb84800 100644 --- a/tools/perf/ui/browsers/hists.h +++ b/tools/perf/ui/browsers/hists.h @@ -18,6 +18,7 @@ struct hist_browser { u64 nr_non_filtered_entries; u64 nr_hierarchy_entries; u64 nr_callchain_rows; + bool c2c_filter; /* Get title string. */ int (*title)(struct hist_browser *browser, diff --git a/tools/perf/ui/gtk/annotate.c b/tools/perf/ui/gtk/annotate.c index 42d319927762..8c9308ac30b7 100644 --- a/tools/perf/ui/gtk/annotate.c +++ b/tools/perf/ui/gtk/annotate.c @@ -167,7 +167,7 @@ static int symbol__gtk_annotate(struct symbol *sym, struct map *map, if (map->dso->annotate_warned) return -1; - err = symbol__disassemble(sym, map, 0); + err = symbol__disassemble(sym, map, perf_evsel__env_arch(evsel), 0); if (err) { char msg[BUFSIZ]; symbol__strerror_disassemble(sym, map, err, msg, sizeof(msg)); diff --git a/tools/perf/ui/helpline.c b/tools/perf/ui/helpline.c index 5b74a7eba210..379039ab00d8 100644 --- a/tools/perf/ui/helpline.c +++ b/tools/perf/ui/helpline.c @@ -72,3 +72,13 @@ int ui_helpline__vshow(const char *fmt, va_list ap) { return helpline_fns->show(fmt, ap); } + +void ui_helpline__printf(const char *fmt, ...) +{ + va_list ap; + + ui_helpline__pop(); + va_start(ap, fmt); + ui_helpline__vpush(fmt, ap); + va_end(ap); +} diff --git a/tools/perf/ui/helpline.h b/tools/perf/ui/helpline.h index 46181f4fc07e..d52d0a1a881b 100644 --- a/tools/perf/ui/helpline.h +++ b/tools/perf/ui/helpline.h @@ -21,6 +21,7 @@ void ui_helpline__push(const char *msg); void ui_helpline__vpush(const char *fmt, va_list ap); void ui_helpline__fpush(const char *fmt, ...); void ui_helpline__puts(const char *msg); +void ui_helpline__printf(const char *fmt, ...); int ui_helpline__vshow(const char *fmt, va_list ap); extern char ui_helpline__current[512]; diff --git a/tools/perf/ui/stdio/hist.c b/tools/perf/ui/stdio/hist.c index 89d8441f9890..668f4aecf2e6 100644 --- a/tools/perf/ui/stdio/hist.c +++ b/tools/perf/ui/stdio/hist.c @@ -41,7 +41,9 @@ static size_t ipchain__fprintf_graph(FILE *fp, struct callchain_node *node, { int i; size_t ret = 0; - char bf[1024]; + char bf[1024], *alloc_str = NULL; + char buf[64]; + const char *str; ret += callchain__fprintf_left_margin(fp, left_margin); for (i = 0; i < depth; i++) { @@ -56,8 +58,26 @@ static size_t ipchain__fprintf_graph(FILE *fp, struct callchain_node *node, } else ret += fprintf(fp, "%s", " "); } - fputs(callchain_list__sym_name(chain, bf, sizeof(bf), false), fp); + + str = callchain_list__sym_name(chain, bf, sizeof(bf), false); + + if (symbol_conf.show_branchflag_count) { + if (!period) + callchain_list_counts__printf_value(node, chain, NULL, + buf, sizeof(buf)); + else + callchain_list_counts__printf_value(NULL, chain, NULL, + buf, sizeof(buf)); + + if (asprintf(&alloc_str, "%s%s", str, buf) < 0) + str = "Not enough memory!"; + else + str = alloc_str; + } + + fputs(str, fp); fputc('\n', fp); + free(alloc_str); return ret; } @@ -219,8 +239,15 @@ static size_t callchain__fprintf_graph(FILE *fp, struct rb_root *root, } else ret += callchain__fprintf_left_margin(fp, left_margin); - ret += fprintf(fp, "%s\n", callchain_list__sym_name(chain, bf, sizeof(bf), - false)); + ret += fprintf(fp, "%s", + callchain_list__sym_name(chain, bf, + sizeof(bf), + false)); + + if (symbol_conf.show_branchflag_count) + ret += callchain_list_counts__printf_value( + NULL, chain, fp, NULL, 0); + ret += fprintf(fp, "\n"); if (++entries_printed == callchain_param.print_limit) break; diff --git a/tools/perf/util/Build b/tools/perf/util/Build index eb60e613d795..3840e3a87057 100644 --- a/tools/perf/util/Build +++ b/tools/perf/util/Build @@ -87,6 +87,7 @@ libperf-y += help-unknown-cmd.o libperf-y += mem-events.o libperf-y += vsprintf.o libperf-y += drv_configs.o +libperf-y += time-utils.o libperf-$(CONFIG_LIBBPF) += bpf-loader.o libperf-$(CONFIG_BPF_PROLOGUE) += bpf-prologue.o @@ -120,9 +121,13 @@ libperf-y += demangle-rust.o ifdef CONFIG_JITDUMP libperf-$(CONFIG_LIBELF) += jitdump.o libperf-$(CONFIG_LIBELF) += genelf.o -libperf-$(CONFIG_LIBELF) += genelf_debug.o +libperf-$(CONFIG_DWARF) += genelf_debug.o endif +libperf-y += perf-hooks.o + +libperf-$(CONFIG_CXX) += c++/ + CFLAGS_config.o += -DETC_PERFCONFIG="BUILD_STR($(ETC_PERFCONFIG_SQ))" # avoid compiler warnings in 32-bit mode CFLAGS_genelf_debug.o += -Wno-packed diff --git a/tools/perf/util/annotate.c b/tools/perf/util/annotate.c index aeb5a441bd74..ea7e0de4b9c1 100644 --- a/tools/perf/util/annotate.c +++ b/tools/perf/util/annotate.c @@ -18,16 +18,119 @@ #include "annotate.h" #include "evsel.h" #include "block-range.h" +#include "arch/common.h" #include <regex.h> #include <pthread.h> #include <linux/bitops.h> +#include <sys/utsname.h> const char *disassembler_style; const char *objdump_path; static regex_t file_lineno; -static struct ins *ins__find(const char *name); -static int disasm_line__parse(char *line, char **namep, char **rawp); +static struct ins_ops *ins__find(struct arch *arch, const char *name); +static void ins__sort(struct arch *arch); +static int disasm_line__parse(char *line, const char **namep, char **rawp); + +struct arch { + const char *name; + struct ins *instructions; + size_t nr_instructions; + size_t nr_instructions_allocated; + struct ins_ops *(*associate_instruction_ops)(struct arch *arch, const char *name); + bool sorted_instructions; + bool initialized; + void *priv; + int (*init)(struct arch *arch); + struct { + char comment_char; + char skip_functions_char; + } objdump; +}; + +static struct ins_ops call_ops; +static struct ins_ops dec_ops; +static struct ins_ops jump_ops; +static struct ins_ops mov_ops; +static struct ins_ops nop_ops; +static struct ins_ops lock_ops; +static struct ins_ops ret_ops; + +static int arch__grow_instructions(struct arch *arch) +{ + struct ins *new_instructions; + size_t new_nr_allocated; + + if (arch->nr_instructions_allocated == 0 && arch->instructions) + goto grow_from_non_allocated_table; + + new_nr_allocated = arch->nr_instructions_allocated + 128; + new_instructions = realloc(arch->instructions, new_nr_allocated * sizeof(struct ins)); + if (new_instructions == NULL) + return -1; + +out_update_instructions: + arch->instructions = new_instructions; + arch->nr_instructions_allocated = new_nr_allocated; + return 0; + +grow_from_non_allocated_table: + new_nr_allocated = arch->nr_instructions + 128; + new_instructions = calloc(new_nr_allocated, sizeof(struct ins)); + if (new_instructions == NULL) + return -1; + + memcpy(new_instructions, arch->instructions, arch->nr_instructions); + goto out_update_instructions; +} + +static int arch__associate_ins_ops(struct arch* arch, const char *name, struct ins_ops *ops) +{ + struct ins *ins; + + if (arch->nr_instructions == arch->nr_instructions_allocated && + arch__grow_instructions(arch)) + return -1; + + ins = &arch->instructions[arch->nr_instructions]; + ins->name = strdup(name); + if (!ins->name) + return -1; + + ins->ops = ops; + arch->nr_instructions++; + + ins__sort(arch); + return 0; +} + +#include "arch/arm/annotate/instructions.c" +#include "arch/arm64/annotate/instructions.c" +#include "arch/x86/annotate/instructions.c" +#include "arch/powerpc/annotate/instructions.c" + +static struct arch architectures[] = { + { + .name = "arm", + .init = arm__annotate_init, + }, + { + .name = "arm64", + .init = arm64__annotate_init, + }, + { + .name = "x86", + .instructions = x86__instructions, + .nr_instructions = ARRAY_SIZE(x86__instructions), + .objdump = { + .comment_char = '#', + }, + }, + { + .name = "powerpc", + .init = powerpc__annotate_init, + }, +}; static void ins__delete(struct ins_operands *ops) { @@ -54,7 +157,7 @@ int ins__scnprintf(struct ins *ins, char *bf, size_t size, return ins__raw_scnprintf(ins, bf, size, ops); } -static int call__parse(struct ins_operands *ops, struct map *map) +static int call__parse(struct arch *arch, struct ins_operands *ops, struct map *map) { char *endptr, *tok, *name; @@ -66,10 +169,9 @@ static int call__parse(struct ins_operands *ops, struct map *map) name++; -#ifdef __arm__ - if (strchr(name, '+')) + if (arch->objdump.skip_functions_char && + strchr(name, arch->objdump.skip_functions_char)) return -1; -#endif tok = strchr(name, '>'); if (tok == NULL) @@ -118,7 +220,7 @@ bool ins__is_call(const struct ins *ins) return ins->ops == &call_ops; } -static int jump__parse(struct ins_operands *ops, struct map *map __maybe_unused) +static int jump__parse(struct arch *arch __maybe_unused, struct ins_operands *ops, struct map *map __maybe_unused) { const char *s = strchr(ops->raw, '+'); @@ -135,6 +237,9 @@ static int jump__parse(struct ins_operands *ops, struct map *map __maybe_unused) static int jump__scnprintf(struct ins *ins, char *bf, size_t size, struct ins_operands *ops) { + if (!ops->target.addr) + return ins__raw_scnprintf(ins, bf, size, ops); + return scnprintf(bf, size, "%-6.6s %" PRIx64, ins->name, ops->target.offset); } @@ -173,28 +278,22 @@ static int comment__symbol(char *raw, char *comment, u64 *addrp, char **namep) return 0; } -static int lock__parse(struct ins_operands *ops, struct map *map) +static int lock__parse(struct arch *arch, struct ins_operands *ops, struct map *map) { - char *name; - ops->locked.ops = zalloc(sizeof(*ops->locked.ops)); if (ops->locked.ops == NULL) return 0; - if (disasm_line__parse(ops->raw, &name, &ops->locked.ops->raw) < 0) + if (disasm_line__parse(ops->raw, &ops->locked.ins.name, &ops->locked.ops->raw) < 0) goto out_free_ops; - ops->locked.ins = ins__find(name); - free(name); + ops->locked.ins.ops = ins__find(arch, ops->locked.ins.name); - if (ops->locked.ins == NULL) + if (ops->locked.ins.ops == NULL) goto out_free_ops; - if (!ops->locked.ins->ops) - return 0; - - if (ops->locked.ins->ops->parse && - ops->locked.ins->ops->parse(ops->locked.ops, map) < 0) + if (ops->locked.ins.ops->parse && + ops->locked.ins.ops->parse(arch, ops->locked.ops, map) < 0) goto out_free_ops; return 0; @@ -209,19 +308,19 @@ static int lock__scnprintf(struct ins *ins, char *bf, size_t size, { int printed; - if (ops->locked.ins == NULL) + if (ops->locked.ins.ops == NULL) return ins__raw_scnprintf(ins, bf, size, ops); printed = scnprintf(bf, size, "%-6.6s ", ins->name); - return printed + ins__scnprintf(ops->locked.ins, bf + printed, + return printed + ins__scnprintf(&ops->locked.ins, bf + printed, size - printed, ops->locked.ops); } static void lock__delete(struct ins_operands *ops) { - struct ins *ins = ops->locked.ins; + struct ins *ins = &ops->locked.ins; - if (ins && ins->ops->free) + if (ins->ops && ins->ops->free) ins->ops->free(ops->locked.ops); else ins__delete(ops->locked.ops); @@ -237,7 +336,7 @@ static struct ins_ops lock_ops = { .scnprintf = lock__scnprintf, }; -static int mov__parse(struct ins_operands *ops, struct map *map __maybe_unused) +static int mov__parse(struct arch *arch, struct ins_operands *ops, struct map *map __maybe_unused) { char *s = strchr(ops->raw, ','), *target, *comment, prev; @@ -252,11 +351,7 @@ static int mov__parse(struct ins_operands *ops, struct map *map __maybe_unused) return -1; target = ++s; -#ifdef __arm__ - comment = strchr(s, ';'); -#else - comment = strchr(s, '#'); -#endif + comment = strchr(s, arch->objdump.comment_char); if (comment != NULL) s = comment - 1; @@ -304,7 +399,7 @@ static struct ins_ops mov_ops = { .scnprintf = mov__scnprintf, }; -static int dec__parse(struct ins_operands *ops, struct map *map __maybe_unused) +static int dec__parse(struct arch *arch __maybe_unused, struct ins_operands *ops, struct map *map __maybe_unused) { char *target, *comment, *s, prev; @@ -321,7 +416,7 @@ static int dec__parse(struct ins_operands *ops, struct map *map __maybe_unused) if (ops->target.raw == NULL) return -1; - comment = strchr(s, '#'); + comment = strchr(s, arch->objdump.comment_char); if (comment == NULL) return 0; @@ -364,99 +459,6 @@ bool ins__is_ret(const struct ins *ins) return ins->ops == &ret_ops; } -static struct ins instructions[] = { - { .name = "add", .ops = &mov_ops, }, - { .name = "addl", .ops = &mov_ops, }, - { .name = "addq", .ops = &mov_ops, }, - { .name = "addw", .ops = &mov_ops, }, - { .name = "and", .ops = &mov_ops, }, -#ifdef __arm__ - { .name = "b", .ops = &jump_ops, }, // might also be a call - { .name = "bcc", .ops = &jump_ops, }, - { .name = "bcs", .ops = &jump_ops, }, - { .name = "beq", .ops = &jump_ops, }, - { .name = "bge", .ops = &jump_ops, }, - { .name = "bgt", .ops = &jump_ops, }, - { .name = "bhi", .ops = &jump_ops, }, - { .name = "bl", .ops = &call_ops, }, - { .name = "bls", .ops = &jump_ops, }, - { .name = "blt", .ops = &jump_ops, }, - { .name = "blx", .ops = &call_ops, }, - { .name = "bne", .ops = &jump_ops, }, -#endif - { .name = "bts", .ops = &mov_ops, }, - { .name = "call", .ops = &call_ops, }, - { .name = "callq", .ops = &call_ops, }, - { .name = "cmp", .ops = &mov_ops, }, - { .name = "cmpb", .ops = &mov_ops, }, - { .name = "cmpl", .ops = &mov_ops, }, - { .name = "cmpq", .ops = &mov_ops, }, - { .name = "cmpw", .ops = &mov_ops, }, - { .name = "cmpxch", .ops = &mov_ops, }, - { .name = "dec", .ops = &dec_ops, }, - { .name = "decl", .ops = &dec_ops, }, - { .name = "imul", .ops = &mov_ops, }, - { .name = "inc", .ops = &dec_ops, }, - { .name = "incl", .ops = &dec_ops, }, - { .name = "ja", .ops = &jump_ops, }, - { .name = "jae", .ops = &jump_ops, }, - { .name = "jb", .ops = &jump_ops, }, - { .name = "jbe", .ops = &jump_ops, }, - { .name = "jc", .ops = &jump_ops, }, - { .name = "jcxz", .ops = &jump_ops, }, - { .name = "je", .ops = &jump_ops, }, - { .name = "jecxz", .ops = &jump_ops, }, - { .name = "jg", .ops = &jump_ops, }, - { .name = "jge", .ops = &jump_ops, }, - { .name = "jl", .ops = &jump_ops, }, - { .name = "jle", .ops = &jump_ops, }, - { .name = "jmp", .ops = &jump_ops, }, - { .name = "jmpq", .ops = &jump_ops, }, - { .name = "jna", .ops = &jump_ops, }, - { .name = "jnae", .ops = &jump_ops, }, - { .name = "jnb", .ops = &jump_ops, }, - { .name = "jnbe", .ops = &jump_ops, }, - { .name = "jnc", .ops = &jump_ops, }, - { .name = "jne", .ops = &jump_ops, }, - { .name = "jng", .ops = &jump_ops, }, - { .name = "jnge", .ops = &jump_ops, }, - { .name = "jnl", .ops = &jump_ops, }, - { .name = "jnle", .ops = &jump_ops, }, - { .name = "jno", .ops = &jump_ops, }, - { .name = "jnp", .ops = &jump_ops, }, - { .name = "jns", .ops = &jump_ops, }, - { .name = "jnz", .ops = &jump_ops, }, - { .name = "jo", .ops = &jump_ops, }, - { .name = "jp", .ops = &jump_ops, }, - { .name = "jpe", .ops = &jump_ops, }, - { .name = "jpo", .ops = &jump_ops, }, - { .name = "jrcxz", .ops = &jump_ops, }, - { .name = "js", .ops = &jump_ops, }, - { .name = "jz", .ops = &jump_ops, }, - { .name = "lea", .ops = &mov_ops, }, - { .name = "lock", .ops = &lock_ops, }, - { .name = "mov", .ops = &mov_ops, }, - { .name = "movb", .ops = &mov_ops, }, - { .name = "movdqa",.ops = &mov_ops, }, - { .name = "movl", .ops = &mov_ops, }, - { .name = "movq", .ops = &mov_ops, }, - { .name = "movslq", .ops = &mov_ops, }, - { .name = "movzbl", .ops = &mov_ops, }, - { .name = "movzwl", .ops = &mov_ops, }, - { .name = "nop", .ops = &nop_ops, }, - { .name = "nopl", .ops = &nop_ops, }, - { .name = "nopw", .ops = &nop_ops, }, - { .name = "or", .ops = &mov_ops, }, - { .name = "orl", .ops = &mov_ops, }, - { .name = "test", .ops = &mov_ops, }, - { .name = "testb", .ops = &mov_ops, }, - { .name = "testl", .ops = &mov_ops, }, - { .name = "xadd", .ops = &mov_ops, }, - { .name = "xbeginl", .ops = &jump_ops, }, - { .name = "xbeginq", .ops = &jump_ops, }, - { .name = "retq", .ops = &ret_ops, }, -}; - static int ins__key_cmp(const void *name, const void *insp) { const struct ins *ins = insp; @@ -472,24 +474,70 @@ static int ins__cmp(const void *a, const void *b) return strcmp(ia->name, ib->name); } -static void ins__sort(void) +static void ins__sort(struct arch *arch) +{ + const int nmemb = arch->nr_instructions; + + qsort(arch->instructions, nmemb, sizeof(struct ins), ins__cmp); +} + +static struct ins_ops *__ins__find(struct arch *arch, const char *name) +{ + struct ins *ins; + const int nmemb = arch->nr_instructions; + + if (!arch->sorted_instructions) { + ins__sort(arch); + arch->sorted_instructions = true; + } + + ins = bsearch(name, arch->instructions, nmemb, sizeof(struct ins), ins__key_cmp); + return ins ? ins->ops : NULL; +} + +static struct ins_ops *ins__find(struct arch *arch, const char *name) +{ + struct ins_ops *ops = __ins__find(arch, name); + + if (!ops && arch->associate_instruction_ops) + ops = arch->associate_instruction_ops(arch, name); + + return ops; +} + +static int arch__key_cmp(const void *name, const void *archp) +{ + const struct arch *arch = archp; + + return strcmp(name, arch->name); +} + +static int arch__cmp(const void *a, const void *b) { - const int nmemb = ARRAY_SIZE(instructions); + const struct arch *aa = a; + const struct arch *ab = b; - qsort(instructions, nmemb, sizeof(struct ins), ins__cmp); + return strcmp(aa->name, ab->name); } -static struct ins *ins__find(const char *name) +static void arch__sort(void) { - const int nmemb = ARRAY_SIZE(instructions); + const int nmemb = ARRAY_SIZE(architectures); + + qsort(architectures, nmemb, sizeof(struct arch), arch__cmp); +} + +static struct arch *arch__find(const char *name) +{ + const int nmemb = ARRAY_SIZE(architectures); static bool sorted; if (!sorted) { - ins__sort(); + arch__sort(); sorted = true; } - return bsearch(name, instructions, nmemb, sizeof(struct ins), ins__key_cmp); + return bsearch(name, architectures, nmemb, sizeof(struct arch), arch__key_cmp); } int symbol__alloc_hist(struct symbol *sym) @@ -709,21 +757,18 @@ int hist_entry__inc_addr_samples(struct hist_entry *he, int evidx, u64 ip) return symbol__inc_addr_samples(he->ms.sym, he->ms.map, evidx, ip); } -static void disasm_line__init_ins(struct disasm_line *dl, struct map *map) +static void disasm_line__init_ins(struct disasm_line *dl, struct arch *arch, struct map *map) { - dl->ins = ins__find(dl->name); + dl->ins.ops = ins__find(arch, dl->ins.name); - if (dl->ins == NULL) + if (!dl->ins.ops) return; - if (!dl->ins->ops) - return; - - if (dl->ins->ops->parse && dl->ins->ops->parse(&dl->ops, map) < 0) - dl->ins = NULL; + if (dl->ins.ops->parse && dl->ins.ops->parse(arch, &dl->ops, map) < 0) + dl->ins.ops = NULL; } -static int disasm_line__parse(char *line, char **namep, char **rawp) +static int disasm_line__parse(char *line, const char **namep, char **rawp) { char *name = line, tmp; @@ -756,12 +801,14 @@ static int disasm_line__parse(char *line, char **namep, char **rawp) return 0; out_free_name: - zfree(namep); + free((void *)namep); + *namep = NULL; return -1; } static struct disasm_line *disasm_line__new(s64 offset, char *line, size_t privsize, int line_nr, + struct arch *arch, struct map *map) { struct disasm_line *dl = zalloc(sizeof(*dl) + privsize); @@ -774,10 +821,10 @@ static struct disasm_line *disasm_line__new(s64 offset, char *line, goto out_delete; if (offset != -1) { - if (disasm_line__parse(dl->line, &dl->name, &dl->ops.raw) < 0) + if (disasm_line__parse(dl->line, &dl->ins.name, &dl->ops.raw) < 0) goto out_free_line; - disasm_line__init_ins(dl, map); + disasm_line__init_ins(dl, arch, map); } } @@ -793,20 +840,21 @@ out_delete: void disasm_line__free(struct disasm_line *dl) { zfree(&dl->line); - zfree(&dl->name); - if (dl->ins && dl->ins->ops->free) - dl->ins->ops->free(&dl->ops); + if (dl->ins.ops && dl->ins.ops->free) + dl->ins.ops->free(&dl->ops); else ins__delete(&dl->ops); + free((void *)dl->ins.name); + dl->ins.name = NULL; free(dl); } int disasm_line__scnprintf(struct disasm_line *dl, char *bf, size_t size, bool raw) { - if (raw || !dl->ins) - return scnprintf(bf, size, "%-6.6s %s", dl->name, dl->ops.raw); + if (raw || !dl->ins.ops) + return scnprintf(bf, size, "%-6.6s %s", dl->ins.name, dl->ops.raw); - return ins__scnprintf(dl->ins, bf, size, &dl->ops); + return ins__scnprintf(&dl->ins, bf, size, &dl->ops); } static void disasm__add(struct list_head *head, struct disasm_line *line) @@ -1087,6 +1135,7 @@ static int disasm_line__print(struct disasm_line *dl, struct symbol *sym, u64 st * The ops.raw part will be parsed further according to type of the instruction. */ static int symbol__parse_objdump_line(struct symbol *sym, struct map *map, + struct arch *arch, FILE *file, size_t privsize, int *line_nr) { @@ -1149,7 +1198,7 @@ static int symbol__parse_objdump_line(struct symbol *sym, struct map *map, parsed_line = tmp2 + 1; } - dl = disasm_line__new(offset, parsed_line, privsize, *line_nr, map); + dl = disasm_line__new(offset, parsed_line, privsize, *line_nr, arch, map); free(line); (*line_nr)++; @@ -1161,7 +1210,7 @@ static int symbol__parse_objdump_line(struct symbol *sym, struct map *map, map__rip_2objdump(map, sym->start); /* kcore has no symbols, so add the call target name */ - if (dl->ins && ins__is_call(dl->ins) && !dl->ops.target.name) { + if (dl->ins.ops && ins__is_call(&dl->ins) && !dl->ops.target.name) { struct addr_map_symbol target = { .map = map, .addr = dl->ops.target.addr, @@ -1191,8 +1240,8 @@ static void delete_last_nop(struct symbol *sym) while (!list_empty(list)) { dl = list_entry(list->prev, struct disasm_line, node); - if (dl->ins && dl->ins->ops) { - if (dl->ins->ops != &nop_ops) + if (dl->ins.ops) { + if (dl->ins.ops != &nop_ops) return; } else { if (!strstr(dl->line, " nop ") && @@ -1280,10 +1329,23 @@ fallback: return 0; } -int symbol__disassemble(struct symbol *sym, struct map *map, size_t privsize) +static const char *annotate__norm_arch(const char *arch_name) +{ + struct utsname uts; + + if (!arch_name) { /* Assume we are annotating locally. */ + if (uname(&uts) < 0) + return NULL; + arch_name = uts.machine; + } + return normalize_arch((char *)arch_name); +} + +int symbol__disassemble(struct symbol *sym, struct map *map, const char *arch_name, size_t privsize) { struct dso *dso = map->dso; char command[PATH_MAX * 2]; + struct arch *arch = NULL; FILE *file; char symfs_filename[PATH_MAX]; struct kcore_extract kce; @@ -1297,6 +1359,22 @@ int symbol__disassemble(struct symbol *sym, struct map *map, size_t privsize) if (err) return err; + arch_name = annotate__norm_arch(arch_name); + if (!arch_name) + return -1; + + arch = arch__find(arch_name); + if (arch == NULL) + return -ENOTSUP; + + if (arch->init) { + err = arch->init(arch); + if (err) { + pr_err("%s: failed to initialize %s arch priv area\n", __func__, arch->name); + return err; + } + } + pr_debug("%s: filename=%s, sym=%s, start=%#" PRIx64 ", end=%#" PRIx64 "\n", __func__, symfs_filename, sym->name, map->unmap_ip(map, sym->start), map->unmap_ip(map, sym->end)); @@ -1395,7 +1473,7 @@ int symbol__disassemble(struct symbol *sym, struct map *map, size_t privsize) nline = 0; while (!feof(file)) { - if (symbol__parse_objdump_line(sym, map, file, privsize, + if (symbol__parse_objdump_line(sym, map, arch, file, privsize, &lineno) < 0) break; nline++; @@ -1764,7 +1842,7 @@ static size_t disasm_line__fprintf(struct disasm_line *dl, FILE *fp) if (dl->offset == -1) return fprintf(fp, "%s\n", dl->line); - printed = fprintf(fp, "%#" PRIx64 " %s", dl->offset, dl->name); + printed = fprintf(fp, "%#" PRIx64 " %s", dl->offset, dl->ins.name); if (dl->ops.raw[0] != '\0') { printed += fprintf(fp, "%.*s %s\n", 6 - (int)printed, " ", @@ -1793,7 +1871,7 @@ int symbol__tty_annotate(struct symbol *sym, struct map *map, struct rb_root source_line = RB_ROOT; u64 len; - if (symbol__disassemble(sym, map, 0) < 0) + if (symbol__disassemble(sym, map, perf_evsel__env_arch(evsel), 0) < 0) return -1; len = symbol__size(sym); diff --git a/tools/perf/util/annotate.h b/tools/perf/util/annotate.h index 5bbcec173b82..87e4cadc5d27 100644 --- a/tools/perf/util/annotate.h +++ b/tools/perf/util/annotate.h @@ -11,7 +11,12 @@ #include <linux/rbtree.h> #include <pthread.h> -struct ins; +struct ins_ops; + +struct ins { + const char *name; + struct ins_ops *ops; +}; struct ins_operands { char *raw; @@ -28,24 +33,21 @@ struct ins_operands { u64 addr; } source; struct { - struct ins *ins; + struct ins ins; struct ins_operands *ops; } locked; }; }; +struct arch; + struct ins_ops { void (*free)(struct ins_operands *ops); - int (*parse)(struct ins_operands *ops, struct map *map); + int (*parse)(struct arch *arch, struct ins_operands *ops, struct map *map); int (*scnprintf)(struct ins *ins, char *bf, size_t size, struct ins_operands *ops); }; -struct ins { - const char *name; - struct ins_ops *ops; -}; - bool ins__is_jump(const struct ins *ins); bool ins__is_call(const struct ins *ins); bool ins__is_ret(const struct ins *ins); @@ -57,8 +59,7 @@ struct disasm_line { struct list_head node; s64 offset; char *line; - char *name; - struct ins *ins; + struct ins ins; int line_nr; float ipc; u64 cycles; @@ -156,7 +157,7 @@ int hist_entry__inc_addr_samples(struct hist_entry *he, int evidx, u64 addr); int symbol__alloc_hist(struct symbol *sym); void symbol__annotate_zero_histograms(struct symbol *sym); -int symbol__disassemble(struct symbol *sym, struct map *map, size_t privsize); +int symbol__disassemble(struct symbol *sym, struct map *map, const char *arch_name, size_t privsize); enum symbol_disassemble_errno { SYMBOL_ANNOTATE_ERRNO__SUCCESS = 0, diff --git a/tools/perf/util/bpf-loader.c b/tools/perf/util/bpf-loader.c index 2b2c9b82f5ab..36c861103291 100644 --- a/tools/perf/util/bpf-loader.c +++ b/tools/perf/util/bpf-loader.c @@ -14,11 +14,11 @@ #include "debug.h" #include "bpf-loader.h" #include "bpf-prologue.h" -#include "llvm-utils.h" #include "probe-event.h" #include "probe-finder.h" // for MAX_PROBES #include "parse-events.h" #include "llvm-utils.h" +#include "c++/clang-c.h" #define DEFINE_PRINT_FN(name, level) \ static int libbpf_##name(const char *fmt, ...) \ @@ -86,10 +86,21 @@ struct bpf_object *bpf__prepare_load(const char *filename, bool source) void *obj_buf; size_t obj_buf_sz; - err = llvm__compile_bpf(filename, &obj_buf, &obj_buf_sz); - if (err) - return ERR_PTR(-BPF_LOADER_ERRNO__COMPILE); + perf_clang__init(); + err = perf_clang__compile_bpf(filename, &obj_buf, &obj_buf_sz); + perf_clang__cleanup(); + if (err) { + pr_warning("bpf: builtin compilation failed: %d, try external compiler\n", err); + err = llvm__compile_bpf(filename, &obj_buf, &obj_buf_sz); + if (err) + return ERR_PTR(-BPF_LOADER_ERRNO__COMPILE); + } else + pr_debug("bpf: successfull builtin compilation\n"); obj = bpf_object__open_buffer(obj_buf, obj_buf_sz, filename); + + if (!IS_ERR(obj) && llvm_param.dump_obj) + llvm__dump_obj(filename, obj_buf, obj_buf_sz); + free(obj_buf); } else obj = bpf_object__open(filename); @@ -241,7 +252,7 @@ parse_prog_config_kvpair(const char *config_str, struct perf_probe_event *pev) int err = 0; if (!text) { - pr_debug("No enough memory: dup config_str failed\n"); + pr_debug("Not enough memory: dup config_str failed\n"); return ERR_PTR(-ENOMEM); } @@ -531,7 +542,7 @@ static int map_prologue(struct perf_probe_event *pev, int *mapping, ptevs = malloc(array_sz); if (!ptevs) { - pr_debug("No enough memory: alloc ptevs failed\n"); + pr_debug("Not enough memory: alloc ptevs failed\n"); return -ENOMEM; } @@ -604,13 +615,13 @@ static int hook_load_preprocessor(struct bpf_program *prog) priv->need_prologue = true; priv->insns_buf = malloc(sizeof(struct bpf_insn) * BPF_MAXINSNS); if (!priv->insns_buf) { - pr_debug("No enough memory: alloc insns_buf failed\n"); + pr_debug("Not enough memory: alloc insns_buf failed\n"); return -ENOMEM; } priv->type_mapping = malloc(sizeof(int) * pev->ntevs); if (!priv->type_mapping) { - pr_debug("No enough memory: alloc type_mapping failed\n"); + pr_debug("Not enough memory: alloc type_mapping failed\n"); return -ENOMEM; } memset(priv->type_mapping, -1, @@ -864,7 +875,7 @@ bpf_map_op_setkey(struct bpf_map_op *op, struct parse_events_term *term) op->k.array.ranges = memdup(term->array.ranges, memsz); if (!op->k.array.ranges) { - pr_debug("No enough memory to alloc indices for map\n"); + pr_debug("Not enough memory to alloc indices for map\n"); return -ENOMEM; } op->key_type = BPF_MAP_KEY_RANGES; @@ -929,7 +940,7 @@ bpf_map_priv__clone(struct bpf_map_priv *priv) newpriv = zalloc(sizeof(*newpriv)); if (!newpriv) { - pr_debug("No enough memory to alloc map private\n"); + pr_debug("Not enough memory to alloc map private\n"); return NULL; } INIT_LIST_HEAD(&newpriv->ops_list); @@ -960,7 +971,7 @@ bpf_map__add_op(struct bpf_map *map, struct bpf_map_op *op) if (!priv) { priv = zalloc(sizeof(*priv)); if (!priv) { - pr_debug("No enough memory to alloc map private\n"); + pr_debug("Not enough memory to alloc map private\n"); return -ENOMEM; } INIT_LIST_HEAD(&priv->ops_list); diff --git a/tools/perf/util/c++/Build b/tools/perf/util/c++/Build new file mode 100644 index 000000000000..988fef1b11d7 --- /dev/null +++ b/tools/perf/util/c++/Build @@ -0,0 +1,2 @@ +libperf-$(CONFIG_CLANGLLVM) += clang.o +libperf-$(CONFIG_CLANGLLVM) += clang-test.o diff --git a/tools/perf/util/c++/clang-c.h b/tools/perf/util/c++/clang-c.h new file mode 100644 index 000000000000..0eadd792ab1f --- /dev/null +++ b/tools/perf/util/c++/clang-c.h @@ -0,0 +1,43 @@ +#ifndef PERF_UTIL_CLANG_C_H +#define PERF_UTIL_CLANG_C_H + +#include <stddef.h> /* for size_t */ +#include <util-cxx.h> /* for __maybe_unused */ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef HAVE_LIBCLANGLLVM_SUPPORT +extern void perf_clang__init(void); +extern void perf_clang__cleanup(void); + +extern int test__clang_to_IR(void); +extern int test__clang_to_obj(void); + +extern int perf_clang__compile_bpf(const char *filename, + void **p_obj_buf, + size_t *p_obj_buf_sz); +#else + + +static inline void perf_clang__init(void) { } +static inline void perf_clang__cleanup(void) { } + +static inline int test__clang_to_IR(void) { return -1; } +static inline int test__clang_to_obj(void) { return -1;} + +static inline int +perf_clang__compile_bpf(const char *filename __maybe_unused, + void **p_obj_buf __maybe_unused, + size_t *p_obj_buf_sz __maybe_unused) +{ + return -ENOTSUP; +} + +#endif + +#ifdef __cplusplus +} +#endif +#endif diff --git a/tools/perf/util/c++/clang-test.cpp b/tools/perf/util/c++/clang-test.cpp new file mode 100644 index 000000000000..9b11e8c82798 --- /dev/null +++ b/tools/perf/util/c++/clang-test.cpp @@ -0,0 +1,62 @@ +#include "clang.h" +#include "clang-c.h" +#include "llvm/IR/Function.h" +#include "llvm/IR/LLVMContext.h" + +#include <util-cxx.h> +#include <tests/llvm.h> +#include <string> + +class perf_clang_scope { +public: + explicit perf_clang_scope() {perf_clang__init();} + ~perf_clang_scope() {perf_clang__cleanup();} +}; + +static std::unique_ptr<llvm::Module> +__test__clang_to_IR(void) +{ + unsigned int kernel_version; + + if (fetch_kernel_version(&kernel_version, NULL, 0)) + return std::unique_ptr<llvm::Module>(nullptr); + + std::string cflag_kver("-DLINUX_VERSION_CODE=" + + std::to_string(kernel_version)); + + std::unique_ptr<llvm::Module> M = + perf::getModuleFromSource({cflag_kver.c_str()}, + "perf-test.c", + test_llvm__bpf_base_prog); + return M; +} + +extern "C" { +int test__clang_to_IR(void) +{ + perf_clang_scope _scope; + + auto M = __test__clang_to_IR(); + if (!M) + return -1; + for (llvm::Function& F : *M) + if (F.getName() == "bpf_func__SyS_epoll_wait") + return 0; + return -1; +} + +int test__clang_to_obj(void) +{ + perf_clang_scope _scope; + + auto M = __test__clang_to_IR(); + if (!M) + return -1; + + auto Buffer = perf::getBPFObjectFromModule(&*M); + if (!Buffer) + return -1; + return 0; +} + +} diff --git a/tools/perf/util/c++/clang.cpp b/tools/perf/util/c++/clang.cpp new file mode 100644 index 000000000000..1e974152cac2 --- /dev/null +++ b/tools/perf/util/c++/clang.cpp @@ -0,0 +1,195 @@ +/* + * llvm C frontend for perf. Support dynamically compile C file + * + * Inspired by clang example code: + * http://llvm.org/svn/llvm-project/cfe/trunk/examples/clang-interpreter/main.cpp + * + * Copyright (C) 2016 Wang Nan <wangnan0@huawei.com> + * Copyright (C) 2016 Huawei Inc. + */ + +#include "clang/CodeGen/CodeGenAction.h" +#include "clang/Frontend/CompilerInvocation.h" +#include "clang/Frontend/CompilerInstance.h" +#include "clang/Frontend/TextDiagnosticPrinter.h" +#include "clang/Tooling/Tooling.h" +#include "llvm/IR/LegacyPassManager.h" +#include "llvm/IR/Module.h" +#include "llvm/Option/Option.h" +#include "llvm/Support/FileSystem.h" +#include "llvm/Support/ManagedStatic.h" +#include "llvm/Support/TargetRegistry.h" +#include "llvm/Support/TargetSelect.h" +#include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetOptions.h" +#include <memory> + +#include "clang.h" +#include "clang-c.h" + +namespace perf { + +static std::unique_ptr<llvm::LLVMContext> LLVMCtx; + +using namespace clang; + +static CompilerInvocation * +createCompilerInvocation(llvm::opt::ArgStringList CFlags, StringRef& Path, + DiagnosticsEngine& Diags) +{ + llvm::opt::ArgStringList CCArgs { + "-cc1", + "-triple", "bpf-pc-linux", + "-fsyntax-only", + "-ferror-limit", "19", + "-fmessage-length", "127", + "-O2", + "-nostdsysteminc", + "-nobuiltininc", + "-vectorize-loops", + "-vectorize-slp", + "-Wno-unused-value", + "-Wno-pointer-sign", + "-x", "c"}; + + CCArgs.append(CFlags.begin(), CFlags.end()); + CompilerInvocation *CI = tooling::newInvocation(&Diags, CCArgs); + + FrontendOptions& Opts = CI->getFrontendOpts(); + Opts.Inputs.clear(); + Opts.Inputs.emplace_back(Path, IK_C); + return CI; +} + +static std::unique_ptr<llvm::Module> +getModuleFromSource(llvm::opt::ArgStringList CFlags, + StringRef Path, IntrusiveRefCntPtr<vfs::FileSystem> VFS) +{ + CompilerInstance Clang; + Clang.createDiagnostics(); + + Clang.setVirtualFileSystem(&*VFS); + + IntrusiveRefCntPtr<CompilerInvocation> CI = + createCompilerInvocation(std::move(CFlags), Path, + Clang.getDiagnostics()); + Clang.setInvocation(&*CI); + + std::unique_ptr<CodeGenAction> Act(new EmitLLVMOnlyAction(&*LLVMCtx)); + if (!Clang.ExecuteAction(*Act)) + return std::unique_ptr<llvm::Module>(nullptr); + + return Act->takeModule(); +} + +std::unique_ptr<llvm::Module> +getModuleFromSource(llvm::opt::ArgStringList CFlags, + StringRef Name, StringRef Content) +{ + using namespace vfs; + + llvm::IntrusiveRefCntPtr<OverlayFileSystem> OverlayFS( + new OverlayFileSystem(getRealFileSystem())); + llvm::IntrusiveRefCntPtr<InMemoryFileSystem> MemFS( + new InMemoryFileSystem(true)); + + /* + * pushOverlay helps setting working dir for MemFS. Must call + * before addFile. + */ + OverlayFS->pushOverlay(MemFS); + MemFS->addFile(Twine(Name), 0, llvm::MemoryBuffer::getMemBuffer(Content)); + + return getModuleFromSource(std::move(CFlags), Name, OverlayFS); +} + +std::unique_ptr<llvm::Module> +getModuleFromSource(llvm::opt::ArgStringList CFlags, StringRef Path) +{ + IntrusiveRefCntPtr<vfs::FileSystem> VFS(vfs::getRealFileSystem()); + return getModuleFromSource(std::move(CFlags), Path, VFS); +} + +std::unique_ptr<llvm::SmallVectorImpl<char>> +getBPFObjectFromModule(llvm::Module *Module) +{ + using namespace llvm; + + std::string TargetTriple("bpf-pc-linux"); + std::string Error; + const Target* Target = TargetRegistry::lookupTarget(TargetTriple, Error); + if (!Target) { + llvm::errs() << Error; + return std::unique_ptr<llvm::SmallVectorImpl<char>>(nullptr); + } + + llvm::TargetOptions Opt; + TargetMachine *TargetMachine = + Target->createTargetMachine(TargetTriple, + "generic", "", + Opt, Reloc::Static); + + Module->setDataLayout(TargetMachine->createDataLayout()); + Module->setTargetTriple(TargetTriple); + + std::unique_ptr<SmallVectorImpl<char>> Buffer(new SmallVector<char, 0>()); + raw_svector_ostream ostream(*Buffer); + + legacy::PassManager PM; + if (TargetMachine->addPassesToEmitFile(PM, ostream, + TargetMachine::CGFT_ObjectFile)) { + llvm::errs() << "TargetMachine can't emit a file of this type\n"; + return std::unique_ptr<llvm::SmallVectorImpl<char>>(nullptr);; + } + PM.run(*Module); + + return std::move(Buffer); +} + +} + +extern "C" { +void perf_clang__init(void) +{ + perf::LLVMCtx.reset(new llvm::LLVMContext()); + LLVMInitializeBPFTargetInfo(); + LLVMInitializeBPFTarget(); + LLVMInitializeBPFTargetMC(); + LLVMInitializeBPFAsmPrinter(); +} + +void perf_clang__cleanup(void) +{ + perf::LLVMCtx.reset(nullptr); + llvm::llvm_shutdown(); +} + +int perf_clang__compile_bpf(const char *filename, + void **p_obj_buf, + size_t *p_obj_buf_sz) +{ + using namespace perf; + + if (!p_obj_buf || !p_obj_buf_sz) + return -EINVAL; + + llvm::opt::ArgStringList CFlags; + auto M = getModuleFromSource(std::move(CFlags), filename); + if (!M) + return -EINVAL; + auto O = getBPFObjectFromModule(&*M); + if (!O) + return -EINVAL; + + size_t size = O->size_in_bytes(); + void *buffer; + + buffer = malloc(size); + if (!buffer) + return -ENOMEM; + memcpy(buffer, O->data(), size); + *p_obj_buf = buffer; + *p_obj_buf_sz = size; + return 0; +} +} diff --git a/tools/perf/util/c++/clang.h b/tools/perf/util/c++/clang.h new file mode 100644 index 000000000000..dd8b0427550d --- /dev/null +++ b/tools/perf/util/c++/clang.h @@ -0,0 +1,26 @@ +#ifndef PERF_UTIL_CLANG_H +#define PERF_UTIL_CLANG_H + +#include "llvm/ADT/StringRef.h" +#include "llvm/IR/LLVMContext.h" +#include "llvm/IR/Module.h" +#include "llvm/Option/Option.h" +#include <memory> + +namespace perf { + +using namespace llvm; + +std::unique_ptr<Module> +getModuleFromSource(opt::ArgStringList CFlags, + StringRef Name, StringRef Content); + +std::unique_ptr<Module> +getModuleFromSource(opt::ArgStringList CFlags, + StringRef Path); + +std::unique_ptr<llvm::SmallVectorImpl<char>> +getBPFObjectFromModule(llvm::Module *Module); + +} +#endif diff --git a/tools/perf/util/callchain.c b/tools/perf/util/callchain.c index 07fd30bc2f81..42922512c1c6 100644 --- a/tools/perf/util/callchain.c +++ b/tools/perf/util/callchain.c @@ -193,7 +193,6 @@ int perf_callchain_config(const char *var, const char *value) if (!strcmp(var, "record-mode")) return parse_callchain_record_opt(value, &callchain_param); -#ifdef HAVE_DWARF_UNWIND_SUPPORT if (!strcmp(var, "dump-size")) { unsigned long size = 0; int ret; @@ -203,7 +202,6 @@ int perf_callchain_config(const char *var, const char *value) return ret; } -#endif if (!strcmp(var, "print-type")) return parse_callchain_mode(value); if (!strcmp(var, "order")) @@ -440,6 +438,21 @@ fill_node(struct callchain_node *node, struct callchain_cursor *cursor) call->ip = cursor_node->ip; call->ms.sym = cursor_node->sym; call->ms.map = cursor_node->map; + + if (cursor_node->branch) { + call->branch_count = 1; + + if (cursor_node->branch_flags.predicted) + call->predicted_count = 1; + + if (cursor_node->branch_flags.abort) + call->abort_count = 1; + + call->cycles_count = cursor_node->branch_flags.cycles; + call->iter_count = cursor_node->nr_loop_iter; + call->samples_count = cursor_node->samples; + } + list_add_tail(&call->list, &node->val); callchain_cursor_advance(cursor); @@ -499,8 +512,23 @@ static enum match_result match_chain(struct callchain_cursor_node *node, right = node->ip; } - if (left == right) + if (left == right) { + if (node->branch) { + cnode->branch_count++; + + if (node->branch_flags.predicted) + cnode->predicted_count++; + + if (node->branch_flags.abort) + cnode->abort_count++; + + cnode->cycles_count += node->branch_flags.cycles; + cnode->iter_count += node->nr_loop_iter; + cnode->samples_count += node->samples; + } + return MATCH_EQ; + } return left > right ? MATCH_GT : MATCH_LT; } @@ -730,7 +758,8 @@ merge_chain_branch(struct callchain_cursor *cursor, list_for_each_entry_safe(list, next_list, &src->val, list) { callchain_cursor_append(cursor, list->ip, - list->ms.map, list->ms.sym); + list->ms.map, list->ms.sym, + false, NULL, 0, 0); list_del(&list->list); free(list); } @@ -767,7 +796,9 @@ int callchain_merge(struct callchain_cursor *cursor, } int callchain_cursor_append(struct callchain_cursor *cursor, - u64 ip, struct map *map, struct symbol *sym) + u64 ip, struct map *map, struct symbol *sym, + bool branch, struct branch_flags *flags, + int nr_loop_iter, int samples) { struct callchain_cursor_node *node = *cursor->last; @@ -782,6 +813,13 @@ int callchain_cursor_append(struct callchain_cursor *cursor, node->ip = ip; node->map = map; node->sym = sym; + node->branch = branch; + node->nr_loop_iter = nr_loop_iter; + node->samples = samples; + + if (flags) + memcpy(&node->branch_flags, flags, + sizeof(struct branch_flags)); cursor->nr++; @@ -939,6 +977,163 @@ int callchain_node__fprintf_value(struct callchain_node *node, return 0; } +static void callchain_counts_value(struct callchain_node *node, + u64 *branch_count, u64 *predicted_count, + u64 *abort_count, u64 *cycles_count) +{ + struct callchain_list *clist; + + list_for_each_entry(clist, &node->val, list) { + if (branch_count) + *branch_count += clist->branch_count; + + if (predicted_count) + *predicted_count += clist->predicted_count; + + if (abort_count) + *abort_count += clist->abort_count; + + if (cycles_count) + *cycles_count += clist->cycles_count; + } +} + +static int callchain_node_branch_counts_cumul(struct callchain_node *node, + u64 *branch_count, + u64 *predicted_count, + u64 *abort_count, + u64 *cycles_count) +{ + struct callchain_node *child; + struct rb_node *n; + + n = rb_first(&node->rb_root_in); + while (n) { + child = rb_entry(n, struct callchain_node, rb_node_in); + n = rb_next(n); + + callchain_node_branch_counts_cumul(child, branch_count, + predicted_count, + abort_count, + cycles_count); + + callchain_counts_value(child, branch_count, + predicted_count, abort_count, + cycles_count); + } + + return 0; +} + +int callchain_branch_counts(struct callchain_root *root, + u64 *branch_count, u64 *predicted_count, + u64 *abort_count, u64 *cycles_count) +{ + if (branch_count) + *branch_count = 0; + + if (predicted_count) + *predicted_count = 0; + + if (abort_count) + *abort_count = 0; + + if (cycles_count) + *cycles_count = 0; + + return callchain_node_branch_counts_cumul(&root->node, + branch_count, + predicted_count, + abort_count, + cycles_count); +} + +static int callchain_counts_printf(FILE *fp, char *bf, int bfsize, + u64 branch_count, u64 predicted_count, + u64 abort_count, u64 cycles_count, + u64 iter_count, u64 samples_count) +{ + double predicted_percent = 0.0; + const char *null_str = ""; + char iter_str[32]; + char *str; + u64 cycles = 0; + + if (branch_count == 0) { + if (fp) + return fprintf(fp, " (calltrace)"); + + return scnprintf(bf, bfsize, " (calltrace)"); + } + + if (iter_count && samples_count) { + scnprintf(iter_str, sizeof(iter_str), + ", iterations:%" PRId64 "", + iter_count / samples_count); + str = iter_str; + } else + str = (char *)null_str; + + predicted_percent = predicted_count * 100.0 / branch_count; + cycles = cycles_count / branch_count; + + if ((predicted_percent >= 100.0) && (abort_count == 0)) { + if (fp) + return fprintf(fp, " (cycles:%" PRId64 "%s)", + cycles, str); + + return scnprintf(bf, bfsize, " (cycles:%" PRId64 "%s)", + cycles, str); + } + + if ((predicted_percent < 100.0) && (abort_count == 0)) { + if (fp) + return fprintf(fp, + " (predicted:%.1f%%, cycles:%" PRId64 "%s)", + predicted_percent, cycles, str); + + return scnprintf(bf, bfsize, + " (predicted:%.1f%%, cycles:%" PRId64 "%s)", + predicted_percent, cycles, str); + } + + if (fp) + return fprintf(fp, + " (predicted:%.1f%%, abort:%" PRId64 ", cycles:%" PRId64 "%s)", + predicted_percent, abort_count, cycles, str); + + return scnprintf(bf, bfsize, + " (predicted:%.1f%%, abort:%" PRId64 ", cycles:%" PRId64 "%s)", + predicted_percent, abort_count, cycles, str); +} + +int callchain_list_counts__printf_value(struct callchain_node *node, + struct callchain_list *clist, + FILE *fp, char *bf, int bfsize) +{ + u64 branch_count, predicted_count; + u64 abort_count, cycles_count; + u64 iter_count = 0, samples_count = 0; + + branch_count = clist->branch_count; + predicted_count = clist->predicted_count; + abort_count = clist->abort_count; + cycles_count = clist->cycles_count; + + if (node) { + struct callchain_list *call; + + list_for_each_entry(call, &node->val, list) { + iter_count += call->iter_count; + samples_count += call->samples_count; + } + } + + return callchain_counts_printf(fp, bf, bfsize, branch_count, + predicted_count, abort_count, + cycles_count, iter_count, samples_count); +} + static void free_callchain_node(struct callchain_node *node) { struct callchain_list *list, *tmp; @@ -1039,3 +1234,30 @@ out: } return -ENOMEM; } + +int callchain_cursor__copy(struct callchain_cursor *dst, + struct callchain_cursor *src) +{ + int rc = 0; + + callchain_cursor_reset(dst); + callchain_cursor_commit(src); + + while (true) { + struct callchain_cursor_node *node; + + node = callchain_cursor_current(src); + if (node == NULL) + break; + + rc = callchain_cursor_append(dst, node->ip, node->map, node->sym, + node->branch, &node->branch_flags, + node->nr_loop_iter, node->samples); + if (rc) + break; + + callchain_cursor_advance(src); + } + + return rc; +} diff --git a/tools/perf/util/callchain.h b/tools/perf/util/callchain.h index 13e75549c440..35c8e379530f 100644 --- a/tools/perf/util/callchain.h +++ b/tools/perf/util/callchain.h @@ -11,11 +11,7 @@ #define CALLCHAIN_HELP "setup and enables call-graph (stack chain/backtrace):\n\n" -#ifdef HAVE_DWARF_UNWIND_SUPPORT # define RECORD_MODE_HELP HELP_PAD "record_mode:\tcall graph recording mode (fp|dwarf|lbr)\n" -#else -# define RECORD_MODE_HELP HELP_PAD "record_mode:\tcall graph recording mode (fp|lbr)\n" -#endif #define RECORD_SIZE_HELP \ HELP_PAD "record_size:\tif record_mode is 'dwarf', max size of stack recording (<bytes>)\n" \ @@ -115,6 +111,12 @@ struct callchain_list { bool unfolded; bool has_children; }; + u64 branch_count; + u64 predicted_count; + u64 abort_count; + u64 cycles_count; + u64 iter_count; + u64 samples_count; char *srcline; struct list_head list; }; @@ -129,6 +131,10 @@ struct callchain_cursor_node { u64 ip; struct map *map; struct symbol *sym; + bool branch; + struct branch_flags branch_flags; + int nr_loop_iter; + int samples; struct callchain_cursor_node *next; }; @@ -183,7 +189,9 @@ static inline void callchain_cursor_reset(struct callchain_cursor *cursor) } int callchain_cursor_append(struct callchain_cursor *cursor, u64 ip, - struct map *map, struct symbol *sym); + struct map *map, struct symbol *sym, + bool branch, struct branch_flags *flags, + int nr_loop_iter, int samples); /* Close a cursor writing session. Initialize for the reader */ static inline void callchain_cursor_commit(struct callchain_cursor *cursor) @@ -208,6 +216,9 @@ static inline void callchain_cursor_advance(struct callchain_cursor *cursor) cursor->pos++; } +int callchain_cursor__copy(struct callchain_cursor *dst, + struct callchain_cursor *src); + struct option; struct hist_entry; @@ -261,8 +272,16 @@ char *callchain_node__scnprintf_value(struct callchain_node *node, int callchain_node__fprintf_value(struct callchain_node *node, FILE *fp, u64 total); +int callchain_list_counts__printf_value(struct callchain_node *node, + struct callchain_list *clist, + FILE *fp, char *bf, int bfsize); + void free_callchain(struct callchain_root *root); void decay_callchain(struct callchain_root *root); int callchain_node__make_parent_list(struct callchain_node *node); +int callchain_branch_counts(struct callchain_root *root, + u64 *branch_count, u64 *predicted_count, + u64 *abort_count, u64 *cycles_count); + #endif /* __PERF_CALLCHAIN_H */ diff --git a/tools/perf/util/config.c b/tools/perf/util/config.c index 18dae745034f..3d906dbbef74 100644 --- a/tools/perf/util/config.c +++ b/tools/perf/util/config.c @@ -594,6 +594,19 @@ static int collect_config(const char *var, const char *value, goto out_free; } + /* perf_config_set can contain both user and system config items. + * So we should know where each value is from. + * The classification would be needed when a particular config file + * is overwrited by setting feature i.e. set_config(). + */ + if (strcmp(config_file_name, perf_etc_perfconfig()) == 0) { + section->from_system_config = true; + item->from_system_config = true; + } else { + section->from_system_config = false; + item->from_system_config = false; + } + ret = set_value(item, value); return ret; @@ -602,6 +615,13 @@ out_free: return -1; } +int perf_config_set__collect(struct perf_config_set *set, const char *file_name, + const char *var, const char *value) +{ + config_file_name = file_name; + return collect_config(var, value, set); +} + static int perf_config_set__init(struct perf_config_set *set) { int ret = -1; diff --git a/tools/perf/util/config.h b/tools/perf/util/config.h index 6f813d46045e..1a59a6b43f8b 100644 --- a/tools/perf/util/config.h +++ b/tools/perf/util/config.h @@ -7,12 +7,14 @@ struct perf_config_item { char *name; char *value; + bool from_system_config; struct list_head node; }; struct perf_config_section { char *name; struct list_head items; + bool from_system_config; struct list_head node; }; @@ -33,6 +35,8 @@ const char *perf_etc_perfconfig(void); struct perf_config_set *perf_config_set__new(void); void perf_config_set__delete(struct perf_config_set *set); +int perf_config_set__collect(struct perf_config_set *set, const char *file_name, + const char *var, const char *value); void perf_config__init(void); void perf_config__exit(void); void perf_config__refresh(void); diff --git a/tools/perf/util/event.h b/tools/perf/util/event.h index 8d363d5e65a2..c735c53a26f8 100644 --- a/tools/perf/util/event.h +++ b/tools/perf/util/event.h @@ -177,6 +177,8 @@ enum { PERF_IP_FLAG_TRACE_BEGIN |\ PERF_IP_FLAG_TRACE_END) +#define MAX_INSN 16 + struct perf_sample { u64 ip; u32 pid, tid; @@ -193,6 +195,7 @@ struct perf_sample { u32 flags; u16 insn_len; u8 cpumode; + char insn[MAX_INSN]; void *raw_data; struct ip_callchain *callchain; struct branch_stack *branch_stack; diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c index 8bc271141d9d..b2365a63db45 100644 --- a/tools/perf/util/evsel.c +++ b/tools/perf/util/evsel.c @@ -28,6 +28,7 @@ #include "debug.h" #include "trace-event.h" #include "stat.h" +#include "util/parse-branch-options.h" static struct { bool sample_id_all; @@ -708,6 +709,14 @@ static void apply_config_terms(struct perf_evsel *evsel, case PERF_EVSEL__CONFIG_TERM_CALLGRAPH: callgraph_buf = term->val.callgraph; break; + case PERF_EVSEL__CONFIG_TERM_BRANCH: + if (term->val.branch && strcmp(term->val.branch, "no")) { + perf_evsel__set_sample_bit(evsel, BRANCH_STACK); + parse_branch_str(term->val.branch, + &attr->branch_sample_type); + } else + perf_evsel__reset_sample_bit(evsel, BRANCH_STACK); + break; case PERF_EVSEL__CONFIG_TERM_STACK_USER: dump_size = term->val.stack_user; break; @@ -1472,7 +1481,7 @@ retry_sample_id: group_fd = get_group_fd(evsel, cpu, thread); retry_open: - pr_debug2("sys_perf_event_open: pid %d cpu %d group_fd %d flags %#lx\n", + pr_debug2("sys_perf_event_open: pid %d cpu %d group_fd %d flags %#lx", pid, cpus->map[cpu], group_fd, flags); FD(evsel, cpu, thread) = sys_perf_event_open(&evsel->attr, @@ -1481,11 +1490,13 @@ retry_open: group_fd, flags); if (FD(evsel, cpu, thread) < 0) { err = -errno; - pr_debug2("sys_perf_event_open failed, error %d\n", + pr_debug2("\nsys_perf_event_open failed, error %d\n", err); goto try_fallback; } + pr_debug2(" = %d\n", FD(evsel, cpu, thread)); + if (evsel->bpf_fd >= 0) { int evt_fd = FD(evsel, cpu, thread); int bpf_fd = evsel->bpf_fd; diff --git a/tools/perf/util/evsel.h b/tools/perf/util/evsel.h index b1503b0ecdff..6abb89cd27f9 100644 --- a/tools/perf/util/evsel.h +++ b/tools/perf/util/evsel.h @@ -47,6 +47,7 @@ enum { PERF_EVSEL__CONFIG_TERM_MAX_STACK, PERF_EVSEL__CONFIG_TERM_OVERWRITE, PERF_EVSEL__CONFIG_TERM_DRV_CFG, + PERF_EVSEL__CONFIG_TERM_BRANCH, PERF_EVSEL__CONFIG_TERM_MAX, }; @@ -63,6 +64,7 @@ struct perf_evsel_config_term { int max_stack; bool inherit; bool overwrite; + char *branch; } val; }; @@ -389,6 +391,8 @@ int perf_evsel__fprintf(struct perf_evsel *evsel, #define EVSEL__PRINT_ONELINE (1<<4) #define EVSEL__PRINT_SRCLINE (1<<5) #define EVSEL__PRINT_UNKNOWN_AS_ADDR (1<<6) +#define EVSEL__PRINT_CALLCHAIN_ARROW (1<<7) +#define EVSEL__PRINT_SKIP_IGNORED (1<<8) struct callchain_cursor; diff --git a/tools/perf/util/evsel_fprintf.c b/tools/perf/util/evsel_fprintf.c index 662a0a6182e7..6b2925542c0a 100644 --- a/tools/perf/util/evsel_fprintf.c +++ b/tools/perf/util/evsel_fprintf.c @@ -108,7 +108,10 @@ int sample__fprintf_callchain(struct perf_sample *sample, int left_alignment, int print_oneline = print_opts & EVSEL__PRINT_ONELINE; int print_srcline = print_opts & EVSEL__PRINT_SRCLINE; int print_unknown_as_addr = print_opts & EVSEL__PRINT_UNKNOWN_AS_ADDR; + int print_arrow = print_opts & EVSEL__PRINT_CALLCHAIN_ARROW; + int print_skip_ignored = print_opts & EVSEL__PRINT_SKIP_IGNORED; char s = print_oneline ? ' ' : '\t'; + bool first = true; if (sample->callchain) { struct addr_location node_al; @@ -122,8 +125,14 @@ int sample__fprintf_callchain(struct perf_sample *sample, int left_alignment, if (!node) break; + if (node->sym && node->sym->ignore && print_skip_ignored) + goto next; + printed += fprintf(fp, "%-*.*s", left_alignment, left_alignment, " "); + if (print_arrow && !first) + printed += fprintf(fp, " <-"); + if (print_ip) printed += fprintf(fp, "%c%16" PRIx64, s, node->ip); @@ -137,7 +146,8 @@ int sample__fprintf_callchain(struct perf_sample *sample, int left_alignment, if (print_symoffset) { printed += __symbol__fprintf_symname_offs(node->sym, &node_al, - print_unknown_as_addr, fp); + print_unknown_as_addr, + true, fp); } else { printed += __symbol__fprintf_symname(node->sym, &node_al, print_unknown_as_addr, fp); @@ -156,6 +166,16 @@ int sample__fprintf_callchain(struct perf_sample *sample, int left_alignment, if (!print_oneline) printed += fprintf(fp, "\n"); + if (symbol_conf.bt_stop_list && + node->sym && + node->sym->name && + strlist__has_entry(symbol_conf.bt_stop_list, + node->sym->name)) { + break; + } + + first = false; +next: callchain_cursor_advance(cursor); } } @@ -188,7 +208,8 @@ int sample__fprintf_sym(struct perf_sample *sample, struct addr_location *al, printed += fprintf(fp, " "); if (print_symoffset) { printed += __symbol__fprintf_symname_offs(al->sym, al, - print_unknown_as_addr, fp); + print_unknown_as_addr, + true, fp); } else { printed += __symbol__fprintf_symname(al->sym, al, print_unknown_as_addr, fp); diff --git a/tools/perf/util/genelf.c b/tools/perf/util/genelf.c index c1ef805c6a8f..c540d47583e7 100644 --- a/tools/perf/util/genelf.c +++ b/tools/perf/util/genelf.c @@ -19,12 +19,18 @@ #include <limits.h> #include <fcntl.h> #include <err.h> +#ifdef HAVE_DWARF_SUPPORT #include <dwarf.h> +#endif #include "perf.h" #include "genelf.h" #include "../util/jitdump.h" +#ifndef NT_GNU_BUILD_ID +#define NT_GNU_BUILD_ID 3 +#endif + #define JVMTI #define BUILD_ID_URANDOM /* different uuid for each run */ @@ -67,6 +73,8 @@ static char shd_string_table[] = { '.', 'd', 'e', 'b', 'u', 'g', '_', 'l', 'i', 'n', 'e', 0, /* 52 */ '.', 'd', 'e', 'b', 'u', 'g', '_', 'i', 'n', 'f', 'o', 0, /* 64 */ '.', 'd', 'e', 'b', 'u', 'g', '_', 'a', 'b', 'b', 'r', 'e', 'v', 0, /* 76 */ + '.', 'e', 'h', '_', 'f', 'r', 'a', 'm', 'e', '_', 'h', 'd', 'r', 0, /* 90 */ + '.', 'e', 'h', '_', 'f', 'r', 'a', 'm', 'e', 0, /* 104 */ }; static struct buildid_note { @@ -147,6 +155,86 @@ gen_build_id(struct buildid_note *note, unsigned long load_addr, const void *cod } #endif +static int +jit_add_eh_frame_info(Elf *e, void* unwinding, uint64_t unwinding_header_size, + uint64_t unwinding_size, uint64_t base_offset) +{ + Elf_Data *d; + Elf_Scn *scn; + Elf_Shdr *shdr; + uint64_t unwinding_table_size = unwinding_size - unwinding_header_size; + + /* + * setup eh_frame section + */ + scn = elf_newscn(e); + if (!scn) { + warnx("cannot create section"); + return -1; + } + + d = elf_newdata(scn); + if (!d) { + warnx("cannot get new data"); + return -1; + } + + d->d_align = 8; + d->d_off = 0LL; + d->d_buf = unwinding; + d->d_type = ELF_T_BYTE; + d->d_size = unwinding_table_size; + d->d_version = EV_CURRENT; + + shdr = elf_getshdr(scn); + if (!shdr) { + warnx("cannot get section header"); + return -1; + } + + shdr->sh_name = 104; + shdr->sh_type = SHT_PROGBITS; + shdr->sh_addr = base_offset; + shdr->sh_flags = SHF_ALLOC; + shdr->sh_entsize = 0; + + /* + * setup eh_frame_hdr section + */ + scn = elf_newscn(e); + if (!scn) { + warnx("cannot create section"); + return -1; + } + + d = elf_newdata(scn); + if (!d) { + warnx("cannot get new data"); + return -1; + } + + d->d_align = 4; + d->d_off = 0LL; + d->d_buf = unwinding + unwinding_table_size; + d->d_type = ELF_T_BYTE; + d->d_size = unwinding_header_size; + d->d_version = EV_CURRENT; + + shdr = elf_getshdr(scn); + if (!shdr) { + warnx("cannot get section header"); + return -1; + } + + shdr->sh_name = 90; + shdr->sh_type = SHT_PROGBITS; + shdr->sh_addr = base_offset + unwinding_table_size; + shdr->sh_flags = SHF_ALLOC; + shdr->sh_entsize = 0; + + return 0; +} + /* * fd: file descriptor open for writing for the output file * load_addr: code load address (could be zero, just used for buildid) @@ -157,13 +245,15 @@ gen_build_id(struct buildid_note *note, unsigned long load_addr, const void *cod int jit_write_elf(int fd, uint64_t load_addr, const char *sym, const void *code, int csize, - void *debug, int nr_debug_entries) + void *debug __maybe_unused, int nr_debug_entries __maybe_unused, + void *unwinding, uint64_t unwinding_header_size, uint64_t unwinding_size) { Elf *e; Elf_Data *d; Elf_Scn *scn; Elf_Ehdr *ehdr; Elf_Shdr *shdr; + uint64_t eh_frame_base_offset; char *strsym = NULL; int symlen; int retval = -1; @@ -194,7 +284,7 @@ jit_write_elf(int fd, uint64_t load_addr, const char *sym, ehdr->e_type = ET_DYN; ehdr->e_entry = GEN_ELF_TEXT_OFFSET; ehdr->e_version = EV_CURRENT; - ehdr->e_shstrndx= 2; /* shdr index for section name */ + ehdr->e_shstrndx= unwinding ? 4 : 2; /* shdr index for section name */ /* * setup text section @@ -231,6 +321,18 @@ jit_write_elf(int fd, uint64_t load_addr, const char *sym, shdr->sh_entsize = 0; /* + * Setup .eh_frame_hdr and .eh_frame + */ + if (unwinding) { + eh_frame_base_offset = ALIGN_8(GEN_ELF_TEXT_OFFSET + csize); + retval = jit_add_eh_frame_info(e, unwinding, + unwinding_header_size, unwinding_size, + eh_frame_base_offset); + if (retval) + goto error; + } + + /* * setup section headers string table */ scn = elf_newscn(e); @@ -298,7 +400,7 @@ jit_write_elf(int fd, uint64_t load_addr, const char *sym, shdr->sh_type = SHT_SYMTAB; shdr->sh_flags = 0; shdr->sh_entsize = sizeof(Elf_Sym); - shdr->sh_link = 4; /* index of .strtab section */ + shdr->sh_link = unwinding ? 6 : 4; /* index of .strtab section */ /* * setup symbols string table @@ -386,11 +488,14 @@ jit_write_elf(int fd, uint64_t load_addr, const char *sym, shdr->sh_size = sizeof(bnote); shdr->sh_entsize = 0; +#ifdef HAVE_DWARF_SUPPORT if (debug && nr_debug_entries) { retval = jit_add_debug_info(e, load_addr, debug, nr_debug_entries); if (retval) goto error; - } else { + } else +#endif + { if (elf_update(e, ELF_C_WRITE) < 0) { warnx("elf_update 4 failed"); goto error; diff --git a/tools/perf/util/genelf.h b/tools/perf/util/genelf.h index 2fbeb59c4bdd..2424bd9862a3 100644 --- a/tools/perf/util/genelf.h +++ b/tools/perf/util/genelf.h @@ -3,9 +3,12 @@ /* genelf.c */ int jit_write_elf(int fd, uint64_t code_addr, const char *sym, - const void *code, int csize, void *debug, int nr_debug_entries); + const void *code, int csize, void *debug, int nr_debug_entries, + void *unwinding, uint64_t unwinding_header_size, uint64_t unwinding_size); +#ifdef HAVE_DWARF_SUPPORT /* genelf_debug.c */ int jit_add_debug_info(Elf *e, uint64_t code_addr, void *debug, int nr_debug_entries); +#endif #if defined(__arm__) #define GEN_ELF_ARCH EM_ARM diff --git a/tools/perf/util/header.c b/tools/perf/util/header.c index 2f3eded54b0c..d89c9c7ef4e5 100644 --- a/tools/perf/util/header.c +++ b/tools/perf/util/header.c @@ -2250,11 +2250,28 @@ int perf_header__fprintf_info(struct perf_session *session, FILE *fp, bool full) struct header_print_data hd; struct perf_header *header = &session->header; int fd = perf_data_file__fd(session->file); + struct stat st; + int ret, bit; + hd.fp = fp; hd.full = full; + ret = fstat(fd, &st); + if (ret == -1) + return -1; + + fprintf(fp, "# captured on: %s", ctime(&st.st_ctime)); + perf_header__process_sections(header, fd, &hd, perf_file_section__fprintf_info); + + fprintf(fp, "# missing features: "); + for_each_clear_bit(bit, header->adds_features, HEADER_LAST_FEATURE) { + if (bit) + fprintf(fp, "%s ", feat_ops[bit].name); + } + + fprintf(fp, "\n"); return 0; } @@ -2273,7 +2290,7 @@ static int do_write_feat(int fd, struct perf_header *h, int type, err = feat_ops[type].write(fd, h, evlist); if (err < 0) { - pr_debug("failed to write feature %d\n", type); + pr_debug("failed to write feature %s\n", feat_ops[type].name); /* undo anything written */ lseek(fd, (*p)->offset, SEEK_SET); diff --git a/tools/perf/util/hist.c b/tools/perf/util/hist.c index a69f027368ef..6770a9645609 100644 --- a/tools/perf/util/hist.c +++ b/tools/perf/util/hist.c @@ -1195,6 +1195,7 @@ static void hist_entry__check_and_remove_filter(struct hist_entry *he, case HIST_FILTER__GUEST: case HIST_FILTER__HOST: case HIST_FILTER__SOCKET: + case HIST_FILTER__C2C: default: return; } diff --git a/tools/perf/util/hist.h b/tools/perf/util/hist.h index 9928fed8bc59..d4b6514eeef5 100644 --- a/tools/perf/util/hist.h +++ b/tools/perf/util/hist.h @@ -22,6 +22,7 @@ enum hist_filter { HIST_FILTER__GUEST, HIST_FILTER__HOST, HIST_FILTER__SOCKET, + HIST_FILTER__C2C, }; enum hist_column { diff --git a/tools/perf/util/intel-bts.c b/tools/perf/util/intel-bts.c index f545ec1e758a..6c2eb5da4afc 100644 --- a/tools/perf/util/intel-bts.c +++ b/tools/perf/util/intel-bts.c @@ -295,6 +295,7 @@ static int intel_bts_synth_branch_sample(struct intel_bts_queue *btsq, sample.cpu = btsq->cpu; sample.flags = btsq->sample_flags; sample.insn_len = btsq->intel_pt_insn.length; + memcpy(sample.insn, btsq->intel_pt_insn.buf, INTEL_PT_INSN_BUF_SZ); if (bts->synth_opts.inject) { event.sample.header.size = bts->branches_event_size; @@ -319,15 +320,12 @@ static int intel_bts_get_next_insn(struct intel_bts_queue *btsq, u64 ip) struct machine *machine = btsq->bts->machine; struct thread *thread; struct addr_location al; - unsigned char buf[1024]; - size_t bufsz; + unsigned char buf[INTEL_PT_INSN_BUF_SZ]; ssize_t len; int x86_64; uint8_t cpumode; int err = -1; - bufsz = intel_pt_insn_max_size(); - if (machine__kernel_ip(machine, ip)) cpumode = PERF_RECORD_MISC_KERNEL; else @@ -341,7 +339,8 @@ static int intel_bts_get_next_insn(struct intel_bts_queue *btsq, u64 ip) if (!al.map || !al.map->dso) goto out_put; - len = dso__data_read_addr(al.map->dso, al.map, machine, ip, buf, bufsz); + len = dso__data_read_addr(al.map->dso, al.map, machine, ip, buf, + INTEL_PT_INSN_BUF_SZ); if (len <= 0) goto out_put; diff --git a/tools/perf/util/intel-pt-decoder/intel-pt-decoder.c b/tools/perf/util/intel-pt-decoder/intel-pt-decoder.c index 16c06d3ae577..e4e7dc781d21 100644 --- a/tools/perf/util/intel-pt-decoder/intel-pt-decoder.c +++ b/tools/perf/util/intel-pt-decoder/intel-pt-decoder.c @@ -980,6 +980,8 @@ out: out_no_progress: decoder->state.insn_op = intel_pt_insn->op; decoder->state.insn_len = intel_pt_insn->length; + memcpy(decoder->state.insn, intel_pt_insn->buf, + INTEL_PT_INSN_BUF_SZ); if (decoder->tx_flags & INTEL_PT_IN_TX) decoder->state.flags |= INTEL_PT_IN_TX; diff --git a/tools/perf/util/intel-pt-decoder/intel-pt-decoder.h b/tools/perf/util/intel-pt-decoder/intel-pt-decoder.h index 89399985fa4d..e90619a43c0c 100644 --- a/tools/perf/util/intel-pt-decoder/intel-pt-decoder.h +++ b/tools/perf/util/intel-pt-decoder/intel-pt-decoder.h @@ -66,6 +66,7 @@ struct intel_pt_state { uint32_t flags; enum intel_pt_insn_op insn_op; int insn_len; + char insn[INTEL_PT_INSN_BUF_SZ]; }; struct intel_pt_insn; diff --git a/tools/perf/util/intel-pt-decoder/intel-pt-insn-decoder.c b/tools/perf/util/intel-pt-decoder/intel-pt-insn-decoder.c index d23138c06665..7913363bde5c 100644 --- a/tools/perf/util/intel-pt-decoder/intel-pt-insn-decoder.c +++ b/tools/perf/util/intel-pt-decoder/intel-pt-insn-decoder.c @@ -27,6 +27,10 @@ #include "intel-pt-insn-decoder.h" +#if INTEL_PT_INSN_BUF_SZ < MAX_INSN_SIZE || INTEL_PT_INSN_BUF_SZ > MAX_INSN +#error Instruction buffer size too small +#endif + /* Based on branch_type() from perf_event_intel_lbr.c */ static void intel_pt_insn_decoder(struct insn *insn, struct intel_pt_insn *intel_pt_insn) @@ -166,10 +170,10 @@ int intel_pt_get_insn(const unsigned char *buf, size_t len, int x86_64, if (!insn_complete(&insn) || insn.length > len) return -1; intel_pt_insn_decoder(&insn, intel_pt_insn); - if (insn.length < INTEL_PT_INSN_DBG_BUF_SZ) + if (insn.length < INTEL_PT_INSN_BUF_SZ) memcpy(intel_pt_insn->buf, buf, insn.length); else - memcpy(intel_pt_insn->buf, buf, INTEL_PT_INSN_DBG_BUF_SZ); + memcpy(intel_pt_insn->buf, buf, INTEL_PT_INSN_BUF_SZ); return 0; } @@ -211,11 +215,6 @@ int intel_pt_insn_desc(const struct intel_pt_insn *intel_pt_insn, char *buf, return 0; } -size_t intel_pt_insn_max_size(void) -{ - return MAX_INSN_SIZE; -} - int intel_pt_insn_type(enum intel_pt_insn_op op) { switch (op) { diff --git a/tools/perf/util/intel-pt-decoder/intel-pt-insn-decoder.h b/tools/perf/util/intel-pt-decoder/intel-pt-insn-decoder.h index b0adbf37323e..37ec5627ae9b 100644 --- a/tools/perf/util/intel-pt-decoder/intel-pt-insn-decoder.h +++ b/tools/perf/util/intel-pt-decoder/intel-pt-insn-decoder.h @@ -20,7 +20,7 @@ #include <stdint.h> #define INTEL_PT_INSN_DESC_MAX 32 -#define INTEL_PT_INSN_DBG_BUF_SZ 16 +#define INTEL_PT_INSN_BUF_SZ 16 enum intel_pt_insn_op { INTEL_PT_OP_OTHER, @@ -47,7 +47,7 @@ struct intel_pt_insn { enum intel_pt_insn_branch branch; int length; int32_t rel; - unsigned char buf[INTEL_PT_INSN_DBG_BUF_SZ]; + unsigned char buf[INTEL_PT_INSN_BUF_SZ]; }; int intel_pt_get_insn(const unsigned char *buf, size_t len, int x86_64, @@ -58,8 +58,6 @@ const char *intel_pt_insn_name(enum intel_pt_insn_op op); int intel_pt_insn_desc(const struct intel_pt_insn *intel_pt_insn, char *buf, size_t buf_len); -size_t intel_pt_insn_max_size(void); - int intel_pt_insn_type(enum intel_pt_insn_op op); #endif diff --git a/tools/perf/util/intel-pt-decoder/intel-pt-log.c b/tools/perf/util/intel-pt-decoder/intel-pt-log.c index 319bef33a64b..e02bc7b166a0 100644 --- a/tools/perf/util/intel-pt-decoder/intel-pt-log.c +++ b/tools/perf/util/intel-pt-decoder/intel-pt-log.c @@ -119,8 +119,8 @@ void __intel_pt_log_insn(struct intel_pt_insn *intel_pt_insn, uint64_t ip) if (intel_pt_log_open()) return; - if (len > INTEL_PT_INSN_DBG_BUF_SZ) - len = INTEL_PT_INSN_DBG_BUF_SZ; + if (len > INTEL_PT_INSN_BUF_SZ) + len = INTEL_PT_INSN_BUF_SZ; intel_pt_print_data(intel_pt_insn->buf, len, ip, 8); if (intel_pt_insn_desc(intel_pt_insn, desc, INTEL_PT_INSN_DESC_MAX) > 0) fprintf(f, "%s\n", desc); diff --git a/tools/perf/util/intel-pt.c b/tools/perf/util/intel-pt.c index dc041d4368c8..85d5eeb66c75 100644 --- a/tools/perf/util/intel-pt.c +++ b/tools/perf/util/intel-pt.c @@ -143,6 +143,7 @@ struct intel_pt_queue { u32 flags; u16 insn_len; u64 last_insn_cnt; + char insn[INTEL_PT_INSN_BUF_SZ]; }; static void intel_pt_dump(struct intel_pt *pt __maybe_unused, @@ -315,6 +316,7 @@ struct intel_pt_cache_entry { enum intel_pt_insn_branch branch; int length; int32_t rel; + char insn[INTEL_PT_INSN_BUF_SZ]; }; static int intel_pt_config_div(const char *var, const char *value, void *data) @@ -400,6 +402,7 @@ static int intel_pt_cache_add(struct dso *dso, struct machine *machine, e->branch = intel_pt_insn->branch; e->length = intel_pt_insn->length; e->rel = intel_pt_insn->rel; + memcpy(e->insn, intel_pt_insn->buf, INTEL_PT_INSN_BUF_SZ); err = auxtrace_cache__add(c, offset, &e->entry); if (err) @@ -428,8 +431,7 @@ static int intel_pt_walk_next_insn(struct intel_pt_insn *intel_pt_insn, struct machine *machine = ptq->pt->machine; struct thread *thread; struct addr_location al; - unsigned char buf[1024]; - size_t bufsz; + unsigned char buf[INTEL_PT_INSN_BUF_SZ]; ssize_t len; int x86_64; u8 cpumode; @@ -437,11 +439,11 @@ static int intel_pt_walk_next_insn(struct intel_pt_insn *intel_pt_insn, u64 insn_cnt = 0; bool one_map = true; + intel_pt_insn->length = 0; + if (to_ip && *ip == to_ip) goto out_no_cache; - bufsz = intel_pt_insn_max_size(); - if (*ip >= ptq->pt->kernel_start) cpumode = PERF_RECORD_MISC_KERNEL; else @@ -478,6 +480,8 @@ static int intel_pt_walk_next_insn(struct intel_pt_insn *intel_pt_insn, intel_pt_insn->branch = e->branch; intel_pt_insn->length = e->length; intel_pt_insn->rel = e->rel; + memcpy(intel_pt_insn->buf, e->insn, + INTEL_PT_INSN_BUF_SZ); intel_pt_log_insn_no_data(intel_pt_insn, *ip); return 0; } @@ -493,7 +497,8 @@ static int intel_pt_walk_next_insn(struct intel_pt_insn *intel_pt_insn, while (1) { len = dso__data_read_offset(al.map->dso, machine, - offset, buf, bufsz); + offset, buf, + INTEL_PT_INSN_BUF_SZ); if (len <= 0) return -EINVAL; @@ -900,6 +905,7 @@ static void intel_pt_sample_flags(struct intel_pt_queue *ptq) if (ptq->state->flags & INTEL_PT_IN_TX) ptq->flags |= PERF_IP_FLAG_IN_TX; ptq->insn_len = ptq->state->insn_len; + memcpy(ptq->insn, ptq->state->insn, INTEL_PT_INSN_BUF_SZ); } } @@ -1080,6 +1086,7 @@ static int intel_pt_synth_branch_sample(struct intel_pt_queue *ptq) sample.cpu = ptq->cpu; sample.flags = ptq->flags; sample.insn_len = ptq->insn_len; + memcpy(sample.insn, ptq->insn, INTEL_PT_INSN_BUF_SZ); /* * perf report cannot handle events without a branch stack when using @@ -1141,6 +1148,7 @@ static int intel_pt_synth_instruction_sample(struct intel_pt_queue *ptq) sample.cpu = ptq->cpu; sample.flags = ptq->flags; sample.insn_len = ptq->insn_len; + memcpy(sample.insn, ptq->insn, INTEL_PT_INSN_BUF_SZ); ptq->last_insn_cnt = ptq->state->tot_insn_cnt; @@ -1203,6 +1211,7 @@ static int intel_pt_synth_transaction_sample(struct intel_pt_queue *ptq) sample.cpu = ptq->cpu; sample.flags = ptq->flags; sample.insn_len = ptq->insn_len; + memcpy(sample.insn, ptq->insn, INTEL_PT_INSN_BUF_SZ); if (pt->synth_opts.callchain) { thread_stack__sample(ptq->thread, ptq->chain, diff --git a/tools/perf/util/jitdump.c b/tools/perf/util/jitdump.c index 95f0884aae02..c9a941ef0f6d 100644 --- a/tools/perf/util/jitdump.c +++ b/tools/perf/util/jitdump.c @@ -37,6 +37,10 @@ struct jit_buf_desc { bool needs_bswap; /* handles cross-endianess */ bool use_arch_timestamp; void *debug_data; + void *unwinding_data; + uint64_t unwinding_size; + uint64_t unwinding_mapped_size; + uint64_t eh_frame_hdr_size; size_t nr_debug_entries; uint32_t code_load_count; u64 bytes_written; @@ -68,7 +72,10 @@ jit_emit_elf(char *filename, const void *code, int csize, void *debug, - int nr_debug_entries) + int nr_debug_entries, + void *unwinding, + uint32_t unwinding_header_size, + uint32_t unwinding_size) { int ret, fd; @@ -81,7 +88,8 @@ jit_emit_elf(char *filename, return -1; } - ret = jit_write_elf(fd, code_addr, sym, (const void *)code, csize, debug, nr_debug_entries); + ret = jit_write_elf(fd, code_addr, sym, (const void *)code, csize, debug, nr_debug_entries, + unwinding, unwinding_header_size, unwinding_size); close(fd); @@ -172,6 +180,12 @@ jit_open(struct jit_buf_desc *jd, const char *name) header.elf_mach, jd->use_arch_timestamp); + if (header.version > JITHEADER_VERSION) { + pr_err("wrong jitdump version %u, expected " STR(JITHEADER_VERSION), + header.version); + goto error; + } + if (header.flags & JITDUMP_FLAGS_RESERVED) { pr_err("jitdump file contains invalid or unsupported flags 0x%llx\n", (unsigned long long)header.flags & JITDUMP_FLAGS_RESERVED); @@ -263,8 +277,7 @@ jit_get_next_entry(struct jit_buf_desc *jd) return NULL; if (id >= JIT_CODE_MAX) { - pr_warning("next_entry: unknown prefix %d, skipping\n", id); - return NULL; + pr_warning("next_entry: unknown record type %d, skipping\n", id); } if (bs > jd->bufsize) { void *n; @@ -296,6 +309,13 @@ jit_get_next_entry(struct jit_buf_desc *jd) } } break; + case JIT_CODE_UNWINDING_INFO: + if (jd->needs_bswap) { + jr->unwinding.unwinding_size = bswap_64(jr->unwinding.unwinding_size); + jr->unwinding.eh_frame_hdr_size = bswap_64(jr->unwinding.eh_frame_hdr_size); + jr->unwinding.mapped_size = bswap_64(jr->unwinding.mapped_size); + } + break; case JIT_CODE_CLOSE: break; case JIT_CODE_LOAD: @@ -322,7 +342,8 @@ jit_get_next_entry(struct jit_buf_desc *jd) break; case JIT_CODE_MAX: default: - return NULL; + /* skip unknown record (we have read them) */ + break; } return jr; } @@ -370,7 +391,7 @@ static int jit_repipe_code_load(struct jit_buf_desc *jd, union jr_entry *jr) u16 idr_size; const char *sym; uint32_t count; - int ret, csize; + int ret, csize, usize; pid_t pid, tid; struct { u32 pid, tid; @@ -380,6 +401,7 @@ static int jit_repipe_code_load(struct jit_buf_desc *jd, union jr_entry *jr) pid = jr->load.pid; tid = jr->load.tid; csize = jr->load.code_size; + usize = jd->unwinding_mapped_size; addr = jr->load.code_addr; sym = (void *)((unsigned long)jr + sizeof(jr->load)); code = (unsigned long)jr + jr->load.p.total_size - csize; @@ -400,7 +422,8 @@ static int jit_repipe_code_load(struct jit_buf_desc *jd, union jr_entry *jr) size = PERF_ALIGN(size, sizeof(u64)); uaddr = (uintptr_t)code; - ret = jit_emit_elf(filename, sym, addr, (const void *)uaddr, csize, jd->debug_data, jd->nr_debug_entries); + ret = jit_emit_elf(filename, sym, addr, (const void *)uaddr, csize, jd->debug_data, jd->nr_debug_entries, + jd->unwinding_data, jd->eh_frame_hdr_size, jd->unwinding_size); if (jd->debug_data && jd->nr_debug_entries) { free(jd->debug_data); @@ -408,6 +431,14 @@ static int jit_repipe_code_load(struct jit_buf_desc *jd, union jr_entry *jr) jd->nr_debug_entries = 0; } + if (jd->unwinding_data && jd->eh_frame_hdr_size) { + free(jd->unwinding_data); + jd->unwinding_data = NULL; + jd->eh_frame_hdr_size = 0; + jd->unwinding_mapped_size = 0; + jd->unwinding_size = 0; + } + if (ret) { free(event); return -1; @@ -422,7 +453,7 @@ static int jit_repipe_code_load(struct jit_buf_desc *jd, union jr_entry *jr) event->mmap2.pgoff = GEN_ELF_TEXT_OFFSET; event->mmap2.start = addr; - event->mmap2.len = csize; + event->mmap2.len = usize ? ALIGN_8(csize) + usize : csize; event->mmap2.pid = pid; event->mmap2.tid = tid; event->mmap2.ino = st.st_ino; @@ -473,6 +504,7 @@ static int jit_repipe_code_move(struct jit_buf_desc *jd, union jr_entry *jr) char *filename; size_t size; struct stat st; + int usize; u16 idr_size; int ret; pid_t pid, tid; @@ -483,6 +515,7 @@ static int jit_repipe_code_move(struct jit_buf_desc *jd, union jr_entry *jr) pid = jr->move.pid; tid = jr->move.tid; + usize = jd->unwinding_mapped_size; idr_size = jd->machine->id_hdr_size; /* @@ -511,7 +544,8 @@ static int jit_repipe_code_move(struct jit_buf_desc *jd, union jr_entry *jr) (sizeof(event->mmap2.filename) - size) + idr_size); event->mmap2.pgoff = GEN_ELF_TEXT_OFFSET; event->mmap2.start = jr->move.new_code_addr; - event->mmap2.len = jr->move.code_size; + event->mmap2.len = usize ? ALIGN_8(jr->move.code_size) + usize + : jr->move.code_size; event->mmap2.pid = pid; event->mmap2.tid = tid; event->mmap2.ino = st.st_ino; @@ -578,10 +612,35 @@ static int jit_repipe_debug_info(struct jit_buf_desc *jd, union jr_entry *jr) } static int +jit_repipe_unwinding_info(struct jit_buf_desc *jd, union jr_entry *jr) +{ + void *unwinding_data; + uint32_t unwinding_data_size; + + if (!(jd && jr)) + return -1; + + unwinding_data_size = jr->prefix.total_size - sizeof(jr->unwinding); + unwinding_data = malloc(unwinding_data_size); + if (!unwinding_data) + return -1; + + memcpy(unwinding_data, &jr->unwinding.unwinding_data, + unwinding_data_size); + + jd->eh_frame_hdr_size = jr->unwinding.eh_frame_hdr_size; + jd->unwinding_size = jr->unwinding.unwinding_size; + jd->unwinding_mapped_size = jr->unwinding.mapped_size; + jd->unwinding_data = unwinding_data; + + return 0; +} + +static int jit_process_dump(struct jit_buf_desc *jd) { union jr_entry *jr; - int ret; + int ret = 0; while ((jr = jit_get_next_entry(jd))) { switch(jr->prefix.id) { @@ -594,6 +653,9 @@ jit_process_dump(struct jit_buf_desc *jd) case JIT_CODE_DEBUG_INFO: ret = jit_repipe_debug_info(jd, jr); break; + case JIT_CODE_UNWINDING_INFO: + ret = jit_repipe_unwinding_info(jd, jr); + break; default: ret = 0; continue; diff --git a/tools/perf/util/jitdump.h b/tools/perf/util/jitdump.h index bcacd20d0c1c..c6b9b67f43bf 100644 --- a/tools/perf/util/jitdump.h +++ b/tools/perf/util/jitdump.h @@ -19,6 +19,7 @@ #define JITHEADER_MAGIC_SW 0x4454694A #define PADDING_8ALIGNED(x) ((((x) + 7) & 7) ^ 7) +#define ALIGN_8(x) (((x) + 7) & (~7)) #define JITHEADER_VERSION 1 @@ -48,6 +49,7 @@ enum jit_record_type { JIT_CODE_MOVE = 1, JIT_CODE_DEBUG_INFO = 2, JIT_CODE_CLOSE = 3, + JIT_CODE_UNWINDING_INFO = 4, JIT_CODE_MAX, }; @@ -101,12 +103,22 @@ struct jr_code_debug_info { struct debug_entry entries[0]; }; +struct jr_code_unwinding_info { + struct jr_prefix p; + + uint64_t unwinding_size; + uint64_t eh_frame_hdr_size; + uint64_t mapped_size; + const char unwinding_data[0]; +}; + union jr_entry { struct jr_code_debug_info info; struct jr_code_close close; struct jr_code_load load; struct jr_code_move move; struct jr_prefix prefix; + struct jr_code_unwinding_info unwinding; }; static inline struct debug_entry * diff --git a/tools/perf/util/llvm-utils.c b/tools/perf/util/llvm-utils.c index bf7216b8731d..b23ff44cf214 100644 --- a/tools/perf/util/llvm-utils.c +++ b/tools/perf/util/llvm-utils.c @@ -7,6 +7,7 @@ #include <limits.h> #include <stdio.h> #include <stdlib.h> +#include <linux/err.h> #include "debug.h" #include "llvm-utils.h" #include "config.h" @@ -282,9 +283,10 @@ static const char *kinc_fetch_script = "rm -rf $TMPDIR\n" "exit $RET\n"; -static inline void -get_kbuild_opts(char **kbuild_dir, char **kbuild_include_opts) +void llvm__get_kbuild_opts(char **kbuild_dir, char **kbuild_include_opts) { + static char *saved_kbuild_dir; + static char *saved_kbuild_include_opts; int err; if (!kbuild_dir || !kbuild_include_opts) @@ -293,10 +295,28 @@ get_kbuild_opts(char **kbuild_dir, char **kbuild_include_opts) *kbuild_dir = NULL; *kbuild_include_opts = NULL; + if (saved_kbuild_dir && saved_kbuild_include_opts && + !IS_ERR(saved_kbuild_dir) && !IS_ERR(saved_kbuild_include_opts)) { + *kbuild_dir = strdup(saved_kbuild_dir); + *kbuild_include_opts = strdup(saved_kbuild_include_opts); + + if (*kbuild_dir && *kbuild_include_opts) + return; + + zfree(kbuild_dir); + zfree(kbuild_include_opts); + /* + * Don't fall through: it may breaks saved_kbuild_dir and + * saved_kbuild_include_opts if detect them again when + * memory is low. + */ + return; + } + if (llvm_param.kbuild_dir && !llvm_param.kbuild_dir[0]) { pr_debug("[llvm.kbuild-dir] is set to \"\" deliberately.\n"); pr_debug("Skip kbuild options detection.\n"); - return; + goto errout; } err = detect_kbuild_dir(kbuild_dir); @@ -306,7 +326,7 @@ get_kbuild_opts(char **kbuild_dir, char **kbuild_include_opts) "Hint:\tSet correct kbuild directory using 'kbuild-dir' option in [llvm]\n" " \tsection of ~/.perfconfig or set it to \"\" to suppress kbuild\n" " \tdetection.\n\n"); - return; + goto errout; } pr_debug("Kernel build dir is set to %s\n", *kbuild_dir); @@ -325,21 +345,50 @@ get_kbuild_opts(char **kbuild_dir, char **kbuild_include_opts) free(*kbuild_dir); *kbuild_dir = NULL; - return; + goto errout; } pr_debug("include option is set to %s\n", *kbuild_include_opts); + + saved_kbuild_dir = strdup(*kbuild_dir); + saved_kbuild_include_opts = strdup(*kbuild_include_opts); + + if (!saved_kbuild_dir || !saved_kbuild_include_opts) { + zfree(&saved_kbuild_dir); + zfree(&saved_kbuild_include_opts); + } + return; +errout: + saved_kbuild_dir = ERR_PTR(-EINVAL); + saved_kbuild_include_opts = ERR_PTR(-EINVAL); } -static void -dump_obj(const char *path, void *obj_buf, size_t size) +int llvm__get_nr_cpus(void) +{ + static int nr_cpus_avail = 0; + char serr[STRERR_BUFSIZE]; + + if (nr_cpus_avail > 0) + return nr_cpus_avail; + + nr_cpus_avail = sysconf(_SC_NPROCESSORS_CONF); + if (nr_cpus_avail <= 0) { + pr_err( +"WARNING:\tunable to get available CPUs in this system: %s\n" +" \tUse 128 instead.\n", str_error_r(errno, serr, sizeof(serr))); + nr_cpus_avail = 128; + } + return nr_cpus_avail; +} + +void llvm__dump_obj(const char *path, void *obj_buf, size_t size) { char *obj_path = strdup(path); FILE *fp; char *p; if (!obj_path) { - pr_warning("WARNING: No enough memory, skip object dumping\n"); + pr_warning("WARNING: Not enough memory, skip object dumping\n"); return; } @@ -406,15 +455,9 @@ int llvm__compile_bpf(const char *path, void **p_obj_buf, * This is an optional work. Even it fail we can continue our * work. Needn't to check error return. */ - get_kbuild_opts(&kbuild_dir, &kbuild_include_opts); + llvm__get_kbuild_opts(&kbuild_dir, &kbuild_include_opts); - nr_cpus_avail = sysconf(_SC_NPROCESSORS_CONF); - if (nr_cpus_avail <= 0) { - pr_err( -"WARNING:\tunable to get available CPUs in this system: %s\n" -" \tUse 128 instead.\n", str_error_r(errno, serr, sizeof(serr))); - nr_cpus_avail = 128; - } + nr_cpus_avail = llvm__get_nr_cpus(); snprintf(nr_cpus_avail_str, sizeof(nr_cpus_avail_str), "%d", nr_cpus_avail); @@ -453,9 +496,6 @@ int llvm__compile_bpf(const char *path, void **p_obj_buf, free(kbuild_dir); free(kbuild_include_opts); - if (llvm_param.dump_obj) - dump_obj(path, obj_buf, obj_buf_sz); - if (!p_obj_buf) free(obj_buf); else diff --git a/tools/perf/util/llvm-utils.h b/tools/perf/util/llvm-utils.h index 9f501cef06a1..c87a2a92a88f 100644 --- a/tools/perf/util/llvm-utils.h +++ b/tools/perf/util/llvm-utils.h @@ -50,4 +50,10 @@ int llvm__compile_bpf(const char *path, void **p_obj_buf, size_t *p_obj_buf_sz); /* This function is for test__llvm() use only */ int llvm__search_clang(void); + +/* Following functions are reused by builtin clang support */ +void llvm__get_kbuild_opts(char **kbuild_dir, char **kbuild_include_opts); +int llvm__get_nr_cpus(void); + +void llvm__dump_obj(const char *path, void *obj_buf, size_t size); #endif diff --git a/tools/perf/util/machine.c b/tools/perf/util/machine.c index df85b9efd80f..9b33bef54581 100644 --- a/tools/perf/util/machine.c +++ b/tools/perf/util/machine.c @@ -1616,7 +1616,11 @@ static int add_callchain_ip(struct thread *thread, struct symbol **parent, struct addr_location *root_al, u8 *cpumode, - u64 ip) + u64 ip, + bool branch, + struct branch_flags *flags, + int nr_loop_iter, + int samples) { struct addr_location al; @@ -1668,7 +1672,8 @@ static int add_callchain_ip(struct thread *thread, if (symbol_conf.hide_unresolved && al.sym == NULL) return 0; - return callchain_cursor_append(cursor, al.addr, al.map, al.sym); + return callchain_cursor_append(cursor, al.addr, al.map, al.sym, + branch, flags, nr_loop_iter, samples); } struct branch_info *sample__resolve_bstack(struct perf_sample *sample, @@ -1757,7 +1762,9 @@ static int resolve_lbr_callchain_sample(struct thread *thread, /* LBR only affects the user callchain */ if (i != chain_nr) { struct branch_stack *lbr_stack = sample->branch_stack; - int lbr_nr = lbr_stack->nr, j; + int lbr_nr = lbr_stack->nr, j, k; + bool branch; + struct branch_flags *flags; /* * LBR callstack can only get user call chain. * The mix_chain_nr is kernel call chain @@ -1772,23 +1779,41 @@ static int resolve_lbr_callchain_sample(struct thread *thread, for (j = 0; j < mix_chain_nr; j++) { int err; + branch = false; + flags = NULL; + if (callchain_param.order == ORDER_CALLEE) { if (j < i + 1) ip = chain->ips[j]; - else if (j > i + 1) - ip = lbr_stack->entries[j - i - 2].from; - else + else if (j > i + 1) { + k = j - i - 2; + ip = lbr_stack->entries[k].from; + branch = true; + flags = &lbr_stack->entries[k].flags; + } else { ip = lbr_stack->entries[0].to; + branch = true; + flags = &lbr_stack->entries[0].flags; + } } else { - if (j < lbr_nr) - ip = lbr_stack->entries[lbr_nr - j - 1].from; + if (j < lbr_nr) { + k = lbr_nr - j - 1; + ip = lbr_stack->entries[k].from; + branch = true; + flags = &lbr_stack->entries[k].flags; + } else if (j > lbr_nr) ip = chain->ips[i + 1 - (j - lbr_nr)]; - else + else { ip = lbr_stack->entries[0].to; + branch = true; + flags = &lbr_stack->entries[0].flags; + } } - err = add_callchain_ip(thread, cursor, parent, root_al, &cpumode, ip); + err = add_callchain_ip(thread, cursor, parent, + root_al, &cpumode, ip, + branch, flags, 0, 0); if (err) return (err < 0) ? err : 0; } @@ -1813,6 +1838,7 @@ static int thread__resolve_callchain_sample(struct thread *thread, int i, j, err, nr_entries; int skip_idx = -1; int first_call = 0; + int nr_loop_iter; if (perf_evsel__has_branch_callstack(evsel)) { err = resolve_lbr_callchain_sample(thread, cursor, sample, parent, @@ -1868,14 +1894,37 @@ static int thread__resolve_callchain_sample(struct thread *thread, be[i] = branch->entries[branch->nr - i - 1]; } + nr_loop_iter = nr; nr = remove_loops(be, nr); + /* + * Get the number of iterations. + * It's only approximation, but good enough in practice. + */ + if (nr_loop_iter > nr) + nr_loop_iter = nr_loop_iter - nr + 1; + else + nr_loop_iter = 0; + for (i = 0; i < nr; i++) { - err = add_callchain_ip(thread, cursor, parent, root_al, - NULL, be[i].to); + if (i == nr - 1) + err = add_callchain_ip(thread, cursor, parent, + root_al, + NULL, be[i].to, + true, &be[i].flags, + nr_loop_iter, 1); + else + err = add_callchain_ip(thread, cursor, parent, + root_al, + NULL, be[i].to, + true, &be[i].flags, + 0, 0); + if (!err) err = add_callchain_ip(thread, cursor, parent, root_al, - NULL, be[i].from); + NULL, be[i].from, + true, &be[i].flags, + 0, 0); if (err == -EINVAL) break; if (err) @@ -1903,7 +1952,9 @@ check_calls: if (ip < PERF_CONTEXT_MAX) ++nr_entries; - err = add_callchain_ip(thread, cursor, parent, root_al, &cpumode, ip); + err = add_callchain_ip(thread, cursor, parent, + root_al, &cpumode, ip, + false, NULL, 0, 0); if (err) return (err < 0) ? err : 0; @@ -1919,7 +1970,8 @@ static int unwind_entry(struct unwind_entry *entry, void *arg) if (symbol_conf.hide_unresolved && entry->sym == NULL) return 0; return callchain_cursor_append(cursor, entry->ip, - entry->map, entry->sym); + entry->map, entry->sym, + false, NULL, 0, 0); } static int thread__resolve_callchain_unwind(struct thread *thread, diff --git a/tools/perf/util/map.c b/tools/perf/util/map.c index c662fef95d14..4f9a71c63026 100644 --- a/tools/perf/util/map.c +++ b/tools/perf/util/map.c @@ -682,9 +682,16 @@ static int maps__fixup_overlappings(struct maps *maps, struct map *map, FILE *fp continue; if (verbose >= 2) { - fputs("overlapping maps:\n", fp); - map__fprintf(map, fp); - map__fprintf(pos, fp); + + if (use_browser) { + pr_warning("overlapping maps in %s " + "(disable tui for more info)\n", + map->dso->name); + } else { + fputs("overlapping maps:\n", fp); + map__fprintf(map, fp); + map__fprintf(pos, fp); + } } rb_erase_init(&pos->rb_node, root); @@ -702,7 +709,7 @@ static int maps__fixup_overlappings(struct maps *maps, struct map *map, FILE *fp before->end = map->start; __map_groups__insert(pos->groups, before); - if (verbose >= 2) + if (verbose >= 2 && !use_browser) map__fprintf(before, fp); map__put(before); } @@ -717,7 +724,7 @@ static int maps__fixup_overlappings(struct maps *maps, struct map *map, FILE *fp after->start = map->end; __map_groups__insert(pos->groups, after); - if (verbose >= 2) + if (verbose >= 2 && !use_browser) map__fprintf(after, fp); map__put(after); } diff --git a/tools/perf/util/mem-events.c b/tools/perf/util/mem-events.c index bbc368e7d1e4..1d4ab53c60ca 100644 --- a/tools/perf/util/mem-events.c +++ b/tools/perf/util/mem-events.c @@ -9,6 +9,7 @@ #include "mem-events.h" #include "debug.h" #include "symbol.h" +#include "sort.h" unsigned int perf_mem_events__loads_ldlat = 30; @@ -268,3 +269,138 @@ int perf_script__meminfo_scnprintf(char *out, size_t sz, struct mem_info *mem_in return i; } + +int c2c_decode_stats(struct c2c_stats *stats, struct mem_info *mi) +{ + union perf_mem_data_src *data_src = &mi->data_src; + u64 daddr = mi->daddr.addr; + u64 op = data_src->mem_op; + u64 lvl = data_src->mem_lvl; + u64 snoop = data_src->mem_snoop; + u64 lock = data_src->mem_lock; + int err = 0; + +#define HITM_INC(__f) \ +do { \ + stats->__f++; \ + stats->tot_hitm++; \ +} while (0) + +#define P(a, b) PERF_MEM_##a##_##b + + stats->nr_entries++; + + if (lock & P(LOCK, LOCKED)) stats->locks++; + + if (op & P(OP, LOAD)) { + /* load */ + stats->load++; + + if (!daddr) { + stats->ld_noadrs++; + return -1; + } + + if (lvl & P(LVL, HIT)) { + if (lvl & P(LVL, UNC)) stats->ld_uncache++; + if (lvl & P(LVL, IO)) stats->ld_io++; + if (lvl & P(LVL, LFB)) stats->ld_fbhit++; + if (lvl & P(LVL, L1 )) stats->ld_l1hit++; + if (lvl & P(LVL, L2 )) stats->ld_l2hit++; + if (lvl & P(LVL, L3 )) { + if (snoop & P(SNOOP, HITM)) + HITM_INC(lcl_hitm); + else + stats->ld_llchit++; + } + + if (lvl & P(LVL, LOC_RAM)) { + stats->lcl_dram++; + if (snoop & P(SNOOP, HIT)) + stats->ld_shared++; + else + stats->ld_excl++; + } + + if ((lvl & P(LVL, REM_RAM1)) || + (lvl & P(LVL, REM_RAM2))) { + stats->rmt_dram++; + if (snoop & P(SNOOP, HIT)) + stats->ld_shared++; + else + stats->ld_excl++; + } + } + + if ((lvl & P(LVL, REM_CCE1)) || + (lvl & P(LVL, REM_CCE2))) { + if (snoop & P(SNOOP, HIT)) + stats->rmt_hit++; + else if (snoop & P(SNOOP, HITM)) + HITM_INC(rmt_hitm); + } + + if ((lvl & P(LVL, MISS))) + stats->ld_miss++; + + } else if (op & P(OP, STORE)) { + /* store */ + stats->store++; + + if (!daddr) { + stats->st_noadrs++; + return -1; + } + + if (lvl & P(LVL, HIT)) { + if (lvl & P(LVL, UNC)) stats->st_uncache++; + if (lvl & P(LVL, L1 )) stats->st_l1hit++; + } + if (lvl & P(LVL, MISS)) + if (lvl & P(LVL, L1)) stats->st_l1miss++; + } else { + /* unparsable data_src? */ + stats->noparse++; + return -1; + } + + if (!mi->daddr.map || !mi->iaddr.map) { + stats->nomap++; + return -1; + } + +#undef P +#undef HITM_INC + return err; +} + +void c2c_add_stats(struct c2c_stats *stats, struct c2c_stats *add) +{ + stats->nr_entries += add->nr_entries; + + stats->locks += add->locks; + stats->store += add->store; + stats->st_uncache += add->st_uncache; + stats->st_noadrs += add->st_noadrs; + stats->st_l1hit += add->st_l1hit; + stats->st_l1miss += add->st_l1miss; + stats->load += add->load; + stats->ld_excl += add->ld_excl; + stats->ld_shared += add->ld_shared; + stats->ld_uncache += add->ld_uncache; + stats->ld_io += add->ld_io; + stats->ld_miss += add->ld_miss; + stats->ld_noadrs += add->ld_noadrs; + stats->ld_fbhit += add->ld_fbhit; + stats->ld_l1hit += add->ld_l1hit; + stats->ld_l2hit += add->ld_l2hit; + stats->ld_llchit += add->ld_llchit; + stats->lcl_hitm += add->lcl_hitm; + stats->rmt_hitm += add->rmt_hitm; + stats->tot_hitm += add->tot_hitm; + stats->rmt_hit += add->rmt_hit; + stats->lcl_dram += add->lcl_dram; + stats->rmt_dram += add->rmt_dram; + stats->nomap += add->nomap; + stats->noparse += add->noparse; +} diff --git a/tools/perf/util/mem-events.h b/tools/perf/util/mem-events.h index 7f69bf9d789d..40f72ee4f42a 100644 --- a/tools/perf/util/mem-events.h +++ b/tools/perf/util/mem-events.h @@ -2,6 +2,10 @@ #define __PERF_MEM_EVENTS_H #include <stdbool.h> +#include <stdint.h> +#include <stdio.h> +#include <linux/types.h> +#include "stat.h" struct perf_mem_event { bool record; @@ -33,4 +37,38 @@ int perf_mem__lck_scnprintf(char *out, size_t sz, struct mem_info *mem_info); int perf_script__meminfo_scnprintf(char *bf, size_t size, struct mem_info *mem_info); +struct c2c_stats { + u32 nr_entries; + + u32 locks; /* count of 'lock' transactions */ + u32 store; /* count of all stores in trace */ + u32 st_uncache; /* stores to uncacheable address */ + u32 st_noadrs; /* cacheable store with no address */ + u32 st_l1hit; /* count of stores that hit L1D */ + u32 st_l1miss; /* count of stores that miss L1D */ + u32 load; /* count of all loads in trace */ + u32 ld_excl; /* exclusive loads, rmt/lcl DRAM - snp none/miss */ + u32 ld_shared; /* shared loads, rmt/lcl DRAM - snp hit */ + u32 ld_uncache; /* loads to uncacheable address */ + u32 ld_io; /* loads to io address */ + u32 ld_miss; /* loads miss */ + u32 ld_noadrs; /* cacheable load with no address */ + u32 ld_fbhit; /* count of loads hitting Fill Buffer */ + u32 ld_l1hit; /* count of loads that hit L1D */ + u32 ld_l2hit; /* count of loads that hit L2D */ + u32 ld_llchit; /* count of loads that hit LLC */ + u32 lcl_hitm; /* count of loads with local HITM */ + u32 rmt_hitm; /* count of loads with remote HITM */ + u32 tot_hitm; /* count of loads with local and remote HITM */ + u32 rmt_hit; /* count of loads with remote hit clean; */ + u32 lcl_dram; /* count of loads miss to local DRAM */ + u32 rmt_dram; /* count of loads miss to remote DRAM */ + u32 nomap; /* count of load/stores with no phys adrs */ + u32 noparse; /* count of unparsable data sources */ +}; + +struct hist_entry; +int c2c_decode_stats(struct c2c_stats *stats, struct mem_info *mi); +void c2c_add_stats(struct c2c_stats *stats, struct c2c_stats *add); + #endif /* __PERF_MEM_EVENTS_H */ diff --git a/tools/perf/util/parse-branch-options.c b/tools/perf/util/parse-branch-options.c index afc088dd7d20..38fd11504015 100644 --- a/tools/perf/util/parse-branch-options.c +++ b/tools/perf/util/parse-branch-options.c @@ -31,59 +31,51 @@ static const struct branch_mode branch_modes[] = { BRANCH_END }; -int -parse_branch_stack(const struct option *opt, const char *str, int unset) +int parse_branch_str(const char *str, __u64 *mode) { #define ONLY_PLM \ (PERF_SAMPLE_BRANCH_USER |\ PERF_SAMPLE_BRANCH_KERNEL |\ PERF_SAMPLE_BRANCH_HV) - uint64_t *mode = (uint64_t *)opt->value; + int ret = 0; + char *p, *s; + char *os = NULL; const struct branch_mode *br; - char *s, *os = NULL, *p; - int ret = -1; - if (unset) + if (str == NULL) { + *mode = PERF_SAMPLE_BRANCH_ANY; return 0; + } - /* - * cannot set it twice, -b + --branch-filter for instance - */ - if (*mode) + /* because str is read-only */ + s = os = strdup(str); + if (!s) return -1; - /* str may be NULL in case no arg is passed to -b */ - if (str) { - /* because str is read-only */ - s = os = strdup(str); - if (!s) - return -1; - - for (;;) { - p = strchr(s, ','); - if (p) - *p = '\0'; - - for (br = branch_modes; br->name; br++) { - if (!strcasecmp(s, br->name)) - break; - } - if (!br->name) { - ui__warning("unknown branch filter %s," - " check man page\n", s); - goto error; - } - - *mode |= br->mode; - - if (!p) - break; + for (;;) { + p = strchr(s, ','); + if (p) + *p = '\0'; - s = p + 1; + for (br = branch_modes; br->name; br++) { + if (!strcasecmp(s, br->name)) + break; + } + if (!br->name) { + ret = -1; + pr_warning("unknown branch filter %s," + " check man page\n", s); + goto error; } + + *mode |= br->mode; + + if (!p) + break; + + s = p + 1; } - ret = 0; /* default to any branch */ if ((*mode & ~ONLY_PLM) == 0) { @@ -93,3 +85,20 @@ error: free(os); return ret; } + +int +parse_branch_stack(const struct option *opt, const char *str, int unset) +{ + __u64 *mode = (__u64 *)opt->value; + + if (unset) + return 0; + + /* + * cannot set it twice, -b + --branch-filter for instance + */ + if (*mode) + return -1; + + return parse_branch_str(str, mode); +} diff --git a/tools/perf/util/parse-branch-options.h b/tools/perf/util/parse-branch-options.h index b9d9470c2e82..6086fd90eb23 100644 --- a/tools/perf/util/parse-branch-options.h +++ b/tools/perf/util/parse-branch-options.h @@ -1,5 +1,6 @@ #ifndef _PERF_PARSE_BRANCH_OPTIONS_H #define _PERF_PARSE_BRANCH_OPTIONS_H 1 -struct option; +#include <stdint.h> int parse_branch_stack(const struct option *opt, const char *str, int unset); +int parse_branch_str(const char *str, __u64 *mode); #endif /* _PERF_PARSE_BRANCH_OPTIONS_H */ diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index 4e778eae1510..3c876b8ba4de 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -22,6 +22,7 @@ #include "cpumap.h" #include "probe-file.h" #include "asm/bug.h" +#include "util/parse-branch-options.h" #define MAX_NAME_LEN 100 @@ -973,10 +974,13 @@ do { \ CHECK_TYPE_VAL(NUM); break; case PARSE_EVENTS__TERM_TYPE_BRANCH_SAMPLE_TYPE: - /* - * TODO uncomment when the field is available - * attr->branch_sample_type = term->val.num; - */ + CHECK_TYPE_VAL(STR); + if (strcmp(term->val.str, "no") && + parse_branch_str(term->val.str, &attr->branch_sample_type)) { + err->str = strdup("invalid branch sample type"); + err->idx = term->err_val; + return -EINVAL; + } break; case PARSE_EVENTS__TERM_TYPE_TIME: CHECK_TYPE_VAL(NUM); @@ -1119,6 +1123,9 @@ do { \ case PARSE_EVENTS__TERM_TYPE_CALLGRAPH: ADD_CONFIG_TERM(CALLGRAPH, callgraph, term->val.str); break; + case PARSE_EVENTS__TERM_TYPE_BRANCH_SAMPLE_TYPE: + ADD_CONFIG_TERM(BRANCH, branch, term->val.str); + break; case PARSE_EVENTS__TERM_TYPE_STACKSIZE: ADD_CONFIG_TERM(STACK_USER, stack_user, term->val.num); break; diff --git a/tools/perf/util/perf-hooks-list.h b/tools/perf/util/perf-hooks-list.h new file mode 100644 index 000000000000..2867c07ee84e --- /dev/null +++ b/tools/perf/util/perf-hooks-list.h @@ -0,0 +1,3 @@ +PERF_HOOK(record_start) +PERF_HOOK(record_end) +PERF_HOOK(test) diff --git a/tools/perf/util/perf-hooks.c b/tools/perf/util/perf-hooks.c new file mode 100644 index 000000000000..cb368306b12b --- /dev/null +++ b/tools/perf/util/perf-hooks.c @@ -0,0 +1,88 @@ +/* + * perf_hooks.c + * + * Copyright (C) 2016 Wang Nan <wangnan0@huawei.com> + * Copyright (C) 2016 Huawei Inc. + */ + +#include <errno.h> +#include <stdlib.h> +#include <setjmp.h> +#include <linux/err.h> +#include "util/util.h" +#include "util/debug.h" +#include "util/perf-hooks.h" + +static sigjmp_buf jmpbuf; +static const struct perf_hook_desc *current_perf_hook; + +void perf_hooks__invoke(const struct perf_hook_desc *desc) +{ + if (!(desc && desc->p_hook_func && *desc->p_hook_func)) + return; + + if (sigsetjmp(jmpbuf, 1)) { + pr_warning("Fatal error (SEGFAULT) in perf hook '%s'\n", + desc->hook_name); + *(current_perf_hook->p_hook_func) = NULL; + } else { + current_perf_hook = desc; + (**desc->p_hook_func)(desc->hook_ctx); + } + current_perf_hook = NULL; +} + +void perf_hooks__recover(void) +{ + if (current_perf_hook) + siglongjmp(jmpbuf, 1); +} + +#define PERF_HOOK(name) \ +perf_hook_func_t __perf_hook_func_##name = NULL; \ +struct perf_hook_desc __perf_hook_desc_##name = \ + {.hook_name = #name, \ + .p_hook_func = &__perf_hook_func_##name, \ + .hook_ctx = NULL}; +#include "perf-hooks-list.h" +#undef PERF_HOOK + +#define PERF_HOOK(name) \ + &__perf_hook_desc_##name, + +static struct perf_hook_desc *perf_hooks[] = { +#include "perf-hooks-list.h" +}; +#undef PERF_HOOK + +int perf_hooks__set_hook(const char *hook_name, + perf_hook_func_t hook_func, + void *hook_ctx) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(perf_hooks); i++) { + if (strcmp(hook_name, perf_hooks[i]->hook_name) != 0) + continue; + + if (*(perf_hooks[i]->p_hook_func)) + pr_warning("Overwrite existing hook: %s\n", hook_name); + *(perf_hooks[i]->p_hook_func) = hook_func; + perf_hooks[i]->hook_ctx = hook_ctx; + return 0; + } + return -ENOENT; +} + +perf_hook_func_t perf_hooks__get_hook(const char *hook_name) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(perf_hooks); i++) { + if (strcmp(hook_name, perf_hooks[i]->hook_name) != 0) + continue; + + return *(perf_hooks[i]->p_hook_func); + } + return ERR_PTR(-ENOENT); +} diff --git a/tools/perf/util/perf-hooks.h b/tools/perf/util/perf-hooks.h new file mode 100644 index 000000000000..838d5797bc1e --- /dev/null +++ b/tools/perf/util/perf-hooks.h @@ -0,0 +1,39 @@ +#ifndef PERF_UTIL_PERF_HOOKS_H +#define PERF_UTIL_PERF_HOOKS_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef void (*perf_hook_func_t)(void *ctx); +struct perf_hook_desc { + const char * const hook_name; + perf_hook_func_t * const p_hook_func; + void *hook_ctx; +}; + +extern void perf_hooks__invoke(const struct perf_hook_desc *); +extern void perf_hooks__recover(void); + +#define PERF_HOOK(name) \ +extern struct perf_hook_desc __perf_hook_desc_##name; \ +static inline void perf_hooks__invoke_##name(void) \ +{ \ + perf_hooks__invoke(&__perf_hook_desc_##name); \ +} + +#include "perf-hooks-list.h" +#undef PERF_HOOK + +extern int +perf_hooks__set_hook(const char *hook_name, + perf_hook_func_t hook_func, + void *hook_ctx); + +extern perf_hook_func_t +perf_hooks__get_hook(const char *hook_name); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index b1474dcadfa2..dc6ccaa4e927 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -504,6 +504,7 @@ static void pmu_add_cpu_aliases(struct list_head *head) struct pmu_events_map *map; struct pmu_event *pe; char *cpuid; + static bool printed; cpuid = getenv("PERF_CPUID"); if (cpuid) @@ -513,7 +514,10 @@ static void pmu_add_cpu_aliases(struct list_head *head) if (!cpuid) return; - pr_debug("Using CPUID %s\n", cpuid); + if (!printed) { + pr_debug("Using CPUID %s\n", cpuid); + printed = true; + } i = 0; while (1) { @@ -1135,9 +1139,11 @@ void print_pmu_events(const char *event_glob, bool name_only, bool quiet_flag, bool is_cpu = !strcmp(pmu->name, "cpu"); if (event_glob != NULL && - !(strglobmatch(name, event_glob) || - (!is_cpu && strglobmatch(alias->name, - event_glob)))) + !(strglobmatch_nocase(name, event_glob) || + (!is_cpu && strglobmatch_nocase(alias->name, + event_glob)) || + (alias->topic && + strglobmatch_nocase(alias->topic, event_glob)))) continue; if (is_cpu && !name_only && !alias->desc) diff --git a/tools/perf/util/probe-event.h b/tools/perf/util/probe-event.h index 8091d15113f7..5d4e94061402 100644 --- a/tools/perf/util/probe-event.h +++ b/tools/perf/util/probe-event.h @@ -18,6 +18,8 @@ struct probe_conf { extern struct probe_conf probe_conf; extern bool probe_event_dry_run; +struct symbol; + /* kprobe-tracer and uprobe-tracer tracing point */ struct probe_trace_point { char *realname; /* function real name (if needed) */ diff --git a/tools/perf/util/python-ext-sources b/tools/perf/util/python-ext-sources index b7d4f4aeee61..0546a4304347 100644 --- a/tools/perf/util/python-ext-sources +++ b/tools/perf/util/python-ext-sources @@ -18,6 +18,7 @@ util/thread_map.c util/util.c util/xyarray.c util/cgroup.c +util/parse-branch-options.c util/rblist.c util/counts.c util/strlist.c diff --git a/tools/perf/util/quote.c b/tools/perf/util/quote.c index 639d1da2f978..293534c1a474 100644 --- a/tools/perf/util/quote.c +++ b/tools/perf/util/quote.c @@ -54,7 +54,7 @@ int sq_quote_argv(struct strbuf *dst, const char** argv, size_t maxlen) break; ret = sq_quote_buf(dst, argv[i]); if (maxlen && dst->len > maxlen) - die("Too many or long arguments"); + return -ENOSPC; } return ret; } diff --git a/tools/perf/util/session.c b/tools/perf/util/session.c index 5d61242a6e64..f268201048a0 100644 --- a/tools/perf/util/session.c +++ b/tools/perf/util/session.c @@ -2025,20 +2025,10 @@ out_delete_map: void perf_session__fprintf_info(struct perf_session *session, FILE *fp, bool full) { - struct stat st; - int fd, ret; - if (session == NULL || fp == NULL) return; - fd = perf_data_file__fd(session->file); - - ret = fstat(fd, &st); - if (ret == -1) - return; - fprintf(fp, "# ========\n"); - fprintf(fp, "# captured on: %s", ctime(&st.st_ctime)); perf_header__fprintf_info(session, fp, full); fprintf(fp, "# ========\n#\n"); } diff --git a/tools/perf/util/sort.c b/tools/perf/util/sort.c index 452e15a10dd2..df622f4e301e 100644 --- a/tools/perf/util/sort.c +++ b/tools/perf/util/sort.c @@ -315,7 +315,7 @@ struct sort_entry sort_sym = { /* --sort srcline */ -static char *hist_entry__get_srcline(struct hist_entry *he) +char *hist_entry__get_srcline(struct hist_entry *he) { struct map *map = he->ms.map; diff --git a/tools/perf/util/sort.h b/tools/perf/util/sort.h index 099c97557d33..7aff317fc7c4 100644 --- a/tools/perf/util/sort.h +++ b/tools/perf/util/sort.h @@ -280,4 +280,5 @@ int64_t sort__daddr_cmp(struct hist_entry *left, struct hist_entry *right); int64_t sort__dcacheline_cmp(struct hist_entry *left, struct hist_entry *right); +char *hist_entry__get_srcline(struct hist_entry *he); #endif /* __PERF_SORT_H */ diff --git a/tools/perf/util/string.c b/tools/perf/util/string.c index 7f7e072be746..d8dfaf64b32e 100644 --- a/tools/perf/util/string.c +++ b/tools/perf/util/string.c @@ -193,7 +193,8 @@ error: } /* Glob/lazy pattern matching */ -static bool __match_glob(const char *str, const char *pat, bool ignore_space) +static bool __match_glob(const char *str, const char *pat, bool ignore_space, + bool case_ins) { while (*str && *pat && *pat != '*') { if (ignore_space) { @@ -219,8 +220,13 @@ static bool __match_glob(const char *str, const char *pat, bool ignore_space) return false; else if (*pat == '\\') /* Escaped char match as normal char */ pat++; - if (*str++ != *pat++) + if (case_ins) { + if (tolower(*str) != tolower(*pat)) + return false; + } else if (*str != *pat) return false; + str++; + pat++; } /* Check wild card */ if (*pat == '*') { @@ -229,7 +235,7 @@ static bool __match_glob(const char *str, const char *pat, bool ignore_space) if (!*pat) /* Tail wild card matches all */ return true; while (*str) - if (__match_glob(str++, pat, ignore_space)) + if (__match_glob(str++, pat, ignore_space, case_ins)) return true; } return !*str && !*pat; @@ -249,7 +255,12 @@ static bool __match_glob(const char *str, const char *pat, bool ignore_space) */ bool strglobmatch(const char *str, const char *pat) { - return __match_glob(str, pat, false); + return __match_glob(str, pat, false, false); +} + +bool strglobmatch_nocase(const char *str, const char *pat) +{ + return __match_glob(str, pat, false, true); } /** @@ -262,7 +273,7 @@ bool strglobmatch(const char *str, const char *pat) */ bool strlazymatch(const char *str, const char *pat) { - return __match_glob(str, pat, true); + return __match_glob(str, pat, true, false); } /** diff --git a/tools/perf/util/symbol.c b/tools/perf/util/symbol.c index aecff69a510d..df2482b2ba45 100644 --- a/tools/perf/util/symbol.c +++ b/tools/perf/util/symbol.c @@ -1962,7 +1962,7 @@ static bool symbol__read_kptr_restrict(void) char line[8]; if (fgets(line, sizeof(line), fp) != NULL) - value = (geteuid() != 0) ? + value = ((geteuid() != 0) || (getuid() != 0)) ? (atoi(line) != 0) : (atoi(line) == 2); @@ -2032,6 +2032,10 @@ int symbol__init(struct perf_env *env) symbol_conf.sym_list_str, "symbol") < 0) goto out_free_tid_list; + if (setup_list(&symbol_conf.bt_stop_list, + symbol_conf.bt_stop_list_str, "symbol") < 0) + goto out_free_sym_list; + /* * A path to symbols of "/" is identical to "" * reset here for simplicity. @@ -2049,6 +2053,8 @@ int symbol__init(struct perf_env *env) symbol_conf.initialized = true; return 0; +out_free_sym_list: + strlist__delete(symbol_conf.sym_list); out_free_tid_list: intlist__delete(symbol_conf.tid_list); out_free_pid_list: @@ -2064,6 +2070,7 @@ void symbol__exit(void) { if (!symbol_conf.initialized) return; + strlist__delete(symbol_conf.bt_stop_list); strlist__delete(symbol_conf.sym_list); strlist__delete(symbol_conf.dso_list); strlist__delete(symbol_conf.comm_list); @@ -2071,6 +2078,7 @@ void symbol__exit(void) intlist__delete(symbol_conf.pid_list); vmlinux_path__exit(); symbol_conf.sym_list = symbol_conf.dso_list = symbol_conf.comm_list = NULL; + symbol_conf.bt_stop_list = NULL; symbol_conf.initialized = false; } diff --git a/tools/perf/util/symbol.h b/tools/perf/util/symbol.h index d964844eb314..6c358b7ed336 100644 --- a/tools/perf/util/symbol.h +++ b/tools/perf/util/symbol.h @@ -58,6 +58,7 @@ struct symbol { u16 namelen; u8 binding; u8 idle:1; + u8 ignore:1; u8 arch_sym; char name[0]; }; @@ -100,6 +101,7 @@ struct symbol_conf { show_total_period, use_callchain, cumulate_callchain, + show_branchflag_count, exclude_other, show_cpu_utilization, initialized, @@ -130,14 +132,16 @@ struct symbol_conf { *pid_list_str, *tid_list_str, *sym_list_str, - *col_width_list_str; + *col_width_list_str, + *bt_stop_list_str; struct strlist *dso_list, *comm_list, *sym_list, *dso_from_list, *dso_to_list, *sym_from_list, - *sym_to_list; + *sym_to_list, + *bt_stop_list; struct intlist *pid_list, *tid_list; const char *symfs; @@ -281,7 +285,8 @@ int symbol__annotation_init(void); struct symbol *symbol__new(u64 start, u64 len, u8 binding, const char *name); size_t __symbol__fprintf_symname_offs(const struct symbol *sym, const struct addr_location *al, - bool unknown_as_addr, FILE *fp); + bool unknown_as_addr, + bool print_offsets, FILE *fp); size_t symbol__fprintf_symname_offs(const struct symbol *sym, const struct addr_location *al, FILE *fp); size_t __symbol__fprintf_symname(const struct symbol *sym, diff --git a/tools/perf/util/symbol_fprintf.c b/tools/perf/util/symbol_fprintf.c index a680bdaa65dc..7c6b33e8e2d2 100644 --- a/tools/perf/util/symbol_fprintf.c +++ b/tools/perf/util/symbol_fprintf.c @@ -15,14 +15,15 @@ size_t symbol__fprintf(struct symbol *sym, FILE *fp) size_t __symbol__fprintf_symname_offs(const struct symbol *sym, const struct addr_location *al, - bool unknown_as_addr, FILE *fp) + bool unknown_as_addr, + bool print_offsets, FILE *fp) { unsigned long offset; size_t length; if (sym && sym->name) { length = fprintf(fp, "%s", sym->name); - if (al) { + if (al && print_offsets) { if (al->addr < sym->end) offset = al->addr - sym->start; else @@ -40,19 +41,19 @@ size_t symbol__fprintf_symname_offs(const struct symbol *sym, const struct addr_location *al, FILE *fp) { - return __symbol__fprintf_symname_offs(sym, al, false, fp); + return __symbol__fprintf_symname_offs(sym, al, false, true, fp); } size_t __symbol__fprintf_symname(const struct symbol *sym, const struct addr_location *al, bool unknown_as_addr, FILE *fp) { - return __symbol__fprintf_symname_offs(sym, al, unknown_as_addr, fp); + return __symbol__fprintf_symname_offs(sym, al, unknown_as_addr, false, fp); } size_t symbol__fprintf_symname(const struct symbol *sym, FILE *fp) { - return __symbol__fprintf_symname_offs(sym, NULL, false, fp); + return __symbol__fprintf_symname_offs(sym, NULL, false, false, fp); } size_t dso__fprintf_symbols_by_name(struct dso *dso, diff --git a/tools/perf/util/time-utils.c b/tools/perf/util/time-utils.c new file mode 100644 index 000000000000..d1b21c72206d --- /dev/null +++ b/tools/perf/util/time-utils.c @@ -0,0 +1,119 @@ +#include <stdlib.h> +#include <string.h> +#include <sys/time.h> +#include <linux/time64.h> +#include <time.h> +#include <errno.h> +#include <inttypes.h> + +#include "perf.h" +#include "debug.h" +#include "time-utils.h" + +int parse_nsec_time(const char *str, u64 *ptime) +{ + u64 time_sec, time_nsec; + char *end; + + time_sec = strtoul(str, &end, 10); + if (*end != '.' && *end != '\0') + return -1; + + if (*end == '.') { + int i; + char nsec_buf[10]; + + if (strlen(++end) > 9) + return -1; + + strncpy(nsec_buf, end, 9); + nsec_buf[9] = '\0'; + + /* make it nsec precision */ + for (i = strlen(nsec_buf); i < 9; i++) + nsec_buf[i] = '0'; + + time_nsec = strtoul(nsec_buf, &end, 10); + if (*end != '\0') + return -1; + } else + time_nsec = 0; + + *ptime = time_sec * NSEC_PER_SEC + time_nsec; + return 0; +} + +static int parse_timestr_sec_nsec(struct perf_time_interval *ptime, + char *start_str, char *end_str) +{ + if (start_str && (*start_str != '\0') && + (parse_nsec_time(start_str, &ptime->start) != 0)) { + return -1; + } + + if (end_str && (*end_str != '\0') && + (parse_nsec_time(end_str, &ptime->end) != 0)) { + return -1; + } + + return 0; +} + +int perf_time__parse_str(struct perf_time_interval *ptime, const char *ostr) +{ + char *start_str, *end_str; + char *d, *str; + int rc = 0; + + if (ostr == NULL || *ostr == '\0') + return 0; + + /* copy original string because we need to modify it */ + str = strdup(ostr); + if (str == NULL) + return -ENOMEM; + + ptime->start = 0; + ptime->end = 0; + + /* str has the format: <start>,<stop> + * variations: <start>, + * ,<stop> + * , + */ + start_str = str; + d = strchr(start_str, ','); + if (d) { + *d = '\0'; + ++d; + } + end_str = d; + + rc = parse_timestr_sec_nsec(ptime, start_str, end_str); + + free(str); + + /* make sure end time is after start time if it was given */ + if (rc == 0 && ptime->end && ptime->end < ptime->start) + return -EINVAL; + + pr_debug("start time %" PRIu64 ", ", ptime->start); + pr_debug("end time %" PRIu64 "\n", ptime->end); + + return rc; +} + +bool perf_time__skip_sample(struct perf_time_interval *ptime, u64 timestamp) +{ + /* if time is not set don't drop sample */ + if (timestamp == 0) + return false; + + /* otherwise compare sample time to time window */ + if ((ptime->start && timestamp < ptime->start) || + (ptime->end && timestamp > ptime->end)) { + return true; + } + + return false; +} diff --git a/tools/perf/util/time-utils.h b/tools/perf/util/time-utils.h new file mode 100644 index 000000000000..c1f197c4af6c --- /dev/null +++ b/tools/perf/util/time-utils.h @@ -0,0 +1,14 @@ +#ifndef _TIME_UTILS_H_ +#define _TIME_UTILS_H_ + +struct perf_time_interval { + u64 start, end; +}; + +int parse_nsec_time(const char *str, u64 *ptime); + +int perf_time__parse_str(struct perf_time_interval *ptime, const char *ostr); + +bool perf_time__skip_sample(struct perf_time_interval *ptime, u64 timestamp); + +#endif diff --git a/tools/perf/util/trace-event-scripting.c b/tools/perf/util/trace-event-scripting.c index 9df61059a85d..0ac9077f62a2 100644 --- a/tools/perf/util/trace-event-scripting.c +++ b/tools/perf/util/trace-event-scripting.c @@ -25,6 +25,7 @@ #include <errno.h> #include "../perf.h" +#include "debug.h" #include "util.h" #include "trace-event.h" @@ -86,16 +87,15 @@ struct scripting_ops python_scripting_unsupported_ops = { static void register_python_scripting(struct scripting_ops *scripting_ops) { - int err; - err = script_spec_register("Python", scripting_ops); - if (err) - die("error registering Python script extension"); - - err = script_spec_register("py", scripting_ops); - if (err) - die("error registering py script extension"); - - scripting_context = malloc(sizeof(struct scripting_context)); + if (scripting_context == NULL) + scripting_context = malloc(sizeof(*scripting_context)); + + if (scripting_context == NULL || + script_spec_register("Python", scripting_ops) || + script_spec_register("py", scripting_ops)) { + pr_err("Error registering Python script extension: disabling it\n"); + zfree(&scripting_context); + } } #ifdef NO_LIBPYTHON @@ -150,16 +150,15 @@ struct scripting_ops perl_scripting_unsupported_ops = { static void register_perl_scripting(struct scripting_ops *scripting_ops) { - int err; - err = script_spec_register("Perl", scripting_ops); - if (err) - die("error registering Perl script extension"); - - err = script_spec_register("pl", scripting_ops); - if (err) - die("error registering pl script extension"); - - scripting_context = malloc(sizeof(struct scripting_context)); + if (scripting_context == NULL) + scripting_context = malloc(sizeof(*scripting_context)); + + if (scripting_context == NULL || + script_spec_register("Perl", scripting_ops) || + script_spec_register("pl", scripting_ops)) { + pr_err("Error registering Perl script extension: disabling it\n"); + zfree(&scripting_context); + } } #ifdef NO_LIBPERL diff --git a/tools/perf/util/unwind-libunwind-local.c b/tools/perf/util/unwind-libunwind-local.c index 20c2e5743903..6fec84dff3f7 100644 --- a/tools/perf/util/unwind-libunwind-local.c +++ b/tools/perf/util/unwind-libunwind-local.c @@ -357,8 +357,8 @@ find_proc_info(unw_addr_space_t as, unw_word_t ip, unw_proc_info_t *pi, di.format = UNW_INFO_FORMAT_REMOTE_TABLE; di.start_ip = map->start; di.end_ip = map->end; - di.u.rti.segbase = map->start + segbase; - di.u.rti.table_data = map->start + table_data; + di.u.rti.segbase = map->start + segbase - map->pgoff; + di.u.rti.table_data = map->start + table_data - map->pgoff; di.u.rti.table_len = fde_count * sizeof(struct table_entry) / sizeof(unw_word_t); ret = dwarf_search_unwind_table(as, ip, &di, pi, diff --git a/tools/perf/util/util-cxx.h b/tools/perf/util/util-cxx.h new file mode 100644 index 000000000000..0e0e019c9f34 --- /dev/null +++ b/tools/perf/util/util-cxx.h @@ -0,0 +1,26 @@ +/* + * Support C++ source use utilities defined in util.h + */ + +#ifndef PERF_UTIL_UTIL_CXX_H +#define PERF_UTIL_UTIL_CXX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Now 'new' is the only C++ keyword found in util.h: + * in tools/include/linux/rbtree.h + * + * Other keywords, like class and delete, should be + * redefined if necessary. + */ +#define new _new +#include "util.h" +#undef new + +#ifdef __cplusplus +} +#endif +#endif diff --git a/tools/perf/util/util.c b/tools/perf/util/util.c index 85c56800f17a..9ddd98827d12 100644 --- a/tools/perf/util/util.c +++ b/tools/perf/util/util.c @@ -400,37 +400,12 @@ void sighandler_dump_stack(int sig) raise(sig); } -int parse_nsec_time(const char *str, u64 *ptime) +int timestamp__scnprintf_usec(u64 timestamp, char *buf, size_t sz) { - u64 time_sec, time_nsec; - char *end; + u64 sec = timestamp / NSEC_PER_SEC; + u64 usec = (timestamp % NSEC_PER_SEC) / NSEC_PER_USEC; - time_sec = strtoul(str, &end, 10); - if (*end != '.' && *end != '\0') - return -1; - - if (*end == '.') { - int i; - char nsec_buf[10]; - - if (strlen(++end) > 9) - return -1; - - strncpy(nsec_buf, end, 9); - nsec_buf[9] = '\0'; - - /* make it nsec precision */ - for (i = strlen(nsec_buf); i < 9; i++) - nsec_buf[i] = '0'; - - time_nsec = strtoul(nsec_buf, &end, 10); - if (*end != '\0') - return -1; - } else - time_nsec = 0; - - *ptime = time_sec * NSEC_PER_SEC + time_nsec; - return 0; + return scnprintf(buf, sz, "%"PRIu64".%06"PRIu64, sec, usec); } unsigned long parse_tag_value(const char *str, struct parse_tag *tags) @@ -629,12 +604,63 @@ bool find_process(const char *name) return ret ? false : true; } +static int +fetch_ubuntu_kernel_version(unsigned int *puint) +{ + ssize_t len; + size_t line_len = 0; + char *ptr, *line = NULL; + int version, patchlevel, sublevel, err; + FILE *vsig = fopen("/proc/version_signature", "r"); + + if (!vsig) { + pr_debug("Open /proc/version_signature failed: %s\n", + strerror(errno)); + return -1; + } + + len = getline(&line, &line_len, vsig); + fclose(vsig); + err = -1; + if (len <= 0) { + pr_debug("Reading from /proc/version_signature failed: %s\n", + strerror(errno)); + goto errout; + } + + ptr = strrchr(line, ' '); + if (!ptr) { + pr_debug("Parsing /proc/version_signature failed: %s\n", line); + goto errout; + } + + err = sscanf(ptr + 1, "%d.%d.%d", + &version, &patchlevel, &sublevel); + if (err != 3) { + pr_debug("Unable to get kernel version from /proc/version_signature '%s'\n", + line); + goto errout; + } + + if (puint) + *puint = (version << 16) + (patchlevel << 8) + sublevel; + err = 0; +errout: + free(line); + return err; +} + int fetch_kernel_version(unsigned int *puint, char *str, size_t str_size) { struct utsname utsname; int version, patchlevel, sublevel, err; + bool int_ver_ready = false; + + if (access("/proc/version_signature", R_OK) == 0) + if (!fetch_ubuntu_kernel_version(puint)) + int_ver_ready = true; if (uname(&utsname)) return -1; @@ -648,12 +674,12 @@ fetch_kernel_version(unsigned int *puint, char *str, &version, &patchlevel, &sublevel); if (err != 3) { - pr_debug("Unablt to get kernel version from uname '%s'\n", + pr_debug("Unable to get kernel version from uname '%s'\n", utsname.release); return -1; } - if (puint) + if (puint && !int_ver_ready) *puint = (version << 16) + (patchlevel << 8) + sublevel; return 0; } diff --git a/tools/perf/util/util.h b/tools/perf/util/util.h index 43899e0d6fa1..1d639e38aa82 100644 --- a/tools/perf/util/util.h +++ b/tools/perf/util/util.h @@ -179,8 +179,6 @@ static inline void *zalloc(size_t size) #undef tolower #undef toupper -int parse_nsec_time(const char *str, u64 *ptime); - extern unsigned char sane_ctype[256]; #define GIT_SPACE 0x01 #define GIT_DIGIT 0x02 @@ -222,6 +220,7 @@ s64 perf_atoll(const char *str); char **argv_split(const char *str, int *argcp); void argv_free(char **argv); bool strglobmatch(const char *str, const char *pat); +bool strglobmatch_nocase(const char *str, const char *pat); bool strlazymatch(const char *str, const char *pat); static inline bool strisglob(const char *str) { @@ -361,4 +360,7 @@ extern int sched_getcpu(void); #endif int is_printable_array(char *p, unsigned int len); + +int timestamp__scnprintf_usec(u64 timestamp, char *buf, size_t sz); + #endif /* GIT_COMPAT_UTIL_H */ diff --git a/tools/perf/util/values.c b/tools/perf/util/values.c index 0fb3c1fcd3e6..5074be4ed467 100644 --- a/tools/perf/util/values.c +++ b/tools/perf/util/values.c @@ -2,15 +2,18 @@ #include "util.h" #include "values.h" +#include "debug.h" -void perf_read_values_init(struct perf_read_values *values) +int perf_read_values_init(struct perf_read_values *values) { values->threads_max = 16; values->pid = malloc(values->threads_max * sizeof(*values->pid)); values->tid = malloc(values->threads_max * sizeof(*values->tid)); values->value = malloc(values->threads_max * sizeof(*values->value)); - if (!values->pid || !values->tid || !values->value) - die("failed to allocate read_values threads arrays"); + if (!values->pid || !values->tid || !values->value) { + pr_debug("failed to allocate read_values threads arrays"); + goto out_free_pid; + } values->threads = 0; values->counters_max = 16; @@ -18,9 +21,22 @@ void perf_read_values_init(struct perf_read_values *values) * sizeof(*values->counterrawid)); values->countername = malloc(values->counters_max * sizeof(*values->countername)); - if (!values->counterrawid || !values->countername) - die("failed to allocate read_values counters arrays"); + if (!values->counterrawid || !values->countername) { + pr_debug("failed to allocate read_values counters arrays"); + goto out_free_counter; + } values->counters = 0; + + return 0; + +out_free_counter: + zfree(&values->counterrawid); + zfree(&values->countername); +out_free_pid: + zfree(&values->pid); + zfree(&values->tid); + zfree(&values->value); + return -ENOMEM; } void perf_read_values_destroy(struct perf_read_values *values) @@ -41,17 +57,27 @@ void perf_read_values_destroy(struct perf_read_values *values) zfree(&values->countername); } -static void perf_read_values__enlarge_threads(struct perf_read_values *values) +static int perf_read_values__enlarge_threads(struct perf_read_values *values) { - values->threads_max *= 2; - values->pid = realloc(values->pid, - values->threads_max * sizeof(*values->pid)); - values->tid = realloc(values->tid, - values->threads_max * sizeof(*values->tid)); - values->value = realloc(values->value, - values->threads_max * sizeof(*values->value)); - if (!values->pid || !values->tid || !values->value) - die("failed to enlarge read_values threads arrays"); + int nthreads_max = values->threads_max * 2; + void *npid = realloc(values->pid, nthreads_max * sizeof(*values->pid)), + *ntid = realloc(values->tid, nthreads_max * sizeof(*values->tid)), + *nvalue = realloc(values->value, nthreads_max * sizeof(*values->value)); + + if (!npid || !ntid || !nvalue) + goto out_err; + + values->threads_max = nthreads_max; + values->pid = npid; + values->tid = ntid; + values->value = nvalue; + return 0; +out_err: + free(npid); + free(ntid); + free(nvalue); + pr_debug("failed to enlarge read_values threads arrays"); + return -ENOMEM; } static int perf_read_values__findnew_thread(struct perf_read_values *values, @@ -63,15 +89,21 @@ static int perf_read_values__findnew_thread(struct perf_read_values *values, if (values->pid[i] == pid && values->tid[i] == tid) return i; - if (values->threads == values->threads_max) - perf_read_values__enlarge_threads(values); + if (values->threads == values->threads_max) { + i = perf_read_values__enlarge_threads(values); + if (i < 0) + return i; + } - i = values->threads++; + i = values->threads + 1; + values->value[i] = malloc(values->counters_max * sizeof(**values->value)); + if (!values->value[i]) { + pr_debug("failed to allocate read_values counters array"); + return -ENOMEM; + } values->pid[i] = pid; values->tid[i] = tid; - values->value[i] = malloc(values->counters_max * sizeof(**values->value)); - if (!values->value[i]) - die("failed to allocate read_values counters array"); + values->threads = i; return i; } @@ -115,16 +147,21 @@ static int perf_read_values__findnew_counter(struct perf_read_values *values, return i; } -void perf_read_values_add_value(struct perf_read_values *values, +int perf_read_values_add_value(struct perf_read_values *values, u32 pid, u32 tid, u64 rawid, const char *name, u64 value) { int tindex, cindex; tindex = perf_read_values__findnew_thread(values, pid, tid); + if (tindex < 0) + return tindex; cindex = perf_read_values__findnew_counter(values, rawid, name); + if (cindex < 0) + return cindex; values->value[tindex][cindex] = value; + return 0; } static void perf_read_values__display_pretty(FILE *fp, diff --git a/tools/perf/util/values.h b/tools/perf/util/values.h index b21a80c6cf8d..808ff9c73bf5 100644 --- a/tools/perf/util/values.h +++ b/tools/perf/util/values.h @@ -14,10 +14,10 @@ struct perf_read_values { u64 **value; }; -void perf_read_values_init(struct perf_read_values *values); +int perf_read_values_init(struct perf_read_values *values); void perf_read_values_destroy(struct perf_read_values *values); -void perf_read_values_add_value(struct perf_read_values *values, +int perf_read_values_add_value(struct perf_read_values *values, u32 pid, u32 tid, u64 rawid, const char *name, u64 value); |