diff options
| -rw-r--r-- | Documentation/devicetree/bindings/soc/zte/pd-2967xx.txt | 19 | ||||
| -rw-r--r-- | MAINTAINERS | 4 | ||||
| -rw-r--r-- | drivers/soc/Kconfig | 1 | ||||
| -rw-r--r-- | drivers/soc/Makefile | 1 | ||||
| -rw-r--r-- | drivers/soc/zte/Kconfig | 13 | ||||
| -rw-r--r-- | drivers/soc/zte/Makefile | 5 | ||||
| -rw-r--r-- | drivers/soc/zte/zx296718_pm_domains.c | 182 | ||||
| -rw-r--r-- | drivers/soc/zte/zx2967_pm_domains.c | 143 | ||||
| -rw-r--r-- | drivers/soc/zte/zx2967_pm_domains.h | 44 | ||||
| -rw-r--r-- | include/dt-bindings/soc/zte,pm_domains.h | 24 |
10 files changed, 436 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/soc/zte/pd-2967xx.txt b/Documentation/devicetree/bindings/soc/zte/pd-2967xx.txt new file mode 100644 index 000000000000..7629de1c2c72 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/zte/pd-2967xx.txt @@ -0,0 +1,19 @@ +* ZTE zx2967 family Power Domains + +zx2967 family includes support for multiple power domains which are used +to gate power to one or more peripherals on the processor. + +Required Properties: + - compatible: should be one of the following. + * zte,zx296718-pcu - for zx296718 power domain. + - reg: physical base address of the controller and length of memory mapped + region. + - #power-domain-cells: Must be 1. + +Example: + + pcu_domain: pcu@117000 { + compatible = "zte,zx296718-pcu"; + reg = <0x00117000 0x1000>; + #power-domain-cells = <1>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 33c0e0d17650..e4874cc6b1b9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1982,14 +1982,18 @@ F: arch/arm/mach-pxa/include/mach/z2.h ARM/ZTE ARCHITECTURE M: Jun Nie <jun.nie@linaro.org> +M: Baoyou Xie <baoyou.xie@linaro.org> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: arch/arm/mach-zx/ F: drivers/clk/zte/ F: drivers/reset/reset-zx2967.c +F: drivers/soc/zte/ F: Documentation/devicetree/bindings/arm/zte.txt F: Documentation/devicetree/bindings/clock/zx296702-clk.txt F: Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt +F: Documentation/devicetree/bindings/soc/zte/ +F: include/dt-bindings/soc/zx*.h ARM/ZYNQ ARCHITECTURE M: Michal Simek <michal.simek@xilinx.com> diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index f31bceb69c0d..f09023f7ab11 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -11,5 +11,6 @@ source "drivers/soc/tegra/Kconfig" source "drivers/soc/ti/Kconfig" source "drivers/soc/ux500/Kconfig" source "drivers/soc/versatile/Kconfig" +source "drivers/soc/zte/Kconfig" endmenu diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 50c23d0bd457..05eae52a30b4 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -16,3 +16,4 @@ obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-$(CONFIG_SOC_TI) += ti/ obj-$(CONFIG_ARCH_U8500) += ux500/ obj-$(CONFIG_PLAT_VERSATILE) += versatile/ +obj-$(CONFIG_ARCH_ZX) += zte/ diff --git a/drivers/soc/zte/Kconfig b/drivers/soc/zte/Kconfig new file mode 100644 index 000000000000..20bde38ce2f9 --- /dev/null +++ b/drivers/soc/zte/Kconfig @@ -0,0 +1,13 @@ +# +# ZTE SoC drivers +# +menuconfig SOC_ZTE + bool "ZTE SoC driver support" + +if SOC_ZTE + +config ZX2967_PM_DOMAINS + bool "ZX2967 PM domains" + depends on PM_GENERIC_DOMAINS + +endif diff --git a/drivers/soc/zte/Makefile b/drivers/soc/zte/Makefile new file mode 100644 index 000000000000..96b7cd4c9629 --- /dev/null +++ b/drivers/soc/zte/Makefile @@ -0,0 +1,5 @@ +# +# ZTE SOC drivers +# +obj-$(CONFIG_ZX2967_PM_DOMAINS) += zx2967_pm_domains.o +obj-$(CONFIG_ZX2967_PM_DOMAINS) += zx296718_pm_domains.o diff --git a/drivers/soc/zte/zx296718_pm_domains.c b/drivers/soc/zte/zx296718_pm_domains.c new file mode 100644 index 000000000000..5ed924fee855 --- /dev/null +++ b/drivers/soc/zte/zx296718_pm_domains.c @@ -0,0 +1,182 @@ +/* + * Copyright (C) 2017 ZTE Ltd. + * + * Author: Baoyou Xie <baoyou.xie@linaro.org> + * License terms: GNU General Public License (GPL) version 2 + */ + +#include <dt-bindings/soc/zte,pm_domains.h> +#include "zx2967_pm_domains.h" + +static u16 zx296718_offsets[REG_ARRAY_SIZE] = { + [REG_CLKEN] = 0x18, + [REG_ISOEN] = 0x1c, + [REG_RSTEN] = 0x20, + [REG_PWREN] = 0x24, + [REG_ACK_SYNC] = 0x28, +}; + +enum { + PCU_DM_VOU = 0, + PCU_DM_SAPPU, + PCU_DM_VDE, + PCU_DM_VCE, + PCU_DM_HDE, + PCU_DM_VIU, + PCU_DM_USB20, + PCU_DM_USB21, + PCU_DM_USB30, + PCU_DM_HSIC, + PCU_DM_GMAC, + PCU_DM_TS, +}; + +static struct zx2967_pm_domain vou_domain = { + .dm = { + .name = "vou_domain", + }, + .bit = PCU_DM_VOU, + .polarity = PWREN, + .reg_offset = zx296718_offsets, +}; + +static struct zx2967_pm_domain sappu_domain = { + .dm = { + .name = "sappu_domain", + }, + .bit = PCU_DM_SAPPU, + .polarity = PWREN, + .reg_offset = zx296718_offsets, +}; + +static struct zx2967_pm_domain vde_domain = { + .dm = { + .name = "vde_domain", + }, + .bit = PCU_DM_VDE, + .polarity = PWREN, + .reg_offset = zx296718_offsets, +}; + +static struct zx2967_pm_domain vce_domain = { + .dm = { + .name = "vce_domain", + }, + .bit = PCU_DM_VCE, + .polarity = PWREN, + .reg_offset = zx296718_offsets, +}; + +static struct zx2967_pm_domain hde_domain = { + .dm = { + .name = "hde_domain", + }, + .bit = PCU_DM_HDE, + .polarity = PWREN, + .reg_offset = zx296718_offsets, +}; + +static struct zx2967_pm_domain viu_domain = { + .dm = { + .name = "viu_domain", + }, + .bit = PCU_DM_VIU, + .polarity = PWREN, + .reg_offset = zx296718_offsets, +}; + +static struct zx2967_pm_domain usb20_domain = { + .dm = { + .name = "usb20_domain", + }, + .bit = PCU_DM_USB20, + .polarity = PWREN, + .reg_offset = zx296718_offsets, +}; + +static struct zx2967_pm_domain usb21_domain = { + .dm = { + .name = "usb21_domain", + }, + .bit = PCU_DM_USB21, + .polarity = PWREN, + .reg_offset = zx296718_offsets, +}; + +static struct zx2967_pm_domain usb30_domain = { + .dm = { + .name = "usb30_domain", + }, + .bit = PCU_DM_USB30, + .polarity = PWREN, + .reg_offset = zx296718_offsets, +}; + +static struct zx2967_pm_domain hsic_domain = { + .dm = { + .name = "hsic_domain", + }, + .bit = PCU_DM_HSIC, + .polarity = PWREN, + .reg_offset = zx296718_offsets, +}; + +static struct zx2967_pm_domain gmac_domain = { + .dm = { + .name = "gmac_domain", + }, + .bit = PCU_DM_GMAC, + .polarity = PWREN, + .reg_offset = zx296718_offsets, +}; + +static struct zx2967_pm_domain ts_domain = { + .dm = { + .name = "ts_domain", + }, + .bit = PCU_DM_TS, + .polarity = PWREN, + .reg_offset = zx296718_offsets, +}; + +static struct generic_pm_domain *zx296718_pm_domains[] = { + [DM_ZX296718_VOU] = &vou_domain.dm, + [DM_ZX296718_SAPPU] = &sappu_domain.dm, + [DM_ZX296718_VDE] = &vde_domain.dm, + [DM_ZX296718_VCE] = &vce_domain.dm, + [DM_ZX296718_HDE] = &hde_domain.dm, + [DM_ZX296718_VIU] = &viu_domain.dm, + [DM_ZX296718_USB20] = &usb20_domain.dm, + [DM_ZX296718_USB21] = &usb21_domain.dm, + [DM_ZX296718_USB30] = &usb30_domain.dm, + [DM_ZX296718_HSIC] = &hsic_domain.dm, + [DM_ZX296718_GMAC] = &gmac_domain.dm, + [DM_ZX296718_TS] = &ts_domain.dm, +}; + +static int zx296718_pd_probe(struct platform_device *pdev) +{ + return zx2967_pd_probe(pdev, + zx296718_pm_domains, + ARRAY_SIZE(zx296718_pm_domains)); +} + +static const struct of_device_id zx296718_pm_domain_matches[] = { + { .compatible = "zte,zx296718-pcu", }, + { }, +}; + +static struct platform_driver zx296718_pd_driver = { + .driver = { + .name = "zx296718-powerdomain", + .owner = THIS_MODULE, + .of_match_table = zx296718_pm_domain_matches, + }, + .probe = zx296718_pd_probe, +}; + +static int __init zx296718_pd_init(void) +{ + return platform_driver_register(&zx296718_pd_driver); +} +subsys_initcall(zx296718_pd_init); diff --git a/drivers/soc/zte/zx2967_pm_domains.c b/drivers/soc/zte/zx2967_pm_domains.c new file mode 100644 index 000000000000..61c8d84bf315 --- /dev/null +++ b/drivers/soc/zte/zx2967_pm_domains.c @@ -0,0 +1,143 @@ +/* + * Copyright (C) 2017 ZTE Ltd. + * + * Author: Baoyou Xie <baoyou.xie@linaro.org> + * License terms: GNU General Public License (GPL) version 2 + */ + +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/of.h> + +#include "zx2967_pm_domains.h" + +#define PCU_DM_CLKEN(zpd) ((zpd)->reg_offset[REG_CLKEN]) +#define PCU_DM_ISOEN(zpd) ((zpd)->reg_offset[REG_ISOEN]) +#define PCU_DM_RSTEN(zpd) ((zpd)->reg_offset[REG_RSTEN]) +#define PCU_DM_PWREN(zpd) ((zpd)->reg_offset[REG_PWREN]) +#define PCU_DM_ACK_SYNC(zpd) ((zpd)->reg_offset[REG_ACK_SYNC]) + +static void __iomem *pcubase; + +static int zx2967_power_on(struct generic_pm_domain *domain) +{ + struct zx2967_pm_domain *zpd = (struct zx2967_pm_domain *)domain; + unsigned long loop = 1000; + u32 val; + + val = readl_relaxed(pcubase + PCU_DM_PWREN(zpd)); + if (zpd->polarity == PWREN) + val |= BIT(zpd->bit); + else + val &= ~BIT(zpd->bit); + writel_relaxed(val, pcubase + PCU_DM_PWREN(zpd)); + + do { + udelay(1); + val = readl_relaxed(pcubase + PCU_DM_ACK_SYNC(zpd)) + & BIT(zpd->bit); + } while (--loop && !val); + + if (!loop) { + pr_err("Error: %s %s fail\n", __func__, domain->name); + return -EIO; + } + + val = readl_relaxed(pcubase + PCU_DM_RSTEN(zpd)); + val |= BIT(zpd->bit); + writel_relaxed(val, pcubase + PCU_DM_RSTEN(zpd)); + udelay(5); + + val = readl_relaxed(pcubase + PCU_DM_ISOEN(zpd)); + val &= ~BIT(zpd->bit); + writel_relaxed(val, pcubase + PCU_DM_ISOEN(zpd)); + udelay(5); + + val = readl_relaxed(pcubase + PCU_DM_CLKEN(zpd)); + val |= BIT(zpd->bit); + writel_relaxed(val, pcubase + PCU_DM_CLKEN(zpd)); + udelay(5); + + pr_debug("poweron %s\n", domain->name); + + return 0; +} + +static int zx2967_power_off(struct generic_pm_domain *domain) +{ + struct zx2967_pm_domain *zpd = (struct zx2967_pm_domain *)domain; + unsigned long loop = 1000; + u32 val; + + val = readl_relaxed(pcubase + PCU_DM_CLKEN(zpd)); + val &= ~BIT(zpd->bit); + writel_relaxed(val, pcubase + PCU_DM_CLKEN(zpd)); + udelay(5); + + val = readl_relaxed(pcubase + PCU_DM_ISOEN(zpd)); + val |= BIT(zpd->bit); + writel_relaxed(val, pcubase + PCU_DM_ISOEN(zpd)); + udelay(5); + + val = readl_relaxed(pcubase + PCU_DM_RSTEN(zpd)); + val &= ~BIT(zpd->bit); + writel_relaxed(val, pcubase + PCU_DM_RSTEN(zpd)); + udelay(5); + + val = readl_relaxed(pcubase + PCU_DM_PWREN(zpd)); + if (zpd->polarity == PWREN) + val &= ~BIT(zpd->bit); + else + val |= BIT(zpd->bit); + writel_relaxed(val, pcubase + PCU_DM_PWREN(zpd)); + + do { + udelay(1); + val = readl_relaxed(pcubase + PCU_DM_ACK_SYNC(zpd)) + & BIT(zpd->bit); + } while (--loop && val); + + if (!loop) { + pr_err("Error: %s %s fail\n", __func__, domain->name); + return -EIO; + } + + pr_debug("poweroff %s\n", domain->name); + + return 0; +} + +int zx2967_pd_probe(struct platform_device *pdev, + struct generic_pm_domain **zx_pm_domains, + int domain_num) +{ + struct genpd_onecell_data *genpd_data; + struct resource *res; + int i; + + genpd_data = devm_kzalloc(&pdev->dev, sizeof(*genpd_data), GFP_KERNEL); + if (!genpd_data) + return -ENOMEM; + + genpd_data->domains = zx_pm_domains; + genpd_data->num_domains = domain_num; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pcubase = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pcubase)) { + dev_err(&pdev->dev, "ioremap fail.\n"); + return PTR_ERR(pcubase); + } + + for (i = 0; i < domain_num; ++i) { + zx_pm_domains[i]->power_on = zx2967_power_on; + zx_pm_domains[i]->power_off = zx2967_power_off; + + pm_genpd_init(zx_pm_domains[i], NULL, false); + } + + of_genpd_add_provider_onecell(pdev->dev.of_node, genpd_data); + dev_info(&pdev->dev, "powerdomain init ok\n"); + return 0; +} diff --git a/drivers/soc/zte/zx2967_pm_domains.h b/drivers/soc/zte/zx2967_pm_domains.h new file mode 100644 index 000000000000..cb46595a7ff3 --- /dev/null +++ b/drivers/soc/zte/zx2967_pm_domains.h @@ -0,0 +1,44 @@ +/* + * Header for ZTE's Power Domain Driver support + * + * Copyright (C) 2017 ZTE Ltd. + * + * Author: Baoyou Xie <baoyou.xie@linaro.org> + * License terms: GNU General Public License (GPL) version 2 + */ + +#ifndef __ZTE_ZX2967_PM_DOMAIN_H +#define __ZTE_ZX2967_PM_DOMAIN_H + +#include <linux/platform_device.h> +#include <linux/pm_domain.h> + +enum { + REG_CLKEN, + REG_ISOEN, + REG_RSTEN, + REG_PWREN, + REG_PWRDN, + REG_ACK_SYNC, + + /* The size of the array - must be last */ + REG_ARRAY_SIZE, +}; + +enum zx2967_power_polarity { + PWREN, + PWRDN, +}; + +struct zx2967_pm_domain { + struct generic_pm_domain dm; + const u16 bit; + const enum zx2967_power_polarity polarity; + const u16 *reg_offset; +}; + +int zx2967_pd_probe(struct platform_device *pdev, + struct generic_pm_domain **zx_pm_domains, + int domain_num); + +#endif /* __ZTE_ZX2967_PM_DOMAIN_H */ diff --git a/include/dt-bindings/soc/zte,pm_domains.h b/include/dt-bindings/soc/zte,pm_domains.h new file mode 100644 index 000000000000..a0b4019c8e01 --- /dev/null +++ b/include/dt-bindings/soc/zte,pm_domains.h @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2017 Linaro Ltd. + * + * Author: Baoyou Xie <baoyou.xie@linaro.org> + * License terms: GNU General Public License (GPL) version 2 + */ + +#ifndef _DT_BINDINGS_SOC_ZTE_PM_DOMAINS_H +#define _DT_BINDINGS_SOC_ZTE_PM_DOMAINS_H + +#define DM_ZX296718_SAPPU 0 +#define DM_ZX296718_VDE 1 /* g1v6 */ +#define DM_ZX296718_VCE 2 /* h1v6 */ +#define DM_ZX296718_HDE 3 /* g2v2 */ +#define DM_ZX296718_VIU 4 +#define DM_ZX296718_USB20 5 +#define DM_ZX296718_USB21 6 +#define DM_ZX296718_USB30 7 +#define DM_ZX296718_HSIC 8 +#define DM_ZX296718_GMAC 9 +#define DM_ZX296718_TS 10 +#define DM_ZX296718_VOU 11 + +#endif /* _DT_BINDINGS_SOC_ZTE_PM_DOMAINS_H */ |