diff options
| -rw-r--r-- | arch/powerpc/kernel/fpu.S | 8 | ||||
| -rw-r--r-- | include/asm-powerpc/ppc_asm.h | 29 |
2 files changed, 19 insertions, 18 deletions
diff --git a/arch/powerpc/kernel/fpu.S b/arch/powerpc/kernel/fpu.S index 51fd78da25b7..4d6001fa1cf2 100644 --- a/arch/powerpc/kernel/fpu.S +++ b/arch/powerpc/kernel/fpu.S @@ -40,17 +40,17 @@ _GLOBAL(load_up_fpu) */ #ifndef CONFIG_SMP LOADBASE(r3, last_task_used_math) - tophys(r3,r3) + toreal(r3) LDL r4,OFF(last_task_used_math)(r3) CMPI 0,r4,0 beq 1f - tophys(r4,r4) + toreal(r4) addi r4,r4,THREAD /* want last_task_used_math->thread */ SAVE_32FPRS(0, r4) mffs fr0 stfd fr0,THREAD_FPSCR(r4) LDL r5,PT_REGS(r4) - tophys(r5,r5) + toreal(r5) LDL r4,_MSR-STACK_FRAME_OVERHEAD(r5) li r10,MSR_FP|MSR_FE0|MSR_FE1 andc r4,r4,r10 /* disable FP for previous task */ @@ -76,7 +76,7 @@ _GLOBAL(load_up_fpu) REST_32FPRS(0, r5) #ifndef CONFIG_SMP subi r4,r5,THREAD - tovirt(r4,r4) + fromreal(r4) STL r4,OFF(last_task_used_math)(r3) #endif /* CONFIG_SMP */ /* restore registers and return */ diff --git a/include/asm-powerpc/ppc_asm.h b/include/asm-powerpc/ppc_asm.h index f8ad5df6ebef..470d7400ac59 100644 --- a/include/asm-powerpc/ppc_asm.h +++ b/include/asm-powerpc/ppc_asm.h @@ -154,7 +154,7 @@ n: * loads the address of 'name' into 'rn' * * LOADBASE( rn, name ) - * loads the address (less the low 16 bits) of 'name' into 'rn' + * loads the address (possibly without the low 16 bits) of 'name' into 'rn' * suitable for base+disp addressing */ #ifdef __powerpc64__ @@ -166,10 +166,7 @@ n: ori rn,rn,name##@l #define LOADBASE(rn,name) \ - .section .toc,"aw"; \ -1: .tc name[TC],name; \ - .previous; \ - ld rn,1b@toc(r2) + ld rn,name@got(r2) #define OFF(name) 0 @@ -278,6 +275,9 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601) #if defined(CONFIG_BOOKE) +#define toreal(rd) +#define fromreal(rd) + #define tophys(rd,rs) \ addis rd,rs,0 @@ -285,23 +285,24 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601) addis rd,rs,0 #elif defined(CONFIG_PPC64) -/* PPPBBB - DRENG If KERNELBASE is always 0xC0..., - * Then we can easily do this with one asm insn. -Peter - */ +#define toreal(rd) /* we can access c000... in real mode */ +#define fromreal(rd) + #define tophys(rd,rs) \ - lis rd,((KERNELBASE>>48)&0xFFFF); \ - rldicr rd,rd,32,31; \ - sub rd,rs,rd + clrldi rd,rs,2 #define tovirt(rd,rs) \ - lis rd,((KERNELBASE>>48)&0xFFFF); \ - rldicr rd,rd,32,31; \ - add rd,rs,rd + rotldi rd,rs,16; \ + ori rd,rd,((KERNELBASE>>48)&0xFFFF);\ + rotldi rd,rd,48 #else /* * On APUS (Amiga PowerPC cpu upgrade board), we don't know the * physical base address of RAM at compile time. */ +#define toreal(rd) tophys(rd,rd) +#define fromreal(rd) tovirt(rd,rd) + #define tophys(rd,rs) \ 0: addis rd,rs,-KERNELBASE@h; \ .section ".vtop_fixup","aw"; \ |