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-rw-r--r--arch/arm/boot/dts/imx6qdl.dtsi20
-rw-r--r--arch/arm/boot/dts/imx6sl.dtsi20
-rw-r--r--arch/arm/boot/dts/imx6sx.dtsi20
-rw-r--r--arch/arm/boot/dts/imx6ul.dtsi11
4 files changed, 50 insertions, 21 deletions
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 63975a42d65c..59ff86695a14 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -695,8 +695,11 @@
interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
<0 54 IRQ_TYPE_LEVEL_HIGH>,
<0 127 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- regulator-1p1 {
+ regulator-1p1@20c8110 {
+ reg = <0x20c8110>;
compatible = "fsl,anatop-regulator";
regulator-name = "vdd1p1";
regulator-min-microvolt = <1000000>;
@@ -711,7 +714,8 @@
anatop-enable-bit = <0>;
};
- regulator-3p0 {
+ regulator-3p0@20c8120 {
+ reg = <0x20c8120>;
compatible = "fsl,anatop-regulator";
regulator-name = "vdd3p0";
regulator-min-microvolt = <2800000>;
@@ -726,7 +730,8 @@
anatop-enable-bit = <0>;
};
- regulator-2p5 {
+ regulator-2p5@20c8130 {
+ reg = <0x20c8130>;
compatible = "fsl,anatop-regulator";
regulator-name = "vdd2p5";
regulator-min-microvolt = <2250000>;
@@ -741,7 +746,8 @@
anatop-enable-bit = <0>;
};
- reg_arm: regulator-vddcore {
+ reg_arm: regulator-vddcore@20c8140 {
+ reg = <0x20c8140>;
compatible = "fsl,anatop-regulator";
regulator-name = "vddarm";
regulator-min-microvolt = <725000>;
@@ -758,7 +764,8 @@
anatop-max-voltage = <1450000>;
};
- reg_pu: regulator-vddpu {
+ reg_pu: regulator-vddpu@20c8140 {
+ reg = <0x20c8140>;
compatible = "fsl,anatop-regulator";
regulator-name = "vddpu";
regulator-min-microvolt = <725000>;
@@ -775,7 +782,8 @@
anatop-max-voltage = <1450000>;
};
- reg_soc: regulator-vddsoc {
+ reg_soc: regulator-vddsoc@20c8140 {
+ reg = <0x20c8140>;
compatible = "fsl,anatop-regulator";
regulator-name = "vddsoc";
regulator-min-microvolt = <725000>;
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 3365182e251e..ae8df3cf687e 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -527,8 +527,11 @@
interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
<0 54 IRQ_TYPE_LEVEL_HIGH>,
<0 127 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- regulator-1p1 {
+ regulator-1p1@20c8110 {
+ reg = <0x20c8110>;
compatible = "fsl,anatop-regulator";
regulator-name = "vdd1p1";
regulator-min-microvolt = <800000>;
@@ -543,7 +546,8 @@
anatop-enable-bit = <0>;
};
- regulator-3p0 {
+ regulator-3p0@20c8120 {
+ reg = <0x20c8120>;
compatible = "fsl,anatop-regulator";
regulator-name = "vdd3p0";
regulator-min-microvolt = <2800000>;
@@ -558,7 +562,8 @@
anatop-enable-bit = <0>;
};
- regulator-2p5 {
+ regulator-2p5@20c8130 {
+ reg = <0x20c8130>;
compatible = "fsl,anatop-regulator";
regulator-name = "vdd2p5";
regulator-min-microvolt = <2100000>;
@@ -573,7 +578,8 @@
anatop-enable-bit = <0>;
};
- reg_arm: regulator-vddcore {
+ reg_arm: regulator-vddcore@20c8140 {
+ reg = <0x20c8140>;
compatible = "fsl,anatop-regulator";
regulator-name = "vddarm";
regulator-min-microvolt = <725000>;
@@ -590,7 +596,8 @@
anatop-max-voltage = <1450000>;
};
- reg_pu: regulator-vddpu {
+ reg_pu: regulator-vddpu@20c8140 {
+ reg = <0x20c8140>;
compatible = "fsl,anatop-regulator";
regulator-name = "vddpu";
regulator-min-microvolt = <725000>;
@@ -607,7 +614,8 @@
anatop-max-voltage = <1450000>;
};
- reg_soc: regulator-vddsoc {
+ reg_soc: regulator-vddsoc@20c8140 {
+ reg = <0x20c8140>;
compatible = "fsl,anatop-regulator";
regulator-name = "vddsoc";
regulator-min-microvolt = <725000>;
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 45003808b8f6..07ba5183a904 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -585,8 +585,11 @@
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- regulator-1p1 {
+ regulator-1p1@20c8110 {
+ reg = <0x20c8110>;
compatible = "fsl,anatop-regulator";
regulator-name = "vdd1p1";
regulator-min-microvolt = <800000>;
@@ -601,7 +604,8 @@
anatop-enable-bit = <0>;
};
- regulator-3p0 {
+ regulator-3p0@20c8120 {
+ reg = <0x20c8120>;
compatible = "fsl,anatop-regulator";
regulator-name = "vdd3p0";
regulator-min-microvolt = <2800000>;
@@ -616,7 +620,8 @@
anatop-enable-bit = <0>;
};
- regulator-2p5 {
+ regulator-2p5@20c8130 {
+ reg = <0x20c8130>;
compatible = "fsl,anatop-regulator";
regulator-name = "vdd2p5";
regulator-min-microvolt = <2100000>;
@@ -631,7 +636,8 @@
anatop-enable-bit = <0>;
};
- reg_arm: regulator-vddcore {
+ reg_arm: regulator-vddcore@20c8140 {
+ reg = <0x20c8140>;
compatible = "fsl,anatop-regulator";
regulator-name = "vddarm";
regulator-min-microvolt = <725000>;
@@ -648,7 +654,8 @@
anatop-max-voltage = <1450000>;
};
- reg_pcie: regulator-vddpcie {
+ reg_pcie: regulator-vddpcie@20c8140 {
+ reg = <0x20c8140>;
compatible = "fsl,anatop-regulator";
regulator-name = "vddpcie";
regulator-min-microvolt = <725000>;
@@ -664,7 +671,8 @@
anatop-max-voltage = <1450000>;
};
- reg_soc: regulator-vddsoc {
+ reg_soc: regulator-vddsoc@20c8140 {
+ reg = <0x20c8140>;
compatible = "fsl,anatop-regulator";
regulator-name = "vddsoc";
regulator-min-microvolt = <725000>;
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index ed55e0ca4b5c..1b14e4d39c26 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -542,8 +542,11 @@
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- reg_3p0: regulator-3p0 {
+ reg_3p0: regulator-3p0@20c8110 {
+ reg = <0x20c8110>;
compatible = "fsl,anatop-regulator";
regulator-name = "vdd3p0";
regulator-min-microvolt = <2625000>;
@@ -557,7 +560,8 @@
anatop-enable-bit = <0>;
};
- reg_arm: regulator-vddcore {
+ reg_arm: regulator-vddcore@20c8140 {
+ reg = <0x20c8140>;
compatible = "fsl,anatop-regulator";
regulator-name = "cpu";
regulator-min-microvolt = <725000>;
@@ -574,7 +578,8 @@
anatop-max-voltage = <1450000>;
};
- reg_soc: regulator-vddsoc {
+ reg_soc: regulator-vddsoc@20c8140 {
+ reg = <0x20c8140>;
compatible = "fsl,anatop-regulator";
regulator-name = "vddsoc";
regulator-min-microvolt = <725000>;
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.