aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--drivers/clk/ti/apll.c3
-rw-r--r--drivers/clk/ti/clk-33xx.c279
-rw-r--r--drivers/clk/ti/clk-3xxx.c263
-rw-r--r--drivers/clk/ti/clk-43xx.c295
-rw-r--r--drivers/clk/ti/clk-44xx.c200
-rw-r--r--drivers/clk/ti/clk-54xx.c697
-rw-r--r--drivers/clk/ti/clk-7xx.c1076
-rw-r--r--drivers/clk/ti/clk-814x.c50
-rw-r--r--drivers/clk/ti/clk-816x.c62
-rw-r--r--drivers/clk/ti/clk.c70
-rw-r--r--drivers/clk/ti/clkctrl.c91
-rw-r--r--drivers/clk/ti/clock.h13
-rw-r--r--drivers/clk/ti/composite.c3
-rw-r--r--drivers/clk/ti/dpll.c3
-rw-r--r--include/dt-bindings/clock/am3.h108
-rw-r--r--include/dt-bindings/clock/am4.h113
-rw-r--r--include/dt-bindings/clock/dm814.h45
-rw-r--r--include/dt-bindings/clock/dm816.h53
-rw-r--r--include/dt-bindings/clock/dra7.h172
-rw-r--r--include/dt-bindings/clock/omap5.h118
20 files changed, 2662 insertions, 1052 deletions
diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c
index 83b148f8037c..9498e9363b57 100644
--- a/drivers/clk/ti/apll.c
+++ b/drivers/clk/ti/apll.c
@@ -133,9 +133,10 @@ static const struct clk_ops apll_ck_ops = {
.get_parent = &dra7_init_apll_parent,
};
-static void __init omap_clk_register_apll(struct clk_hw *hw,
+static void __init omap_clk_register_apll(void *user,
struct device_node *node)
{
+ struct clk_hw *hw = user;
struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
struct dpll_data *ad = clk_hw->dpll_data;
struct clk *clk;
diff --git a/drivers/clk/ti/clk-33xx.c b/drivers/clk/ti/clk-33xx.c
index 0e47d95faf49..612491a26070 100644
--- a/drivers/clk/ti/clk-33xx.c
+++ b/drivers/clk/ti/clk-33xx.c
@@ -19,98 +19,201 @@
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/clk/ti.h>
+#include <dt-bindings/clock/am3.h>
#include "clock.h"
+static const char * const am3_gpio1_dbclk_parents[] __initconst = {
+ "l4_per_cm:clk:0138:0",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data am3_gpio2_bit_data[] __initconst = {
+ { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data am3_gpio3_bit_data[] __initconst = {
+ { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data am3_gpio4_bit_data[] __initconst = {
+ { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data am3_l4_per_clkctrl_regs[] __initconst = {
+ { AM3_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk", "cpsw_125mhz_clkdm" },
+ { AM3_LCDC_CLKCTRL, NULL, CLKF_SW_SUP, "lcd_gclk", "lcdc_clkdm" },
+ { AM3_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "usbotg_fck", "l3s_clkdm" },
+ { AM3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
+ { AM3_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_div2_ck", "l3_clkdm" },
+ { AM3_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
+ { AM3_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
+ { AM3_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck", "l3s_clkdm" },
+ { AM3_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM3_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
+ { AM3_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM3_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM3_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM3_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM3_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM3_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM3_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck", "l3s_clkdm" },
+ { AM3_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM3_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM3_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM3_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM3_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
+ { AM3_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
+ { AM3_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
+ { AM3_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
+ { AM3_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
+ { AM3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck", "l3_clkdm" },
+ { AM3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
+ { AM3_GPIO2_CLKCTRL, am3_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM3_GPIO3_CLKCTRL, am3_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM3_GPIO4_CLKCTRL, am3_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
+ { AM3_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
+ { AM3_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
+ { AM3_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM3_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM3_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM3_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
+ { AM3_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
+ { AM3_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk", "pruss_ocp_clkdm" },
+ { AM3_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
+ { AM3_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
+ { AM3_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
+ { AM3_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk", "l3s_clkdm" },
+ { AM3_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
+ { AM3_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
+ { AM3_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM3_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM3_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk", "l4hs_clkdm" },
+ { AM3_OCPWP_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM3_CLKDIV32K_CLKCTRL, NULL, CLKF_SW_SUP, "clkdiv32k_ck", "clk_24mhz_clkdm" },
+ { 0 },
+};
+
+static const char * const am3_gpio0_dbclk_parents[] __initconst = {
+ "gpio0_dbclk_mux_ck",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data am3_gpio1_bit_data[] __initconst = {
+ { 18, TI_CLK_GATE, am3_gpio0_dbclk_parents, NULL },
+ { 0 },
+};
+
+static const char * const am3_dbg_sysclk_ck_parents[] __initconst = {
+ "sys_clkin_ck",
+ NULL,
+};
+
+static const char * const am3_trace_pmd_clk_mux_ck_parents[] __initconst = {
+ "l4_wkup_cm:clk:0010:19",
+ "l4_wkup_cm:clk:0010:30",
+ NULL,
+};
+
+static const char * const am3_trace_clk_div_ck_parents[] __initconst = {
+ "l4_wkup_cm:clk:0010:20",
+ NULL,
+};
+
+static const struct omap_clkctrl_div_data am3_trace_clk_div_ck_data __initconst = {
+ .max_div = 64,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
+};
+
+static const char * const am3_stm_clk_div_ck_parents[] __initconst = {
+ "l4_wkup_cm:clk:0010:22",
+ NULL,
+};
+
+static const struct omap_clkctrl_div_data am3_stm_clk_div_ck_data __initconst = {
+ .max_div = 64,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
+};
+
+static const char * const am3_dbg_clka_ck_parents[] __initconst = {
+ "dpll_core_m4_ck",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data am3_debugss_bit_data[] __initconst = {
+ { 19, TI_CLK_GATE, am3_dbg_sysclk_ck_parents, NULL },
+ { 20, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
+ { 22, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
+ { 24, TI_CLK_DIVIDER, am3_trace_clk_div_ck_parents, &am3_trace_clk_div_ck_data },
+ { 27, TI_CLK_DIVIDER, am3_stm_clk_div_ck_parents, &am3_stm_clk_div_ck_data },
+ { 30, TI_CLK_GATE, am3_dbg_clka_ck_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data am3_l4_wkup_clkctrl_regs[] __initconst = {
+ { AM3_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
+ { AM3_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
+ { AM3_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
+ { AM3_DEBUGSS_CLKCTRL, am3_debugss_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0010:24", "l3_aon_clkdm" },
+ { AM3_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "dpll_core_m4_div2_ck", "l4_wkup_aon_clkdm" },
+ { AM3_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
+ { AM3_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
+ { AM3_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck" },
+ { AM3_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck" },
+ { AM3_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },
+ { AM3_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck" },
+ { AM3_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data am3_mpu_clkctrl_regs[] __initconst = {
+ { AM3_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data am3_l4_rtc_clkctrl_regs[] __initconst = {
+ { AM3_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data am3_gfx_l3_clkctrl_regs[] __initconst = {
+ { AM3_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data am3_l4_cefuse_clkctrl_regs[] __initconst = {
+ { AM3_CEFUSE_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" },
+ { 0 },
+};
+
+const struct omap_clkctrl_data am3_clkctrl_data[] __initconst = {
+ { 0x44e00014, am3_l4_per_clkctrl_regs },
+ { 0x44e00404, am3_l4_wkup_clkctrl_regs },
+ { 0x44e00604, am3_mpu_clkctrl_regs },
+ { 0x44e00800, am3_l4_rtc_clkctrl_regs },
+ { 0x44e00904, am3_gfx_l3_clkctrl_regs },
+ { 0x44e00a20, am3_l4_cefuse_clkctrl_regs },
+ { 0 },
+};
+
static struct ti_dt_clk am33xx_clks[] = {
- DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"),
- DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"),
- DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
- DT_CLK(NULL, "virt_24000000_ck", "virt_24000000_ck"),
- DT_CLK(NULL, "virt_25000000_ck", "virt_25000000_ck"),
- DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
- DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"),
- DT_CLK(NULL, "tclkin_ck", "tclkin_ck"),
- DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
- DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
- DT_CLK(NULL, "dpll_core_m4_ck", "dpll_core_m4_ck"),
- DT_CLK(NULL, "dpll_core_m5_ck", "dpll_core_m5_ck"),
- DT_CLK(NULL, "dpll_core_m6_ck", "dpll_core_m6_ck"),
- DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
- DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
- DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"),
- DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"),
- DT_CLK(NULL, "dpll_ddr_m2_div2_ck", "dpll_ddr_m2_div2_ck"),
- DT_CLK(NULL, "dpll_disp_ck", "dpll_disp_ck"),
- DT_CLK(NULL, "dpll_disp_m2_ck", "dpll_disp_m2_ck"),
- DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
- DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
- DT_CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", "dpll_per_m2_div4_wkupdm_ck"),
- DT_CLK(NULL, "dpll_per_m2_div4_ck", "dpll_per_m2_div4_ck"),
- DT_CLK(NULL, "adc_tsc_fck", "adc_tsc_fck"),
- DT_CLK(NULL, "cefuse_fck", "cefuse_fck"),
- DT_CLK(NULL, "clkdiv32k_ck", "clkdiv32k_ck"),
- DT_CLK(NULL, "clkdiv32k_ick", "clkdiv32k_ick"),
- DT_CLK(NULL, "dcan0_fck", "dcan0_fck"),
- DT_CLK("481cc000.d_can", NULL, "dcan0_fck"),
- DT_CLK(NULL, "dcan1_fck", "dcan1_fck"),
- DT_CLK("481d0000.d_can", NULL, "dcan1_fck"),
- DT_CLK(NULL, "pruss_ocp_gclk", "pruss_ocp_gclk"),
- DT_CLK(NULL, "mcasp0_fck", "mcasp0_fck"),
- DT_CLK(NULL, "mcasp1_fck", "mcasp1_fck"),
- DT_CLK(NULL, "mmu_fck", "mmu_fck"),
- DT_CLK(NULL, "smartreflex0_fck", "smartreflex0_fck"),
- DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"),
- DT_CLK(NULL, "sha0_fck", "sha0_fck"),
- DT_CLK(NULL, "aes0_fck", "aes0_fck"),
- DT_CLK(NULL, "rng_fck", "rng_fck"),
- DT_CLK(NULL, "timer1_fck", "timer1_fck"),
- DT_CLK(NULL, "timer2_fck", "timer2_fck"),
- DT_CLK(NULL, "timer3_fck", "timer3_fck"),
- DT_CLK(NULL, "timer4_fck", "timer4_fck"),
- DT_CLK(NULL, "timer5_fck", "timer5_fck"),
- DT_CLK(NULL, "timer6_fck", "timer6_fck"),
- DT_CLK(NULL, "timer7_fck", "timer7_fck"),
- DT_CLK(NULL, "usbotg_fck", "usbotg_fck"),
- DT_CLK(NULL, "ieee5000_fck", "ieee5000_fck"),
- DT_CLK(NULL, "wdt1_fck", "wdt1_fck"),
- DT_CLK(NULL, "l4_rtc_gclk", "l4_rtc_gclk"),
- DT_CLK(NULL, "l3_gclk", "l3_gclk"),
- DT_CLK(NULL, "dpll_core_m4_div2_ck", "dpll_core_m4_div2_ck"),
- DT_CLK(NULL, "l4hs_gclk", "l4hs_gclk"),
- DT_CLK(NULL, "l3s_gclk", "l3s_gclk"),
- DT_CLK(NULL, "l4fw_gclk", "l4fw_gclk"),
- DT_CLK(NULL, "l4ls_gclk", "l4ls_gclk"),
- DT_CLK(NULL, "clk_24mhz", "clk_24mhz"),
- DT_CLK(NULL, "sysclk_div_ck", "sysclk_div_ck"),
- DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),
- DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),
- DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"),
- DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"),
- DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
- DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
- DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
- DT_CLK(NULL, "lcd_gclk", "lcd_gclk"),
- DT_CLK(NULL, "mmc_clk", "mmc_clk"),
- DT_CLK(NULL, "gfx_fclk_clksel_ck", "gfx_fclk_clksel_ck"),
- DT_CLK(NULL, "gfx_fck_div_ck", "gfx_fck_div_ck"),
- DT_CLK(NULL, "sysclkout_pre_ck", "sysclkout_pre_ck"),
- DT_CLK(NULL, "clkout2_div_ck", "clkout2_div_ck"),
- DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
+ DT_CLK(NULL, "timer_32k_ck", "l4_per_cm:0138:0"),
DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
- DT_CLK(NULL, "dbg_sysclk_ck", "dbg_sysclk_ck"),
- DT_CLK(NULL, "dbg_clka_ck", "dbg_clka_ck"),
- DT_CLK(NULL, "stm_pmd_clock_mux_ck", "stm_pmd_clock_mux_ck"),
- DT_CLK(NULL, "trace_pmd_clk_mux_ck", "trace_pmd_clk_mux_ck"),
- DT_CLK(NULL, "stm_clk_div_ck", "stm_clk_div_ck"),
- DT_CLK(NULL, "trace_clk_div_ck", "trace_clk_div_ck"),
- DT_CLK(NULL, "clkout2_ck", "clkout2_ck"),
- DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"),
- DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"),
- DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"),
- DT_CLK("48300200.pwm", "tbclk", "ehrpwm0_tbclk"),
- DT_CLK("48302200.pwm", "tbclk", "ehrpwm1_tbclk"),
- DT_CLK("48304200.pwm", "tbclk", "ehrpwm2_tbclk"),
+ DT_CLK(NULL, "clkdiv32k_ick", "l4_per_cm:0138:0"),
+ DT_CLK(NULL, "dbg_clka_ck", "l4_wkup_cm:0010:30"),
+ DT_CLK(NULL, "dbg_sysclk_ck", "l4_wkup_cm:0010:19"),
+ DT_CLK(NULL, "gpio0_dbclk", "l4_wkup_cm:0004:18"),
+ DT_CLK(NULL, "gpio1_dbclk", "l4_per_cm:0098:18"),
+ DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:009c:18"),
+ DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:00a0:18"),
+ DT_CLK(NULL, "stm_clk_div_ck", "l4_wkup_cm:0010:27"),
+ DT_CLK(NULL, "stm_pmd_clock_mux_ck", "l4_wkup_cm:0010:22"),
+ DT_CLK(NULL, "trace_clk_div_ck", "l4_wkup_cm:0010:24"),
+ DT_CLK(NULL, "trace_pmd_clk_mux_ck", "l4_wkup_cm:0010:20"),
{ .node_name = NULL },
};
@@ -133,6 +236,8 @@ int __init am33xx_dt_clk_init(void)
omap2_clk_disable_autoidle_all();
+ ti_clk_add_aliases();
+
omap2_clk_enable_init_clocks(enable_init_clks,
ARRAY_SIZE(enable_init_clks));
diff --git a/drivers/clk/ti/clk-3xxx.c b/drivers/clk/ti/clk-3xxx.c
index b1251cae98b8..8aa5f5793835 100644
--- a/drivers/clk/ti/clk-3xxx.c
+++ b/drivers/clk/ti/clk-3xxx.c
@@ -224,296 +224,43 @@ const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait = {
};
static struct ti_dt_clk omap3xxx_clks[] = {
- DT_CLK(NULL, "apb_pclk", "dummy_apb_pclk"),
- DT_CLK(NULL, "omap_32k_fck", "omap_32k_fck"),
- DT_CLK(NULL, "virt_12m_ck", "virt_12m_ck"),
- DT_CLK(NULL, "virt_13m_ck", "virt_13m_ck"),
- DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
- DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
- DT_CLK(NULL, "virt_38_4m_ck", "virt_38_4m_ck"),
- DT_CLK(NULL, "osc_sys_ck", "osc_sys_ck"),
- DT_CLK("twl", "fck", "osc_sys_ck"),
- DT_CLK(NULL, "sys_ck", "sys_ck"),
- DT_CLK(NULL, "omap_96m_alwon_fck", "omap_96m_alwon_fck"),
- DT_CLK("etb", "emu_core_alwon_ck", "emu_core_alwon_ck"),
- DT_CLK(NULL, "sys_altclk", "sys_altclk"),
- DT_CLK(NULL, "sys_clkout1", "sys_clkout1"),
- DT_CLK(NULL, "dpll1_ck", "dpll1_ck"),
- DT_CLK(NULL, "dpll1_x2_ck", "dpll1_x2_ck"),
- DT_CLK(NULL, "dpll1_x2m2_ck", "dpll1_x2m2_ck"),
- DT_CLK(NULL, "dpll3_ck", "dpll3_ck"),
- DT_CLK(NULL, "core_ck", "core_ck"),
- DT_CLK(NULL, "dpll3_x2_ck", "dpll3_x2_ck"),
- DT_CLK(NULL, "dpll3_m2_ck", "dpll3_m2_ck"),
- DT_CLK(NULL, "dpll3_m2x2_ck", "dpll3_m2x2_ck"),
- DT_CLK(NULL, "dpll3_m3_ck", "dpll3_m3_ck"),
- DT_CLK(NULL, "dpll3_m3x2_ck", "dpll3_m3x2_ck"),
- DT_CLK(NULL, "dpll4_ck", "dpll4_ck"),
- DT_CLK(NULL, "dpll4_x2_ck", "dpll4_x2_ck"),
- DT_CLK(NULL, "omap_96m_fck", "omap_96m_fck"),
- DT_CLK(NULL, "cm_96m_fck", "cm_96m_fck"),
- DT_CLK(NULL, "omap_54m_fck", "omap_54m_fck"),
- DT_CLK(NULL, "omap_48m_fck", "omap_48m_fck"),
- DT_CLK(NULL, "omap_12m_fck", "omap_12m_fck"),
- DT_CLK(NULL, "dpll4_m2_ck", "dpll4_m2_ck"),
- DT_CLK(NULL, "dpll4_m2x2_ck", "dpll4_m2x2_ck"),
- DT_CLK(NULL, "dpll4_m3_ck", "dpll4_m3_ck"),
- DT_CLK(NULL, "dpll4_m3x2_ck", "dpll4_m3x2_ck"),
- DT_CLK(NULL, "dpll4_m4_ck", "dpll4_m4_ck"),
- DT_CLK(NULL, "dpll4_m4x2_ck", "dpll4_m4x2_ck"),
- DT_CLK(NULL, "dpll4_m5_ck", "dpll4_m5_ck"),
- DT_CLK(NULL, "dpll4_m5x2_ck", "dpll4_m5x2_ck"),
- DT_CLK(NULL, "dpll4_m6_ck", "dpll4_m6_ck"),
- DT_CLK(NULL, "dpll4_m6x2_ck", "dpll4_m6x2_ck"),
- DT_CLK("etb", "emu_per_alwon_ck", "emu_per_alwon_ck"),
- DT_CLK(NULL, "clkout2_src_ck", "clkout2_src_ck"),
- DT_CLK(NULL, "sys_clkout2", "sys_clkout2"),
- DT_CLK(NULL, "corex2_fck", "corex2_fck"),
- DT_CLK(NULL, "dpll1_fck", "dpll1_fck"),
- DT_CLK(NULL, "mpu_ck", "mpu_ck"),
- DT_CLK(NULL, "arm_fck", "arm_fck"),
- DT_CLK("etb", "emu_mpu_alwon_ck", "emu_mpu_alwon_ck"),
- DT_CLK(NULL, "l3_ick", "l3_ick"),
- DT_CLK(NULL, "l4_ick", "l4_ick"),
- DT_CLK(NULL, "rm_ick", "rm_ick"),
- DT_CLK(NULL, "gpt10_fck", "gpt10_fck"),
- DT_CLK(NULL, "gpt11_fck", "gpt11_fck"),
- DT_CLK(NULL, "core_96m_fck", "core_96m_fck"),
- DT_CLK(NULL, "mmchs2_fck", "mmchs2_fck"),
- DT_CLK(NULL, "mmchs1_fck", "mmchs1_fck"),
- DT_CLK(NULL, "i2c3_fck", "i2c3_fck"),
- DT_CLK(NULL, "i2c2_fck", "i2c2_fck"),
- DT_CLK(NULL, "i2c1_fck", "i2c1_fck"),
- DT_CLK(NULL, "core_48m_fck", "core_48m_fck"),
- DT_CLK(NULL, "mcspi4_fck", "mcspi4_fck"),
- DT_CLK(NULL, "mcspi3_fck", "mcspi3_fck"),
- DT_CLK(NULL, "mcspi2_fck", "mcspi2_fck"),
- DT_CLK(NULL, "mcspi1_fck", "mcspi1_fck"),
- DT_CLK(NULL, "uart2_fck", "uart2_fck"),
- DT_CLK(NULL, "uart1_fck", "uart1_fck"),
- DT_CLK(NULL, "core_12m_fck", "core_12m_fck"),
- DT_CLK("omap_hdq.0", "fck", "hdq_fck"),
- DT_CLK(NULL, "hdq_fck", "hdq_fck"),
- DT_CLK(NULL, "core_l3_ick", "core_l3_ick"),
- DT_CLK(NULL, "sdrc_ick", "sdrc_ick"),
- DT_CLK(NULL, "gpmc_fck", "gpmc_fck"),
- DT_CLK(NULL, "core_l4_ick", "core_l4_ick"),
- DT_CLK("omap_hsmmc.1", "ick", "mmchs2_ick"),
- DT_CLK("omap_hsmmc.0", "ick", "mmchs1_ick"),
- DT_CLK(NULL, "mmchs2_ick", "mmchs2_ick"),
- DT_CLK(NULL, "mmchs1_ick", "mmchs1_ick"),
- DT_CLK("omap_hdq.0", "ick", "hdq_ick"),
- DT_CLK(NULL, "hdq_ick", "hdq_ick"),
- DT_CLK("omap2_mcspi.4", "ick", "mcspi4_ick"),
- DT_CLK("omap2_mcspi.3", "ick", "mcspi3_ick"),
- DT_CLK("omap2_mcspi.2", "ick", "mcspi2_ick"),
- DT_CLK("omap2_mcspi.1", "ick", "mcspi1_ick"),
- DT_CLK(NULL, "mcspi4_ick", "mcspi4_ick"),
- DT_CLK(NULL, "mcspi3_ick", "mcspi3_ick"),
- DT_CLK(NULL, "mcspi2_ick", "mcspi2_ick"),
- DT_CLK(NULL, "mcspi1_ick", "mcspi1_ick"),
- DT_CLK("omap_i2c.3", "ick", "i2c3_ick"),
- DT_CLK("omap_i2c.2", "ick", "i2c2_ick"),
- DT_CLK("omap_i2c.1", "ick", "i2c1_ick"),
- DT_CLK(NULL, "i2c3_ick", "i2c3_ick"),
- DT_CLK(NULL, "i2c2_ick", "i2c2_ick"),
- DT_CLK(NULL, "i2c1_ick", "i2c1_ick"),
- DT_CLK(NULL, "uart2_ick", "uart2_ick"),
- DT_CLK(NULL, "uart1_ick", "uart1_ick"),
- DT_CLK(NULL, "gpt11_ick", "gpt11_ick"),
- DT_CLK(NULL, "gpt10_ick", "gpt10_ick"),
- DT_CLK(NULL, "omapctrl_ick", "omapctrl_ick"),
- DT_CLK(NULL, "dss_tv_fck", "dss_tv_fck"),
- DT_CLK(NULL, "dss_96m_fck", "dss_96m_fck"),
- DT_CLK(NULL, "dss2_alwon_fck", "dss2_alwon_fck"),
- DT_CLK(NULL, "init_60m_fclk", "dummy_ck"),
- DT_CLK(NULL, "gpt1_fck", "gpt1_fck"),
- DT_CLK(NULL, "aes2_ick", "aes2_ick"),
- DT_CLK(NULL, "wkup_32k_fck", "wkup_32k_fck"),
- DT_CLK(NULL, "gpio1_dbck", "gpio1_dbck"),
- DT_CLK(NULL, "sha12_ick", "sha12_ick"),
- DT_CLK(NULL, "wdt2_fck", "wdt2_fck"),
- DT_CLK("omap_wdt", "ick", "wdt2_ick"),
- DT_CLK(NULL, "wdt2_ick", "wdt2_ick"),
- DT_CLK(NULL, "wdt1_ick", "wdt1_ick"),
- DT_CLK(NULL, "gpio1_ick", "gpio1_ick"),
- DT_CLK(NULL, "omap_32ksync_ick", "omap_32ksync_ick"),
- DT_CLK(NULL, "gpt12_ick", "gpt12_ick"),
- DT_CLK(NULL, "gpt1_ick", "gpt1_ick"),
- DT_CLK(NULL, "per_96m_fck", "per_96m_fck"),
- DT_CLK(NULL, "per_48m_fck", "per_48m_fck"),
- DT_CLK(NULL, "uart3_fck", "uart3_fck"),
- DT_CLK(NULL, "gpt2_fck", "gpt2_fck"),
- DT_CLK(NULL, "gpt3_fck", "gpt3_fck"),
- DT_CLK(NULL, "gpt4_fck", "gpt4_fck"),
- DT_CLK(NULL, "gpt5_fck", "gpt5_fck"),
- DT_CLK(NULL, "gpt6_fck", "gpt6_fck"),
- DT_CLK(NULL, "gpt7_fck", "gpt7_fck"),
- DT_CLK(NULL, "gpt8_fck", "gpt8_fck"),
- DT_CLK(NULL, "gpt9_fck", "gpt9_fck"),
- DT_CLK(NULL, "per_32k_alwon_fck", "per_32k_alwon_fck"),
- DT_CLK(NULL, "gpio6_dbck", "gpio6_dbck"),
- DT_CLK(NULL, "gpio5_dbck", "gpio5_dbck"),
- DT_CLK(NULL, "gpio4_dbck", "gpio4_dbck"),
- DT_CLK(NULL, "gpio3_dbck", "gpio3_dbck"),
- DT_CLK(NULL, "gpio2_dbck", "gpio2_dbck"),
- DT_CLK(NULL, "wdt3_fck", "wdt3_fck"),
- DT_CLK(NULL, "per_l4_ick", "per_l4_ick"),
- DT_CLK(NULL, "gpio6_ick", "gpio6_ick"),
- DT_CLK(NULL, "gpio5_ick", "gpio5_ick"),
- DT_CLK(NULL, "gpio4_ick", "gpio4_ick"),
- DT_CLK(NULL, "gpio3_ick", "gpio3_ick"),
- DT_CLK(NULL, "gpio2_ick", "gpio2_ick"),
- DT_CLK(NULL, "wdt3_ick", "wdt3_ick"),
- DT_CLK(NULL, "uart3_ick", "uart3_ick"),
- DT_CLK(NULL, "gpt9_ick", "gpt9_ick"),
- DT_CLK(NULL, "gpt8_ick", "gpt8_ick"),
- DT_CLK(NULL, "gpt7_ick", "gpt7_ick"),
- DT_CLK(NULL, "gpt6_ick", "gpt6_ick"),
- DT_CLK(NULL, "gpt5_ick", "gpt5_ick"),
- DT_CLK(NULL, "gpt4_ick", "gpt4_ick"),
- DT_CLK(NULL, "gpt3_ick", "gpt3_ick"),
- DT_CLK(NULL, "gpt2_ick", "gpt2_ick"),
- DT_CLK(NULL, "mcbsp_clks", "mcbsp_clks"),
- DT_CLK(NULL, "mcbsp1_ick", "mcbsp1_ick"),
- DT_CLK(NULL, "mcbsp2_ick", "mcbsp2_ick"),
- DT_CLK(NULL, "mcbsp3_ick", "mcbsp3_ick"),
- DT_CLK(NULL, "mcbsp4_ick", "mcbsp4_ick"),
- DT_CLK(NULL, "mcbsp5_ick", "mcbsp5_ick"),
- DT_CLK(NULL, "mcbsp1_fck", "mcbsp1_fck"),
- DT_CLK(NULL, "mcbsp2_fck", "mcbsp2_fck"),
- DT_CLK(NULL, "mcbsp3_fck", "mcbsp3_fck"),
- DT_CLK(NULL, "mcbsp4_fck", "mcbsp4_fck"),
- DT_CLK(NULL, "mcbsp5_fck", "mcbsp5_fck"),
- DT_CLK("etb", "emu_src_ck", "emu_src_ck"),
- DT_CLK(NULL, "emu_src_ck", "emu_src_ck"),
- DT_CLK(NULL, "pclk_fck", "pclk_fck"),
- DT_CLK(NULL, "pclkx2_fck", "pclkx2_fck"),
- DT_CLK(NULL, "atclk_fck", "atclk_fck"),
- DT_CLK(NULL, "traceclk_src_fck", "traceclk_src_fck"),
- DT_CLK(NULL, "traceclk_fck", "traceclk_fck"),
- DT_CLK(NULL, "secure_32k_fck", "secure_32k_fck"),
- DT_CLK(NULL, "gpt12_fck", "gpt12_fck"),
- DT_CLK(NULL, "wdt1_fck", "wdt1_fck"),
DT_CLK(NULL, "timer_32k_ck", "omap_32k_fck"),
DT_CLK(NULL, "timer_sys_ck", "sys_ck"),
- DT_CLK(NULL, "cpufreq_ck", "dpll1_ck"),
- { .node_name = NULL },
-};
-
-static struct ti_dt_clk omap34xx_omap36xx_clks[] = {
- DT_CLK(NULL, "aes1_ick", "aes1_ick"),
- DT_CLK("omap_rng", "ick", "rng_ick"),
- DT_CLK("omap3-rom-rng", "ick", "rng_ick"),
- DT_CLK(NULL, "sha11_ick", "sha11_ick"),
- DT_CLK(NULL, "des1_ick", "des1_ick"),
- DT_CLK(NULL, "cam_mclk", "cam_mclk"),
- DT_CLK(NULL, "cam_ick", "cam_ick"),
- DT_CLK(NULL, "csi2_96m_fck", "csi2_96m_fck"),
- DT_CLK(NULL, "security_l3_ick", "security_l3_ick"),
- DT_CLK(NULL, "pka_ick", "pka_ick"),
- DT_CLK(NULL, "icr_ick", "icr_ick"),
- DT_CLK("omap-aes", "ick", "aes2_ick"),
- DT_CLK("omap-sham", "ick", "sha12_ick"),
- DT_CLK(NULL, "des2_ick", "des2_ick"),
- DT_CLK(NULL, "mspro_ick", "mspro_ick"),
- DT_CLK(NULL, "mailboxes_ick", "mailboxes_ick"),
- DT_CLK(NULL, "ssi_l4_ick", "ssi_l4_ick"),
- DT_CLK(NULL, "sr1_fck", "sr1_fck"),
- DT_CLK(NULL, "sr2_fck", "sr2_fck"),
- DT_CLK(NULL, "sr_l4_ick", "sr_l4_ick"),
- DT_CLK(NULL, "security_l4_ick2", "security_l4_ick2"),
- DT_CLK(NULL, "wkup_l4_ick", "wkup_l4_ick"),
- DT_CLK(NULL, "dpll2_fck", "dpll2_fck"),
- DT_CLK(NULL, "iva2_ck", "iva2_ck"),
- DT_CLK(NULL, "modem_fck", "modem_fck"),
- DT_CLK(NULL, "sad2d_ick", "sad2d_ick"),
- DT_CLK(NULL, "mad2d_ick", "mad2d_ick"),
- DT_CLK(NULL, "mspro_fck", "mspro_fck"),
- DT_CLK(NULL, "dpll2_ck", "dpll2_ck"),
- DT_CLK(NULL, "dpll2_m2_ck", "dpll2_m2_ck"),
{ .node_name = NULL },
};
static struct ti_dt_clk omap36xx_omap3430es2plus_clks[] = {
DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es2"),
DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es2"),
- DT_CLK("musb-omap2430", "ick", "hsotgusb_ick_3430es2"),
DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es2"),
DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es2"),
- DT_CLK(NULL, "usim_fck", "usim_fck"),
- DT_CLK(NULL, "usim_ick", "usim_ick"),
{ .node_name = NULL },
};
static struct ti_dt_clk omap3430es1_clks[] = {
- DT_CLK(NULL, "gfx_l3_ck", "gfx_l3_ck"),
- DT_CLK(NULL, "gfx_l3_fck", "gfx_l3_fck"),
- DT_CLK(NULL, "gfx_l3_ick", "gfx_l3_ick"),
- DT_CLK(NULL, "gfx_cg1_ck", "gfx_cg1_ck"),
- DT_CLK(NULL, "gfx_cg2_ck", "gfx_cg2_ck"),
- DT_CLK(NULL, "d2d_26m_fck", "d2d_26m_fck"),
- DT_CLK(NULL, "fshostusb_fck", "fshostusb_fck"),
DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es1"),
DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es1"),
- DT_CLK("musb-omap2430", "ick", "hsotgusb_ick_3430es1"),
DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es1"),
- DT_CLK(NULL, "fac_ick", "fac_ick"),
DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es1"),
- DT_CLK(NULL, "usb_l4_ick", "usb_l4_ick"),
DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es1"),
- DT_CLK("omapdss_dss", "ick", "dss_ick_3430es1"),
DT_CLK(NULL, "dss_ick", "dss_ick_3430es1"),
{ .node_name = NULL },
};
static struct ti_dt_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
- DT_CLK(NULL, "virt_16_8m_ck", "virt_16_8m_ck"),
- DT_CLK(NULL, "dpll5_ck", "dpll5_ck"),
- DT_CLK(NULL, "dpll5_m2_ck", "dpll5_m2_ck"),
- DT_CLK(NULL, "sgx_fck", "sgx_fck"),
- DT_CLK(NULL, "sgx_ick", "sgx_ick"),
- DT_CLK(NULL, "cpefuse_fck", "cpefuse_fck"),
- DT_CLK(NULL, "ts_fck", "ts_fck"),
- DT_CLK(NULL, "usbtll_fck", "usbtll_fck"),
- DT_CLK(NULL, "usbtll_ick", "usbtll_ick"),
- DT_CLK("omap_hsmmc.2", "ick", "mmchs3_ick"),
- DT_CLK(NULL, "mmchs3_ick", "mmchs3_ick"),
- DT_CLK(NULL, "mmchs3_fck", "mmchs3_fck"),
DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es2"),
- DT_CLK("omapdss_dss", "ick", "dss_ick_3430es2"),
DT_CLK(NULL, "dss_ick", "dss_ick_3430es2"),
- DT_CLK(NULL, "usbhost_120m_fck", "usbhost_120m_fck"),
- DT_CLK(NULL, "usbhost_48m_fck", "usbhost_48m_fck"),
- DT_CLK(NULL, "usbhost_ick", "usbhost_ick"),
{ .node_name = NULL },
};
static struct ti_dt_clk am35xx_clks[] = {
- DT_CLK(NULL, "ipss_ick", "ipss_ick"),
- DT_CLK(NULL, "rmii_ck", "rmii_ck"),
- DT_CLK(NULL, "pclk_ck", "pclk_ck"),
- DT_CLK(NULL, "emac_ick", "emac_ick"),
- DT_CLK(NULL, "emac_fck", "emac_fck"),
- DT_CLK("davinci_emac.0", NULL, "emac_ick"),
- DT_CLK("davinci_mdio.0", NULL, "emac_fck"),
- DT_CLK("vpfe-capture", "master", "vpfe_ick"),
- DT_CLK("vpfe-capture", "slave", "vpfe_fck"),
DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_am35xx"),
DT_CLK(NULL, "hsotgusb_fck", "hsotgusb_fck_am35xx"),
- DT_CLK(NULL, "hecc_ck", "hecc_ck"),
DT_CLK(NULL, "uart4_ick", "uart4_ick_am35xx"),
DT_CLK(NULL, "uart4_fck", "uart4_fck_am35xx"),
{ .node_name = NULL },
};
-static struct ti_dt_clk omap36xx_clks[] = {
- DT_CLK(NULL, "omap_192m_alwon_fck", "omap_192m_alwon_fck"),
- DT_CLK(NULL, "uart4_fck", "uart4_fck"),
- DT_CLK(NULL, "uart4_ick", "uart4_ick"),
- { .node_name = NULL },
-};
-
static const char *enable_init_clks[] = {
"sdrc_ick",
"gpmc_fck",
@@ -579,16 +326,10 @@ static int __init omap3xxx_dt_clk_init(int soc_type)
soc_type == OMAP3_SOC_OMAP3630)
ti_dt_clocks_register(omap36xx_omap3430es2plus_clks);
- if (soc_type == OMAP3_SOC_OMAP3430_ES1 ||
- soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS ||
- soc_type == OMAP3_SOC_OMAP3630)
- ti_dt_clocks_register(omap34xx_omap36xx_clks);
-
- if (soc_type == OMAP3_SOC_OMAP3630)
- ti_dt_clocks_register(omap36xx_clks);
-
omap2_clk_disable_autoidle_all();
+ ti_clk_add_aliases();
+
omap2_clk_enable_init_clocks(enable_init_clks,
ARRAY_SIZE(enable_init_clks));
diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c
index e816a7500e43..2b7c2e017665 100644
--- a/drivers/clk/ti/clk-43xx.c
+++ b/drivers/clk/ti/clk-43xx.c
@@ -19,109 +19,208 @@
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/clk/ti.h>
+#include <dt-bindings/clock/am4.h>
#include "clock.h"
+static const char * const am4_synctimer_32kclk_parents[] __initconst = {
+ "mux_synctimer32k_ck",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data am4_counter_32k_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, am4_synctimer_32kclk_parents, NULL },
+ { 0 },
+};
+
+static const char * const am4_gpio0_dbclk_parents[] __initconst = {
+ "gpio0_dbclk_mux_ck",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data am4_gpio1_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, am4_gpio0_dbclk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data am4_l4_wkup_clkctrl_regs[] __initconst = {
+ { AM4_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck", "l3s_tsc_clkdm" },
+ { AM4_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" },
+ { AM4_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "sys_clkin_ck" },
+ { AM4_COUNTER_32K_CLKCTRL, am4_counter_32k_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0210:8" },
+ { AM4_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck", "l4_wkup_clkdm" },
+ { AM4_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck", "l4_wkup_clkdm" },
+ { AM4_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck", "l4_wkup_clkdm" },
+ { AM4_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck", "l4_wkup_clkdm" },
+ { AM4_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck", "l4_wkup_clkdm" },
+ { AM4_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck", "l4_wkup_clkdm" },
+ { AM4_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" },
+ { AM4_GPIO1_CLKCTRL, am4_gpio1_bit_data, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data am4_mpu_clkctrl_regs[] __initconst = {
+ { AM4_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data am4_gfx_l3_clkctrl_regs[] __initconst = {
+ { AM4_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data am4_l4_rtc_clkctrl_regs[] __initconst = {
+ { AM4_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" },
+ { 0 },
+};
+
+static const char * const am4_usb_otg_ss0_refclk960m_parents[] __initconst = {
+ "dpll_per_clkdcoldo",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data am4_usb_otg_ss0_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data am4_usb_otg_ss1_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL },
+ { 0 },
+};
+
+static const char * const am4_gpio1_dbclk_parents[] __initconst = {
+ "clkdiv32k_ick",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data am4_gpio2_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data am4_gpio3_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data am4_gpio4_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data am4_gpio5_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data am4_gpio6_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data am4_l4_per_clkctrl_regs[] __initconst = {
+ { AM4_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
+ { AM4_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck", "l3_clkdm" },
+ { AM4_DES_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
+ { AM4_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
+ { AM4_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
+ { AM4_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
+ { AM4_VPFE0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3s_clkdm" },
+ { AM4_VPFE1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3s_clkdm" },
+ { AM4_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
+ { AM4_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
+ { AM4_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
+ { AM4_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
+ { AM4_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk", "l3_clkdm" },
+ { AM4_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
+ { AM4_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck", "l3s_clkdm" },
+ { AM4_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck", "l3s_clkdm" },
+ { AM4_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk", "l3s_clkdm" },
+ { AM4_QSPI_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
+ { AM4_USB_OTG_SS0_CLKCTRL, am4_usb_otg_ss0_bit_data, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
+ { AM4_USB_OTG_SS1_CLKCTRL, am4_usb_otg_ss1_bit_data, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
+ { AM4_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk", "pruss_ocp_clkdm" },
+ { AM4_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM4_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
+ { AM4_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
+ { AM4_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM4_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM4_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM4_EPWMSS3_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM4_EPWMSS4_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM4_EPWMSS5_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM4_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM4_GPIO2_CLKCTRL, am4_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM4_GPIO3_CLKCTRL, am4_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM4_GPIO4_CLKCTRL, am4_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM4_GPIO5_CLKCTRL, am4_gpio5_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM4_GPIO6_CLKCTRL, am4_gpio6_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM4_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_clk" },
+ { AM4_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM4_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM4_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM4_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
+ { AM4_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
+ { AM4_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
+ { AM4_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM4_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM4_SPI2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM4_SPI3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM4_SPI4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM4_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM4_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
+ { AM4_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
+ { AM4_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
+ { AM4_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
+ { AM4_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
+ { AM4_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
+ { AM4_TIMER8_CLKCTRL, NULL, CLKF_SW_SUP, "timer8_fck" },
+ { AM4_TIMER9_CLKCTRL, NULL, CLKF_SW_SUP, "timer9_fck" },
+ { AM4_TIMER10_CLKCTRL, NULL, CLKF_SW_SUP, "timer10_fck" },
+ { AM4_TIMER11_CLKCTRL, NULL, CLKF_SW_SUP, "timer11_fck" },
+ { AM4_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM4_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM4_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM4_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM4_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM4_OCP2SCP0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM4_OCP2SCP1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM4_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_ck", "emif_clkdm" },
+ { AM4_DSS_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "disp_clk", "dss_clkdm" },
+ { AM4_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk", "cpsw_125mhz_clkdm" },
+ { 0 },
+};
+
+const struct omap_clkctrl_data am4_clkctrl_data[] __initconst = {
+ { 0x44df2820, am4_l4_wkup_clkctrl_regs },
+ { 0x44df8320, am4_mpu_clkctrl_regs },
+ { 0x44df8420, am4_gfx_l3_clkctrl_regs },
+ { 0x44df8520, am4_l4_rtc_clkctrl_regs },
+ { 0x44df8820, am4_l4_per_clkctrl_regs },
+ { 0 },
+};
+
+const struct omap_clkctrl_data am438x_clkctrl_data[] __initconst = {
+ { 0x44df2820, am4_l4_wkup_clkctrl_regs },
+ { 0x44df8320, am4_mpu_clkctrl_regs },
+ { 0x44df8420, am4_gfx_l3_clkctrl_regs },
+ { 0x44df8820, am4_l4_per_clkctrl_regs },
+ { 0 },
+};
+
static struct ti_dt_clk am43xx_clks[] = {
- DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"),
- DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"),
- DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
- DT_CLK(NULL, "virt_24000000_ck", "virt_24000000_ck"),
- DT_CLK(NULL, "virt_25000000_ck", "virt_25000000_ck"),
- DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
- DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"),
- DT_CLK(NULL, "tclkin_ck", "tclkin_ck"),
- DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
- DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
- DT_CLK(NULL, "dpll_core_m4_ck", "dpll_core_m4_ck"),
- DT_CLK(NULL, "dpll_core_m5_ck", "dpll_core_m5_ck"),
- DT_CLK(NULL, "dpll_core_m6_ck", "dpll_core_m6_ck"),
- DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
- DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
- DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"),
- DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"),
- DT_CLK(NULL, "dpll_disp_ck", "dpll_disp_ck"),
- DT_CLK(NULL, "dpll_disp_m2_ck", "dpll_disp_m2_ck"),
- DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
- DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
- DT_CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", "dpll_per_m2_div4_wkupdm_ck"),
- DT_CLK(NULL, "dpll_per_m2_div4_ck", "dpll_per_m2_div4_ck"),
- DT_CLK(NULL, "adc_tsc_fck", "adc_tsc_fck"),
- DT_CLK(NULL, "clkdiv32k_ck", "clkdiv32k_ck"),
- DT_CLK(NULL, "clkdiv32k_ick", "clkdiv32k_ick"),
- DT_CLK(NULL, "dcan0_fck", "dcan0_fck"),
- DT_CLK(NULL, "dcan1_fck", "dcan1_fck"),
- DT_CLK(NULL, "pruss_ocp_gclk", "pruss_ocp_gclk"),
- DT_CLK(NULL, "mcasp0_fck", "mcasp0_fck"),
- DT_CLK(NULL, "mcasp1_fck", "mcasp1_fck"),
- DT_CLK(NULL, "smartreflex0_fck", "smartreflex0_fck"),
- DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"),
- DT_CLK(NULL, "sha0_fck", "sha0_fck"),
- DT_CLK(NULL, "aes0_fck", "aes0_fck"),
- DT_CLK(NULL, "rng_fck", "rng_fck"),
- DT_CLK(NULL, "timer1_fck", "timer1_fck"),
- DT_CLK(NULL, "timer2_fck", "timer2_fck"),
- DT_CLK(NULL, "timer3_fck", "timer3_fck"),
- DT_CLK(NULL, "timer4_fck", "timer4_fck"),
- DT_CLK(NULL, "timer5_fck", "timer5_fck"),
- DT_CLK(NULL, "timer6_fck", "timer6_fck"),
- DT_CLK(NULL, "timer7_fck", "timer7_fck"),
- DT_CLK(NULL, "wdt1_fck", "wdt1_fck"),
- DT_CLK(NULL, "l3_gclk", "l3_gclk"),
- DT_CLK(NULL, "dpll_core_m4_div2_ck", "dpll_core_m4_div2_ck"),
- DT_CLK(NULL, "l4hs_gclk", "l4hs_gclk"),
- DT_CLK(NULL, "l3s_gclk", "l3s_gclk"),
- DT_CLK(NULL, "l4ls_gclk", "l4ls_gclk"),
- DT_CLK(NULL, "clk_24mhz", "clk_24mhz"),
- DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),
- DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),
- DT_CLK(NULL, "dpll_clksel_mac_clk", "dpll_clksel_mac_clk"),
- DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"),
- DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"),
- DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
- DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
- DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
- DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"),
- DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"),
- DT_CLK(NULL, "mmc_clk", "mmc_clk"),
- DT_CLK(NULL, "gfx_fclk_clksel_ck", "gfx_fclk_clksel_ck"),
- DT_CLK(NULL, "gfx_fck_div_ck", "gfx_fck_div_ck"),
DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
- DT_CLK(NULL, "sysclk_div", "sysclk_div"),
- DT_CLK(NULL, "disp_clk", "disp_clk"),
- DT_CLK(NULL, "clk_32k_mosc_ck", "clk_32k_mosc_ck"),
- DT_CLK(NULL, "clk_32k_tpm_ck", "clk_32k_tpm_ck"),
- DT_CLK(NULL, "dpll_extdev_ck", "dpll_extdev_ck"),
- DT_CLK(NULL, "dpll_extdev_m2_ck", "dpll_extdev_m2_ck"),
- DT_CLK(NULL, "mux_synctimer32k_ck", "mux_synctimer32k_ck"),
- DT_CLK(NULL, "synctimer_32kclk", "synctimer_32kclk"),
- DT_CLK(NULL, "timer8_fck", "timer8_fck"),
- DT_CLK(NULL, "timer9_fck", "timer9_fck"),
- DT_CLK(NULL, "timer10_fck", "timer10_fck"),
- DT_CLK(NULL, "timer11_fck", "timer11_fck"),
- DT_CLK(NULL, "cpsw_50m_clkdiv", "cpsw_50m_clkdiv"),
- DT_CLK(NULL, "cpsw_5m_clkdiv", "cpsw_5m_clkdiv"),
- DT_CLK(NULL, "dpll_ddr_x2_ck", "dpll_ddr_x2_ck"),
- DT_CLK(NULL, "dpll_ddr_m4_ck", "dpll_ddr_m4_ck"),
- DT_CLK(NULL, "dpll_per_clkdcoldo", "dpll_per_clkdcoldo"),
- DT_CLK(NULL, "dll_aging_clk_div", "dll_aging_clk_div"),
- DT_CLK(NULL, "div_core_25m_ck", "div_core_25m_ck"),
- DT_CLK(NULL, "func_12m_clk", "func_12m_clk"),
- DT_CLK(NULL, "vtp_clk_div", "vtp_clk_div"),
- DT_CLK(NULL, "usbphy_32khz_clkmux", "usbphy_32khz_clkmux"),
- DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"),
- DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"),
- DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"),
- DT_CLK("48306200.ehrpwm", "tbclk", "ehrpwm3_tbclk"),
- DT_CLK("48308200.ehrpwm", "tbclk", "ehrpwm4_tbclk"),
- DT_CLK("4830a200.ehrpwm", "tbclk", "ehrpwm5_tbclk"),
- DT_CLK("48300200.pwm", "tbclk", "ehrpwm0_tbclk"),
- DT_CLK("48302200.pwm", "tbclk", "ehrpwm1_tbclk"),
- DT_CLK("48304200.pwm", "tbclk", "ehrpwm2_tbclk"),
- DT_CLK("48306200.pwm", "tbclk", "ehrpwm3_tbclk"),
- DT_CLK("48308200.pwm", "tbclk", "ehrpwm4_tbclk"),
- DT_CLK("4830a200.pwm", "tbclk", "ehrpwm5_tbclk"),
+ DT_CLK(NULL, "gpio0_dbclk", "l4_wkup_cm:0348:8"),
+ DT_CLK(NULL, "gpio1_dbclk", "l4_per_cm:0458:8"),
+ DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:0460:8"),
+ DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:0468:8"),
+ DT_CLK(NULL, "gpio4_dbclk", "l4_per_cm:0470:8"),
+ DT_CLK(NULL, "gpio5_dbclk", "l4_per_cm:0478:8"),
+ DT_CLK(NULL, "synctimer_32kclk", "l4_wkup_cm:0210:8"),
+ DT_CLK(NULL, "usb_otg_ss0_refclk960m", "l4_per_cm:0240:8"),
+ DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l4_per_cm:0248:8"),
{ .node_name = NULL },
};
@@ -133,6 +232,8 @@ int __init am43xx_dt_clk_init(void)
omap2_clk_disable_autoidle_all();
+ ti_clk_add_aliases();
+
/*
* cpsw_cpts_rft_clk has got the choice of 3 clocksources
* dpll_core_m4_ck, dpll_core_m5_ck and dpll_disp_m2_ck.
diff --git a/drivers/clk/ti/clk-44xx.c b/drivers/clk/ti/clk-44xx.c
index 2005f032c02f..339d30d64ebb 100644
--- a/drivers/clk/ti/clk-44xx.c
+++ b/drivers/clk/ti/clk-44xx.c
@@ -35,7 +35,7 @@
#define OMAP4_DPLL_USB_DEFFREQ 960000000
static const struct omap_clkctrl_reg_data omap4_mpuss_clkctrl_regs[] __initconst = {
- { OMAP4_MPU_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_mpu_m2_ck" },
+ { OMAP4_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
{ 0 },
};
@@ -59,7 +59,7 @@ static const struct omap_clkctrl_bit_data omap4_aess_bit_data[] __initconst = {
};
static const char * const omap4_func_dmic_abe_gfclk_parents[] __initconst = {
- "dmic_sync_mux_ck",
+ "abe_cm:clk:0018:26",
"pad_clks_ck",
"slimbus_clk",
NULL,
@@ -79,7 +79,7 @@ static const struct omap_clkctrl_bit_data omap4_dmic_bit_data[] __initconst = {
};
static const char * const omap4_func_mcasp_abe_gfclk_parents[] __initconst = {
- "mcasp_sync_mux_ck",
+ "abe_cm:clk:0020:26",
"pad_clks_ck",
"slimbus_clk",
NULL,
@@ -92,7 +92,7 @@ static const struct omap_clkctrl_bit_data omap4_mcasp_bit_data[] __initconst = {
};
static const char * const omap4_func_mcbsp1_gfclk_parents[] __initconst = {
- "mcbsp1_sync_mux_ck",
+ "abe_cm:clk:0028:26",
"pad_clks_ck",
"slimbus_clk",
NULL,
@@ -105,7 +105,7 @@ static const struct omap_clkctrl_bit_data omap4_mcbsp1_bit_data[] __initconst =
};
static const char * const omap4_func_mcbsp2_gfclk_parents[] __initconst = {
- "mcbsp2_sync_mux_ck",
+ "abe_cm:clk:0030:26",
"pad_clks_ck",
"slimbus_clk",
NULL,
@@ -118,7 +118,7 @@ static const struct omap_clkctrl_bit_data omap4_mcbsp2_bit_data[] __initconst =
};
static const char * const omap4_func_mcbsp3_gfclk_parents[] __initconst = {
- "mcbsp3_sync_mux_ck",
+ "abe_cm:clk:0038:26",
"pad_clks_ck",
"slimbus_clk",
NULL,
@@ -186,18 +186,18 @@ static const struct omap_clkctrl_bit_data omap4_timer8_bit_data[] __initconst =
static const struct omap_clkctrl_reg_data omap4_abe_clkctrl_regs[] __initconst = {
{ OMAP4_L4_ABE_CLKCTRL, NULL, 0, "ocp_abe_iclk" },
- { OMAP4_AESS_CLKCTRL, omap4_aess_bit_data, CLKF_SW_SUP, "aess_fclk" },
+ { OMAP4_AESS_CLKCTRL, omap4_aess_bit_data, CLKF_SW_SUP, "abe_cm:clk:0008:24" },
{ OMAP4_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" },
- { OMAP4_DMIC_CLKCTRL, omap4_dmic_bit_data, CLKF_SW_SUP, "func_dmic_abe_gfclk" },
- { OMAP4_MCASP_CLKCTRL, omap4_mcasp_bit_data, CLKF_SW_SUP, "func_mcasp_abe_gfclk" },
- { OMAP4_MCBSP1_CLKCTRL, omap4_mcbsp1_bit_data, CLKF_SW_SUP, "func_mcbsp1_gfclk" },
- { OMAP4_MCBSP2_CLKCTRL, omap4_mcbsp2_bit_data, CLKF_SW_SUP, "func_mcbsp2_gfclk" },
- { OMAP4_MCBSP3_CLKCTRL, omap4_mcbsp3_bit_data, CLKF_SW_SUP, "func_mcbsp3_gfclk" },
- { OMAP4_SLIMBUS1_CLKCTRL, omap4_slimbus1_bit_data, CLKF_SW_SUP, "slimbus1_fclk_0" },
- { OMAP4_TIMER5_CLKCTRL, omap4_timer5_bit_data, CLKF_SW_SUP, "timer5_sync_mux" },
- { OMAP4_TIMER6_CLKCTRL, omap4_timer6_bit_data, CLKF_SW_SUP, "timer6_sync_mux" },
- { OMAP4_TIMER7_CLKCTRL, omap4_timer7_bit_data, CLKF_SW_SUP, "timer7_sync_mux" },
- { OMAP4_TIMER8_CLKCTRL, omap4_timer8_bit_data, CLKF_SW_SUP, "timer8_sync_mux" },
+ { OMAP4_DMIC_CLKCTRL, omap4_dmic_bit_data, CLKF_SW_SUP, "abe_cm:clk:0018:24" },
+ { OMAP4_MCASP_CLKCTRL, omap4_mcasp_bit_data, CLKF_SW_SUP, "abe_cm:clk:0020:24" },
+ { OMAP4_MCBSP1_CLKCTRL, omap4_mcbsp1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0028:24" },
+ { OMAP4_MCBSP2_CLKCTRL, omap4_mcbsp2_bit_data, CLKF_SW_SUP, "abe_cm:clk:0030:24" },
+ { OMAP4_MCBSP3_CLKCTRL, omap4_mcbsp3_bit_data, CLKF_SW_SUP, "abe_cm:clk:0038:24" },
+ { OMAP4_SLIMBUS1_CLKCTRL, omap4_slimbus1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0040:8" },
+ { OMAP4_TIMER5_CLKCTRL, omap4_timer5_bit_data, CLKF_SW_SUP, "abe_cm:clk:0048:24" },
+ { OMAP4_TIMER6_CLKCTRL, omap4_timer6_bit_data, CLKF_SW_SUP, "abe_cm:clk:0050:24" },
+ { OMAP4_TIMER7_CLKCTRL, omap4_timer7_bit_data, CLKF_SW_SUP, "abe_cm:clk:0058:24" },
+ { OMAP4_TIMER8_CLKCTRL, omap4_timer8_bit_data, CLKF_SW_SUP, "abe_cm:clk:0060:24" },
{ OMAP4_WD_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
{ 0 },
};
@@ -280,6 +280,7 @@ static const char * const omap4_fdif_fck_parents[] __initconst = {
static const struct omap_clkctrl_div_data omap4_fdif_fck_data __initconst = {
.max_div = 4,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
};
static const struct omap_clkctrl_bit_data omap4_fdif_bit_data[] __initconst = {
@@ -289,7 +290,7 @@ static const struct omap_clkctrl_bit_data omap4_fdif_bit_data[] __initconst = {
static const struct omap_clkctrl_reg_data omap4_iss_clkctrl_regs[] __initconst = {
{ OMAP4_ISS_CLKCTRL, omap4_iss_bit_data, CLKF_SW_SUP, "ducati_clk_mux_ck" },
- { OMAP4_FDIF_CLKCTRL, omap4_fdif_bit_data, CLKF_SW_SUP, "fdif_fck" },
+ { OMAP4_FDIF_CLKCTRL, omap4_fdif_bit_data, CLKF_SW_SUP, "iss_cm:clk:0008:24" },
{ 0 },
};
@@ -322,7 +323,7 @@ static const struct omap_clkctrl_bit_data omap4_dss_core_bit_data[] __initconst
};
static const struct omap_clkctrl_reg_data omap4_l3_dss_clkctrl_regs[] __initconst = {
- { OMAP4_DSS_CORE_CLKCTRL, omap4_dss_core_bit_data, CLKF_SW_SUP, "dss_dss_clk" },
+ { OMAP4_DSS_CORE_CLKCTRL, omap4_dss_core_bit_data, CLKF_SW_SUP, "l3_dss_cm:clk:0000:8" },
{ 0 },
};
@@ -338,7 +339,7 @@ static const struct omap_clkctrl_bit_data omap4_gpu_bit_data[] __initconst = {
};
static const struct omap_clkctrl_reg_data omap4_l3_gfx_clkctrl_regs[] __initconst = {
- { OMAP4_GPU_CLKCTRL, omap4_gpu_bit_data, CLKF_SW_SUP, "sgx_clk_mux" },
+ { OMAP4_GPU_CLKCTRL, omap4_gpu_bit_data, CLKF_SW_SUP, "l3_gfx_cm:clk:0000:24" },
{ 0 },
};
@@ -365,6 +366,7 @@ static const char * const omap4_hsi_fck_parents[] __initconst = {
static const struct omap_clkctrl_div_data omap4_hsi_fck_data __initconst = {
.max_div = 4,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
};
static const struct omap_clkctrl_bit_data omap4_hsi_bit_data[] __initconst = {
@@ -373,12 +375,12 @@ static const struct omap_clkctrl_bit_data omap4_hsi_bit_data[] __initconst = {
};
static const char * const omap4_usb_host_hs_utmi_p1_clk_parents[] __initconst = {
- "utmi_p1_gfclk",
+ "l3_init_cm:clk:0038:24",
NULL,
};
static const char * const omap4_usb_host_hs_utmi_p2_clk_parents[] __initconst = {
- "utmi_p2_gfclk",
+ "l3_init_cm:clk:0038:25",
NULL,
};
@@ -419,7 +421,7 @@ static const struct omap_clkctrl_bit_data omap4_usb_host_hs_bit_data[] __initcon
};
static const char * const omap4_usb_otg_hs_xclk_parents[] __initconst = {
- "otg_60m_gfclk",
+ "l3_init_cm:clk:0040:24",
NULL,
};
@@ -453,14 +455,14 @@ static const struct omap_clkctrl_bit_data omap4_ocp2scp_usb_phy_bit_data[] __ini
};
static const struct omap_clkctrl_reg_data omap4_l3_init_clkctrl_regs[] __initconst = {
- { OMAP4_MMC1_CLKCTRL, omap4_mmc1_bit_data, CLKF_SW_SUP, "hsmmc1_fclk" },
- { OMAP4_MMC2_CLKCTRL, omap4_mmc2_bit_data, CLKF_SW_SUP, "hsmmc2_fclk" },
- { OMAP4_HSI_CLKCTRL, omap4_hsi_bit_data, CLKF_HW_SUP, "hsi_fck" },
+ { OMAP4_MMC1_CLKCTRL, omap4_mmc1_bit_data, CLKF_SW_SUP, "l3_init_cm:clk:0008:24" },
+ { OMAP4_MMC2_CLKCTRL, omap4_mmc2_bit_data, CLKF_SW_SUP, "l3_init_cm:clk:0010:24" },
+ { OMAP4_HSI_CLKCTRL, omap4_hsi_bit_data, CLKF_HW_SUP, "l3_init_cm:clk:0018:24" },
{ OMAP4_USB_HOST_HS_CLKCTRL, omap4_usb_host_hs_bit_data, CLKF_SW_SUP, "init_60m_fclk" },
{ OMAP4_USB_OTG_HS_CLKCTRL, omap4_usb_otg_hs_bit_data, CLKF_HW_SUP, "l3_div_ck" },
{ OMAP4_USB_TLL_HS_CLKCTRL, omap4_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_div_ck" },
{ OMAP4_USB_HOST_FS_CLKCTRL, NULL, CLKF_SW_SUP, "func_48mc_fclk" },
- { OMAP4_OCP2SCP_USB_PHY_CLKCTRL, omap4_ocp2scp_usb_phy_bit_data, CLKF_HW_SUP, "ocp2scp_usb_phy_phy_48m" },
+ { OMAP4_OCP2SCP_USB_PHY_CLKCTRL, omap4_ocp2scp_usb_phy_bit_data, CLKF_HW_SUP, "l3_init_cm:clk:00c0:8" },
{ 0 },
};
@@ -531,7 +533,7 @@ static const struct omap_clkctrl_bit_data omap4_gpio6_bit_data[] __initconst = {
};
static const char * const omap4_per_mcbsp4_gfclk_parents[] __initconst = {
- "mcbsp4_sync_mux_ck",
+ "l4_per_cm:clk:00c0:26",
"pad_clks_ck",
NULL,
};
@@ -544,7 +546,7 @@ static const char * const omap4_mcbsp4_sync_mux_ck_parents[] __initconst = {
static const struct omap_clkctrl_bit_data omap4_mcbsp4_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap4_per_mcbsp4_gfclk_parents, NULL },
- { 25, TI_CLK_MUX, omap4_mcbsp4_sync_mux_ck_parents, NULL },
+ { 26, TI_CLK_MUX, omap4_mcbsp4_sync_mux_ck_parents, NULL },
{ 0 },
};
@@ -571,12 +573,12 @@ static const struct omap_clkctrl_bit_data omap4_slimbus2_bit_data[] __initconst
};
static const struct omap_clkctrl_reg_data omap4_l4_per_clkctrl_regs[] __initconst = {
- { OMAP4_TIMER10_CLKCTRL, omap4_timer10_bit_data, CLKF_SW_SUP, "cm2_dm10_mux" },
- { OMAP4_TIMER11_CLKCTRL, omap4_timer11_bit_data, CLKF_SW_SUP, "cm2_dm11_mux" },
- { OMAP4_TIMER2_CLKCTRL, omap4_timer2_bit_data, CLKF_SW_SUP, "cm2_dm2_mux" },
- { OMAP4_TIMER3_CLKCTRL, omap4_timer3_bit_data, CLKF_SW_SUP, "cm2_dm3_mux" },
- { OMAP4_TIMER4_CLKCTRL, omap4_timer4_bit_data, CLKF_SW_SUP, "cm2_dm4_mux" },
- { OMAP4_TIMER9_CLKCTRL, omap4_timer9_bit_data, CLKF_SW_SUP, "cm2_dm9_mux" },
+ { OMAP4_TIMER10_CLKCTRL, omap4_timer10_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0008:24" },
+ { OMAP4_TIMER11_CLKCTRL, omap4_timer11_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0010:24" },
+ { OMAP4_TIMER2_CLKCTRL, omap4_timer2_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0018:24" },
+ { OMAP4_TIMER3_CLKCTRL, omap4_timer3_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0020:24" },
+ { OMAP4_TIMER4_CLKCTRL, omap4_timer4_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0028:24" },
+ { OMAP4_TIMER9_CLKCTRL, omap4_timer9_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0030:24" },
{ OMAP4_ELM_CLKCTRL, NULL, 0, "l4_div_ck" },
{ OMAP4_GPIO2_CLKCTRL, omap4_gpio2_bit_data, CLKF_HW_SUP, "l4_div_ck" },
{ OMAP4_GPIO3_CLKCTRL, omap4_gpio3_bit_data, CLKF_HW_SUP, "l4_div_ck" },
@@ -589,14 +591,14 @@ static const struct omap_clkctrl_reg_data omap4_l4_per_clkctrl_regs[] __initcons
{ OMAP4_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ OMAP4_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ OMAP4_L4_PER_CLKCTRL, NULL, 0, "l4_div_ck" },
- { OMAP4_MCBSP4_CLKCTRL, omap4_mcbsp4_bit_data, CLKF_SW_SUP, "per_mcbsp4_gfclk" },
+ { OMAP4_MCBSP4_CLKCTRL, omap4_mcbsp4_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:00c0:24" },
{ OMAP4_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP4_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP4_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP4_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP4_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP4_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
- { OMAP4_SLIMBUS2_CLKCTRL, omap4_slimbus2_bit_data, CLKF_SW_SUP, "slimbus2_fclk_0" },
+ { OMAP4_SLIMBUS2_CLKCTRL, omap4_slimbus2_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0118:8" },
{ OMAP4_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP4_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP4_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
@@ -619,7 +621,7 @@ static const struct omap_clkctrl_reg_data omap4_l4_wkup_clkctrl_regs[] __initcon
{ OMAP4_L4_WKUP_CLKCTRL, NULL, 0, "l4_wkup_clk_mux_ck" },
{ OMAP4_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
{ OMAP4_GPIO1_CLKCTRL, omap4_gpio1_bit_data, CLKF_HW_SUP, "l4_wkup_clk_mux_ck" },
- { OMAP4_TIMER1_CLKCTRL, omap4_timer1_bit_data, CLKF_SW_SUP, "dmt1_clk_mux" },
+ { OMAP4_TIMER1_CLKCTRL, omap4_timer1_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0020:24" },
{ OMAP4_COUNTER_32K_CLKCTRL, NULL, 0, "sys_32k_ck" },
{ OMAP4_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
{ 0 },
@@ -633,7 +635,7 @@ static const char * const omap4_pmd_stm_clock_mux_ck_parents[] __initconst = {
};
static const char * const omap4_trace_clk_div_div_ck_parents[] __initconst = {
- "pmd_trace_clk_mux_ck",
+ "emu_sys_cm:clk:0000:22",
NULL,
};
@@ -651,12 +653,13 @@ static const struct omap_clkctrl_div_data omap4_trace_clk_div_div_ck_data __init
};
static const char * const omap4_stm_clk_div_ck_parents[] __initconst = {
- "pmd_stm_clock_mux_ck",
+ "emu_sys_cm:clk:0000:20",
NULL,
};
static const struct omap_clkctrl_div_data omap4_stm_clk_div_ck_data __initconst = {
.max_div = 64,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
};
static const struct omap_clkctrl_bit_data omap4_debugss_bit_data[] __initconst = {
@@ -697,52 +700,79 @@ const struct omap_clkctrl_data omap4_clkctrl_data[] __initconst = {
};
static struct ti_dt_clk omap44xx_clks[] = {
- DT_CLK("smp_twd", NULL, "mpu_periphclk"),
- DT_CLK("omapdss_dss", "ick", "dss_fck"),
- DT_CLK("usbhs_omap", "fs_fck", "usb_host_fs_fck"),
- DT_CLK("usbhs_omap", "hs_fck", "usb_host_hs_fck"),
- DT_CLK("musb-omap2430", "ick", "usb_otg_hs_ick"),
- DT_CLK("usbhs_omap", "usbtll_ick", "usb_tll_hs_ick"),
- DT_CLK("usbhs_tll", "usbtll_ick", "usb_tll_hs_ick"),
- DT_CLK("omap_i2c.1", "ick", "dummy_ck"),
- DT_CLK("omap_i2c.2", "ick", "dummy_ck"),
- DT_CLK("omap_i2c.3", "ick", "dummy_ck"),
- DT_CLK("omap_i2c.4", "ick", "dummy_ck"),
- DT_CLK(NULL, "mailboxes_ick", "dummy_ck"),
- DT_CLK("omap_hsmmc.0", "ick", "dummy_ck"),
- DT_CLK("omap_hsmmc.1", "ick", "dummy_ck"),
- DT_CLK("omap_hsmmc.2", "ick", "dummy_ck"),
- DT_CLK("omap_hsmmc.3", "ick", "dummy_ck"),
- DT_CLK("omap_hsmmc.4", "ick", "dummy_ck"),
- DT_CLK("omap-mcbsp.1", "ick", "dummy_ck"),
- DT_CLK("omap-mcbsp.2", "ick", "dummy_ck"),
- DT_CLK("omap-mcbsp.3", "ick", "dummy_ck"),
- DT_CLK("omap-mcbsp.4", "ick", "dummy_ck"),
- DT_CLK("omap2_mcspi.1", "ick", "dummy_ck"),
- DT_CLK("omap2_mcspi.2", "ick", "dummy_ck"),
- DT_CLK("omap2_mcspi.3", "ick", "dummy_ck"),
- DT_CLK("omap2_mcspi.4", "ick", "dummy_ck"),
- DT_CLK(NULL, "uart1_ick", "dummy_ck"),
- DT_CLK(NULL, "uart2_ick", "dummy_ck"),
- DT_CLK(NULL, "uart3_ick", "dummy_ck"),
- DT_CLK(NULL, "uart4_ick", "dummy_ck"),
- DT_CLK("usbhs_omap", "usbhost_ick", "dummy_ck"),
- DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"),
- DT_CLK("usbhs_tll", "usbtll_fck", "dummy_ck"),
- DT_CLK("omap_wdt", "ick", "dummy_ck"),
DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
- DT_CLK("4a318000.timer", "timer_sys_ck", "sys_clkin_ck"),
- DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin_ck"),
- DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin_ck"),
- DT_CLK("48036000.timer", "timer_sys_ck", "sys_clkin_ck"),
- DT_CLK("4803e000.timer", "timer_sys_ck", "sys_clkin_ck"),
- DT_CLK("48086000.timer", "timer_sys_ck", "sys_clkin_ck"),
- DT_CLK("48088000.timer", "timer_sys_ck", "sys_clkin_ck"),
- DT_CLK("40138000.timer", "timer_sys_ck", "syc_clk_div_ck"),
- DT_CLK("4013a000.timer", "timer_sys_ck", "syc_clk_div_ck"),
- DT_CLK("4013c000.timer", "timer_sys_ck", "syc_clk_div_ck"),
- DT_CLK("4013e000.timer", "timer_sys_ck", "syc_clk_div_ck"),
- DT_CLK(NULL, "cpufreq_ck", "dpll_mpu_ck"),
+ /*
+ * XXX: All the clock aliases below are only needed for legacy
+ * hwmod support. Once hwmod is removed, these can be removed
+ * also.
+ */
+ DT_CLK(NULL, "aess_fclk", "abe_cm:0008:24"),
+ DT_CLK(NULL, "cm2_dm10_mux", "l4_per_cm:0008:24"),
+ DT_CLK(NULL, "cm2_dm11_mux", "l4_per_cm:0010:24"),
+ DT_CLK(NULL, "cm2_dm2_mux", "l4_per_cm:0018:24"),
+ DT_CLK(NULL, "cm2_dm3_mux", "l4_per_cm:0020:24"),
+ DT_CLK(NULL, "cm2_dm4_mux", "l4_per_cm:0028:24"),
+ DT_CLK(NULL, "cm2_dm9_mux", "l4_per_cm:0030:24"),
+ DT_CLK(NULL, "dmic_sync_mux_ck", "abe_cm:0018:26"),
+ DT_CLK(NULL, "dmt1_clk_mux", "l4_wkup_cm:0020:24"),
+ DT_CLK(NULL, "dss_48mhz_clk", "l3_dss_cm:0000:9"),
+ DT_CLK(NULL, "dss_dss_clk", "l3_dss_cm:0000:8"),
+ DT_CLK(NULL, "dss_sys_clk", "l3_dss_cm:0000:10"),
+ DT_CLK(NULL, "dss_tv_clk", "l3_dss_cm:0000:11"),
+ DT_CLK(NULL, "fdif_fck", "iss_cm:0008:24"),
+ DT_CLK(NULL, "func_dmic_abe_gfclk", "abe_cm:0018:24"),
+ DT_CLK(NULL, "func_mcasp_abe_gfclk", "abe_cm:0020:24"),
+ DT_CLK(NULL, "func_mcbsp1_gfclk", "abe_cm:0028:24"),
+ DT_CLK(NULL, "func_mcbsp2_gfclk", "abe_cm:0030:24"),
+ DT_CLK(NULL, "func_mcbsp3_gfclk", "abe_cm:0038:24"),
+ DT_CLK(NULL, "gpio1_dbclk", "l4_wkup_cm:0018:8"),
+ DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:0040:8"),
+ DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:0048:8"),
+ DT_CLK(NULL, "gpio4_dbclk", "l4_per_cm:0050:8"),
+ DT_CLK(NULL, "gpio5_dbclk", "l4_per_cm:0058:8"),
+ DT_CLK(NULL, "gpio6_dbclk", "l4_per_cm:0060:8"),
+ DT_CLK(NULL, "hsi_fck", "l3_init_cm:0018:24"),
+ DT_CLK(NULL, "hsmmc1_fclk", "l3_init_cm:0008:24"),
+ DT_CLK(NULL, "hsmmc2_fclk", "l3_init_cm:0010:24"),
+ DT_CLK(NULL, "iss_ctrlclk", "iss_cm:0000:8"),
+ DT_CLK(NULL, "mcasp_sync_mux_ck", "abe_cm:0020:26"),
+ DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe_cm:0028:26"),
+ DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe_cm:0030:26"),
+ DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe_cm:0038:26"),
+ DT_CLK(NULL, "mcbsp4_sync_mux_ck", "l4_per_cm:00c0:26"),
+ DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "l3_init_cm:00c0:8"),
+ DT_CLK(NULL, "otg_60m_gfclk", "l3_init_cm:0040:24"),
+ DT_CLK(NULL, "per_mcbsp4_gfclk", "l4_per_cm:00c0:24"),
+ DT_CLK(NULL, "pmd_stm_clock_mux_ck", "emu_sys_cm:0000:20"),
+ DT_CLK(NULL, "pmd_trace_clk_mux_ck", "emu_sys_cm:0000:22"),
+ DT_CLK(NULL, "sgx_clk_mux", "l3_gfx_cm:0000:24"),
+ DT_CLK(NULL, "slimbus1_fclk_0", "abe_cm:0040:8"),
+ DT_CLK(NULL, "slimbus1_fclk_1", "abe_cm:0040:9"),
+ DT_CLK(NULL, "slimbus1_fclk_2", "abe_cm:0040:10"),
+ DT_CLK(NULL, "slimbus1_slimbus_clk", "abe_cm:0040:11"),
+ DT_CLK(NULL, "slimbus2_fclk_0", "l4_per_cm:0118:8"),
+ DT_CLK(NULL, "slimbus2_fclk_1", "l4_per_cm:0118:9"),
+ DT_CLK(NULL, "slimbus2_slimbus_clk", "l4_per_cm:0118:10"),
+ DT_CLK(NULL, "stm_clk_div_ck", "emu_sys_cm:0000:27"),
+ DT_CLK(NULL, "timer5_sync_mux", "abe_cm:0048:24"),
+ DT_CLK(NULL, "timer6_sync_mux", "abe_cm:0050:24"),
+ DT_CLK(NULL, "timer7_sync_mux", "abe_cm:0058:24"),
+ DT_CLK(NULL, "timer8_sync_mux", "abe_cm:0060:24"),
+ DT_CLK(NULL, "trace_clk_div_div_ck", "emu_sys_cm:0000:24"),
+ DT_CLK(NULL, "usb_host_hs_func48mclk", "l3_init_cm:0038:15"),
+ DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3_init_cm:0038:13"),
+ DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3_init_cm:0038:14"),
+ DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3_init_cm:0038:11"),
+ DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3_init_cm:0038:12"),
+ DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3_init_cm:0038:8"),
+ DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3_init_cm:0038:9"),
+ DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3_init_cm:0038:10"),
+ DT_CLK(NULL, "usb_otg_hs_xclk", "l3_init_cm:0040:8"),
+ DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3_init_cm:0048:8"),
+ DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3_init_cm:0048:9"),
+ DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3_init_cm:0048:10"),
+ DT_CLK(NULL, "utmi_p1_gfclk", "l3_init_cm:0038:24"),
+ DT_CLK(NULL, "utmi_p2_gfclk", "l3_init_cm:0038:25"),
{ .node_name = NULL },
};
diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c
index 294bc03ec067..a17b0c4646a1 100644
--- a/drivers/clk/ti/clk-54xx.c
+++ b/drivers/clk/ti/clk-54xx.c
@@ -16,6 +16,7 @@
#include <linux/clkdev.h>
#include <linux/io.h>
#include <linux/clk/ti.h>
+#include <dt-bindings/clock/omap5.h>
#include "clock.h"
@@ -27,201 +28,511 @@
*/
#define OMAP5_DPLL_USB_DEFFREQ 960000000
+static const struct omap_clkctrl_reg_data omap5_mpu_clkctrl_regs[] __initconst = {
+ { OMAP5_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap5_dsp_clkctrl_regs[] __initconst = {
+ { OMAP5_MMU_DSP_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h11x2_ck" },
+ { 0 },
+};
+
+static const char * const omap5_dmic_gfclk_parents[] __initconst = {
+ "abe_cm:clk:0018:26",
+ "pad_clks_ck",
+ "slimbus_clk",
+ NULL,
+};
+
+static const char * const omap5_dmic_sync_mux_ck_parents[] __initconst = {
+ "abe_24m_fclk",
+ "dss_syc_gfclk_div",
+ "func_24m_clk",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap5_dmic_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, omap5_dmic_gfclk_parents, NULL },
+ { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
+ { 0 },
+};
+
+static const char * const omap5_mcbsp1_gfclk_parents[] __initconst = {
+ "abe_cm:clk:0028:26",
+ "pad_clks_ck",
+ "slimbus_clk",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap5_mcbsp1_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, omap5_mcbsp1_gfclk_parents, NULL },
+ { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
+ { 0 },
+};
+
+static const char * const omap5_mcbsp2_gfclk_parents[] __initconst = {
+ "abe_cm:clk:0030:26",
+ "pad_clks_ck",
+ "slimbus_clk",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap5_mcbsp2_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, omap5_mcbsp2_gfclk_parents, NULL },
+ { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
+ { 0 },
+};
+
+static const char * const omap5_mcbsp3_gfclk_parents[] __initconst = {
+ "abe_cm:clk:0038:26",
+ "pad_clks_ck",
+ "slimbus_clk",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap5_mcbsp3_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, omap5_mcbsp3_gfclk_parents, NULL },
+ { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
+ { 0 },
+};
+
+static const char * const omap5_timer5_gfclk_mux_parents[] __initconst = {
+ "dss_syc_gfclk_div",
+ "sys_32k_ck",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap5_timer5_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap5_timer6_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap5_timer7_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap5_timer8_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap5_abe_clkctrl_regs[] __initconst = {
+ { OMAP5_L4_ABE_CLKCTRL, NULL, 0, "abe_iclk" },
+ { OMAP5_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" },
+ { OMAP5_DMIC_CLKCTRL, omap5_dmic_bit_data, CLKF_SW_SUP, "abe_cm:clk:0018:24" },
+ { OMAP5_MCBSP1_CLKCTRL, omap5_mcbsp1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0028:24" },
+ { OMAP5_MCBSP2_CLKCTRL, omap5_mcbsp2_bit_data, CLKF_SW_SUP, "abe_cm:clk:0030:24" },
+ { OMAP5_MCBSP3_CLKCTRL, omap5_mcbsp3_bit_data, CLKF_SW_SUP, "abe_cm:clk:0038:24" },
+ { OMAP5_TIMER5_CLKCTRL, omap5_timer5_bit_data, CLKF_SW_SUP, "abe_cm:clk:0048:24" },
+ { OMAP5_TIMER6_CLKCTRL, omap5_timer6_bit_data, CLKF_SW_SUP, "abe_cm:clk:0050:24" },
+ { OMAP5_TIMER7_CLKCTRL, omap5_timer7_bit_data, CLKF_SW_SUP, "abe_cm:clk:0058:24" },
+ { OMAP5_TIMER8_CLKCTRL, omap5_timer8_bit_data, CLKF_SW_SUP, "abe_cm:clk:0060:24" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap5_l3main1_clkctrl_regs[] __initconst = {
+ { OMAP5_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap5_l3main2_clkctrl_regs[] __initconst = {
+ { OMAP5_L3_MAIN_2_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap5_ipu_clkctrl_regs[] __initconst = {
+ { OMAP5_MMU_IPU_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h22x2_ck" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap5_dma_clkctrl_regs[] __initconst = {
+ { OMAP5_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap5_emif_clkctrl_regs[] __initconst = {
+ { OMAP5_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { OMAP5_EMIF1_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h11x2_ck" },
+ { OMAP5_EMIF2_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h11x2_ck" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap5_l4cfg_clkctrl_regs[] __initconst = {
+ { OMAP5_L4_CFG_CLKCTRL, NULL, 0, "l4_root_clk_div" },
+ { OMAP5_SPINLOCK_CLKCTRL, NULL, 0, "l4_root_clk_div" },
+ { OMAP5_MAILBOX_CLKCTRL, NULL, 0, "l4_root_clk_div" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap5_l3instr_clkctrl_regs[] __initconst = {
+ { OMAP5_L3_MAIN_3_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
+ { OMAP5_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
+ { 0 },
+};
+
+static const char * const omap5_timer10_gfclk_mux_parents[] __initconst = {
+ "sys_clkin",
+ "sys_32k_ck",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap5_timer10_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap5_timer11_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap5_timer2_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap5_timer3_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap5_timer4_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap5_timer9_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const char * const omap5_gpio2_dbclk_parents[] __initconst = {
+ "sys_32k_ck",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap5_gpio2_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap5_gpio3_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap5_gpio4_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap5_gpio5_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap5_gpio6_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap5_gpio7_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap5_gpio8_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap5_l4per_clkctrl_regs[] __initconst = {
+ { OMAP5_TIMER10_CLKCTRL, omap5_timer10_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0008:24" },
+ { OMAP5_TIMER11_CLKCTRL, omap5_timer11_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0010:24" },
+ { OMAP5_TIMER2_CLKCTRL, omap5_timer2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0018:24" },
+ { OMAP5_TIMER3_CLKCTRL, omap5_timer3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0020:24" },
+ { OMAP5_TIMER4_CLKCTRL, omap5_timer4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0028:24" },
+ { OMAP5_TIMER9_CLKCTRL, omap5_timer9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0030:24" },
+ { OMAP5_GPIO2_CLKCTRL, omap5_gpio2_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
+ { OMAP5_GPIO3_CLKCTRL, omap5_gpio3_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
+ { OMAP5_GPIO4_CLKCTRL, omap5_gpio4_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
+ { OMAP5_GPIO5_CLKCTRL, omap5_gpio5_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
+ { OMAP5_GPIO6_CLKCTRL, omap5_gpio6_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
+ { OMAP5_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
+ { OMAP5_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
+ { OMAP5_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
+ { OMAP5_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
+ { OMAP5_L4_PER_CLKCTRL, NULL, 0, "l4_root_clk_div" },
+ { OMAP5_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+ { OMAP5_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+ { OMAP5_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+ { OMAP5_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+ { OMAP5_GPIO7_CLKCTRL, omap5_gpio7_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
+ { OMAP5_GPIO8_CLKCTRL, omap5_gpio8_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
+ { OMAP5_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+ { OMAP5_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+ { OMAP5_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+ { OMAP5_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+ { OMAP5_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+ { OMAP5_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+ { OMAP5_MMC5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
+ { OMAP5_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
+ { OMAP5_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+ { OMAP5_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+ { 0 },
+};
+
+static const char * const omap5_dss_dss_clk_parents[] __initconst = {
+ "dpll_per_h12x2_ck",
+ NULL,
+};
+
+static const char * const omap5_dss_48mhz_clk_parents[] __initconst = {
+ "func_48m_fclk",
+ NULL,
+};
+
+static const char * const omap5_dss_sys_clk_parents[] __initconst = {
+ "dss_syc_gfclk_div",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap5_dss_core_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, omap5_dss_dss_clk_parents, NULL },
+ { 9, TI_CLK_GATE, omap5_dss_48mhz_clk_parents, NULL },
+ { 10, TI_CLK_GATE, omap5_dss_sys_clk_parents, NULL },
+ { 11, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap5_dss_clkctrl_regs[] __initconst = {
+ { OMAP5_DSS_CORE_CLKCTRL, omap5_dss_core_bit_data, CLKF_SW_SUP, "dss_cm:clk:0000:8" },
+ { 0 },
+};
+
+static const char * const omap5_mmc1_fclk_mux_parents[] __initconst = {
+ "func_128m_clk",
+ "dpll_per_m2x2_ck",
+ NULL,
+};
+
+static const char * const omap5_mmc1_fclk_parents[] __initconst = {
+ "l3init_cm:clk:0008:24",
+ NULL,
+};
+
+static const struct omap_clkctrl_div_data omap5_mmc1_fclk_data __initconst = {
+ .max_div = 2,
+};
+
+static const struct omap_clkctrl_bit_data omap5_mmc1_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
+ { 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL },
+ { 25, TI_CLK_DIVIDER, omap5_mmc1_fclk_parents, &omap5_mmc1_fclk_data },
+ { 0 },
+};
+
+static const char * const omap5_mmc2_fclk_parents[] __initconst = {
+ "l3init_cm:clk:0010:24",
+ NULL,
+};
+
+static const struct omap_clkctrl_div_data omap5_mmc2_fclk_data __initconst = {
+ .max_div = 2,
+};
+
+static const struct omap_clkctrl_bit_data omap5_mmc2_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL },
+ { 25, TI_CLK_DIVIDER, omap5_mmc2_fclk_parents, &omap5_mmc2_fclk_data },
+ { 0 },
+};
+
+static const char * const omap5_usb_host_hs_hsic60m_p3_clk_parents[] __initconst = {
+ "l3init_60m_fclk",
+ NULL,
+};
+
+static const char * const omap5_usb_host_hs_hsic480m_p3_clk_parents[] __initconst = {
+ "dpll_usb_m2_ck",
+ NULL,
+};
+
+static const char * const omap5_usb_host_hs_utmi_p1_clk_parents[] __initconst = {
+ "l3init_cm:clk:0038:24",
+ NULL,
+};
+
+static const char * const omap5_usb_host_hs_utmi_p2_clk_parents[] __initconst = {
+ "l3init_cm:clk:0038:25",
+ NULL,
+};
+
+static const char * const omap5_utmi_p1_gfclk_parents[] __initconst = {
+ "l3init_60m_fclk",
+ "xclk60mhsp1_ck",
+ NULL,
+};
+
+static const char * const omap5_utmi_p2_gfclk_parents[] __initconst = {
+ "l3init_60m_fclk",
+ "xclk60mhsp2_ck",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap5_usb_host_hs_bit_data[] __initconst = {
+ { 6, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
+ { 7, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
+ { 8, TI_CLK_GATE, omap5_usb_host_hs_utmi_p1_clk_parents, NULL },
+ { 9, TI_CLK_GATE, omap5_usb_host_hs_utmi_p2_clk_parents, NULL },
+ { 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
+ { 11, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
+ { 12, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
+ { 13, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
+ { 14, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
+ { 24, TI_CLK_MUX, omap5_utmi_p1_gfclk_parents, NULL },
+ { 25, TI_CLK_MUX, omap5_utmi_p2_gfclk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap5_usb_tll_hs_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
+ { 9, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
+ { 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
+ { 0 },
+};
+
+static const char * const omap5_sata_ref_clk_parents[] __initconst = {
+ "sys_clkin",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap5_sata_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, omap5_sata_ref_clk_parents, NULL },
+ { 0 },
+};
+
+static const char * const omap5_usb_otg_ss_refclk960m_parents[] __initconst = {
+ "dpll_usb_clkdcoldo",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap5_usb_otg_ss_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, omap5_usb_otg_ss_refclk960m_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap5_l3init_clkctrl_regs[] __initconst = {
+ { OMAP5_MMC1_CLKCTRL, omap5_mmc1_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0008:25" },
+ { OMAP5_MMC2_CLKCTRL, omap5_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" },
+ { OMAP5_USB_HOST_HS_CLKCTRL, omap5_usb_host_hs_bit_data, CLKF_SW_SUP, "l3init_60m_fclk" },
+ { OMAP5_USB_TLL_HS_CLKCTRL, omap5_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
+ { OMAP5_SATA_CLKCTRL, omap5_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
+ { OMAP5_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
+ { OMAP5_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
+ { OMAP5_USB_OTG_SS_CLKCTRL, omap5_usb_otg_ss_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap5_gpio1_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap5_timer1_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap5_wkupaon_clkctrl_regs[] __initconst = {
+ { OMAP5_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
+ { OMAP5_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
+ { OMAP5_GPIO1_CLKCTRL, omap5_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
+ { OMAP5_TIMER1_CLKCTRL, omap5_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" },
+ { OMAP5_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
+ { OMAP5_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
+ { 0 },
+};
+
+const struct omap_clkctrl_data omap5_clkctrl_data[] __initconst = {
+ { 0x4a004320, omap5_mpu_clkctrl_regs },
+ { 0x4a004420, omap5_dsp_clkctrl_regs },
+ { 0x4a004520, omap5_abe_clkctrl_regs },
+ { 0x4a008720, omap5_l3main1_clkctrl_regs },
+ { 0x4a008820, omap5_l3main2_clkctrl_regs },
+ { 0x4a008920, omap5_ipu_clkctrl_regs },
+ { 0x4a008a20, omap5_dma_clkctrl_regs },
+ { 0x4a008b20, omap5_emif_clkctrl_regs },
+ { 0x4a008d20, omap5_l4cfg_clkctrl_regs },
+ { 0x4a008e20, omap5_l3instr_clkctrl_regs },
+ { 0x4a009020, omap5_l4per_clkctrl_regs },
+ { 0x4a009420, omap5_dss_clkctrl_regs },
+ { 0x4a009620, omap5_l3init_clkctrl_regs },
+ { 0x4ae07920, omap5_wkupaon_clkctrl_regs },
+ { 0 },
+};
+
static struct ti_dt_clk omap54xx_clks[] = {
- DT_CLK(NULL, "pad_clks_src_ck", "pad_clks_src_ck"),
- DT_CLK(NULL, "pad_clks_ck", "pad_clks_ck"),
- DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"),
- DT_CLK(NULL, "slimbus_src_clk", "slimbus_src_clk"),
- DT_CLK(NULL, "slimbus_clk", "slimbus_clk"),
- DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"),
- DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"),
- DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"),
- DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"),
- DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
- DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
- DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"),
- DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"),
- DT_CLK(NULL, "sys_clkin", "sys_clkin"),
- DT_CLK(NULL, "xclk60mhsp1_ck", "xclk60mhsp1_ck"),
- DT_CLK(NULL, "xclk60mhsp2_ck", "xclk60mhsp2_ck"),
- DT_CLK(NULL, "abe_dpll_bypass_clk_mux", "abe_dpll_bypass_clk_mux"),
- DT_CLK(NULL, "abe_dpll_clk_mux", "abe_dpll_clk_mux"),
- DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"),
- DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"),
- DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"),
- DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"),
- DT_CLK(NULL, "abe_clk", "abe_clk"),
- DT_CLK(NULL, "abe_iclk", "abe_iclk"),
- DT_CLK(NULL, "abe_lp_clk_div", "abe_lp_clk_div"),
- DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"),
- DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
- DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
- DT_CLK(NULL, "dpll_core_h21x2_ck", "dpll_core_h21x2_ck"),
- DT_CLK(NULL, "c2c_fclk", "c2c_fclk"),
- DT_CLK(NULL, "c2c_iclk", "c2c_iclk"),
- DT_CLK(NULL, "custefuse_sys_gfclk_div", "custefuse_sys_gfclk_div"),
- DT_CLK(NULL, "dpll_core_h11x2_ck", "dpll_core_h11x2_ck"),
- DT_CLK(NULL, "dpll_core_h12x2_ck", "dpll_core_h12x2_ck"),
- DT_CLK(NULL, "dpll_core_h13x2_ck", "dpll_core_h13x2_ck"),
- DT_CLK(NULL, "dpll_core_h14x2_ck", "dpll_core_h14x2_ck"),
- DT_CLK(NULL, "dpll_core_h22x2_ck", "dpll_core_h22x2_ck"),
- DT_CLK(NULL, "dpll_core_h23x2_ck", "dpll_core_h23x2_ck"),
- DT_CLK(NULL, "dpll_core_h24x2_ck", "dpll_core_h24x2_ck"),
- DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"),
- DT_CLK(NULL, "dpll_core_m3x2_ck", "dpll_core_m3x2_ck"),
- DT_CLK(NULL, "iva_dpll_hs_clk_div", "iva_dpll_hs_clk_div"),
- DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"),
- DT_CLK(NULL, "dpll_iva_x2_ck", "dpll_iva_x2_ck"),
- DT_CLK(NULL, "dpll_iva_h11x2_ck", "dpll_iva_h11x2_ck"),
- DT_CLK(NULL, "dpll_iva_h12x2_ck", "dpll_iva_h12x2_ck"),
- DT_CLK(NULL, "mpu_dpll_hs_clk_div", "mpu_dpll_hs_clk_div"),
- DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
- DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
- DT_CLK(NULL, "per_dpll_hs_clk_div", "per_dpll_hs_clk_div"),
- DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
- DT_CLK(NULL, "dpll_per_x2_ck", "dpll_per_x2_ck"),
- DT_CLK(NULL, "dpll_per_h11x2_ck", "dpll_per_h11x2_ck"),
- DT_CLK(NULL, "dpll_per_h12x2_ck", "dpll_per_h12x2_ck"),
- DT_CLK(NULL, "dpll_per_h14x2_ck", "dpll_per_h14x2_ck"),
- DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
- DT_CLK(NULL, "dpll_per_m2x2_ck", "dpll_per_m2x2_ck"),
- DT_CLK(NULL, "dpll_per_m3x2_ck", "dpll_per_m3x2_ck"),
- DT_CLK(NULL, "dpll_unipro1_ck", "dpll_unipro1_ck"),
- DT_CLK(NULL, "dpll_unipro1_clkdcoldo", "dpll_unipro1_clkdcoldo"),
- DT_CLK(NULL, "dpll_unipro1_m2_ck", "dpll_unipro1_m2_ck"),
- DT_CLK(NULL, "dpll_unipro2_ck", "dpll_unipro2_ck"),
- DT_CLK(NULL, "dpll_unipro2_clkdcoldo", "dpll_unipro2_clkdcoldo"),
- DT_CLK(NULL, "dpll_unipro2_m2_ck", "dpll_unipro2_m2_ck"),
- DT_CLK(NULL, "usb_dpll_hs_clk_div", "usb_dpll_hs_clk_div"),
- DT_CLK(NULL, "dpll_usb_ck", "dpll_usb_ck"),
- DT_CLK(NULL, "dpll_usb_clkdcoldo", "dpll_usb_clkdcoldo"),
- DT_CLK(NULL, "dpll_usb_m2_ck", "dpll_usb_m2_ck"),
- DT_CLK(NULL, "dss_syc_gfclk_div", "dss_syc_gfclk_div"),
- DT_CLK(NULL, "func_128m_clk", "func_128m_clk"),
- DT_CLK(NULL, "func_12m_fclk", "func_12m_fclk"),
- DT_CLK(NULL, "func_24m_clk", "func_24m_clk"),
- DT_CLK(NULL, "func_48m_fclk", "func_48m_fclk"),
- DT_CLK(NULL, "func_96m_fclk", "func_96m_fclk"),
- DT_CLK(NULL, "l3_iclk_div", "l3_iclk_div"),
- DT_CLK(NULL, "gpu_l3_iclk", "gpu_l3_iclk"),
- DT_CLK(NULL, "l3init_60m_fclk", "l3init_60m_fclk"),
- DT_CLK(NULL, "wkupaon_iclk_mux", "wkupaon_iclk_mux"),
- DT_CLK(NULL, "l3instr_ts_gclk_div", "l3instr_ts_gclk_div"),
- DT_CLK(NULL, "l4_root_clk_div", "l4_root_clk_div"),
- DT_CLK(NULL, "dss_32khz_clk", "dss_32khz_clk"),
- DT_CLK(NULL, "dss_48mhz_clk", "dss_48mhz_clk"),
- DT_CLK(NULL, "dss_dss_clk", "dss_dss_clk"),
- DT_CLK(NULL, "dss_sys_clk", "dss_sys_clk"),
- DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
- DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
- DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
- DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"),
- DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"),
- DT_CLK(NULL, "gpio6_dbclk", "gpio6_dbclk"),
- DT_CLK(NULL, "gpio7_dbclk", "gpio7_dbclk"),
- DT_CLK(NULL, "gpio8_dbclk", "gpio8_dbclk"),
- DT_CLK(NULL, "iss_ctrlclk", "iss_ctrlclk"),
- DT_CLK(NULL, "lli_txphy_clk", "lli_txphy_clk"),
- DT_CLK(NULL, "lli_txphy_ls_clk", "lli_txphy_ls_clk"),
- DT_CLK(NULL, "mmc1_32khz_clk", "mmc1_32khz_clk"),
- DT_CLK(NULL, "sata_ref_clk", "sata_ref_clk"),
- DT_CLK(NULL, "slimbus1_slimbus_clk", "slimbus1_slimbus_clk"),
- DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "usb_host_hs_hsic480m_p1_clk"),
- DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "usb_host_hs_hsic480m_p2_clk"),
- DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "usb_host_hs_hsic480m_p3_clk"),
- DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "usb_host_hs_hsic60m_p1_clk"),
- DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "usb_host_hs_hsic60m_p2_clk"),
- DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "usb_host_hs_hsic60m_p3_clk"),
- DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "usb_host_hs_utmi_p1_clk"),
- DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "usb_host_hs_utmi_p2_clk"),
- DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "usb_host_hs_utmi_p3_clk"),
- DT_CLK(NULL, "usb_otg_ss_refclk960m", "usb_otg_ss_refclk960m"),
- DT_CLK(NULL, "usb_phy_cm_clk32k", "usb_phy_cm_clk32k"),
- DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "usb_tll_hs_usb_ch0_clk"),
- DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "usb_tll_hs_usb_ch1_clk"),
- DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "usb_tll_hs_usb_ch2_clk"),
- DT_CLK(NULL, "aess_fclk", "aess_fclk"),
- DT_CLK(NULL, "dmic_sync_mux_ck", "dmic_sync_mux_ck"),
- DT_CLK(NULL, "dmic_gfclk", "dmic_gfclk"),
- DT_CLK(NULL, "fdif_fclk", "fdif_fclk"),
- DT_CLK(NULL, "gpu_core_gclk_mux", "gpu_core_gclk_mux"),
- DT_CLK(NULL, "gpu_hyd_gclk_mux", "gpu_hyd_gclk_mux"),
- DT_CLK(NULL, "hsi_fclk", "hsi_fclk"),
- DT_CLK(NULL, "mcasp_sync_mux_ck", "mcasp_sync_mux_ck"),
- DT_CLK(NULL, "mcasp_gfclk", "mcasp_gfclk"),
- DT_CLK(NULL, "mcbsp1_sync_mux_ck", "mcbsp1_sync_mux_ck"),
- DT_CLK(NULL, "mcbsp1_gfclk", "mcbsp1_gfclk"),
- DT_CLK(NULL, "mcbsp2_sync_mux_ck", "mcbsp2_sync_mux_ck"),
- DT_CLK(NULL, "mcbsp2_gfclk", "mcbsp2_gfclk"),
- DT_CLK(NULL, "mcbsp3_sync_mux_ck", "mcbsp3_sync_mux_ck"),
- DT_CLK(NULL, "mcbsp3_gfclk", "mcbsp3_gfclk"),
- DT_CLK(NULL, "mmc1_fclk_mux", "mmc1_fclk_mux"),
- DT_CLK(NULL, "mmc1_fclk", "mmc1_fclk"),
- DT_CLK(NULL, "mmc2_fclk_mux", "mmc2_fclk_mux"),
- DT_CLK(NULL, "mmc2_fclk", "mmc2_fclk"),
- DT_CLK(NULL, "timer10_gfclk_mux", "timer10_gfclk_mux"),
- DT_CLK(NULL, "timer11_gfclk_mux", "timer11_gfclk_mux"),
- DT_CLK(NULL, "timer1_gfclk_mux", "timer1_gfclk_mux"),
- DT_CLK(NULL, "timer2_gfclk_mux", "timer2_gfclk_mux"),
- DT_CLK(NULL, "timer3_gfclk_mux", "timer3_gfclk_mux"),
- DT_CLK(NULL, "timer4_gfclk_mux", "timer4_gfclk_mux"),
- DT_CLK(NULL, "timer5_gfclk_mux", "timer5_gfclk_mux"),
- DT_CLK(NULL, "timer6_gfclk_mux", "timer6_gfclk_mux"),
- DT_CLK(NULL, "timer7_gfclk_mux", "timer7_gfclk_mux"),
- DT_CLK(NULL, "timer8_gfclk_mux", "timer8_gfclk_mux"),
- DT_CLK(NULL, "timer9_gfclk_mux", "timer9_gfclk_mux"),
- DT_CLK(NULL, "utmi_p1_gfclk", "utmi_p1_gfclk"),
- DT_CLK(NULL, "utmi_p2_gfclk", "utmi_p2_gfclk"),
- DT_CLK(NULL, "auxclk0_src_ck", "auxclk0_src_ck"),
- DT_CLK(NULL, "auxclk0_ck", "auxclk0_ck"),
- DT_CLK(NULL, "auxclkreq0_ck", "auxclkreq0_ck"),
- DT_CLK(NULL, "auxclk1_src_ck", "auxclk1_src_ck"),
- DT_CLK(NULL, "auxclk1_ck", "auxclk1_ck"),
- DT_CLK(NULL, "auxclkreq1_ck", "auxclkreq1_ck"),
- DT_CLK(NULL, "auxclk2_src_ck", "auxclk2_src_ck"),
- DT_CLK(NULL, "auxclk2_ck", "auxclk2_ck"),
- DT_CLK(NULL, "auxclkreq2_ck", "auxclkreq2_ck"),
- DT_CLK(NULL, "auxclk3_src_ck", "auxclk3_src_ck"),
- DT_CLK(NULL, "auxclk3_ck", "auxclk3_ck"),
- DT_CLK(NULL, "auxclkreq3_ck", "auxclkreq3_ck"),
- DT_CLK("omap_i2c.1", "ick", "dummy_ck"),
- DT_CLK("omap_i2c.2", "ick", "dummy_ck"),
- DT_CLK("omap_i2c.3", "ick", "dummy_ck"),
- DT_CLK("omap_i2c.4", "ick", "dummy_ck"),
- DT_CLK(NULL, "mailboxes_ick", "dummy_ck"),
- DT_CLK("omap_hsmmc.0", "ick", "dummy_ck"),
- DT_CLK("omap_hsmmc.1", "ick", "dummy_ck"),
- DT_CLK("omap_hsmmc.2", "ick", "dummy_ck"),
- DT_CLK("omap_hsmmc.3", "ick", "dummy_ck"),
- DT_CLK("omap_hsmmc.4", "ick", "dummy_ck"),
- DT_CLK("omap-mcbsp.1", "ick", "dummy_ck"),
- DT_CLK("omap-mcbsp.2", "ick", "dummy_ck"),
- DT_CLK("omap-mcbsp.3", "ick", "dummy_ck"),
- DT_CLK("omap-mcbsp.4", "ick", "dummy_ck"),
- DT_CLK("omap2_mcspi.1", "ick", "dummy_ck"),
- DT_CLK("omap2_mcspi.2", "ick", "dummy_ck"),
- DT_CLK("omap2_mcspi.3", "ick", "dummy_ck"),
- DT_CLK("omap2_mcspi.4", "ick", "dummy_ck"),
- DT_CLK(NULL, "uart1_ick", "dummy_ck"),
- DT_CLK(NULL, "uart2_ick", "dummy_ck"),
- DT_CLK(NULL, "uart3_ick", "dummy_ck"),
- DT_CLK(NULL, "uart4_ick", "dummy_ck"),
- DT_CLK("usbhs_omap", "usbhost_ick", "dummy_ck"),
- DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"),
- DT_CLK("omap_wdt", "ick", "dummy_ck"),
DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
DT_CLK(NULL, "sys_clkin_ck", "sys_clkin"),
- DT_CLK("4ae18000.timer", "timer_sys_ck", "sys_clkin"),
- DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin"),
- DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin"),
- DT_CLK("48036000.timer", "timer_sys_ck", "sys_clkin"),
- DT_CLK("4803e000.timer", "timer_sys_ck", "sys_clkin"),
- DT_CLK("48086000.timer", "timer_sys_ck", "sys_clkin"),
- DT_CLK("48088000.timer", "timer_sys_ck", "sys_clkin"),
- DT_CLK("40138000.timer", "timer_sys_ck", "dss_syc_gfclk_div"),
- DT_CLK("4013a000.timer", "timer_sys_ck", "dss_syc_gfclk_div"),
- DT_CLK("4013c000.timer", "timer_sys_ck", "dss_syc_gfclk_div"),
- DT_CLK("4013e000.timer", "timer_sys_ck", "dss_syc_gfclk_div"),
+ DT_CLK(NULL, "dmic_gfclk", "abe_cm:0018:24"),
+ DT_CLK(NULL, "dmic_sync_mux_ck", "abe_cm:0018:26"),
+ DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"),
+ DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"),
+ DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"),
+ DT_CLK(NULL, "dss_sys_clk", "dss_cm:0000:10"),
+ DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"),
+ DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0040:8"),
+ DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0048:8"),
+ DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0050:8"),
+ DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0058:8"),
+ DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0060:8"),
+ DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:00f0:8"),
+ DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:00f8:8"),
+ DT_CLK(NULL, "mcbsp1_gfclk", "abe_cm:0028:24"),
+ DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe_cm:0028:26"),
+ DT_CLK(NULL, "mcbsp2_gfclk", "abe_cm:0030:24"),
+ DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe_cm:0030:26"),
+ DT_CLK(NULL, "mcbsp3_gfclk", "abe_cm:0038:24"),
+ DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe_cm:0038:26"),
+ DT_CLK(NULL, "mmc1_32khz_clk", "l3init_cm:0008:8"),
+ DT_CLK(NULL, "mmc1_fclk", "l3init_cm:0008:25"),
+ DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"),
+ DT_CLK(NULL, "mmc2_fclk", "l3init_cm:0010:25"),
+ DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"),
+ DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"),
+ DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0008:24"),
+ DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0010:24"),
+ DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"),
+ DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0018:24"),
+ DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0020:24"),
+ DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0028:24"),
+ DT_CLK(NULL, "timer5_gfclk_mux", "abe_cm:0048:24"),
+ DT_CLK(NULL, "timer6_gfclk_mux", "abe_cm:0050:24"),
+ DT_CLK(NULL, "timer7_gfclk_mux", "abe_cm:0058:24"),
+ DT_CLK(NULL, "timer8_gfclk_mux", "abe_cm:0060:24"),
+ DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0030:24"),
+ DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3init_cm:0038:13"),
+ DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3init_cm:0038:14"),
+ DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "l3init_cm:0038:7"),
+ DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3init_cm:0038:11"),
+ DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3init_cm:0038:12"),
+ DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "l3init_cm:0038:6"),
+ DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3init_cm:0038:8"),
+ DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3init_cm:0038:9"),
+ DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3init_cm:0038:10"),
+ DT_CLK(NULL, "usb_otg_ss_refclk960m", "l3init_cm:00d0:8"),
+ DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3init_cm:0048:8"),
+ DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3init_cm:0048:9"),
+ DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3init_cm:0048:10"),
+ DT_CLK(NULL, "utmi_p1_gfclk", "l3init_cm:0038:24"),
+ DT_CLK(NULL, "utmi_p2_gfclk", "l3init_cm:0038:25"),
{ .node_name = NULL },
};
@@ -234,6 +545,8 @@ int __init omap5xxx_dt_clk_init(void)
omap2_clk_disable_autoidle_all();
+ ti_clk_add_aliases();
+
abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_clk_mux");
sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
index 9fd6043314eb..fb249a1637a5 100644
--- a/drivers/clk/ti/clk-7xx.c
+++ b/drivers/clk/ti/clk-7xx.c
@@ -15,297 +15,809 @@
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk/ti.h>
+#include <dt-bindings/clock/dra7.h>
#include "clock.h"
#define DRA7_DPLL_GMAC_DEFFREQ 1000000000
#define DRA7_DPLL_USB_DEFFREQ 960000000
+static const struct omap_clkctrl_reg_data dra7_mpu_clkctrl_regs[] __initconst = {
+ { DRA7_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
+ { 0 },
+};
+
+static const char * const dra7_mcasp1_aux_gfclk_mux_parents[] __initconst = {
+ "per_abe_x1_gfclk2_div",
+ "video1_clk2_div",
+ "video2_clk2_div",
+ "hdmi_clk2_div",
+ NULL,
+};
+
+static const char * const dra7_mcasp1_ahclkx_mux_parents[] __initconst = {
+ "abe_24m_fclk",
+ "abe_sys_clk_div",
+ "func_24m_clk",
+ "atl_clkin3_ck",
+ "atl_clkin2_ck",
+ "atl_clkin1_ck",
+ "atl_clkin0_ck",
+ "sys_clkin2",
+ "ref_clkin0_ck",
+ "ref_clkin1_ck",
+ "ref_clkin2_ck",
+ "ref_clkin3_ck",
+ "mlb_clk",
+ "mlbp_clk",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data dra7_mcasp1_bit_data[] __initconst = {
+ { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
+ { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
+ { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
+ { 0 },
+};
+
+static const char * const dra7_timer5_gfclk_mux_parents[] __initconst = {
+ "timer_sys_clk_div",
+ "sys_32k_ck",
+ "sys_clkin2",
+ "ref_clkin0_ck",
+ "ref_clkin1_ck",
+ "ref_clkin2_ck",
+ "ref_clkin3_ck",
+ "abe_giclk_div",
+ "video1_div_clk",
+ "video2_div_clk",
+ "hdmi_div_clk",
+ "clkoutmux0_clk_mux",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data dra7_timer5_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_timer6_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_timer7_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_timer8_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const char * const dra7_uart6_gfclk_mux_parents[] __initconst = {
+ "func_48m_fclk",
+ "dpll_per_m2x2_ck",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data dra7_uart6_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data dra7_ipu_clkctrl_regs[] __initconst = {
+ { DRA7_MCASP1_CLKCTRL, dra7_mcasp1_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0010:22" },
+ { DRA7_TIMER5_CLKCTRL, dra7_timer5_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0018:24" },
+ { DRA7_TIMER6_CLKCTRL, dra7_timer6_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0020:24" },
+ { DRA7_TIMER7_CLKCTRL, dra7_timer7_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0028:24" },
+ { DRA7_TIMER8_CLKCTRL, dra7_timer8_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0030:24" },
+ { DRA7_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
+ { DRA7_UART6_CLKCTRL, dra7_uart6_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0040:24" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data dra7_rtc_clkctrl_regs[] __initconst = {
+ { DRA7_RTCSS_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data dra7_coreaon_clkctrl_regs[] __initconst = {
+ { DRA7_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
+ { DRA7_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data dra7_l3main1_clkctrl_regs[] __initconst = {
+ { DRA7_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { DRA7_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
+ { DRA7_TPCC_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { DRA7_TPTC0_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
+ { DRA7_TPTC1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
+ { DRA7_VCP1_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { DRA7_VCP2_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data dra7_dma_clkctrl_regs[] __initconst = {
+ { DRA7_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data dra7_emif_clkctrl_regs[] __initconst = {
+ { DRA7_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { 0 },
+};
+
+static const char * const dra7_atl_dpll_clk_mux_parents[] __initconst = {
+ "sys_32k_ck",
+ "video1_clkin_ck",
+ "video2_clkin_ck",
+ "hdmi_clkin_ck",
+ NULL,
+};
+
+static const char * const dra7_atl_gfclk_mux_parents[] __initconst = {
+ "l3_iclk_div",
+ "dpll_abe_m2_ck",
+ "atl_cm:clk:0000:24",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data dra7_atl_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_atl_dpll_clk_mux_parents, NULL },
+ { 26, TI_CLK_MUX, dra7_atl_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data dra7_atl_clkctrl_regs[] __initconst = {
+ { DRA7_ATL_CLKCTRL, dra7_atl_bit_data, CLKF_SW_SUP, "atl_cm:clk:0000:26" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data dra7_l4cfg_clkctrl_regs[] __initconst = {
+ { DRA7_L4_CFG_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { DRA7_SPINLOCK_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { DRA7_MAILBOX1_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { DRA7_MAILBOX2_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { DRA7_MAILBOX3_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { DRA7_MAILBOX4_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { DRA7_MAILBOX5_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { DRA7_MAILBOX6_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { DRA7_MAILBOX7_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { DRA7_MAILBOX8_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { DRA7_MAILBOX9_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { DRA7_MAILBOX10_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { DRA7_MAILBOX11_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { DRA7_MAILBOX12_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { DRA7_MAILBOX13_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data dra7_l3instr_clkctrl_regs[] __initconst = {
+ { DRA7_L3_MAIN_2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
+ { DRA7_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
+ { 0 },
+};
+
+static const char * const dra7_dss_dss_clk_parents[] __initconst = {
+ "dpll_per_h12x2_ck",
+ NULL,
+};
+
+static const char * const dra7_dss_48mhz_clk_parents[] __initconst = {
+ "func_48m_fclk",
+ NULL,
+};
+
+static const char * const dra7_dss_hdmi_clk_parents[] __initconst = {
+ "hdmi_dpll_clk_mux",
+ NULL,
+};
+
+static const char * const dra7_dss_32khz_clk_parents[] __initconst = {
+ "sys_32k_ck",
+ NULL,
+};
+
+static const char * const dra7_dss_video1_clk_parents[] __initconst = {
+ "video1_dpll_clk_mux",
+ NULL,
+};
+
+static const char * const dra7_dss_video2_clk_parents[] __initconst = {
+ "video2_dpll_clk_mux",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data dra7_dss_core_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, dra7_dss_dss_clk_parents, NULL },
+ { 9, TI_CLK_GATE, dra7_dss_48mhz_clk_parents, NULL },
+ { 10, TI_CLK_GATE, dra7_dss_hdmi_clk_parents, NULL },
+ { 11, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
+ { 12, TI_CLK_GATE, dra7_dss_video1_clk_parents, NULL },
+ { 13, TI_CLK_GATE, dra7_dss_video2_clk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data dra7_dss_clkctrl_regs[] __initconst = {
+ { DRA7_DSS_CORE_CLKCTRL, dra7_dss_core_bit_data, CLKF_SW_SUP, "dss_cm:clk:0000:8" },
+ { DRA7_BB2D_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_h24x2_ck" },
+ { 0 },
+};
+
+static const char * const dra7_mmc1_fclk_mux_parents[] __initconst = {
+ "func_128m_clk",
+ "dpll_per_m2x2_ck",
+ NULL,
+};
+
+static const char * const dra7_mmc1_fclk_div_parents[] __initconst = {
+ "l3init_cm:clk:0008:24",
+ NULL,
+};
+
+static const struct omap_clkctrl_div_data dra7_mmc1_fclk_div_data __initconst = {
+ .max_div = 4,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
+};
+
+static const struct omap_clkctrl_bit_data dra7_mmc1_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
+ { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
+ { 25, TI_CLK_DIVIDER, dra7_mmc1_fclk_div_parents, &dra7_mmc1_fclk_div_data },
+ { 0 },
+};
+
+static const char * const dra7_mmc2_fclk_div_parents[] __initconst = {
+ "l3init_cm:clk:0010:24",
+ NULL,
+};
+
+static const struct omap_clkctrl_div_data dra7_mmc2_fclk_div_data __initconst = {
+ .max_div = 4,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
+};
+
+static const struct omap_clkctrl_bit_data dra7_mmc2_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
+ { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
+ { 25, TI_CLK_DIVIDER, dra7_mmc2_fclk_div_parents, &dra7_mmc2_fclk_div_data },
+ { 0 },
+};
+
+static const char * const dra7_usb_otg_ss2_refclk960m_parents[] __initconst = {
+ "l3init_960m_gfclk",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data dra7_usb_otg_ss2_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
+ { 0 },
+};
+
+static const char * const dra7_sata_ref_clk_parents[] __initconst = {
+ "sys_clkin1",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data dra7_sata_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, dra7_sata_ref_clk_parents, NULL },
+ { 0 },
+};
+
+static const char * const dra7_optfclk_pciephy1_clk_parents[] __initconst = {
+ "apll_pcie_ck",
+ NULL,
+};
+
+static const char * const dra7_optfclk_pciephy1_div_clk_parents[] __initconst = {
+ "optfclk_pciephy_div",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data dra7_pcie1_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
+ { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
+ { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_pcie2_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
+ { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
+ { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
+ { 0 },
+};
+
+static const char * const dra7_rmii_50mhz_clk_mux_parents[] __initconst = {
+ "dpll_gmac_h11x2_ck",
+ "rmii_clk_ck",
+ NULL,
+};
+
+static const char * const dra7_gmac_rft_clk_mux_parents[] __initconst = {
+ "video1_clkin_ck",
+ "video2_clkin_ck",
+ "dpll_abe_m2_ck",
+ "hdmi_clkin_ck",
+ "l3_iclk_div",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data dra7_gmac_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_rmii_50mhz_clk_mux_parents, NULL },
+ { 25, TI_CLK_MUX, dra7_gmac_rft_clk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_usb_otg_ss1_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data dra7_l3init_clkctrl_regs[] __initconst = {
+ { DRA7_MMC1_CLKCTRL, dra7_mmc1_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0008:25" },
+ { DRA7_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" },
+ { DRA7_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
+ { DRA7_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
+ { DRA7_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
+ { DRA7_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
+ { DRA7_PCIE1_CLKCTRL, dra7_pcie1_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" },
+ { DRA7_PCIE2_CLKCTRL, dra7_pcie2_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" },
+ { DRA7_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "dpll_gmac_ck", "gmac_clkdm" },
+ { DRA7_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
+ { DRA7_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
+ { DRA7_USB_OTG_SS1_CLKCTRL, dra7_usb_otg_ss1_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
+ { 0 },
+};
+
+static const char * const dra7_timer10_gfclk_mux_parents[] __initconst = {
+ "timer_sys_clk_div",
+ "sys_32k_ck",
+ "sys_clkin2",
+ "ref_clkin0_ck",
+ "ref_clkin1_ck",
+ "ref_clkin2_ck",
+ "ref_clkin3_ck",
+ "abe_giclk_div",
+ "video1_div_clk",
+ "video2_div_clk",
+ "hdmi_div_clk",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data dra7_timer10_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_timer11_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_timer2_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_timer3_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_timer4_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_timer9_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_gpio2_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_gpio3_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_gpio4_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_gpio5_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_gpio6_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_timer13_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_timer14_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_timer15_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_gpio7_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_gpio8_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
+ { 0 },
+};
+
+static const char * const dra7_mmc3_gfclk_div_parents[] __initconst = {
+ "l4per_cm:clk:0120:24",
+ NULL,
+};
+
+static const struct omap_clkctrl_div_data dra7_mmc3_gfclk_div_data __initconst = {
+ .max_div = 4,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
+};
+
+static const struct omap_clkctrl_bit_data dra7_mmc3_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
+ { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
+ { 25, TI_CLK_DIVIDER, dra7_mmc3_gfclk_div_parents, &dra7_mmc3_gfclk_div_data },
+ { 0 },
+};
+
+static const char * const dra7_mmc4_gfclk_div_parents[] __initconst = {
+ "l4per_cm:clk:0128:24",
+ NULL,
+};
+
+static const struct omap_clkctrl_div_data dra7_mmc4_gfclk_div_data __initconst = {
+ .max_div = 4,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
+};
+
+static const struct omap_clkctrl_bit_data dra7_mmc4_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
+ { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
+ { 25, TI_CLK_DIVIDER, dra7_mmc4_gfclk_div_parents, &dra7_mmc4_gfclk_div_data },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_timer16_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const char * const dra7_qspi_gfclk_mux_parents[] __initconst = {
+ "func_128m_clk",
+ "dpll_per_h13x2_ck",
+ NULL,
+};
+
+static const char * const dra7_qspi_gfclk_div_parents[] __initconst = {
+ "l4per_cm:clk:0138:24",
+ NULL,
+};
+
+static const struct omap_clkctrl_div_data dra7_qspi_gfclk_div_data __initconst = {
+ .max_div = 4,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
+};
+
+static const struct omap_clkctrl_bit_data dra7_qspi_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_qspi_gfclk_mux_parents, NULL },
+ { 25, TI_CLK_DIVIDER, dra7_qspi_gfclk_div_parents, &dra7_qspi_gfclk_div_data },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_uart1_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_uart2_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_uart3_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_uart4_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_mcasp2_bit_data[] __initconst = {
+ { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
+ { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
+ { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_mcasp3_bit_data[] __initconst = {
+ { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
+ { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_uart5_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_mcasp5_bit_data[] __initconst = {
+ { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
+ { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_mcasp8_bit_data[] __initconst = {
+ { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
+ { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_mcasp4_bit_data[] __initconst = {
+ { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
+ { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_uart7_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_uart8_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_uart9_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_mcasp6_bit_data[] __initconst = {
+ { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
+ { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_mcasp7_bit_data[] __initconst = {
+ { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
+ { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data dra7_l4per_clkctrl_regs[] __initconst = {
+ { DRA7_L4_PER2_CLKCTRL, NULL, 0, "l3_iclk_div", "l4per2_clkdm" },
+ { DRA7_L4_PER3_CLKCTRL, NULL, 0, "l3_iclk_div", "l4per3_clkdm" },
+ { DRA7_TIMER10_CLKCTRL, dra7_timer10_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0028:24" },
+ { DRA7_TIMER11_CLKCTRL, dra7_timer11_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0030:24" },
+ { DRA7_TIMER2_CLKCTRL, dra7_timer2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0038:24" },
+ { DRA7_TIMER3_CLKCTRL, dra7_timer3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0040:24" },
+ { DRA7_TIMER4_CLKCTRL, dra7_timer4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0048:24" },
+ { DRA7_TIMER9_CLKCTRL, dra7_timer9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0050:24" },
+ { DRA7_ELM_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { DRA7_GPIO2_CLKCTRL, dra7_gpio2_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
+ { DRA7_GPIO3_CLKCTRL, dra7_gpio3_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
+ { DRA7_GPIO4_CLKCTRL, dra7_gpio4_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
+ { DRA7_GPIO5_CLKCTRL, dra7_gpio5_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
+ { DRA7_GPIO6_CLKCTRL, dra7_gpio6_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
+ { DRA7_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" },
+ { DRA7_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
+ { DRA7_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
+ { DRA7_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
+ { DRA7_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
+ { DRA7_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
+ { DRA7_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
+ { DRA7_L4_PER1_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { DRA7_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
+ { DRA7_TIMER13_CLKCTRL, dra7_timer13_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00c8:24", "l4per3_clkdm" },
+ { DRA7_TIMER14_CLKCTRL, dra7_timer14_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00d0:24", "l4per3_clkdm" },
+ { DRA7_TIMER15_CLKCTRL, dra7_timer15_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00d8:24", "l4per3_clkdm" },
+ { DRA7_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+ { DRA7_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+ { DRA7_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+ { DRA7_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+ { DRA7_GPIO7_CLKCTRL, dra7_gpio7_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
+ { DRA7_GPIO8_CLKCTRL, dra7_gpio8_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
+ { DRA7_MMC3_CLKCTRL, dra7_mmc3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0120:25" },
+ { DRA7_MMC4_CLKCTRL, dra7_mmc4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0128:25" },
+ { DRA7_TIMER16_CLKCTRL, dra7_timer16_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0130:24", "l4per3_clkdm" },
+ { DRA7_QSPI_CLKCTRL, dra7_qspi_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0138:25", "l4per2_clkdm" },
+ { DRA7_UART1_CLKCTRL, dra7_uart1_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0140:24" },
+ { DRA7_UART2_CLKCTRL, dra7_uart2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0148:24" },
+ { DRA7_UART3_CLKCTRL, dra7_uart3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0150:24" },
+ { DRA7_UART4_CLKCTRL, dra7_uart4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0158:24" },
+ { DRA7_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0160:22", "l4per2_clkdm" },
+ { DRA7_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0168:22", "l4per2_clkdm" },
+ { DRA7_UART5_CLKCTRL, dra7_uart5_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0170:24" },
+ { DRA7_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0178:22", "l4per2_clkdm" },
+ { DRA7_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0190:24", "l4per2_clkdm" },
+ { DRA7_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0198:22", "l4per2_clkdm" },
+ { DRA7_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
+ { DRA7_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
+ { DRA7_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
+ { DRA7_RNG_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
+ { DRA7_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
+ { DRA7_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01d0:24", "l4per2_clkdm" },
+ { DRA7_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e0:24", "l4per2_clkdm" },
+ { DRA7_UART9_CLKCTRL, dra7_uart9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e8:24", "l4per2_clkdm" },
+ { DRA7_DCAN2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin1", "l4per2_clkdm" },
+ { DRA7_MCASP6_CLKCTRL, dra7_mcasp6_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0204:22", "l4per2_clkdm" },
+ { DRA7_MCASP7_CLKCTRL, dra7_mcasp7_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0208:22", "l4per2_clkdm" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_gpio1_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_timer1_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_uart10_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const char * const dra7_dcan1_sys_clk_mux_parents[] __initconst = {
+ "sys_clkin1",
+ "sys_clkin2",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data dra7_dcan1_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_dcan1_sys_clk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initconst = {
+ { DRA7_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
+ { DRA7_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
+ { DRA7_GPIO1_CLKCTRL, dra7_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
+ { DRA7_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" },
+ { DRA7_TIMER12_CLKCTRL, NULL, 0, "secure_32k_clk_src_ck" },
+ { DRA7_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
+ { DRA7_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0060:24" },
+ { DRA7_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0068:24" },
+ { 0 },
+};
+
+const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = {
+ { 0x4a005320, dra7_mpu_clkctrl_regs },
+ { 0x4a005540, dra7_ipu_clkctrl_regs },
+ { 0x4a005740, dra7_rtc_clkctrl_regs },
+ { 0x4a008620, dra7_coreaon_clkctrl_regs },
+ { 0x4a008720, dra7_l3main1_clkctrl_regs },
+ { 0x4a008a20, dra7_dma_clkctrl_regs },
+ { 0x4a008b20, dra7_emif_clkctrl_regs },
+ { 0x4a008c00, dra7_atl_clkctrl_regs },
+ { 0x4a008d20, dra7_l4cfg_clkctrl_regs },
+ { 0x4a008e20, dra7_l3instr_clkctrl_regs },
+ { 0x4a009120, dra7_dss_clkctrl_regs },
+ { 0x4a009320, dra7_l3init_clkctrl_regs },
+ { 0x4a009700, dra7_l4per_clkctrl_regs },
+ { 0x4ae07820, dra7_wkupaon_clkctrl_regs },
+ { 0 },
+};
+
static struct ti_dt_clk dra7xx_clks[] = {
- DT_CLK(NULL, "atl_clkin0_ck", "atl_clkin0_ck"),
- DT_CLK(NULL, "atl_clkin1_ck", "atl_clkin1_ck"),
- DT_CLK(NULL, "atl_clkin2_ck", "atl_clkin2_ck"),
- DT_CLK(NULL, "atl_clkin3_ck", "atl_clkin3_ck"),
- DT_CLK(NULL, "hdmi_clkin_ck", "hdmi_clkin_ck"),
- DT_CLK(NULL, "mlb_clkin_ck", "mlb_clkin_ck"),
- DT_CLK(NULL, "mlbp_clkin_ck", "mlbp_clkin_ck"),
- DT_CLK(NULL, "pciesref_acs_clk_ck", "pciesref_acs_clk_ck"),
- DT_CLK(NULL, "ref_clkin0_ck", "ref_clkin0_ck"),
- DT_CLK(NULL, "ref_clkin1_ck", "ref_clkin1_ck"),
- DT_CLK(NULL, "ref_clkin2_ck", "ref_clkin2_ck"),
- DT_CLK(NULL, "ref_clkin3_ck", "ref_clkin3_ck"),
- DT_CLK(NULL, "rmii_clk_ck", "rmii_clk_ck"),
- DT_CLK(NULL, "sdvenc_clkin_ck", "sdvenc_clkin_ck"),
- DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"),
- DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"),
- DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"),
- DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"),
- DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"),
- DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
- DT_CLK(NULL, "virt_20000000_ck", "virt_20000000_ck"),
- DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
- DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"),
- DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"),
- DT_CLK(NULL, "sys_clkin1", "sys_clkin1"),
- DT_CLK(NULL, "sys_clkin2", "sys_clkin2"),
- DT_CLK(NULL, "usb_otg_clkin_ck", "usb_otg_clkin_ck"),
- DT_CLK(NULL, "video1_clkin_ck", "video1_clkin_ck"),
- DT_CLK(NULL, "video1_m2_clkin_ck", "video1_m2_clkin_ck"),
- DT_CLK(NULL, "video2_clkin_ck", "video2_clkin_ck"),
- DT_CLK(NULL, "video2_m2_clkin_ck", "video2_m2_clkin_ck"),
- DT_CLK(NULL, "abe_dpll_sys_clk_mux", "abe_dpll_sys_clk_mux"),
- DT_CLK(NULL, "abe_dpll_bypass_clk_mux", "abe_dpll_bypass_clk_mux"),
- DT_CLK(NULL, "abe_dpll_clk_mux", "abe_dpll_clk_mux"),
- DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"),
- DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"),
- DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"),
- DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"),
- DT_CLK(NULL, "abe_clk", "abe_clk"),
- DT_CLK(NULL, "aess_fclk", "aess_fclk"),
- DT_CLK(NULL, "abe_giclk_div", "abe_giclk_div"),
- DT_CLK(NULL, "abe_lp_clk_div", "abe_lp_clk_div"),
- DT_CLK(NULL, "abe_sys_clk_div", "abe_sys_clk_div"),
- DT_CLK(NULL, "adc_gfclk_mux", "adc_gfclk_mux"),
- DT_CLK(NULL, "dpll_pcie_ref_ck", "dpll_pcie_ref_ck"),
- DT_CLK(NULL, "dpll_pcie_ref_m2ldo_ck", "dpll_pcie_ref_m2ldo_ck"),
- DT_CLK(NULL, "apll_pcie_ck", "apll_pcie_ck"),
- DT_CLK(NULL, "apll_pcie_clkvcoldo", "apll_pcie_clkvcoldo"),
- DT_CLK(NULL, "apll_pcie_clkvcoldo_div", "apll_pcie_clkvcoldo_div"),
- DT_CLK(NULL, "apll_pcie_m2_ck", "apll_pcie_m2_ck"),
- DT_CLK(NULL, "sys_clk1_dclk_div", "sys_clk1_dclk_div"),
- DT_CLK(NULL, "sys_clk2_dclk_div", "sys_clk2_dclk_div"),
- DT_CLK(NULL, "dpll_abe_m2_ck", "dpll_abe_m2_ck"),
- DT_CLK(NULL, "per_abe_x1_dclk_div", "per_abe_x1_dclk_div"),
- DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"),
- DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
- DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
- DT_CLK(NULL, "dpll_core_h12x2_ck", "dpll_core_h12x2_ck"),
- DT_CLK(NULL, "mpu_dpll_hs_clk_div", "mpu_dpll_hs_clk_div"),
- DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
- DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
- DT_CLK(NULL, "mpu_dclk_div", "mpu_dclk_div"),
- DT_CLK(NULL, "dsp_dpll_hs_clk_div", "dsp_dpll_hs_clk_div"),
- DT_CLK(NULL, "dpll_dsp_ck", "dpll_dsp_ck"),
- DT_CLK(NULL, "dpll_dsp_m2_ck", "dpll_dsp_m2_ck"),
- DT_CLK(NULL, "dsp_gclk_div", "dsp_gclk_div"),
- DT_CLK(NULL, "iva_dpll_hs_clk_div", "iva_dpll_hs_clk_div"),
- DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"),
- DT_CLK(NULL, "dpll_iva_m2_ck", "dpll_iva_m2_ck"),
- DT_CLK(NULL, "iva_dclk", "iva_dclk"),
- DT_CLK(NULL, "dpll_gpu_ck", "dpll_gpu_ck"),
- DT_CLK(NULL, "dpll_gpu_m2_ck", "dpll_gpu_m2_ck"),
- DT_CLK(NULL, "gpu_dclk", "gpu_dclk"),
- DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"),
- DT_CLK(NULL, "core_dpll_out_dclk_div", "core_dpll_out_dclk_div"),
- DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"),
- DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"),
- DT_CLK(NULL, "emif_phy_dclk_div", "emif_phy_dclk_div"),
- DT_CLK(NULL, "dpll_gmac_ck", "dpll_gmac_ck"),
- DT_CLK(NULL, "dpll_gmac_m2_ck", "dpll_gmac_m2_ck"),
- DT_CLK(NULL, "gmac_250m_dclk_div", "gmac_250m_dclk_div"),
- DT_CLK(NULL, "video2_dclk_div", "video2_dclk_div"),
- DT_CLK(NULL, "video1_dclk_div", "video1_dclk_div"),
- DT_CLK(NULL, "hdmi_dclk_div", "hdmi_dclk_div"),
- DT_CLK(NULL, "per_dpll_hs_clk_div", "per_dpll_hs_clk_div"),
- DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
- DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
- DT_CLK(NULL, "func_96m_aon_dclk_div", "func_96m_aon_dclk_div"),
- DT_CLK(NULL, "usb_dpll_hs_clk_div", "usb_dpll_hs_clk_div"),
- DT_CLK(NULL, "dpll_usb_ck", "dpll_usb_ck"),
- DT_CLK(NULL, "dpll_usb_m2_ck", "dpll_usb_m2_ck"),
- DT_CLK(NULL, "l3init_480m_dclk_div", "l3init_480m_dclk_div"),
- DT_CLK(NULL, "usb_otg_dclk_div", "usb_otg_dclk_div"),
- DT_CLK(NULL, "sata_dclk_div", "sata_dclk_div"),
- DT_CLK(NULL, "dpll_pcie_ref_m2_ck", "dpll_pcie_ref_m2_ck"),
- DT_CLK(NULL, "pcie2_dclk_div", "pcie2_dclk_div"),
- DT_CLK(NULL, "pcie_dclk_div", "pcie_dclk_div"),
- DT_CLK(NULL, "emu_dclk_div", "emu_dclk_div"),
- DT_CLK(NULL, "secure_32k_dclk_div", "secure_32k_dclk_div"),
- DT_CLK(NULL, "eve_dpll_hs_clk_div", "eve_dpll_hs_clk_div"),
- DT_CLK(NULL, "dpll_eve_ck", "dpll_eve_ck"),
- DT_CLK(NULL, "dpll_eve_m2_ck", "dpll_eve_m2_ck"),
- DT_CLK(NULL, "eve_dclk_div", "eve_dclk_div"),
- DT_CLK(NULL, "clkoutmux0_clk_mux", "clkoutmux0_clk_mux"),
- DT_CLK(NULL, "clkoutmux1_clk_mux", "clkoutmux1_clk_mux"),
- DT_CLK(NULL, "clkoutmux2_clk_mux", "clkoutmux2_clk_mux"),
- DT_CLK(NULL, "custefuse_sys_gfclk_div", "custefuse_sys_gfclk_div"),
- DT_CLK(NULL, "dpll_core_h13x2_ck", "dpll_core_h13x2_ck"),
- DT_CLK(NULL, "dpll_core_h14x2_ck", "dpll_core_h14x2_ck"),
- DT_CLK(NULL, "dpll_core_h22x2_ck", "dpll_core_h22x2_ck"),
- DT_CLK(NULL, "dpll_core_h23x2_ck", "dpll_core_h23x2_ck"),
- DT_CLK(NULL, "dpll_core_h24x2_ck", "dpll_core_h24x2_ck"),
- DT_CLK(NULL, "dpll_ddr_x2_ck", "dpll_ddr_x2_ck"),
- DT_CLK(NULL, "dpll_ddr_h11x2_ck", "dpll_ddr_h11x2_ck"),
- DT_CLK(NULL, "dpll_dsp_x2_ck", "dpll_dsp_x2_ck"),
- DT_CLK(NULL, "dpll_dsp_m3x2_ck", "dpll_dsp_m3x2_ck"),
- DT_CLK(NULL, "dpll_gmac_x2_ck", "dpll_gmac_x2_ck"),
- DT_CLK(NULL, "dpll_gmac_h11x2_ck", "dpll_gmac_h11x2_ck"),
- DT_CLK(NULL, "dpll_gmac_h12x2_ck", "dpll_gmac_h12x2_ck"),
- DT_CLK(NULL, "dpll_gmac_h13x2_ck", "dpll_gmac_h13x2_ck"),
- DT_CLK(NULL, "dpll_gmac_m3x2_ck", "dpll_gmac_m3x2_ck"),
- DT_CLK(NULL, "dpll_per_x2_ck", "dpll_per_x2_ck"),
- DT_CLK(NULL, "dpll_per_h11x2_ck", "dpll_per_h11x2_ck"),
- DT_CLK(NULL, "dpll_per_h12x2_ck", "dpll_per_h12x2_ck"),
- DT_CLK(NULL, "dpll_per_h13x2_ck", "dpll_per_h13x2_ck"),
- DT_CLK(NULL, "dpll_per_h14x2_ck", "dpll_per_h14x2_ck"),
- DT_CLK(NULL, "dpll_per_m2x2_ck", "dpll_per_m2x2_ck"),
- DT_CLK(NULL, "dpll_usb_clkdcoldo", "dpll_usb_clkdcoldo"),
- DT_CLK(NULL, "eve_clk", "eve_clk"),
- DT_CLK(NULL, "func_128m_clk", "func_128m_clk"),
- DT_CLK(NULL, "func_12m_fclk", "func_12m_fclk"),
- DT_CLK(NULL, "func_24m_clk", "func_24m_clk"),
- DT_CLK(NULL, "func_48m_fclk", "func_48m_fclk"),
- DT_CLK(NULL, "func_96m_fclk", "func_96m_fclk"),
- DT_CLK(NULL, "gmii_m_clk_div", "gmii_m_clk_div"),
- DT_CLK(NULL, "hdmi_clk2_div", "hdmi_clk2_div"),
- DT_CLK(NULL, "hdmi_div_clk", "hdmi_div_clk"),
- DT_CLK(NULL, "hdmi_dpll_clk_mux", "hdmi_dpll_clk_mux"),
- DT_CLK(NULL, "l3_iclk_div", "l3_iclk_div"),
- DT_CLK(NULL, "l3init_60m_fclk", "l3init_60m_fclk"),
- DT_CLK(NULL, "l4_root_clk_div", "l4_root_clk_div"),
- DT_CLK(NULL, "mlb_clk", "mlb_clk"),
- DT_CLK(NULL, "mlbp_clk", "mlbp_clk"),
- DT_CLK(NULL, "per_abe_x1_gfclk2_div", "per_abe_x1_gfclk2_div"),
- DT_CLK(NULL, "timer_sys_clk_div", "timer_sys_clk_div"),
- DT_CLK(NULL, "video1_clk2_div", "video1_clk2_div"),
- DT_CLK(NULL, "video1_div_clk", "video1_div_clk"),
- DT_CLK(NULL, "video1_dpll_clk_mux", "video1_dpll_clk_mux"),
- DT_CLK(NULL, "video2_clk2_div", "video2_clk2_div"),
- DT_CLK(NULL, "video2_div_clk", "video2_div_clk"),
- DT_CLK(NULL, "video2_dpll_clk_mux", "video2_dpll_clk_mux"),
- DT_CLK(NULL, "wkupaon_iclk_mux", "wkupaon_iclk_mux"),
- DT_CLK(NULL, "dss_32khz_clk", "dss_32khz_clk"),
- DT_CLK(NULL, "dss_48mhz_clk", "dss_48mhz_clk"),
- DT_CLK(NULL, "dss_dss_clk", "dss_dss_clk"),
- DT_CLK(NULL, "dss_hdmi_clk", "dss_hdmi_clk"),
- DT_CLK(NULL, "dss_video1_clk", "dss_video1_clk"),
- DT_CLK(NULL, "dss_video2_clk", "dss_video2_clk"),
- DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
- DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
- DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
- DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"),
- DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"),
- DT_CLK(NULL, "gpio6_dbclk", "gpio6_dbclk"),
- DT_CLK(NULL, "gpio7_dbclk", "gpio7_dbclk"),
- DT_CLK(NULL, "gpio8_dbclk", "gpio8_dbclk"),
- DT_CLK(NULL, "mmc1_clk32k", "mmc1_clk32k"),
- DT_CLK(NULL, "mmc2_clk32k", "mmc2_clk32k"),
- DT_CLK(NULL, "mmc3_clk32k", "mmc3_clk32k"),
- DT_CLK(NULL, "mmc4_clk32k", "mmc4_clk32k"),
- DT_CLK(NULL, "sata_ref_clk", "sata_ref_clk"),
- DT_CLK(NULL, "usb_otg_ss1_refclk960m", "usb_otg_ss1_refclk960m"),
- DT_CLK(NULL, "usb_otg_ss2_refclk960m", "usb_otg_ss2_refclk960m"),
- DT_CLK(NULL, "usb_phy1_always_on_clk32k", "usb_phy1_always_on_clk32k"),
- DT_CLK(NULL, "usb_phy2_always_on_clk32k", "usb_phy2_always_on_clk32k"),
- DT_CLK(NULL, "usb_phy3_always_on_clk32k", "usb_phy3_always_on_clk32k"),
- DT_CLK(NULL, "atl_dpll_clk_mux", "atl_dpll_clk_mux"),
- DT_CLK(NULL, "atl_gfclk_mux", "atl_gfclk_mux"),
- DT_CLK(NULL, "dcan1_sys_clk_mux", "dcan1_sys_clk_mux"),
- DT_CLK(NULL, "gmac_rft_clk_mux", "gmac_rft_clk_mux"),
- DT_CLK(NULL, "gpu_core_gclk_mux", "gpu_core_gclk_mux"),
- DT_CLK(NULL, "gpu_hyd_gclk_mux", "gpu_hyd_gclk_mux"),
- DT_CLK(NULL, "ipu1_gfclk_mux", "ipu1_gfclk_mux"),
- DT_CLK(NULL, "l3instr_ts_gclk_div", "l3instr_ts_gclk_div"),
- DT_CLK(NULL, "mcasp1_ahclkr_mux", "mcasp1_ahclkr_mux"),
- DT_CLK(NULL, "mcasp1_ahclkx_mux", "mcasp1_ahclkx_mux"),
- DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "mcasp1_aux_gfclk_mux"),
- DT_CLK(NULL, "mcasp2_ahclkr_mux", "mcasp2_ahclkr_mux"),
- DT_CLK(NULL, "mcasp2_ahclkx_mux", "mcasp2_ahclkx_mux"),
- DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "mcasp2_aux_gfclk_mux"),
- DT_CLK(NULL, "mcasp3_ahclkx_mux", "mcasp3_ahclkx_mux"),
- DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "mcasp3_aux_gfclk_mux"),
- DT_CLK(NULL, "mcasp4_ahclkx_mux", "mcasp4_ahclkx_mux"),
- DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "mcasp4_aux_gfclk_mux"),
- DT_CLK(NULL, "mcasp5_ahclkx_mux", "mcasp5_ahclkx_mux"),
- DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "mcasp5_aux_gfclk_mux"),
- DT_CLK(NULL, "mcasp6_ahclkx_mux", "mcasp6_ahclkx_mux"),
- DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "mcasp6_aux_gfclk_mux"),
- DT_CLK(NULL, "mcasp7_ahclkx_mux", "mcasp7_ahclkx_mux"),
- DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "mcasp7_aux_gfclk_mux"),
- DT_CLK(NULL, "mcasp8_ahclkx_mux", "mcasp8_ahclkx_mux"),
- DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "mcasp8_aux_gfclk_mux"),
- DT_CLK(NULL, "mmc1_fclk_mux", "mmc1_fclk_mux"),
- DT_CLK(NULL, "mmc1_fclk_div", "mmc1_fclk_div"),
- DT_CLK(NULL, "mmc2_fclk_mux", "mmc2_fclk_mux"),
- DT_CLK(NULL, "mmc2_fclk_div", "mmc2_fclk_div"),
- DT_CLK(NULL, "mmc3_gfclk_mux", "mmc3_gfclk_mux"),
- DT_CLK(NULL, "mmc3_gfclk_div", "mmc3_gfclk_div"),
- DT_CLK(NULL, "mmc4_gfclk_mux", "mmc4_gfclk_mux"),
- DT_CLK(NULL, "mmc4_gfclk_div", "mmc4_gfclk_div"),
- DT_CLK(NULL, "qspi_gfclk_mux", "qspi_gfclk_mux"),
- DT_CLK(NULL, "qspi_gfclk_div", "qspi_gfclk_div"),
- DT_CLK(NULL, "timer10_gfclk_mux", "timer10_gfclk_mux"),
- DT_CLK(NULL, "timer11_gfclk_mux", "timer11_gfclk_mux"),
- DT_CLK(NULL, "timer13_gfclk_mux", "timer13_gfclk_mux"),
- DT_CLK(NULL, "timer14_gfclk_mux", "timer14_gfclk_mux"),
- DT_CLK(NULL, "timer15_gfclk_mux", "timer15_gfclk_mux"),
- DT_CLK(NULL, "timer16_gfclk_mux", "timer16_gfclk_mux"),
- DT_CLK(NULL, "timer1_gfclk_mux", "timer1_gfclk_mux"),
- DT_CLK(NULL, "timer2_gfclk_mux", "timer2_gfclk_mux"),
- DT_CLK(NULL, "timer3_gfclk_mux", "timer3_gfclk_mux"),
- DT_CLK(NULL, "timer4_gfclk_mux", "timer4_gfclk_mux"),
- DT_CLK(NULL, "timer5_gfclk_mux", "timer5_gfclk_mux"),
- DT_CLK(NULL, "timer6_gfclk_mux", "timer6_gfclk_mux"),
- DT_CLK(NULL, "timer7_gfclk_mux", "timer7_gfclk_mux"),
- DT_CLK(NULL, "timer8_gfclk_mux", "timer8_gfclk_mux"),
- DT_CLK(NULL, "timer9_gfclk_mux", "timer9_gfclk_mux"),
- DT_CLK(NULL, "uart10_gfclk_mux", "uart10_gfclk_mux"),
- DT_CLK(NULL, "uart1_gfclk_mux", "uart1_gfclk_mux"),
- DT_CLK(NULL, "uart2_gfclk_mux", "uart2_gfclk_mux"),
- DT_CLK(NULL, "uart3_gfclk_mux", "uart3_gfclk_mux"),
- DT_CLK(NULL, "uart4_gfclk_mux", "uart4_gfclk_mux"),
- DT_CLK(NULL, "uart5_gfclk_mux", "uart5_gfclk_mux"),
- DT_CLK(NULL, "uart6_gfclk_mux", "uart6_gfclk_mux"),
- DT_CLK(NULL, "uart7_gfclk_mux", "uart7_gfclk_mux"),
- DT_CLK(NULL, "uart8_gfclk_mux", "uart8_gfclk_mux"),
- DT_CLK(NULL, "uart9_gfclk_mux", "uart9_gfclk_mux"),
- DT_CLK(NULL, "vip1_gclk_mux", "vip1_gclk_mux"),
- DT_CLK(NULL, "vip2_gclk_mux", "vip2_gclk_mux"),
- DT_CLK(NULL, "vip3_gclk_mux", "vip3_gclk_mux"),
- DT_CLK("omap_i2c.1", "ick", "dummy_ck"),
- DT_CLK("omap_i2c.2", "ick", "dummy_ck"),
- DT_CLK("omap_i2c.3", "ick", "dummy_ck"),
- DT_CLK("omap_i2c.4", "ick", "dummy_ck"),
- DT_CLK(NULL, "mailboxes_ick", "dummy_ck"),
- DT_CLK("omap_hsmmc.0", "ick", "dummy_ck"),
- DT_CLK("omap_hsmmc.1", "ick", "dummy_ck"),
- DT_CLK("omap_hsmmc.2", "ick", "dummy_ck"),
- DT_CLK("omap_hsmmc.3", "ick", "dummy_ck"),
- DT_CLK("omap_hsmmc.4", "ick", "dummy_ck"),
- DT_CLK("omap-mcbsp.1", "ick", "dummy_ck"),
- DT_CLK("omap-mcbsp.2", "ick", "dummy_ck"),
- DT_CLK("omap-mcbsp.3", "ick", "dummy_ck"),
- DT_CLK("omap-mcbsp.4", "ick", "dummy_ck"),
- DT_CLK("omap2_mcspi.1", "ick", "dummy_ck"),
- DT_CLK("omap2_mcspi.2", "ick", "dummy_ck"),
- DT_CLK("omap2_mcspi.3", "ick", "dummy_ck"),
- DT_CLK("omap2_mcspi.4", "ick", "dummy_ck"),
- DT_CLK(NULL, "uart1_ick", "dummy_ck"),
- DT_CLK(NULL, "uart2_ick", "dummy_ck"),
- DT_CLK(NULL, "uart3_ick", "dummy_ck"),
- DT_CLK(NULL, "uart4_ick", "dummy_ck"),
- DT_CLK("usbhs_omap", "usbhost_ick", "dummy_ck"),
- DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"),
- DT_CLK("omap_wdt", "ick", "dummy_ck"),
DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
DT_CLK(NULL, "sys_clkin_ck", "timer_sys_clk_div"),
- DT_CLK("4ae18000.timer", "timer_sys_ck", "timer_sys_clk_div"),
- DT_CLK("48032000.timer", "timer_sys_ck", "timer_sys_clk_div"),
- DT_CLK("48034000.timer", "timer_sys_ck", "timer_sys_clk_div"),
- DT_CLK("48036000.timer", "timer_sys_ck", "timer_sys_clk_div"),
- DT_CLK("4803e000.timer", "timer_sys_ck", "timer_sys_clk_div"),
- DT_CLK("48086000.timer", "timer_sys_ck", "timer_sys_clk_div"),
- DT_CLK("48088000.timer", "timer_sys_ck", "timer_sys_clk_div"),
- DT_CLK("48820000.timer", "timer_sys_ck", "timer_sys_clk_div"),
- DT_CLK("48822000.timer", "timer_sys_ck", "timer_sys_clk_div"),
- DT_CLK("48824000.timer", "timer_sys_ck", "timer_sys_clk_div"),
- DT_CLK("48826000.timer", "timer_sys_ck", "timer_sys_clk_div"),
- DT_CLK("48828000.timer", "timer_sys_ck", "timer_sys_clk_div"),
- DT_CLK("4882a000.timer", "timer_sys_ck", "timer_sys_clk_div"),
- DT_CLK("4882c000.timer", "timer_sys_ck", "timer_sys_clk_div"),
- DT_CLK("4882e000.timer", "timer_sys_ck", "timer_sys_clk_div"),
DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
- DT_CLK(NULL, "dss_deshdcp_clk", "dss_deshdcp_clk"),
+ DT_CLK(NULL, "atl_dpll_clk_mux", "atl_cm:0000:24"),
+ DT_CLK(NULL, "atl_gfclk_mux", "atl_cm:0000:26"),
+ DT_CLK(NULL, "dcan1_sys_clk_mux", "wkupaon_cm:0068:24"),
+ DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"),
+ DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"),
+ DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"),
+ DT_CLK(NULL, "dss_hdmi_clk", "dss_cm:0000:10"),
+ DT_CLK(NULL, "dss_video1_clk", "dss_cm:0000:12"),
+ DT_CLK(NULL, "dss_video2_clk", "dss_cm:0000:13"),
+ DT_CLK(NULL, "gmac_rft_clk_mux", "l3init_cm:00b0:25"),
+ DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"),
+ DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0060:8"),
+ DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0068:8"),
+ DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0070:8"),
+ DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0078:8"),
+ DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0080:8"),
+ DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:0110:8"),
+ DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:0118:8"),
+ DT_CLK(NULL, "mcasp1_ahclkr_mux", "ipu_cm:0010:28"),
+ DT_CLK(NULL, "mcasp1_ahclkx_mux", "ipu_cm:0010:24"),
+ DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "ipu_cm:0010:22"),
+ DT_CLK(NULL, "mcasp2_ahclkr_mux", "l4per_cm:0160:28"),
+ DT_CLK(NULL, "mcasp2_ahclkx_mux", "l4per_cm:0160:24"),
+ DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "l4per_cm:0160:22"),
+ DT_CLK(NULL, "mcasp3_ahclkx_mux", "l4per_cm:0168:24"),
+ DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "l4per_cm:0168:22"),
+ DT_CLK(NULL, "mcasp4_ahclkx_mux", "l4per_cm:0198:24"),
+ DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "l4per_cm:0198:22"),
+ DT_CLK(NULL, "mcasp5_ahclkx_mux", "l4per_cm:0178:24"),
+ DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "l4per_cm:0178:22"),
+ DT_CLK(NULL, "mcasp6_ahclkx_mux", "l4per_cm:0204:24"),
+ DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per_cm:0204:22"),
+ DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per_cm:0208:24"),
+ DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per_cm:0208:22"),
+ DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per_cm:0190:22"),
+ DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per_cm:0190:24"),
+ DT_CLK(NULL, "mmc1_clk32k", "l3init_cm:0008:8"),
+ DT_CLK(NULL, "mmc1_fclk_div", "l3init_cm:0008:25"),
+ DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"),
+ DT_CLK(NULL, "mmc2_clk32k", "l3init_cm:0010:8"),
+ DT_CLK(NULL, "mmc2_fclk_div", "l3init_cm:0010:25"),
+ DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"),
+ DT_CLK(NULL, "mmc3_clk32k", "l4per_cm:0120:8"),
+ DT_CLK(NULL, "mmc3_gfclk_div", "l4per_cm:0120:25"),
+ DT_CLK(NULL, "mmc3_gfclk_mux", "l4per_cm:0120:24"),
+ DT_CLK(NULL, "mmc4_clk32k", "l4per_cm:0128:8"),
+ DT_CLK(NULL, "mmc4_gfclk_div", "l4per_cm:0128:25"),
+ DT_CLK(NULL, "mmc4_gfclk_mux", "l4per_cm:0128:24"),
+ DT_CLK(NULL, "optfclk_pciephy1_32khz", "l3init_cm:0090:8"),
+ DT_CLK(NULL, "optfclk_pciephy1_clk", "l3init_cm:0090:9"),
+ DT_CLK(NULL, "optfclk_pciephy1_div_clk", "l3init_cm:0090:10"),
+ DT_CLK(NULL, "optfclk_pciephy2_32khz", "l3init_cm:0098:8"),
+ DT_CLK(NULL, "optfclk_pciephy2_clk", "l3init_cm:0098:9"),
+ DT_CLK(NULL, "optfclk_pciephy2_div_clk", "l3init_cm:0098:10"),
+ DT_CLK(NULL, "qspi_gfclk_div", "l4per_cm:0138:25"),
+ DT_CLK(NULL, "qspi_gfclk_mux", "l4per_cm:0138:24"),
+ DT_CLK(NULL, "rmii_50mhz_clk_mux", "l3init_cm:00b0:24"),
+ DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"),
+ DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0028:24"),
+ DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0030:24"),
+ DT_CLK(NULL, "timer13_gfclk_mux", "l4per_cm:00c8:24"),
+ DT_CLK(NULL, "timer14_gfclk_mux", "l4per_cm:00d0:24"),
+ DT_CLK(NULL, "timer15_gfclk_mux", "l4per_cm:00d8:24"),
+ DT_CLK(NULL, "timer16_gfclk_mux", "l4per_cm:0130:24"),
+ DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"),
+ DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0038:24"),
+ DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0040:24"),
+ DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0048:24"),
+ DT_CLK(NULL, "timer5_gfclk_mux", "ipu_cm:0018:24"),
+ DT_CLK(NULL, "timer6_gfclk_mux", "ipu_cm:0020:24"),
+ DT_CLK(NULL, "timer7_gfclk_mux", "ipu_cm:0028:24"),
+ DT_CLK(NULL, "timer8_gfclk_mux", "ipu_cm:0030:24"),
+ DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0050:24"),
+ DT_CLK(NULL, "uart10_gfclk_mux", "wkupaon_cm:0060:24"),
+ DT_CLK(NULL, "uart1_gfclk_mux", "l4per_cm:0140:24"),
+ DT_CLK(NULL, "uart2_gfclk_mux", "l4per_cm:0148:24"),
+ DT_CLK(NULL, "uart3_gfclk_mux", "l4per_cm:0150:24"),
+ DT_CLK(NULL, "uart4_gfclk_mux", "l4per_cm:0158:24"),
+ DT_CLK(NULL, "uart5_gfclk_mux", "l4per_cm:0170:24"),
+ DT_CLK(NULL, "uart6_gfclk_mux", "ipu_cm:0040:24"),
+ DT_CLK(NULL, "uart7_gfclk_mux", "l4per_cm:01d0:24"),
+ DT_CLK(NULL, "uart8_gfclk_mux", "l4per_cm:01e0:24"),
+ DT_CLK(NULL, "uart9_gfclk_mux", "l4per_cm:01e8:24"),
+ DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3init_cm:00d0:8"),
+ DT_CLK(NULL, "usb_otg_ss2_refclk960m", "l3init_cm:0020:8"),
{ .node_name = NULL },
};
@@ -318,6 +830,8 @@ int __init dra7xx_dt_clk_init(void)
omap2_clk_disable_autoidle_all();
+ ti_clk_add_aliases();
+
dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck");
rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ);
if (rc)
diff --git a/drivers/clk/ti/clk-814x.c b/drivers/clk/ti/clk-814x.c
index 52c6efc53731..f688fdd2cb59 100644
--- a/drivers/clk/ti/clk-814x.c
+++ b/drivers/clk/ti/clk-814x.c
@@ -9,23 +9,48 @@
#include <linux/clk-provider.h>
#include <linux/clk/ti.h>
#include <linux/of_platform.h>
+#include <dt-bindings/clock/dm814.h>
#include "clock.h"
+static const struct omap_clkctrl_reg_data dm814_default_clkctrl_regs[] __initconst = {
+ { DM814_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "pll260dcoclkldo" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data dm814_alwon_clkctrl_regs[] __initconst = {
+ { DM814_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
+ { DM814_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
+ { DM814_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
+ { DM814_GPIO1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
+ { DM814_GPIO2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
+ { DM814_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
+ { DM814_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
+ { DM814_WD_TIMER_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
+ { DM814_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
+ { DM814_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
+ { DM814_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk" },
+ { DM814_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "mpu_ck" },
+ { DM814_RTC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
+ { DM814_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
+ { DM814_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
+ { DM814_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
+ { DM814_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
+ { DM814_TPTC3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
+ { DM814_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" },
+ { DM814_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" },
+ { DM814_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" },
+ { 0 },
+};
+
+const struct omap_clkctrl_data dm814_clkctrl_data[] __initconst = {
+ { 0x48180500, dm814_default_clkctrl_regs },
+ { 0x48181400, dm814_alwon_clkctrl_regs },
+ { 0 },
+};
+
static struct ti_dt_clk dm814_clks[] = {
- DT_CLK(NULL, "devosc_ck", "devosc_ck"),
- DT_CLK(NULL, "mpu_ck", "mpu_ck"),
- DT_CLK(NULL, "sysclk4_ck", "sysclk4_ck"),
- DT_CLK(NULL, "sysclk5_ck", "sysclk5_ck"),
- DT_CLK(NULL, "sysclk6_ck", "sysclk6_ck"),
- DT_CLK(NULL, "sysclk8_ck", "sysclk8_ck"),
- DT_CLK(NULL, "sysclk10_ck", "sysclk10_ck"),
- DT_CLK(NULL, "sysclk18_ck", "sysclk18_ck"),
DT_CLK(NULL, "timer_sys_ck", "devosc_ck"),
- DT_CLK(NULL, "timer1_fck", "timer1_fck"),
- DT_CLK(NULL, "timer2_fck", "timer2_fck"),
- DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),
- DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),
{ .node_name = NULL },
};
@@ -83,6 +108,7 @@ int __init dm814x_dt_clk_init(void)
{
ti_dt_clocks_register(dm814_clks);
omap2_clk_disable_autoidle_all();
+ ti_clk_add_aliases();
omap2_clk_enable_init_clocks(NULL, 0);
timer_clocks_initialized = true;
diff --git a/drivers/clk/ti/clk-816x.c b/drivers/clk/ti/clk-816x.c
index 2a5d84fdddc5..7d215cdf9dda 100644
--- a/drivers/clk/ti/clk-816x.c
+++ b/drivers/clk/ti/clk-816x.c
@@ -13,30 +13,59 @@
#include <linux/list.h>
#include <linux/clk-provider.h>
#include <linux/clk/ti.h>
+#include <dt-bindings/clock/dm816.h>
#include "clock.h"
+static const struct omap_clkctrl_reg_data dm816_default_clkctrl_regs[] __initconst = {
+ { DM816_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data dm816_alwon_clkctrl_regs[] __initconst = {
+ { DM816_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
+ { DM816_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
+ { DM816_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
+ { DM816_GPIO1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
+ { DM816_GPIO2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
+ { DM816_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
+ { DM816_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
+ { DM816_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },
+ { DM816_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
+ { DM816_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
+ { DM816_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
+ { DM816_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
+ { DM816_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
+ { DM816_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
+ { DM816_WD_TIMER_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
+ { DM816_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
+ { DM816_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
+ { DM816_SPINBOX_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
+ { DM816_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
+ { DM816_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
+ { DM816_DAVINCI_MDIO_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk24_ck" },
+ { DM816_EMAC1_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk24_ck" },
+ { DM816_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk2_ck" },
+ { DM816_RTC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
+ { DM816_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
+ { DM816_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
+ { DM816_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
+ { DM816_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
+ { DM816_TPTC3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
+ { 0 },
+};
+
+const struct omap_clkctrl_data dm816_clkctrl_data[] __initconst = {
+ { 0x48180500, dm816_default_clkctrl_regs },
+ { 0x48181400, dm816_alwon_clkctrl_regs },
+ { 0 },
+};
+
static struct ti_dt_clk dm816x_clks[] = {
DT_CLK(NULL, "sys_clkin", "sys_clkin_ck"),
DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
- DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"),
DT_CLK(NULL, "timer_32k_ck", "sysclk18_ck"),
DT_CLK(NULL, "timer_ext_ck", "tclkin_ck"),
- DT_CLK(NULL, "mpu_ck", "mpu_ck"),
- DT_CLK(NULL, "timer1_fck", "timer1_fck"),
- DT_CLK(NULL, "timer2_fck", "timer2_fck"),
- DT_CLK(NULL, "timer3_fck", "timer3_fck"),
- DT_CLK(NULL, "timer4_fck", "timer4_fck"),
- DT_CLK(NULL, "timer5_fck", "timer5_fck"),
- DT_CLK(NULL, "timer6_fck", "timer6_fck"),
- DT_CLK(NULL, "timer7_fck", "timer7_fck"),
- DT_CLK(NULL, "sysclk4_ck", "sysclk4_ck"),
- DT_CLK(NULL, "sysclk5_ck", "sysclk5_ck"),
- DT_CLK(NULL, "sysclk6_ck", "sysclk6_ck"),
- DT_CLK(NULL, "sysclk10_ck", "sysclk10_ck"),
- DT_CLK(NULL, "sysclk18_ck", "sysclk18_ck"),
- DT_CLK(NULL, "sysclk24_ck", "sysclk24_ck"),
- DT_CLK("4a100000.ethernet", "sysclk24_ck", "sysclk24_ck"),
{ .node_name = NULL },
};
@@ -50,6 +79,7 @@ int __init dm816x_dt_clk_init(void)
{
ti_dt_clocks_register(dm816x_clks);
omap2_clk_disable_autoidle_all();
+ ti_clk_add_aliases();
omap2_clk_enable_init_clocks(enable_init_clks,
ARRAY_SIZE(enable_init_clks));
diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c
index e5a1c8297a1d..302c9e64e5fa 100644
--- a/drivers/clk/ti/clk.c
+++ b/drivers/clk/ti/clk.c
@@ -108,25 +108,77 @@ void __init ti_dt_clocks_register(struct ti_dt_clk oclks[])
struct device_node *node;
struct clk *clk;
struct of_phandle_args clkspec;
+ char buf[64];
+ char *ptr;
+ char *tags[2];
+ int i;
+ int num_args;
+ int ret;
+ static bool clkctrl_nodes_missing;
+ static bool has_clkctrl_data;
for (c = oclks; c->node_name != NULL; c++) {
- node = of_find_node_by_name(NULL, c->node_name);
+ strcpy(buf, c->node_name);
+ ptr = buf;
+ for (i = 0; i < 2; i++)
+ tags[i] = NULL;
+ num_args = 0;
+ while (*ptr) {
+ if (*ptr == ':') {
+ if (num_args >= 2) {
+ pr_warn("Bad number of tags on %s\n",
+ c->node_name);
+ return;
+ }
+ tags[num_args++] = ptr + 1;
+ *ptr = 0;
+ }
+ ptr++;
+ }
+
+ if (num_args && clkctrl_nodes_missing)
+ continue;
+
+ node = of_find_node_by_name(NULL, buf);
+ if (num_args)
+ node = of_find_node_by_name(node, "clk");
clkspec.np = node;
+ clkspec.args_count = num_args;
+ for (i = 0; i < num_args; i++) {
+ ret = kstrtoint(tags[i], i ? 10 : 16, clkspec.args + i);
+ if (ret) {
+ pr_warn("Bad tag in %s at %d: %s\n",
+ c->node_name, i, tags[i]);
+ return;
+ }
+ }
clk = of_clk_get_from_provider(&clkspec);
if (!IS_ERR(clk)) {
c->lk.clk = clk;
clkdev_add(&c->lk);
} else {
- pr_warn("failed to lookup clock node %s\n",
- c->node_name);
+ if (num_args && !has_clkctrl_data) {
+ if (of_find_compatible_node(NULL, NULL,
+ "ti,clkctrl")) {
+ has_clkctrl_data = true;
+ } else {
+ clkctrl_nodes_missing = true;
+
+ pr_warn("missing clkctrl nodes, please update your dts.\n");
+ continue;
+ }
+ }
+
+ pr_warn("failed to lookup clock node %s, ret=%ld\n",
+ c->node_name, PTR_ERR(clk));
}
}
}
struct clk_init_item {
struct device_node *node;
- struct clk_hw *hw;
+ void *user;
ti_of_clk_init_cb_t func;
struct list_head link;
};
@@ -136,14 +188,14 @@ static LIST_HEAD(retry_list);
/**
* ti_clk_retry_init - retries a failed clock init at later phase
* @node: device not for the clock
- * @hw: partially initialized clk_hw struct for the clock
+ * @user: user data pointer
* @func: init function to be called for the clock
*
* Adds a failed clock init to the retry list. The retry list is parsed
* once all the other clocks have been initialized.
*/
-int __init ti_clk_retry_init(struct device_node *node, struct clk_hw *hw,
- ti_of_clk_init_cb_t func)
+int __init ti_clk_retry_init(struct device_node *node, void *user,
+ ti_of_clk_init_cb_t func)
{
struct clk_init_item *retry;
@@ -154,7 +206,7 @@ int __init ti_clk_retry_init(struct device_node *node, struct clk_hw *hw,
retry->node = node;
retry->func = func;
- retry->hw = hw;
+ retry->user = user;
list_add(&retry->link, &retry_list);
return 0;
@@ -276,7 +328,7 @@ void ti_dt_clk_init_retry_clks(void)
while (!list_empty(&retry_list) && retries) {
list_for_each_entry_safe(retry, tmp, &retry_list, link) {
pr_debug("retry-init: %s\n", retry->node->name);
- retry->func(retry->hw, retry->node);
+ retry->func(retry->user, retry->node);
list_del(&retry->link);
kfree(retry);
}
diff --git a/drivers/clk/ti/clkctrl.c b/drivers/clk/ti/clkctrl.c
index 53e71d0503ec..afa0d6bfc5c1 100644
--- a/drivers/clk/ti/clkctrl.c
+++ b/drivers/clk/ti/clkctrl.c
@@ -21,6 +21,7 @@
#include <linux/of_address.h>
#include <linux/clk/ti.h>
#include <linux/delay.h>
+#include <linux/timekeeping.h>
#include "clock.h"
#define NO_IDLEST 0x1
@@ -46,6 +47,7 @@ static bool _early_timeout = true;
struct omap_clkctrl_provider {
void __iomem *base;
struct list_head clocks;
+ char *clkdm_name;
};
struct omap_clkctrl_clk {
@@ -89,7 +91,18 @@ static bool _omap4_is_ready(u32 val)
static bool _omap4_is_timeout(union omap4_timeout *time, u32 timeout)
{
- if (unlikely(_early_timeout)) {
+ /*
+ * There are two special cases where ktime_to_ns() can't be
+ * used to track the timeouts. First one is during early boot
+ * when the timers haven't been initialized yet. The second
+ * one is during suspend-resume cycle while timekeeping is
+ * being suspended / resumed. Clocksource for the system
+ * can be from a timer that requires pm_runtime access, which
+ * will eventually bring us here with timekeeping_suspended,
+ * during both suspend entry and resume paths. This happens
+ * at least on am43xx platform.
+ */
+ if (unlikely(_early_timeout || timekeeping_suspended)) {
if (time->cycles++ < timeout) {
udelay(1);
return false;
@@ -208,6 +221,7 @@ static const struct clk_ops omap4_clkctrl_clk_ops = {
.enable = _omap4_clkctrl_clk_enable,
.disable = _omap4_clkctrl_clk_disable,
.is_enabled = _omap4_clkctrl_clk_is_enabled,
+ .init = omap2_init_clk_clkdm,
};
static struct clk_hw *_ti_omap4_clkctrl_xlate(struct of_phandle_args *clkspec,
@@ -321,6 +335,9 @@ _ti_clkctrl_setup_mux(struct omap_clkctrl_provider *provider,
}
mux->mask = num_parents;
+ if (!(mux->flags & CLK_MUX_INDEX_ONE))
+ mux->mask--;
+
mux->mask = (1 << fls(mux->mask)) - 1;
mux->shift = data->bit;
@@ -340,6 +357,7 @@ _ti_clkctrl_setup_div(struct omap_clkctrl_provider *provider,
{
struct clk_omap_divider *div;
const struct omap_clkctrl_div_data *div_data = data->data;
+ u8 div_flags = 0;
div = kzalloc(sizeof(*div), GFP_KERNEL);
if (!div)
@@ -347,12 +365,16 @@ _ti_clkctrl_setup_div(struct omap_clkctrl_provider *provider,
div->reg.ptr = reg;
div->shift = data->bit;
+ div->flags = div_data->flags;
+
+ if (div->flags & CLK_DIVIDER_POWER_OF_TWO)
+ div_flags |= CLKF_INDEX_POWER_OF_TWO;
- if (ti_clk_parse_divider_data((int *)div_data->dividers,
- div_data->max_div, 0, 0,
+ if (ti_clk_parse_divider_data((int *)div_data->dividers, 0,
+ div_data->max_div, div_flags,
&div->width, &div->table)) {
- pr_err("%s: Data parsing for %s:%04x:%d failed\n", __func__,
- node->name, offset, data->bit);
+ pr_err("%s: Data parsing for %pOF:%04x:%d failed\n", __func__,
+ node, offset, data->bit);
kfree(div);
return;
}
@@ -400,6 +422,12 @@ _ti_clkctrl_setup_subclks(struct omap_clkctrl_provider *provider,
}
}
+static void __init _clkctrl_add_provider(void *data,
+ struct device_node *np)
+{
+ of_clk_add_hw_provider(np, _ti_omap4_clkctrl_xlate, data);
+}
+
static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
{
struct omap_clkctrl_provider *provider;
@@ -411,6 +439,7 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
struct omap_clkctrl_clk *clkctrl_clk;
const __be32 *addrp;
u32 addr;
+ int ret;
addrp = of_get_address(node, 0, NULL, NULL);
addr = (u32)of_translate_address(node, addrp);
@@ -419,6 +448,31 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
if (of_machine_is_compatible("ti,omap4"))
data = omap4_clkctrl_data;
#endif
+#ifdef CONFIG_SOC_OMAP5
+ if (of_machine_is_compatible("ti,omap5"))
+ data = omap5_clkctrl_data;
+#endif
+#ifdef CONFIG_SOC_DRA7XX
+ if (of_machine_is_compatible("ti,dra7"))
+ data = dra7_clkctrl_data;
+#endif
+#ifdef CONFIG_SOC_AM33XX
+ if (of_machine_is_compatible("ti,am33xx"))
+ data = am3_clkctrl_data;
+#endif
+#ifdef CONFIG_SOC_AM43XX
+ if (of_machine_is_compatible("ti,am4372"))
+ data = am4_clkctrl_data;
+ if (of_machine_is_compatible("ti,am438x"))
+ data = am438x_clkctrl_data;
+#endif
+#ifdef CONFIG_SOC_TI81XX
+ if (of_machine_is_compatible("ti,dm814"))
+ data = dm814_clkctrl_data;
+
+ if (of_machine_is_compatible("ti,dm816"))
+ data = dm816_clkctrl_data;
+#endif
while (data->addr) {
if (addr == data->addr)
@@ -428,7 +482,7 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
}
if (!data->addr) {
- pr_err("%s not found from clkctrl data.\n", node->name);
+ pr_err("%pOF not found from clkctrl data.\n", node);
return;
}
@@ -438,6 +492,21 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
provider->base = of_iomap(node, 0);
+ provider->clkdm_name = kmalloc(strlen(node->parent->name) + 3,
+ GFP_KERNEL);
+ if (!provider->clkdm_name) {
+ kfree(provider);
+ return;
+ }
+
+ /*
+ * Create default clkdm name, replace _cm from end of parent node
+ * name with _clkdm
+ */
+ strcpy(provider->clkdm_name, node->parent->name);
+ provider->clkdm_name[strlen(provider->clkdm_name) - 2] = 0;
+ strcat(provider->clkdm_name, "clkdm");
+
INIT_LIST_HEAD(&provider->clocks);
/* Generate clocks */
@@ -460,6 +529,11 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
if (reg_data->flags & CLKF_NO_IDLEST)
hw->flags |= NO_IDLEST;
+ if (reg_data->clkdm_name)
+ hw->clkdm_name = reg_data->clkdm_name;
+ else
+ hw->clkdm_name = provider->clkdm_name;
+
init.parent_names = &reg_data->parent;
init.num_parents = 1;
init.flags = 0;
@@ -485,7 +559,10 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
reg_data++;
}
- of_clk_add_hw_provider(node, _ti_omap4_clkctrl_xlate, provider);
+ ret = of_clk_add_hw_provider(node, _ti_omap4_clkctrl_xlate, provider);
+ if (ret == -EPROBE_DEFER)
+ ti_clk_retry_init(node, provider, _clkctrl_add_provider);
+
return;
cleanup:
diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h
index 561dbe99ced7..883e39e5d3ec 100644
--- a/drivers/clk/ti/clock.h
+++ b/drivers/clk/ti/clock.h
@@ -207,6 +207,7 @@ struct ti_dt_clk {
struct omap_clkctrl_div_data {
const int *dividers;
int max_div;
+ u32 flags;
};
struct omap_clkctrl_bit_data {
@@ -221,6 +222,7 @@ struct omap_clkctrl_reg_data {
const struct omap_clkctrl_bit_data *bit_data;
u16 flags;
const char *parent;
+ const char *clkdm_name;
};
struct omap_clkctrl_data {
@@ -229,12 +231,19 @@ struct omap_clkctrl_data {
};
extern const struct omap_clkctrl_data omap4_clkctrl_data[];
+extern const struct omap_clkctrl_data omap5_clkctrl_data[];
+extern const struct omap_clkctrl_data dra7_clkctrl_data[];
+extern const struct omap_clkctrl_data am3_clkctrl_data[];
+extern const struct omap_clkctrl_data am4_clkctrl_data[];
+extern const struct omap_clkctrl_data am438x_clkctrl_data[];
+extern const struct omap_clkctrl_data dm814_clkctrl_data[];
+extern const struct omap_clkctrl_data dm816_clkctrl_data[];
#define CLKF_SW_SUP BIT(0)
#define CLKF_HW_SUP BIT(1)
#define CLKF_NO_IDLEST BIT(2)
-typedef void (*ti_of_clk_init_cb_t)(struct clk_hw *, struct device_node *);
+typedef void (*ti_of_clk_init_cb_t)(void *, struct device_node *);
struct clk *ti_clk_register_gate(struct ti_clk *setup);
struct clk *ti_clk_register_interface(struct ti_clk *setup);
@@ -262,7 +271,7 @@ int ti_clk_register_legacy_clks(struct ti_clk_alias *clks);
int ti_clk_get_reg_addr(struct device_node *node, int index,
struct clk_omap_reg *reg);
void ti_dt_clocks_register(struct ti_dt_clk *oclks);
-int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw,
+int ti_clk_retry_init(struct device_node *node, void *user,
ti_of_clk_init_cb_t func);
int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type);
diff --git a/drivers/clk/ti/composite.c b/drivers/clk/ti/composite.c
index beea89463ca2..3eaba2d16ce4 100644
--- a/drivers/clk/ti/composite.c
+++ b/drivers/clk/ti/composite.c
@@ -161,9 +161,10 @@ struct clk *ti_clk_register_composite(struct ti_clk *setup)
}
#endif
-static void __init _register_composite(struct clk_hw *hw,
+static void __init _register_composite(void *user,
struct device_node *node)
{
+ struct clk_hw *hw = user;
struct clk *clk;
struct clk_hw_omap_comp *cclk = to_clk_hw_comp(hw);
struct component_clk *comp;
diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c
index d4e4444bc5ca..d246598c5016 100644
--- a/drivers/clk/ti/dpll.c
+++ b/drivers/clk/ti/dpll.c
@@ -152,9 +152,10 @@ static const struct clk_ops dpll_x2_ck_ops = {
* clk-bypass is missing), the clock is added to retry list and
* the initialization is retried on later stage.
*/
-static void __init _register_dpll(struct clk_hw *hw,
+static void __init _register_dpll(void *user,
struct device_node *node)
{
+ struct clk_hw *hw = user;
struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
struct dpll_data *dd = clk_hw->dpll_data;
struct clk *clk;
diff --git a/include/dt-bindings/clock/am3.h b/include/dt-bindings/clock/am3.h
new file mode 100644
index 000000000000..b396f00e481d
--- /dev/null
+++ b/include/dt-bindings/clock/am3.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright 2017 Texas Instruments, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_CLK_AM3_H
+#define __DT_BINDINGS_CLK_AM3_H
+
+#define AM3_CLKCTRL_OFFSET 0x0
+#define AM3_CLKCTRL_INDEX(offset) ((offset) - AM3_CLKCTRL_OFFSET)
+
+/* l4_per clocks */
+#define AM3_L4_PER_CLKCTRL_OFFSET 0x14
+#define AM3_L4_PER_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_PER_CLKCTRL_OFFSET)
+#define AM3_CPGMAC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14)
+#define AM3_LCDC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x18)
+#define AM3_USB_OTG_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x1c)
+#define AM3_TPTC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x24)
+#define AM3_EMIF_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x28)
+#define AM3_OCMCRAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x2c)
+#define AM3_GPMC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x30)
+#define AM3_MCASP0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x34)
+#define AM3_UART6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x38)
+#define AM3_MMC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x3c)
+#define AM3_ELM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x40)
+#define AM3_I2C3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x44)
+#define AM3_I2C2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x48)
+#define AM3_SPI0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x4c)
+#define AM3_SPI1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x50)
+#define AM3_L4_LS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x60)
+#define AM3_MCASP1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x68)
+#define AM3_UART2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x6c)
+#define AM3_UART3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x70)
+#define AM3_UART4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x74)
+#define AM3_UART5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x78)
+#define AM3_TIMER7_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x7c)
+#define AM3_TIMER2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x80)
+#define AM3_TIMER3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x84)
+#define AM3_TIMER4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x88)
+#define AM3_RNG_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x90)
+#define AM3_AES_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x94)
+#define AM3_SHAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xa0)
+#define AM3_GPIO2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xac)
+#define AM3_GPIO3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb0)
+#define AM3_GPIO4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb4)
+#define AM3_TPCC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xbc)
+#define AM3_D_CAN0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc0)
+#define AM3_D_CAN1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc4)
+#define AM3_EPWMSS1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xcc)
+#define AM3_EPWMSS0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd4)
+#define AM3_EPWMSS2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd8)
+#define AM3_L3_INSTR_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xdc)
+#define AM3_L3_MAIN_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe0)
+#define AM3_PRUSS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe8)
+#define AM3_TIMER5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xec)
+#define AM3_TIMER6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf0)
+#define AM3_MMC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf4)
+#define AM3_MMC3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf8)
+#define AM3_TPTC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xfc)
+#define AM3_TPTC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x100)
+#define AM3_SPINLOCK_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x10c)
+#define AM3_MAILBOX_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x110)
+#define AM3_L4_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x120)
+#define AM3_OCPWP_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x130)
+#define AM3_CLKDIV32K_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14c)
+
+/* l4_wkup clocks */
+#define AM3_L4_WKUP_CLKCTRL_OFFSET 0x4
+#define AM3_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_CLKCTRL_OFFSET)
+#define AM3_CONTROL_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x4)
+#define AM3_GPIO1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x8)
+#define AM3_L4_WKUP_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc)
+#define AM3_DEBUGSS_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x14)
+#define AM3_WKUP_M3_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb0)
+#define AM3_UART1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb4)
+#define AM3_I2C1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb8)
+#define AM3_ADC_TSC_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xbc)
+#define AM3_SMARTREFLEX0_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc0)
+#define AM3_TIMER1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc4)
+#define AM3_SMARTREFLEX1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc8)
+#define AM3_WD_TIMER2_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xd4)
+
+/* mpu clocks */
+#define AM3_MPU_CLKCTRL_OFFSET 0x4
+#define AM3_MPU_CLKCTRL_INDEX(offset) ((offset) - AM3_MPU_CLKCTRL_OFFSET)
+#define AM3_MPU_CLKCTRL AM3_MPU_CLKCTRL_INDEX(0x4)
+
+/* l4_rtc clocks */
+#define AM3_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0)
+
+/* gfx_l3 clocks */
+#define AM3_GFX_L3_CLKCTRL_OFFSET 0x4
+#define AM3_GFX_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_GFX_L3_CLKCTRL_OFFSET)
+#define AM3_GFX_CLKCTRL AM3_GFX_L3_CLKCTRL_INDEX(0x4)
+
+/* l4_cefuse clocks */
+#define AM3_L4_CEFUSE_CLKCTRL_OFFSET 0x20
+#define AM3_L4_CEFUSE_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_CEFUSE_CLKCTRL_OFFSET)
+#define AM3_CEFUSE_CLKCTRL AM3_L4_CEFUSE_CLKCTRL_INDEX(0x20)
+
+#endif
diff --git a/include/dt-bindings/clock/am4.h b/include/dt-bindings/clock/am4.h
new file mode 100644
index 000000000000..d21df00b3270
--- /dev/null
+++ b/include/dt-bindings/clock/am4.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright 2017 Texas Instruments, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_CLK_AM4_H
+#define __DT_BINDINGS_CLK_AM4_H
+
+#define AM4_CLKCTRL_OFFSET 0x20
+#define AM4_CLKCTRL_INDEX(offset) ((offset) - AM4_CLKCTRL_OFFSET)
+
+/* l4_wkup clocks */
+#define AM4_ADC_TSC_CLKCTRL AM4_CLKCTRL_INDEX(0x120)
+#define AM4_L4_WKUP_CLKCTRL AM4_CLKCTRL_INDEX(0x220)
+#define AM4_WKUP_M3_CLKCTRL AM4_CLKCTRL_INDEX(0x228)
+#define AM4_COUNTER_32K_CLKCTRL AM4_CLKCTRL_INDEX(0x230)
+#define AM4_TIMER1_CLKCTRL AM4_CLKCTRL_INDEX(0x328)
+#define AM4_WD_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x338)
+#define AM4_I2C1_CLKCTRL AM4_CLKCTRL_INDEX(0x340)
+#define AM4_UART1_CLKCTRL AM4_CLKCTRL_INDEX(0x348)
+#define AM4_SMARTREFLEX0_CLKCTRL AM4_CLKCTRL_INDEX(0x350)
+#define AM4_SMARTREFLEX1_CLKCTRL AM4_CLKCTRL_INDEX(0x358)
+#define AM4_CONTROL_CLKCTRL AM4_CLKCTRL_INDEX(0x360)
+#define AM4_GPIO1_CLKCTRL AM4_CLKCTRL_INDEX(0x368)
+
+/* mpu clocks */
+#define AM4_MPU_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
+
+/* gfx_l3 clocks */
+#define AM4_GFX_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
+
+/* l4_rtc clocks */
+#define AM4_RTC_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
+
+/* l4_per clocks */
+#define AM4_L3_MAIN_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
+#define AM4_AES_CLKCTRL AM4_CLKCTRL_INDEX(0x28)
+#define AM4_DES_CLKCTRL AM4_CLKCTRL_INDEX(0x30)
+#define AM4_L3_INSTR_CLKCTRL AM4_CLKCTRL_INDEX(0x40)
+#define AM4_OCMCRAM_CLKCTRL AM4_CLKCTRL_INDEX(0x50)
+#define AM4_SHAM_CLKCTRL AM4_CLKCTRL_INDEX(0x58)
+#define AM4_VPFE0_CLKCTRL AM4_CLKCTRL_INDEX(0x68)
+#define AM4_VPFE1_CLKCTRL AM4_CLKCTRL_INDEX(0x70)
+#define AM4_TPCC_CLKCTRL AM4_CLKCTRL_INDEX(0x78)
+#define AM4_TPTC0_CLKCTRL AM4_CLKCTRL_INDEX(0x80)
+#define AM4_TPTC1_CLKCTRL AM4_CLKCTRL_INDEX(0x88)
+#define AM4_TPTC2_CLKCTRL AM4_CLKCTRL_INDEX(0x90)
+#define AM4_L4_HS_CLKCTRL AM4_CLKCTRL_INDEX(0xa0)
+#define AM4_GPMC_CLKCTRL AM4_CLKCTRL_INDEX(0x220)
+#define AM4_MCASP0_CLKCTRL AM4_CLKCTRL_INDEX(0x238)
+#define AM4_MCASP1_CLKCTRL AM4_CLKCTRL_INDEX(0x240)
+#define AM4_MMC3_CLKCTRL AM4_CLKCTRL_INDEX(0x248)
+#define AM4_QSPI_CLKCTRL AM4_CLKCTRL_INDEX(0x258)
+#define AM4_USB_OTG_SS0_CLKCTRL AM4_CLKCTRL_INDEX(0x260)
+#define AM4_USB_OTG_SS1_CLKCTRL AM4_CLKCTRL_INDEX(0x268)
+#define AM4_PRUSS_CLKCTRL AM4_CLKCTRL_INDEX(0x320)
+#define AM4_L4_LS_CLKCTRL AM4_CLKCTRL_INDEX(0x420)
+#define AM4_D_CAN0_CLKCTRL AM4_CLKCTRL_INDEX(0x428)
+#define AM4_D_CAN1_CLKCTRL AM4_CLKCTRL_INDEX(0x430)
+#define AM4_EPWMSS0_CLKCTRL AM4_CLKCTRL_INDEX(0x438)
+#define AM4_EPWMSS1_CLKCTRL AM4_CLKCTRL_INDEX(0x440)
+#define AM4_EPWMSS2_CLKCTRL AM4_CLKCTRL_INDEX(0x448)
+#define AM4_EPWMSS3_CLKCTRL AM4_CLKCTRL_INDEX(0x450)
+#define AM4_EPWMSS4_CLKCTRL AM4_CLKCTRL_INDEX(0x458)
+#define AM4_EPWMSS5_CLKCTRL AM4_CLKCTRL_INDEX(0x460)
+#define AM4_ELM_CLKCTRL AM4_CLKCTRL_INDEX(0x468)
+#define AM4_GPIO2_CLKCTRL AM4_CLKCTRL_INDEX(0x478)
+#define AM4_GPIO3_CLKCTRL AM4_CLKCTRL_INDEX(0x480)
+#define AM4_GPIO4_CLKCTRL AM4_CLKCTRL_INDEX(0x488)
+#define AM4_GPIO5_CLKCTRL AM4_CLKCTRL_INDEX(0x490)
+#define AM4_GPIO6_CLKCTRL AM4_CLKCTRL_INDEX(0x498)
+#define AM4_HDQ1W_CLKCTRL AM4_CLKCTRL_INDEX(0x4a0)
+#define AM4_I2C2_CLKCTRL AM4_CLKCTRL_INDEX(0x4a8)
+#define AM4_I2C3_CLKCTRL AM4_CLKCTRL_INDEX(0x4b0)
+#define AM4_MAILBOX_CLKCTRL AM4_CLKCTRL_INDEX(0x4b8)
+#define AM4_MMC1_CLKCTRL AM4_CLKCTRL_INDEX(0x4c0)
+#define AM4_MMC2_CLKCTRL AM4_CLKCTRL_INDEX(0x4c8)
+#define AM4_RNG_CLKCTRL AM4_CLKCTRL_INDEX(0x4e0)
+#define AM4_SPI0_CLKCTRL AM4_CLKCTRL_INDEX(0x500)
+#define AM4_SPI1_CLKCTRL AM4_CLKCTRL_INDEX(0x508)
+#define AM4_SPI2_CLKCTRL AM4_CLKCTRL_INDEX(0x510)
+#define AM4_SPI3_CLKCTRL AM4_CLKCTRL_INDEX(0x518)
+#define AM4_SPI4_CLKCTRL AM4_CLKCTRL_INDEX(0x520)
+#define AM4_SPINLOCK_CLKCTRL AM4_CLKCTRL_INDEX(0x528)
+#define AM4_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x530)
+#define AM4_TIMER3_CLKCTRL AM4_CLKCTRL_INDEX(0x538)
+#define AM4_TIMER4_CLKCTRL AM4_CLKCTRL_INDEX(0x540)
+#define AM4_TIMER5_CLKCTRL AM4_CLKCTRL_INDEX(0x548)
+#define AM4_TIMER6_CLKCTRL AM4_CLKCTRL_INDEX(0x550)
+#define AM4_TIMER7_CLKCTRL AM4_CLKCTRL_INDEX(0x558)
+#define AM4_TIMER8_CLKCTRL AM4_CLKCTRL_INDEX(0x560)
+#define AM4_TIMER9_CLKCTRL AM4_CLKCTRL_INDEX(0x568)
+#define AM4_TIMER10_CLKCTRL AM4_CLKCTRL_INDEX(0x570)
+#define AM4_TIMER11_CLKCTRL AM4_CLKCTRL_INDEX(0x578)
+#define AM4_UART2_CLKCTRL AM4_CLKCTRL_INDEX(0x580)
+#define AM4_UART3_CLKCTRL AM4_CLKCTRL_INDEX(0x588)
+#define AM4_UART4_CLKCTRL AM4_CLKCTRL_INDEX(0x590)
+#define AM4_UART5_CLKCTRL AM4_CLKCTRL_INDEX(0x598)
+#define AM4_UART6_CLKCTRL AM4_CLKCTRL_INDEX(0x5a0)
+#define AM4_OCP2SCP0_CLKCTRL AM4_CLKCTRL_INDEX(0x5b8)
+#define AM4_OCP2SCP1_CLKCTRL AM4_CLKCTRL_INDEX(0x5c0)
+#define AM4_EMIF_CLKCTRL AM4_CLKCTRL_INDEX(0x720)
+#define AM4_DSS_CORE_CLKCTRL AM4_CLKCTRL_INDEX(0xa20)
+#define AM4_CPGMAC0_CLKCTRL AM4_CLKCTRL_INDEX(0xb20)
+
+#endif
diff --git a/include/dt-bindings/clock/dm814.h b/include/dt-bindings/clock/dm814.h
new file mode 100644
index 000000000000..0e7099a344e1
--- /dev/null
+++ b/include/dt-bindings/clock/dm814.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2017 Texas Instruments, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_CLK_DM814_H
+#define __DT_BINDINGS_CLK_DM814_H
+
+#define DM814_CLKCTRL_OFFSET 0x0
+#define DM814_CLKCTRL_INDEX(offset) ((offset) - DM814_CLKCTRL_OFFSET)
+
+/* default clocks */
+#define DM814_USB_OTG_HS_CLKCTRL DM814_CLKCTRL_INDEX(0x58)
+
+/* alwon clocks */
+#define DM814_UART1_CLKCTRL DM814_CLKCTRL_INDEX(0x150)
+#define DM814_UART2_CLKCTRL DM814_CLKCTRL_INDEX(0x154)
+#define DM814_UART3_CLKCTRL DM814_CLKCTRL_INDEX(0x158)
+#define DM814_GPIO1_CLKCTRL DM814_CLKCTRL_INDEX(0x15c)
+#define DM814_GPIO2_CLKCTRL DM814_CLKCTRL_INDEX(0x160)
+#define DM814_I2C1_CLKCTRL DM814_CLKCTRL_INDEX(0x164)
+#define DM814_I2C2_CLKCTRL DM814_CLKCTRL_INDEX(0x168)
+#define DM814_WD_TIMER_CLKCTRL DM814_CLKCTRL_INDEX(0x18c)
+#define DM814_MCSPI1_CLKCTRL DM814_CLKCTRL_INDEX(0x190)
+#define DM814_GPMC_CLKCTRL DM814_CLKCTRL_INDEX(0x1d0)
+#define DM814_CPGMAC0_CLKCTRL DM814_CLKCTRL_INDEX(0x1d4)
+#define DM814_MPU_CLKCTRL DM814_CLKCTRL_INDEX(0x1dc)
+#define DM814_RTC_CLKCTRL DM814_CLKCTRL_INDEX(0x1f0)
+#define DM814_TPCC_CLKCTRL DM814_CLKCTRL_INDEX(0x1f4)
+#define DM814_TPTC0_CLKCTRL DM814_CLKCTRL_INDEX(0x1f8)
+#define DM814_TPTC1_CLKCTRL DM814_CLKCTRL_INDEX(0x1fc)
+#define DM814_TPTC2_CLKCTRL DM814_CLKCTRL_INDEX(0x200)
+#define DM814_TPTC3_CLKCTRL DM814_CLKCTRL_INDEX(0x204)
+#define DM814_MMC1_CLKCTRL DM814_CLKCTRL_INDEX(0x21c)
+#define DM814_MMC2_CLKCTRL DM814_CLKCTRL_INDEX(0x220)
+#define DM814_MMC3_CLKCTRL DM814_CLKCTRL_INDEX(0x224)
+
+#endif
diff --git a/include/dt-bindings/clock/dm816.h b/include/dt-bindings/clock/dm816.h
new file mode 100644
index 000000000000..69e8a36d783e
--- /dev/null
+++ b/include/dt-bindings/clock/dm816.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2017 Texas Instruments, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_CLK_DM816_H
+#define __DT_BINDINGS_CLK_DM816_H
+
+#define DM816_CLKCTRL_OFFSET 0x0
+#define DM816_CLKCTRL_INDEX(offset) ((offset) - DM816_CLKCTRL_OFFSET)
+
+/* default clocks */
+#define DM816_USB_OTG_HS_CLKCTRL DM816_CLKCTRL_INDEX(0x58)
+
+/* alwon clocks */
+#define DM816_UART1_CLKCTRL DM816_CLKCTRL_INDEX(0x150)
+#define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154)
+#define DM816_UART3_CLKCTRL DM816_CLKCTRL_INDEX(0x158)
+#define DM816_GPIO1_CLKCTRL DM816_CLKCTRL_INDEX(0x15c)
+#define DM816_GPIO2_CLKCTRL DM816_CLKCTRL_INDEX(0x160)
+#define DM816_I2C1_CLKCTRL DM816_CLKCTRL_INDEX(0x164)
+#define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168)
+#define DM816_TIMER1_CLKCTRL DM816_CLKCTRL_INDEX(0x170)
+#define DM816_TIMER2_CLKCTRL DM816_CLKCTRL_INDEX(0x174)
+#define DM816_TIMER3_CLKCTRL DM816_CLKCTRL_INDEX(0x178)
+#define DM816_TIMER4_CLKCTRL DM816_CLKCTRL_INDEX(0x17c)
+#define DM816_TIMER5_CLKCTRL DM816_CLKCTRL_INDEX(0x180)
+#define DM816_TIMER6_CLKCTRL DM816_CLKCTRL_INDEX(0x184)
+#define DM816_TIMER7_CLKCTRL DM816_CLKCTRL_INDEX(0x188)
+#define DM816_WD_TIMER_CLKCTRL DM816_CLKCTRL_INDEX(0x18c)
+#define DM816_MCSPI1_CLKCTRL DM816_CLKCTRL_INDEX(0x190)
+#define DM816_MAILBOX_CLKCTRL DM816_CLKCTRL_INDEX(0x194)
+#define DM816_SPINBOX_CLKCTRL DM816_CLKCTRL_INDEX(0x198)
+#define DM816_MMC1_CLKCTRL DM816_CLKCTRL_INDEX(0x1b0)
+#define DM816_GPMC_CLKCTRL DM816_CLKCTRL_INDEX(0x1d0)
+#define DM816_DAVINCI_MDIO_CLKCTRL DM816_CLKCTRL_INDEX(0x1d4)
+#define DM816_EMAC1_CLKCTRL DM816_CLKCTRL_INDEX(0x1d8)
+#define DM816_MPU_CLKCTRL DM816_CLKCTRL_INDEX(0x1dc)
+#define DM816_RTC_CLKCTRL DM816_CLKCTRL_INDEX(0x1f0)
+#define DM816_TPCC_CLKCTRL DM816_CLKCTRL_INDEX(0x1f4)
+#define DM816_TPTC0_CLKCTRL DM816_CLKCTRL_INDEX(0x1f8)
+#define DM816_TPTC1_CLKCTRL DM816_CLKCTRL_INDEX(0x1fc)
+#define DM816_TPTC2_CLKCTRL DM816_CLKCTRL_INDEX(0x200)
+#define DM816_TPTC3_CLKCTRL DM816_CLKCTRL_INDEX(0x204)
+
+#endif
diff --git a/include/dt-bindings/clock/dra7.h b/include/dt-bindings/clock/dra7.h
new file mode 100644
index 000000000000..5e1061b15aed
--- /dev/null
+++ b/include/dt-bindings/clock/dra7.h
@@ -0,0 +1,172 @@
+/*
+ * Copyright 2017 Texas Instruments, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_CLK_DRA7_H
+#define __DT_BINDINGS_CLK_DRA7_H
+
+#define DRA7_CLKCTRL_OFFSET 0x20
+#define DRA7_CLKCTRL_INDEX(offset) ((offset) - DRA7_CLKCTRL_OFFSET)
+
+/* mpu clocks */
+#define DRA7_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
+
+/* ipu clocks */
+#define DRA7_IPU_CLKCTRL_OFFSET 0x40
+#define DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - DRA7_IPU_CLKCTRL_OFFSET)
+#define DRA7_MCASP1_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x50)
+#define DRA7_TIMER5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x58)
+#define DRA7_TIMER6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x60)
+#define DRA7_TIMER7_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x68)
+#define DRA7_TIMER8_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x70)
+#define DRA7_I2C5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x78)
+#define DRA7_UART6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x80)
+
+/* rtc clocks */
+#define DRA7_RTC_CLKCTRL_OFFSET 0x40
+#define DRA7_RTC_CLKCTRL_INDEX(offset) ((offset) - DRA7_RTC_CLKCTRL_OFFSET)
+#define DRA7_RTCSS_CLKCTRL DRA7_RTC_CLKCTRL_INDEX(0x44)
+
+/* coreaon clocks */
+#define DRA7_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
+#define DRA7_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
+
+/* l3main1 clocks */
+#define DRA7_L3_MAIN_1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
+#define DRA7_GPMC_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
+#define DRA7_TPCC_CLKCTRL DRA7_CLKCTRL_INDEX(0x70)
+#define DRA7_TPTC0_CLKCTRL DRA7_CLKCTRL_INDEX(0x78)
+#define DRA7_TPTC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
+#define DRA7_VCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
+#define DRA7_VCP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x90)
+
+/* dma clocks */
+#define DRA7_DMA_SYSTEM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
+
+/* emif clocks */
+#define DRA7_DMM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
+
+/* atl clocks */
+#define DRA7_ATL_CLKCTRL_OFFSET 0x0
+#define DRA7_ATL_CLKCTRL_INDEX(offset) ((offset) - DRA7_ATL_CLKCTRL_OFFSET)
+#define DRA7_ATL_CLKCTRL DRA7_ATL_CLKCTRL_INDEX(0x0)
+
+/* l4cfg clocks */
+#define DRA7_L4_CFG_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
+#define DRA7_SPINLOCK_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
+#define DRA7_MAILBOX1_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
+#define DRA7_MAILBOX2_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
+#define DRA7_MAILBOX3_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
+#define DRA7_MAILBOX4_CLKCTRL DRA7_CLKCTRL_INDEX(0x58)
+#define DRA7_MAILBOX5_CLKCTRL DRA7_CLKCTRL_INDEX(0x60)
+#define DRA7_MAILBOX6_CLKCTRL DRA7_CLKCTRL_INDEX(0x68)
+#define DRA7_MAILBOX7_CLKCTRL DRA7_CLKCTRL_INDEX(0x70)
+#define DRA7_MAILBOX8_CLKCTRL DRA7_CLKCTRL_INDEX(0x78)
+#define DRA7_MAILBOX9_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
+#define DRA7_MAILBOX10_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
+#define DRA7_MAILBOX11_CLKCTRL DRA7_CLKCTRL_INDEX(0x90)
+#define DRA7_MAILBOX12_CLKCTRL DRA7_CLKCTRL_INDEX(0x98)
+#define DRA7_MAILBOX13_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0)
+
+/* l3instr clocks */
+#define DRA7_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
+#define DRA7_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
+
+/* dss clocks */
+#define DRA7_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
+#define DRA7_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
+
+/* l3init clocks */
+#define DRA7_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
+#define DRA7_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
+#define DRA7_USB_OTG_SS2_CLKCTRL DRA7_CLKCTRL_INDEX(0x40)
+#define DRA7_USB_OTG_SS3_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
+#define DRA7_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
+#define DRA7_SATA_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
+#define DRA7_PCIE1_CLKCTRL DRA7_CLKCTRL_INDEX(0xb0)
+#define DRA7_PCIE2_CLKCTRL DRA7_CLKCTRL_INDEX(0xb8)
+#define DRA7_GMAC_CLKCTRL DRA7_CLKCTRL_INDEX(0xd0)
+#define DRA7_OCP2SCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0xe0)
+#define DRA7_OCP2SCP3_CLKCTRL DRA7_CLKCTRL_INDEX(0xe8)
+#define DRA7_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0)
+
+/* l4per clocks */
+#define DRA7_L4PER_CLKCTRL_OFFSET 0x0
+#define DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER_CLKCTRL_OFFSET)
+#define DRA7_L4_PER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc)
+#define DRA7_L4_PER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x14)
+#define DRA7_TIMER10_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x28)
+#define DRA7_TIMER11_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x30)
+#define DRA7_TIMER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x38)
+#define DRA7_TIMER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x40)
+#define DRA7_TIMER4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x48)
+#define DRA7_TIMER9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x50)
+#define DRA7_ELM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x58)
+#define DRA7_GPIO2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x60)
+#define DRA7_GPIO3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x68)
+#define DRA7_GPIO4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x70)
+#define DRA7_GPIO5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x78)
+#define DRA7_GPIO6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x80)
+#define DRA7_HDQ1W_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x88)
+#define DRA7_EPWMSS1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x90)
+#define DRA7_EPWMSS2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x98)
+#define DRA7_I2C1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa0)
+#define DRA7_I2C2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa8)
+#define DRA7_I2C3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb0)
+#define DRA7_I2C4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb8)
+#define DRA7_L4_PER1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc0)
+#define DRA7_EPWMSS0_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc4)
+#define DRA7_TIMER13_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc8)
+#define DRA7_TIMER14_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xd0)
+#define DRA7_TIMER15_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xd8)
+#define DRA7_MCSPI1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf0)
+#define DRA7_MCSPI2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf8)
+#define DRA7_MCSPI3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x100)
+#define DRA7_MCSPI4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x108)
+#define DRA7_GPIO7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x110)
+#define DRA7_GPIO8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x118)
+#define DRA7_MMC3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x120)
+#define DRA7_MMC4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x128)
+#define DRA7_TIMER16_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x130)
+#define DRA7_QSPI_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x138)
+#define DRA7_UART1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x140)
+#define DRA7_UART2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x148)
+#define DRA7_UART3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x150)
+#define DRA7_UART4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x158)
+#define DRA7_MCASP2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x160)
+#define DRA7_MCASP3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x168)
+#define DRA7_UART5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x170)
+#define DRA7_MCASP5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x178)
+#define DRA7_MCASP8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x190)
+#define DRA7_MCASP4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x198)
+#define DRA7_AES1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1a0)
+#define DRA7_AES2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1a8)
+#define DRA7_DES_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1b0)
+#define DRA7_RNG_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1c0)
+#define DRA7_SHAM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1c8)
+#define DRA7_UART7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1d0)
+#define DRA7_UART8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1e0)
+#define DRA7_UART9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1e8)
+#define DRA7_DCAN2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1f0)
+#define DRA7_MCASP6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x204)
+#define DRA7_MCASP7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x208)
+
+/* wkupaon clocks */
+#define DRA7_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
+#define DRA7_WD_TIMER2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
+#define DRA7_GPIO1_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
+#define DRA7_TIMER1_CLKCTRL DRA7_CLKCTRL_INDEX(0x40)
+#define DRA7_TIMER12_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
+#define DRA7_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
+#define DRA7_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
+#define DRA7_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
+
+#endif
diff --git a/include/dt-bindings/clock/omap5.h b/include/dt-bindings/clock/omap5.h
new file mode 100644
index 000000000000..f51821a91216
--- /dev/null
+++ b/include/dt-bindings/clock/omap5.h
@@ -0,0 +1,118 @@
+/*
+ * Copyright 2017 Texas Instruments, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_CLK_OMAP5_H
+#define __DT_BINDINGS_CLK_OMAP5_H
+
+#define OMAP5_CLKCTRL_OFFSET 0x20
+#define OMAP5_CLKCTRL_INDEX(offset) ((offset) - OMAP5_CLKCTRL_OFFSET)
+
+/* mpu clocks */
+#define OMAP5_MPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+
+/* dsp clocks */
+#define OMAP5_MMU_DSP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+
+/* abe clocks */
+#define OMAP5_L4_ABE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+#define OMAP5_MCPDM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
+#define OMAP5_DMIC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
+#define OMAP5_MCBSP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48)
+#define OMAP5_MCBSP2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50)
+#define OMAP5_MCBSP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58)
+#define OMAP5_TIMER5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68)
+#define OMAP5_TIMER6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70)
+#define OMAP5_TIMER7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78)
+#define OMAP5_TIMER8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80)
+
+/* l3main1 clocks */
+#define OMAP5_L3_MAIN_1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+
+/* l3main2 clocks */
+#define OMAP5_L3_MAIN_2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+
+/* ipu clocks */
+#define OMAP5_MMU_IPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+
+/* dma clocks */
+#define OMAP5_DMA_SYSTEM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+
+/* emif clocks */
+#define OMAP5_DMM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+#define OMAP5_EMIF1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
+#define OMAP5_EMIF2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
+
+/* l4cfg clocks */
+#define OMAP5_L4_CFG_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+#define OMAP5_SPINLOCK_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
+#define OMAP5_MAILBOX_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
+
+/* l3instr clocks */
+#define OMAP5_L3_MAIN_3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+#define OMAP5_L3_INSTR_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
+
+/* l4per clocks */
+#define OMAP5_TIMER10_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
+#define OMAP5_TIMER11_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
+#define OMAP5_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
+#define OMAP5_TIMER3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40)
+#define OMAP5_TIMER4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48)
+#define OMAP5_TIMER9_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50)
+#define OMAP5_GPIO2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x60)
+#define OMAP5_GPIO3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68)
+#define OMAP5_GPIO4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70)
+#define OMAP5_GPIO5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78)
+#define OMAP5_GPIO6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80)
+#define OMAP5_I2C1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa0)
+#define OMAP5_I2C2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa8)
+#define OMAP5_I2C3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb0)
+#define OMAP5_I2C4_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb8)
+#define OMAP5_L4_PER_CLKCTRL OMAP5_CLKCTRL_INDEX(0xc0)
+#define OMAP5_MCSPI1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0)
+#define OMAP5_MCSPI2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf8)
+#define OMAP5_MCSPI3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x100)
+#define OMAP5_MCSPI4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x108)
+#define OMAP5_GPIO7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x110)
+#define OMAP5_GPIO8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x118)
+#define OMAP5_MMC3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x120)
+#define OMAP5_MMC4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x128)
+#define OMAP5_UART1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x140)
+#define OMAP5_UART2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x148)
+#define OMAP5_UART3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x150)
+#define OMAP5_UART4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x158)
+#define OMAP5_MMC5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x160)
+#define OMAP5_I2C5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x168)
+#define OMAP5_UART5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x170)
+#define OMAP5_UART6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x178)
+
+/* dss clocks */
+#define OMAP5_DSS_CORE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+
+/* l3init clocks */
+#define OMAP5_MMC1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
+#define OMAP5_MMC2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
+#define OMAP5_USB_HOST_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58)
+#define OMAP5_USB_TLL_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68)
+#define OMAP5_SATA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x88)
+#define OMAP5_OCP2SCP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe0)
+#define OMAP5_OCP2SCP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe8)
+#define OMAP5_USB_OTG_SS_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0)
+
+/* wkupaon clocks */
+#define OMAP5_L4_WKUP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+#define OMAP5_WD_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
+#define OMAP5_GPIO1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
+#define OMAP5_TIMER1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40)
+#define OMAP5_COUNTER_32K_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50)
+#define OMAP5_KBD_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78)
+
+#endif
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.