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-rw-r--r--arch/arm/boot/dts/am335x-baltos.dtsi2
-rw-r--r--arch/arm/boot/dts/am335x-guardian.dts376
-rw-r--r--arch/arm/boot/dts/am33xx-clocks.dtsi373
-rw-r--r--arch/arm/boot/dts/am43xx-clocks.dtsi339
-rw-r--r--arch/arm/boot/dts/dra7xx-clocks.dtsi693
-rw-r--r--arch/arm/boot/dts/logicpd-som-lv.dtsi10
-rw-r--r--arch/arm/boot/dts/omap3-beagle-xm.dts2
-rw-r--r--arch/arm/boot/dts/omap4-panda-common.dtsi2
-rw-r--r--arch/arm/boot/dts/omap443x-clocks.dtsi1
-rw-r--r--arch/arm/boot/dts/omap446x-clocks.dtsi2
-rw-r--r--arch/arm/boot/dts/omap44xx-clocks.dtsi173
-rw-r--r--arch/arm/boot/dts/omap5-igep0050.dts2
-rw-r--r--arch/arm/boot/dts/omap5-uevm.dts2
-rw-r--r--arch/arm/boot/dts/omap54xx-clocks.dtsi160
-rw-r--r--drivers/iommu/omap-iommu.c2
15 files changed, 1583 insertions, 556 deletions
diff --git a/arch/arm/boot/dts/am335x-baltos.dtsi b/arch/arm/boot/dts/am335x-baltos.dtsi
index 366702630290..d3eafee79a23 100644
--- a/arch/arm/boot/dts/am335x-baltos.dtsi
+++ b/arch/arm/boot/dts/am335x-baltos.dtsi
@@ -285,7 +285,7 @@
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
regulator-name = "vdd_mpu";
regulator-min-microvolt = <912500>;
- regulator-max-microvolt = <1312500>;
+ regulator-max-microvolt = <1351500>;
regulator-boot-on;
regulator-always-on;
};
diff --git a/arch/arm/boot/dts/am335x-guardian.dts b/arch/arm/boot/dts/am335x-guardian.dts
index 1918766c1f80..1a7e187b1953 100644
--- a/arch/arm/boot/dts/am335x-guardian.dts
+++ b/arch/arm/boot/dts/am335x-guardian.dts
@@ -29,39 +29,44 @@
reg = <0x80000000 0x10000000>; /* 256 MB */
};
- gpio_keys {
+ guardian_buttons: gpio-keys {
+ pinctrl-names = "default";
+ pinctrl-0 = <&guardian_button_pins>;
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&gpio_keys_pins>;
- button21 {
+ select-button {
+ label = "guardian-select-button";
+ linux,code = <KEY_5>;
+ gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
+ wakeup-source;
+ };
+
+ power-button {
label = "guardian-power-button";
linux,code = <KEY_POWER>;
- gpios = <&gpio2 21 0>;
+ gpios = <&gpio2 21 GPIO_ACTIVE_LOW>;
wakeup-source;
};
};
- leds {
- compatible = "gpio-leds";
+ guardian_leds: gpio-leds {
pinctrl-names = "default";
- pinctrl-0 = <&leds_pins>;
+ pinctrl-0 = <&guardian_led_pins>;
+ compatible = "gpio-leds";
- led1 {
- label = "green:heartbeat";
- gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
+ life-led {
+ label = "guardian:life-led";
+ gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
default-state = "off";
};
+ };
- led2 {
- label = "green:mmc0";
- gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "mmc0";
- default-state = "off";
- };
+ gpio-poweroff {
+ compatible = "gpio-poweroff";
+ gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
};
panel {
@@ -100,20 +105,36 @@
};
- pwm7: dmtimer-pwm {
+ guardian_beeper: dmtimer-pwm@7 {
compatible = "ti,omap-dmtimer-pwm";
ti,timers = <&timer7>;
pinctrl-names = "default";
- pinctrl-0 = <&dmtimer7_pins>;
+ pinctrl-0 = <&guardian_beeper_pins>;
ti,clock-source = <0x01>;
};
- vmmcsd_fixed: regulator-3v3 {
+ vmmcsd_fixed: fixedregulator0 {
compatible = "regulator-fixed";
regulator-name = "vmmcsd_fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
+
+ mt_keypad: mt_keypad@0 {
+ compatible = "gpio-mt-keypad";
+ debounce-delay-ms = <10>;
+ col-scan-delay-us = <2>;
+ keypad,num-lines = <5>;
+ linux,no-autorepeat;
+ gpio-activelow;
+ line-gpios = <
+ &gpio1 24 GPIO_ACTIVE_LOW /*gpio_56*/
+ &gpio1 23 GPIO_ACTIVE_LOW /*gpio_55*/
+ &gpio1 22 GPIO_ACTIVE_LOW /*gpio_54*/
+ &gpio1 20 GPIO_ACTIVE_LOW /*gpio_52*/
+ &gpio1 16 GPIO_ACTIVE_LOW /*gpio_48*/
+ >;
+ };
};
&elm {
@@ -133,28 +154,29 @@
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
+ ti,nand-xfer-type = "prefetch-dma";
ti,nand-ecc-opt = "bch16";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
gpmc,device-width = <1>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
- gpmc,cs-rd-off-ns = <44>;
- gpmc,cs-wr-off-ns = <44>;
- gpmc,adv-on-ns = <6>;
- gpmc,adv-rd-off-ns = <34>;
- gpmc,adv-wr-off-ns = <44>;
+ gpmc,cs-rd-off-ns = <30>;
+ gpmc,cs-wr-off-ns = <30>;
+ gpmc,adv-on-ns = <0>;
+ gpmc,adv-rd-off-ns = <30>;
+ gpmc,adv-wr-off-ns = <30>;
gpmc,we-on-ns = <0>;
- gpmc,we-off-ns = <40>;
- gpmc,oe-on-ns = <0>;
- gpmc,oe-off-ns = <54>;
- gpmc,access-ns = <64>;
- gpmc,rd-cycle-ns = <82>;
- gpmc,wr-cycle-ns = <82>;
+ gpmc,we-off-ns = <15>;
+ gpmc,oe-on-ns = <1>;
+ gpmc,oe-off-ns = <15>;
+ gpmc,access-ns = <30>;
+ gpmc,rd-cycle-ns = <30>;
+ gpmc,wr-cycle-ns = <30>;
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
- gpmc,wr-access-ns = <40>;
+ gpmc,wr-access-ns = <0>;
gpmc,wr-data-mux-bus-ns = <0>;
/*
@@ -198,18 +220,33 @@
};
partition@6 {
- label = "u-boot-env";
- reg = <0x300000 0x40000>;
+ label = "u-boot-2";
+ reg = <0x300000 0x100000>;
};
partition@7 {
- label = "u-boot-env.backup1";
- reg = <0x340000 0x40000>;
+ label = "u-boot-2.backup1";
+ reg = <0x400000 0x100000>;
};
partition@8 {
+ label = "u-boot-env";
+ reg = <0x500000 0x40000>;
+ };
+
+ partition@9 {
+ label = "u-boot-env.backup1";
+ reg = <0x540000 0x40000>;
+ };
+
+ partition@10 {
+ label = "splash-screen";
+ reg = <0x580000 0x40000>;
+ };
+
+ partition@11 {
label = "UBI";
- reg = <0x380000 0x1fc80000>;
+ reg = <0x5c0000 0x1fa40000>;
};
};
};
@@ -228,6 +265,11 @@
&lcdc {
blue-and-red-wiring = "crossed";
status = "okay";
+ port {
+ lcdc_0: endpoint@0 {
+ remote-endpoint = <0>;
+ };
+ };
};
&mmc1 {
@@ -242,7 +284,6 @@
&rtc {
clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
- system-power-controller;
};
&spi0 {
@@ -255,14 +296,34 @@
#include "tps65217.dtsi"
&tps {
+ /*
+ * Configure pmic to enter OFF-state instead of SLEEP-state ("RTC-only
+ * mode") at poweroff. Most BeagleBone versions do not support RTC-only
+ * mode and risk hardware damage if this mode is entered.
+ *
+ * For details, see linux-omap mailing list May 2015 thread
+ * [PATCH] ARM: dts: am335x-bone* enable pmic-shutdown-controller
+ * In particular, messages:
+ * http://www.spinics.net/lists/linux-omap/msg118585.html
+ * http://www.spinics.net/lists/linux-omap/msg118615.html
+ *
+ * You can override this later with
+ * &tps { /delete-property/ ti,pmic-shutdown-controller; }
+ * if you want to use RTC-only mode and made sure you are not affected
+ * by the hardware problems. (Tip: double-check by performing a current
+ * measurement after shutdown: it should be less than 1 mA.)
+ */
ti,pmic-shutdown-controller;
interrupt-parent = <&intc>;
interrupts = <7>; /* NMI */
backlight {
isel = <1>; /* 1 - ISET1, 2 ISET2 */
- fdim = <100>; /* TPS65217_BL_FDIM_100HZ */
- default-brightness = <100>;
+ fdim = <500>; /* TPS65217_BL_FDIM_500HZ */
+ default-brightness = <50>;
+ /* 1(on) - enable current sink, while initialization */
+ /* 0(off) - disable current sink, while initialization */
+ isink-en = <1>;
};
regulators {
@@ -272,6 +333,7 @@
};
dcdc2_reg: regulator@1 {
+ /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
regulator-name = "vdd_mpu";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <1351500>;
@@ -280,6 +342,7 @@
};
dcdc3_reg: regulator@2 {
+ /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
regulator-name = "vdd_core";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <1150000>;
@@ -319,171 +382,364 @@
};
};
+&gpio0 {
+ gpio-line-names =
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "MirxWakeup",
+ "",
+ "";
+};
+
+&gpio3 {
+ ti,gpio-always-on;
+ ti,no-reset-on-init;
+ gpio-line-names =
+ "",
+ "MirxBtReset",
+ "",
+ "CcVolAdcEn",
+ "MirxBlePause",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "AspEn",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "BatVolAdcEn",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "okay";
+};
+
&usb0 {
dr_mode = "peripheral";
};
&usb1 {
dr_mode = "host";
+ /delete-property/dmas;
+ /delete-property/dma-names;
};
&am33xx_pinmux {
pinctrl-names = "default";
- pinctrl-0 = <&clkout2_pin &gpio_pins>;
+ pinctrl-0 = <&clkout2_pin &guardian_interface_pins>;
clkout2_pin: pinmux_clkout2_pin {
pinctrl-single,pins = <
+ /* xdma_event_intr1.clkout2 */
AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3)
>;
};
- dmtimer7_pins: pinmux_dmtimer7_pins {
+ guardian_interface_pins: pinmux_interface_pins {
pinctrl-single,pins = <
- AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE5)
+ /* ADC_BATSENSE_EN */
+ /* (A14) MCASP0_AHCLKx.gpio3[21] */
+ AM33XX_IOPAD(0x9ac, PIN_OUTPUT_PULLDOWN | MUX_MODE7 )
+ /* ADC_COINCELL_EN */
+ /* (J16) MII1_TX_EN.gpio3[3] */
+ AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE7 )
+ /* ASP_ENABLE */
+ /* (A13) MCASP0_ACLKx.gpio3[14] */
+ AM33XX_IOPAD(0x990, PIN_OUTPUT_PULLUP | MUX_MODE7)
+ /* (D16) uart1_rxd.uart1_rxd */
+ AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE7)
+ /* (D15) uart1_txd.uart1_txd */
+ AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE7)
+ /*SWITCH-OFF_3V6*/
+ /* (M18) gpio0[1] */
+ AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE7)
+ /* MIRACULIX */
+ /* (H17) gmii1_crs.gpio3[1] */
+ AM33XX_IOPAD(0x90c, PIN_OUTPUT_PULLDOWN | MUX_MODE7 )
+ /* (H18) rmii1_refclk.gpio0[29] */
+ AM33XX_IOPAD(0x944, PIN_OUTPUT_PULLDOWN | MUX_MODE7 )
+ /* (J18) gmii1_txd3.gpio0[16] */
+ AM33XX_IOPAD(0x91c, PIN_INPUT | MUX_MODE7 )
+ /* (J17) gmii1_rxdv.gpio3[4] */
+ AM33XX_IOPAD(0x918, PIN_OUTPUT_PULLDOWN | MUX_MODE7 )
>;
};
- gpio_keys_pins: pinmux_gpio_keys_pins {
+ guardian_beeper_pins: pinmux_dmtimer7_pins {
pinctrl-single,pins = <
- AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE5) /* (E18) timer7 */
>;
};
- gpio_pins: pinmux_gpio_pins {
+ guardian_button_pins: pinmux_guardian_button_pins {
pinctrl-single,pins = <
- AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE7)
- AM33XX_IOPAD(0x990, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE7) /* (M16) gmii1_rxd0.gpio2[21] */
+ AM33XX_IOPAD(0x884, PIN_INPUT | MUX_MODE7) /* (V9) gpmc_csn2.gpio1[31] */
>;
};
+
i2c0_pins: pinmux_i2c0_pins {
pinctrl-single,pins = <
- AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)
- AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)
+ AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
+ AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
+ >;
+ };
+
+ led_bl_pins: gpio_led_bl_pins {
+ pinctrl-single,pins = <
+ /* P9_14, gpmc_a[2].GPIO1[18] (backlight control) */
+ AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE7)
>;
};
lcd_disen_pins: pinmux_lcd_disen_pins {
pinctrl-single,pins = <
+ /* P9_27, mcasp0_fsr.gpio3[19] (lcd_disen) */
AM33XX_IOPAD(0x9a4, PIN_OUTPUT_PULLUP | SLEWCTRL_SLOW | MUX_MODE7)
>;
};
lcd_pins_default: pinmux_lcd_pins_default {
pinctrl-single,pins = <
+ /* (U10) gpmc_ad8.lcd_data23 */
AM33XX_IOPAD(0x820, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
+ /* (T10) gpmc_ad9.lcd_data22 */
AM33XX_IOPAD(0x824, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
+ /* (T11) gpmc_ad10.lcd_data21 */
AM33XX_IOPAD(0x828, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
+ /* (U12) gpmc_ad11.lcd_data20 */
AM33XX_IOPAD(0x82c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
+ /* (T12) gpmc_ad12.lcd_data19 */
AM33XX_IOPAD(0x830, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
+ /* (R12) gpmc_ad13.lcd_data18 */
AM33XX_IOPAD(0x834, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
+ /* (V13) gpmc_ad14.lcd_data17 */
AM33XX_IOPAD(0x838, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
+ /* (U13) gpmc_ad15.lcd_data16 */
AM33XX_IOPAD(0x83c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
+ /* lcd_data0.lcd_data0 */
AM33XX_IOPAD(0x8a0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data1.lcd_data1 */
AM33XX_IOPAD(0x8a4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data2.lcd_data2 */
AM33XX_IOPAD(0x8a8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data3.lcd_data3 */
AM33XX_IOPAD(0x8ac, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data4.lcd_data4 */
AM33XX_IOPAD(0x8b0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data5.lcd_data5 */
AM33XX_IOPAD(0x8b4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data6.lcd_data6 */
AM33XX_IOPAD(0x8b8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data7.lcd_data7 */
AM33XX_IOPAD(0x8bc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data8.lcd_data8 */
AM33XX_IOPAD(0x8c0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data9.lcd_data9 */
AM33XX_IOPAD(0x8c4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data10.lcd_data10 */
AM33XX_IOPAD(0x8c8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data11.lcd_data11 */
AM33XX_IOPAD(0x8cc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data12.lcd_data12 */
AM33XX_IOPAD(0x8d0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data13.lcd_data13 */
AM33XX_IOPAD(0x8d4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data14.lcd_data14 */
AM33XX_IOPAD(0x8d8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data15.lcd_data15 */
AM33XX_IOPAD(0x8dc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_vsync.lcd_vsync */
AM33XX_IOPAD(0x8e0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_hsync.lcd_hsync */
AM33XX_IOPAD(0x8e4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_pclk.lcd_pclk */
AM33XX_IOPAD(0x8e8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_ac_bias_en.lcd_ac_bias_en */
AM33XX_IOPAD(0x8ec, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
>;
};
lcd_pins_sleep: pinmux_lcd_pins_sleep {
pinctrl-single,pins = <
+ /* lcd_data0.lcd_data0 */
AM33XX_IOPAD(0x8a0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data1.lcd_data1 */
AM33XX_IOPAD(0x8a4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data2.lcd_data2 */
AM33XX_IOPAD(0x8a8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data3.lcd_data3 */
AM33XX_IOPAD(0x8ac, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data4.lcd_data4 */
AM33XX_IOPAD(0x8b0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data5.lcd_data5 */
AM33XX_IOPAD(0x8b4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data6.lcd_data6 */
AM33XX_IOPAD(0x8b8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data7.lcd_data7 */
AM33XX_IOPAD(0x8bc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data8.lcd_data8 */
AM33XX_IOPAD(0x8c0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data9.lcd_data9 */
AM33XX_IOPAD(0x8c4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data10.lcd_data10 */
AM33XX_IOPAD(0x8c8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data11.lcd_data11 */
AM33XX_IOPAD(0x8cc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data12.lcd_data12 */
AM33XX_IOPAD(0x8d0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data13.lcd_data13 */
AM33XX_IOPAD(0x8d4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data14.lcd_data14 */
AM33XX_IOPAD(0x8d8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data15.lcd_data15 */
AM33XX_IOPAD(0x8dc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_vsync.lcd_vsync */
AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_hsync.lcd_hsync */
AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_pclk.lcd_pclk */
AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_ac_bias_en.lcd_ac_bias_en */
AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7)
>;
};
- leds_pins: pinmux_leds_pins {
+ guardian_led_pins: pinmux_guardian_led_pins {
pinctrl-single,pins = <
- AM33XX_IOPAD(0x868, PIN_OUTPUT | MUX_MODE7)
- AM33XX_IOPAD(0x86c, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x868, PIN_OUTPUT | MUX_MODE7) /* (T16) gpmc_a10.gpio1[26] */
>;
};
mmc1_pins: pinmux_mmc1_pins {
pinctrl-single,pins = <
- AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0)
- AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0)
- AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0)
- AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0)
- AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0)
- AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0)
- AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
+ AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
+ AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
+ AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
+ AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
+ AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
+ AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* GPIO0_6 */
>;
};
spi0_pins: pinmux_spi0_pins {
pinctrl-single,pins = <
+ /* SPI0_CLK - spi0_clk.spi */
AM33XX_IOPAD(0x950, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
+ /* SPI0_MOSI - spi0_d0.spi0 */
AM33XX_IOPAD(0x954, PIN_OUTPUT_PULLUP | MUX_MODE0)
+ /* SPI0_MISO - spi0_d1.spi0 */
AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0)
+ /* SPI0_CS0 - spi */
AM33XX_IOPAD(0x95c, PIN_OUTPUT_PULLUP | MUX_MODE0)
>;
};
uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
+ /* uart0_rxd.uart0_rxd */
AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)
+ /* uart0_txd.uart0_txd */
AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
>;
};
+ uart2_pins: pinmux_uart2_pins {
+ pinctrl-single,pins = <
+ /* K18 uart2_rxd.mirx_txd */
+ AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE1)
+ /* L18 uart2_txd.mirx_rxd */
+ AM33XX_IOPAD(0x930, PIN_OUTPUT_PULLDOWN | MUX_MODE1)
+ >;
+ };
+
nandflash_pins: pinmux_nandflash_pins {
pinctrl-single,pins = <
+ /* (U7) gpmc_ad0.gpmc_ad0 */
AM33XX_IOPAD(0x800, PIN_INPUT | MUX_MODE0)
+ /* (V7) gpmc_ad1.gpmc_ad1 */
AM33XX_IOPAD(0x804, PIN_INPUT | MUX_MODE0)
+ /* (R8) gpmc_ad2.gpmc_ad2 */
AM33XX_IOPAD(0x808, PIN_INPUT | MUX_MODE0)
+ /* (T8) gpmc_ad3.gpmc_ad3 */
AM33XX_IOPAD(0x80c, PIN_INPUT | MUX_MODE0)
+ /* (U8) gpmc_ad4.gpmc_ad4 */
AM33XX_IOPAD(0x810, PIN_INPUT | MUX_MODE0)
+ /* (V8) gpmc_ad5.gpmc_ad5 */
AM33XX_IOPAD(0x814, PIN_INPUT | MUX_MODE0)
+ /* (R9) gpmc_ad6.gpmc_ad6 */
AM33XX_IOPAD(0x818, PIN_INPUT | MUX_MODE0)
+ /* (T9) gpmc_ad7.gpmc_ad7 */
AM33XX_IOPAD(0x81c, PIN_INPUT | MUX_MODE0)
+ /* (T17) gpmc_wait0.gpmc_wait0 */
AM33XX_IOPAD(0x870, PIN_INPUT | MUX_MODE0)
+ /* (U17) gpmc_wpn.gpmc_wpn */
AM33XX_IOPAD(0x874, PIN_OUTPUT | MUX_MODE0)
+ /* (V6) gpmc_csn0.gpmc_csn0 */
AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0)
+ /* (R7) gpmc_advn_ale.gpmc_advn_ale */
AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0)
+ /* (T7) gpmc_oen_ren.gpmc_oen_ren */
AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0)
+ /* (U6) gpmc_wen.gpmc_wen */
AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0)
+ /* (T6) gpmc_be0n_cle.gpmc_be0n_cle */
AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0)
>;
};
diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi
index b7b7106f2dee..d34483ae1778 100644
--- a/arch/arm/boot/dts/am33xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
@@ -5,251 +5,288 @@
* Copyright (C) 2013 Texas Instruments, Inc.
*/
&scm_clocks {
- sys_clkin_ck: sys_clkin_ck@40 {
+ sys_clkin_ck: clock-sys-clkin-22@40 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "sys_clkin_ck";
clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
ti,bit-shift = <22>;
reg = <0x0040>;
};
- adc_tsc_fck: adc_tsc_fck {
+ adc_tsc_fck: clock-adc-tsc-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "adc_tsc_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dcan0_fck: dcan0_fck {
+ dcan0_fck: clock-dcan0-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dcan0_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dcan1_fck: dcan1_fck {
+ dcan1_fck: clock-dcan1-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dcan1_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- mcasp0_fck: mcasp0_fck {
+ mcasp0_fck: clock-mcasp0-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "mcasp0_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- mcasp1_fck: mcasp1_fck {
+ mcasp1_fck: clock-mcasp1-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "mcasp1_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- smartreflex0_fck: smartreflex0_fck {
+ smartreflex0_fck: clock-smartreflex0-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "smartreflex0_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- smartreflex1_fck: smartreflex1_fck {
+ smartreflex1_fck: clock-smartreflex1-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "smartreflex1_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- sha0_fck: sha0_fck {
+ sha0_fck: clock-sha0-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "sha0_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- aes0_fck: aes0_fck {
+ aes0_fck: clock-aes0-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "aes0_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- rng_fck: rng_fck {
+ rng_fck: clock-rng-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "rng_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l4ls_gclk>;
- ti,bit-shift = <0>;
- reg = <0x0664>;
- };
+ clock@664 {
+ compatible = "ti,clksel";
+ reg = <0x664>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
- ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l4ls_gclk>;
- ti,bit-shift = <1>;
- reg = <0x0664>;
- };
+ ehrpwm0_tbclk: clock-ehrpwm0-tbclk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clock-output-names = "ehrpwm0_tbclk";
+ clocks = <&l4ls_gclk>;
+ ti,bit-shift = <0>;
+ };
- ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l4ls_gclk>;
- ti,bit-shift = <2>;
- reg = <0x0664>;
+ ehrpwm1_tbclk: clock-ehrpwm1-tbclk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clock-output-names = "ehrpwm1_tbclk";
+ clocks = <&l4ls_gclk>;
+ ti,bit-shift = <1>;
+ };
+
+ ehrpwm2_tbclk: clock-ehrpwm2-tbclk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clock-output-names = "ehrpwm2_tbclk";
+ clocks = <&l4ls_gclk>;
+ ti,bit-shift = <2>;
+ };
};
};
&prcm_clocks {
- clk_32768_ck: clk_32768_ck {
+ clk_32768_ck: clock-clk-32768 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "clk_32768_ck";
clock-frequency = <32768>;
};
- clk_rc32k_ck: clk_rc32k_ck {
+ clk_rc32k_ck: clock-clk-rc32k {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "clk_rc32k_ck";
clock-frequency = <32000>;
};
- virt_19200000_ck: virt_19200000_ck {
+ virt_19200000_ck: clock-virt-19200000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_19200000_ck";
clock-frequency = <19200000>;
};
- virt_24000000_ck: virt_24000000_ck {
+ virt_24000000_ck: clock-virt-24000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_24000000_ck";
clock-frequency = <24000000>;
};
- virt_25000000_ck: virt_25000000_ck {
+ virt_25000000_ck: clock-virt-25000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_25000000_ck";
clock-frequency = <25000000>;
};
- virt_26000000_ck: virt_26000000_ck {
+ virt_26000000_ck: clock-virt-26000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_26000000_ck";
clock-frequency = <26000000>;
};
- tclkin_ck: tclkin_ck {
+ tclkin_ck: clock-tclkin {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "tclkin_ck";
clock-frequency = <12000000>;
};
- dpll_core_ck: dpll_core_ck@490 {
+ dpll_core_ck: clock@490 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-core-clock";
+ clock-output-names = "dpll_core_ck";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x0490>, <0x045c>, <0x0468>, <0x0460>, <0x0464>;
};
- dpll_core_x2_ck: dpll_core_x2_ck {
+ dpll_core_x2_ck: clock-dpll-core-x2 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-x2-clock";
+ clock-output-names = "dpll_core_x2_ck";
clocks = <&dpll_core_ck>;
};
- dpll_core_m4_ck: dpll_core_m4_ck@480 {
+ dpll_core_m4_ck: clock-dpll-core-m4@480 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m4_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <31>;
reg = <0x0480>;
ti,index-starts-at-one;
};
- dpll_core_m5_ck: dpll_core_m5_ck@484 {
+ dpll_core_m5_ck: clock-dpll-core-m5@484 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m5_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <31>;
reg = <0x0484>;
ti,index-starts-at-one;
};
- dpll_core_m6_ck: dpll_core_m6_ck@4d8 {
+ dpll_core_m6_ck: clock-dpll-core-m6@4d8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m6_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <31>;
reg = <0x04d8>;
ti,index-starts-at-one;
};
- dpll_mpu_ck: dpll_mpu_ck@488 {
+ dpll_mpu_ck: clock@488 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
+ clock-output-names = "dpll_mpu_ck";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>;
};
- dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 {
+ dpll_mpu_m2_ck: clock-dpll-mpu-m2@4a8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_mpu_m2_ck";
clocks = <&dpll_mpu_ck>;
ti,max-div = <31>;
reg = <0x04a8>;
ti,index-starts-at-one;
};
- dpll_ddr_ck: dpll_ddr_ck@494 {
+ dpll_ddr_ck: clock@494 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-no-gate-clock";
+ clock-output-names = "dpll_ddr_ck";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x0494>, <0x0434>, <0x0440>, <0x0438>, <0x043c>;
};
- dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 {
+ dpll_ddr_m2_ck: clock-dpll-ddr-m2@4a0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_ddr_m2_ck";
clocks = <&dpll_ddr_ck>;
ti,max-div = <31>;
reg = <0x04a0>;
ti,index-starts-at-one;
};
- dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck {
+ dpll_ddr_m2_div2_ck: clock-dpll-ddr-m2-div2 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dpll_ddr_m2_div2_ck";
clocks = <&dpll_ddr_m2_ck>;
clock-mult = <1>;
clock-div = <2>;
};
- dpll_disp_ck: dpll_disp_ck@498 {
+ dpll_disp_ck: clock@498 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-no-gate-clock";
+ clock-output-names = "dpll_disp_ck";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>;
};
- dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 {
+ dpll_disp_m2_ck: clock-dpll-disp-m2@4a4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_disp_m2_ck";
clocks = <&dpll_disp_ck>;
ti,max-div = <31>;
reg = <0x04a4>;
@@ -257,418 +294,484 @@
ti,set-rate-parent;
};
- dpll_per_ck: dpll_per_ck@48c {
+ dpll_per_ck: clock@48c {
#clock-cells = <0>;
compatible = "ti,am3-dpll-no-gate-j-type-clock";
+ clock-output-names = "dpll_per_ck";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x048c>, <0x0470>, <0x049c>, <0x0474>, <0x0478>;
};
- dpll_per_m2_ck: dpll_per_m2_ck@4ac {
+ dpll_per_m2_ck: clock-dpll-per-m2@4ac {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m2_ck";
clocks = <&dpll_per_ck>;
ti,max-div = <31>;
reg = <0x04ac>;
ti,index-starts-at-one;
};
- dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
+ dpll_per_m2_div4_wkupdm_ck: clock-dpll-per-m2-div4-wkupdm {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dpll_per_m2_div4_wkupdm_ck";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <4>;
};
- dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
+ dpll_per_m2_div4_ck: clock-dpll-per-m2-div4 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dpll_per_m2_div4_ck";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <4>;
};
- clk_24mhz: clk_24mhz {
+ clk_24mhz: clock-clk-24mhz {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "clk_24mhz";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <8>;
};
- clkdiv32k_ck: clkdiv32k_ck {
+ clkdiv32k_ck: clock-clkdiv32k {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "clkdiv32k_ck";
clocks = <&clk_24mhz>;
clock-mult = <1>;
clock-div = <732>;
};
- l3_gclk: l3_gclk {
+ l3_gclk: clock-l3-gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "l3_gclk";
clocks = <&dpll_core_m4_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- pruss_ocp_gclk: pruss_ocp_gclk@530 {
+ pruss_ocp_gclk: clock-pruss-ocp-gclk@530 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "pruss_ocp_gclk";
clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
reg = <0x0530>;
};
- mmu_fck: mmu_fck@914 {
+ mmu_fck: clock-mmu-fck-1@914 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "mmu_fck";
clocks = <&dpll_core_m4_ck>;
ti,bit-shift = <1>;
reg = <0x0914>;
};
- timer1_fck: timer1_fck@528 {
+ timer1_fck: clock-timer1-fck@528 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer1_fck";
clocks = <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
reg = <0x0528>;
};
- timer2_fck: timer2_fck@508 {
+ timer2_fck: clock-timer2-fck@508 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer2_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x0508>;
};
- timer3_fck: timer3_fck@50c {
+ timer3_fck: clock-timer3-fck@50c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer3_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x050c>;
};
- timer4_fck: timer4_fck@510 {
+ timer4_fck: clock-timer4-fck@510 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer4_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x0510>;
};
- timer5_fck: timer5_fck@518 {
+ timer5_fck: clock-timer5-fck@518 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer5_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x0518>;
};
- timer6_fck: timer6_fck@51c {
+ timer6_fck: clock-timer6-fck@51c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer6_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x051c>;
};
- timer7_fck: timer7_fck@504 {
+ timer7_fck: clock-timer7-fck@504 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer7_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x0504>;
};
- usbotg_fck: usbotg_fck@47c {
+ usbotg_fck: clock-usbotg-fck-8@47c {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "usbotg_fck";
clocks = <&dpll_per_ck>;
ti,bit-shift = <8>;
reg = <0x047c>;
};
- dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
+ dpll_core_m4_div2_ck: clock-dpll-core-m4-div2 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dpll_core_m4_div2_ck";
clocks = <&dpll_core_m4_ck>;
clock-mult = <1>;
clock-div = <2>;
};
- ieee5000_fck: ieee5000_fck@e4 {
+ ieee5000_fck: clock-ieee5000-fck-1@e4 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "ieee5000_fck";
clocks = <&dpll_core_m4_div2_ck>;
ti,bit-shift = <1>;
reg = <0x00e4>;
};
- wdt1_fck: wdt1_fck@538 {
+ wdt1_fck: clock-wdt1-fck@538 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "wdt1_fck";
clocks = <&clk_rc32k_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x0538>;
};
- l4_rtc_gclk: l4_rtc_gclk {
+ l4_rtc_gclk: clock-l4-rtc-gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "l4_rtc_gclk";
clocks = <&dpll_core_m4_ck>;
clock-mult = <1>;
clock-div = <2>;
};
- l4hs_gclk: l4hs_gclk {
+ l4hs_gclk: clock-l4hs-gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "l4hs_gclk";
clocks = <&dpll_core_m4_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- l3s_gclk: l3s_gclk {
+ l3s_gclk: clock-l3s-gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "l3s_gclk";
clocks = <&dpll_core_m4_div2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- l4fw_gclk: l4fw_gclk {
+ l4fw_gclk: clock-l4fw-gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "l4fw_gclk";
clocks = <&dpll_core_m4_div2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- l4ls_gclk: l4ls_gclk {
+ l4ls_gclk: clock-l4ls-gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "l4ls_gclk";
clocks = <&dpll_core_m4_div2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- sysclk_div_ck: sysclk_div_ck {
+ sysclk_div_ck: clock-sysclk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "sysclk_div_ck";
clocks = <&dpll_core_m4_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- cpsw_125mhz_gclk: cpsw_125mhz_gclk {
+ cpsw_125mhz_gclk: clock-cpsw-125mhz-gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "cpsw_125mhz_gclk";
clocks = <&dpll_core_m5_ck>;
clock-mult = <1>;
clock-div = <2>;
};
- cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@520 {
+ cpsw_cpts_rft_clk: clock-cpsw-cpts-rft@520 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "cpsw_cpts_rft_clk";
clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
reg = <0x0520>;
};
- gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@53c {
+ gpio0_dbclk_mux_ck: clock-gpio0-dbclk-mux@53c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "gpio0_dbclk_mux_ck";
clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x053c>;
};
- lcd_gclk: lcd_gclk@534 {
+ lcd_gclk: clock-lcd-gclk@534 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "lcd_gclk";
clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
reg = <0x0534>;
ti,set-rate-parent;
};
- mmc_clk: mmc_clk {
+ mmc_clk: clock-mmc {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "mmc_clk";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <2>;
};
- gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@52c {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
- ti,bit-shift = <1>;
- reg = <0x052c>;
- };
+ clock@52c {
+ compatible = "ti,clksel";
+ reg = <0x52c>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
- gfx_fck_div_ck: gfx_fck_div_ck@52c {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&gfx_fclk_clksel_ck>;
- reg = <0x052c>;
- ti,max-div = <2>;
- };
+ gfx_fclk_clksel_ck: clock-gfx-fclk-clksel {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clock-output-names = "gfx_fclk_clksel_ck";
+ clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
+ ti,bit-shift = <1>;
+ };
- sysclkout_pre_ck: sysclkout_pre_ck@700 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
- reg = <0x0700>;
+ gfx_fck_div_ck: clock-gfx-fck-div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clock-output-names = "gfx_fck_div_ck";
+ clocks = <&gfx_fclk_clksel_ck>;
+ ti,max-div = <2>;
+ };
};
- clkout2_div_ck: clkout2_div_ck@700 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&sysclkout_pre_ck>;
- ti,bit-shift = <3>;
- ti,max-div = <8>;
- reg = <0x0700>;
- };
+ clock@700 {
+ compatible = "ti,clksel";
+ reg = <0x700>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
- clkout2_ck: clkout2_ck@700 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&clkout2_div_ck>;
- ti,bit-shift = <7>;
- reg = <0x0700>;
+ sysclkout_pre_ck: clock-sysclkout-pre {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clock-output-names = "sysclkout_pre_ck";
+ clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
+ };
+
+ clkout2_div_ck: clock-clkout2-div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clock-output-names = "clkout2_div_ck";
+ clocks = <&sysclkout_pre_ck>;
+ ti,bit-shift = <3>;
+ ti,max-div = <8>;
+ };
+
+ clkout2_ck: clock-clkout2 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clock-output-names = "clkout2_ck";
+ clocks = <&clkout2_div_ck>;
+ ti,bit-shift = <7>;
+ };
};
};
&prcm {
- per_cm: per-cm@0 {
+ per_cm: clock@0 {
compatible = "ti,omap4-cm";
+ clock-output-names = "per_cm";
reg = <0x0 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0x400>;
- l4ls_clkctrl: l4ls-clkctrl@38 {
+ l4ls_clkctrl: clock@38 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4ls_clkctrl";
reg = <0x38 0x2c>, <0x6c 0x28>, <0xac 0xc>, <0xc0 0x1c>, <0xec 0xc>, <0x10c 0x8>, <0x130 0x4>;
#clock-cells = <2>;
};
- l3s_clkctrl: l3s-clkctrl@1c {
+ l3s_clkctrl: clock@1c {
compatible = "ti,clkctrl";
+ clock-output-names = "l3s_clkctrl";
reg = <0x1c 0x4>, <0x30 0x8>, <0x68 0x4>, <0xf8 0x4>;
#clock-cells = <2>;
};
- l3_clkctrl: l3-clkctrl@24 {
+ l3_clkctrl: clock@24 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3_clkctrl";
reg = <0x24 0xc>, <0x94 0x10>, <0xbc 0x4>, <0xdc 0x8>, <0xfc 0x8>;
#clock-cells = <2>;
};
- l4hs_clkctrl: l4hs-clkctrl@120 {
+ l4hs_clkctrl: clock@120 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4hs_clkctrl";
reg = <0x120 0x4>;
#clock-cells = <2>;
};
- pruss_ocp_clkctrl: pruss-ocp-clkctrl@e8 {
+ pruss_ocp_clkctrl: clock@e8 {
compatible = "ti,clkctrl";
+ clock-output-names = "pruss_ocp_clkctrl";
reg = <0xe8 0x4>;
#clock-cells = <2>;
};
- cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@0 {
+ cpsw_125mhz_clkctrl: clock@0 {
compatible = "ti,clkctrl";
+ clock-output-names = "cpsw_125mhz_clkctrl";
reg = <0x0 0x18>;
#clock-cells = <2>;
};
- lcdc_clkctrl: lcdc-clkctrl@18 {
+ lcdc_clkctrl: clock@18 {
compatible = "ti,clkctrl";
+ clock-output-names = "lcdc_clkctrl";
reg = <0x18 0x4>;
#clock-cells = <2>;
};
- clk_24mhz_clkctrl: clk-24mhz-clkctrl@14c {
+ clk_24mhz_clkctrl: clock@14c {
compatible = "ti,clkctrl";
+ clock-output-names = "clk_24mhz_clkctrl";
reg = <0x14c 0x4>;
#clock-cells = <2>;
};
};
- wkup_cm: wkup-cm@400 {
+ wkup_cm: clock@400 {
compatible = "ti,omap4-cm";
+ clock-output-names = "wkup_cm";
reg = <0x400 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x400 0x100>;
- l4_wkup_clkctrl: l4-wkup-clkctrl@0 {
+ l4_wkup_clkctrl: clock@0 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4_wkup_clkctrl";
reg = <0x0 0x10>, <0xb4 0x24>;
#clock-cells = <2>;
};
- l3_aon_clkctrl: l3-aon-clkctrl@14 {
+ l3_aon_clkctrl: clock@14 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3_aon_clkctrl";
reg = <0x14 0x4>;
#clock-cells = <2>;
};
- l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@b0 {
+ l4_wkup_aon_clkctrl: clock@b0 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4_wkup_aon_clkctrl";
reg = <0xb0 0x4>;
#clock-cells = <2>;
};
};
- mpu_cm: mpu-cm@600 {
+ mpu_cm: clock@600 {
compatible = "ti,omap4-cm";
+ clock-output-names = "mpu_cm";
reg = <0x600 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x600 0x100>;
- mpu_clkctrl: mpu-clkctrl@0 {
+ mpu_clkctrl: clock@0 {
compatible = "ti,clkctrl";
+ clock-output-names = "mpu_clkctrl";
reg = <0x0 0x8>;
#clock-cells = <2>;
};
};
- l4_rtc_cm: l4-rtc-cm@800 {
+ l4_rtc_cm: clock@800 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l4_rtc_cm";
reg = <0x800 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x800 0x100>;
- l4_rtc_clkctrl: l4-rtc-clkctrl@0 {
+ l4_rtc_clkctrl: clock@0 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4_rtc_clkctrl";
reg = <0x0 0x4>;
#clock-cells = <2>;
};
};
- gfx_l3_cm: gfx-l3-cm@900 {
+ gfx_l3_cm: clock@900 {
compatible = "ti,omap4-cm";
+ clock-output-names = "gfx_l3_cm";
reg = <0x900 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x900 0x100>;
- gfx_l3_clkctrl: gfx-l3-clkctrl@0 {
+ gfx_l3_clkctrl: clock@0 {
compatible = "ti,clkctrl";
+ clock-output-names = "gfx_l3_clkctrl";
reg = <0x0 0x8>;
#clock-cells = <2>;
};
};
- l4_cefuse_cm: l4-cefuse-cm@a00 {
+ l4_cefuse_cm: clock@a00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l4_cefuse_cm";
reg = <0xa00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xa00 0x100>;
- l4_cefuse_clkctrl: l4-cefuse-clkctrl@0 {
+ l4_cefuse_clkctrl: clock@0 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4_cefuse_clkctrl";
reg = <0x0 0x24>;
#clock-cells = <2>;
};
diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi
index 66e892fa3398..9a5437b3d6a8 100644
--- a/arch/arm/boot/dts/am43xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -5,217 +5,246 @@
* Copyright (C) 2013 Texas Instruments, Inc.
*/
&scm_clocks {
- sys_clkin_ck: sys_clkin_ck@40 {
+ sys_clkin_ck: clock-sys-clkin-31@40 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "sys_clkin_ck";
clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>;
ti,bit-shift = <31>;
reg = <0x0040>;
};
- crystal_freq_sel_ck: crystal_freq_sel_ck@40 {
+ crystal_freq_sel_ck: clock-crystal-freq-sel-29@40 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "crystal_freq_sel_ck";
clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
ti,bit-shift = <29>;
reg = <0x0040>;
};
- sysboot_freq_sel_ck: sysboot_freq_sel_ck@44e10040 {
+ sysboot_freq_sel_ck: clock-sysboot-freq-sel-22@44e10040 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "sysboot_freq_sel_ck";
clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
ti,bit-shift = <22>;
reg = <0x0040>;
};
- adc_tsc_fck: adc_tsc_fck {
+ adc_tsc_fck: clock-adc-tsc-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "adc_tsc_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dcan0_fck: dcan0_fck {
+ dcan0_fck: clock-dcan0-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dcan0_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dcan1_fck: dcan1_fck {
+ dcan1_fck: clock-dcan1-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dcan1_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- mcasp0_fck: mcasp0_fck {
+ mcasp0_fck: clock-mcasp0-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "mcasp0_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- mcasp1_fck: mcasp1_fck {
+ mcasp1_fck: clock-mcasp1-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "mcasp1_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- smartreflex0_fck: smartreflex0_fck {
+ smartreflex0_fck: clock-smartreflex0-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "smartreflex0_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- smartreflex1_fck: smartreflex1_fck {
+ smartreflex1_fck: clock-smartreflex1-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "smartreflex1_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- sha0_fck: sha0_fck {
+ sha0_fck: clock-sha0-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "sha0_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- aes0_fck: aes0_fck {
+ aes0_fck: clock-aes0-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "aes0_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- rng_fck: rng_fck {
+ rng_fck: clock-rng-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "rng_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- ehrpwm0_tbclk: ehrpwm0_tbclk@664 {
+ ehrpwm0_tbclk: clock-ehrpwm0-tbclk-0@664 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "ehrpwm0_tbclk";
clocks = <&l4ls_gclk>;
ti,bit-shift = <0>;
reg = <0x0664>;
};
- ehrpwm1_tbclk: ehrpwm1_tbclk@664 {
+ ehrpwm1_tbclk: clock-ehrpwm1-tbclk-1@664 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "ehrpwm1_tbclk";
clocks = <&l4ls_gclk>;
ti,bit-shift = <1>;
reg = <0x0664>;
};
- ehrpwm2_tbclk: ehrpwm2_tbclk@664 {
+ ehrpwm2_tbclk: clock-ehrpwm2-tbclk-2@664 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "ehrpwm2_tbclk";
clocks = <&l4ls_gclk>;
ti,bit-shift = <2>;
reg = <0x0664>;
};
- ehrpwm3_tbclk: ehrpwm3_tbclk@664 {
+ ehrpwm3_tbclk: clock-ehrpwm3-tbclk-4@664 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "ehrpwm3_tbclk";
clocks = <&l4ls_gclk>;
ti,bit-shift = <4>;
reg = <0x0664>;
};
- ehrpwm4_tbclk: ehrpwm4_tbclk@664 {
+ ehrpwm4_tbclk: clock-ehrpwm4-tbclk-5@664 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "ehrpwm4_tbclk";
clocks = <&l4ls_gclk>;
ti,bit-shift = <5>;
reg = <0x0664>;
};
- ehrpwm5_tbclk: ehrpwm5_tbclk@664 {
+ ehrpwm5_tbclk: clock-ehrpwm5-tbclk-6@664 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "ehrpwm5_tbclk";
clocks = <&l4ls_gclk>;
ti,bit-shift = <6>;
reg = <0x0664>;
};
};
&prcm_clocks {
- clk_32768_ck: clk_32768_ck {
+ clk_32768_ck: clock-clk-32768 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "clk_32768_ck";
clock-frequency = <32768>;
};
- clk_rc32k_ck: clk_rc32k_ck {
+ clk_rc32k_ck: clock-clk-rc32k {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "clk_rc32k_ck";
clock-frequency = <32768>;
};
- virt_19200000_ck: virt_19200000_ck {
+ virt_19200000_ck: clock-virt-19200000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_19200000_ck";
clock-frequency = <19200000>;
};
- virt_24000000_ck: virt_24000000_ck {
+ virt_24000000_ck: clock-virt-24000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_24000000_ck";
clock-frequency = <24000000>;
};
- virt_25000000_ck: virt_25000000_ck {
+ virt_25000000_ck: clock-virt-25000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_25000000_ck";
clock-frequency = <25000000>;
};
- virt_26000000_ck: virt_26000000_ck {
+ virt_26000000_ck: clock-virt-26000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_26000000_ck";
clock-frequency = <26000000>;
};
- tclkin_ck: tclkin_ck {
+ tclkin_ck: clock-tclkin {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "tclkin_ck";
clock-frequency = <26000000>;
};
- dpll_core_ck: dpll_core_ck@2d20 {
+ dpll_core_ck: clock@2d20 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-core-clock";
+ clock-output-names = "dpll_core_ck";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x2d20>, <0x2d24>, <0x2d2c>, <0x2d48>, <0x2d4c>;
};
- dpll_core_x2_ck: dpll_core_x2_ck {
+ dpll_core_x2_ck: clock-dpll-core-x2 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-x2-clock";
+ clock-output-names = "dpll_core_x2_ck";
clocks = <&dpll_core_ck>;
};
- dpll_core_m4_ck: dpll_core_m4_ck@2d38 {
+ dpll_core_m4_ck: clock-dpll-core-m4-8@2d38 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m4_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -224,9 +253,10 @@
ti,invert-autoidle-bit;
};
- dpll_core_m5_ck: dpll_core_m5_ck@2d3c {
+ dpll_core_m5_ck: clock-dpll-core-m5-8@2d3c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m5_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -235,9 +265,10 @@
ti,invert-autoidle-bit;
};
- dpll_core_m6_ck: dpll_core_m6_ck@2d40 {
+ dpll_core_m6_ck: clock-dpll-core-m6-8@2d40 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m6_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -246,16 +277,18 @@
ti,invert-autoidle-bit;
};
- dpll_mpu_ck: dpll_mpu_ck@2d60 {
+ dpll_mpu_ck: clock@2d60 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
+ clock-output-names = "dpll_mpu_ck";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x2d60>, <0x2d64>, <0x2d6c>, <0x2d88>, <0x2d8c>;
};
- dpll_mpu_m2_ck: dpll_mpu_m2_ck@2d70 {
+ dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@2d70 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_mpu_m2_ck";
clocks = <&dpll_mpu_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -264,24 +297,27 @@
ti,invert-autoidle-bit;
};
- mpu_periphclk: mpu_periphclk {
+ mpu_periphclk: clock-mpu-periphclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "mpu_periphclk";
clocks = <&dpll_mpu_m2_ck>;
clock-mult = <1>;
clock-div = <2>;
};
- dpll_ddr_ck: dpll_ddr_ck@2da0 {
+ dpll_ddr_ck: clock@2da0 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
+ clock-output-names = "dpll_ddr_ck";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x2da0>, <0x2da4>, <0x2dac>, <0x2dc8>, <0x2dcc>;
};
- dpll_ddr_m2_ck: dpll_ddr_m2_ck@2db0 {
+ dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@2db0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_ddr_m2_ck";
clocks = <&dpll_ddr_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -290,16 +326,18 @@
ti,invert-autoidle-bit;
};
- dpll_disp_ck: dpll_disp_ck@2e20 {
+ dpll_disp_ck: clock@2e20 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
+ clock-output-names = "dpll_disp_ck";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x2e20>, <0x2e24>, <0x2e2c>, <0x2e48>, <0x2e4c>;
};
- dpll_disp_m2_ck: dpll_disp_m2_ck@2e30 {
+ dpll_disp_m2_ck: clock-dpll-disp-m2-8@2e30 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_disp_m2_ck";
clocks = <&dpll_disp_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -309,16 +347,18 @@
ti,set-rate-parent;
};
- dpll_per_ck: dpll_per_ck@2de0 {
+ dpll_per_ck: clock@2de0 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-j-type-clock";
+ clock-output-names = "dpll_per_ck";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x2de0>, <0x2de4>, <0x2dec>, <0x2e08>, <0x2e0c>;
};
- dpll_per_m2_ck: dpll_per_m2_ck@2df0 {
+ dpll_per_m2_ck: clock-dpll-per-m2-8@2df0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m2_ck";
clocks = <&dpll_per_ck>;
ti,max-div = <127>;
ti,autoidle-shift = <8>;
@@ -327,119 +367,135 @@
ti,invert-autoidle-bit;
};
- dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
+ dpll_per_m2_div4_wkupdm_ck: clock-dpll-per-m2-div4-wkupdm {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dpll_per_m2_div4_wkupdm_ck";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <4>;
};
- dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
+ dpll_per_m2_div4_ck: clock-dpll-per-m2-div4 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dpll_per_m2_div4_ck";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <4>;
};
- clk_24mhz: clk_24mhz {
+ clk_24mhz: clock-clk-24mhz {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "clk_24mhz";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <8>;
};
- clkdiv32k_ck: clkdiv32k_ck {
+ clkdiv32k_ck: clock-clkdiv32k {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "clkdiv32k_ck";
clocks = <&clk_24mhz>;
clock-mult = <1>;
clock-div = <732>;
};
- clkdiv32k_ick: clkdiv32k_ick@2a38 {
+ clkdiv32k_ick: clock-clkdiv32k-ick-8@2a38 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "clkdiv32k_ick";
clocks = <&clkdiv32k_ck>;
ti,bit-shift = <8>;
reg = <0x2a38>;
};
- sysclk_div: sysclk_div {
+ sysclk_div: clock-sysclk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "sysclk_div";
clocks = <&dpll_core_m4_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- pruss_ocp_gclk: pruss_ocp_gclk@4248 {
+ pruss_ocp_gclk: clock-pruss-ocp-gclk@4248 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "pruss_ocp_gclk";
clocks = <&sysclk_div>, <&dpll_disp_m2_ck>;
reg = <0x4248>;
};
- clk_32k_tpm_ck: clk_32k_tpm_ck {
+ clk_32k_tpm_ck: clock-clk-32k-tpm {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "clk_32k_tpm_ck";
clock-frequency = <32768>;
};
- timer1_fck: timer1_fck@4200 {
+ timer1_fck: clock-timer1-fck@4200 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer1_fck";
clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>;
reg = <0x4200>;
};
- timer2_fck: timer2_fck@4204 {
+ timer2_fck: clock-timer2-fck@4204 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer2_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
reg = <0x4204>;
};
- timer3_fck: timer3_fck@4208 {
+ timer3_fck: clock-timer3-fck@4208 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer3_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
reg = <0x4208>;
};
- timer4_fck: timer4_fck@420c {
+ timer4_fck: clock-timer4-fck@420c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer4_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
reg = <0x420c>;
};
- timer5_fck: timer5_fck@4210 {
+ timer5_fck: clock-timer5-fck@4210 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer5_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
reg = <0x4210>;
};
- timer6_fck: timer6_fck@4214 {
+ timer6_fck: clock-timer6-fck@4214 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer6_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
reg = <0x4214>;
};
- timer7_fck: timer7_fck@4218 {
+ timer7_fck: clock-timer7-fck@4218 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer7_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
reg = <0x4218>;
};
- wdt1_fck: wdt1_fck@422c {
+ wdt1_fck: clock-wdt1-fck@422c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "wdt1_fck";
clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
reg = <0x422c>;
};
@@ -451,125 +507,141 @@
reg = <0x424c>;
};
- l3_gclk: l3_gclk {
+ l3_gclk: clock-l3-gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "l3_gclk";
clocks = <&dpll_core_m4_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
+ dpll_core_m4_div2_ck: clock-dpll-core-m4-div2 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dpll_core_m4_div2_ck";
clocks = <&sysclk_div>;
clock-mult = <1>;
clock-div = <2>;
};
- l4hs_gclk: l4hs_gclk {
+ l4hs_gclk: clock-l4hs-gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "l4hs_gclk";
clocks = <&dpll_core_m4_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- l3s_gclk: l3s_gclk {
+ l3s_gclk: clock-l3s-gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "l3s_gclk";
clocks = <&dpll_core_m4_div2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- l4ls_gclk: l4ls_gclk {
+ l4ls_gclk: clock-l4ls-gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "l4ls_gclk";
clocks = <&dpll_core_m4_div2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- cpsw_125mhz_gclk: cpsw_125mhz_gclk {
+ cpsw_125mhz_gclk: clock-cpsw-125mhz-gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "cpsw_125mhz_gclk";
clocks = <&dpll_core_m5_ck>;
clock-mult = <1>;
clock-div = <2>;
};
- cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@4238 {
+ cpsw_cpts_rft_clk: clock-cpsw-cpts-rft@4238 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "cpsw_cpts_rft_clk";
clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>;
reg = <0x4238>;
};
- dpll_clksel_mac_clk: dpll_clksel_mac_clk@4234 {
+ dpll_clksel_mac_clk: clock-dpll-clksel-mac-2@4234 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_clksel_mac_clk";
clocks = <&dpll_core_m5_ck>;
reg = <0x4234>;
ti,bit-shift = <2>;
ti,dividers = <2>, <5>;
};
- clk_32k_mosc_ck: clk_32k_mosc_ck {
+ clk_32k_mosc_ck: clock-clk-32k-mosc {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "clk_32k_mosc_ck";
clock-frequency = <32768>;
};
- gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@4240 {
+ gpio0_dbclk_mux_ck: clock-gpio0-dbclk-mux@4240 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "gpio0_dbclk_mux_ck";
clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>;
reg = <0x4240>;
};
- mmc_clk: mmc_clk {
+ mmc_clk: clock-mmc {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "mmc_clk";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <2>;
};
- gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@423c {
+ gfx_fclk_clksel_ck: clock-gfx-fclk-clksel-1@423c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "gfx_fclk_clksel_ck";
clocks = <&sysclk_div>, <&dpll_per_m2_ck>;
ti,bit-shift = <1>;
reg = <0x423c>;
};
- gfx_fck_div_ck: gfx_fck_div_ck@423c {
+ gfx_fck_div_ck: clock-gfx-fck-div@423c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "gfx_fck_div_ck";
clocks = <&gfx_fclk_clksel_ck>;
reg = <0x423c>;
ti,max-div = <2>;
};
- disp_clk: disp_clk@4244 {
+ disp_clk: clock-disp@4244 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "disp_clk";
clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
reg = <0x4244>;
ti,set-rate-parent;
};
- dpll_extdev_ck: dpll_extdev_ck@2e60 {
+ dpll_extdev_ck: clock@2e60 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
+ clock-output-names = "dpll_extdev_ck";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x2e60>, <0x2e64>, <0x2e6c>, <0x2e88>, <0x2e8c>;
};
- dpll_extdev_m2_ck: dpll_extdev_m2_ck@2e70 {
+ dpll_extdev_m2_ck: clock-dpll-extdev-m2-8@2e70 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_extdev_m2_ck";
clocks = <&dpll_extdev_ck>;
ti,max-div = <127>;
ti,autoidle-shift = <8>;
@@ -578,66 +650,75 @@
ti,invert-autoidle-bit;
};
- mux_synctimer32k_ck: mux_synctimer32k_ck@4230 {
+ mux_synctimer32k_ck: clock-mux-synctimer32k@4230 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "mux_synctimer32k_ck";
clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>;
reg = <0x4230>;
};
- timer8_fck: timer8_fck@421c {
+ timer8_fck: clock-timer8-fck@421c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer8_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
reg = <0x421c>;
};
- timer9_fck: timer9_fck@4220 {
+ timer9_fck: clock-timer9-fck@4220 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer9_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
reg = <0x4220>;
};
- timer10_fck: timer10_fck@4224 {
+ timer10_fck: clock-timer10-fck@4224 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer10_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
reg = <0x4224>;
};
- timer11_fck: timer11_fck@4228 {
+ timer11_fck: clock-timer11-fck@4228 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer11_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
reg = <0x4228>;
};
- cpsw_50m_clkdiv: cpsw_50m_clkdiv {
+ cpsw_50m_clkdiv: clock-cpsw-50m-clkdiv {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "cpsw_50m_clkdiv";
clocks = <&dpll_core_m5_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- cpsw_5m_clkdiv: cpsw_5m_clkdiv {
+ cpsw_5m_clkdiv: clock-cpsw-5m-clkdiv {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "cpsw_5m_clkdiv";
clocks = <&cpsw_50m_clkdiv>;
clock-mult = <1>;
clock-div = <10>;
};
- dpll_ddr_x2_ck: dpll_ddr_x2_ck {
+ dpll_ddr_x2_ck: clock-dpll-ddr-x2 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-x2-clock";
+ clock-output-names = "dpll_ddr_x2_ck";
clocks = <&dpll_ddr_ck>;
};
- dpll_ddr_m4_ck: dpll_ddr_m4_ck@2db8 {
+ dpll_ddr_m4_ck: clock-dpll-ddr-m4-8@2db8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_ddr_m4_ck";
clocks = <&dpll_ddr_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -646,9 +727,10 @@
ti,invert-autoidle-bit;
};
- dpll_per_clkdcoldo: dpll_per_clkdcoldo@2e14 {
+ dpll_per_clkdcoldo: clock-dpll-per-clkdcoldo-8@2e14 {
#clock-cells = <0>;
compatible = "ti,fixed-factor-clock";
+ clock-output-names = "dpll_per_clkdcoldo";
clocks = <&dpll_per_ck>;
ti,clock-mult = <1>;
ti,clock-div = <1>;
@@ -657,91 +739,102 @@
ti,invert-autoidle-bit;
};
- dll_aging_clk_div: dll_aging_clk_div@4250 {
+ dll_aging_clk_div: clock-dll-aging-clk-div@4250 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dll_aging_clk_div";
clocks = <&sys_clkin_ck>;
reg = <0x4250>;
ti,dividers = <8>, <16>, <32>;
};
- div_core_25m_ck: div_core_25m_ck {
+ div_core_25m_ck: clock-div-core-25m {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "div_core_25m_ck";
clocks = <&sysclk_div>;
clock-mult = <1>;
clock-div = <8>;
};
- func_12m_clk: func_12m_clk {
+ func_12m_clk: clock-func-12m {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_12m_clk";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <16>;
};
- vtp_clk_div: vtp_clk_div {
+ vtp_clk_div: clock-vtp-clk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "vtp_clk_div";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <2>;
};
- usbphy_32khz_clkmux: usbphy_32khz_clkmux@4260 {
+ usbphy_32khz_clkmux: clock-usbphy-32khz-clkmux@4260 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "usbphy_32khz_clkmux";
clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>;
reg = <0x4260>;
};
- usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k@2a40 {
+ usb_phy0_always_on_clk32k: clock-usb-phy0-always-on-clk32k-8@2a40 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "usb_phy0_always_on_clk32k";
clocks = <&usbphy_32khz_clkmux>;
ti,bit-shift = <8>;
reg = <0x2a40>;
};
- usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@2a48 {
+ usb_phy1_always_on_clk32k: clock-usb-phy1-always-on-clk32k-8@2a48 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "usb_phy1_always_on_clk32k";
clocks = <&usbphy_32khz_clkmux>;
ti,bit-shift = <8>;
reg = <0x2a48>;
};
- clkout1_osc_div_ck: clkout1-osc-div-ck {
+ clkout1_osc_div_ck: clock-clkout1-osc-div-ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "clkout1_osc_div_ck";
clocks = <&sys_clkin_ck>;
ti,bit-shift = <20>;
ti,max-div = <4>;
reg = <0x4100>;
};
- clkout1_src2_mux_ck: clkout1-src2-mux-ck {
+ clkout1_src2_mux_ck: clock-clkout1-src2-mux-ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "clkout1_src2_mux_ck";
clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>,
<&dpll_per_m2_ck>, <&dpll_disp_m2_ck>,
<&dpll_mpu_m2_ck>;
reg = <0x4100>;
};
- clkout1_src2_pre_div_ck: clkout1-src2-pre-div-ck {
+ clkout1_src2_pre_div_ck: clock-clkout1-src2-pre-div-ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "clkout1_src2_pre_div_ck";
clocks = <&clkout1_src2_mux_ck>;
ti,bit-shift = <4>;
ti,max-div = <8>;
reg = <0x4100>;
};
- clkout1_src2_post_div_ck: clkout1-src2-post-div-ck {
+ clkout1_src2_post_div_ck: clock-clkout1-src2-post-div-ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "clkout1_src2_post_div_ck";
clocks = <&clkout1_src2_pre_div_ck>;
ti,bit-shift = <8>;
ti,max-div = <32>;
@@ -749,18 +842,20 @@
reg = <0x4100>;
};
- clkout1_mux_ck: clkout1-mux-ck {
+ clkout1_mux_ck: clock-clkout1-mux-ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "clkout1_mux_ck";
clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>,
<&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>;
ti,bit-shift = <16>;
reg = <0x4100>;
};
- clkout1_ck: clkout1-ck {
+ clkout1_ck: clock-clkout1-ck {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "clkout1_ck";
clocks = <&clkout1_mux_ck>;
ti,bit-shift = <23>;
reg = <0x4100>;
@@ -768,120 +863,138 @@
};
&prcm {
- wkup_cm: wkup-cm@2800 {
+ wkup_cm: clock@2800 {
compatible = "ti,omap4-cm";
+ clock-output-names = "wkup_cm";
reg = <0x2800 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x2800 0x400>;
- l3s_tsc_clkctrl: l3s-tsc-clkctrl@120 {
+ l3s_tsc_clkctrl: clock@120 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3s_tsc_clkctrl";
reg = <0x120 0x4>;
#clock-cells = <2>;
};
- l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@228 {
+ l4_wkup_aon_clkctrl: clock@228 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4_wkup_aon_clkctrl";
reg = <0x228 0xc>;
#clock-cells = <2>;
};
- l4_wkup_clkctrl: l4-wkup-clkctrl@220 {
+ l4_wkup_clkctrl: clock@220 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4_wkup_clkctrl";
reg = <0x220 0x4>, <0x328 0x44>;
#clock-cells = <2>;
};
};
- mpu_cm: mpu-cm@8300 {
+ mpu_cm: clock@8300 {
compatible = "ti,omap4-cm";
+ clock-output-names = "mpu_cm";
reg = <0x8300 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8300 0x100>;
- mpu_clkctrl: mpu-clkctrl@20 {
+ mpu_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "mpu_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
- gfx_l3_cm: gfx-l3-cm@8400 {
+ gfx_l3_cm: clock@8400 {
compatible = "ti,omap4-cm";
+ clock-output-names = "gfx_l3_cm";
reg = <0x8400 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8400 0x100>;
- gfx_l3_clkctrl: gfx-l3-clkctrl@20 {
+ gfx_l3_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "gfx_l3_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
- l4_rtc_cm: l4-rtc-cm@8500 {
+ l4_rtc_cm: clock@8500 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l4_rtc_cm";
reg = <0x8500 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8500 0x100>;
- l4_rtc_clkctrl: l4-rtc-clkctrl@20 {
+ l4_rtc_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4_rtc_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
- per_cm: per-cm@8800 {
+ per_cm: clock@8800 {
compatible = "ti,omap4-cm";
+ clock-output-names = "per_cm";
reg = <0x8800 0xc00>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8800 0xc00>;
- l3_clkctrl: l3-clkctrl@20 {
+ l3_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3_clkctrl";
reg = <0x20 0x3c>, <0x78 0x2c>;
#clock-cells = <2>;
};
- l3s_clkctrl: l3s-clkctrl@68 {
+ l3s_clkctrl: clock@68 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3s_clkctrl";
reg = <0x68 0xc>, <0x220 0x4c>;
#clock-cells = <2>;
};
- pruss_ocp_clkctrl: pruss-ocp-clkctrl@320 {
+ pruss_ocp_clkctrl: clock@320 {
compatible = "ti,clkctrl";
+ clock-output-names = "pruss_ocp_clkctrl";
reg = <0x320 0x4>;
#clock-cells = <2>;
};
- l4ls_clkctrl: l4ls-clkctrl@420 {
+ l4ls_clkctrl: clock@420 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4ls_clkctrl";
reg = <0x420 0x1a4>;
#clock-cells = <2>;
};
- emif_clkctrl: emif-clkctrl@720 {
+ emif_clkctrl: clock@720 {
compatible = "ti,clkctrl";
+ clock-output-names = "emif_clkctrl";
reg = <0x720 0x4>;
#clock-cells = <2>;
};
- dss_clkctrl: dss-clkctrl@a20 {
+ dss_clkctrl: clock@a20 {
compatible = "ti,clkctrl";
+ clock-output-names = "dss_clkctrl";
reg = <0xa20 0x4>;
#clock-cells = <2>;
};
- cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@b20 {
+ cpsw_125mhz_clkctrl: clock@b20 {
compatible = "ti,clkctrl";
+ clock-output-names = "cpsw_125mhz_clkctrl";
reg = <0xb20 0x4>;
#clock-cells = <2>;
};
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 2365554eef3c..04a7a6d1d529 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -5,210 +5,244 @@
* Copyright (C) 2013 Texas Instruments, Inc.
*/
&cm_core_aon_clocks {
- atl_clkin0_ck: atl_clkin0_ck {
+ atl_clkin0_ck: clock-atl-clkin0 {
#clock-cells = <0>;
compatible = "ti,dra7-atl-clock";
+ clock-output-names = "atl_clkin0_ck";
clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
};
- atl_clkin1_ck: atl_clkin1_ck {
+ atl_clkin1_ck: clock-atl-clkin1 {
#clock-cells = <0>;
compatible = "ti,dra7-atl-clock";
+ clock-output-names = "atl_clkin1_ck";
clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
};
- atl_clkin2_ck: atl_clkin2_ck {
+ atl_clkin2_ck: clock-atl-clkin2 {
#clock-cells = <0>;
compatible = "ti,dra7-atl-clock";
+ clock-output-names = "atl_clkin2_ck";
clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
};
- atl_clkin3_ck: atl_clkin3_ck {
+ atl_clkin3_ck: clock-atl-clkin3 {
#clock-cells = <0>;
compatible = "ti,dra7-atl-clock";
+ clock-output-names = "atl_clkin3_ck";
clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
};
- hdmi_clkin_ck: hdmi_clkin_ck {
+ hdmi_clkin_ck: clock-hdmi-clkin {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "hdmi_clkin_ck";
clock-frequency = <0>;
};
- mlb_clkin_ck: mlb_clkin_ck {
+ mlb_clkin_ck: clock-mlb-clkin {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "mlb_clkin_ck";
clock-frequency = <0>;
};
- mlbp_clkin_ck: mlbp_clkin_ck {
+ mlbp_clkin_ck: clock-mlbp-clkin {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "mlbp_clkin_ck";
clock-frequency = <0>;
};
- pciesref_acs_clk_ck: pciesref_acs_clk_ck {
+ pciesref_acs_clk_ck: clock-pciesref-acs {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "pciesref_acs_clk_ck";
clock-frequency = <100000000>;
};
- ref_clkin0_ck: ref_clkin0_ck {
+ ref_clkin0_ck: clock-ref-clkin0 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "ref_clkin0_ck";
clock-frequency = <0>;
};
- ref_clkin1_ck: ref_clkin1_ck {
+ ref_clkin1_ck: clock-ref-clkin1 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "ref_clkin1_ck";
clock-frequency = <0>;
};
- ref_clkin2_ck: ref_clkin2_ck {
+ ref_clkin2_ck: clock-ref-clkin2 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "ref_clkin2_ck";
clock-frequency = <0>;
};
- ref_clkin3_ck: ref_clkin3_ck {
+ ref_clkin3_ck: clock-ref-clkin3 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "ref_clkin3_ck";
clock-frequency = <0>;
};
- rmii_clk_ck: rmii_clk_ck {
+ rmii_clk_ck: clock-rmii {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "rmii_clk_ck";
clock-frequency = <0>;
};
- sdvenc_clkin_ck: sdvenc_clkin_ck {
+ sdvenc_clkin_ck: clock-sdvenc-clkin {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "sdvenc_clkin_ck";
clock-frequency = <0>;
};
- secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+ secure_32k_clk_src_ck: clock-secure-32k-clk-src {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "secure_32k_clk_src_ck";
clock-frequency = <32768>;
};
- sys_clk32_crystal_ck: sys_clk32_crystal_ck {
+ sys_clk32_crystal_ck: clock-sys-clk32-crystal {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "sys_clk32_crystal_ck";
clock-frequency = <32768>;
};
- sys_clk32_pseudo_ck: sys_clk32_pseudo_ck {
+ sys_clk32_pseudo_ck: clock-sys-clk32-pseudo {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "sys_clk32_pseudo_ck";
clocks = <&sys_clkin1>;
clock-mult = <1>;
clock-div = <610>;
};
- virt_12000000_ck: virt_12000000_ck {
+ virt_12000000_ck: clock-virt-12000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_12000000_ck";
clock-frequency = <12000000>;
};
- virt_13000000_ck: virt_13000000_ck {
+ virt_13000000_ck: clock-virt-13000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_13000000_ck";
clock-frequency = <13000000>;
};
- virt_16800000_ck: virt_16800000_ck {
+ virt_16800000_ck: clock-virt-16800000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_16800000_ck";
clock-frequency = <16800000>;
};
- virt_19200000_ck: virt_19200000_ck {
+ virt_19200000_ck: clock-virt-19200000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_19200000_ck";
clock-frequency = <19200000>;
};
- virt_20000000_ck: virt_20000000_ck {
+ virt_20000000_ck: clock-virt-20000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_20000000_ck";
clock-frequency = <20000000>;
};
- virt_26000000_ck: virt_26000000_ck {
+ virt_26000000_ck: clock-virt-26000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_26000000_ck";
clock-frequency = <26000000>;
};
- virt_27000000_ck: virt_27000000_ck {
+ virt_27000000_ck: clock-virt-27000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_27000000_ck";
clock-frequency = <27000000>;
};
- virt_38400000_ck: virt_38400000_ck {
+ virt_38400000_ck: clock-virt-38400000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_38400000_ck";
clock-frequency = <38400000>;
};
- sys_clkin2: sys_clkin2 {
+ sys_clkin2: clock-sys-clkin2 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "sys_clkin2";
clock-frequency = <22579200>;
};
- usb_otg_clkin_ck: usb_otg_clkin_ck {
+ usb_otg_clkin_ck: clock-usb-otg-clkin {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "usb_otg_clkin_ck";
clock-frequency = <0>;
};
- video1_clkin_ck: video1_clkin_ck {
+ video1_clkin_ck: clock-video1-clkin {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "video1_clkin_ck";
clock-frequency = <0>;
};
- video1_m2_clkin_ck: video1_m2_clkin_ck {
+ video1_m2_clkin_ck: clock-video1-m2-clkin {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "video1_m2_clkin_ck";
clock-frequency = <0>;
};
- video2_clkin_ck: video2_clkin_ck {
+ video2_clkin_ck: clock-video2-clkin {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "video2_clkin_ck";
clock-frequency = <0>;
};
- video2_m2_clkin_ck: video2_m2_clkin_ck {
+ video2_m2_clkin_ck: clock-video2-m2-clkin {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "video2_m2_clkin_ck";
clock-frequency = <0>;
};
- dpll_abe_ck: dpll_abe_ck@1e0 {
+ dpll_abe_ck: clock@1e0 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-m4xen-clock";
+ clock-output-names = "dpll_abe_ck";
clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
};
- dpll_abe_x2_ck: dpll_abe_x2_ck {
+ dpll_abe_x2_ck: clock-dpll-abe-x2 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_abe_x2_ck";
clocks = <&dpll_abe_ck>;
};
- dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
+ dpll_abe_m2x2_ck: clock-dpll-abe-m2x2-8@1f0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_abe_m2x2_ck";
clocks = <&dpll_abe_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -217,18 +251,20 @@
ti,invert-autoidle-bit;
};
- abe_clk: abe_clk@108 {
+ abe_clk: clock-abe@108 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "abe_clk";
clocks = <&dpll_abe_m2x2_ck>;
ti,max-div = <4>;
reg = <0x0108>;
ti,index-power-of-two;
};
- dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 {
+ dpll_abe_m2_ck: clock-dpll-abe-m2-8@1f0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_abe_m2_ck";
clocks = <&dpll_abe_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -237,9 +273,10 @@
ti,invert-autoidle-bit;
};
- dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
+ dpll_abe_m3x2_ck: clock-dpll-abe-m3x2-8@1f4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_abe_m3x2_ck";
clocks = <&dpll_abe_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -248,30 +285,34 @@
ti,invert-autoidle-bit;
};
- dpll_core_byp_mux: dpll_core_byp_mux@12c {
+ dpll_core_byp_mux: clock-dpll-core-byp-mux-23@12c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "dpll_core_byp_mux";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
ti,bit-shift = <23>;
reg = <0x012c>;
};
- dpll_core_ck: dpll_core_ck@120 {
+ dpll_core_ck: clock@120 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-core-clock";
+ clock-output-names = "dpll_core_ck";
clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
};
- dpll_core_x2_ck: dpll_core_x2_ck {
+ dpll_core_x2_ck: clock-dpll-core-x2 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_core_x2_ck";
clocks = <&dpll_core_ck>;
};
- dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c {
+ dpll_core_h12x2_ck: clock-dpll-core-h12x2-8@13c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h12x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -280,24 +321,27 @@
ti,invert-autoidle-bit;
};
- mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
+ mpu_dpll_hs_clk_div: clock-mpu-dpll-hs-clk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "mpu_dpll_hs_clk_div";
clocks = <&dpll_core_h12x2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dpll_mpu_ck: dpll_mpu_ck@160 {
+ dpll_mpu_ck: clock@160 {
#clock-cells = <0>;
compatible = "ti,omap5-mpu-dpll-clock";
+ clock-output-names = "dpll_mpu_ck";
clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
};
- dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
+ dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@170 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_mpu_m2_ck";
clocks = <&dpll_mpu_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -306,42 +350,47 @@
ti,invert-autoidle-bit;
};
- mpu_dclk_div: mpu_dclk_div {
+ mpu_dclk_div: clock-mpu-dclk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "mpu_dclk_div";
clocks = <&dpll_mpu_m2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
+ dsp_dpll_hs_clk_div: clock-dsp-dpll-hs-clk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dsp_dpll_hs_clk_div";
clocks = <&dpll_core_h12x2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dpll_dsp_byp_mux: dpll_dsp_byp_mux@240 {
+ dpll_dsp_byp_mux: clock-dpll-dsp-byp-mux-23@240 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "dpll_dsp_byp_mux";
clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x0240>;
};
- dpll_dsp_ck: dpll_dsp_ck@234 {
+ dpll_dsp_ck: clock@234 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_dsp_ck";
clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
assigned-clocks = <&dpll_dsp_ck>;
assigned-clock-rates = <600000000>;
};
- dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 {
+ dpll_dsp_m2_ck: clock-dpll-dsp-m2-8@244 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_dsp_m2_ck";
clocks = <&dpll_dsp_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -352,34 +401,38 @@
assigned-clock-rates = <600000000>;
};
- iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
+ iva_dpll_hs_clk_div: clock-iva-dpll-hs-clk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "iva_dpll_hs_clk_div";
clocks = <&dpll_core_h12x2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dpll_iva_byp_mux: dpll_iva_byp_mux@1ac {
+ dpll_iva_byp_mux: clock-dpll-iva-byp-mux-23@1ac {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "dpll_iva_byp_mux";
clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x01ac>;
};
- dpll_iva_ck: dpll_iva_ck@1a0 {
+ dpll_iva_ck: clock@1a0 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_iva_ck";
clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
assigned-clocks = <&dpll_iva_ck>;
assigned-clock-rates = <1165000000>;
};
- dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 {
+ dpll_iva_m2_ck: clock-dpll-iva-m2-8@1b0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_iva_m2_ck";
clocks = <&dpll_iva_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -390,34 +443,38 @@
assigned-clock-rates = <388333334>;
};
- iva_dclk: iva_dclk {
+ iva_dclk: clock-iva-dclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "iva_dclk";
clocks = <&dpll_iva_m2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dpll_gpu_byp_mux: dpll_gpu_byp_mux@2e4 {
+ dpll_gpu_byp_mux: clock-dpll-gpu-byp-mux-23@2e4 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "dpll_gpu_byp_mux";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
ti,bit-shift = <23>;
reg = <0x02e4>;
};
- dpll_gpu_ck: dpll_gpu_ck@2d8 {
+ dpll_gpu_ck: clock@2d8 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_gpu_ck";
clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
assigned-clocks = <&dpll_gpu_ck>;
assigned-clock-rates = <1277000000>;
};
- dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 {
+ dpll_gpu_m2_ck: clock-dpll-gpu-m2-8@2e8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_gpu_m2_ck";
clocks = <&dpll_gpu_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -428,9 +485,10 @@
assigned-clock-rates = <425666667>;
};
- dpll_core_m2_ck: dpll_core_m2_ck@130 {
+ dpll_core_m2_ck: clock-dpll-core-m2-8@130 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m2_ck";
clocks = <&dpll_core_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -439,32 +497,36 @@
ti,invert-autoidle-bit;
};
- core_dpll_out_dclk_div: core_dpll_out_dclk_div {
+ core_dpll_out_dclk_div: clock-core-dpll-out-dclk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "core_dpll_out_dclk_div";
clocks = <&dpll_core_m2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dpll_ddr_byp_mux: dpll_ddr_byp_mux@21c {
+ dpll_ddr_byp_mux: clock-dpll-ddr-byp-mux-23@21c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "dpll_ddr_byp_mux";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
ti,bit-shift = <23>;
reg = <0x021c>;
};
- dpll_ddr_ck: dpll_ddr_ck@210 {
+ dpll_ddr_ck: clock@210 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_ddr_ck";
clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;
reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
};
- dpll_ddr_m2_ck: dpll_ddr_m2_ck@220 {
+ dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@220 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_ddr_m2_ck";
clocks = <&dpll_ddr_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -473,24 +535,27 @@
ti,invert-autoidle-bit;
};
- dpll_gmac_byp_mux: dpll_gmac_byp_mux@2b4 {
+ dpll_gmac_byp_mux: clock-dpll-gmac-byp-mux-23@2b4 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "dpll_gmac_byp_mux";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
ti,bit-shift = <23>;
reg = <0x02b4>;
};
- dpll_gmac_ck: dpll_gmac_ck@2a8 {
+ dpll_gmac_ck: clock@2a8 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_gmac_ck";
clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
};
- dpll_gmac_m2_ck: dpll_gmac_m2_ck@2b8 {
+ dpll_gmac_m2_ck: clock-dpll-gmac-m2-8@2b8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_gmac_m2_ck";
clocks = <&dpll_gmac_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -499,72 +564,81 @@
ti,invert-autoidle-bit;
};
- video2_dclk_div: video2_dclk_div {
+ video2_dclk_div: clock-video2-dclk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "video2_dclk_div";
clocks = <&video2_m2_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- video1_dclk_div: video1_dclk_div {
+ video1_dclk_div: clock-video1-dclk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "video1_dclk_div";
clocks = <&video1_m2_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- hdmi_dclk_div: hdmi_dclk_div {
+ hdmi_dclk_div: clock-hdmi-dclk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "hdmi_dclk_div";
clocks = <&hdmi_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- per_dpll_hs_clk_div: per_dpll_hs_clk_div {
+ per_dpll_hs_clk_div: clock-per-dpll-hs-clk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "per_dpll_hs_clk_div";
clocks = <&dpll_abe_m3x2_ck>;
clock-mult = <1>;
clock-div = <2>;
};
- usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
+ usb_dpll_hs_clk_div: clock-usb-dpll-hs-clk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "usb_dpll_hs_clk_div";
clocks = <&dpll_abe_m3x2_ck>;
clock-mult = <1>;
clock-div = <3>;
};
- eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
+ eve_dpll_hs_clk_div: clock-eve-dpll-hs-clk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "eve_dpll_hs_clk_div";
clocks = <&dpll_core_h12x2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dpll_eve_byp_mux: dpll_eve_byp_mux@290 {
+ dpll_eve_byp_mux: clock-dpll-eve-byp-mux-23@290 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "dpll_eve_byp_mux";
clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x0290>;
};
- dpll_eve_ck: dpll_eve_ck@284 {
+ dpll_eve_ck: clock@284 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_eve_ck";
clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;
reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
};
- dpll_eve_m2_ck: dpll_eve_m2_ck@294 {
+ dpll_eve_m2_ck: clock-dpll-eve-m2-8@294 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_eve_m2_ck";
clocks = <&dpll_eve_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -573,17 +647,19 @@
ti,invert-autoidle-bit;
};
- eve_dclk_div: eve_dclk_div {
+ eve_dclk_div: clock-eve-dclk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "eve_dclk_div";
clocks = <&dpll_eve_m2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 {
+ dpll_core_h13x2_ck: clock-dpll-core-h13x2-8@140 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h13x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -592,9 +668,10 @@
ti,invert-autoidle-bit;
};
- dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 {
+ dpll_core_h14x2_ck: clock-dpll-core-h14x2-8@144 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h14x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -603,9 +680,10 @@
ti,invert-autoidle-bit;
};
- dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 {
+ dpll_core_h22x2_ck: clock-dpll-core-h22x2-8@154 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h22x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -614,9 +692,10 @@
ti,invert-autoidle-bit;
};
- dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 {
+ dpll_core_h23x2_ck: clock-dpll-core-h23x2-8@158 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h23x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -625,9 +704,10 @@
ti,invert-autoidle-bit;
};
- dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c {
+ dpll_core_h24x2_ck: clock-dpll-core-h24x2-8@15c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h24x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -636,15 +716,17 @@
ti,invert-autoidle-bit;
};
- dpll_ddr_x2_ck: dpll_ddr_x2_ck {
+ dpll_ddr_x2_ck: clock-dpll-ddr-x2 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_ddr_x2_ck";
clocks = <&dpll_ddr_ck>;
};
- dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck@228 {
+ dpll_ddr_h11x2_ck: clock-dpll-ddr-h11x2-8@228 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_ddr_h11x2_ck";
clocks = <&dpll_ddr_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -653,15 +735,17 @@
ti,invert-autoidle-bit;
};
- dpll_dsp_x2_ck: dpll_dsp_x2_ck {
+ dpll_dsp_x2_ck: clock-dpll-dsp-x2 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_dsp_x2_ck";
clocks = <&dpll_dsp_ck>;
};
- dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck@248 {
+ dpll_dsp_m3x2_ck: clock-dpll-dsp-m3x2-8@248 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_dsp_m3x2_ck";
clocks = <&dpll_dsp_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -672,15 +756,17 @@
assigned-clock-rates = <400000000>;
};
- dpll_gmac_x2_ck: dpll_gmac_x2_ck {
+ dpll_gmac_x2_ck: clock-dpll-gmac-x2 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_gmac_x2_ck";
clocks = <&dpll_gmac_ck>;
};
- dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck@2c0 {
+ dpll_gmac_h11x2_ck: clock-dpll-gmac-h11x2-8@2c0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_gmac_h11x2_ck";
clocks = <&dpll_gmac_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -689,9 +775,10 @@
ti,invert-autoidle-bit;
};
- dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck@2c4 {
+ dpll_gmac_h12x2_ck: clock-dpll-gmac-h12x2-8@2c4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_gmac_h12x2_ck";
clocks = <&dpll_gmac_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -700,9 +787,10 @@
ti,invert-autoidle-bit;
};
- dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck@2c8 {
+ dpll_gmac_h13x2_ck: clock-dpll-gmac-h13x2-8@2c8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_gmac_h13x2_ck";
clocks = <&dpll_gmac_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -711,9 +799,10 @@
ti,invert-autoidle-bit;
};
- dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck@2bc {
+ dpll_gmac_m3x2_ck: clock-dpll-gmac-m3x2-8@2bc {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_gmac_m3x2_ck";
clocks = <&dpll_gmac_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -722,33 +811,37 @@
ti,invert-autoidle-bit;
};
- gmii_m_clk_div: gmii_m_clk_div {
+ gmii_m_clk_div: clock-gmii-m-clk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "gmii_m_clk_div";
clocks = <&dpll_gmac_h11x2_ck>;
clock-mult = <1>;
clock-div = <2>;
};
- hdmi_clk2_div: hdmi_clk2_div {
+ hdmi_clk2_div: clock-hdmi-clk2-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "hdmi_clk2_div";
clocks = <&hdmi_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- hdmi_div_clk: hdmi_div_clk {
+ hdmi_div_clk: clock-hdmi-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "hdmi_div_clk";
clocks = <&hdmi_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- l3_iclk_div: l3_iclk_div@100 {
+ l3_iclk_div: clock-l3-iclk-div-4@100 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "l3_iclk_div";
ti,max-div = <2>;
ti,bit-shift = <4>;
reg = <0x0100>;
@@ -756,374 +849,420 @@
ti,index-power-of-two;
};
- l4_root_clk_div: l4_root_clk_div {
+ l4_root_clk_div: clock-l4-root-clk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "l4_root_clk_div";
clocks = <&l3_iclk_div>;
clock-mult = <1>;
clock-div = <2>;
};
- video1_clk2_div: video1_clk2_div {
+ video1_clk2_div: clock-video1-clk2-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "video1_clk2_div";
clocks = <&video1_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- video1_div_clk: video1_div_clk {
+ video1_div_clk: clock-video1-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "video1_div_clk";
clocks = <&video1_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- video2_clk2_div: video2_clk2_div {
+ video2_clk2_div: clock-video2-clk2-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "video2_clk2_div";
clocks = <&video2_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- video2_div_clk: video2_div_clk {
+ video2_div_clk: clock-video2-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "video2_div_clk";
clocks = <&video2_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dummy_ck: dummy_ck {
+ dummy_ck: clock-dummy {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "dummy_ck";
clock-frequency = <0>;
};
};
&prm_clocks {
- sys_clkin1: sys_clkin1@110 {
+ sys_clkin1: clock-sys-clkin1@110 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "sys_clkin1";
clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
reg = <0x0110>;
ti,index-starts-at-one;
};
- abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux@118 {
+ abe_dpll_sys_clk_mux: clock-abe-dpll-sys-clk-mux@118 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "abe_dpll_sys_clk_mux";
clocks = <&sys_clkin1>, <&sys_clkin2>;
reg = <0x0118>;
};
- abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@114 {
+ abe_dpll_bypass_clk_mux: clock-abe-dpll-bypass-clk-mux@114 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "abe_dpll_bypass_clk_mux";
clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
reg = <0x0114>;
};
- abe_dpll_clk_mux: abe_dpll_clk_mux@10c {
+ abe_dpll_clk_mux: clock-abe-dpll-clk-mux@10c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "abe_dpll_clk_mux";
clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
reg = <0x010c>;
};
- abe_24m_fclk: abe_24m_fclk@11c {
+ abe_24m_fclk: clock-abe-24m@11c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "abe_24m_fclk";
clocks = <&dpll_abe_m2x2_ck>;
reg = <0x011c>;
ti,dividers = <8>, <16>;
};
- aess_fclk: aess_fclk@178 {
+ aess_fclk: clock-aess@178 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "aess_fclk";
clocks = <&abe_clk>;
reg = <0x0178>;
ti,max-div = <2>;
};
- abe_giclk_div: abe_giclk_div@174 {
+ abe_giclk_div: clock-abe-giclk-div@174 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "abe_giclk_div";
clocks = <&aess_fclk>;
reg = <0x0174>;
ti,max-div = <2>;
};
- abe_lp_clk_div: abe_lp_clk_div@1d8 {
+ abe_lp_clk_div: clock-abe-lp-clk-div@1d8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "abe_lp_clk_div";
clocks = <&dpll_abe_m2x2_ck>;
reg = <0x01d8>;
ti,dividers = <16>, <32>;
};
- abe_sys_clk_div: abe_sys_clk_div@120 {
+ abe_sys_clk_div: clock-abe-sys-clk-div@120 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "abe_sys_clk_div";
clocks = <&sys_clkin1>;
reg = <0x0120>;
ti,max-div = <2>;
};
- adc_gfclk_mux: adc_gfclk_mux@1dc {
+ adc_gfclk_mux: clock-adc-gfclk-mux@1dc {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "adc_gfclk_mux";
clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
reg = <0x01dc>;
};
- sys_clk1_dclk_div: sys_clk1_dclk_div@1c8 {
+ sys_clk1_dclk_div: clock-sys-clk1-dclk-div@1c8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "sys_clk1_dclk_div";
clocks = <&sys_clkin1>;
ti,max-div = <64>;
reg = <0x01c8>;
ti,index-power-of-two;
};
- sys_clk2_dclk_div: sys_clk2_dclk_div@1cc {
+ sys_clk2_dclk_div: clock-sys-clk2-dclk-div@1cc {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "sys_clk2_dclk_div";
clocks = <&sys_clkin2>;
ti,max-div = <64>;
reg = <0x01cc>;
ti,index-power-of-two;
};
- per_abe_x1_dclk_div: per_abe_x1_dclk_div@1bc {
+ per_abe_x1_dclk_div: clock-per-abe-x1-dclk-div@1bc {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "per_abe_x1_dclk_div";
clocks = <&dpll_abe_m2_ck>;
ti,max-div = <64>;
reg = <0x01bc>;
ti,index-power-of-two;
};
- dsp_gclk_div: dsp_gclk_div@18c {
+ dsp_gclk_div: clock-dsp-gclk-div@18c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dsp_gclk_div";
clocks = <&dpll_dsp_m2_ck>;
ti,max-div = <64>;
reg = <0x018c>;
ti,index-power-of-two;
};
- gpu_dclk: gpu_dclk@1a0 {
+ gpu_dclk: clock-gpu-dclk@1a0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "gpu_dclk";
clocks = <&dpll_gpu_m2_ck>;
ti,max-div = <64>;
reg = <0x01a0>;
ti,index-power-of-two;
};
- emif_phy_dclk_div: emif_phy_dclk_div@190 {
+ emif_phy_dclk_div: clock-emif-phy-dclk-div@190 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "emif_phy_dclk_div";
clocks = <&dpll_ddr_m2_ck>;
ti,max-div = <64>;
reg = <0x0190>;
ti,index-power-of-two;
};
- gmac_250m_dclk_div: gmac_250m_dclk_div@19c {
+ gmac_250m_dclk_div: clock-gmac-250m-dclk-div@19c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "gmac_250m_dclk_div";
clocks = <&dpll_gmac_m2_ck>;
ti,max-div = <64>;
reg = <0x019c>;
ti,index-power-of-two;
};
- gmac_main_clk: gmac_main_clk {
+ gmac_main_clk: clock-gmac-main {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "gmac_main_clk";
clocks = <&gmac_250m_dclk_div>;
clock-mult = <1>;
clock-div = <2>;
};
- l3init_480m_dclk_div: l3init_480m_dclk_div@1ac {
+ l3init_480m_dclk_div: clock-l3init-480m-dclk-div@1ac {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "l3init_480m_dclk_div";
clocks = <&dpll_usb_m2_ck>;
ti,max-div = <64>;
reg = <0x01ac>;
ti,index-power-of-two;
};
- usb_otg_dclk_div: usb_otg_dclk_div@184 {
+ usb_otg_dclk_div: clock-usb-otg-dclk-div@184 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "usb_otg_dclk_div";
clocks = <&usb_otg_clkin_ck>;
ti,max-div = <64>;
reg = <0x0184>;
ti,index-power-of-two;
};
- sata_dclk_div: sata_dclk_div@1c0 {
+ sata_dclk_div: clock-sata-dclk-div@1c0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "sata_dclk_div";
clocks = <&sys_clkin1>;
ti,max-div = <64>;
reg = <0x01c0>;
ti,index-power-of-two;
};
- pcie2_dclk_div: pcie2_dclk_div@1b8 {
+ pcie2_dclk_div: clock-pcie2-dclk-div@1b8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "pcie2_dclk_div";
clocks = <&dpll_pcie_ref_m2_ck>;
ti,max-div = <64>;
reg = <0x01b8>;
ti,index-power-of-two;
};
- pcie_dclk_div: pcie_dclk_div@1b4 {
+ pcie_dclk_div: clock-pcie-dclk-div@1b4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "pcie_dclk_div";
clocks = <&apll_pcie_m2_ck>;
ti,max-div = <64>;
reg = <0x01b4>;
ti,index-power-of-two;
};
- emu_dclk_div: emu_dclk_div@194 {
+ emu_dclk_div: clock-emu-dclk-div@194 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "emu_dclk_div";
clocks = <&sys_clkin1>;
ti,max-div = <64>;
reg = <0x0194>;
ti,index-power-of-two;
};
- secure_32k_dclk_div: secure_32k_dclk_div@1c4 {
+ secure_32k_dclk_div: clock-secure-32k-dclk-div@1c4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "secure_32k_dclk_div";
clocks = <&secure_32k_clk_src_ck>;
ti,max-div = <64>;
reg = <0x01c4>;
ti,index-power-of-two;
};
- clkoutmux0_clk_mux: clkoutmux0_clk_mux@158 {
+ clkoutmux0_clk_mux: clock-clkoutmux0-clk-mux@158 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "clkoutmux0_clk_mux";
clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
reg = <0x0158>;
};
- clkoutmux1_clk_mux: clkoutmux1_clk_mux@15c {
+ clkoutmux1_clk_mux: clock-clkoutmux1-clk-mux@15c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "clkoutmux1_clk_mux";
clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
reg = <0x015c>;
};
- clkoutmux2_clk_mux: clkoutmux2_clk_mux@160 {
+ clkoutmux2_clk_mux: clock-clkoutmux2-clk-mux@160 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "clkoutmux2_clk_mux";
clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
reg = <0x0160>;
};
- custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
+ custefuse_sys_gfclk_div: clock-custefuse-sys-gfclk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "custefuse_sys_gfclk_div";
clocks = <&sys_clkin1>;
clock-mult = <1>;
clock-div = <2>;
};
- eve_clk: eve_clk@180 {
+ eve_clk: clock-eve@180 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "eve_clk";
clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
reg = <0x0180>;
};
- hdmi_dpll_clk_mux: hdmi_dpll_clk_mux@164 {
+ hdmi_dpll_clk_mux: clock-hdmi-dpll-clk-mux@164 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "hdmi_dpll_clk_mux";
clocks = <&sys_clkin1>, <&sys_clkin2>;
reg = <0x0164>;
};
- mlb_clk: mlb_clk@134 {
+ mlb_clk: clock-mlb@134 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "mlb_clk";
clocks = <&mlb_clkin_ck>;
ti,max-div = <64>;
reg = <0x0134>;
ti,index-power-of-two;
};
- mlbp_clk: mlbp_clk@130 {
+ mlbp_clk: clock-mlbp@130 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "mlbp_clk";
clocks = <&mlbp_clkin_ck>;
ti,max-div = <64>;
reg = <0x0130>;
ti,index-power-of-two;
};
- per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div@138 {
+ per_abe_x1_gfclk2_div: clock-per-abe-x1-gfclk2-div@138 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "per_abe_x1_gfclk2_div";
clocks = <&dpll_abe_m2_ck>;
ti,max-div = <64>;
reg = <0x0138>;
ti,index-power-of-two;
};
- timer_sys_clk_div: timer_sys_clk_div@144 {
+ timer_sys_clk_div: clock-timer-sys-clk-div@144 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "timer_sys_clk_div";
clocks = <&sys_clkin1>;
reg = <0x0144>;
ti,max-div = <2>;
};
- video1_dpll_clk_mux: video1_dpll_clk_mux@168 {
+ video1_dpll_clk_mux: clock-video1-dpll-clk-mux@168 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "video1_dpll_clk_mux";
clocks = <&sys_clkin1>, <&sys_clkin2>;
reg = <0x0168>;
};
- video2_dpll_clk_mux: video2_dpll_clk_mux@16c {
+ video2_dpll_clk_mux: clock-video2-dpll-clk-mux@16c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "video2_dpll_clk_mux";
clocks = <&sys_clkin1>, <&sys_clkin2>;
reg = <0x016c>;
};
- wkupaon_iclk_mux: wkupaon_iclk_mux@108 {
+ wkupaon_iclk_mux: clock-wkupaon-iclk-mux@108 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "wkupaon_iclk_mux";
clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
reg = <0x0108>;
};
};
&cm_core_clocks {
- dpll_pcie_ref_ck: dpll_pcie_ref_ck@200 {
+ dpll_pcie_ref_ck: clock@200 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_pcie_ref_ck";
clocks = <&sys_clkin1>, <&sys_clkin1>;
reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
};
- dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@210 {
+ dpll_pcie_ref_m2ldo_ck: clock-dpll-pcie-ref-m2ldo-8@210 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_pcie_ref_m2ldo_ck";
clocks = <&dpll_pcie_ref_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -1132,23 +1271,26 @@
ti,invert-autoidle-bit;
};
- apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
+ apll_pcie_in_clk_mux: clock-apll-pcie-in-clk-mux-7@4ae06118 {
compatible = "ti,mux-clock";
+ clock-output-names = "apll_pcie_in_clk_mux";
clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
#clock-cells = <0>;
reg = <0x021c 0x4>;
ti,bit-shift = <7>;
};
- apll_pcie_ck: apll_pcie_ck@21c {
+ apll_pcie_ck: clock@21c {
#clock-cells = <0>;
compatible = "ti,dra7-apll-clock";
+ clock-output-names = "apll_pcie_ck";
clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
reg = <0x021c>, <0x0220>;
};
- optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
+ optfclk_pciephy_div: clock-optfclk-pciephy-div-8@4a00821c {
compatible = "ti,divider-clock";
+ clock-output-names = "optfclk_pciephy_div";
clocks = <&apll_pcie_ck>;
#clock-cells = <0>;
reg = <0x021c>;
@@ -1157,48 +1299,54 @@
ti,max-div = <2>;
};
- apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
+ apll_pcie_clkvcoldo: clock-apll-pcie-clkvcoldo {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "apll_pcie_clkvcoldo";
clocks = <&apll_pcie_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
+ apll_pcie_clkvcoldo_div: clock-apll-pcie-clkvcoldo-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "apll_pcie_clkvcoldo_div";
clocks = <&apll_pcie_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- apll_pcie_m2_ck: apll_pcie_m2_ck {
+ apll_pcie_m2_ck: clock-apll-pcie-m2 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "apll_pcie_m2_ck";
clocks = <&apll_pcie_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dpll_per_byp_mux: dpll_per_byp_mux@14c {
+ dpll_per_byp_mux: clock-dpll-per-byp-mux-23@14c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "dpll_per_byp_mux";
clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x014c>;
};
- dpll_per_ck: dpll_per_ck@140 {
+ dpll_per_ck: clock@140 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_per_ck";
clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;
reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
};
- dpll_per_m2_ck: dpll_per_m2_ck@150 {
+ dpll_per_m2_ck: clock-dpll-per-m2-8@150 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m2_ck";
clocks = <&dpll_per_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -1207,32 +1355,36 @@
ti,invert-autoidle-bit;
};
- func_96m_aon_dclk_div: func_96m_aon_dclk_div {
+ func_96m_aon_dclk_div: clock-func-96m-aon-dclk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_96m_aon_dclk_div";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dpll_usb_byp_mux: dpll_usb_byp_mux@18c {
+ dpll_usb_byp_mux: clock-dpll-usb-byp-mux-23@18c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "dpll_usb_byp_mux";
clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x018c>;
};
- dpll_usb_ck: dpll_usb_ck@180 {
+ dpll_usb_ck: clock@180 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-j-type-clock";
+ clock-output-names = "dpll_usb_ck";
clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;
reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
};
- dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
+ dpll_usb_m2_ck: clock-dpll-usb-m2-8@190 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_usb_m2_ck";
clocks = <&dpll_usb_ck>;
ti,max-div = <127>;
ti,autoidle-shift = <8>;
@@ -1241,9 +1393,10 @@
ti,invert-autoidle-bit;
};
- dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck@210 {
+ dpll_pcie_ref_m2_ck: clock-dpll-pcie-ref-m2-8@210 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_pcie_ref_m2_ck";
clocks = <&dpll_pcie_ref_ck>;
ti,max-div = <127>;
ti,autoidle-shift = <8>;
@@ -1252,15 +1405,17 @@
ti,invert-autoidle-bit;
};
- dpll_per_x2_ck: dpll_per_x2_ck {
+ dpll_per_x2_ck: clock-dpll-per-x2 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_per_x2_ck";
clocks = <&dpll_per_ck>;
};
- dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 {
+ dpll_per_h11x2_ck: clock-dpll-per-h11x2-8@158 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_h11x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -1269,9 +1424,10 @@
ti,invert-autoidle-bit;
};
- dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c {
+ dpll_per_h12x2_ck: clock-dpll-per-h12x2-8@15c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_h12x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -1280,9 +1436,10 @@
ti,invert-autoidle-bit;
};
- dpll_per_h13x2_ck: dpll_per_h13x2_ck@160 {
+ dpll_per_h13x2_ck: clock-dpll-per-h13x2-8@160 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_h13x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -1291,9 +1448,10 @@
ti,invert-autoidle-bit;
};
- dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 {
+ dpll_per_h14x2_ck: clock-dpll-per-h14x2-8@164 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_h14x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -1302,9 +1460,10 @@
ti,invert-autoidle-bit;
};
- dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
+ dpll_per_m2x2_ck: clock-dpll-per-m2x2-8@150 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m2x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -1313,105 +1472,118 @@
ti,invert-autoidle-bit;
};
- dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
+ dpll_usb_clkdcoldo: clock-dpll-usb-clkdcoldo {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dpll_usb_clkdcoldo";
clocks = <&dpll_usb_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- func_128m_clk: func_128m_clk {
+ func_128m_clk: clock-func-128m {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_128m_clk";
clocks = <&dpll_per_h11x2_ck>;
clock-mult = <1>;
clock-div = <2>;
};
- func_12m_fclk: func_12m_fclk {
+ func_12m_fclk: clock-func-12m-fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_12m_fclk";
clocks = <&dpll_per_m2x2_ck>;
clock-mult = <1>;
clock-div = <16>;
};
- func_24m_clk: func_24m_clk {
+ func_24m_clk: clock-func-24m {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_24m_clk";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <4>;
};
- func_48m_fclk: func_48m_fclk {
+ func_48m_fclk: clock-func-48m-fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_48m_fclk";
clocks = <&dpll_per_m2x2_ck>;
clock-mult = <1>;
clock-div = <4>;
};
- func_96m_fclk: func_96m_fclk {
+ func_96m_fclk: clock-func-96m-fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_96m_fclk";
clocks = <&dpll_per_m2x2_ck>;
clock-mult = <1>;
clock-div = <2>;
};
- l3init_60m_fclk: l3init_60m_fclk@104 {
+ l3init_60m_fclk: clock-l3init-60m@104 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "l3init_60m_fclk";
clocks = <&dpll_usb_m2_ck>;
reg = <0x0104>;
ti,dividers = <1>, <8>;
};
- clkout2_clk: clkout2_clk@6b0 {
+ clkout2_clk: clock-clkout2-8@6b0 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "clkout2_clk";
clocks = <&clkoutmux2_clk_mux>;
ti,bit-shift = <8>;
reg = <0x06b0>;
};
- l3init_960m_gfclk: l3init_960m_gfclk@6c0 {
+ l3init_960m_gfclk: clock-l3init-960m-gfclk-8@6c0 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "l3init_960m_gfclk";
clocks = <&dpll_usb_clkdcoldo>;
ti,bit-shift = <8>;
reg = <0x06c0>;
};
- usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@640 {
+ usb_phy1_always_on_clk32k: clock-usb-phy1-always-on-clk32k-8@640 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "usb_phy1_always_on_clk32k";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x0640>;
};
- usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k@688 {
+ usb_phy2_always_on_clk32k: clock-usb-phy2-always-on-clk32k-8@688 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "usb_phy2_always_on_clk32k";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x0688>;
};
- usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@698 {
+ usb_phy3_always_on_clk32k: clock-usb-phy3-always-on-clk32k-8@698 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "usb_phy3_always_on_clk32k";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x0698>;
};
- gpu_core_gclk_mux: gpu_core_gclk_mux@1220 {
+ gpu_core_gclk_mux: clock-gpu-core-gclk-mux-24@1220 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "gpu_core_gclk_mux";
clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
ti,bit-shift = <24>;
reg = <0x1220>;
@@ -1419,9 +1591,10 @@
assigned-clock-parents = <&dpll_gpu_m2_ck>;
};
- gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 {
+ gpu_hyd_gclk_mux: clock-gpu-hyd-gclk-mux-26@1220 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "gpu_hyd_gclk_mux";
clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
ti,bit-shift = <26>;
reg = <0x1220>;
@@ -1429,34 +1602,38 @@
assigned-clock-parents = <&dpll_gpu_m2_ck>;
};
- l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 {
+ l3instr_ts_gclk_div: clock-l3instr-ts-gclk-div-24@e50 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "l3instr_ts_gclk_div";
clocks = <&wkupaon_iclk_mux>;
ti,bit-shift = <24>;
reg = <0x0e50>;
ti,dividers = <8>, <16>, <32>;
};
- vip1_gclk_mux: vip1_gclk_mux@1020 {
+ vip1_gclk_mux: clock-vip1-gclk-mux-24@1020 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "vip1_gclk_mux";
clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
ti,bit-shift = <24>;
reg = <0x1020>;
};
- vip2_gclk_mux: vip2_gclk_mux@1028 {
+ vip2_gclk_mux: clock-vip2-gclk-mux-24@1028 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "vip2_gclk_mux";
clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
ti,bit-shift = <24>;
reg = <0x1028>;
};
- vip3_gclk_mux: vip3_gclk_mux@1030 {
+ vip3_gclk_mux: clock-vip3-gclk-mux-24@1030 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "vip3_gclk_mux";
clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
ti,bit-shift = <24>;
reg = <0x1030>;
@@ -1464,48 +1641,54 @@
};
&cm_core_clockdomains {
- coreaon_clkdm: coreaon_clkdm {
+ coreaon_clkdm: clock-coreaon-clkdm {
compatible = "ti,clockdomain";
+ clock-output-names = "coreaon_clkdm";
clocks = <&dpll_usb_ck>;
};
};
&scm_conf_clocks {
- dss_deshdcp_clk: dss_deshdcp_clk@558 {
+ dss_deshdcp_clk: clock-dss-deshdcp-0@558 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "dss_deshdcp_clk";
clocks = <&l3_iclk_div>;
ti,bit-shift = <0>;
reg = <0x558>;
};
- ehrpwm0_tbclk: ehrpwm0_tbclk@558 {
+ ehrpwm0_tbclk: clock-ehrpwm0-tbclk-20@558 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "ehrpwm0_tbclk";
clocks = <&l4_root_clk_div>;
ti,bit-shift = <20>;
reg = <0x0558>;
};
- ehrpwm1_tbclk: ehrpwm1_tbclk@558 {
+ ehrpwm1_tbclk: clock-ehrpwm1-tbclk-21@558 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "ehrpwm1_tbclk";
clocks = <&l4_root_clk_div>;
ti,bit-shift = <21>;
reg = <0x0558>;
};
- ehrpwm2_tbclk: ehrpwm2_tbclk@558 {
+ ehrpwm2_tbclk: clock-ehrpwm2-tbclk-22@558 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "ehrpwm2_tbclk";
clocks = <&l4_root_clk_div>;
ti,bit-shift = <22>;
reg = <0x0558>;
};
- sys_32k_ck: sys_32k_ck {
+ sys_32k_ck: clock-sys-32k {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "sys_32k_ck";
clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>;
ti,bit-shift = <8>;
reg = <0x6c4>;
@@ -1513,97 +1696,110 @@
};
&cm_core_aon {
- mpu_cm: mpu-cm@300 {
+ mpu_cm: clock@300 {
compatible = "ti,omap4-cm";
+ clock-output-names = "mpu_cm";
reg = <0x300 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x300 0x100>;
- mpu_clkctrl: mpu-clkctrl@20 {
+ mpu_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "mpu_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
- dsp1_cm: dsp1-cm@400 {
+ dsp1_cm: clock@400 {
compatible = "ti,omap4-cm";
+ clock-output-names = "dsp1_cm";
reg = <0x400 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x400 0x100>;
- dsp1_clkctrl: dsp1-clkctrl@20 {
+ dsp1_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "dsp1_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
- ipu_cm: ipu-cm@500 {
+ ipu_cm: clock@500 {
compatible = "ti,omap4-cm";
+ clock-output-names = "ipu_cm";
reg = <0x500 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x500 0x100>;
- ipu1_clkctrl: ipu1-clkctrl@20 {
+ ipu1_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "ipu1_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
assigned-clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 24>;
assigned-clock-parents = <&dpll_core_h22x2_ck>;
};
- ipu_clkctrl: ipu-clkctrl@50 {
+ ipu_clkctrl: clock@50 {
compatible = "ti,clkctrl";
+ clock-output-names = "ipu_clkctrl";
reg = <0x50 0x34>;
#clock-cells = <2>;
};
};
- dsp2_cm: dsp2-cm@600 {
+ dsp2_cm: clock@600 {
compatible = "ti,omap4-cm";
+ clock-output-names = "dsp2_cm";
reg = <0x600 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x600 0x100>;
- dsp2_clkctrl: dsp2-clkctrl@20 {
+ dsp2_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "dsp2_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
- rtc_cm: rtc-cm@700 {
+ rtc_cm: clock@700 {
compatible = "ti,omap4-cm";
+ clock-output-names = "rtc_cm";
reg = <0x700 0x60>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x700 0x60>;
- rtc_clkctrl: rtc-clkctrl@20 {
+ rtc_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "rtc_clkctrl";
reg = <0x20 0x28>;
#clock-cells = <2>;
};
};
- vpe_cm: vpe-cm@760 {
+ vpe_cm: clock@760 {
compatible = "ti,omap4-cm";
+ clock-output-names = "vpe_cm";
reg = <0x760 0xc>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x760 0xc>;
- vpe_clkctrl: vpe-clkctrl@0 {
+ vpe_clkctrl: clock@0 {
compatible = "ti,clkctrl";
+ clock-output-names = "vpe_clkctrl";
reg = <0x0 0xc>;
#clock-cells = <2>;
};
@@ -1612,212 +1808,242 @@
};
&cm_core {
- coreaon_cm: coreaon-cm@600 {
+ coreaon_cm: clock@600 {
compatible = "ti,omap4-cm";
+ clock-output-names = "coreaon_cm";
reg = <0x600 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x600 0x100>;
- coreaon_clkctrl: coreaon-clkctrl@20 {
+ coreaon_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "coreaon_clkctrl";
reg = <0x20 0x1c>;
#clock-cells = <2>;
};
};
- l3main1_cm: l3main1-cm@700 {
+ l3main1_cm: clock@700 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3main1_cm";
reg = <0x700 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x700 0x100>;
- l3main1_clkctrl: l3main1-clkctrl@20 {
+ l3main1_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3main1_clkctrl";
reg = <0x20 0x74>;
#clock-cells = <2>;
};
};
- ipu2_cm: ipu2-cm@900 {
+ ipu2_cm: clock@900 {
compatible = "ti,omap4-cm";
+ clock-output-names = "ipu2_cm";
reg = <0x900 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x900 0x100>;
- ipu2_clkctrl: ipu2-clkctrl@20 {
+ ipu2_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "ipu2_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
- dma_cm: dma-cm@a00 {
+ dma_cm: clock@a00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "dma_cm";
reg = <0xa00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xa00 0x100>;
- dma_clkctrl: dma-clkctrl@20 {
+ dma_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "dma_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
- emif_cm: emif-cm@b00 {
+ emif_cm: clock@b00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "emif_cm";
reg = <0xb00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xb00 0x100>;
- emif_clkctrl: emif-clkctrl@20 {
+ emif_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "emif_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
- atl_cm: atl-cm@c00 {
+ atl_cm: clock@c00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "atl_cm";
reg = <0xc00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xc00 0x100>;
- atl_clkctrl: atl-clkctrl@0 {
+ atl_clkctrl: clock@0 {
compatible = "ti,clkctrl";
+ clock-output-names = "atl_clkctrl";
reg = <0x0 0x4>;
#clock-cells = <2>;
};
};
- l4cfg_cm: l4cfg-cm@d00 {
+ l4cfg_cm: clock@d00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l4cfg_cm";
reg = <0xd00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xd00 0x100>;
- l4cfg_clkctrl: l4cfg-clkctrl@20 {
+ l4cfg_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4cfg_clkctrl";
reg = <0x20 0x84>;
#clock-cells = <2>;
};
};
- l3instr_cm: l3instr-cm@e00 {
+ l3instr_cm: clock@e00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3instr_cm";
reg = <0xe00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xe00 0x100>;
- l3instr_clkctrl: l3instr-clkctrl@20 {
+ l3instr_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3instr_clkctrl";
reg = <0x20 0xc>;
#clock-cells = <2>;
};
};
- iva_cm: iva-cm@f00 {
+ iva_cm: clock@f00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "iva_cm";
reg = <0xf00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xf00 0x100>;
- iva_clkctrl: iva-clkctrl@20 {
+ iva_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "iva_clkctrl";
reg = <0x20 0xc>;
#clock-cells = <2>;
};
};
- cam_cm: cam-cm@1000 {
+ cam_cm: clock@1000 {
compatible = "ti,omap4-cm";
+ clock-output-names = "cam_cm";
reg = <0x1000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1000 0x100>;
- cam_clkctrl: cam-clkctrl@20 {
+ cam_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "cam_clkctrl";
reg = <0x20 0x2c>;
#clock-cells = <2>;
};
};
- dss_cm: dss-cm@1100 {
+ dss_cm: clock@1100 {
compatible = "ti,omap4-cm";
+ clock-output-names = "dss_cm";
reg = <0x1100 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1100 0x100>;
- dss_clkctrl: dss-clkctrl@20 {
+ dss_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "dss_clkctrl";
reg = <0x20 0x14>;
#clock-cells = <2>;
};
};
- gpu_cm: gpu-cm@1200 {
+ gpu_cm: clock@1200 {
compatible = "ti,omap4-cm";
+ clock-output-names = "gpu_cm";
reg = <0x1200 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1200 0x100>;
- gpu_clkctrl: gpu-clkctrl@20 {
+ gpu_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "gpu_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
- l3init_cm: l3init-cm@1300 {
+ l3init_cm: clock@1300 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3init_cm";
reg = <0x1300 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1300 0x100>;
- l3init_clkctrl: l3init-clkctrl@20 {
+ l3init_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3init_clkctrl";
reg = <0x20 0x6c>, <0xe0 0x14>;
#clock-cells = <2>;
};
- pcie_clkctrl: pcie-clkctrl@b0 {
+ pcie_clkctrl: clock@b0 {
compatible = "ti,clkctrl";
+ clock-output-names = "pcie_clkctrl";
reg = <0xb0 0xc>;
#clock-cells = <2>;
};
- gmac_clkctrl: gmac-clkctrl@d0 {
+ gmac_clkctrl: clock@d0 {
compatible = "ti,clkctrl";
+ clock-output-names = "gmac_clkctrl";
reg = <0xd0 0x4>;
#clock-cells = <2>;
};
};
- l4per_cm: l4per-cm@1700 {
+ l4per_cm: clock@1700 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l4per_cm";
reg = <0x1700 0x300>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1700 0x300>;
- l4per_clkctrl: l4per-clkctrl@28 {
+ l4per_clkctrl: clock@28 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4per_clkctrl";
reg = <0x28 0x64>, <0xa0 0x24>, <0xf0 0x3c>, <0x140 0x1c>, <0x170 0x4>;
#clock-cells = <2>;
@@ -1825,20 +2051,23 @@
assigned-clock-parents = <&abe_24m_fclk>;
};
- l4sec_clkctrl: l4sec-clkctrl@1a0 {
+ l4sec_clkctrl: clock@1a0 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4sec_clkctrl";
reg = <0x1a0 0x2c>;
#clock-cells = <2>;
};
- l4per2_clkctrl: l4per2-clkctrl@c {
+ l4per2_clkctrl: clock@c {
compatible = "ti,clkctrl";
+ clock-output-names = "l4per2_clkctrl";
reg = <0xc 0x4>, <0x18 0xc>, <0x90 0xc>, <0xc4 0x4>, <0x138 0x4>, <0x160 0xc>, <0x178 0x24>, <0x1d0 0x3c>;
#clock-cells = <2>;
};
- l4per3_clkctrl: l4per3-clkctrl@14 {
+ l4per3_clkctrl: clock@14 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4per3_clkctrl";
reg = <0x14 0x4>, <0xc8 0x14>, <0x130 0x4>;
#clock-cells = <2>;
};
@@ -1847,15 +2076,17 @@
};
&prm {
- wkupaon_cm: wkupaon-cm@1800 {
+ wkupaon_cm: clock@1800 {
compatible = "ti,omap4-cm";
+ clock-output-names = "wkupaon_cm";
reg = <0x1800 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1800 0x100>;
- wkupaon_clkctrl: wkupaon-clkctrl@20 {
+ wkupaon_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "wkupaon_clkctrl";
reg = <0x20 0x6c>;
#clock-cells = <2>;
};
diff --git a/arch/arm/boot/dts/logicpd-som-lv.dtsi b/arch/arm/boot/dts/logicpd-som-lv.dtsi
index b56524cc7fe2..5475e5de3d78 100644
--- a/arch/arm/boot/dts/logicpd-som-lv.dtsi
+++ b/arch/arm/boot/dts/logicpd-som-lv.dtsi
@@ -27,6 +27,8 @@
/* HS USB Host PHY on PORT 1 */
hsusb2_phy: hsusb2_phy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hsusb2_reset_pin>;
compatible = "usb-nop-xceiv";
reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* gpio_4 */
#phy-cells = <0>;
@@ -144,6 +146,8 @@
};
&usbhshost {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hsusb2_pins>;
port2-mode = "ehci-phy";
};
@@ -151,10 +155,7 @@
phys = <0 &hsusb2_phy>;
};
-
&omap3_pmx_core {
- pinctrl-names = "default";
- pinctrl-0 = <&hsusb2_pins>;
mmc3_pins: pinmux_mm3_pins {
pinctrl-single,pins = <
@@ -250,8 +251,7 @@
};
&omap3_pmx_wkup {
- pinctrl-names = "default";
- pinctrl-0 = <&hsusb2_reset_pin>;
+
hsusb2_reset_pin: pinmux_hsusb1_reset_pin {
pinctrl-single,pins = <
OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4) /* sys_boot2.gpio_4 */
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index a858ebfa1500..35eced6521ef 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -370,7 +370,7 @@
#address-cells = <1>;
#size-cells = <0>;
- ethernet: usbether@1 {
+ ethernet: ethernet@1 {
compatible = "usb424,ec00";
reg = <1>;
};
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 609a8dea946b..518652a599bd 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -558,7 +558,7 @@
#address-cells = <1>;
#size-cells = <0>;
- ethernet: usbether@1 {
+ ethernet: ethernet@1 {
compatible = "usb424,ec00";
reg = <1>;
};
diff --git a/arch/arm/boot/dts/omap443x-clocks.dtsi b/arch/arm/boot/dts/omap443x-clocks.dtsi
index 39297868ec85..581e088231b5 100644
--- a/arch/arm/boot/dts/omap443x-clocks.dtsi
+++ b/arch/arm/boot/dts/omap443x-clocks.dtsi
@@ -8,6 +8,7 @@
bandgap_fclk: bandgap_fclk@1888 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "bandgap_fclk";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1888>;
diff --git a/arch/arm/boot/dts/omap446x-clocks.dtsi b/arch/arm/boot/dts/omap446x-clocks.dtsi
index 0f41714cffbb..d9362fef6720 100644
--- a/arch/arm/boot/dts/omap446x-clocks.dtsi
+++ b/arch/arm/boot/dts/omap446x-clocks.dtsi
@@ -8,6 +8,7 @@
div_ts_ck: div_ts_ck@1888 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "div_ts_ck";
clocks = <&l4_wkup_clk_mux_ck>;
ti,bit-shift = <24>;
reg = <0x1888>;
@@ -17,6 +18,7 @@
bandgap_ts_fclk: bandgap_ts_fclk@1888 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "bandgap_ts_fclk";
clocks = <&div_ts_ck>;
ti,bit-shift = <8>;
reg = <0x1888>;
diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi
index 1f1c04d8f472..8df73d285638 100644
--- a/arch/arm/boot/dts/omap44xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi
@@ -8,18 +8,21 @@
extalt_clkin_ck: extalt_clkin_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "extalt_clkin_ck";
clock-frequency = <59000000>;
};
pad_clks_src_ck: pad_clks_src_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "pad_clks_src_ck";
clock-frequency = <12000000>;
};
pad_clks_ck: pad_clks_ck@108 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "pad_clks_ck";
clocks = <&pad_clks_src_ck>;
ti,bit-shift = <8>;
reg = <0x0108>;
@@ -28,24 +31,28 @@
pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "pad_slimbus_core_clks_ck";
clock-frequency = <12000000>;
};
secure_32k_clk_src_ck: secure_32k_clk_src_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "secure_32k_clk_src_ck";
clock-frequency = <32768>;
};
slimbus_src_clk: slimbus_src_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "slimbus_src_clk";
clock-frequency = <12000000>;
};
slimbus_clk: slimbus_clk@108 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "slimbus_clk";
clocks = <&slimbus_src_clk>;
ti,bit-shift = <10>;
reg = <0x0108>;
@@ -54,84 +61,98 @@
sys_32k_ck: sys_32k_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "sys_32k_ck";
clock-frequency = <32768>;
};
virt_12000000_ck: virt_12000000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_12000000_ck";
clock-frequency = <12000000>;
};
virt_13000000_ck: virt_13000000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_13000000_ck";
clock-frequency = <13000000>;
};
virt_16800000_ck: virt_16800000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_16800000_ck";
clock-frequency = <16800000>;
};
virt_19200000_ck: virt_19200000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_19200000_ck";
clock-frequency = <19200000>;
};
virt_26000000_ck: virt_26000000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_26000000_ck";
clock-frequency = <26000000>;
};
virt_27000000_ck: virt_27000000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_27000000_ck";
clock-frequency = <27000000>;
};
virt_38400000_ck: virt_38400000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_38400000_ck";
clock-frequency = <38400000>;
};
tie_low_clock_ck: tie_low_clock_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "tie_low_clock_ck";
clock-frequency = <0>;
};
utmi_phy_clkout_ck: utmi_phy_clkout_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "utmi_phy_clkout_ck";
clock-frequency = <60000000>;
};
xclk60mhsp1_ck: xclk60mhsp1_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "xclk60mhsp1_ck";
clock-frequency = <60000000>;
};
xclk60mhsp2_ck: xclk60mhsp2_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "xclk60mhsp2_ck";
clock-frequency = <60000000>;
};
xclk60motg_ck: xclk60motg_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "xclk60motg_ck";
clock-frequency = <60000000>;
};
dpll_abe_ck: dpll_abe_ck@1e0 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-m4xen-clock";
+ clock-output-names = "dpll_abe_ck";
clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>;
reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
};
@@ -139,6 +160,7 @@
dpll_abe_x2_ck: dpll_abe_x2_ck@1f0 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_abe_x2_ck";
clocks = <&dpll_abe_ck>;
reg = <0x01f0>;
};
@@ -146,6 +168,7 @@
dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_abe_m2x2_ck";
clocks = <&dpll_abe_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -157,6 +180,7 @@
abe_24m_fclk: abe_24m_fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "abe_24m_fclk";
clocks = <&dpll_abe_m2x2_ck>;
clock-mult = <1>;
clock-div = <8>;
@@ -165,6 +189,7 @@
abe_clk: abe_clk@108 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "abe_clk";
clocks = <&dpll_abe_m2x2_ck>;
ti,max-div = <4>;
reg = <0x0108>;
@@ -175,6 +200,7 @@
dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_abe_m3x2_ck";
clocks = <&dpll_abe_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -186,6 +212,7 @@
core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck@12c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "core_hsd_byp_clk_mux_ck";
clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>;
ti,bit-shift = <23>;
reg = <0x012c>;
@@ -194,6 +221,7 @@
dpll_core_ck: dpll_core_ck@120 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-core-clock";
+ clock-output-names = "dpll_core_ck";
clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>;
reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
};
@@ -201,12 +229,14 @@
dpll_core_x2_ck: dpll_core_x2_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_core_x2_ck";
clocks = <&dpll_core_ck>;
};
dpll_core_m6x2_ck: dpll_core_m6x2_ck@140 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m6x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -218,6 +248,7 @@
dpll_core_m2_ck: dpll_core_m2_ck@130 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m2_ck";
clocks = <&dpll_core_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -229,6 +260,7 @@
ddrphy_ck: ddrphy_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "ddrphy_ck";
clocks = <&dpll_core_m2_ck>;
clock-mult = <1>;
clock-div = <2>;
@@ -237,6 +269,7 @@
dpll_core_m5x2_ck: dpll_core_m5x2_ck@13c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m5x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -248,6 +281,7 @@
div_core_ck: div_core_ck@100 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "div_core_ck";
clocks = <&dpll_core_m5x2_ck>;
reg = <0x0100>;
ti,max-div = <2>;
@@ -256,6 +290,7 @@
div_iva_hs_clk: div_iva_hs_clk@1dc {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "div_iva_hs_clk";
clocks = <&dpll_core_m5x2_ck>;
ti,max-div = <4>;
reg = <0x01dc>;
@@ -265,6 +300,7 @@
div_mpu_hs_clk: div_mpu_hs_clk@19c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "div_mpu_hs_clk";
clocks = <&dpll_core_m5x2_ck>;
ti,max-div = <4>;
reg = <0x019c>;
@@ -274,6 +310,7 @@
dpll_core_m4x2_ck: dpll_core_m4x2_ck@138 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m4x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -285,6 +322,7 @@
dll_clk_div_ck: dll_clk_div_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dll_clk_div_ck";
clocks = <&dpll_core_m4x2_ck>;
clock-mult = <1>;
clock-div = <2>;
@@ -293,6 +331,7 @@
dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_abe_m2_ck";
clocks = <&dpll_abe_ck>;
ti,max-div = <31>;
reg = <0x01f0>;
@@ -302,6 +341,7 @@
dpll_core_m3x2_gate_ck: dpll_core_m3x2_gate_ck@134 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "dpll_core_m3x2_gate_ck";
clocks = <&dpll_core_x2_ck>;
ti,bit-shift = <8>;
reg = <0x0134>;
@@ -310,6 +350,7 @@
dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck@134 {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
+ clock-output-names = "dpll_core_m3x2_div_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <31>;
reg = <0x0134>;
@@ -319,12 +360,14 @@
dpll_core_m3x2_ck: dpll_core_m3x2_ck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
+ clock-output-names = "dpll_core_m3x2_ck";
clocks = <&dpll_core_m3x2_gate_ck>, <&dpll_core_m3x2_div_ck>;
};
dpll_core_m7x2_ck: dpll_core_m7x2_ck@144 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m7x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -336,6 +379,7 @@
iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck@1ac {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "iva_hsd_byp_clk_mux_ck";
clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>;
ti,bit-shift = <23>;
reg = <0x01ac>;
@@ -344,6 +388,7 @@
dpll_iva_ck: dpll_iva_ck@1a0 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_iva_ck";
clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>;
reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
assigned-clocks = <&dpll_iva_ck>;
@@ -353,12 +398,14 @@
dpll_iva_x2_ck: dpll_iva_x2_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_iva_x2_ck";
clocks = <&dpll_iva_ck>;
};
dpll_iva_m4x2_ck: dpll_iva_m4x2_ck@1b8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_iva_m4x2_ck";
clocks = <&dpll_iva_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -372,6 +419,7 @@
dpll_iva_m5x2_ck: dpll_iva_m5x2_ck@1bc {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_iva_m5x2_ck";
clocks = <&dpll_iva_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -385,6 +433,7 @@
dpll_mpu_ck: dpll_mpu_ck@160 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_mpu_ck";
clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>;
reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
};
@@ -392,6 +441,7 @@
dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_mpu_m2_ck";
clocks = <&dpll_mpu_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -403,6 +453,7 @@
per_hs_clk_div_ck: per_hs_clk_div_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "per_hs_clk_div_ck";
clocks = <&dpll_abe_m3x2_ck>;
clock-mult = <1>;
clock-div = <2>;
@@ -411,6 +462,7 @@
usb_hs_clk_div_ck: usb_hs_clk_div_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "usb_hs_clk_div_ck";
clocks = <&dpll_abe_m3x2_ck>;
clock-mult = <1>;
clock-div = <3>;
@@ -419,6 +471,7 @@
l3_div_ck: l3_div_ck@100 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "l3_div_ck";
clocks = <&div_core_ck>;
ti,bit-shift = <4>;
ti,max-div = <2>;
@@ -428,6 +481,7 @@
l4_div_ck: l4_div_ck@100 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "l4_div_ck";
clocks = <&l3_div_ck>;
ti,bit-shift = <8>;
ti,max-div = <2>;
@@ -437,6 +491,7 @@
lp_clk_div_ck: lp_clk_div_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "lp_clk_div_ck";
clocks = <&dpll_abe_m2x2_ck>;
clock-mult = <1>;
clock-div = <16>;
@@ -445,6 +500,7 @@
mpu_periphclk: mpu_periphclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "mpu_periphclk";
clocks = <&dpll_mpu_ck>;
clock-mult = <1>;
clock-div = <2>;
@@ -453,6 +509,7 @@
ocp_abe_iclk: ocp_abe_iclk@528 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "ocp_abe_iclk";
clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 24>;
ti,bit-shift = <24>;
reg = <0x0528>;
@@ -462,6 +519,7 @@
per_abe_24m_fclk: per_abe_24m_fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "per_abe_24m_fclk";
clocks = <&dpll_abe_m2_ck>;
clock-mult = <1>;
clock-div = <4>;
@@ -470,6 +528,7 @@
dummy_ck: dummy_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "dummy_ck";
clock-frequency = <0>;
};
};
@@ -478,6 +537,7 @@
sys_clkin_ck: sys_clkin_ck@110 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "sys_clkin_ck";
clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
reg = <0x0110>;
ti,index-starts-at-one;
@@ -486,6 +546,7 @@
abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@108 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "abe_dpll_bypass_clk_mux_ck";
clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
ti,bit-shift = <24>;
reg = <0x0108>;
@@ -494,6 +555,7 @@
abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck@10c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "abe_dpll_refclk_mux_ck";
clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
reg = <0x010c>;
};
@@ -501,6 +563,7 @@
dbgclk_mux_ck: dbgclk_mux_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dbgclk_mux_ck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
@@ -509,6 +572,7 @@
l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck@108 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "l4_wkup_clk_mux_ck";
clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>;
reg = <0x0108>;
};
@@ -516,6 +580,7 @@
syc_clk_div_ck: syc_clk_div_ck@100 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "syc_clk_div_ck";
clocks = <&sys_clkin_ck>;
reg = <0x0100>;
ti,max-div = <2>;
@@ -524,6 +589,7 @@
usim_ck: usim_ck@1858 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "usim_ck";
clocks = <&dpll_per_m4x2_ck>;
ti,bit-shift = <24>;
reg = <0x1858>;
@@ -533,6 +599,7 @@
usim_fclk: usim_fclk@1858 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "usim_fclk";
clocks = <&usim_ck>;
ti,bit-shift = <8>;
reg = <0x1858>;
@@ -541,6 +608,7 @@
trace_clk_div_ck: trace_clk_div_ck {
#clock-cells = <0>;
compatible = "ti,clkdm-gate-clock";
+ clock-output-names = "trace_clk_div_ck";
clocks = <&emu_sys_clkctrl OMAP4_DEBUGSS_CLKCTRL 24>;
};
};
@@ -548,6 +616,7 @@
&prm_clockdomains {
emu_sys_clkdm: emu_sys_clkdm {
compatible = "ti,clockdomain";
+ clock-output-names = "emu_sys_clkdm";
clocks = <&trace_clk_div_ck>;
};
};
@@ -556,6 +625,7 @@
per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck@14c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "per_hsd_byp_clk_mux_ck";
clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>;
ti,bit-shift = <23>;
reg = <0x014c>;
@@ -564,6 +634,7 @@
dpll_per_ck: dpll_per_ck@140 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_per_ck";
clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>;
reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
};
@@ -571,6 +642,7 @@
dpll_per_m2_ck: dpll_per_m2_ck@150 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m2_ck";
clocks = <&dpll_per_ck>;
ti,max-div = <31>;
reg = <0x0150>;
@@ -580,6 +652,7 @@
dpll_per_x2_ck: dpll_per_x2_ck@150 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_per_x2_ck";
clocks = <&dpll_per_ck>;
reg = <0x0150>;
};
@@ -587,6 +660,7 @@
dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m2x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -598,6 +672,7 @@
dpll_per_m3x2_gate_ck: dpll_per_m3x2_gate_ck@154 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "dpll_per_m3x2_gate_ck";
clocks = <&dpll_per_x2_ck>;
ti,bit-shift = <8>;
reg = <0x0154>;
@@ -606,6 +681,7 @@
dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck@154 {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
+ clock-output-names = "dpll_per_m3x2_div_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <31>;
reg = <0x0154>;
@@ -615,12 +691,14 @@
dpll_per_m3x2_ck: dpll_per_m3x2_ck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
+ clock-output-names = "dpll_per_m3x2_ck";
clocks = <&dpll_per_m3x2_gate_ck>, <&dpll_per_m3x2_div_ck>;
};
dpll_per_m4x2_ck: dpll_per_m4x2_ck@158 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m4x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -632,6 +710,7 @@
dpll_per_m5x2_ck: dpll_per_m5x2_ck@15c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m5x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -643,6 +722,7 @@
dpll_per_m6x2_ck: dpll_per_m6x2_ck@160 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m6x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -654,6 +734,7 @@
dpll_per_m7x2_ck: dpll_per_m7x2_ck@164 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m7x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -665,6 +746,7 @@
dpll_usb_ck: dpll_usb_ck@180 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-j-type-clock";
+ clock-output-names = "dpll_usb_ck";
clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>;
reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
};
@@ -672,6 +754,7 @@
dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck@1b4 {
#clock-cells = <0>;
compatible = "ti,fixed-factor-clock";
+ clock-output-names = "dpll_usb_clkdcoldo_ck";
clocks = <&dpll_usb_ck>;
ti,clock-div = <1>;
ti,autoidle-shift = <8>;
@@ -683,6 +766,7 @@
dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_usb_m2_ck";
clocks = <&dpll_usb_ck>;
ti,max-div = <127>;
ti,autoidle-shift = <8>;
@@ -694,6 +778,7 @@
ducati_clk_mux_ck: ducati_clk_mux_ck@100 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "ducati_clk_mux_ck";
clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>;
reg = <0x0100>;
};
@@ -701,6 +786,7 @@
func_12m_fclk: func_12m_fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_12m_fclk";
clocks = <&dpll_per_m2x2_ck>;
clock-mult = <1>;
clock-div = <16>;
@@ -709,6 +795,7 @@
func_24m_clk: func_24m_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_24m_clk";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <4>;
@@ -717,6 +804,7 @@
func_24mc_fclk: func_24mc_fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_24mc_fclk";
clocks = <&dpll_per_m2x2_ck>;
clock-mult = <1>;
clock-div = <8>;
@@ -725,6 +813,7 @@
func_48m_fclk: func_48m_fclk@108 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "func_48m_fclk";
clocks = <&dpll_per_m2x2_ck>;
reg = <0x0108>;
ti,dividers = <4>, <8>;
@@ -733,6 +822,7 @@
func_48mc_fclk: func_48mc_fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_48mc_fclk";
clocks = <&dpll_per_m2x2_ck>;
clock-mult = <1>;
clock-div = <4>;
@@ -741,6 +831,7 @@
func_64m_fclk: func_64m_fclk@108 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "func_64m_fclk";
clocks = <&dpll_per_m4x2_ck>;
reg = <0x0108>;
ti,dividers = <2>, <4>;
@@ -749,6 +840,7 @@
func_96m_fclk: func_96m_fclk@108 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "func_96m_fclk";
clocks = <&dpll_per_m2x2_ck>;
reg = <0x0108>;
ti,dividers = <2>, <4>;
@@ -757,6 +849,7 @@
init_60m_fclk: init_60m_fclk@104 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "init_60m_fclk";
clocks = <&dpll_usb_m2_ck>;
reg = <0x0104>;
ti,dividers = <1>, <8>;
@@ -765,6 +858,7 @@
per_abe_nc_fclk: per_abe_nc_fclk@108 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "per_abe_nc_fclk";
clocks = <&dpll_abe_m2_ck>;
reg = <0x0108>;
ti,max-div = <2>;
@@ -773,6 +867,7 @@
usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "usb_phy_cm_clk32k";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x0640>;
@@ -782,6 +877,7 @@
&cm2_clockdomains {
l3_init_clkdm: l3_init_clkdm {
compatible = "ti,clockdomain";
+ clock-output-names = "l3_init_clkdm";
clocks = <&dpll_usb_ck>;
};
};
@@ -790,6 +886,7 @@
auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "auxclk0_src_gate_ck";
clocks = <&dpll_core_m3x2_ck>;
ti,bit-shift = <8>;
reg = <0x0310>;
@@ -798,6 +895,7 @@
auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
+ clock-output-names = "auxclk0_src_mux_ck";
clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
ti,bit-shift = <1>;
reg = <0x0310>;
@@ -806,12 +904,14 @@
auxclk0_src_ck: auxclk0_src_ck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
+ clock-output-names = "auxclk0_src_ck";
clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
};
auxclk0_ck: auxclk0_ck@310 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "auxclk0_ck";
clocks = <&auxclk0_src_ck>;
ti,bit-shift = <16>;
ti,max-div = <16>;
@@ -821,6 +921,7 @@
auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "auxclk1_src_gate_ck";
clocks = <&dpll_core_m3x2_ck>;
ti,bit-shift = <8>;
reg = <0x0314>;
@@ -829,6 +930,7 @@
auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
+ clock-output-names = "auxclk1_src_mux_ck";
clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
ti,bit-shift = <1>;
reg = <0x0314>;
@@ -837,12 +939,14 @@
auxclk1_src_ck: auxclk1_src_ck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
+ clock-output-names = "auxclk1_src_ck";
clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
};
auxclk1_ck: auxclk1_ck@314 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "auxclk1_ck";
clocks = <&auxclk1_src_ck>;
ti,bit-shift = <16>;
ti,max-div = <16>;
@@ -852,6 +956,7 @@
auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "auxclk2_src_gate_ck";
clocks = <&dpll_core_m3x2_ck>;
ti,bit-shift = <8>;
reg = <0x0318>;
@@ -860,6 +965,7 @@
auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
+ clock-output-names = "auxclk2_src_mux_ck";
clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
ti,bit-shift = <1>;
reg = <0x0318>;
@@ -868,12 +974,14 @@
auxclk2_src_ck: auxclk2_src_ck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
+ clock-output-names = "auxclk2_src_ck";
clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
};
auxclk2_ck: auxclk2_ck@318 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "auxclk2_ck";
clocks = <&auxclk2_src_ck>;
ti,bit-shift = <16>;
ti,max-div = <16>;
@@ -883,6 +991,7 @@
auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "auxclk3_src_gate_ck";
clocks = <&dpll_core_m3x2_ck>;
ti,bit-shift = <8>;
reg = <0x031c>;
@@ -891,6 +1000,7 @@
auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
+ clock-output-names = "auxclk3_src_mux_ck";
clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
ti,bit-shift = <1>;
reg = <0x031c>;
@@ -899,12 +1009,14 @@
auxclk3_src_ck: auxclk3_src_ck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
+ clock-output-names = "auxclk3_src_ck";
clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
};
auxclk3_ck: auxclk3_ck@31c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "auxclk3_ck";
clocks = <&auxclk3_src_ck>;
ti,bit-shift = <16>;
ti,max-div = <16>;
@@ -914,6 +1026,7 @@
auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "auxclk4_src_gate_ck";
clocks = <&dpll_core_m3x2_ck>;
ti,bit-shift = <8>;
reg = <0x0320>;
@@ -922,6 +1035,7 @@
auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
+ clock-output-names = "auxclk4_src_mux_ck";
clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
ti,bit-shift = <1>;
reg = <0x0320>;
@@ -930,12 +1044,14 @@
auxclk4_src_ck: auxclk4_src_ck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
+ clock-output-names = "auxclk4_src_ck";
clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
};
auxclk4_ck: auxclk4_ck@320 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "auxclk4_ck";
clocks = <&auxclk4_src_ck>;
ti,bit-shift = <16>;
ti,max-div = <16>;
@@ -945,6 +1061,7 @@
auxclk5_src_gate_ck: auxclk5_src_gate_ck@324 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "auxclk5_src_gate_ck";
clocks = <&dpll_core_m3x2_ck>;
ti,bit-shift = <8>;
reg = <0x0324>;
@@ -953,6 +1070,7 @@
auxclk5_src_mux_ck: auxclk5_src_mux_ck@324 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
+ clock-output-names = "auxclk5_src_mux_ck";
clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
ti,bit-shift = <1>;
reg = <0x0324>;
@@ -961,12 +1079,14 @@
auxclk5_src_ck: auxclk5_src_ck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
+ clock-output-names = "auxclk5_src_ck";
clocks = <&auxclk5_src_gate_ck>, <&auxclk5_src_mux_ck>;
};
auxclk5_ck: auxclk5_ck@324 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "auxclk5_ck";
clocks = <&auxclk5_src_ck>;
ti,bit-shift = <16>;
ti,max-div = <16>;
@@ -976,6 +1096,7 @@
auxclkreq0_ck: auxclkreq0_ck@210 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "auxclkreq0_ck";
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
ti,bit-shift = <2>;
reg = <0x0210>;
@@ -984,6 +1105,7 @@
auxclkreq1_ck: auxclkreq1_ck@214 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "auxclkreq1_ck";
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
ti,bit-shift = <2>;
reg = <0x0214>;
@@ -992,6 +1114,7 @@
auxclkreq2_ck: auxclkreq2_ck@218 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "auxclkreq2_ck";
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
ti,bit-shift = <2>;
reg = <0x0218>;
@@ -1000,6 +1123,7 @@
auxclkreq3_ck: auxclkreq3_ck@21c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "auxclkreq3_ck";
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
ti,bit-shift = <2>;
reg = <0x021c>;
@@ -1008,6 +1132,7 @@
auxclkreq4_ck: auxclkreq4_ck@220 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "auxclkreq4_ck";
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
ti,bit-shift = <2>;
reg = <0x0220>;
@@ -1016,6 +1141,7 @@
auxclkreq5_ck: auxclkreq5_ck@224 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "auxclkreq5_ck";
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
ti,bit-shift = <2>;
reg = <0x0224>;
@@ -1025,6 +1151,7 @@
&cm1 {
mpuss_cm: mpuss_cm@300 {
compatible = "ti,omap4-cm";
+ clock-output-names = "mpuss_cm";
reg = <0x300 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1032,6 +1159,7 @@
mpuss_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "mpuss_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1039,6 +1167,7 @@
tesla_cm: tesla_cm@400 {
compatible = "ti,omap4-cm";
+ clock-output-names = "tesla_cm";
reg = <0x400 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1046,6 +1175,7 @@
tesla_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "tesla_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1053,6 +1183,7 @@
abe_cm: abe_cm@500 {
compatible = "ti,omap4-cm";
+ clock-output-names = "abe_cm";
reg = <0x500 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1060,6 +1191,7 @@
abe_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "abe_clkctrl";
reg = <0x20 0x6c>;
#clock-cells = <2>;
};
@@ -1070,6 +1202,7 @@
&cm2 {
l4_ao_cm: l4_ao_cm@600 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l4_ao_cm";
reg = <0x600 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1077,6 +1210,7 @@
l4_ao_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4_ao_clkctrl";
reg = <0x20 0x1c>;
#clock-cells = <2>;
};
@@ -1084,6 +1218,7 @@
l3_1_cm: l3_1_cm@700 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3_1_cm";
reg = <0x700 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1091,6 +1226,7 @@
l3_1_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3_1_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1098,6 +1234,7 @@
l3_2_cm: l3_2_cm@800 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3_2_cm";
reg = <0x800 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1105,6 +1242,7 @@
l3_2_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3_2_clkctrl";
reg = <0x20 0x14>;
#clock-cells = <2>;
};
@@ -1112,6 +1250,7 @@
ducati_cm: ducati_cm@900 {
compatible = "ti,omap4-cm";
+ clock-output-names = "ducati_cm";
reg = <0x900 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1119,6 +1258,7 @@
ducati_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "ducati_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1126,6 +1266,7 @@
l3_dma_cm: l3_dma_cm@a00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3_dma_cm";
reg = <0xa00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1133,6 +1274,7 @@
l3_dma_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3_dma_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1140,6 +1282,7 @@
l3_emif_cm: l3_emif_cm@b00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3_emif_cm";
reg = <0xb00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1147,6 +1290,7 @@
l3_emif_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3_emif_clkctrl";
reg = <0x20 0x1c>;
#clock-cells = <2>;
};
@@ -1154,6 +1298,7 @@
d2d_cm: d2d_cm@c00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "d2d_cm";
reg = <0xc00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1161,6 +1306,7 @@
d2d_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "d2d_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1168,6 +1314,7 @@
l4_cfg_cm: l4_cfg_cm@d00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l4_cfg_cm";
reg = <0xd00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1175,6 +1322,7 @@
l4_cfg_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4_cfg_clkctrl";
reg = <0x20 0x14>;
#clock-cells = <2>;
};
@@ -1182,6 +1330,7 @@
l3_instr_cm: l3_instr_cm@e00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3_instr_cm";
reg = <0xe00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1189,6 +1338,7 @@
l3_instr_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3_instr_clkctrl";
reg = <0x20 0x24>;
#clock-cells = <2>;
};
@@ -1196,6 +1346,7 @@
ivahd_cm: ivahd_cm@f00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "ivahd_cm";
reg = <0xf00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1203,6 +1354,7 @@
ivahd_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "ivahd_clkctrl";
reg = <0x20 0xc>;
#clock-cells = <2>;
};
@@ -1210,6 +1362,7 @@
iss_cm: iss_cm@1000 {
compatible = "ti,omap4-cm";
+ clock-output-names = "iss_cm";
reg = <0x1000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1217,6 +1370,7 @@
iss_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "iss_clkctrl";
reg = <0x20 0xc>;
#clock-cells = <2>;
};
@@ -1224,6 +1378,7 @@
l3_dss_cm: l3_dss_cm@1100 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3_dss_cm";
reg = <0x1100 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1231,6 +1386,7 @@
l3_dss_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3_dss_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1238,6 +1394,7 @@
l3_gfx_cm: l3_gfx_cm@1200 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3_gfx_cm";
reg = <0x1200 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1245,6 +1402,7 @@
l3_gfx_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3_gfx_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1252,6 +1410,7 @@
l3_init_cm: l3_init_cm@1300 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3_init_cm";
reg = <0x1300 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1259,26 +1418,30 @@
l3_init_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3_init_clkctrl";
reg = <0x20 0xc4>;
#clock-cells = <2>;
};
};
- l4_per_cm: l4_per_cm@1400 {
+ l4_per_cm: clock@1400 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l4_per_cm";
reg = <0x1400 0x200>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1400 0x200>;
l4_per_clkctrl: clock@20 {
- compatible = "ti,clkctrl-l4-per", "ti,clkctrl";
+ compatible = "ti,clkctrl";
+ clock-output-names = "l4_per_clkctrl";
reg = <0x20 0x144>;
#clock-cells = <2>;
};
l4_secure_clkctrl: clock@1a0 {
- compatible = "ti,clkctrl-l4-secure", "ti,clkctrl";
+ compatible = "ti,clkctrl";
+ clock-output-names = "l4_secure_clkctrl";
reg = <0x1a0 0x3c>;
#clock-cells = <2>;
};
@@ -1288,6 +1451,7 @@
&prm {
l4_wkup_cm: l4_wkup_cm@1800 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l4_wkup_cm";
reg = <0x1800 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1295,6 +1459,7 @@
l4_wkup_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4_wkup_clkctrl";
reg = <0x20 0x5c>;
#clock-cells = <2>;
};
@@ -1302,6 +1467,7 @@
emu_sys_cm: emu_sys_cm@1a00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "emu_sys_cm";
reg = <0x1a00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1309,6 +1475,7 @@
emu_sys_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "emu_sys_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
diff --git a/arch/arm/boot/dts/omap5-igep0050.dts b/arch/arm/boot/dts/omap5-igep0050.dts
index 76e499d89d24..3851120857d7 100644
--- a/arch/arm/boot/dts/omap5-igep0050.dts
+++ b/arch/arm/boot/dts/omap5-igep0050.dts
@@ -128,7 +128,7 @@
#address-cells = <1>;
#size-cells = <0>;
- ethernet: usbether@3 {
+ ethernet: ethernet@3 {
compatible = "usb424,7500";
reg = <3>;
};
diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
index 51d5fcae5081..453da9f18a99 100644
--- a/arch/arm/boot/dts/omap5-uevm.dts
+++ b/arch/arm/boot/dts/omap5-uevm.dts
@@ -209,7 +209,7 @@
#size-cells = <0>;
};
- ethernet: usbether@3 {
+ ethernet: ethernet@3 {
compatible = "usb424,9730";
reg = <3>;
};
diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi
index 42f2c447727d..5cf3b0e78c15 100644
--- a/arch/arm/boot/dts/omap54xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi
@@ -8,12 +8,14 @@
pad_clks_src_ck: pad_clks_src_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "pad_clks_src_ck";
clock-frequency = <12000000>;
};
pad_clks_ck: pad_clks_ck@108 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "pad_clks_ck";
clocks = <&pad_clks_src_ck>;
ti,bit-shift = <8>;
reg = <0x0108>;
@@ -22,18 +24,21 @@
secure_32k_clk_src_ck: secure_32k_clk_src_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "secure_32k_clk_src_ck";
clock-frequency = <32768>;
};
slimbus_src_clk: slimbus_src_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "slimbus_src_clk";
clock-frequency = <12000000>;
};
slimbus_clk: slimbus_clk@108 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "slimbus_clk";
clocks = <&slimbus_src_clk>;
ti,bit-shift = <10>;
reg = <0x0108>;
@@ -42,66 +47,77 @@
sys_32k_ck: sys_32k_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "sys_32k_ck";
clock-frequency = <32768>;
};
virt_12000000_ck: virt_12000000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_12000000_ck";
clock-frequency = <12000000>;
};
virt_13000000_ck: virt_13000000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_13000000_ck";
clock-frequency = <13000000>;
};
virt_16800000_ck: virt_16800000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_16800000_ck";
clock-frequency = <16800000>;
};
virt_19200000_ck: virt_19200000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_19200000_ck";
clock-frequency = <19200000>;
};
virt_26000000_ck: virt_26000000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_26000000_ck";
clock-frequency = <26000000>;
};
virt_27000000_ck: virt_27000000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_27000000_ck";
clock-frequency = <27000000>;
};
virt_38400000_ck: virt_38400000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_38400000_ck";
clock-frequency = <38400000>;
};
xclk60mhsp1_ck: xclk60mhsp1_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "xclk60mhsp1_ck";
clock-frequency = <60000000>;
};
xclk60mhsp2_ck: xclk60mhsp2_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "xclk60mhsp2_ck";
clock-frequency = <60000000>;
};
dpll_abe_ck: dpll_abe_ck@1e0 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-m4xen-clock";
+ clock-output-names = "dpll_abe_ck";
clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
};
@@ -109,12 +125,14 @@
dpll_abe_x2_ck: dpll_abe_x2_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_abe_x2_ck";
clocks = <&dpll_abe_ck>;
};
dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_abe_m2x2_ck";
clocks = <&dpll_abe_x2_ck>;
ti,max-div = <31>;
reg = <0x01f0>;
@@ -124,6 +142,7 @@
abe_24m_fclk: abe_24m_fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "abe_24m_fclk";
clocks = <&dpll_abe_m2x2_ck>;
clock-mult = <1>;
clock-div = <8>;
@@ -132,6 +151,7 @@
abe_clk: abe_clk@108 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "abe_clk";
clocks = <&dpll_abe_m2x2_ck>;
ti,max-div = <4>;
reg = <0x0108>;
@@ -141,6 +161,7 @@
abe_iclk: abe_iclk@528 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "abe_iclk";
clocks = <&aess_fclk>;
ti,bit-shift = <24>;
reg = <0x0528>;
@@ -150,6 +171,7 @@
abe_lp_clk_div: abe_lp_clk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "abe_lp_clk_div";
clocks = <&dpll_abe_m2x2_ck>;
clock-mult = <1>;
clock-div = <16>;
@@ -158,6 +180,7 @@
dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_abe_m3x2_ck";
clocks = <&dpll_abe_x2_ck>;
ti,max-div = <31>;
reg = <0x01f4>;
@@ -167,6 +190,7 @@
dpll_core_byp_mux: dpll_core_byp_mux@12c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "dpll_core_byp_mux";
clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
ti,bit-shift = <23>;
reg = <0x012c>;
@@ -175,6 +199,7 @@
dpll_core_ck: dpll_core_ck@120 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-core-clock";
+ clock-output-names = "dpll_core_ck";
clocks = <&sys_clkin>, <&dpll_core_byp_mux>;
reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
};
@@ -182,12 +207,14 @@
dpll_core_x2_ck: dpll_core_x2_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_core_x2_ck";
clocks = <&dpll_core_ck>;
};
dpll_core_h21x2_ck: dpll_core_h21x2_ck@150 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h21x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
reg = <0x0150>;
@@ -197,6 +224,7 @@
c2c_fclk: c2c_fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "c2c_fclk";
clocks = <&dpll_core_h21x2_ck>;
clock-mult = <1>;
clock-div = <1>;
@@ -205,6 +233,7 @@
c2c_iclk: c2c_iclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "c2c_iclk";
clocks = <&c2c_fclk>;
clock-mult = <1>;
clock-div = <2>;
@@ -213,6 +242,7 @@
dpll_core_h11x2_ck: dpll_core_h11x2_ck@138 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h11x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
reg = <0x0138>;
@@ -222,6 +252,7 @@
dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h12x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
reg = <0x013c>;
@@ -231,6 +262,7 @@
dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h13x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
reg = <0x0140>;
@@ -240,6 +272,7 @@
dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h14x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
reg = <0x0144>;
@@ -249,6 +282,7 @@
dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h22x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
reg = <0x0154>;
@@ -258,6 +292,7 @@
dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h23x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
reg = <0x0158>;
@@ -267,6 +302,7 @@
dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h24x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
reg = <0x015c>;
@@ -276,6 +312,7 @@
dpll_core_m2_ck: dpll_core_m2_ck@130 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m2_ck";
clocks = <&dpll_core_ck>;
ti,max-div = <31>;
reg = <0x0130>;
@@ -285,6 +322,7 @@
dpll_core_m3x2_ck: dpll_core_m3x2_ck@134 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m3x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <31>;
reg = <0x0134>;
@@ -294,6 +332,7 @@
iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "iva_dpll_hs_clk_div";
clocks = <&dpll_core_h12x2_ck>;
clock-mult = <1>;
clock-div = <1>;
@@ -302,6 +341,7 @@
dpll_iva_byp_mux: dpll_iva_byp_mux@1ac {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "dpll_iva_byp_mux";
clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x01ac>;
@@ -310,6 +350,7 @@
dpll_iva_ck: dpll_iva_ck@1a0 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_iva_ck";
clocks = <&sys_clkin>, <&dpll_iva_byp_mux>;
reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
assigned-clocks = <&dpll_iva_ck>;
@@ -319,12 +360,14 @@
dpll_iva_x2_ck: dpll_iva_x2_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_iva_x2_ck";
clocks = <&dpll_iva_ck>;
};
dpll_iva_h11x2_ck: dpll_iva_h11x2_ck@1b8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_iva_h11x2_ck";
clocks = <&dpll_iva_x2_ck>;
ti,max-div = <63>;
reg = <0x01b8>;
@@ -336,6 +379,7 @@
dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@1bc {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_iva_h12x2_ck";
clocks = <&dpll_iva_x2_ck>;
ti,max-div = <63>;
reg = <0x01bc>;
@@ -347,6 +391,7 @@
mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "mpu_dpll_hs_clk_div";
clocks = <&dpll_core_h12x2_ck>;
clock-mult = <1>;
clock-div = <1>;
@@ -355,6 +400,7 @@
dpll_mpu_ck: dpll_mpu_ck@160 {
#clock-cells = <0>;
compatible = "ti,omap5-mpu-dpll-clock";
+ clock-output-names = "dpll_mpu_ck";
clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>;
reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
};
@@ -362,6 +408,7 @@
dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_mpu_m2_ck";
clocks = <&dpll_mpu_ck>;
ti,max-div = <31>;
reg = <0x0170>;
@@ -371,6 +418,7 @@
per_dpll_hs_clk_div: per_dpll_hs_clk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "per_dpll_hs_clk_div";
clocks = <&dpll_abe_m3x2_ck>;
clock-mult = <1>;
clock-div = <2>;
@@ -379,6 +427,7 @@
usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "usb_dpll_hs_clk_div";
clocks = <&dpll_abe_m3x2_ck>;
clock-mult = <1>;
clock-div = <3>;
@@ -387,6 +436,7 @@
l3_iclk_div: l3_iclk_div@100 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "l3_iclk_div";
ti,max-div = <2>;
ti,bit-shift = <4>;
reg = <0x100>;
@@ -397,6 +447,7 @@
gpu_l3_iclk: gpu_l3_iclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "gpu_l3_iclk";
clocks = <&l3_iclk_div>;
clock-mult = <1>;
clock-div = <1>;
@@ -405,6 +456,7 @@
l4_root_clk_div: l4_root_clk_div@100 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "l4_root_clk_div";
ti,max-div = <2>;
ti,bit-shift = <8>;
reg = <0x100>;
@@ -415,6 +467,7 @@
slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "slimbus1_slimbus_clk";
clocks = <&slimbus_clk>;
ti,bit-shift = <11>;
reg = <0x0560>;
@@ -423,6 +476,7 @@
aess_fclk: aess_fclk@528 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "aess_fclk";
clocks = <&abe_clk>;
ti,bit-shift = <24>;
ti,max-div = <2>;
@@ -432,6 +486,7 @@
mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "mcasp_sync_mux_ck";
clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
ti,bit-shift = <26>;
reg = <0x0540>;
@@ -440,6 +495,7 @@
mcasp_gfclk: mcasp_gfclk@540 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "mcasp_gfclk";
clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
ti,bit-shift = <24>;
reg = <0x0540>;
@@ -448,6 +504,7 @@
dummy_ck: dummy_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "dummy_ck";
clock-frequency = <0>;
};
};
@@ -455,6 +512,7 @@
sys_clkin: sys_clkin@110 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "sys_clkin";
clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
reg = <0x0110>;
ti,index-starts-at-one;
@@ -463,6 +521,7 @@
abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@108 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "abe_dpll_bypass_clk_mux";
clocks = <&sys_clkin>, <&sys_32k_ck>;
reg = <0x0108>;
};
@@ -470,6 +529,7 @@
abe_dpll_clk_mux: abe_dpll_clk_mux@10c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "abe_dpll_clk_mux";
clocks = <&sys_clkin>, <&sys_32k_ck>;
reg = <0x010c>;
};
@@ -477,6 +537,7 @@
custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "custefuse_sys_gfclk_div";
clocks = <&sys_clkin>;
clock-mult = <1>;
clock-div = <2>;
@@ -485,6 +546,7 @@
dss_syc_gfclk_div: dss_syc_gfclk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dss_syc_gfclk_div";
clocks = <&sys_clkin>;
clock-mult = <1>;
clock-div = <1>;
@@ -493,6 +555,7 @@
wkupaon_iclk_mux: wkupaon_iclk_mux@108 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "wkupaon_iclk_mux";
clocks = <&sys_clkin>, <&abe_lp_clk_div>;
reg = <0x0108>;
};
@@ -500,6 +563,7 @@
l3instr_ts_gclk_div: l3instr_ts_gclk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "l3instr_ts_gclk_div";
clocks = <&wkupaon_iclk_mux>;
clock-mult = <1>;
clock-div = <1>;
@@ -511,6 +575,7 @@
dpll_per_byp_mux: dpll_per_byp_mux@14c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "dpll_per_byp_mux";
clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x014c>;
@@ -519,6 +584,7 @@
dpll_per_ck: dpll_per_ck@140 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_per_ck";
clocks = <&sys_clkin>, <&dpll_per_byp_mux>;
reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
};
@@ -526,12 +592,14 @@
dpll_per_x2_ck: dpll_per_x2_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_per_x2_ck";
clocks = <&dpll_per_ck>;
};
dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_h11x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <63>;
reg = <0x0158>;
@@ -541,6 +609,7 @@
dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_h12x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <63>;
reg = <0x015c>;
@@ -550,6 +619,7 @@
dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_h14x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <63>;
reg = <0x0164>;
@@ -559,6 +629,7 @@
dpll_per_m2_ck: dpll_per_m2_ck@150 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m2_ck";
clocks = <&dpll_per_ck>;
ti,max-div = <31>;
reg = <0x0150>;
@@ -568,6 +639,7 @@
dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m2x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <31>;
reg = <0x0150>;
@@ -577,6 +649,7 @@
dpll_per_m3x2_ck: dpll_per_m3x2_ck@154 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m3x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <31>;
reg = <0x0154>;
@@ -586,6 +659,7 @@
dpll_unipro1_ck: dpll_unipro1_ck@200 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_unipro1_ck";
clocks = <&sys_clkin>, <&sys_clkin>;
reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
};
@@ -593,6 +667,7 @@
dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dpll_unipro1_clkdcoldo";
clocks = <&dpll_unipro1_ck>;
clock-mult = <1>;
clock-div = <1>;
@@ -601,6 +676,7 @@
dpll_unipro1_m2_ck: dpll_unipro1_m2_ck@210 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_unipro1_m2_ck";
clocks = <&dpll_unipro1_ck>;
ti,max-div = <127>;
reg = <0x0210>;
@@ -610,6 +686,7 @@
dpll_unipro2_ck: dpll_unipro2_ck@1c0 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_unipro2_ck";
clocks = <&sys_clkin>, <&sys_clkin>;
reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>;
};
@@ -617,6 +694,7 @@
dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dpll_unipro2_clkdcoldo";
clocks = <&dpll_unipro2_ck>;
clock-mult = <1>;
clock-div = <1>;
@@ -625,6 +703,7 @@
dpll_unipro2_m2_ck: dpll_unipro2_m2_ck@1d0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_unipro2_m2_ck";
clocks = <&dpll_unipro2_ck>;
ti,max-div = <127>;
reg = <0x01d0>;
@@ -634,6 +713,7 @@
dpll_usb_byp_mux: dpll_usb_byp_mux@18c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "dpll_usb_byp_mux";
clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x018c>;
@@ -642,6 +722,7 @@
dpll_usb_ck: dpll_usb_ck@180 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-j-type-clock";
+ clock-output-names = "dpll_usb_ck";
clocks = <&sys_clkin>, <&dpll_usb_byp_mux>;
reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
};
@@ -649,6 +730,7 @@
dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dpll_usb_clkdcoldo";
clocks = <&dpll_usb_ck>;
clock-mult = <1>;
clock-div = <1>;
@@ -657,6 +739,7 @@
dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_usb_m2_ck";
clocks = <&dpll_usb_ck>;
ti,max-div = <127>;
reg = <0x0190>;
@@ -666,6 +749,7 @@
func_128m_clk: func_128m_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_128m_clk";
clocks = <&dpll_per_h11x2_ck>;
clock-mult = <1>;
clock-div = <2>;
@@ -674,6 +758,7 @@
func_12m_fclk: func_12m_fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_12m_fclk";
clocks = <&dpll_per_m2x2_ck>;
clock-mult = <1>;
clock-div = <16>;
@@ -682,6 +767,7 @@
func_24m_clk: func_24m_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_24m_clk";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <4>;
@@ -690,6 +776,7 @@
func_48m_fclk: func_48m_fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_48m_fclk";
clocks = <&dpll_per_m2x2_ck>;
clock-mult = <1>;
clock-div = <4>;
@@ -698,6 +785,7 @@
func_96m_fclk: func_96m_fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_96m_fclk";
clocks = <&dpll_per_m2x2_ck>;
clock-mult = <1>;
clock-div = <2>;
@@ -706,6 +794,7 @@
l3init_60m_fclk: l3init_60m_fclk@104 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "l3init_60m_fclk";
clocks = <&dpll_usb_m2_ck>;
reg = <0x0104>;
ti,dividers = <1>, <8>;
@@ -714,6 +803,7 @@
iss_ctrlclk: iss_ctrlclk@1320 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "iss_ctrlclk";
clocks = <&func_96m_fclk>;
ti,bit-shift = <8>;
reg = <0x1320>;
@@ -722,6 +812,7 @@
lli_txphy_clk: lli_txphy_clk@f20 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "lli_txphy_clk";
clocks = <&dpll_unipro1_clkdcoldo>;
ti,bit-shift = <8>;
reg = <0x0f20>;
@@ -730,6 +821,7 @@
lli_txphy_ls_clk: lli_txphy_ls_clk@f20 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "lli_txphy_ls_clk";
clocks = <&dpll_unipro1_m2_ck>;
ti,bit-shift = <9>;
reg = <0x0f20>;
@@ -738,6 +830,7 @@
usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "usb_phy_cm_clk32k";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x0640>;
@@ -746,6 +839,7 @@
fdif_fclk: fdif_fclk@1328 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "fdif_fclk";
clocks = <&dpll_per_h11x2_ck>;
ti,bit-shift = <24>;
ti,max-div = <2>;
@@ -755,6 +849,7 @@
gpu_core_gclk_mux: gpu_core_gclk_mux@1520 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "gpu_core_gclk_mux";
clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
ti,bit-shift = <24>;
reg = <0x1520>;
@@ -763,6 +858,7 @@
gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1520 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "gpu_hyd_gclk_mux";
clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
ti,bit-shift = <25>;
reg = <0x1520>;
@@ -771,6 +867,7 @@
hsi_fclk: hsi_fclk@1638 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "hsi_fclk";
clocks = <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
ti,max-div = <2>;
@@ -781,6 +878,7 @@
&cm_core_clockdomains {
l3init_clkdm: l3init_clkdm {
compatible = "ti,clockdomain";
+ clock-output-names = "l3init_clkdm";
clocks = <&dpll_usb_ck>;
};
};
@@ -789,6 +887,7 @@
auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "auxclk0_src_gate_ck";
clocks = <&dpll_core_m3x2_ck>;
ti,bit-shift = <8>;
reg = <0x0310>;
@@ -797,6 +896,7 @@
auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
+ clock-output-names = "auxclk0_src_mux_ck";
clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
ti,bit-shift = <1>;
reg = <0x0310>;
@@ -805,12 +905,14 @@
auxclk0_src_ck: auxclk0_src_ck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
+ clock-output-names = "auxclk0_src_ck";
clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
};
auxclk0_ck: auxclk0_ck@310 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "auxclk0_ck";
clocks = <&auxclk0_src_ck>;
ti,bit-shift = <16>;
ti,max-div = <16>;
@@ -820,6 +922,7 @@
auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "auxclk1_src_gate_ck";
clocks = <&dpll_core_m3x2_ck>;
ti,bit-shift = <8>;
reg = <0x0314>;
@@ -828,6 +931,7 @@
auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
+ clock-output-names = "auxclk1_src_mux_ck";
clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
ti,bit-shift = <1>;
reg = <0x0314>;
@@ -836,12 +940,14 @@
auxclk1_src_ck: auxclk1_src_ck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
+ clock-output-names = "auxclk1_src_ck";
clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
};
auxclk1_ck: auxclk1_ck@314 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "auxclk1_ck";
clocks = <&auxclk1_src_ck>;
ti,bit-shift = <16>;
ti,max-div = <16>;
@@ -851,6 +957,7 @@
auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "auxclk2_src_gate_ck";
clocks = <&dpll_core_m3x2_ck>;
ti,bit-shift = <8>;
reg = <0x0318>;
@@ -859,6 +966,7 @@
auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
+ clock-output-names = "auxclk2_src_mux_ck";
clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
ti,bit-shift = <1>;
reg = <0x0318>;
@@ -867,12 +975,14 @@
auxclk2_src_ck: auxclk2_src_ck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
+ clock-output-names = "auxclk2_src_ck";
clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
};
auxclk2_ck: auxclk2_ck@318 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "auxclk2_ck";
clocks = <&auxclk2_src_ck>;
ti,bit-shift = <16>;
ti,max-div = <16>;
@@ -882,6 +992,7 @@
auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "auxclk3_src_gate_ck";
clocks = <&dpll_core_m3x2_ck>;
ti,bit-shift = <8>;
reg = <0x031c>;
@@ -890,6 +1001,7 @@
auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
+ clock-output-names = "auxclk3_src_mux_ck";
clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
ti,bit-shift = <1>;
reg = <0x031c>;
@@ -898,12 +1010,14 @@
auxclk3_src_ck: auxclk3_src_ck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
+ clock-output-names = "auxclk3_src_ck";
clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
};
auxclk3_ck: auxclk3_ck@31c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "auxclk3_ck";
clocks = <&auxclk3_src_ck>;
ti,bit-shift = <16>;
ti,max-div = <16>;
@@ -913,6 +1027,7 @@
auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "auxclk4_src_gate_ck";
clocks = <&dpll_core_m3x2_ck>;
ti,bit-shift = <8>;
reg = <0x0320>;
@@ -921,6 +1036,7 @@
auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
+ clock-output-names = "auxclk4_src_mux_ck";
clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
ti,bit-shift = <1>;
reg = <0x0320>;
@@ -929,12 +1045,14 @@
auxclk4_src_ck: auxclk4_src_ck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
+ clock-output-names = "auxclk4_src_ck";
clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
};
auxclk4_ck: auxclk4_ck@320 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "auxclk4_ck";
clocks = <&auxclk4_src_ck>;
ti,bit-shift = <16>;
ti,max-div = <16>;
@@ -944,6 +1062,7 @@
auxclkreq0_ck: auxclkreq0_ck@210 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "auxclkreq0_ck";
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
ti,bit-shift = <2>;
reg = <0x0210>;
@@ -952,6 +1071,7 @@
auxclkreq1_ck: auxclkreq1_ck@214 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "auxclkreq1_ck";
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
ti,bit-shift = <2>;
reg = <0x0214>;
@@ -960,6 +1080,7 @@
auxclkreq2_ck: auxclkreq2_ck@218 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "auxclkreq2_ck";
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
ti,bit-shift = <2>;
reg = <0x0218>;
@@ -968,6 +1089,7 @@
auxclkreq3_ck: auxclkreq3_ck@21c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "auxclkreq3_ck";
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
ti,bit-shift = <2>;
reg = <0x021c>;
@@ -977,6 +1099,7 @@
&cm_core_aon {
mpu_cm: mpu_cm@300 {
compatible = "ti,omap4-cm";
+ clock-output-names = "mpu_cm";
reg = <0x300 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -984,6 +1107,7 @@
mpu_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "mpu_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -991,6 +1115,7 @@
dsp_cm: dsp_cm@400 {
compatible = "ti,omap4-cm";
+ clock-output-names = "dsp_cm";
reg = <0x400 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -998,6 +1123,7 @@
dsp_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "dsp_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1005,6 +1131,7 @@
abe_cm: abe_cm@500 {
compatible = "ti,omap4-cm";
+ clock-output-names = "abe_cm";
reg = <0x500 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1012,6 +1139,7 @@
abe_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "abe_clkctrl";
reg = <0x20 0x64>;
#clock-cells = <2>;
};
@@ -1022,6 +1150,7 @@
&cm_core {
l3main1_cm: l3main1_cm@700 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3main1_cm";
reg = <0x700 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1029,6 +1158,7 @@
l3main1_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3main1_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1036,6 +1166,7 @@
l3main2_cm: l3main2_cm@800 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3main2_cm";
reg = <0x800 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1043,6 +1174,7 @@
l3main2_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3main2_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1050,6 +1182,7 @@
ipu_cm: ipu_cm@900 {
compatible = "ti,omap4-cm";
+ clock-output-names = "ipu_cm";
reg = <0x900 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1057,6 +1190,7 @@
ipu_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "ipu_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1064,6 +1198,7 @@
dma_cm: dma_cm@a00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "dma_cm";
reg = <0xa00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1071,6 +1206,7 @@
dma_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "dma_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1078,6 +1214,7 @@
emif_cm: emif_cm@b00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "emif_cm";
reg = <0xb00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1085,6 +1222,7 @@
emif_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "emif_clkctrl";
reg = <0x20 0x1c>;
#clock-cells = <2>;
};
@@ -1092,6 +1230,7 @@
l4cfg_cm: l4cfg_cm@d00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l4cfg_cm";
reg = <0xd00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1099,6 +1238,7 @@
l4cfg_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4cfg_clkctrl";
reg = <0x20 0x14>;
#clock-cells = <2>;
};
@@ -1106,6 +1246,7 @@
l3instr_cm: l3instr_cm@e00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3instr_cm";
reg = <0xe00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1113,26 +1254,30 @@
l3instr_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3instr_clkctrl";
reg = <0x20 0xc>;
#clock-cells = <2>;
};
};
- l4per_cm: l4per_cm@1000 {
+ l4per_cm: clock@1000 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l4per_cm";
reg = <0x1000 0x200>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1000 0x200>;
l4per_clkctrl: clock@20 {
- compatible = "ti,clkctrl-l4per", "ti,clkctrl";
+ compatible = "ti,clkctrl";
+ clock-output-names = "l4per_clkctrl";
reg = <0x20 0x15c>;
#clock-cells = <2>;
};
l4sec_clkctrl: clock@1a0 {
- compatible = "ti,clkctrl-l4sec", "ti,clkctrl";
+ compatible = "ti,clkctrl";
+ clock-output-names = "l4sec_clkctrl";
reg = <0x1a0 0x3c>;
#clock-cells = <2>;
};
@@ -1140,6 +1285,7 @@
dss_cm: dss_cm@1400 {
compatible = "ti,omap4-cm";
+ clock-output-names = "dss_cm";
reg = <0x1400 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1147,6 +1293,7 @@
dss_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "dss_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1154,6 +1301,7 @@
gpu_cm: gpu_cm@1500 {
compatible = "ti,omap4-cm";
+ clock-output-names = "gpu_cm";
reg = <0x1500 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1161,6 +1309,7 @@
gpu_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "gpu_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1168,6 +1317,7 @@
l3init_cm: l3init_cm@1600 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3init_cm";
reg = <0x1600 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1175,6 +1325,7 @@
l3init_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3init_clkctrl";
reg = <0x20 0xd4>;
#clock-cells = <2>;
};
@@ -1184,6 +1335,7 @@
&prm {
wkupaon_cm: wkupaon_cm@1900 {
compatible = "ti,omap4-cm";
+ clock-output-names = "wkupaon_cm";
reg = <0x1900 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1191,6 +1343,7 @@
wkupaon_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "wkupaon_clkctrl";
reg = <0x20 0x5c>;
#clock-cells = <2>;
};
@@ -1201,6 +1354,7 @@
fref_xtal_ck: fref_xtal_ck {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "fref_xtal_ck";
clocks = <&sys_clkin>;
ti,bit-shift = <28>;
reg = <0x14>;
diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c
index 4aab631ef517..d9cf2820c02e 100644
--- a/drivers/iommu/omap-iommu.c
+++ b/drivers/iommu/omap-iommu.c
@@ -1661,7 +1661,7 @@ static struct iommu_device *omap_iommu_probe_device(struct device *dev)
num_iommus = of_property_count_elems_of_size(dev->of_node, "iommus",
sizeof(phandle));
if (num_iommus < 0)
- return 0;
+ return ERR_PTR(-ENODEV);
arch_data = kcalloc(num_iommus + 1, sizeof(*arch_data), GFP_KERNEL);
if (!arch_data)
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.