diff options
175 files changed, 836 insertions, 6779 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 1e3aeccd7322..3b404b7dfa39 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -15,29 +15,6 @@ choice prompt "System type" default SGI_IP22 -config LEMOTE_FULONG - bool "Lemote Fulong mini-PC" - select ARCH_SPARSEMEM_ENABLE - select SYS_HAS_CPU_LOONGSON2 - select DMA_NONCOHERENT - select BOOT_ELF32 - select BOARD_SCACHE - select HAVE_STD_PC_SERIAL_PORT - select HW_HAS_PCI - select I8259 - select ISA - select IRQ_CPU - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_SUPPORTS_HIGHMEM - select SYS_HAS_EARLY_PRINTK - select GENERIC_HARDIRQS_NO__DO_IRQ - select CPU_HAS_WB - help - Lemote Fulong mini-PC board based on the Chinese Loongson-2E CPU and - an FPGA northbridge - config MACH_ALCHEMY bool "Alchemy processor based machines" @@ -131,6 +108,29 @@ config MACH_JAZZ Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and Olivetti M700-10 workstations. +config LEMOTE_FULONG + bool "Lemote Fulong mini-PC" + select ARCH_SPARSEMEM_ENABLE + select SYS_HAS_CPU_LOONGSON2 + select DMA_NONCOHERENT + select BOOT_ELF32 + select BOARD_SCACHE + select HAVE_STD_PC_SERIAL_PORT + select HW_HAS_PCI + select I8259 + select ISA + select IRQ_CPU + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_HIGHMEM + select SYS_HAS_EARLY_PRINTK + select GENERIC_HARDIRQS_NO__DO_IRQ + select CPU_HAS_WB + help + Lemote Fulong mini-PC board based on the Chinese Loongson-2E CPU and + an FPGA northbridge + config MIPS_ATLAS bool "MIPS Atlas board" select BOOT_ELF32 @@ -210,27 +210,6 @@ config MIPS_SEAD This enables support for the MIPS Technologies SEAD evaluation board. -config WR_PPMC - bool "Wind River PPMC board" - select IRQ_CPU - select BOOT_ELF32 - select DMA_NONCOHERENT - select HW_HAS_PCI - select PCI_GT64XXX_PCI0 - select SWAP_IO_SPACE - select SYS_HAS_CPU_MIPS32_R1 - select SYS_HAS_CPU_MIPS32_R2 - select SYS_HAS_CPU_MIPS64_R1 - select SYS_HAS_CPU_NEVADA - select SYS_HAS_CPU_RM7000 - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL - select SYS_SUPPORTS_BIG_ENDIAN - select SYS_SUPPORTS_LITTLE_ENDIAN - help - This enables support for the Wind River MIPS32 4KC PPMC evaluation - board, which is based on GT64120 bridge chip. - config MIPS_SIM bool 'MIPS simulator (MIPSsim)' select DMA_NONCOHERENT @@ -248,23 +227,24 @@ config MIPS_SIM This option enables support for MIPS Technologies MIPSsim software emulator. -config MOMENCO_OCELOT - bool "Momentum Ocelot board" +config MARKEINS + bool "NEC EMMA2RH Mark-eins" select DMA_NONCOHERENT select HW_HAS_PCI select IRQ_CPU - select IRQ_CPU_RM7K - select PCI_GT64XXX_PCI0 - select RM7000_CPU_SCACHE select SWAP_IO_SPACE - select SYS_HAS_CPU_RM7000 select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL select SYS_SUPPORTS_BIG_ENDIAN - select SYS_SUPPORTS_KGDB + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_HAS_CPU_R5000 help - The Ocelot is a MIPS-based Single Board Computer (SBC) made by - Momentum Computer <http://www.momenco.com/>. + This enables support for the R5432-based NEC Mark-eins + boards with R5500 CPU. + +config MACH_VR41XX + bool "NEC VR4100 series based machines" + select SYS_HAS_CPU_VR41XX + select GENERIC_HARDIRQS_NO__DO_IRQ config PNX8550_JBS bool "Philips PNX8550 based JBS board" @@ -276,31 +256,6 @@ config PNX8550_STB810 select PNX8550 select SYS_SUPPORTS_LITTLE_ENDIAN -config DDB5477 - bool "NEC DDB Vrc-5477" - select DDB5XXX_COMMON - select DMA_NONCOHERENT - select HW_HAS_PCI - select I8259 - select IRQ_CPU - select SYS_HAS_CPU_R5432 - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL - select SYS_SUPPORTS_KGDB - select SYS_SUPPORTS_KGDB - select SYS_SUPPORTS_LITTLE_ENDIAN - help - This enables support for the R5432-based NEC DDB Vrc-5477, - or Rockhopper/SolutionGear boards with R5432/R5500 CPUs. - - Features : kernel debugging, serial terminal, NFS root fs, on-board - ether port USB, AC97, PCI, etc. - -config MACH_VR41XX - bool "NEC VR4100 series based machines" - select SYS_HAS_CPU_VR41XX - select GENERIC_HARDIRQS_NO__DO_IRQ - config PMC_MSP bool "PMC-Sierra MSP chipsets" depends on EXPERIMENTAL @@ -367,20 +322,6 @@ config QEMU simulate actual MIPS hardware platforms. More information on Qemu can be found at http://www.linux-mips.org/wiki/Qemu. -config MARKEINS - bool "NEC EMMA2RH Mark-eins" - select DMA_NONCOHERENT - select HW_HAS_PCI - select IRQ_CPU - select SWAP_IO_SPACE - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_BIG_ENDIAN - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_HAS_CPU_R5000 - help - This enables support for the R5432-based NEC Mark-eins - boards with R5500 CPU. - config SGI_IP22 bool "SGI IP22 (Indy/Indigo2)" select ARC @@ -443,41 +384,38 @@ config SGI_IP32 help If you want this kernel to run on SGI O2 workstation, say Y here. -config SIBYTE_BIGSUR - bool "Sibyte BCM91480B-BigSur" +config SIBYTE_CRHINE + bool "Sibyte BCM91120C-CRhine" + depends on EXPERIMENTAL select BOOT_ELF32 select DMA_COHERENT - select NR_CPUS_DEFAULT_4 - select PCI_DOMAINS - select SIBYTE_BCM1x80 + select SIBYTE_BCM1120 select SWAP_IO_SPACE select SYS_HAS_CPU_SB1 select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_LITTLE_ENDIAN -config SIBYTE_SWARM - bool "Sibyte BCM91250A-SWARM" +config SIBYTE_CARMEL + bool "Sibyte BCM91120x-Carmel" + depends on EXPERIMENTAL select BOOT_ELF32 select DMA_COHERENT - select NR_CPUS_DEFAULT_2 - select SIBYTE_SB1250 + select SIBYTE_BCM1120 select SWAP_IO_SPACE select SYS_HAS_CPU_SB1 select SYS_SUPPORTS_BIG_ENDIAN - select SYS_SUPPORTS_HIGHMEM - select SYS_SUPPORTS_KGDB select SYS_SUPPORTS_LITTLE_ENDIAN -config SIBYTE_SENTOSA - bool "Sibyte BCM91250E-Sentosa" +config SIBYTE_CRHONE + bool "Sibyte BCM91125C-CRhone" depends on EXPERIMENTAL select BOOT_ELF32 select DMA_COHERENT - select NR_CPUS_DEFAULT_2 - select SIBYTE_SB1250 + select SIBYTE_BCM1125 select SWAP_IO_SPACE select SYS_HAS_CPU_SB1 select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_HIGHMEM select SYS_SUPPORTS_LITTLE_ENDIAN config SIBYTE_RHONE @@ -491,19 +429,21 @@ config SIBYTE_RHONE select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_LITTLE_ENDIAN -config SIBYTE_CARMEL - bool "Sibyte BCM91120x-Carmel" - depends on EXPERIMENTAL +config SIBYTE_SWARM + bool "Sibyte BCM91250A-SWARM" select BOOT_ELF32 select DMA_COHERENT - select SIBYTE_BCM1120 + select NR_CPUS_DEFAULT_2 + select SIBYTE_SB1250 select SWAP_IO_SPACE select SYS_HAS_CPU_SB1 select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_HIGHMEM + select SYS_SUPPORTS_KGDB select SYS_SUPPORTS_LITTLE_ENDIAN -config SIBYTE_PTSWARM - bool "Sibyte BCM91250PT-PTSWARM" +config SIBYTE_LITTLESUR + bool "Sibyte BCM91250C2-LittleSur" depends on EXPERIMENTAL select BOOT_ELF32 select DMA_COHERENT @@ -515,8 +455,8 @@ config SIBYTE_PTSWARM select SYS_SUPPORTS_HIGHMEM select SYS_SUPPORTS_LITTLE_ENDIAN -config SIBYTE_LITTLESUR - bool "Sibyte BCM91250C2-LittleSur" +config SIBYTE_SENTOSA + bool "Sibyte BCM91250E-Sentosa" depends on EXPERIMENTAL select BOOT_ELF32 select DMA_COHERENT @@ -525,30 +465,31 @@ config SIBYTE_LITTLESUR select SWAP_IO_SPACE select SYS_HAS_CPU_SB1 select SYS_SUPPORTS_BIG_ENDIAN - select SYS_SUPPORTS_HIGHMEM select SYS_SUPPORTS_LITTLE_ENDIAN -config SIBYTE_CRHINE - bool "Sibyte BCM91120C-CRhine" +config SIBYTE_PTSWARM + bool "Sibyte BCM91250PT-PTSWARM" depends on EXPERIMENTAL select BOOT_ELF32 select DMA_COHERENT - select SIBYTE_BCM1120 + select NR_CPUS_DEFAULT_2 + select SIBYTE_SB1250 select SWAP_IO_SPACE select SYS_HAS_CPU_SB1 select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_HIGHMEM select SYS_SUPPORTS_LITTLE_ENDIAN -config SIBYTE_CRHONE - bool "Sibyte BCM91125C-CRhone" - depends on EXPERIMENTAL +config SIBYTE_BIGSUR + bool "Sibyte BCM91480B-BigSur" select BOOT_ELF32 select DMA_COHERENT - select SIBYTE_BCM1125 + select NR_CPUS_DEFAULT_4 + select PCI_DOMAINS + select SIBYTE_BCM1x80 select SWAP_IO_SPACE select SYS_HAS_CPU_SB1 select SYS_SUPPORTS_BIG_ENDIAN - select SYS_SUPPORTS_HIGHMEM select SYS_SUPPORTS_LITTLE_ENDIAN config SNI_RM @@ -595,7 +536,7 @@ config TOSHIBA_JMR3927 select GENERIC_HARDIRQS_NO__DO_IRQ config TOSHIBA_RBTX4927 - bool "Toshiba TBTX49[23]7 board" + bool "Toshiba RBTX49[23]7 board" select DMA_NONCOHERENT select HAS_TXX9_SERIAL select HW_HAS_PCI @@ -632,10 +573,30 @@ config TOSHIBA_RBTX4938 This Toshiba board is based on the TX4938 processor. Say Y here to support this machine type +config WR_PPMC + bool "Wind River PPMC board" + select IRQ_CPU + select BOOT_ELF32 + select DMA_NONCOHERENT + select HW_HAS_PCI + select PCI_GT64XXX_PCI0 + select SWAP_IO_SPACE + select SYS_HAS_CPU_MIPS32_R1 + select SYS_HAS_CPU_MIPS32_R2 + select SYS_HAS_CPU_MIPS64_R1 + select SYS_HAS_CPU_NEVADA + select SYS_HAS_CPU_RM7000 + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_LITTLE_ENDIAN + help + This enables support for the Wind River MIPS32 4KC PPMC evaluation + board, which is based on GT64120 bridge chip. + endchoice source "arch/mips/au1000/Kconfig" -source "arch/mips/ddb5xxx/Kconfig" source "arch/mips/jazz/Kconfig" source "arch/mips/pmc-sierra/Kconfig" source "arch/mips/sgi-ip27/Kconfig" @@ -807,10 +768,6 @@ config IRQ_MSP_SLP config IRQ_MSP_CIC bool -config DDB5XXX_COMMON - bool - select SYS_SUPPORTS_KGDB - config MIPS_BOARDS_GEN bool @@ -1377,17 +1334,6 @@ config MIPS_MT_SMTC This is a kernel model which is known a SMTC or lately has been marketesed into SMVP. -config MIPS_VPE_LOADER - bool "VPE loader support." - depends on SYS_SUPPORTS_MULTITHREADING - select CPU_MIPSR2_IRQ_VI - select CPU_MIPSR2_IRQ_EI - select CPU_MIPSR2_SRS - select MIPS_MT - help - Includes a loader for loading an elf relocatable object - onto another VPE and running it. - endchoice config MIPS_MT @@ -1398,8 +1344,19 @@ config SYS_SUPPORTS_MULTITHREADING config MIPS_MT_FPAFF bool "Dynamic FPU affinity for FP-intensive threads" - depends on MIPS_MT default y + depends on MIPS_MT_SMP || MIPS_MT_SMTC + +config MIPS_VPE_LOADER + bool "VPE loader support." + depends on SYS_SUPPORTS_MULTITHREADING + select CPU_MIPSR2_IRQ_VI + select CPU_MIPSR2_IRQ_EI + select CPU_MIPSR2_SRS + select MIPS_MT + help + Includes a loader for loading an elf relocatable object + onto another VPE and running it. config MIPS_MT_SMTC_INSTANT_REPLAY bool "Low-latency Dispatch of Deferred SMTC IPIs" @@ -1772,7 +1729,7 @@ config KEXEC config SECCOMP bool "Enable seccomp to safely compute untrusted bytecode" - depends on PROC_FS && BROKEN + depends on PROC_FS default y help This kernel feature is useful for number crunching applications diff --git a/arch/mips/Makefile b/arch/mips/Makefile index a9a987a06daf..32c1c8fb6f98 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -67,6 +67,8 @@ cflags-y += $(call cc-option,-msym32) endif endif +all-$(CONFIG_BOOT_ELF32) := $(vmlinux-32) +all-$(CONFIG_BOOT_ELF64) := $(vmlinux-64) # # GCC uses -G 0 -mabicalls -fpic as default. We don't want PIC in the kernel @@ -309,6 +311,7 @@ core-$(CONFIG_MIPS_ATLAS) += arch/mips/mips-boards/atlas/ cflags-$(CONFIG_MIPS_ATLAS) += -Iinclude/asm-mips/mach-atlas cflags-$(CONFIG_MIPS_ATLAS) += -Iinclude/asm-mips/mach-mips load-$(CONFIG_MIPS_ATLAS) += 0xffffffff80100000 +all-$(CONFIG_MIPS_ATLAS) := vmlinux.srec # # MIPS Malta board @@ -316,6 +319,7 @@ load-$(CONFIG_MIPS_ATLAS) += 0xffffffff80100000 core-$(CONFIG_MIPS_MALTA) += arch/mips/mips-boards/malta/ cflags-$(CONFIG_MIPS_MALTA) += -Iinclude/asm-mips/mach-mips load-$(CONFIG_MIPS_MALTA) += 0xffffffff80100000 +all-$(CONFIG_MIPS_MALTA) := vmlinux.srec # # MIPS SEAD board @@ -323,6 +327,7 @@ load-$(CONFIG_MIPS_MALTA) += 0xffffffff80100000 core-$(CONFIG_MIPS_SEAD) += arch/mips/mips-boards/sead/ cflags-$(CONFIG_MIPS_SEAD) += -Iinclude/asm-mips/mach-mips load-$(CONFIG_MIPS_SEAD) += 0xffffffff80100000 +all-$(CONFIG_MIPS_SEAD) := vmlinux.srec # # MIPS SIM @@ -332,17 +337,6 @@ cflags-$(CONFIG_MIPS_SIM) += -Iinclude/asm-mips/mach-mipssim load-$(CONFIG_MIPS_SIM) += 0x80100000 # -# Momentum Ocelot board -# -# The Ocelot setup.o must be linked early - it does the ioremap() for the -# mips_io_port_base. -# -core-$(CONFIG_MOMENCO_OCELOT) += arch/mips/gt64120/common/ \ - arch/mips/gt64120/momenco_ocelot/ -cflags-$(CONFIG_MOMENCO_OCELOT) += -Iinclude/asm-mips/mach-ocelot -load-$(CONFIG_MOMENCO_OCELOT) += 0xffffffff80100000 - -# # PMC-Sierra MSP SOCs # core-$(CONFIG_PMC_MSP) += arch/mips/pmc-sierra/msp71xx/ @@ -363,6 +357,7 @@ load-$(CONFIG_PMC_YOSEMITE) += 0xffffffff80100000 core-$(CONFIG_QEMU) += arch/mips/qemu/ cflags-$(CONFIG_QEMU) += -Iinclude/asm-mips/mach-qemu load-$(CONFIG_QEMU) += 0xffffffff80010000 +all-$(CONFIG_QEMU) := vmlinux.bin # # Basler eXcite @@ -372,17 +367,6 @@ cflags-$(CONFIG_BASLER_EXCITE) += -Iinclude/asm-mips/mach-excite load-$(CONFIG_BASLER_EXCITE) += 0x80100000 # -# NEC DDB -# -core-$(CONFIG_DDB5XXX_COMMON) += arch/mips/ddb5xxx/common/ - -# -# NEC DDB Vrc-5477 -# -core-$(CONFIG_DDB5477) += arch/mips/ddb5xxx/ddb5477/ -load-$(CONFIG_DDB5477) += 0xffffffff80100000 - -# # Common VR41xx # core-$(CONFIG_MACH_VR41XX) += arch/mips/vr41xx/common/ @@ -554,6 +538,7 @@ load-$(CONFIG_SIBYTE_BIGSUR) := 0xffffffff80100000 core-$(CONFIG_SNI_RM) += arch/mips/sni/ cflags-$(CONFIG_SNI_RM) += -Iinclude/asm-mips/mach-rm load-$(CONFIG_SNI_RM) += 0xffffffff80600000 +all-$(CONFIG_SNI_RM) := vmlinux.ecoff # # Toshiba JMR-TX3927 board @@ -647,33 +632,7 @@ vmlinux.64: vmlinux makeboot =$(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) $(1) -ifdef CONFIG_BOOT_ELF32 -all: $(vmlinux-32) -endif - -ifdef CONFIG_BOOT_ELF64 -all: $(vmlinux-64) -endif - -ifdef CONFIG_MIPS_ATLAS -all: vmlinux.srec -endif - -ifdef CONFIG_MIPS_MALTA -all: vmlinux.srec -endif - -ifdef CONFIG_MIPS_SEAD -all: vmlinux.srec -endif - -ifdef CONFIG_QEMU -all: vmlinux.bin -endif - -ifdef CONFIG_SNI_RM -all: vmlinux.ecoff -endif +all: $(all-y) vmlinux.bin: $(vmlinux-32) +@$(call makeboot,$@) @@ -700,6 +659,14 @@ endif archclean: @$(MAKE) $(clean)=arch/mips/boot +define archhelp + echo ' vmlinux.ecoff - ECOFF boot image' + echo ' vmlinux.bin - Raw binary boot image' + echo ' vmlinux.srec - SREC boot image' + echo + echo ' These will be default as apropriate for a configured platform.' +endef + CLEAN_FILES += vmlinux.32 \ vmlinux.64 \ vmlinux.ecoff diff --git a/arch/mips/arc/file.c b/arch/mips/arc/file.c index a43425b3c838..cb0127cf5bc1 100644 --- a/arch/mips/arc/file.c +++ b/arch/mips/arc/file.c @@ -13,63 +13,63 @@ #include <asm/arc/types.h> #include <asm/sgialib.h> -LONG __init +LONG ArcGetDirectoryEntry(ULONG FileID, struct linux_vdirent *Buffer, ULONG N, ULONG *Count) { return ARC_CALL4(get_vdirent, FileID, Buffer, N, Count); } -LONG __init +LONG ArcOpen(CHAR *Path, enum linux_omode OpenMode, ULONG *FileID) { return ARC_CALL3(open, Path, OpenMode, FileID); } -LONG __init +LONG ArcClose(ULONG FileID) { return ARC_CALL1(close, FileID); } -LONG __init +LONG ArcRead(ULONG FileID, VOID *Buffer, ULONG N, ULONG *Count) { return ARC_CALL4(read, FileID, Buffer, N, Count); } -LONG __init +LONG ArcGetReadStatus(ULONG FileID) { return ARC_CALL1(get_rstatus, FileID); } -LONG __init +LONG ArcWrite(ULONG FileID, PVOID Buffer, ULONG N, PULONG Count) { return ARC_CALL4(write, FileID, Buffer, N, Count); } -LONG __init +LONG ArcSeek(ULONG FileID, struct linux_bigint *Position, enum linux_seekmode SeekMode) { return ARC_CALL3(seek, FileID, Position, SeekMode); } -LONG __init +LONG ArcMount(char *name, enum linux_mountops op) { return ARC_CALL2(mount, name, op); } -LONG __init +LONG ArcGetFileInformation(ULONG FileID, struct linux_finfo *Information) { return ARC_CALL2(get_finfo, FileID, Information); } -LONG __init ArcSetFileInformation(ULONG FileID, ULONG AttributeFlags, - ULONG AttributeMask) +LONG ArcSetFileInformation(ULONG FileID, ULONG AttributeFlags, + ULONG AttributeMask) { return ARC_CALL3(set_finfo, FileID, AttributeFlags, AttributeMask); } diff --git a/arch/mips/au1000/common/Makefile b/arch/mips/au1000/common/Makefile index 4c35525edb4f..90e2d7a46e8e 100644 --- a/arch/mips/au1000/common/Makefile +++ b/arch/mips/au1000/common/Makefile @@ -12,3 +12,5 @@ obj-y += prom.o irq.o puts.o time.o reset.o \ obj-$(CONFIG_KGDB) += dbg_io.o obj-$(CONFIG_PCI) += pci.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/boot/Makefile b/arch/mips/boot/Makefile index 0dc84417bf49..2a209d74f0b4 100644 --- a/arch/mips/boot/Makefile +++ b/arch/mips/boot/Makefile @@ -42,10 +42,6 @@ vmlinux.srec: $(VMLINUX) $(obj)/addinitrd: $(obj)/addinitrd.c $(HOSTCC) -o $@ $^ -archhelp: - @echo '* vmlinux.ecoff - ECOFF boot image' - @echo '* vmlinux.srec - SREC boot image' - clean-files += addinitrd \ elf2ecoff \ vmlinux.bin \ diff --git a/arch/mips/cobalt/Makefile b/arch/mips/cobalt/Makefile index c292f80a8c74..a043f93f7d08 100644 --- a/arch/mips/cobalt/Makefile +++ b/arch/mips/cobalt/Makefile @@ -7,3 +7,5 @@ obj-y := buttons.o irq.o reset.o rtc.o serial.o setup.o obj-$(CONFIG_PCI) += pci.o obj-$(CONFIG_EARLY_PRINTK) += console.o obj-$(CONFIG_MTD_PHYSMAP) += mtd.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/cobalt/serial.c b/arch/mips/cobalt/serial.c index c27116599a5f..08e739704cc9 100644 --- a/arch/mips/cobalt/serial.c +++ b/arch/mips/cobalt/serial.c @@ -55,9 +55,9 @@ static __init int cobalt_uart_add(void) int retval; /* - * Cobalt Qube1 and RAQ1 have no UART. + * Cobalt Qube1 has no UART. */ - if (cobalt_board_id <= COBALT_BRD_ID_RAQ1) + if (cobalt_board_id == COBALT_BRD_ID_QUBE1) return 0; pdev = platform_device_alloc("serial8250", -1); diff --git a/arch/mips/configs/atlas_defconfig b/arch/mips/configs/atlas_defconfig index 129e2c961fec..62bcc887f2ca 100644 --- a/arch/mips/configs/atlas_defconfig +++ b/arch/mips/configs/atlas_defconfig @@ -32,12 +32,9 @@ CONFIG_MIPS_ATLAS=y # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_QEMU is not set diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig index dc3e1bf4e42e..67a80f4c7d87 100644 --- a/arch/mips/configs/bigsur_defconfig +++ b/arch/mips/configs/bigsur_defconfig @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_QEMU is not set diff --git a/arch/mips/configs/capcella_defconfig b/arch/mips/configs/capcella_defconfig index 4c7031222e64..4dc3197e2e9f 100644 --- a/arch/mips/configs/capcella_defconfig +++ b/arch/mips/configs/capcella_defconfig @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set CONFIG_MACH_VR41XX=y # CONFIG_PMC_YOSEMITE is not set # CONFIG_QEMU is not set diff --git a/arch/mips/configs/cobalt_defconfig b/arch/mips/configs/cobalt_defconfig index c8c05785a86d..6d6a01b9a817 100644 --- a/arch/mips/configs/cobalt_defconfig +++ b/arch/mips/configs/cobalt_defconfig @@ -18,10 +18,8 @@ CONFIG_MIPS_COBALT=y # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set -# CONFIG_MOMENCO_OCELOT is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_QEMU is not set diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig index ec60beb888b2..885b633647e9 100644 --- a/arch/mips/configs/db1000_defconfig +++ b/arch/mips/configs/db1000_defconfig @@ -33,12 +33,9 @@ CONFIG_MIPS_DB1000=y # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_QEMU is not set diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig index f3c25f08bfad..e3c3a07e8a7c 100644 --- a/arch/mips/configs/db1100_defconfig +++ b/arch/mips/configs/db1100_defconfig @@ -33,12 +33,9 @@ CONFIG_MIPS_DB1100=y # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_QEMU is not set diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig index 6d400befbacc..9aa7c3ebfa3f 100644 --- a/arch/mips/configs/db1200_defconfig +++ b/arch/mips/configs/db1200_defconfig @@ -33,12 +33,9 @@ CONFIG_MIPS_DB1200=y # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_QEMU is not set diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig index 82aea6e08823..99240668bca1 100644 --- a/arch/mips/configs/db1500_defconfig +++ b/arch/mips/configs/db1500_defconfig @@ -33,12 +33,9 @@ CONFIG_MIPS_DB1500=y # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_QEMU is not set diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig index 82697714a9e3..19992f76c60d 100644 --- a/arch/mips/configs/db1550_defconfig +++ b/arch/mips/configs/db1550_defconfig @@ -33,12 +33,9 @@ CONFIG_MIPS_DB1550=y # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_QEMU is not set diff --git a/arch/mips/configs/ddb5477_defconfig b/arch/mips/configs/ddb5477_defconfig deleted file mode 100644 index a42ab9ae7d4b..000000000000 --- a/arch/mips/configs/ddb5477_defconfig +++ /dev/null @@ -1,990 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.20 -# Tue Feb 20 21:47:28 2007 -# -CONFIG_MIPS=y - -# -# Machine selection -# -CONFIG_ZONE_DMA=y -# CONFIG_MIPS_MTX1 is not set -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1100 is not set -# CONFIG_MIPS_PB1500 is not set -# CONFIG_MIPS_PB1550 is not set -# CONFIG_MIPS_PB1200 is not set -# CONFIG_MIPS_DB1000 is not set -# CONFIG_MIPS_DB1100 is not set -# CONFIG_MIPS_DB1500 is not set -# CONFIG_MIPS_DB1550 is not set -# CONFIG_MIPS_DB1200 is not set -# CONFIG_MIPS_MIRAGE is not set -# CONFIG_BASLER_EXCITE is not set -# CONFIG_MIPS_COBALT is not set -# CONFIG_MACH_DECSTATION is not set -# CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set -# CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set -# CONFIG_WR_PPMC is not set -# CONFIG_MIPS_SIM is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MIPS_XXS1500 is not set -# CONFIG_PNX8550_JBS is not set -# CONFIG_PNX8550_STB810 is not set -CONFIG_DDB5477=y -# CONFIG_MACH_VR41XX is not set -# CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set -# CONFIG_MARKEINS is not set -# CONFIG_SGI_IP22 is not set -# CONFIG_SGI_IP27 is not set -# CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SIBYTE_SWARM is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set -# CONFIG_SIBYTE_LITTLESUR is not set -# CONFIG_SIBYTE_CRHINE is not set -# CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM is not set -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -# CONFIG_TOSHIBA_RBTX4938 is not set -CONFIG_DDB5477_BUS_FREQUENCY=0 -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_GENERIC_FIND_NEXT_BIT=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_TIME=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set -CONFIG_DMA_NONCOHERENT=y -CONFIG_DMA_NEED_PCI_MAP_STATE=y -CONFIG_I8259=y -# CONFIG_CPU_BIG_ENDIAN is not set -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_IRQ_CPU=y -CONFIG_DDB5XXX_COMMON=y -CONFIG_MIPS_L1_CACHE_SHIFT=5 - -# -# CPU selection -# -# CONFIG_CPU_MIPS32_R1 is not set -# CONFIG_CPU_MIPS32_R2 is not set -# CONFIG_CPU_MIPS64_R1 is not set -# CONFIG_CPU_MIPS64_R2 is not set -# CONFIG_CPU_R3000 is not set -# CONFIG_CPU_TX39XX is not set -# CONFIG_CPU_VR41XX is not set -# CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set -# CONFIG_CPU_TX49XX is not set -# CONFIG_CPU_R5000 is not set -CONFIG_CPU_R5432=y -# CONFIG_CPU_R6000 is not set -# CONFIG_CPU_NEVADA is not set -# CONFIG_CPU_R8000 is not set -# CONFIG_CPU_R10000 is not set -# CONFIG_CPU_RM7000 is not set -# CONFIG_CPU_RM9000 is not set -# CONFIG_CPU_SB1 is not set -CONFIG_SYS_HAS_CPU_R5432=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y - -# -# Kernel type -# -CONFIG_32BIT=y -# CONFIG_64BIT is not set -CONFIG_PAGE_SIZE_4KB=y -# CONFIG_PAGE_SIZE_8KB is not set -# CONFIG_PAGE_SIZE_16KB is not set -# CONFIG_PAGE_SIZE_64KB is not set -CONFIG_MIPS_MT_DISABLED=y -# CONFIG_MIPS_MT_SMP is not set -# CONFIG_MIPS_MT_SMTC is not set -# CONFIG_MIPS_VPE_LOADER is not set -CONFIG_CPU_HAS_LLSC=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_RESOURCES_64BIT is not set -CONFIG_ZONE_DMA_FLAG=1 -# CONFIG_HZ_48 is not set -# CONFIG_HZ_100 is not set -# CONFIG_HZ_128 is not set -# CONFIG_HZ_250 is not set -# CONFIG_HZ_256 is not set -CONFIG_HZ_1000=y -# CONFIG_HZ_1024 is not set -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_HZ=1000 -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set -# CONFIG_PREEMPT is not set -# CONFIG_KEXEC is not set -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -# CONFIG_IPC_NS is not set -CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_TASKSTATS is not set -# CONFIG_UTS_NS is not set -# CONFIG_AUDIT is not set -# CONFIG_IKCONFIG is not set -CONFIG_SYSFS_DEPRECATED=y -CONFIG_RELAY=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SYSCTL=y -CONFIG_EMBEDDED=y -CONFIG_SYSCTL_SYSCALL=y -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SHMEM=y -CONFIG_SLAB=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_RT_MUTEXES=y -# CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 -# CONFIG_SLOB is not set - -# -# Loadable module support -# -# CONFIG_MODULES is not set - -# -# Block layer -# -CONFIG_BLOCK=y -# CONFIG_LBD is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_LSF is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -CONFIG_DEFAULT_AS=y -# CONFIG_DEFAULT_DEADLINE is not set -# CONFIG_DEFAULT_CFQ is not set -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" - -# -# Bus options (PCI, PCMCIA, EISA, ISA, TC) -# -CONFIG_HW_HAS_PCI=y -CONFIG_PCI=y -CONFIG_MMU=y - -# -# PCCARD (PCMCIA/CardBus) support -# -# CONFIG_PCCARD is not set - -# -# PCI Hotplug Support -# -# CONFIG_HOTPLUG_PCI is not set - -# -# Executable file formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -CONFIG_TRAD_SIGNALS=y - -# -# Power management options -# -CONFIG_PM=y -# CONFIG_PM_LEGACY is not set -# CONFIG_PM_DEBUG is not set -# CONFIG_PM_SYSFS_DEPRECATED is not set - -# -# Networking -# -CONFIG_NET=y - -# -# Networking options -# -# CONFIG_NETDEBUG is not set -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_UNIX=y -CONFIG_XFRM=y -CONFIG_XFRM_USER=y -# CONFIG_XFRM_SUB_POLICY is not set -CONFIG_XFRM_MIGRATE=y -CONFIG_NET_KEY=y -CONFIG_NET_KEY_MIGRATE=y -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -CONFIG_TCP_MD5SIG=y -# CONFIG_IPV6 is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set -CONFIG_NETWORK_SECMARK=y -# CONFIG_NETFILTER is not set - -# -# DCCP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_DCCP is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set - -# -# TIPC Configuration (EXPERIMENTAL) -# -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_IEEE80211=y -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=y -CONFIG_IEEE80211_CRYPT_CCMP=y -CONFIG_IEEE80211_SOFTMAC=y -# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set -CONFIG_WIRELESS_EXT=y - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -# CONFIG_SYS_HYPERVISOR is not set - -# -# Connector - unified userspace <-> kernelspace linker -# -CONFIG_CONNECTOR=y -CONFIG_PROC_EVENTS=y - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# -# CONFIG_PNPACPI is not set - -# -# Block devices -# -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_UMEM is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_SX8 is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_INITRD is not set -CONFIG_CDROM_PKTCDVD=y -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set -CONFIG_ATA_OVER_ETH=y - -# -# Misc devices -# -CONFIG_SGI_IOC4=y -# CONFIG_TIFM_CORE is not set - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -CONFIG_RAID_ATTRS=y -# CONFIG_SCSI is not set -# CONFIG_SCSI_NETLINK is not set - -# -# Serial ATA (prod) and Parallel ATA (experimental) drivers -# -# CONFIG_ATA is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_IEEE1394 is not set - -# -# I2O device support -# -# CONFIG_I2O is not set - -# -# Network device support -# -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set - -# -# PHY device support -# -CONFIG_PHYLIB=y - -# -# MII PHY device drivers -# -CONFIG_MARVELL_PHY=y -CONFIG_DAVICOM_PHY=y -CONFIG_QSEMI_PHY=y -CONFIG_LXT_PHY=y -CONFIG_CICADA_PHY=y -CONFIG_VITESSE_PHY=y -CONFIG_SMSC_PHY=y -# CONFIG_BROADCOM_PHY is not set -# CONFIG_FIXED_PHY is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -# CONFIG_CASSINI is not set -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_DM9000 is not set - -# -# Tulip family network device support -# -# CONFIG_NET_TULIP is not set -# CONFIG_HP100 is not set -CONFIG_NET_PCI=y -CONFIG_PCNET32=y -# CONFIG_PCNET32_NAPI is not set -# CONFIG_AMD8111_ETH is not set -# CONFIG_ADAPTEC_STARFIRE is not set -# CONFIG_B44 is not set -# CONFIG_FORCEDETH is not set -# CONFIG_DGRS is not set -# CONFIG_EEPRO100 is not set -# CONFIG_E100 is not set -# CONFIG_FEALNX is not set -# CONFIG_NATSEMI is not set -# CONFIG_NE2K_PCI is not set -# CONFIG_8139CP is not set -# CONFIG_8139TOO is not set -# CONFIG_SIS900 is not set -# CONFIG_EPIC100 is not set -# CONFIG_SUNDANCE is not set -# CONFIG_TLAN is not set -# CONFIG_VIA_RHINE is not set -# CONFIG_SC92031 is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_E1000 is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_R8169 is not set -# CONFIG_SIS190 is not set -# CONFIG_SKGE is not set -# CONFIG_SKY2 is not set -# CONFIG_SK98LIN is not set -# CONFIG_VIA_VELOCITY is not set -# CONFIG_TIGON3 is not set -# CONFIG_BNX2 is not set -CONFIG_QLA3XXX=y -# CONFIG_ATL1 is not set - -# -# Ethernet (10000 Mbit) -# -# CONFIG_CHELSIO_T1 is not set -CONFIG_CHELSIO_T3=y -# CONFIG_IXGB is not set -# CONFIG_S2IO is not set -# CONFIG_MYRI10GE is not set -CONFIG_NETXEN_NIC=y - -# -# Token Ring devices -# -# CONFIG_TR is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=y -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_PCI=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_JSM is not set -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_RTC is not set -# CONFIG_GEN_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# -# CONFIG_TCG_TPM is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# SPI support -# -# CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set - -# -# Dallas's 1-wire bus -# -# CONFIG_W1 is not set - -# -# Hardware Monitoring support -# -# CONFIG_HWMON is not set -# CONFIG_HWMON_VID is not set - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# HID Devices -# -# CONFIG_HID is not set - -# -# USB support -# -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -CONFIG_USB_ARCH_HAS_EHCI=y -# CONFIG_USB is not set - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -# - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# MMC/SD Card support -# -# CONFIG_MMC is not set - -# -# LED devices -# -# CONFIG_NEW_LEDS is not set - -# -# LED drivers -# - -# -# LED Triggers -# - -# -# InfiniBand support -# -# CONFIG_INFINIBAND is not set - -# -# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) -# - -# -# Real Time Clock -# -# CONFIG_RTC_CLASS is not set - -# -# DMA Engine support -# -# CONFIG_DMA_ENGINE is not set - -# -# DMA Clients -# - -# -# DMA Devices -# - -# -# Auxiliary Display support -# - -# -# Virtualization -# - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -# CONFIG_EXT3_FS is not set -# CONFIG_EXT4DEV_FS is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_FS_POSIX_ACL is not set -# CONFIG_XFS_FS is not set -# CONFIG_GFS2_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -CONFIG_AUTOFS_FS=y -CONFIG_AUTOFS4_FS=y -CONFIG_FUSE_FS=y - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_PROC_SYSCTL=y -CONFIG_SYSFS=y -# CONFIG_TMPFS is not set -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y -CONFIG_CONFIGFS_FS=y - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_ECRYPT_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -# CONFIG_NFS_V3 is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -CONFIG_NFSD=y -# CONFIG_NFSD_V3 is not set -# CONFIG_NFSD_TCP is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -CONFIG_EXPORTFS=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set -# CONFIG_9P_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -# CONFIG_NLS is not set - -# -# Distributed Lock Manager -# -CONFIG_DLM=y -CONFIG_DLM_TCP=y -# CONFIG_DLM_SCTP is not set -# CONFIG_DLM_DEBUG is not set - -# -# Profiling support -# -# CONFIG_PROFILING is not set - -# -# Kernel hacking -# -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -# CONFIG_PRINTK_TIME is not set -CONFIG_ENABLE_MUST_CHECK=y -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_FS is not set -# CONFIG_HEADERS_CHECK is not set -# CONFIG_DEBUG_KERNEL is not set -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE="ip=any" -CONFIG_SYS_SUPPORTS_KGDB=y - -# -# Security options -# -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -CONFIG_CRYPTO=y -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_XCBC=y -CONFIG_CRYPTO_NULL=y -CONFIG_CRYPTO_MD4=y -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_WP512=y -CONFIG_CRYPTO_TGR192=y -CONFIG_CRYPTO_GF128MUL=y -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_PCBC=y -CONFIG_CRYPTO_LRW=y -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_FCRYPT=y -CONFIG_CRYPTO_BLOWFISH=y -CONFIG_CRYPTO_TWOFISH=y -CONFIG_CRYPTO_TWOFISH_COMMON=y -CONFIG_CRYPTO_SERPENT=y -CONFIG_CRYPTO_AES=y -CONFIG_CRYPTO_CAST5=y -CONFIG_CRYPTO_CAST6=y -CONFIG_CRYPTO_TEA=y -CONFIG_CRYPTO_ARC4=y -CONFIG_CRYPTO_KHAZAD=y -CONFIG_CRYPTO_ANUBIS=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_MICHAEL_MIC=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CAMELLIA=y - -# -# Hardware crypto devices -# - -# -# Library routines -# -CONFIG_BITREVERSE=y -# CONFIG_CRC_CCITT is not set -CONFIG_CRC16=y -CONFIG_CRC32=y -CONFIG_LIBCRC32C=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_PLIST=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y diff --git a/arch/mips/configs/decstation_defconfig b/arch/mips/configs/decstation_defconfig index d6e3fffbc80d..2fb350432669 100644 --- a/arch/mips/configs/decstation_defconfig +++ b/arch/mips/configs/decstation_defconfig @@ -32,12 +32,9 @@ CONFIG_MACH_DECSTATION=y # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_QEMU is not set diff --git a/arch/mips/configs/e55_defconfig b/arch/mips/configs/e55_defconfig index 78f5004fb721..5467d750b6eb 100644 --- a/arch/mips/configs/e55_defconfig +++ b/arch/mips/configs/e55_defconfig @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set CONFIG_MACH_VR41XX=y # CONFIG_PMC_YOSEMITE is not set # CONFIG_QEMU is not set diff --git a/arch/mips/configs/emma2rh_defconfig b/arch/mips/configs/emma2rh_defconfig index b29bff0f56c3..d73d965f7615 100644 --- a/arch/mips/configs/emma2rh_defconfig +++ b/arch/mips/configs/emma2rh_defconfig @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_QEMU is not set diff --git a/arch/mips/configs/excite_defconfig b/arch/mips/configs/excite_defconfig index 69810592aa6b..17a866057fd4 100644 --- a/arch/mips/configs/excite_defconfig +++ b/arch/mips/configs/excite_defconfig @@ -33,12 +33,9 @@ CONFIG_BASLER_EXCITE=y # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_QEMU is not set diff --git a/arch/mips/configs/fulong_defconfig b/arch/mips/configs/fulong_defconfig index 6ab94d8cf08b..4ef39a0527cc 100644 --- a/arch/mips/configs/fulong_defconfig +++ b/arch/mips/configs/fulong_defconfig @@ -19,10 +19,8 @@ CONFIG_LEMOTE_FULONG=y # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set -# CONFIG_MOMENCO_OCELOT is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_QEMU is not set diff --git a/arch/mips/configs/ip22_defconfig b/arch/mips/configs/ip22_defconfig index 405c9f505a77..934d8a008936 100644 --- a/arch/mips/configs/ip22_defconfig +++ b/arch/mips/configs/ip22_defconfig @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_QEMU is not set diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig index a9dcbcf563cb..eb35f7518d06 100644 --- a/arch/mips/configs/ip27_defconfig +++ b/arch/mips/configs/ip27_defconfig @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_QEMU is not set diff --git a/arch/mips/configs/ip32_defconfig b/arch/mips/configs/ip32_defconfig index a040459bec11..47f49b60c5d6 100644 --- a/arch/mips/configs/ip32_defconfig +++ b/arch/mips/configs/ip32_defconfig @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_QEMU is not set diff --git a/arch/mips/configs/jazz_defconfig b/arch/mips/configs/jazz_defconfig index 8a0b4ac5283d..fa655e247ecc 100644 --- a/arch/mips/configs/jazz_defconfig +++ b/arch/mips/configs/jazz_defconfig @@ -32,12 +32,9 @@ CONFIG_MACH_JAZZ=y # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_QEMU is not set diff --git a/arch/mips/configs/jmr3927_defconfig b/arch/mips/configs/jmr3927_defconfig index 9a25e770abd8..95a72d2750ef 100644 --- a/arch/mips/configs/jmr3927_defconfig +++ b/arch/mips/configs/jmr3927_defconfig @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_QEMU is not set diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig index 546cb243fd09..fbfa5685887c 100644 --- a/arch/mips/configs/malta_defconfig +++ b/arch/mips/configs/malta_defconfig @@ -32,12 +32,9 @@ CONFIG_MIPS_MALTA=y # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_QEMU is not set diff --git a/arch/mips/configs/mipssim_defconfig b/arch/mips/configs/mipssim_defconfig index 6abad6f88313..86dcb7464353 100644 --- a/arch/mips/configs/mipssim_defconfig +++ b/arch/mips/configs/mipssim_defconfig @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y # CONFIG_WR_PPMC is not set CONFIG_MIPS_SIM=y # CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_QEMU is not set diff --git a/arch/mips/configs/mpc30x_defconfig b/arch/mips/configs/mpc30x_defconfig index 4981ce425d82..239810b6c88d 100644 --- a/arch/mips/configs/mpc30x_defconfig +++ b/arch/mips/configs/mpc30x_defconfig @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set CONFIG_MACH_VR41XX=y # CONFIG_PMC_YOSEMITE is not set # CONFIG_QEMU is not set diff --git a/arch/mips/configs/msp71xx_defconfig b/arch/mips/configs/msp71xx_defconfig index adca5f7ba533..69278999c9a2 100644 --- a/arch/mips/configs/msp71xx_defconfig +++ b/arch/mips/configs/msp71xx_defconfig @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set CONFIG_PMC_MSP=y # CONFIG_PMC_YOSEMITE is not set diff --git a/arch/mips/configs/ocelot_defconfig b/arch/mips/configs/ocelot_defconfig deleted file mode 100644 index e1db1fb80cd0..000000000000 --- a/arch/mips/configs/ocelot_defconfig +++ /dev/null @@ -1,919 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.20 -# Tue Feb 20 21:47:36 2007 -# -CONFIG_MIPS=y - -# -# Machine selection -# -CONFIG_ZONE_DMA=y -# CONFIG_MIPS_MTX1 is not set -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1100 is not set -# CONFIG_MIPS_PB1500 is not set -# CONFIG_MIPS_PB1550 is not set -# CONFIG_MIPS_PB1200 is not set -# CONFIG_MIPS_DB1000 is not set -# CONFIG_MIPS_DB1100 is not set -# CONFIG_MIPS_DB1500 is not set -# CONFIG_MIPS_DB1550 is not set -# CONFIG_MIPS_DB1200 is not set -# CONFIG_MIPS_MIRAGE is not set -# CONFIG_BASLER_EXCITE is not set -# CONFIG_MIPS_COBALT is not set -# CONFIG_MACH_DECSTATION is not set -# CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set -# CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set -# CONFIG_WR_PPMC is not set -# CONFIG_MIPS_SIM is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -CONFIG_MOMENCO_OCELOT=y -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MIPS_XXS1500 is not set -# CONFIG_PNX8550_JBS is not set -# CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set -# CONFIG_MARKEINS is not set -# CONFIG_SGI_IP22 is not set -# CONFIG_SGI_IP27 is not set -# CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SIBYTE_SWARM is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set -# CONFIG_SIBYTE_LITTLESUR is not set -# CONFIG_SIBYTE_CRHINE is not set -# CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM is not set -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -# CONFIG_TOSHIBA_RBTX4938 is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_GENERIC_FIND_NEXT_BIT=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_TIME=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set -CONFIG_DMA_NONCOHERENT=y -CONFIG_DMA_NEED_PCI_MAP_STATE=y -CONFIG_CPU_BIG_ENDIAN=y -# CONFIG_CPU_LITTLE_ENDIAN is not set -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -CONFIG_IRQ_CPU=y -CONFIG_IRQ_CPU_RM7K=y -CONFIG_MIPS_GT64120=y -CONFIG_SWAP_IO_SPACE=y -# CONFIG_SYSCLK_75 is not set -# CONFIG_SYSCLK_83 is not set -CONFIG_SYSCLK_100=y -CONFIG_MIPS_L1_CACHE_SHIFT=5 - -# -# CPU selection -# -# CONFIG_CPU_MIPS32_R1 is not set -# CONFIG_CPU_MIPS32_R2 is not set -# CONFIG_CPU_MIPS64_R1 is not set -# CONFIG_CPU_MIPS64_R2 is not set -# CONFIG_CPU_R3000 is not set -# CONFIG_CPU_TX39XX is not set -# CONFIG_CPU_VR41XX is not set -# CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set -# CONFIG_CPU_TX49XX is not set -# CONFIG_CPU_R5000 is not set -# CONFIG_CPU_R5432 is not set -# CONFIG_CPU_R6000 is not set -# CONFIG_CPU_NEVADA is not set -# CONFIG_CPU_R8000 is not set -# CONFIG_CPU_R10000 is not set -CONFIG_CPU_RM7000=y -# CONFIG_CPU_RM9000 is not set -# CONFIG_CPU_SB1 is not set -CONFIG_SYS_HAS_CPU_RM7000=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y - -# -# Kernel type -# -CONFIG_32BIT=y -# CONFIG_64BIT is not set -CONFIG_PAGE_SIZE_4KB=y -# CONFIG_PAGE_SIZE_8KB is not set -# CONFIG_PAGE_SIZE_16KB is not set -# CONFIG_PAGE_SIZE_64KB is not set -CONFIG_BOARD_SCACHE=y -CONFIG_RM7000_CPU_SCACHE=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y -# CONFIG_MIPS_MT_SMP is not set -# CONFIG_MIPS_MT_SMTC is not set -# CONFIG_MIPS_VPE_LOADER is not set -# CONFIG_64BIT_PHYS_ADDR is not set -CONFIG_CPU_HAS_LLSC=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_RESOURCES_64BIT is not set -CONFIG_ZONE_DMA_FLAG=1 -# CONFIG_HZ_48 is not set -# CONFIG_HZ_100 is not set -# CONFIG_HZ_128 is not set -# CONFIG_HZ_250 is not set -# CONFIG_HZ_256 is not set -CONFIG_HZ_1000=y -# CONFIG_HZ_1024 is not set -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_HZ=1000 -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set -# CONFIG_PREEMPT is not set -# CONFIG_KEXEC is not set -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -# CONFIG_IPC_NS is not set -CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_TASKSTATS is not set -# CONFIG_UTS_NS is not set -# CONFIG_AUDIT is not set -# CONFIG_IKCONFIG is not set -CONFIG_SYSFS_DEPRECATED=y -CONFIG_RELAY=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SYSCTL=y -CONFIG_EMBEDDED=y -CONFIG_SYSCTL_SYSCALL=y -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_EXTRA_PASS is not set -# CONFIG_HOTPLUG is not set -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SHMEM=y -CONFIG_SLAB=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_RT_MUTEXES=y -# CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 -# CONFIG_SLOB is not set - -# -# Loadable module support -# -# CONFIG_MODULES is not set - -# -# Block layer -# -CONFIG_BLOCK=y -# CONFIG_LBD is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_LSF is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -CONFIG_DEFAULT_AS=y -# CONFIG_DEFAULT_DEADLINE is not set -# CONFIG_DEFAULT_CFQ is not set -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" - -# -# Bus options (PCI, PCMCIA, EISA, ISA, TC) -# -CONFIG_HW_HAS_PCI=y -# CONFIG_PCI is not set -CONFIG_MMU=y - -# -# PCCARD (PCMCIA/CardBus) support -# - -# -# PCI Hotplug Support -# - -# -# Executable file formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -CONFIG_TRAD_SIGNALS=y - -# -# Power management options -# -CONFIG_PM=y -# CONFIG_PM_LEGACY is not set -# CONFIG_PM_DEBUG is not set -# CONFIG_PM_SYSFS_DEPRECATED is not set - -# -# Networking -# -CONFIG_NET=y - -# -# Networking options -# -# CONFIG_NETDEBUG is not set -# CONFIG_PACKET is not set -CONFIG_UNIX=y -CONFIG_XFRM=y -CONFIG_XFRM_USER=y -# CONFIG_XFRM_SUB_POLICY is not set -CONFIG_XFRM_MIGRATE=y -CONFIG_NET_KEY=y -CONFIG_NET_KEY_MIGRATE=y -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -CONFIG_TCP_MD5SIG=y -# CONFIG_IPV6 is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set -CONFIG_NETWORK_SECMARK=y -# CONFIG_NETFILTER is not set - -# -# DCCP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_DCCP is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set - -# -# TIPC Configuration (EXPERIMENTAL) -# -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_IEEE80211=y -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=y -CONFIG_IEEE80211_CRYPT_CCMP=y -CONFIG_IEEE80211_SOFTMAC=y -# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set -CONFIG_WIRELESS_EXT=y - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_SYS_HYPERVISOR is not set - -# -# Connector - unified userspace <-> kernelspace linker -# -CONFIG_CONNECTOR=y -CONFIG_PROC_EVENTS=y - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# -# CONFIG_PNPACPI is not set - -# -# Block devices -# -# CONFIG_BLK_DEV_COW_COMMON is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_INITRD is not set -CONFIG_CDROM_PKTCDVD=y -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set -CONFIG_ATA_OVER_ETH=y - -# -# Misc devices -# - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -CONFIG_RAID_ATTRS=y -# CONFIG_SCSI is not set -# CONFIG_SCSI_NETLINK is not set - -# -# Serial ATA (prod) and Parallel ATA (experimental) drivers -# -# CONFIG_ATA is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# - -# -# I2O device support -# - -# -# Network device support -# -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set - -# -# PHY device support -# -CONFIG_PHYLIB=y - -# -# MII PHY device drivers -# -CONFIG_MARVELL_PHY=y -CONFIG_DAVICOM_PHY=y -CONFIG_QSEMI_PHY=y -CONFIG_LXT_PHY=y -CONFIG_CICADA_PHY=y -CONFIG_VITESSE_PHY=y -CONFIG_SMSC_PHY=y -# CONFIG_BROADCOM_PHY is not set -# CONFIG_FIXED_PHY is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -# CONFIG_MII is not set -# CONFIG_DM9000 is not set - -# -# Ethernet (1000 Mbit) -# - -# -# Ethernet (10000 Mbit) -# - -# -# Token Ring devices -# - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=y -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_RTC is not set -# CONFIG_GEN_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# -# CONFIG_TCG_TPM is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# SPI support -# -# CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set - -# -# Dallas's 1-wire bus -# -# CONFIG_W1 is not set - -# -# Hardware Monitoring support -# -# CONFIG_HWMON is not set -# CONFIG_HWMON_VID is not set - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# HID Devices -# -# CONFIG_HID is not set - -# -# USB support -# -# CONFIG_USB_ARCH_HAS_HCD is not set -# CONFIG_USB_ARCH_HAS_OHCI is not set -# CONFIG_USB_ARCH_HAS_EHCI is not set - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -# - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# MMC/SD Card support -# -# CONFIG_MMC is not set - -# -# LED devices -# -# CONFIG_NEW_LEDS is not set - -# -# LED drivers -# - -# -# LED Triggers -# - -# -# InfiniBand support -# - -# -# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) -# - -# -# Real Time Clock -# -# CONFIG_RTC_CLASS is not set - -# -# DMA Engine support -# -# CONFIG_DMA_ENGINE is not set - -# -# DMA Clients -# - -# -# DMA Devices -# - -# -# Auxiliary Display support -# - -# -# Virtualization -# - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -# CONFIG_EXT3_FS is not set -# CONFIG_EXT4DEV_FS is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -CONFIG_FS_POSIX_ACL=y -# CONFIG_XFS_FS is not set -# CONFIG_GFS2_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -CONFIG_FUSE_FS=y -CONFIG_GENERIC_ACL=y - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_PROC_SYSCTL=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y -CONFIG_CONFIGFS_FS=y - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_ECRYPT_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -# CONFIG_NFS_V3 is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -CONFIG_NFSD=y -# CONFIG_NFSD_V3 is not set -# CONFIG_NFSD_TCP is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -CONFIG_EXPORTFS=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set -# CONFIG_9P_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -# CONFIG_NLS is not set - -# -# Distributed Lock Manager -# -CONFIG_DLM=y -CONFIG_DLM_TCP=y -# CONFIG_DLM_SCTP is not set -# CONFIG_DLM_DEBUG is not set - -# -# Profiling support -# -# CONFIG_PROFILING is not set - -# -# Kernel hacking -# -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -# CONFIG_PRINTK_TIME is not set -CONFIG_ENABLE_MUST_CHECK=y -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_FS is not set -# CONFIG_HEADERS_CHECK is not set -# CONFIG_DEBUG_KERNEL is not set -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE="" -CONFIG_SYS_SUPPORTS_KGDB=y - -# -# Security options -# -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -CONFIG_CRYPTO=y -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_XCBC=y -CONFIG_CRYPTO_NULL=y -CONFIG_CRYPTO_MD4=y -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_WP512=y -CONFIG_CRYPTO_TGR192=y -CONFIG_CRYPTO_GF128MUL=y -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_PCBC=y -CONFIG_CRYPTO_LRW=y -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_FCRYPT=y -CONFIG_CRYPTO_BLOWFISH=y -CONFIG_CRYPTO_TWOFISH=y -CONFIG_CRYPTO_TWOFISH_COMMON=y -CONFIG_CRYPTO_SERPENT=y -CONFIG_CRYPTO_AES=y -CONFIG_CRYPTO_CAST5=y -CONFIG_CRYPTO_CAST6=y -CONFIG_CRYPTO_TEA=y -CONFIG_CRYPTO_ARC4=y -CONFIG_CRYPTO_KHAZAD=y -CONFIG_CRYPTO_ANUBIS=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_MICHAEL_MIC=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CAMELLIA=y - -# -# Hardware crypto devices -# - -# -# Library routines -# -CONFIG_BITREVERSE=y -# CONFIG_CRC_CCITT is not set -CONFIG_CRC16=y -CONFIG_CRC32=y -CONFIG_LIBCRC32C=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_PLIST=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig index 0028aef0af9d..d53fa8f8e099 100644 --- a/arch/mips/configs/pb1100_defconfig +++ b/arch/mips/configs/pb1100_defconfig @@ -33,12 +33,9 @@ CONFIG_MIPS_PB1100=y # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_QEMU is not set diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig index 8a1d5888739c..dc4aa0c66847 100644 --- a/arch/mips/configs/pb1500_defconfig +++ b/arch/mips/configs/pb1500_defconfig @@ -33,12 +33,9 @@ CONFIG_MIPS_PB1500=y # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_QEMU is not set diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig index 5581ad2ca411..24428e13002b 100644 --- a/arch/mips/configs/pb1550_defconfig +++ b/arch/mips/configs/pb1550_defconfig @@ -33,12 +33,9 @@ CONFIG_MIPS_PB1550=y # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_QEMU is not set diff --git a/arch/mips/configs/pnx8550-jbs_defconfig b/arch/mips/configs/pnx8550-jbs_defconfig index 821c1cee5639..f6906b069e04 100644 --- a/arch/mips/configs/pnx8550-jbs_defconfig +++ b/arch/mips/configs/pnx8550-jbs_defconfig @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set # CONFIG_MIPS_XXS1500 is not set CONFIG_PNX8550_JBS=y # CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_QEMU is not set diff --git a/arch/mips/configs/pnx8550-stb810_defconfig b/arch/mips/configs/pnx8550-stb810_defconfig index 0e8bd92b38cf..b741f81696fb 100644 --- a/arch/mips/configs/pnx8550-stb810_defconfig +++ b/arch/mips/configs/pnx8550-stb810_defconfig @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_JBS is not set CONFIG_PNX8550_STB810=y -# CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_QEMU is not set diff --git a/arch/mips/configs/qemu_defconfig b/arch/mips/configs/qemu_defconfig index 703de002e372..b3caf5125c15 100644 --- a/arch/mips/configs/qemu_defconfig +++ b/arch/mips/configs/qemu_defconfig @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set CONFIG_QEMU=y diff --git a/arch/mips/configs/rbhma4200_defconfig b/arch/mips/configs/rbhma4200_defconfig index 20a38526d483..9913980add21 100644 --- a/arch/mips/configs/rbhma4200_defconfig +++ b/arch/mips/configs/rbhma4200_defconfig @@ -30,11 +30,9 @@ CONFIG_MIPS=y # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set -# CONFIG_MOMENCO_OCELOT is not set # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_QEMU is not set diff --git a/arch/mips/configs/rbhma4500_defconfig b/arch/mips/configs/rbhma4500_defconfig index 5dbb250f71c7..40453cd7c70e 100644 --- a/arch/mips/configs/rbhma4500_defconfig +++ b/arch/mips/configs/rbhma4500_defconfig @@ -20,10 +20,8 @@ CONFIG_ZONE_DMA=y # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set -# CONFIG_MOMENCO_OCELOT is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set diff --git a/arch/mips/configs/rm200_defconfig b/arch/mips/configs/rm200_defconfig index a5dc5cb97aae..fc388118b114 100644 --- a/arch/mips/configs/rm200_defconfig +++ b/arch/mips/configs/rm200_defconfig @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_QEMU is not set diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250-swarm_defconfig index 98a914092258..e72fdf36b3fe 100644 --- a/arch/mips/configs/sb1250-swarm_defconfig +++ b/arch/mips/configs/sb1250-swarm_defconfig @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_QEMU is not set diff --git a/arch/mips/configs/sead_defconfig b/arch/mips/configs/sead_defconfig index 69c08b24c82a..2b6282d132a8 100644 --- a/arch/mips/configs/sead_defconfig +++ b/arch/mips/configs/sead_defconfig @@ -32,12 +32,9 @@ CONFIG_MIPS_SEAD=y # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_QEMU is not set diff --git a/arch/mips/configs/tb0219_defconfig b/arch/mips/configs/tb0219_defconfig index 5d4fc0e4f729..e9f2cef4c716 100644 --- a/arch/mips/configs/tb0219_defconfig +++ b/arch/mips/configs/tb0219_defconfig @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set CONFIG_MACH_VR41XX=y # CONFIG_PMC_YOSEMITE is not set # CONFIG_QEMU is not set diff --git a/arch/mips/configs/tb0226_defconfig b/arch/mips/configs/tb0226_defconfig index 1b92b48de051..aea67568842a 100644 --- a/arch/mips/configs/tb0226_defconfig +++ b/arch/mips/configs/tb0226_defconfig @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set CONFIG_MACH_VR41XX=y # CONFIG_PMC_YOSEMITE is not set # CONFIG_QEMU is not set diff --git a/arch/mips/configs/tb0287_defconfig b/arch/mips/configs/tb0287_defconfig index 5b77c7a5d83a..66383ecff200 100644 --- a/arch/mips/configs/tb0287_defconfig +++ b/arch/mips/configs/tb0287_defconfig @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set CONFIG_MACH_VR41XX=y # CONFIG_PMC_YOSEMITE is not set # CONFIG_QEMU is not set diff --git a/arch/mips/configs/workpad_defconfig b/arch/mips/configs/workpad_defconfig index 94a4f94a8b24..db6fd4f15719 100644 --- a/arch/mips/configs/workpad_defconfig +++ b/arch/mips/configs/workpad_defconfig @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set CONFIG_MACH_VR41XX=y # CONFIG_PMC_YOSEMITE is not set # CONFIG_QEMU is not set diff --git a/arch/mips/configs/wrppmc_defconfig b/arch/mips/configs/wrppmc_defconfig index e38bd9b0eadc..7e410e10fed7 100644 --- a/arch/mips/configs/wrppmc_defconfig +++ b/arch/mips/configs/wrppmc_defconfig @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y CONFIG_WR_PPMC=y # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_QEMU is not set diff --git a/arch/mips/configs/yosemite_defconfig b/arch/mips/configs/yosemite_defconfig index f342d8c887b8..acaf0e21bb00 100644 --- a/arch/mips/configs/yosemite_defconfig +++ b/arch/mips/configs/yosemite_defconfig @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set CONFIG_PMC_YOSEMITE=y # CONFIG_QEMU is not set diff --git a/arch/mips/ddb5xxx/Kconfig b/arch/mips/ddb5xxx/Kconfig deleted file mode 100644 index e9b5de49f4c2..000000000000 --- a/arch/mips/ddb5xxx/Kconfig +++ /dev/null @@ -1,4 +0,0 @@ -config DDB5477_BUS_FREQUENCY - int "bus frequency (in kHZ, 0 for auto-detect)" - depends on DDB5477 - default 0 diff --git a/arch/mips/ddb5xxx/common/Makefile b/arch/mips/ddb5xxx/common/Makefile deleted file mode 100644 index bc44e3032711..000000000000 --- a/arch/mips/ddb5xxx/common/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for the common code of NEC DDB-Vrc5xxx board -# - -obj-y += nile4.o prom.o rtc_ds1386.o diff --git a/arch/mips/ddb5xxx/common/nile4.c b/arch/mips/ddb5xxx/common/nile4.c deleted file mode 100644 index 7ec7d903ba97..000000000000 --- a/arch/mips/ddb5xxx/common/nile4.c +++ /dev/null @@ -1,130 +0,0 @@ -/* - * - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * arch/mips/ddb5xxx/common/nile4.c - * misc low-level routines for vrc-5xxx controllers. - * - * derived from original code by Geert Uytterhoeven <geert@sonycom.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include <linux/types.h> -#include <linux/kernel.h> - -#include <asm/ddb5xxx/ddb5xxx.h> - -u32 -ddb_calc_pdar(u32 phys, u32 size, int width, - int on_memory_bus, int pci_visible) -{ - u32 maskbits; - u32 widthbits; - - switch (size) { -#if 0 /* We don't support 4 GB yet */ - case 0x100000000: /* 4 GB */ - maskbits = 4; - break; -#endif - case 0x80000000: /* 2 GB */ - maskbits = 5; - break; - case 0x40000000: /* 1 GB */ - maskbits = 6; - break; - case 0x20000000: /* 512 MB */ - maskbits = 7; - break; - case 0x10000000: /* 256 MB */ - maskbits = 8; - break; - case 0x08000000: /* 128 MB */ - maskbits = 9; - break; - case 0x04000000: /* 64 MB */ - maskbits = 10; - break; - case 0x02000000: /* 32 MB */ - maskbits = 11; - break; - case 0x01000000: /* 16 MB */ - maskbits = 12; - break; - case 0x00800000: /* 8 MB */ - maskbits = 13; - break; - case 0x00400000: /* 4 MB */ - maskbits = 14; - break; - case 0x00200000: /* 2 MB */ - maskbits = 15; - break; - case 0: /* OFF */ - maskbits = 0; - break; - default: - panic("nile4_set_pdar: unsupported size %p", (void *) size); - } - switch (width) { - case 8: - widthbits = 0; - break; - case 16: - widthbits = 1; - break; - case 32: - widthbits = 2; - break; - case 64: - widthbits = 3; - break; - default: - panic("nile4_set_pdar: unsupported width %d", width); - } - - return maskbits | (on_memory_bus ? 0x10 : 0) | - (pci_visible ? 0x20 : 0) | (widthbits << 6) | - (phys & 0xffe00000); -} - -void -ddb_set_pdar(u32 pdar, u32 phys, u32 size, int width, - int on_memory_bus, int pci_visible) -{ - u32 temp= ddb_calc_pdar(phys, size, width, on_memory_bus, pci_visible); - ddb_out32(pdar, temp); - ddb_out32(pdar + 4, 0); - - /* - * When programming a PDAR, the register should be read immediately - * after writing it. This ensures that address decoders are properly - * configured. - * [jsun] is this really necessary? - */ - ddb_in32(pdar); - ddb_in32(pdar + 4); -} - -/* - * routines that mess with PCIINITx registers - */ - -void ddb_set_pmr(u32 pmr, u32 type, u32 addr, u32 options) -{ - switch (type) { - case DDB_PCICMD_IACK: /* PCI Interrupt Acknowledge */ - case DDB_PCICMD_IO: /* PCI I/O Space */ - case DDB_PCICMD_MEM: /* PCI Memory Space */ - case DDB_PCICMD_CFG: /* PCI Configuration Space */ - break; - default: - panic("nile4_set_pmr: invalid type %d", type); - } - ddb_out32(pmr, (type << 1) | (addr & 0xffe00000) | options ); - ddb_out32(pmr + 4, 0); -} diff --git a/arch/mips/ddb5xxx/common/prom.c b/arch/mips/ddb5xxx/common/prom.c deleted file mode 100644 index 54a857b5e3ba..000000000000 --- a/arch/mips/ddb5xxx/common/prom.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include <linux/init.h> -#include <linux/mm.h> -#include <linux/sched.h> -#include <linux/bootmem.h> - -#include <asm/addrspace.h> -#include <asm/bootinfo.h> -#include <asm/ddb5xxx/ddb5xxx.h> -#include <asm/debug.h> - -const char *get_system_type(void) -{ - switch (mips_machtype) { - case MACH_NEC_DDB5477: return "NEC DDB Vrc-5477"; - case MACH_NEC_ROCKHOPPER: return "NEC Rockhopper"; - case MACH_NEC_ROCKHOPPERII: return "NEC RockhopperII"; - default: return "Unknown NEC board"; - } -} - -#if defined(CONFIG_DDB5477) -void ddb5477_runtime_detection(void); -#endif - -/* [jsun@junsun.net] PMON passes arguments in C main() style */ -void __init prom_init(void) -{ - int argc = fw_arg0; - char **arg = (char**) fw_arg1; - int i; - - /* if user passes kernel args, ignore the default one */ - if (argc > 1) - arcs_cmdline[0] = '\0'; - - /* arg[0] is "g", the rest is boot parameters */ - for (i = 1; i < argc; i++) { - if (strlen(arcs_cmdline) + strlen(arg[i] + 1) - >= sizeof(arcs_cmdline)) - break; - strcat(arcs_cmdline, arg[i]); - strcat(arcs_cmdline, " "); - } - - mips_machgroup = MACH_GROUP_NEC_DDB; - -#if defined(CONFIG_DDB5477) - ddb5477_runtime_detection(); - add_memory_region(0, board_ram_size, BOOT_MEM_RAM); -#endif -} - -void __init prom_free_prom_memory(void) -{ -} - -#if defined(CONFIG_DDB5477) - -#define DEFAULT_LCS1_BASE 0x19000000 -#define TESTVAL1 'K' -#define TESTVAL2 'S' - -int board_ram_size; -void ddb5477_runtime_detection(void) -{ - volatile char *test_offset; - char saved_test_byte; - - /* Determine if this is a DDB5477 board, or a BSB-VR0300 - base board. We can tell by checking for the location of - the NVRAM. It lives at the beginning of LCS1 on the DDB5477, - and the beginning of LCS1 on the BSB-VR0300 is flash memory. - The first 2K of the NVRAM are reserved, so don't we'll poke - around just after that. - */ - - /* We can only use the PCI bus to distinquish between - the Rockhopper and RockhopperII backplanes and this must - wait until ddb5477_board_init() in setup.c after the 5477 - is initialized. So, until then handle - both Rockhopper and RockhopperII backplanes as Rockhopper 1 - */ - - test_offset = (char *)KSEG1ADDR(DEFAULT_LCS1_BASE + 0x800); - saved_test_byte = *test_offset; - - *test_offset = TESTVAL1; - if (*test_offset != TESTVAL1) { - /* We couldn't set our test value, so it must not be NVRAM, - so it's a BSB_VR0300 */ - mips_machtype = MACH_NEC_ROCKHOPPER; - } else { - /* We may have gotten lucky, and the TESTVAL1 was already - stored at the test location, so we must check a second - test value */ - *test_offset = TESTVAL2; - if (*test_offset != TESTVAL2) { - /* OK, we couldn't set this value either, so it must - definately be a BSB_VR0300 */ - mips_machtype = MACH_NEC_ROCKHOPPER; - } else { - /* We could change the value twice, so it must be - NVRAM, so it's a DDB_VRC5477 */ - mips_machtype = MACH_NEC_DDB5477; - } - } - /* Restore the original byte */ - *test_offset = saved_test_byte; - - /* before we know a better way, we will trust PMON for getting - * RAM size - */ - board_ram_size = 1 << (36 - (ddb_in32(DDB_SDRAM0) & 0xf)); - - db_run(printk("DDB run-time detection : %s, %d MB RAM\n", - mips_machtype == MACH_NEC_DDB5477 ? - "DDB5477" : "Rockhopper", - board_ram_size >> 20)); - - /* we can't handle ram size > 128 MB */ - db_assert(board_ram_size <= (128 << 20)); -} -#endif diff --git a/arch/mips/ddb5xxx/common/rtc_ds1386.c b/arch/mips/ddb5xxx/common/rtc_ds1386.c deleted file mode 100644 index 5dc34daa7150..000000000000 --- a/arch/mips/ddb5xxx/common/rtc_ds1386.c +++ /dev/null @@ -1,170 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * arch/mips/ddb5xxx/common/rtc_ds1386.c - * low-level RTC hookups for s for Dallas 1396 chip. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - - -/* - * This file exports a function, rtc_ds1386_init(), which expects an - * uncached base address as the argument. It will set the two function - * pointers expected by the MIPS generic timer code. - */ - -#include <linux/types.h> -#include <linux/time.h> -#include <linux/bcd.h> - -#include <asm/time.h> -#include <asm/addrspace.h> - -#include <asm/mc146818rtc.h> -#include <asm/debug.h> - -#define EPOCH 2000 - -#define READ_RTC(x) *(volatile unsigned char*)(rtc_base+x) -#define WRITE_RTC(x, y) *(volatile unsigned char*)(rtc_base+x) = y - -static unsigned long rtc_base; - -static unsigned long -rtc_ds1386_get_time(void) -{ - u8 byte; - u8 temp; - unsigned int year, month, day, hour, minute, second; - unsigned long flags; - - spin_lock_irqsave(&rtc_lock, flags); - /* let us freeze external registers */ - byte = READ_RTC(0xB); - byte &= 0x3f; - WRITE_RTC(0xB, byte); - - /* read time data */ - year = BCD2BIN(READ_RTC(0xA)) + EPOCH; - month = BCD2BIN(READ_RTC(0x9) & 0x1f); - day = BCD2BIN(READ_RTC(0x8)); - minute = BCD2BIN(READ_RTC(0x2)); - second = BCD2BIN(READ_RTC(0x1)); - - /* hour is special - deal with it later */ - temp = READ_RTC(0x4); - - /* enable time transfer */ - byte |= 0x80; - WRITE_RTC(0xB, byte); - spin_unlock_irqrestore(&rtc_lock, flags); - - /* calc hour */ - if (temp & 0x40) { - /* 12 hour format */ - hour = BCD2BIN(temp & 0x1f); - if (temp & 0x20) hour += 12; /* PM */ - } else { - /* 24 hour format */ - hour = BCD2BIN(temp & 0x3f); - } - - return mktime(year, month, day, hour, minute, second); -} - -static int -rtc_ds1386_set_time(unsigned long t) -{ - struct rtc_time tm; - u8 byte; - u8 temp; - u8 year, month, day, hour, minute, second; - unsigned long flags; - - spin_lock_irqsave(&rtc_lock, flags); - /* let us freeze external registers */ - byte = READ_RTC(0xB); - byte &= 0x3f; - WRITE_RTC(0xB, byte); - - /* convert */ - to_tm(t, &tm); - - - /* check each field one by one */ - year = BIN2BCD(tm.tm_year - EPOCH); - if (year != READ_RTC(0xA)) { - WRITE_RTC(0xA, year); - } - - temp = READ_RTC(0x9); - month = BIN2BCD(tm.tm_mon+1); /* tm_mon starts from 0 to 11 */ - if (month != (temp & 0x1f)) { - WRITE_RTC( 0x9, - (month & 0x1f) | (temp & ~0x1f) ); - } - - day = BIN2BCD(tm.tm_mday); - if (day != READ_RTC(0x8)) { - WRITE_RTC(0x8, day); - } - - temp = READ_RTC(0x4); - if (temp & 0x40) { - /* 12 hour format */ - hour = 0x40; - if (tm.tm_hour > 12) { - hour |= 0x20 | (BIN2BCD(hour-12) & 0x1f); - } else { - hour |= BIN2BCD(tm.tm_hour); - } - } else { - /* 24 hour format */ - hour = BIN2BCD(tm.tm_hour) & 0x3f; - } - if (hour != temp) WRITE_RTC(0x4, hour); - - minute = BIN2BCD(tm.tm_min); - if (minute != READ_RTC(0x2)) { - WRITE_RTC(0x2, minute); - } - - second = BIN2BCD(tm.tm_sec); - if (second != READ_RTC(0x1)) { - WRITE_RTC(0x1, second); - } - spin_unlock_irqrestore(&rtc_lock, flags); - - return 0; -} - -void -rtc_ds1386_init(unsigned long base) -{ - unsigned char byte; - - /* remember the base */ - rtc_base = base; - db_assert((rtc_base & 0xe0000000) == KSEG1); - - /* turn on RTC if it is not on */ - byte = READ_RTC(0x9); - if (byte & 0x80) { - byte &= 0x7f; - WRITE_RTC(0x9, byte); - } - - /* enable time transfer */ - byte = READ_RTC(0xB); - byte |= 0x80; - WRITE_RTC(0xB, byte); - - /* set the function pointers */ - rtc_mips_get_time = rtc_ds1386_get_time; - rtc_mips_set_time = rtc_ds1386_set_time; -} diff --git a/arch/mips/ddb5xxx/ddb5477/Makefile b/arch/mips/ddb5xxx/ddb5477/Makefile deleted file mode 100644 index 4864b8a659c7..000000000000 --- a/arch/mips/ddb5xxx/ddb5477/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# Makefile for NEC DDB-Vrc5477 board -# - -obj-y += ddb5477-platform.o irq.o irq_5477.o setup.o \ - lcd44780.o - -obj-$(CONFIG_RUNTIME_DEBUG) += debug.o -obj-$(CONFIG_KGDB) += kgdb_io.o diff --git a/arch/mips/ddb5xxx/ddb5477/ddb5477-platform.c b/arch/mips/ddb5xxx/ddb5477/ddb5477-platform.c deleted file mode 100644 index c16020ad54c2..000000000000 --- a/arch/mips/ddb5xxx/ddb5477/ddb5477-platform.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) - */ -#include <linux/init.h> -#include <linux/module.h> -#include <linux/serial_8250.h> - -#include <asm/ddb5xxx/ddb5477.h> - -#define DDB_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP) - -#define DDB5477_PORT(base, int) \ -{ \ - .mapbase = base, \ - .irq = int, \ - .uartclk = 1843200, \ - .iotype = UPIO_MEM, \ - .flags = DDB_UART_FLAGS, \ - .regshift = 3, \ -} - -static struct plat_serial8250_port uart8250_data[] = { - DDB5477_PORT(0xbfa04200, VRC5477_IRQ_UART0), - DDB5477_PORT(0xbfa04240, VRC5477_IRQ_UART1), - { }, -}; - -static struct platform_device uart8250_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = uart8250_data, - }, -}; - -static int __init uart8250_init(void) -{ - return platform_device_register(&uart8250_device); -} - -module_init(uart8250_init); - -MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>"); -MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("8250 UART probe driver for the NEC DDB5477"); diff --git a/arch/mips/ddb5xxx/ddb5477/debug.c b/arch/mips/ddb5xxx/ddb5477/debug.c deleted file mode 100644 index 68919d5f8ffd..000000000000 --- a/arch/mips/ddb5xxx/ddb5477/debug.c +++ /dev/null @@ -1,160 +0,0 @@ -/*********************************************************************** - * - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * arch/mips/ddb5xxx/ddb5477/debug.c - * vrc5477 specific debug routines. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - *********************************************************************** - */ - -#include <linux/kernel.h> - -#include <asm/mipsregs.h> -#include <asm/ddb5xxx/ddb5xxx.h> - -typedef struct { - const char *regname; - unsigned regaddr; -} Register; - -void jsun_show_regs(char *name, Register *regs) -{ - int i; - - printk("\nshow regs: %s\n", name); - for(i=0;regs[i].regname!= NULL; i++) { - printk("%-16s= %08x\t\t(@%08x)\n", - regs[i].regname, - *(unsigned *)(regs[i].regaddr), - regs[i].regaddr); - } -} - -static Register int_regs[] = { - {"DDB_INTCTRL0", DDB_BASE + DDB_INTCTRL0}, - {"DDB_INTCTRL1", DDB_BASE + DDB_INTCTRL1}, - {"DDB_INTCTRL2", DDB_BASE + DDB_INTCTRL2}, - {"DDB_INTCTRL3", DDB_BASE + DDB_INTCTRL3}, - {"DDB_INT0STAT", DDB_BASE + DDB_INT0STAT}, - {"DDB_INT1STAT", DDB_BASE + DDB_INT1STAT}, - {"DDB_INT2STAT", DDB_BASE + DDB_INT2STAT}, - {"DDB_INT3STAT", DDB_BASE + DDB_INT3STAT}, - {"DDB_INT4STAT", DDB_BASE + DDB_INT4STAT}, - {"DDB_NMISTAT", DDB_BASE + DDB_NMISTAT}, - {"DDB_INTPPES0", DDB_BASE + DDB_INTPPES0}, - {"DDB_INTPPES1", DDB_BASE + DDB_INTPPES1}, - {NULL, 0x0} -}; - -void vrc5477_show_int_regs() -{ - jsun_show_regs("interrupt registers", int_regs); - printk("CPU CAUSE = %08x\n", read_c0_cause()); - printk("CPU STATUS = %08x\n", read_c0_status()); -} -static Register pdar_regs[] = { - {"DDB_SDRAM0", DDB_BASE + DDB_SDRAM0}, - {"DDB_SDRAM1", DDB_BASE + DDB_SDRAM1}, - {"DDB_LCS0", DDB_BASE + DDB_LCS0}, - {"DDB_LCS1", DDB_BASE + DDB_LCS1}, - {"DDB_LCS2", DDB_BASE + DDB_LCS2}, - {"DDB_INTCS", DDB_BASE + DDB_INTCS}, - {"DDB_BOOTCS", DDB_BASE + DDB_BOOTCS}, - {"DDB_PCIW0", DDB_BASE + DDB_PCIW0}, - {"DDB_PCIW1", DDB_BASE + DDB_PCIW1}, - {"DDB_IOPCIW0", DDB_BASE + DDB_IOPCIW0}, - {"DDB_IOPCIW1", DDB_BASE + DDB_IOPCIW1}, - {NULL, 0x0} -}; -void vrc5477_show_pdar_regs(void) -{ - jsun_show_regs("PDAR regs", pdar_regs); -} - -static Register bar_regs[] = { - {"DDB_BARC0", DDB_BASE + DDB_BARC0}, - {"DDB_BARM010", DDB_BASE + DDB_BARM010}, - {"DDB_BARM230", DDB_BASE + DDB_BARM230}, - {"DDB_BAR00", DDB_BASE + DDB_BAR00}, - {"DDB_BAR10", DDB_BASE + DDB_BAR10}, - {"DDB_BAR20", DDB_BASE + DDB_BAR20}, - {"DDB_BAR30", DDB_BASE + DDB_BAR30}, - {"DDB_BAR40", DDB_BASE + DDB_BAR40}, - {"DDB_BAR50", DDB_BASE + DDB_BAR50}, - {"DDB_BARB0", DDB_BASE + DDB_BARB0}, - {"DDB_BARC1", DDB_BASE + DDB_BARC1}, - {"DDB_BARM011", DDB_BASE + DDB_BARM011}, - {"DDB_BARM231", DDB_BASE + DDB_BARM231}, - {"DDB_BAR01", DDB_BASE + DDB_BAR01}, - {"DDB_BAR11", DDB_BASE + DDB_BAR11}, - {"DDB_BAR21", DDB_BASE + DDB_BAR21}, - {"DDB_BAR31", DDB_BASE + DDB_BAR31}, - {"DDB_BAR41", DDB_BASE + DDB_BAR41}, - {"DDB_BAR51", DDB_BASE + DDB_BAR51}, - {"DDB_BARB1", DDB_BASE + DDB_BARB1}, - {NULL, 0x0} -}; -void vrc5477_show_bar_regs(void) -{ - jsun_show_regs("BAR regs", bar_regs); -} - -static Register pci_regs[] = { - {"DDB_PCIW0", DDB_BASE + DDB_PCIW0}, - {"DDB_PCIW1", DDB_BASE + DDB_PCIW1}, - {"DDB_PCIINIT00", DDB_BASE + DDB_PCIINIT00}, - {"DDB_PCIINIT10", DDB_BASE + DDB_PCIINIT10}, - {"DDB_PCICTL0_L", DDB_BASE + DDB_PCICTL0_L}, - {"DDB_PCICTL0_H", DDB_BASE + DDB_PCICTL0_H}, - {"DDB_PCIARB0_L", DDB_BASE + DDB_PCIARB0_L}, - {"DDB_PCIARB0_H", DDB_BASE + DDB_PCIARB0_H}, - {"DDB_PCISWP0", DDB_BASE + DDB_PCISWP0}, - {"DDB_PCIERR0", DDB_BASE + DDB_PCIERR0}, - {"DDB_IOPCIW0", DDB_BASE + DDB_IOPCIW0}, - {"DDB_IOPCIW1", DDB_BASE + DDB_IOPCIW1}, - {"DDB_PCIINIT01", DDB_BASE + DDB_PCIINIT01}, - {"DDB_PCIINIT11", DDB_BASE + DDB_PCIINIT11}, - {"DDB_PCICTL1_L", DDB_BASE + DDB_PCICTL1_L}, - {"DDB_PCICTL1_H", DDB_BASE + DDB_PCICTL1_H}, - {"DDB_PCIARB1_L", DDB_BASE + DDB_PCIARB1_L}, - {"DDB_PCIARB1_H", DDB_BASE + DDB_PCIARB1_H}, - {"DDB_PCISWP1", DDB_BASE + DDB_PCISWP1}, - {"DDB_PCIERR1", DDB_BASE + DDB_PCIERR1}, - {NULL, 0x0} -}; -void vrc5477_show_pci_regs(void) -{ - jsun_show_regs("PCI regs", pci_regs); -} - -static Register lb_regs[] = { - {"DDB_LCNFG", DDB_BASE + DDB_LCNFG}, - {"DDB_LCST0", DDB_BASE + DDB_LCST0}, - {"DDB_LCST1", DDB_BASE + DDB_LCST1}, - {"DDB_LCST2", DDB_BASE + DDB_LCST2}, - {"DDB_ERRADR", DDB_BASE + DDB_ERRADR}, - {"DDB_ERRCS", DDB_BASE + DDB_ERRCS}, - {"DDB_BTM", DDB_BASE + DDB_BTM}, - {"DDB_BCST", DDB_BASE + DDB_BCST}, - {NULL, 0x0} -}; -void vrc5477_show_lb_regs(void) -{ - jsun_show_regs("Local Bus regs", lb_regs); -} - -void vrc5477_show_all_regs(void) -{ - vrc5477_show_pdar_regs(); - vrc5477_show_pci_regs(); - vrc5477_show_bar_regs(); - vrc5477_show_int_regs(); - vrc5477_show_lb_regs(); -} diff --git a/arch/mips/ddb5xxx/ddb5477/irq.c b/arch/mips/ddb5xxx/ddb5477/irq.c deleted file mode 100644 index faa4a506bf82..000000000000 --- a/arch/mips/ddb5xxx/ddb5477/irq.c +++ /dev/null @@ -1,209 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * arch/mips/ddb5xxx/ddb5477/irq.c - * The irq setup and misc routines for DDB5476. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/types.h> -#include <linux/ptrace.h> - -#include <asm/i8259.h> -#include <asm/irq_cpu.h> -#include <asm/system.h> -#include <asm/mipsregs.h> -#include <asm/debug.h> -#include <asm/addrspace.h> -#include <asm/bootinfo.h> - -#include <asm/ddb5xxx/ddb5xxx.h> - - -/* - * IRQ mapping - * - * 0-7: 8 CPU interrupts - * 0 - software interrupt 0 - * 1 - software interrupt 1 - * 2 - most Vrc5477 interrupts are routed to this pin - * 3 - (optional) some other interrupts routed to this pin for debugg - * 4 - not used - * 5 - not used - * 6 - not used - * 7 - cpu timer (used by default) - * - * 8-39: 32 Vrc5477 interrupt sources - * (refer to the Vrc5477 manual) - */ - -#define PCI0 DDB_INTPPES0 -#define PCI1 DDB_INTPPES1 - -#define ACTIVE_LOW 1 -#define ACTIVE_HIGH 0 - -#define LEVEL_SENSE 2 -#define EDGE_TRIGGER 0 - -#define INTA 0 -#define INTB 1 -#define INTC 2 -#define INTD 3 -#define INTE 4 - -static inline void -set_pci_int_attr(u32 pci, u32 intn, u32 active, u32 trigger) -{ - u32 reg_value; - u32 reg_bitmask; - - reg_value = ddb_in32(pci); - reg_bitmask = 0x3 << (intn * 2); - - reg_value &= ~reg_bitmask; - reg_value |= (active | trigger) << (intn * 2); - ddb_out32(pci, reg_value); -} - -extern void vrc5477_irq_init(u32 base); -static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL }; - -void __init arch_init_irq(void) -{ - /* by default, we disable all interrupts and route all vrc5477 - * interrupts to pin 0 (irq 2) */ - ddb_out32(DDB_INTCTRL0, 0); - ddb_out32(DDB_INTCTRL1, 0); - ddb_out32(DDB_INTCTRL2, 0); - ddb_out32(DDB_INTCTRL3, 0); - - clear_c0_status(0xff00); - set_c0_status(0x0400); - - /* setup PCI interrupt attributes */ - set_pci_int_attr(PCI0, INTA, ACTIVE_LOW, LEVEL_SENSE); - set_pci_int_attr(PCI0, INTB, ACTIVE_LOW, LEVEL_SENSE); - if (mips_machtype == MACH_NEC_ROCKHOPPERII) - set_pci_int_attr(PCI0, INTC, ACTIVE_HIGH, LEVEL_SENSE); - else - set_pci_int_attr(PCI0, INTC, ACTIVE_LOW, LEVEL_SENSE); - set_pci_int_attr(PCI0, INTD, ACTIVE_LOW, LEVEL_SENSE); - set_pci_int_attr(PCI0, INTE, ACTIVE_LOW, LEVEL_SENSE); - - set_pci_int_attr(PCI1, INTA, ACTIVE_LOW, LEVEL_SENSE); - set_pci_int_attr(PCI1, INTB, ACTIVE_LOW, LEVEL_SENSE); - set_pci_int_attr(PCI1, INTC, ACTIVE_LOW, LEVEL_SENSE); - set_pci_int_attr(PCI1, INTD, ACTIVE_LOW, LEVEL_SENSE); - set_pci_int_attr(PCI1, INTE, ACTIVE_LOW, LEVEL_SENSE); - - /* - * for debugging purpose, we enable several error interrupts - * and route them to pin 1. (IP3) - */ - /* cpu parity check - 0 */ - ll_vrc5477_irq_route(0, 1); ll_vrc5477_irq_enable(0); - /* cpu no-target decode - 1 */ - ll_vrc5477_irq_route(1, 1); ll_vrc5477_irq_enable(1); - /* local bus read time-out - 7 */ - ll_vrc5477_irq_route(7, 1); ll_vrc5477_irq_enable(7); - /* PCI SERR# - 14 */ - ll_vrc5477_irq_route(14, 1); ll_vrc5477_irq_enable(14); - /* PCI internal error - 15 */ - ll_vrc5477_irq_route(15, 1); ll_vrc5477_irq_enable(15); - /* IOPCI SERR# - 30 */ - ll_vrc5477_irq_route(30, 1); ll_vrc5477_irq_enable(30); - /* IOPCI internal error - 31 */ - ll_vrc5477_irq_route(31, 1); ll_vrc5477_irq_enable(31); - - /* init all controllers */ - init_i8259_irqs(); - mips_cpu_irq_init(); - vrc5477_irq_init(VRC5477_IRQ_BASE); - - - /* setup cascade interrupts */ - setup_irq(VRC5477_IRQ_BASE + VRC5477_I8259_CASCADE, &irq_cascade); - setup_irq(CPU_IRQ_BASE + CPU_VRC5477_CASCADE, &irq_cascade); -} - -u8 i8259_interrupt_ack(void) -{ - u8 irq; - u32 reg; - - /* Set window 0 for interrupt acknowledge */ - reg = ddb_in32(DDB_PCIINIT10); - - ddb_set_pmr(DDB_PCIINIT10, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32); - irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE); - ddb_out32(DDB_PCIINIT10, reg); - - return irq; -} -/* - * the first level int-handler will jump here if it is a vrc5477 irq - */ -#define NUM_5477_IRQS 32 -static void vrc5477_irq_dispatch(void) -{ - u32 intStatus; - u32 bitmask; - u32 i; - - db_assert(ddb_in32(DDB_INT2STAT) == 0); - db_assert(ddb_in32(DDB_INT3STAT) == 0); - db_assert(ddb_in32(DDB_INT4STAT) == 0); - db_assert(ddb_in32(DDB_NMISTAT) == 0); - - if (ddb_in32(DDB_INT1STAT) != 0) { -#if defined(CONFIG_RUNTIME_DEBUG) - vrc5477_show_int_regs(); -#endif - panic("error interrupt has happened."); - } - - intStatus = ddb_in32(DDB_INT0STAT); - - if (mips_machtype == MACH_NEC_ROCKHOPPERII) { - /* check for i8259 interrupts */ - if (intStatus & (1 << VRC5477_I8259_CASCADE)) { - int i8259_irq = i8259_interrupt_ack(); - do_IRQ(i8259_irq); - return; - } - } - - for (i=0, bitmask=1; i<= NUM_5477_IRQS; bitmask <<=1, i++) { - /* do we need to "and" with the int mask? */ - if (intStatus & bitmask) { - do_IRQ(VRC5477_IRQ_BASE + i); - return; - } - } -} - -#define VR5477INTS (STATUSF_IP2|STATUSF_IP3|STATUSF_IP4|STATUSF_IP5|STATUSF_IP6) - -asmlinkage void plat_irq_dispatch(void) -{ - unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; - - if (pending & STATUSF_IP7) - do_IRQ(CPU_IRQ_BASE + 7); - else if (pending & VR5477INTS) - vrc5477_irq_dispatch(); - else if (pending & STATUSF_IP0) - do_IRQ(CPU_IRQ_BASE); - else if (pending & STATUSF_IP1) - do_IRQ(CPU_IRQ_BASE + 1); - else - spurious_interrupt(); -} diff --git a/arch/mips/ddb5xxx/ddb5477/irq_5477.c b/arch/mips/ddb5xxx/ddb5477/irq_5477.c deleted file mode 100644 index 98c3b15eb369..000000000000 --- a/arch/mips/ddb5xxx/ddb5477/irq_5477.c +++ /dev/null @@ -1,154 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * arch/mips/ddb5xxx/ddb5477/irq_5477.c - * This file defines the irq handler for Vrc5477. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -/* - * Vrc5477 defines 32 IRQs. - * - * This file exports one function: - * vrc5477_irq_init(u32 irq_base); - */ - -#include <linux/interrupt.h> -#include <linux/types.h> -#include <linux/ptrace.h> - -#include <asm/debug.h> - -#include <asm/ddb5xxx/ddb5xxx.h> - -/* number of total irqs supported by Vrc5477 */ -#define NUM_5477_IRQ 32 - -static int vrc5477_irq_base = -1; - - -static void -vrc5477_irq_enable(unsigned int irq) -{ - db_assert(vrc5477_irq_base != -1); - db_assert(irq >= vrc5477_irq_base); - db_assert(irq < vrc5477_irq_base+ NUM_5477_IRQ); - - ll_vrc5477_irq_enable(irq - vrc5477_irq_base); -} - -static void -vrc5477_irq_disable(unsigned int irq) -{ - db_assert(vrc5477_irq_base != -1); - db_assert(irq >= vrc5477_irq_base); - db_assert(irq < vrc5477_irq_base + NUM_5477_IRQ); - - ll_vrc5477_irq_disable(irq - vrc5477_irq_base); -} - -static void -vrc5477_irq_ack(unsigned int irq) -{ - db_assert(vrc5477_irq_base != -1); - db_assert(irq >= vrc5477_irq_base); - db_assert(irq < vrc5477_irq_base+ NUM_5477_IRQ); - - /* clear the interrupt bit */ - /* some irqs require the driver to clear the sources */ - ddb_out32(DDB_INTCLR32, 1 << (irq - vrc5477_irq_base)); - - /* disable interrupt - some handler will re-enable the irq - * and if the interrupt is leveled, we will have infinite loop - */ - ll_vrc5477_irq_disable(irq - vrc5477_irq_base); -} - -static void -vrc5477_irq_end(unsigned int irq) -{ - db_assert(vrc5477_irq_base != -1); - db_assert(irq >= vrc5477_irq_base); - db_assert(irq < vrc5477_irq_base + NUM_5477_IRQ); - - if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - ll_vrc5477_irq_enable( irq - vrc5477_irq_base); -} - -struct irq_chip vrc5477_irq_controller = { - .name = "vrc5477_irq", - .ack = vrc5477_irq_ack, - .mask = vrc5477_irq_disable, - .mask_ack = vrc5477_irq_ack, - .unmask = vrc5477_irq_enable, - .end = vrc5477_irq_end -}; - -void __init vrc5477_irq_init(u32 irq_base) -{ - u32 i; - - for (i= irq_base; i< irq_base+ NUM_5477_IRQ; i++) - set_irq_chip(i, &vrc5477_irq_controller); - - vrc5477_irq_base = irq_base; -} - -void ll_vrc5477_irq_route(int vrc5477_irq, int ip) -{ - u32 reg_value; - u32 reg_bitmask; - u32 reg_index; - - db_assert(vrc5477_irq >= 0); - db_assert(vrc5477_irq < NUM_5477_IRQ); - db_assert(ip >= 0); - db_assert((ip < 5) || (ip == 6)); - - reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4; - reg_value = ddb_in32(reg_index); - reg_bitmask = 7 << (vrc5477_irq % 8 * 4); - reg_value &= ~reg_bitmask; - reg_value |= ip << (vrc5477_irq % 8 * 4); - ddb_out32(reg_index, reg_value); -} - -void ll_vrc5477_irq_enable(int vrc5477_irq) -{ - u32 reg_value; - u32 reg_bitmask; - u32 reg_index; - - db_assert(vrc5477_irq >= 0); - db_assert(vrc5477_irq < NUM_5477_IRQ); - - reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4; - reg_value = ddb_in32(reg_index); - reg_bitmask = 8 << (vrc5477_irq % 8 * 4); - db_assert((reg_value & reg_bitmask) == 0); - ddb_out32(reg_index, reg_value | reg_bitmask); -} - -void ll_vrc5477_irq_disable(int vrc5477_irq) -{ - u32 reg_value; - u32 reg_bitmask; - u32 reg_index; - - db_assert(vrc5477_irq >= 0); - db_assert(vrc5477_irq < NUM_5477_IRQ); - - reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4; - reg_value = ddb_in32(reg_index); - reg_bitmask = 8 << (vrc5477_irq % 8 * 4); - - /* we assert that the interrupt is enabled (perhaps over-zealous) */ - db_assert( (reg_value & reg_bitmask) != 0); - ddb_out32(reg_index, reg_value & ~reg_bitmask); -} diff --git a/arch/mips/ddb5xxx/ddb5477/kgdb_io.c b/arch/mips/ddb5xxx/ddb5477/kgdb_io.c deleted file mode 100644 index 385bbdb10170..000000000000 --- a/arch/mips/ddb5xxx/ddb5477/kgdb_io.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * kgdb io functions for DDB5477. We use the second serial port (upper one). - * - * Copyright (C) 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -/* ======================= CONFIG ======================== */ - -/* [jsun] we use the second serial port for kdb */ -#define BASE 0xbfa04240 -#define MAX_BAUD 115200 - -/* distance in bytes between two serial registers */ -#define REG_OFFSET 8 - -/* - * 0 - kgdb does serial init - * 1 - kgdb skip serial init - */ -static int remoteDebugInitialized = 0; - -/* - * the default baud rate *if* kgdb does serial init - */ -#define BAUD_DEFAULT UART16550_BAUD_38400 - -/* ======================= END OF CONFIG ======================== */ - -typedef unsigned char uint8; -typedef unsigned int uint32; - -#define UART16550_BAUD_2400 2400 -#define UART16550_BAUD_4800 4800 -#define UART16550_BAUD_9600 9600 -#define UART16550_BAUD_19200 19200 -#define UART16550_BAUD_38400 38400 -#define UART16550_BAUD_57600 57600 -#define UART16550_BAUD_115200 115200 - -#define UART16550_PARITY_NONE 0 -#define UART16550_PARITY_ODD 0x08 -#define UART16550_PARITY_EVEN 0x18 -#define UART16550_PARITY_MARK 0x28 -#define UART16550_PARITY_SPACE 0x38 - -#define UART16550_DATA_5BIT 0x0 -#define UART16550_DATA_6BIT 0x1 -#define UART16550_DATA_7BIT 0x2 -#define UART16550_DATA_8BIT 0x3 - -#define UART16550_STOP_1BIT 0x0 -#define UART16550_STOP_2BIT 0x4 - -/* register offset */ -#define OFS_RCV_BUFFER 0 -#define OFS_TRANS_HOLD 0 -#define OFS_SEND_BUFFER 0 -#define OFS_INTR_ENABLE (1*REG_OFFSET) -#define OFS_INTR_ID (2*REG_OFFSET) -#define OFS_DATA_FORMAT (3*REG_OFFSET) -#define OFS_LINE_CONTROL (3*REG_OFFSET) -#define OFS_MODEM_CONTROL (4*REG_OFFSET) -#define OFS_RS232_OUTPUT (4*REG_OFFSET) -#define OFS_LINE_STATUS (5*REG_OFFSET) -#define OFS_MODEM_STATUS (6*REG_OFFSET) -#define OFS_RS232_INPUT (6*REG_OFFSET) -#define OFS_SCRATCH_PAD (7*REG_OFFSET) - -#define OFS_DIVISOR_LSB (0*REG_OFFSET) -#define OFS_DIVISOR_MSB (1*REG_OFFSET) - - -/* memory-mapped read/write of the port */ -#define UART16550_READ(y) (*((volatile uint8*)(BASE + y))) -#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z) - -void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop) -{ - /* disable interrupts */ - UART16550_WRITE(OFS_INTR_ENABLE, 0); - - /* set up baud rate */ - { - uint32 divisor; - - /* set DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x80); - - /* set divisor */ - divisor = MAX_BAUD / baud; - UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff); - UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8); - - /* clear DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x0); - } - - /* set data format */ - UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop); -} - - -uint8 getDebugChar(void) -{ - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(BAUD_DEFAULT, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); - } - - while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0); - return UART16550_READ(OFS_RCV_BUFFER); -} - - -int putDebugChar(uint8 byte) -{ - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(BAUD_DEFAULT, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); - } - - while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0); - UART16550_WRITE(OFS_SEND_BUFFER, byte); - return 1; -} diff --git a/arch/mips/ddb5xxx/ddb5477/lcd44780.c b/arch/mips/ddb5xxx/ddb5477/lcd44780.c deleted file mode 100644 index 9510b9ae6453..000000000000 --- a/arch/mips/ddb5xxx/ddb5477/lcd44780.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * lcd44780.c - * Simple "driver" for a memory-mapped 44780-style LCD display. - * - * Copyright 2001 Bradley D. LaRonde <brad@ltc.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#define LCD44780_COMMAND ((volatile unsigned char *)0xbe020000) -#define LCD44780_DATA ((volatile unsigned char *)0xbe020001) - -#define LCD44780_4BIT_1LINE 0x20 -#define LCD44780_4BIT_2LINE 0x28 -#define LCD44780_8BIT_1LINE 0x30 -#define LCD44780_8BIT_2LINE 0x38 -#define LCD44780_MODE_DEC 0x04 -#define LCD44780_MODE_DEC_SHIFT 0x05 -#define LCD44780_MODE_INC 0x06 -#define LCD44780_MODE_INC_SHIFT 0x07 -#define LCD44780_SCROLL_LEFT 0x18 -#define LCD44780_SCROLL_RIGHT 0x1e -#define LCD44780_CURSOR_UNDERLINE 0x0e -#define LCD44780_CURSOR_BLOCK 0x0f -#define LCD44780_CURSOR_OFF 0x0c -#define LCD44780_CLEAR 0x01 -#define LCD44780_BLANK 0x08 -#define LCD44780_RESTORE 0x0c // Same as CURSOR_OFF -#define LCD44780_HOME 0x02 -#define LCD44780_LEFT 0x10 -#define LCD44780_RIGHT 0x14 - -void lcd44780_wait(void) -{ - int i, j; - for(i=0; i < 400; i++) - for(j=0; j < 10000; j++); -} - -void lcd44780_command(unsigned char c) -{ - *LCD44780_COMMAND = c; - lcd44780_wait(); -} - -void lcd44780_data(unsigned char c) -{ - *LCD44780_DATA = c; - lcd44780_wait(); -} - -void lcd44780_puts(const char* s) -{ - int j; - int pos = 0; - - lcd44780_command(LCD44780_CLEAR); - while(*s) { - lcd44780_data(*s); - s++; - pos++; - if (pos == 8) { - /* We must write 32 of spaces to get cursor to 2nd line */ - for (j=0; j<32; j++) { - lcd44780_data(' '); - } - } - if (pos == 16) { - /* We have filled all 16 character positions, so stop - outputing data */ - break; - } - } -#ifdef LCD44780_PUTS_PAUSE - { - int i; - - for(i = 1; i < 2000; i++) - lcd44780_wait(); - } -#endif -} - -void lcd44780_init(void) -{ - // The display on the RockHopper is physically a single - // 16 char line (two 8 char lines concatenated). bdl - lcd44780_command(LCD44780_8BIT_2LINE); - lcd44780_command(LCD44780_MODE_INC); - lcd44780_command(LCD44780_CURSOR_BLOCK); - lcd44780_command(LCD44780_CLEAR); -} diff --git a/arch/mips/ddb5xxx/ddb5477/lcd44780.h b/arch/mips/ddb5xxx/ddb5477/lcd44780.h deleted file mode 100644 index cf2f0f71eee5..000000000000 --- a/arch/mips/ddb5xxx/ddb5477/lcd44780.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * lcd44780.h - * Simple "driver" for a memory-mapped 44780-style LCD display. - * - * Copyright 2001 Bradley D. LaRonde <brad@ltc.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -void lcd44780_puts(const char* s); -void lcd44780_init(void); diff --git a/arch/mips/ddb5xxx/ddb5477/setup.c b/arch/mips/ddb5xxx/ddb5477/setup.c deleted file mode 100644 index f0cc0e8a8afa..000000000000 --- a/arch/mips/ddb5xxx/ddb5477/setup.c +++ /dev/null @@ -1,399 +0,0 @@ -/* - * - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) - * - * arch/mips/ddb5xxx/ddb5477/setup.c - * Setup file for DDB5477. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/sched.h> -#include <linux/pci.h> -#include <linux/ide.h> -#include <linux/irq.h> -#include <linux/fs.h> -#include <linux/ioport.h> -#include <linux/param.h> /* for HZ */ -#include <linux/major.h> -#include <linux/kdev_t.h> -#include <linux/root_dev.h> -#include <linux/pm.h> - -#include <asm/cpu.h> -#include <asm/bootinfo.h> -#include <asm/addrspace.h> -#include <asm/time.h> -#include <asm/bcache.h> -#include <asm/irq.h> -#include <asm/reboot.h> -#include <asm/gdb-stub.h> -#include <asm/traps.h> -#include <asm/debug.h> - -#include <asm/ddb5xxx/ddb5xxx.h> - -#include "lcd44780.h" - - -#define USE_CPU_COUNTER_TIMER /* whether we use cpu counter */ - -#define SP_TIMER_BASE DDB_SPT1CTRL_L -#define SP_TIMER_IRQ VRC5477_IRQ_SPT1 - -static int bus_frequency = CONFIG_DDB5477_BUS_FREQUENCY*1000; - -static void ddb_machine_restart(char *command) -{ - static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000; - - u32 t; - - /* PCI cold reset */ - ddb_pci_reset_bus(); - - /* CPU cold reset */ - t = ddb_in32(DDB_CPUSTAT); - db_assert((t&1)); - ddb_out32(DDB_CPUSTAT, t); - - /* Call the PROM */ - back_to_prom(); -} - -static void ddb_machine_halt(void) -{ - printk("DDB Vrc-5477 halted.\n"); - while (1); -} - -static void ddb_machine_power_off(void) -{ - printk("DDB Vrc-5477 halted. Please turn off the power.\n"); - while (1); -} - -extern void rtc_ds1386_init(unsigned long base); - -static unsigned int __init detect_bus_frequency(unsigned long rtc_base) -{ - unsigned int freq; - unsigned char c; - unsigned int t1, t2; - unsigned i; - - ddb_out32(SP_TIMER_BASE, 0xffffffff); - ddb_out32(SP_TIMER_BASE+4, 0x1); - ddb_out32(SP_TIMER_BASE+8, 0xffffffff); - - /* check if rtc is running */ - c= *(volatile unsigned char*)rtc_base; - for(i=0; (c == *(volatile unsigned char*)rtc_base) && (i<100000000); i++); - if (c == *(volatile unsigned char*)rtc_base) { - printk("Failed to detect bus frequency. Use default 83.3MHz.\n"); - return 83333000; - } - - c= *(volatile unsigned char*)rtc_base; - while (c == *(volatile unsigned char*)rtc_base); - /* we are now at the turn of 1/100th second, if no error. */ - t1 = ddb_in32(SP_TIMER_BASE+8); - - for (i=0; i< 10; i++) { - c= *(volatile unsigned char*)rtc_base; - while (c == *(volatile unsigned char*)rtc_base); - /* we are now at the turn of another 1/100th second */ - t2 = ddb_in32(SP_TIMER_BASE+8); - } - - ddb_out32(SP_TIMER_BASE+4, 0x0); /* disable it again */ - - freq = (t1 - t2)*10; - printk("DDB bus frequency detection : %u \n", freq); - return freq; -} - -static void __init ddb_time_init(void) -{ - unsigned long rtc_base; - unsigned int i; - - /* we have ds1396 RTC chip */ - if (mips_machtype == MACH_NEC_ROCKHOPPER - || mips_machtype == MACH_NEC_ROCKHOPPERII) { - rtc_base = KSEG1ADDR(DDB_LCS2_BASE); - } else { - rtc_base = KSEG1ADDR(DDB_LCS1_BASE); - } - rtc_ds1386_init(rtc_base); - - /* do we need to do run-time detection of bus speed? */ - if (bus_frequency == 0) { - bus_frequency = detect_bus_frequency(rtc_base); - } - - /* mips_hpt_frequency is 1/2 of the cpu core freq */ - i = (read_c0_config() >> 28 ) & 7; - if ((current_cpu_data.cputype == CPU_R5432) && (i == 3)) - i = 4; - mips_hpt_frequency = bus_frequency*(i+4)/4; -} - -void __init plat_timer_setup(struct irqaction *irq) -{ -#if defined(USE_CPU_COUNTER_TIMER) - - /* we are using the cpu counter for timer interrupts */ - setup_irq(CPU_IRQ_BASE + 7, irq); - -#else - - /* if we use Special purpose timer 1 */ - ddb_out32(SP_TIMER_BASE, bus_frequency/HZ); - ddb_out32(SP_TIMER_BASE+4, 0x1); - setup_irq(SP_TIMER_IRQ, irq); - -#endif -} - -static void ddb5477_board_init(void); - -extern struct pci_controller ddb5477_ext_controller; -extern struct pci_controller ddb5477_io_controller; - -void __init plat_mem_setup(void) -{ - /* initialize board - we don't trust the loader */ - ddb5477_board_init(); - - set_io_port_base(KSEG1ADDR(DDB_PCI_IO_BASE)); - - board_time_init = ddb_time_init; - - _machine_restart = ddb_machine_restart; - _machine_halt = ddb_machine_halt; - pm_power_off = ddb_machine_power_off; - - /* setup resource limits */ - ioport_resource.end = DDB_PCI0_IO_SIZE + DDB_PCI1_IO_SIZE - 1; - iomem_resource.end = 0xffffffff; - - /* Reboot on panic */ - panic_timeout = 180; - - register_pci_controller (&ddb5477_ext_controller); - register_pci_controller (&ddb5477_io_controller); -} - -static void __init ddb5477_board_init(void) -{ - /* ----------- setup PDARs ------------ */ - - /* SDRAM should have been set */ - db_assert(ddb_in32(DDB_SDRAM0) == - ddb_calc_pdar(DDB_SDRAM_BASE, board_ram_size, 32, 0, 1)); - - /* SDRAM1 should be turned off. What is this for anyway ? */ - db_assert( (ddb_in32(DDB_SDRAM1) & 0xf) == 0); - - /* Setup local bus. */ - - /* Flash U12 PDAR and timing. */ - ddb_set_pdar(DDB_LCS0, DDB_LCS0_BASE, DDB_LCS0_SIZE, 16, 0, 0); - ddb_out32(DDB_LCST0, 0x00090842); - - /* We need to setup LCS1 and LCS2 differently based on the - board_version */ - if (mips_machtype == MACH_NEC_ROCKHOPPER) { - /* Flash U13 PDAR and timing. */ - ddb_set_pdar(DDB_LCS1, DDB_LCS1_BASE, DDB_LCS1_SIZE, 16, 0, 0); - ddb_out32(DDB_LCST1, 0x00090842); - - /* EPLD (NVRAM, switch, LCD, and mezzanie). */ - ddb_set_pdar(DDB_LCS2, DDB_LCS2_BASE, DDB_LCS2_SIZE, 8, 0, 0); - } else { - /* misc */ - ddb_set_pdar(DDB_LCS1, DDB_LCS1_BASE, DDB_LCS1_SIZE, 8, 0, 0); - /* mezzanie (?) */ - ddb_set_pdar(DDB_LCS2, DDB_LCS2_BASE, DDB_LCS2_SIZE, 16, 0, 0); - } - - /* verify VRC5477 base addr */ - db_assert(ddb_in32(DDB_VRC5477) == - ddb_calc_pdar(DDB_VRC5477_BASE, DDB_VRC5477_SIZE, 32, 0, 1)); - - /* verify BOOT ROM addr */ - db_assert(ddb_in32(DDB_BOOTCS) == - ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0)); - - /* setup PCI windows - window0 for MEM/config, window1 for IO */ - ddb_set_pdar(DDB_PCIW0, DDB_PCI0_MEM_BASE, DDB_PCI0_MEM_SIZE, 32, 0, 1); - ddb_set_pdar(DDB_PCIW1, DDB_PCI0_IO_BASE, DDB_PCI0_IO_SIZE, 32, 0, 1); - ddb_set_pdar(DDB_IOPCIW0, DDB_PCI1_MEM_BASE, DDB_PCI1_MEM_SIZE, 32, 0, 1); - ddb_set_pdar(DDB_IOPCIW1, DDB_PCI1_IO_BASE, DDB_PCI1_IO_SIZE, 32, 0, 1); - - /* ------------ reset PCI bus and BARs ----------------- */ - ddb_pci_reset_bus(); - - ddb_out32(DDB_BARM010, 0x00000008); - ddb_out32(DDB_BARM011, 0x00000008); - - ddb_out32(DDB_BARC0, 0xffffffff); - ddb_out32(DDB_BARM230, 0xffffffff); - ddb_out32(DDB_BAR00, 0xffffffff); - ddb_out32(DDB_BAR10, 0xffffffff); - ddb_out32(DDB_BAR20, 0xffffffff); - ddb_out32(DDB_BAR30, 0xffffffff); - ddb_out32(DDB_BAR40, 0xffffffff); - ddb_out32(DDB_BAR50, 0xffffffff); - ddb_out32(DDB_BARB0, 0xffffffff); - - ddb_out32(DDB_BARC1, 0xffffffff); - ddb_out32(DDB_BARM231, 0xffffffff); - ddb_out32(DDB_BAR01, 0xffffffff); - ddb_out32(DDB_BAR11, 0xffffffff); - ddb_out32(DDB_BAR21, 0xffffffff); - ddb_out32(DDB_BAR31, 0xffffffff); - ddb_out32(DDB_BAR41, 0xffffffff); - ddb_out32(DDB_BAR51, 0xffffffff); - ddb_out32(DDB_BARB1, 0xffffffff); - - /* - * We use pci master register 0 for memory space / config space - * And we use register 1 for IO space. - * Note that for memory space, we bump up the pci base address - * so that we have 1:1 mapping between PCI memory and cpu physical. - * For PCI IO space, it starts from 0 in PCI IO space but with - * DDB_xx_IO_BASE in CPU physical address space. - */ - ddb_set_pmr(DDB_PCIINIT00, DDB_PCICMD_MEM, DDB_PCI0_MEM_BASE, - DDB_PCI_ACCESS_32); - ddb_set_pmr(DDB_PCIINIT10, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32); - - ddb_set_pmr(DDB_PCIINIT01, DDB_PCICMD_MEM, DDB_PCI1_MEM_BASE, - DDB_PCI_ACCESS_32); - ddb_set_pmr(DDB_PCIINIT11, DDB_PCICMD_IO, DDB_PCI0_IO_SIZE, - DDB_PCI_ACCESS_32); - - - /* PCI cross window should be set properly */ - ddb_set_pdar(DDB_BARP00, DDB_PCI1_MEM_BASE, DDB_PCI1_MEM_SIZE, 32, 0, 1); - ddb_set_pdar(DDB_BARP10, DDB_PCI1_IO_BASE, DDB_PCI1_IO_SIZE, 32, 0, 1); - ddb_set_pdar(DDB_BARP01, DDB_PCI0_MEM_BASE, DDB_PCI0_MEM_SIZE, 32, 0, 1); - ddb_set_pdar(DDB_BARP11, DDB_PCI0_IO_BASE, DDB_PCI0_IO_SIZE, 32, 0, 1); - - if (mips_machtype == MACH_NEC_ROCKHOPPER - || mips_machtype == MACH_NEC_ROCKHOPPERII) { - /* Disable bus diagnostics. */ - ddb_out32(DDB_PCICTL0_L, 0); - ddb_out32(DDB_PCICTL0_H, 0); - ddb_out32(DDB_PCICTL1_L, 0); - ddb_out32(DDB_PCICTL1_H, 0); - } - - if (mips_machtype == MACH_NEC_ROCKHOPPER) { - u16 vid; - struct pci_bus bus; - struct pci_dev dev_m1533; - extern struct pci_ops ddb5477_ext_pci_ops; - - bus.parent = NULL; /* we scan the top level only */ - bus.ops = &ddb5477_ext_pci_ops; - dev_m1533.bus = &bus; - dev_m1533.sysdata = NULL; - dev_m1533.devfn = 7*8; // slot 7: M1533 SouthBridge. - pci_read_config_word(&dev_m1533, 0, &vid); - if (vid == PCI_VENDOR_ID_AL) { - printk("Changing mips_machtype to MACH_NEC_ROCKHOPPERII\n"); - mips_machtype = MACH_NEC_ROCKHOPPERII; - } - } - - /* enable USB input buffers */ - ddb_out32(DDB_PIBMISC, 0x00000007); - - /* For dual-function pins, make them all non-GPIO */ - ddb_out32(DDB_GIUFUNSEL, 0x0); - // ddb_out32(DDB_GIUFUNSEL, 0xfe0fcfff); /* NEC recommanded value */ - - if (mips_machtype == MACH_NEC_ROCKHOPPERII) { - - /* enable IDE controller on Ali chip (south bridge) */ - u8 temp8; - struct pci_bus bus; - struct pci_dev dev_m1533; - struct pci_dev dev_m5229; - extern struct pci_ops ddb5477_ext_pci_ops; - - /* Setup M1535 registers */ - bus.parent = NULL; /* we scan the top level only */ - bus.ops = &ddb5477_ext_pci_ops; - dev_m1533.bus = &bus; - dev_m1533.sysdata = NULL; - dev_m1533.devfn = 7*8; // slot 7: M1533 SouthBridge. - - /* setup IDE controller - * enable IDE controller (bit 6 - 1) - * IDE IDSEL to be addr:A15 (bit 4:5 - 11) - * disable IDE ATA Secondary Bus Signal Pad Control (bit 3 - 0) - * enable IDE ATA Primary Bus Signal Pad Control (bit 2 - 1) - */ - pci_write_config_byte(&dev_m1533, 0x58, 0x74); - - /* - * positive decode (bit6 -0) - * enable IDE controler interrupt (bit 4 -1) - * setup SIRQ to point to IRQ 14 (bit 3:0 - 1101) - */ - pci_write_config_byte(&dev_m1533, 0x44, 0x1d); - - /* Setup M5229 registers */ - dev_m5229.bus = &bus; - dev_m5229.sysdata = NULL; - dev_m5229.devfn = 4*8; // slot 4 (AD15): M5229 IDE - - /* - * enable IDE in the M5229 config register 0x50 (bit 0 - 1) - * M5229 IDSEL is addr:15; see above setting - */ - pci_read_config_byte(&dev_m5229, 0x50, &temp8); - pci_write_config_byte(&dev_m5229, 0x50, temp8 | 0x1); - - /* - * enable bus master (bit 2) and IO decoding (bit 0) - */ - pci_read_config_byte(&dev_m5229, 0x04, &temp8); - pci_write_config_byte(&dev_m5229, 0x04, temp8 | 0x5); - - /* - * enable native, copied from arch/ppc/k2boot/head.S - * TODO - need volatile, need to be portable - */ - pci_write_config_byte(&dev_m5229, 0x09, 0xef); - - /* Set Primary Channel Command Block Timing */ - pci_write_config_byte(&dev_m5229, 0x59, 0x31); - - /* - * Enable primary channel 40-pin cable - * M5229 register 0x4a (bit 0) - */ - pci_read_config_byte(&dev_m5229, 0x4a, &temp8); - pci_write_config_byte(&dev_m5229, 0x4a, temp8 | 0x1); - } - - if (mips_machtype == MACH_NEC_ROCKHOPPER - || mips_machtype == MACH_NEC_ROCKHOPPERII) { - printk("lcd44780: initializing\n"); - lcd44780_init(); - lcd44780_puts("MontaVista Linux"); - } -} diff --git a/arch/mips/dec/Makefile b/arch/mips/dec/Makefile index 9eb2f9c036aa..c530208ee154 100644 --- a/arch/mips/dec/Makefile +++ b/arch/mips/dec/Makefile @@ -8,3 +8,5 @@ obj-y := ecc-berr.o int-handler.o ioasic-irq.o kn01-berr.o \ obj-$(CONFIG_PROM_CONSOLE) += promcon.o obj-$(CONFIG_TC) += tc.o obj-$(CONFIG_CPU_HAS_WB) += wbflush.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/defconfig b/arch/mips/defconfig index b3b6e58058f6..d3d81fb2765a 100644 --- a/arch/mips/defconfig +++ b/arch/mips/defconfig @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_QEMU is not set diff --git a/arch/mips/gt64120/common/Makefile b/arch/mips/gt64120/common/Makefile deleted file mode 100644 index 1ef676e22ab4..000000000000 --- a/arch/mips/gt64120/common/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for common code of gt64120-based boards. -# - -obj-y += time.o diff --git a/arch/mips/gt64120/common/time.c b/arch/mips/gt64120/common/time.c deleted file mode 100644 index c47eeb768192..000000000000 --- a/arch/mips/gt64120/common/time.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * Galileo Technology chip interrupt handler - */ -#include <linux/interrupt.h> -#include <linux/kernel.h> -#include <linux/sched.h> -#include <linux/kernel_stat.h> -#include <asm/irq_regs.h> -#include <asm/gt64120.h> - -/* - * These are interrupt handlers for the GT on-chip interrupts. They all come - * in to the MIPS on a single interrupt line, and have to be handled and ack'ed - * differently than other MIPS interrupts. - */ - -static irqreturn_t gt64120_irq(int irq, void *dev_id) -{ - unsigned int irq_src, int_high_src, irq_src_mask, int_high_src_mask; - int handled = 0; - - irq_src = GT_READ(GT_INTRCAUSE_OFS); - irq_src_mask = GT_READ(GT_INTRMASK_OFS); - int_high_src = GT_READ(GT_HINTRCAUSE_OFS); - int_high_src_mask = GT_READ(GT_HINTRMASK_OFS); - irq_src = irq_src & irq_src_mask; - int_high_src = int_high_src & int_high_src_mask; - - if (irq_src & 0x00000800) { /* Check for timer interrupt */ - handled = 1; - irq_src &= ~0x00000800; - do_timer(1); -#ifndef CONFIG_SMP - update_process_times(user_mode(get_irq_regs())); -#endif - } - - GT_WRITE(GT_INTRCAUSE_OFS, 0); - GT_WRITE(GT_HINTRCAUSE_OFS, 0); - - return IRQ_HANDLED; -} - -/* - * Initializes timer using galileo's built in timer. - */ -#ifdef CONFIG_SYSCLK_100 -#define Sys_clock (100 * 1000000) // 100 MHz -#endif -#ifdef CONFIG_SYSCLK_83 -#define Sys_clock (83.333 * 1000000) // 83.333 MHz -#endif -#ifdef CONFIG_SYSCLK_75 -#define Sys_clock (75 * 1000000) // 75 MHz -#endif - -/* - * This will ignore the standard MIPS timer interrupt handler that is passed in - * as *irq (=irq0 in ../kernel/time.c). We will do our own timer interrupt - * handling. - */ -void __init plat_timer_setup(struct irqaction *irq) -{ - static struct irqaction timer; - - /* Disable timer first */ - GT_WRITE(GT_TC_CONTROL_OFS, 0); - /* Load timer value for 100 Hz */ - GT_WRITE(GT_TC3_OFS, Sys_clock / HZ); - - /* - * Create the IRQ structure entry for the timer. Since we're too early - * in the boot process to use the "request_irq()" call, we'll hard-code - * the values to the correct interrupt line. - */ - timer.handler = gt64120_irq; - timer.flags = IRQF_SHARED | IRQF_DISABLED; - timer.name = "timer"; - timer.dev_id = NULL; - timer.next = NULL; - timer.mask = CPU_MASK_NONE; - irq_desc[GT_TIMER].action = &timer; - - enable_irq(GT_TIMER); - - /* Enable timer ints */ - GT_WRITE(GT_TC_CONTROL_OFS, 0xc0); - /* clear Cause register first */ - GT_WRITE(GT_INTRCAUSE_OFS, 0x0); - /* Unmask timer int */ - GT_WRITE(GT_INTRMASK_OFS, 0x800); - /* Clear High int register */ - GT_WRITE(GT_HINTRCAUSE_OFS, 0x0); - /* Mask All interrupts at High cause interrupt */ - GT_WRITE(GT_HINTRMASK_OFS, 0x0); -} diff --git a/arch/mips/gt64120/momenco_ocelot/Makefile b/arch/mips/gt64120/momenco_ocelot/Makefile deleted file mode 100644 index 1df5fe23c642..000000000000 --- a/arch/mips/gt64120/momenco_ocelot/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# Makefile for Momentum's Ocelot board. -# - -obj-y += irq.o ocelot-platform.o prom.o reset.o setup.o - -obj-$(CONFIG_KGDB) += dbg_io.o diff --git a/arch/mips/gt64120/momenco_ocelot/dbg_io.c b/arch/mips/gt64120/momenco_ocelot/dbg_io.c deleted file mode 100644 index 32d6fb4ee679..000000000000 --- a/arch/mips/gt64120/momenco_ocelot/dbg_io.c +++ /dev/null @@ -1,121 +0,0 @@ - -#include <asm/serial.h> /* For the serial port location and base baud */ - -/* --- CONFIG --- */ - -typedef unsigned char uint8; -typedef unsigned int uint32; - -/* --- END OF CONFIG --- */ - -#define UART16550_BAUD_2400 2400 -#define UART16550_BAUD_4800 4800 -#define UART16550_BAUD_9600 9600 -#define UART16550_BAUD_19200 19200 -#define UART16550_BAUD_38400 38400 -#define UART16550_BAUD_57600 57600 -#define UART16550_BAUD_115200 115200 - -#define UART16550_PARITY_NONE 0 -#define UART16550_PARITY_ODD 0x08 -#define UART16550_PARITY_EVEN 0x18 -#define UART16550_PARITY_MARK 0x28 -#define UART16550_PARITY_SPACE 0x38 - -#define UART16550_DATA_5BIT 0x0 -#define UART16550_DATA_6BIT 0x1 -#define UART16550_DATA_7BIT 0x2 -#define UART16550_DATA_8BIT 0x3 - -#define UART16550_STOP_1BIT 0x0 -#define UART16550_STOP_2BIT 0x4 - -/* ----------------------------------------------------- */ - -/* === CONFIG === */ - -/* [jsun] we use the second serial port for kdb */ -#define BASE OCELOT_SERIAL1_BASE -#define MAX_BAUD OCELOT_BASE_BAUD - -/* === END OF CONFIG === */ - -#define REG_OFFSET 4 - -/* register offset */ -#define OFS_RCV_BUFFER 0 -#define OFS_TRANS_HOLD 0 -#define OFS_SEND_BUFFER 0 -#define OFS_INTR_ENABLE (1*REG_OFFSET) -#define OFS_INTR_ID (2*REG_OFFSET) -#define OFS_DATA_FORMAT (3*REG_OFFSET) -#define OFS_LINE_CONTROL (3*REG_OFFSET) -#define OFS_MODEM_CONTROL (4*REG_OFFSET) -#define OFS_RS232_OUTPUT (4*REG_OFFSET) -#define OFS_LINE_STATUS (5*REG_OFFSET) -#define OFS_MODEM_STATUS (6*REG_OFFSET) -#define OFS_RS232_INPUT (6*REG_OFFSET) -#define OFS_SCRATCH_PAD (7*REG_OFFSET) - -#define OFS_DIVISOR_LSB (0*REG_OFFSET) -#define OFS_DIVISOR_MSB (1*REG_OFFSET) - - -/* memory-mapped read/write of the port */ -#define UART16550_READ(y) (*((volatile uint8*)(BASE + y))) -#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z) - -void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop) -{ - /* disable interrupts */ - UART16550_WRITE(OFS_INTR_ENABLE, 0); - - /* set up baud rate */ - { - uint32 divisor; - - /* set DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x80); - - /* set divisor */ - divisor = MAX_BAUD / baud; - UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff); - UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8); - - /* clear DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x0); - } - - /* set data format */ - UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop); -} - -static int remoteDebugInitialized = 0; - -uint8 getDebugChar(void) -{ - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(UART16550_BAUD_38400, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); - } - - while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0); - return UART16550_READ(OFS_RCV_BUFFER); -} - - -int putDebugChar(uint8 byte) -{ - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(UART16550_BAUD_38400, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); - } - - while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0); - UART16550_WRITE(OFS_SEND_BUFFER, byte); - return 1; -} diff --git a/arch/mips/gt64120/momenco_ocelot/irq.c b/arch/mips/gt64120/momenco_ocelot/irq.c deleted file mode 100644 index 2585d9dbda33..000000000000 --- a/arch/mips/gt64120/momenco_ocelot/irq.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (C) 2000 RidgeRun, Inc. - * Author: RidgeRun, Inc. - * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com - * - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * Copyright (C) 2000, 2001, 2003 Ralf Baechle (ralf@gnu.org) - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ -#include <linux/errno.h> -#include <linux/init.h> -#include <linux/kernel_stat.h> -#include <linux/module.h> -#include <linux/signal.h> -#include <linux/sched.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/ioport.h> -#include <linux/timex.h> -#include <linux/slab.h> -#include <linux/random.h> -#include <linux/bitops.h> -#include <asm/bootinfo.h> -#include <asm/io.h> -#include <asm/irq.h> -#include <asm/irq_cpu.h> -#include <asm/mipsregs.h> -#include <asm/system.h> - -asmlinkage void plat_irq_dispatch(void) -{ - unsigned int pending = read_c0_status() & read_c0_cause(); - - if (pending & STATUSF_IP2) /* int0 hardware line */ - do_IRQ(2); - else if (pending & STATUSF_IP3) /* int1 hardware line */ - do_IRQ(3); - else if (pending & STATUSF_IP4) /* int2 hardware line */ - do_IRQ(4); - else if (pending & STATUSF_IP5) /* int3 hardware line */ - do_IRQ(5); - else if (pending & STATUSF_IP6) /* int4 hardware line */ - do_IRQ(6); - else if (pending & STATUSF_IP7) /* cpu timer */ - do_IRQ(7); - else { - /* - * Now look at the extended interrupts - */ - pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16; - - if (pending & STATUSF_IP8) /* int6 hardware line */ - do_IRQ(8); - else if (pending & STATUSF_IP9) /* int7 hardware line */ - do_IRQ(9); - else if (pending & STATUSF_IP10) /* int8 hardware line */ - do_IRQ(10); - else if (pending & STATUSF_IP11) /* int9 hardware line */ - do_IRQ(11); - } -} - -void __init arch_init_irq(void) -{ - /* - * Clear all of the interrupts while we change the able around a bit. - * int-handler is not on bootstrap - */ - clear_c0_status(ST0_IM); - local_irq_disable(); - - mips_cpu_irq_init(); - rm7k_cpu_irq_init(); -} diff --git a/arch/mips/gt64120/momenco_ocelot/ocelot-platform.c b/arch/mips/gt64120/momenco_ocelot/ocelot-platform.c deleted file mode 100644 index 81d9031a5a2a..000000000000 --- a/arch/mips/gt64120/momenco_ocelot/ocelot-platform.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) - * - * A NS16552 DUART with a 20MHz crystal. - * - */ -#include <linux/module.h> -#include <linux/init.h> -#include <linux/serial_8250.h> - -#define OCELOT_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP) - -static struct plat_serial8250_port uart8250_data[] = { - { - .mapbase = 0xe0001020, - .irq = 4, - .uartclk = 20000000, - .iotype = UPIO_MEM, - .flags = OCELOT_UART_FLAGS, - .regshift = 2, - }, - { }, -}; - -static struct platform_device uart8250_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = uart8250_data, - }, -}; - -static int __init uart8250_init(void) -{ - return platform_device_register(&uart8250_device); -} - -module_init(uart8250_init); - -MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>"); -MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("8250 UART probe driver for the Momenco Ocelot"); diff --git a/arch/mips/gt64120/momenco_ocelot/ocelot_pld.h b/arch/mips/gt64120/momenco_ocelot/ocelot_pld.h deleted file mode 100644 index 11f02c402b2a..000000000000 --- a/arch/mips/gt64120/momenco_ocelot/ocelot_pld.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Ocelot Board Register Definitions - * - * (C) 2001 Red Hat, Inc. - * - * GPL'd - */ -#ifndef __MOMENCO_OCELOT_PLD_H__ -#define __MOMENCO_OCELOT_PLD_H__ - -#define OCELOT_CS0_ADDR (0xe0020000) - -#define OCELOT_REG_BOARDREV (0) -#define OCELOT_REG_PLD1_ID (1) -#define OCELOT_REG_PLD2_ID (2) -#define OCELOT_REG_RESET_STATUS (3) -#define OCELOT_REG_BOARD_STATUS (4) -#define OCELOT_REG_CPCI_ID (5) -#define OCELOT_REG_I2C_CTRL (8) -#define OCELOT_REG_EEPROM_MODE (9) -#define OCELOT_REG_INTMASK (10) -#define OCELOT_REG_INTSTATUS (11) -#define OCELOT_REG_INTSET (12) -#define OCELOT_REG_INTCLR (13) - -#define OCELOT_PLD_WRITE(x, y) writeb(x, OCELOT_CS0_ADDR + OCELOT_REG_##y) -#define OCELOT_PLD_READ(x) readb(OCELOT_CS0_ADDR + OCELOT_REG_##x) - - -#endif /* __MOMENCO_OCELOT_PLD_H__ */ diff --git a/arch/mips/gt64120/momenco_ocelot/prom.c b/arch/mips/gt64120/momenco_ocelot/prom.c deleted file mode 100644 index c71c85276c74..000000000000 --- a/arch/mips/gt64120/momenco_ocelot/prom.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include <linux/init.h> -#include <linux/mm.h> -#include <linux/sched.h> -#include <linux/bootmem.h> - -#include <asm/addrspace.h> -#include <asm/bootinfo.h> -#include <asm/pmon.h> - -struct callvectors* debug_vectors; - -extern unsigned long gt64120_base; - -const char *get_system_type(void) -{ - return "Momentum Ocelot"; -} - -/* [jsun@junsun.net] PMON passes arguments in C main() style */ -void __init prom_init(void) -{ - int argc = fw_arg0; - char **arg = (char **) fw_arg1; - char **env = (char **) fw_arg2; - struct callvectors *cv = (struct callvectors *) fw_arg3; - int i; - - /* save the PROM vectors for debugging use */ - debug_vectors = cv; - - /* arg[0] is "g", the rest is boot parameters */ - arcs_cmdline[0] = '\0'; - for (i = 1; i < argc; i++) { - if (strlen(arcs_cmdline) + strlen(arg[i] + 1) - >= sizeof(arcs_cmdline)) - break; - strcat(arcs_cmdline, arg[i]); - strcat(arcs_cmdline, " "); - } - - mips_machgroup = MACH_GROUP_MOMENCO; - mips_machtype = MACH_MOMENCO_OCELOT; - - while (*env) { - if (strncmp("gtbase", *env, 6) == 0) { - gt64120_base = simple_strtol(*env + strlen("gtbase="), - NULL, 16); - break; - } - *env++; - } - - debug_vectors->printf("Booting Linux kernel...\n"); - - /* All the boards have at least 64MiB. If there's more, we - detect and register it later */ - add_memory_region(0, 64 << 20, BOOT_MEM_RAM); -} - -void __init prom_free_prom_memory(void) -{ -} diff --git a/arch/mips/gt64120/momenco_ocelot/reset.c b/arch/mips/gt64120/momenco_ocelot/reset.c deleted file mode 100644 index 3fd499adf4cf..000000000000 --- a/arch/mips/gt64120/momenco_ocelot/reset.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * Copyright (C) 1997, 2001 Ralf Baechle - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - */ -#include <linux/sched.h> -#include <linux/mm.h> -#include <asm/io.h> -#include <asm/pgtable.h> -#include <asm/processor.h> -#include <asm/reboot.h> -#include <asm/system.h> -#include <linux/delay.h> - -void momenco_ocelot_restart(char *command) -{ - void *nvram = ioremap_nocache(0x2c807000, 0x1000); - - if (!nvram) { - printk(KERN_NOTICE "ioremap of reset register failed\n"); - return; - } - writeb(0x84, nvram + 0xff7); /* Ask the NVRAM/RTC/watchdog chip to - assert reset in 1/16 second */ - mdelay(10+(1000/16)); - iounmap(nvram); - printk(KERN_NOTICE "Watchdog reset failed\n"); -} - -void momenco_ocelot_halt(void) -{ - printk(KERN_NOTICE "\n** You can safely turn off the power\n"); - while (1) - __asm__(".set\tmips3\n\t" - "wait\n\t" - ".set\tmips0"); -} - -void momenco_ocelot_power_off(void) -{ - momenco_ocelot_halt(); -} diff --git a/arch/mips/gt64120/momenco_ocelot/setup.c b/arch/mips/gt64120/momenco_ocelot/setup.c deleted file mode 100644 index 98b6fb38096d..000000000000 --- a/arch/mips/gt64120/momenco_ocelot/setup.c +++ /dev/null @@ -1,365 +0,0 @@ -/* - * setup.c - * - * BRIEF MODULE DESCRIPTION - * Momentum Computer Ocelot (CP7000) - board dependent boot routines - * - * Copyright (C) 1996, 1997, 2001, 06 Ralf Baechle (ralf@linux-mips.org) - * Copyright (C) 2000 RidgeRun, Inc. - * Copyright (C) 2001 Red Hat, Inc. - * Copyright (C) 2002 Momentum Computer - * - * Author: RidgeRun, Inc. - * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com - * - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/mm.h> -#include <linux/swap.h> -#include <linux/ioport.h> -#include <linux/sched.h> -#include <linux/interrupt.h> -#include <linux/pci.h> -#include <linux/timex.h> -#include <linux/vmalloc.h> -#include <linux/pm.h> - -#include <asm/time.h> -#include <asm/bootinfo.h> -#include <asm/page.h> -#include <asm/io.h> -#include <asm/irq.h> -#include <asm/pci.h> -#include <asm/processor.h> -#include <asm/reboot.h> -#include <asm/traps.h> -#include <linux/bootmem.h> -#include <linux/initrd.h> -#include <asm/gt64120.h> -#include "ocelot_pld.h" - -unsigned long gt64120_base = KSEG1ADDR(GT_DEF_BASE); - -/* These functions are used for rebooting or halting the machine*/ -extern void momenco_ocelot_restart(char *command); -extern void momenco_ocelot_halt(void); -extern void momenco_ocelot_power_off(void); - -extern void momenco_ocelot_irq_setup(void); - -static char reset_reason; - -#define ENTRYLO(x) ((pte_val(pfn_pte((x) >> PAGE_SHIFT, PAGE_KERNEL_UNCACHED)) >> 6)|1) - -static void __init setup_l3cache(unsigned long size); - -/* setup code for a handoff from a version 1 PMON 2000 PROM */ -static void PMON_v1_setup(void) -{ - /* A wired TLB entry for the GT64120A and the serial port. The - GT64120A is going to be hit on every IRQ anyway - there's - absolutely no point in letting it be a random TLB entry, as - it'll just cause needless churning of the TLB. And we use - the other half for the serial port, which is just a PITA - otherwise :) - - Device Physical Virtual - GT64120 Internal Regs 0x24000000 0xe0000000 - UARTs (CS2) 0x2d000000 0xe0001000 - */ - add_wired_entry(ENTRYLO(0x24000000), ENTRYLO(0x2D000000), 0xe0000000, PM_4K); - - /* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM - in the CS[012] region. We can't use ioremap() yet. The NVRAM - is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions. - - Ocelot PLD (CS0) 0x2c000000 0xe0020000 - NVRAM 0x2c800000 0xe0030000 - */ - - add_temporary_entry(ENTRYLO(0x2C000000), ENTRYLO(0x2d000000), 0xe0020000, PM_64K); - - /* Relocate the CS3/BootCS region */ - GT_WRITE(GT_CS3BOOTLD_OFS, 0x2f000000 >> 21); - - /* Relocate CS[012] */ - GT_WRITE(GT_CS20LD_OFS, 0x2c000000 >> 21); - - /* Relocate the GT64120A itself... */ - GT_WRITE(GT_ISD_OFS, 0x24000000 >> 21); - mb(); - gt64120_base = 0xe0000000; - - /* ...and the PCI0 view of it. */ - GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000020); - GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x24000000); - GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000024); - GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x24000001); -} - -/* setup code for a handoff from a version 2 PMON 2000 PROM */ -void PMON_v2_setup() -{ - /* A wired TLB entry for the GT64120A and the serial port. The - GT64120A is going to be hit on every IRQ anyway - there's - absolutely no point in letting it be a random TLB entry, as - it'll just cause needless churning of the TLB. And we use - the other half for the serial port, which is just a PITA - otherwise :) - - Device Physical Virtual - GT64120 Internal Regs 0xf4000000 0xe0000000 - UARTs (CS2) 0xfd000000 0xe0001000 - */ - add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xfD000000), 0xe0000000, PM_4K); - - /* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM - in the CS[012] region. We can't use ioremap() yet. The NVRAM - is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions. - - Ocelot PLD (CS0) 0xfc000000 0xe0020000 - NVRAM 0xfc800000 0xe0030000 - */ - add_temporary_entry(ENTRYLO(0xfC000000), ENTRYLO(0xfd000000), 0xe0020000, PM_64K); - - gt64120_base = 0xe0000000; -} - -void __init plat_mem_setup(void) -{ - void (*l3func)(unsigned long)=KSEG1ADDR(&setup_l3cache); - unsigned int tmpword; - - _machine_restart = momenco_ocelot_restart; - _machine_halt = momenco_ocelot_halt; - pm_power_off = momenco_ocelot_power_off; - - /* - * initrd_start = (unsigned long)ocelot_initrd_start; - * initrd_end = (unsigned long)ocelot_initrd_start + (ulong)ocelot_initrd_size; - * initrd_below_start_ok = 1; - */ - - /* do handoff reconfiguration */ - if (gt64120_base == KSEG1ADDR(GT_DEF_BASE)) - PMON_v1_setup(); - else - PMON_v2_setup(); - - /* Turn off the Bit-Error LED */ - OCELOT_PLD_WRITE(0x80, INTCLR); - - /* Relocate all the PCI1 stuff, not that we use it */ - GT_WRITE(GT_PCI1IOLD_OFS, 0x30000000 >> 21); - GT_WRITE(GT_PCI1M0LD_OFS, 0x32000000 >> 21); - GT_WRITE(GT_PCI1M1LD_OFS, 0x34000000 >> 21); - - /* Relocate PCI0 I/O and Mem0 */ - GT_WRITE(GT_PCI0IOLD_OFS, 0x20000000 >> 21); - GT_WRITE(GT_PCI0M0LD_OFS, 0x22000000 >> 21); - - /* Relocate PCI0 Mem1 */ - GT_WRITE(GT_PCI0M1LD_OFS, 0x36000000 >> 21); - - /* For the initial programming, we assume 512MB configuration */ - /* Relocate the CPU's view of the RAM... */ - GT_WRITE(GT_SCS10LD_OFS, 0); - GT_WRITE(GT_SCS10HD_OFS, 0x0fe00000 >> 21); - GT_WRITE(GT_SCS32LD_OFS, 0x10000000 >> 21); - GT_WRITE(GT_SCS32HD_OFS, 0x0fe00000 >> 21); - - GT_WRITE(GT_SCS1LD_OFS, 0xff); - GT_WRITE(GT_SCS1HD_OFS, 0x00); - GT_WRITE(GT_SCS0LD_OFS, 0); - GT_WRITE(GT_SCS0HD_OFS, 0xff); - GT_WRITE(GT_SCS3LD_OFS, 0xff); - GT_WRITE(GT_SCS3HD_OFS, 0x00); - GT_WRITE(GT_SCS2LD_OFS, 0); - GT_WRITE(GT_SCS2HD_OFS, 0xff); - - /* ...and the PCI0 view of it. */ - GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000010); - GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x00000000); - GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014); - GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x10000000); - GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x0ffff000); - GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x0ffff000); - - tmpword = OCELOT_PLD_READ(BOARDREV); - if (tmpword < 26) - printk("Momenco Ocelot: Board Assembly Rev. %c\n", 'A'+tmpword); - else - printk("Momenco Ocelot: Board Assembly Revision #0x%x\n", tmpword); - - tmpword = OCELOT_PLD_READ(PLD1_ID); - printk("PLD 1 ID: %d.%d\n", tmpword>>4, tmpword&15); - tmpword = OCELOT_PLD_READ(PLD2_ID); - printk("PLD 2 ID: %d.%d\n", tmpword>>4, tmpword&15); - tmpword = OCELOT_PLD_READ(RESET_STATUS); - printk("Reset reason: 0x%x\n", tmpword); - reset_reason = tmpword; - OCELOT_PLD_WRITE(0xff, RESET_STATUS); - - tmpword = OCELOT_PLD_READ(BOARD_STATUS); - printk("Board Status register: 0x%02x\n", tmpword); - printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent"); - printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent"); - printk(" - Tulip PHY %s connected\n", (tmpword&0x10)?"is":"not"); - printk(" - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1); - printk(" - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3))); - - if (tmpword&12) - l3func((1<<(((tmpword&12) >> 2)+20))); - - switch(tmpword &3) { - case 3: - /* 512MiB */ - /* Decoders are allready set -- just add the - * appropriate region */ - add_memory_region( 0x40<<20, 0xC0<<20, BOOT_MEM_RAM); - add_memory_region(0x100<<20, 0x100<<20, BOOT_MEM_RAM); - break; - case 2: - /* 256MiB -- two banks of 128MiB */ - GT_WRITE(GT_SCS10HD_OFS, 0x07e00000 >> 21); - GT_WRITE(GT_SCS32LD_OFS, 0x08000000 >> 21); - GT_WRITE(GT_SCS32HD_OFS, 0x0fe00000 >> 21); - - GT_WRITE(GT_SCS0HD_OFS, 0x7f); - GT_WRITE(GT_SCS2LD_OFS, 0x80); - GT_WRITE(GT_SCS2HD_OFS, 0xff); - - /* reconfigure the PCI0 interface view of memory */ - GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014); - GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x08000000); - GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x0ffff000); - GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x0ffff000); - - add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM); - add_memory_region(0x80<<20, 0x80<<20, BOOT_MEM_RAM); - break; - case 1: - /* 128MiB -- 64MiB per bank */ - GT_WRITE(GT_SCS10HD_OFS, 0x03e00000 >> 21); - GT_WRITE(GT_SCS32LD_OFS, 0x04000000 >> 21); - GT_WRITE(GT_SCS32HD_OFS, 0x07e00000 >> 21); - - GT_WRITE(GT_SCS0HD_OFS, 0x3f); - GT_WRITE(GT_SCS2LD_OFS, 0x40); - GT_WRITE(GT_SCS2HD_OFS, 0x7f); - - /* reconfigure the PCI0 interface view of memory */ - GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014); - GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x04000000); - GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x03fff000); - GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x03fff000); - - /* add the appropriate region */ - add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM); - break; - case 0: - /* 64MiB */ - GT_WRITE(GT_SCS10HD_OFS, 0x01e00000 >> 21); - GT_WRITE(GT_SCS32LD_OFS, 0x02000000 >> 21); - GT_WRITE(GT_SCS32HD_OFS, 0x03e00000 >> 21); - - GT_WRITE(GT_SCS0HD_OFS, 0x1f); - GT_WRITE(GT_SCS2LD_OFS, 0x20); - GT_WRITE(GT_SCS2HD_OFS, 0x3f); - - /* reconfigure the PCI0 interface view of memory */ - GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014); - GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x04000000); - GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x01fff000); - GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x01fff000); - - break; - } - - /* Fix up the DiskOnChip mapping */ - GT_WRITE(GT_DEV_B3_OFS, 0xfef73); -} - -extern int rm7k_tcache_enabled; -/* - * This runs in KSEG1. See the verbiage in rm7k.c::probe_scache() - */ -#define Page_Invalidate_T 0x16 -static void __init setup_l3cache(unsigned long size) -{ - int register i; - unsigned long tmp; - - printk("Enabling L3 cache..."); - - /* Enable the L3 cache in the GT64120A's CPU Configuration register */ - tmp = GT_READ(GT_CPU_OFS); - GT_WRITE(GT_CPU_OFS, tmp | (1<<14)); - - /* Enable the L3 cache in the CPU */ - set_c0_config(1<<12 /* CONF_TE */); - - /* Clear the cache */ - write_c0_taglo(0); - write_c0_taghi(0); - - for (i=0; i < size; i+= 4096) { - __asm__ __volatile__ ( - ".set noreorder\n\t" - ".set mips3\n\t" - "cache %1, (%0)\n\t" - ".set mips0\n\t" - ".set reorder" - : - : "r" (KSEG0ADDR(i)), - "i" (Page_Invalidate_T)); - } - - /* Let the RM7000 MM code know that the tertiary cache is enabled */ - rm7k_tcache_enabled = 1; - - printk("Done\n"); -} - - -/* This needs to be one of the first initcalls, because no I/O port access - can work before this */ - -static int io_base_ioremap(void) -{ - void *io_remap_range = ioremap(GT_PCI_IO_BASE, GT_PCI_IO_SIZE); - - if (!io_remap_range) { - panic("Could not ioremap I/O port range"); - } - set_io_port_base(io_remap_range - GT_PCI_IO_BASE); - - return 0; -} - -module_init(io_base_ioremap); diff --git a/arch/mips/gt64120/wrppmc/Makefile b/arch/mips/gt64120/wrppmc/Makefile index e4250435ad89..bef15c90ae15 100644 --- a/arch/mips/gt64120/wrppmc/Makefile +++ b/arch/mips/gt64120/wrppmc/Makefile @@ -10,3 +10,5 @@ # obj-y += irq.o reset.o setup.o time.o pci.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/jazz/Makefile b/arch/mips/jazz/Makefile index ae4c402b5004..575a9442bc82 100644 --- a/arch/mips/jazz/Makefile +++ b/arch/mips/jazz/Makefile @@ -3,3 +3,5 @@ # obj-y := irq.o jazzdma.o jazz-platform.o reset.o setup.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/jmr3927/common/Makefile b/arch/mips/jmr3927/common/Makefile index 01e7db19bcbe..8fd4fcccf10e 100644 --- a/arch/mips/jmr3927/common/Makefile +++ b/arch/mips/jmr3927/common/Makefile @@ -3,3 +3,5 @@ # obj-y += prom.o puts.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/jmr3927/rbhma3100/Makefile b/arch/mips/jmr3927/rbhma3100/Makefile index 8d00ba460cef..d86e30dca8f3 100644 --- a/arch/mips/jmr3927/rbhma3100/Makefile +++ b/arch/mips/jmr3927/rbhma3100/Makefile @@ -4,3 +4,5 @@ obj-y += init.o irq.o setup.o obj-$(CONFIG_KGDB) += kgdb_io.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 5c8085b6d7ab..07344cb37596 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -71,3 +71,5 @@ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o CFLAGS_cpu-bugs64.o = $(shell if $(CC) $(CFLAGS) -Wa,-mdaddi -c -o /dev/null -xc /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi) obj-$(CONFIG_HAVE_STD_PC_SERIAL_PORT) += 8250-platform.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c index 3b27309d54b1..013327286c26 100644 --- a/arch/mips/kernel/asm-offsets.c +++ b/arch/mips/kernel/asm-offsets.c @@ -132,7 +132,6 @@ void output_thread_defines(void) offset("#define THREAD_ECODE ", struct task_struct, \ thread.error_code); offset("#define THREAD_TRAPNO ", struct task_struct, thread.trap_no); - offset("#define THREAD_MFLAGS ", struct task_struct, thread.mflags); offset("#define THREAD_TRAMP ", struct task_struct, \ thread.irix_trampoline); offset("#define THREAD_OLDCTX ", struct task_struct, \ diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S index c15bbc436bbd..e46782b0ebc8 100644 --- a/arch/mips/kernel/head.S +++ b/arch/mips/kernel/head.S @@ -138,7 +138,6 @@ .fill 0x400 #endif -EXPORT(stext) # used for profiling EXPORT(_stext) #ifndef CONFIG_BOOT_RAW diff --git a/arch/mips/kernel/kspd.c b/arch/mips/kernel/kspd.c index c6580018c94b..cb9a14a1ca5b 100644 --- a/arch/mips/kernel/kspd.c +++ b/arch/mips/kernel/kspd.c @@ -89,7 +89,7 @@ static int sp_stopping = 0; #define MTSP_O_EXCL 0x0800 #define MTSP_O_BINARY 0x8000 -#define SP_VPE 1 +extern int tclimit; struct apsp_table { int sp; @@ -225,8 +225,8 @@ void sp_work_handle_request(void) /* Run the syscall at the priviledge of the user who loaded the SP program */ - if (vpe_getuid(SP_VPE)) - sp_setfsuidgid( vpe_getuid(SP_VPE), vpe_getgid(SP_VPE)); + if (vpe_getuid(tclimit)) + sp_setfsuidgid(vpe_getuid(tclimit), vpe_getgid(tclimit)); switch (sc.cmd) { /* needs the flags argument translating from SDE kit to @@ -245,7 +245,7 @@ void sp_work_handle_request(void) case MTSP_SYSCALL_EXIT: list_for_each_entry(n, &kspd_notifylist, list) - n->kspd_sp_exit(SP_VPE); + n->kspd_sp_exit(tclimit); sp_stopping = 1; printk(KERN_DEBUG "KSPD got exit syscall from SP exitcode %d\n", @@ -255,7 +255,7 @@ void sp_work_handle_request(void) case MTSP_SYSCALL_OPEN: generic.arg1 = translate_open_flags(generic.arg1); - vcwd = vpe_getcwd(SP_VPE); + vcwd = vpe_getcwd(tclimit); /* change to the cwd of the process that loaded the SP program */ old_fs = get_fs(); @@ -283,7 +283,7 @@ void sp_work_handle_request(void) break; } /* switch */ - if (vpe_getuid(SP_VPE)) + if (vpe_getuid(tclimit)) sp_setfsuidgid( 0, 0); old_fs = get_fs(); @@ -364,10 +364,9 @@ static void startwork(int vpe) } INIT_WORK(&work, sp_work); - queue_work(workqueue, &work); - } else - queue_work(workqueue, &work); + } + queue_work(workqueue, &work); } static void stopwork(int vpe) @@ -389,7 +388,7 @@ static int kspd_module_init(void) notify.start = startwork; notify.stop = stopwork; - vpe_notify(SP_VPE, ¬ify); + vpe_notify(tclimit, ¬ify); return 0; } diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c index c37568d6fb55..135d9a5fe337 100644 --- a/arch/mips/kernel/linux32.c +++ b/arch/mips/kernel/linux32.c @@ -566,6 +566,13 @@ asmlinkage long sys32_fadvise64_64(int fd, int __pad, flags); } +asmlinkage long sys32_fallocate(int fd, int mode, unsigned offset_a2, + unsigned offset_a3, unsigned len_a4, unsigned len_a5) +{ + return sys_fallocate(fd, mode, merge_64(offset_a2, offset_a3), + merge_64(len_a4, len_a5)); +} + save_static_function(sys32_clone); static int noinline __used _sys32_clone(nabi_no_regargs struct pt_regs regs) diff --git a/arch/mips/kernel/machine_kexec.c b/arch/mips/kernel/machine_kexec.c index 8f42fa85ac9e..22960d67cf07 100644 --- a/arch/mips/kernel/machine_kexec.c +++ b/arch/mips/kernel/machine_kexec.c @@ -14,7 +14,7 @@ #include <asm/page.h> extern const unsigned char relocate_new_kernel[]; -extern const unsigned int relocate_new_kernel_size; +extern const size_t relocate_new_kernel_size; extern unsigned long kexec_start_address; extern unsigned long kexec_indirection_page; @@ -40,6 +40,8 @@ machine_crash_shutdown(struct pt_regs *regs) { } +typedef void (*noretfun_t)(void) __attribute__((noreturn)); + void machine_kexec(struct kimage *image) { @@ -51,7 +53,8 @@ machine_kexec(struct kimage *image) (unsigned long)page_address(image->control_code_page); kexec_start_address = image->start; - kexec_indirection_page = phys_to_virt(image->head & PAGE_MASK); + kexec_indirection_page = + (unsigned long) phys_to_virt(image->head & PAGE_MASK); memcpy((void*)reboot_code_buffer, relocate_new_kernel, relocate_new_kernel_size); @@ -67,7 +70,7 @@ machine_kexec(struct kimage *image) phys_to_virt(entry & PAGE_MASK) : ptr + 1) { if (*ptr & IND_SOURCE || *ptr & IND_INDIRECTION || *ptr & IND_DESTINATION) - *ptr = phys_to_virt(*ptr); + *ptr = (unsigned long) phys_to_virt(*ptr); } /* @@ -78,8 +81,8 @@ machine_kexec(struct kimage *image) flush_icache_range(reboot_code_buffer, reboot_code_buffer + KEXEC_CONTROL_CODE_SIZE); - printk("Will call new kernel at %08x\n", image->start); + printk("Will call new kernel at %08lx\n", image->start); printk("Bye ...\n"); flush_cache_all(); - ((void (*)(void))reboot_code_buffer)(); + ((noretfun_t) reboot_code_buffer)(); } diff --git a/arch/mips/kernel/mips-mt-fpaff.c b/arch/mips/kernel/mips-mt-fpaff.c index ede5d73d652e..892665bb12b1 100644 --- a/arch/mips/kernel/mips-mt-fpaff.c +++ b/arch/mips/kernel/mips-mt-fpaff.c @@ -50,6 +50,7 @@ asmlinkage long mipsmt_sys_sched_setaffinity(pid_t pid, unsigned int len, cpumask_t effective_mask; int retval; struct task_struct *p; + struct thread_info *ti; if (len < sizeof(new_mask)) return -EINVAL; @@ -93,16 +94,16 @@ asmlinkage long mipsmt_sys_sched_setaffinity(pid_t pid, unsigned int len, read_unlock(&tasklist_lock); /* Compute new global allowed CPU set if necessary */ - if ((p->thread.mflags & MF_FPUBOUND) - && cpus_intersects(new_mask, mt_fpu_cpumask)) { + ti = task_thread_info(p); + if (test_ti_thread_flag(ti, TIF_FPUBOUND) && + cpus_intersects(new_mask, mt_fpu_cpumask)) { cpus_and(effective_mask, new_mask, mt_fpu_cpumask); retval = set_cpus_allowed(p, effective_mask); } else { - p->thread.mflags &= ~MF_FPUBOUND; + clear_ti_thread_flag(ti, TIF_FPUBOUND); retval = set_cpus_allowed(p, new_mask); } - out_unlock: put_task_struct(p); unlock_cpu_hotplug(); diff --git a/arch/mips/kernel/mips-mt.c b/arch/mips/kernel/mips-mt.c index 1a7d89231299..7169a4db37b8 100644 --- a/arch/mips/kernel/mips-mt.c +++ b/arch/mips/kernel/mips-mt.c @@ -21,6 +21,28 @@ #include <asm/r4kcache.h> #include <asm/cacheflush.h> +int vpelimit; + +static int __init maxvpes(char *str) +{ + get_option(&str, &vpelimit); + + return 1; +} + +__setup("maxvpes=", maxvpes); + +int tclimit; + +static int __init maxtcs(char *str) +{ + get_option(&str, &tclimit); + + return 1; +} + +__setup("maxtcs=", maxtcs); + /* * Dump new MIPS MT state for the core. Does not leave TCs halted. * Takes an argument which taken to be a pre-call MVPControl value. diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index bd05f5a927ea..e6ce943099a0 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -77,7 +77,7 @@ void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp) status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|KU_MASK); #ifdef CONFIG_64BIT status &= ~ST0_FR; - status |= (current->thread.mflags & MF_32BIT_REGS) ? 0 : ST0_FR; + status |= test_thread_flag(TIF_32BIT_REGS) ? 0 : ST0_FR; #endif status |= KU_USER; regs->cp0_status = status; diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c index 893e7bccf226..bbd57b20b43e 100644 --- a/arch/mips/kernel/ptrace.c +++ b/arch/mips/kernel/ptrace.c @@ -20,11 +20,11 @@ #include <linux/mm.h> #include <linux/errno.h> #include <linux/ptrace.h> -#include <linux/audit.h> #include <linux/smp.h> #include <linux/user.h> #include <linux/security.h> -#include <linux/signal.h> +#include <linux/audit.h> +#include <linux/seccomp.h> #include <asm/byteorder.h> #include <asm/cpu.h> @@ -470,12 +470,17 @@ static inline int audit_arch(void) */ asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit) { + /* do the secure computing check first */ + if (!entryexit) + secure_computing(regs->regs[0]); + if (unlikely(current->audit_context) && entryexit) audit_syscall_exit(AUDITSC_RESULT(regs->regs[2]), regs->regs[2]); if (!(current->ptrace & PT_PTRACED)) goto out; + if (!test_thread_flag(TIF_SYSCALL_TRACE)) goto out; @@ -493,9 +498,10 @@ asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit) send_sig(current->exit_code, current, 1); current->exit_code = 0; } - out: + +out: if (unlikely(current->audit_context) && !entryexit) - audit_syscall_entry(audit_arch(), regs->regs[2], + audit_syscall_entry(audit_arch(), regs->regs[0], regs->regs[4], regs->regs[5], regs->regs[6], regs->regs[7]); } diff --git a/arch/mips/kernel/relocate_kernel.S b/arch/mips/kernel/relocate_kernel.S index a3f0d00c1334..87481f916a61 100644 --- a/arch/mips/kernel/relocate_kernel.S +++ b/arch/mips/kernel/relocate_kernel.S @@ -14,67 +14,69 @@ #include <asm/stackframe.h> #include <asm/addrspace.h> - .globl relocate_new_kernel -relocate_new_kernel: - - PTR_L s0, kexec_indirection_page - PTR_L s1, kexec_start_address +LEAF(relocate_new_kernel) + PTR_L s0, kexec_indirection_page + PTR_L s1, kexec_start_address process_entry: - PTR_L s2, (s0) - PTR_ADD s0, s0, SZREG + PTR_L s2, (s0) + PTR_ADD s0, s0, SZREG /* destination page */ - and s3, s2, 0x1 - beq s3, zero, 1f - and s4, s2, ~0x1 /* store destination addr in s4 */ - move a0, s4 - b process_entry + and s3, s2, 0x1 + beq s3, zero, 1f + and s4, s2, ~0x1 /* store destination addr in s4 */ + move a0, s4 + b process_entry 1: /* indirection page, update s0 */ - and s3, s2, 0x2 - beq s3, zero, 1f - and s0, s2, ~0x2 - b process_entry + and s3, s2, 0x2 + beq s3, zero, 1f + and s0, s2, ~0x2 + b process_entry 1: /* done page */ - and s3, s2, 0x4 - beq s3, zero, 1f - b done + and s3, s2, 0x4 + beq s3, zero, 1f + b done 1: /* source page */ - and s3, s2, 0x8 - beq s3, zero, process_entry - and s2, s2, ~0x8 - li s6, (1 << PAGE_SHIFT) / SZREG + and s3, s2, 0x8 + beq s3, zero, process_entry + and s2, s2, ~0x8 + li s6, (1 << PAGE_SHIFT) / SZREG copy_word: /* copy page word by word */ - REG_L s5, (s2) - REG_S s5, (s4) - INT_ADD s4, s4, SZREG - INT_ADD s2, s2, SZREG - INT_SUB s6, s6, 1 - beq s6, zero, process_entry - b copy_word - b process_entry + REG_L s5, (s2) + REG_S s5, (s4) + PTR_ADD s4, s4, SZREG + PTR_ADD s2, s2, SZREG + LONG_SUB s6, s6, 1 + beq s6, zero, process_entry + b copy_word + b process_entry done: /* jump to kexec_start_address */ - j s1 + j s1 + END(relocate_new_kernel) - .globl kexec_start_address kexec_start_address: - .long 0x0 + EXPORT(kexec_start_address) + PTR 0x0 + .size kexec_start_address, PTRSIZE - .globl kexec_indirection_page kexec_indirection_page: - .long 0x0 + EXPORT(kexec_indirection_page) + PTR 0 + .size kexec_indirection_page, PTRSIZE relocate_new_kernel_end: - .globl relocate_new_kernel_size relocate_new_kernel_size: - .long relocate_new_kernel_end - relocate_new_kernel + EXPORT(relocate_new_kernel_size) + PTR relocate_new_kernel_end - relocate_new_kernel + .size relocate_new_kernel_size, PTRSIZE diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c index 8cf24d716d41..aab89e97abb5 100644 --- a/arch/mips/kernel/rtlx.c +++ b/arch/mips/kernel/rtlx.c @@ -40,12 +40,11 @@ #include <asm/atomic.h> #include <asm/cpu.h> #include <asm/processor.h> +#include <asm/mips_mt.h> #include <asm/system.h> #include <asm/vpe.h> #include <asm/rtlx.h> -#define RTLX_TARG_VPE 1 - static struct rtlx_info *rtlx; static int major; static char module_name[] = "rtlx"; @@ -165,10 +164,10 @@ int rtlx_open(int index, int can_sleep) } if (rtlx == NULL) { - if( (p = vpe_get_shared(RTLX_TARG_VPE)) == NULL) { + if( (p = vpe_get_shared(tclimit)) == NULL) { if (can_sleep) { __wait_event_interruptible(channel_wqs[index].lx_queue, - (p = vpe_get_shared(RTLX_TARG_VPE)), + (p = vpe_get_shared(tclimit)), ret); if (ret) goto out_fail; @@ -472,11 +471,24 @@ static int rtlx_irq_num = MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ; static char register_chrdev_failed[] __initdata = KERN_ERR "rtlx_module_init: unable to register device\n"; -static int rtlx_module_init(void) +static int __init rtlx_module_init(void) { struct device *dev; int i, err; + if (!cpu_has_mipsmt) { + printk("VPE loader: not a MIPS MT capable processor\n"); + return -ENODEV; + } + + if (tclimit == 0) { + printk(KERN_WARNING "No TCs reserved for AP/SP, not " + "initializing RTLX.\nPass maxtcs=<n> argument as kernel " + "argument\n"); + + return -ENODEV; + } + major = register_chrdev(0, module_name, &rtlx_fops); if (major < 0) { printk(register_chrdev_failed); @@ -501,7 +513,7 @@ static int rtlx_module_init(void) /* set up notifiers */ notify.start = starting; notify.stop = stopping; - vpe_notify(RTLX_TARG_VPE, ¬ify); + vpe_notify(tclimit, ¬ify); if (cpu_has_vint) set_vi_handler(MIPS_CPU_RTLX_IRQ, rtlx_dispatch); diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S index ae985d1fcca1..82480a1717d8 100644 --- a/arch/mips/kernel/scall32-o32.S +++ b/arch/mips/kernel/scall32-o32.S @@ -662,6 +662,7 @@ einval: li v0, -EINVAL sys sys_signalfd 3 sys sys_timerfd 4 sys sys_eventfd 1 + sys sys_fallocate 6 /* 4320 */ .endm /* We pre-compute the number of _instruction_ bytes needed to diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S index 7bcd5a1a85f5..c2c10876da2e 100644 --- a/arch/mips/kernel/scall64-64.S +++ b/arch/mips/kernel/scall64-64.S @@ -477,4 +477,5 @@ sys_call_table: PTR sys_signalfd PTR sys_timerfd PTR sys_eventfd + PTR sys_fallocate .size sys_call_table,.-sys_call_table diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S index 532a2f3b42fc..53d7a977193c 100644 --- a/arch/mips/kernel/scall64-n32.S +++ b/arch/mips/kernel/scall64-n32.S @@ -403,4 +403,5 @@ EXPORT(sysn32_call_table) PTR compat_sys_signalfd /* 5280 */ PTR compat_sys_timerfd PTR sys_eventfd + PTR sys_fallocate .size sysn32_call_table,.-sysn32_call_table diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S index 6bbe0f4ed8ba..b3ed731a24c6 100644 --- a/arch/mips/kernel/scall64-o32.S +++ b/arch/mips/kernel/scall64-o32.S @@ -525,4 +525,5 @@ sys_call_table: PTR compat_sys_signalfd PTR compat_sys_timerfd PTR sys_eventfd + PTR sys_fallocate /* 4320 */ .size sys_call_table,.-sys_call_table diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c index 486b8e5f52d0..64b612a0a622 100644 --- a/arch/mips/kernel/signal32.c +++ b/arch/mips/kernel/signal32.c @@ -18,7 +18,6 @@ #include <linux/errno.h> #include <linux/wait.h> #include <linux/ptrace.h> -#include <linux/compat.h> #include <linux/suspend.h> #include <linux/compiler.h> #include <linux/uaccess.h> diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index 04bbbd8d91ab..73b0dab02668 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -194,6 +194,61 @@ void smp_call_function_interrupt(void) } } +int smp_call_function_single(int cpu, void (*func) (void *info), void *info, + int retry, int wait) +{ + struct call_data_struct data; + int me; + + /* + * Can die spectacularly if this CPU isn't yet marked online + */ + if (!cpu_online(cpu)) + return 0; + + me = get_cpu(); + BUG_ON(!cpu_online(me)); + + if (cpu == me) { + local_irq_disable(); + func(info); + local_irq_enable(); + put_cpu(); + return 0; + } + + /* Can deadlock when called with interrupts disabled */ + WARN_ON(irqs_disabled()); + + data.func = func; + data.info = info; + atomic_set(&data.started, 0); + data.wait = wait; + if (wait) + atomic_set(&data.finished, 0); + + spin_lock(&smp_call_lock); + call_data = &data; + smp_mb(); + + /* Send a message to the other CPU */ + core_send_ipi(cpu, SMP_CALL_FUNCTION); + + /* Wait for response */ + /* FIXME: lock-up detection, backtrace on lock-up */ + while (atomic_read(&data.started) != 1) + barrier(); + + if (wait) + while (atomic_read(&data.finished) != 1) + barrier(); + call_data = NULL; + spin_unlock(&smp_call_lock); + + put_cpu(); + return 0; +} + static void stop_this_cpu(void *dummy) { /* diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c index 342d873b2ecc..16aa5d37117c 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c @@ -86,25 +86,11 @@ unsigned int smtc_status = 0; /* Boot command line configuration overrides */ -static int vpelimit = 0; -static int tclimit = 0; static int ipibuffers = 0; static int nostlb = 0; static int asidmask = 0; unsigned long smtc_asid_mask = 0xff; -static int __init maxvpes(char *str) -{ - get_option(&str, &vpelimit); - return 1; -} - -static int __init maxtcs(char *str) -{ - get_option(&str, &tclimit); - return 1; -} - static int __init ipibufs(char *str) { get_option(&str, &ipibuffers); @@ -137,8 +123,6 @@ static int __init asidmask_set(char *str) return 1; } -__setup("maxvpes=", maxvpes); -__setup("maxtcs=", maxtcs); __setup("ipibufs=", ipibufs); __setup("nostlb", stlb_disable); __setup("asidmask=", asidmask_set); @@ -168,9 +152,9 @@ static int __init tintq(char *str) __setup("tintq=", tintq); -int imstuckcount[2][8]; +static int imstuckcount[2][8]; /* vpemask represents IM/IE bits of per-VPE Status registers, low-to-high */ -int vpemask[2][8] = { +static int vpemask[2][8] = { {0, 0, 1, 0, 0, 0, 0, 1}, {0, 0, 0, 0, 0, 0, 0, 1} }; @@ -540,7 +524,7 @@ void mipsmt_prepare_cpus(void) * (unsigned long)idle->thread_info the gp * */ -void smtc_boot_secondary(int cpu, struct task_struct *idle) +void __cpuinit smtc_boot_secondary(int cpu, struct task_struct *idle) { extern u32 kernelsp[NR_CPUS]; long flags; @@ -876,7 +860,7 @@ void deferred_smtc_ipi(void) * Send clock tick to all TCs except the one executing the funtion */ -void smtc_timer_broadcast(int vpe) +void smtc_timer_broadcast(void) { int cpu; int myTC = cpu_data[smp_processor_id()].tc_id; @@ -975,7 +959,12 @@ static void ipi_irq_dispatch(void) do_IRQ(cpu_ipi_irq); } -static struct irqaction irq_ipi; +static struct irqaction irq_ipi = { + .handler = ipi_interrupt, + .flags = IRQF_DISABLED, + .name = "SMTC_IPI", + .flags = IRQF_PERCPU +}; static void setup_cross_vpe_interrupts(unsigned int nvpe) { @@ -987,13 +976,8 @@ static void setup_cross_vpe_interrupts(unsigned int nvpe) set_vi_handler(MIPS_CPU_IPI_IRQ, ipi_irq_dispatch); - irq_ipi.handler = ipi_interrupt; - irq_ipi.flags = IRQF_DISABLED; - irq_ipi.name = "SMTC_IPI"; - setup_irq_smtc(cpu_ipi_irq, &irq_ipi, (0x100 << MIPS_CPU_IPI_IRQ)); - irq_desc[cpu_ipi_irq].status |= IRQ_PER_CPU; set_irq_handler(cpu_ipi_irq, handle_percpu_irq); } diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c index 541b5005957e..7c800ec3ff55 100644 --- a/arch/mips/kernel/syscall.c +++ b/arch/mips/kernel/syscall.c @@ -281,16 +281,24 @@ asmlinkage int sys_set_thread_area(unsigned long addr) asmlinkage int _sys_sysmips(int cmd, long arg1, int arg2, int arg3) { - int tmp; - - switch(cmd) { + switch (cmd) { case MIPS_ATOMIC_SET: printk(KERN_CRIT "How did I get here?\n"); return -EINVAL; case MIPS_FIXADE: - tmp = current->thread.mflags & ~3; - current->thread.mflags = tmp | (arg1 & 3); + if (arg1 & ~3) + return -EINVAL; + + if (arg1 & 1) + set_thread_flag(TIF_FIXADE); + else + clear_thread_flag(TIF_FIXADE); + if (arg1 & 2) + set_thread_flag(TIF_LOGADE); + else + clear_thread_flag(TIF_FIXADE); + return 0; case FLUSH_CACHE: diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index ce277cb34dd0..c8e291c83057 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -775,7 +775,7 @@ static void mt_ase_fp_affinity(void) cpus_and(tmask, current->thread.user_cpus_allowed, mt_fpu_cpumask); set_cpus_allowed(current, tmask); - current->thread.mflags |= MF_FPUBOUND; + set_thread_flag(TIF_FPUBOUND); } } #endif /* CONFIG_MIPS_MT_FPAFF */ diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c index 8b9c34ffae18..d34b1fb3665d 100644 --- a/arch/mips/kernel/unaligned.c +++ b/arch/mips/kernel/unaligned.c @@ -101,16 +101,14 @@ static u32 unaligned_action; #endif extern void show_registers(struct pt_regs *regs); -static inline int emulate_load_store_insn(struct pt_regs *regs, - void __user *addr, unsigned int __user *pc, - unsigned long **regptr, unsigned long *newvalue) +static void emulate_load_store_insn(struct pt_regs *regs, + void __user *addr, unsigned int __user *pc) { union mips_instruction insn; unsigned long value; unsigned int res; regs->regs[0] = 0; - *regptr=NULL; /* * This load never faults. @@ -179,8 +177,8 @@ static inline int emulate_load_store_insn(struct pt_regs *regs, : "r" (addr), "i" (-EFAULT)); if (res) goto fault; - *newvalue = value; - *regptr = ®s->regs[insn.i_format.rt]; + compute_return_epc(regs); + regs->regs[insn.i_format.rt] = value; break; case lw_op: @@ -209,8 +207,8 @@ static inline int emulate_load_store_insn(struct pt_regs *regs, : "r" (addr), "i" (-EFAULT)); if (res) goto fault; - *newvalue = value; - *regptr = ®s->regs[insn.i_format.rt]; + compute_return_epc(regs); + regs->regs[insn.i_format.rt] = value; break; case lhu_op: @@ -243,8 +241,8 @@ static inline int emulate_load_store_insn(struct pt_regs *regs, : "r" (addr), "i" (-EFAULT)); if (res) goto fault; - *newvalue = value; - *regptr = ®s->regs[insn.i_format.rt]; + compute_return_epc(regs); + regs->regs[insn.i_format.rt] = value; break; case lwu_op: @@ -283,8 +281,8 @@ static inline int emulate_load_store_insn(struct pt_regs *regs, : "r" (addr), "i" (-EFAULT)); if (res) goto fault; - *newvalue = value; - *regptr = ®s->regs[insn.i_format.rt]; + compute_return_epc(regs); + regs->regs[insn.i_format.rt] = value; break; #endif /* CONFIG_64BIT */ @@ -325,8 +323,8 @@ static inline int emulate_load_store_insn(struct pt_regs *regs, : "r" (addr), "i" (-EFAULT)); if (res) goto fault; - *newvalue = value; - *regptr = ®s->regs[insn.i_format.rt]; + compute_return_epc(regs); + regs->regs[insn.i_format.rt] = value; break; #endif /* CONFIG_64BIT */ @@ -367,6 +365,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs, : "r" (value), "r" (addr), "i" (-EFAULT)); if (res) goto fault; + compute_return_epc(regs); break; case sw_op: @@ -397,6 +396,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs, : "r" (value), "r" (addr), "i" (-EFAULT)); if (res) goto fault; + compute_return_epc(regs); break; case sd_op: @@ -435,6 +435,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs, : "r" (value), "r" (addr), "i" (-EFAULT)); if (res) goto fault; + compute_return_epc(regs); break; #endif /* CONFIG_64BIT */ @@ -473,34 +474,31 @@ static inline int emulate_load_store_insn(struct pt_regs *regs, unaligned_instructions++; #endif - return 0; + return; fault: /* Did we have an exception handler installed? */ if (fixup_exception(regs)) - return 1; + return; die_if_kernel ("Unhandled kernel unaligned access", regs); send_sig(SIGSEGV, current, 1); - return 0; + return; sigbus: die_if_kernel("Unhandled kernel unaligned access", regs); send_sig(SIGBUS, current, 1); - return 0; + return; sigill: die_if_kernel("Unhandled kernel unaligned access or invalid instruction", regs); send_sig(SIGILL, current, 1); - - return 0; } asmlinkage void do_ade(struct pt_regs *regs) { - unsigned long *regptr, newval; extern int do_dsemulret(struct pt_regs *); unsigned int __user *pc; mm_segment_t seg; @@ -524,7 +522,7 @@ asmlinkage void do_ade(struct pt_regs *regs) goto sigbus; pc = (unsigned int __user *) exception_epc(regs); - if (user_mode(regs) && (current->thread.mflags & MF_FIXADE) == 0) + if (user_mode(regs) && !test_thread_flag(TIF_FIXADE)) goto sigbus; if (unaligned_action == UNALIGNED_ACTION_SIGNAL) goto sigbus; @@ -538,16 +536,7 @@ asmlinkage void do_ade(struct pt_regs *regs) seg = get_fs(); if (!user_mode(regs)) set_fs(KERNEL_DS); - if (!emulate_load_store_insn(regs, (void __user *)regs->cp0_badvaddr, pc, - ®ptr, &newval)) { - compute_return_epc(regs); - /* - * Now that branch is evaluated, update the dest - * register if necessary - */ - if (regptr) - *regptr = newval; - } + emulate_load_store_insn(regs, (void __user *)regs->cp0_badvaddr, pc); set_fs(seg); return; diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c index a2bee10f04cf..3c09b9785f4c 100644 --- a/arch/mips/kernel/vpe.c +++ b/arch/mips/kernel/vpe.c @@ -27,7 +27,6 @@ * To load and run, simply cat a SP 'program file' to /dev/vpe1. * i.e cat spapp >/dev/vpe1. */ - #include <linux/kernel.h> #include <linux/device.h> #include <linux/module.h> @@ -54,6 +53,7 @@ #include <asm/system.h> #include <asm/vpe.h> #include <asm/kspd.h> +#include <asm/mips_mt.h> typedef void *vpe_handle; @@ -64,6 +64,10 @@ typedef void *vpe_handle; /* If this is set, the section belongs in the init part of the module */ #define INIT_OFFSET_MASK (1UL << (BITS_PER_LONG-1)) +/* + * The number of TCs and VPEs physically available on the core + */ +static int hw_tcs, hw_vpes; static char module_name[] = "vpe"; static int major; static const int minor = 1; /* fixed for now */ @@ -126,20 +130,17 @@ struct vpe { /* the list of who wants to know when something major happens */ struct list_head notify; + + unsigned int ntcs; }; struct tc { enum tc_state state; int index; - /* parent VPE */ - struct vpe *pvpe; - - /* The list of TC's with this VPE */ - struct list_head tc; - - /* The global list of tc's */ - struct list_head list; + struct vpe *pvpe; /* parent VPE */ + struct list_head tc; /* The list of TC's with this VPE */ + struct list_head list; /* The global list of tc's */ }; struct { @@ -217,18 +218,17 @@ struct vpe *alloc_vpe(int minor) /* allocate a tc. At startup only tc0 is running, all other can be halted. */ struct tc *alloc_tc(int index) { - struct tc *t; + struct tc *tc; - if ((t = kzalloc(sizeof(struct tc), GFP_KERNEL)) == NULL) { - return NULL; - } - - INIT_LIST_HEAD(&t->tc); - list_add_tail(&t->list, &vpecontrol.tc_list); + if ((tc = kzalloc(sizeof(struct tc), GFP_KERNEL)) == NULL) + goto out; - t->index = index; + INIT_LIST_HEAD(&tc->tc); + tc->index = index; + list_add_tail(&tc->list, &vpecontrol.tc_list); - return t; +out: + return tc; } /* clean up and free everything */ @@ -663,66 +663,48 @@ static void dump_elfsymbols(Elf_Shdr * sechdrs, unsigned int symindex, } #endif -static void dump_tc(struct tc *t) -{ - unsigned long val; - - settc(t->index); - printk(KERN_DEBUG "VPE loader: TC index %d targtc %ld " - "TCStatus 0x%lx halt 0x%lx\n", - t->index, read_c0_vpecontrol() & VPECONTROL_TARGTC, - read_tc_c0_tcstatus(), read_tc_c0_tchalt()); - - printk(KERN_DEBUG " tcrestart 0x%lx\n", read_tc_c0_tcrestart()); - printk(KERN_DEBUG " tcbind 0x%lx\n", read_tc_c0_tcbind()); - - val = read_c0_vpeconf0(); - printk(KERN_DEBUG " VPEConf0 0x%lx MVP %ld\n", val, - (val & VPECONF0_MVP) >> VPECONF0_MVP_SHIFT); - - printk(KERN_DEBUG " c0 status 0x%lx\n", read_vpe_c0_status()); - printk(KERN_DEBUG " c0 cause 0x%lx\n", read_vpe_c0_cause()); - - printk(KERN_DEBUG " c0 badvaddr 0x%lx\n", read_vpe_c0_badvaddr()); - printk(KERN_DEBUG " c0 epc 0x%lx\n", read_vpe_c0_epc()); -} - -static void dump_tclist(void) -{ - struct tc *t; - - list_for_each_entry(t, &vpecontrol.tc_list, list) { - dump_tc(t); - } -} - /* We are prepared so configure and start the VPE... */ static int vpe_run(struct vpe * v) { + unsigned long flags, val, dmt_flag; struct vpe_notifications *n; - unsigned long val, dmt_flag; + unsigned int vpeflags; struct tc *t; /* check we are the Master VPE */ + local_irq_save(flags); val = read_c0_vpeconf0(); if (!(val & VPECONF0_MVP)) { printk(KERN_WARNING "VPE loader: only Master VPE's are allowed to configure MT\n"); + local_irq_restore(flags); + return -1; } - /* disable MT (using dvpe) */ - dvpe(); + dmt_flag = dmt(); + vpeflags = dvpe(); if (!list_empty(&v->tc)) { if ((t = list_entry(v->tc.next, struct tc, tc)) == NULL) { - printk(KERN_WARNING "VPE loader: TC %d is already in use.\n", - t->index); + evpe(vpeflags); + emt(dmt_flag); + local_irq_restore(flags); + + printk(KERN_WARNING + "VPE loader: TC %d is already in use.\n", + t->index); return -ENOEXEC; } } else { - printk(KERN_WARNING "VPE loader: No TC's associated with VPE %d\n", + evpe(vpeflags); + emt(dmt_flag); + local_irq_restore(flags); + + printk(KERN_WARNING + "VPE loader: No TC's associated with VPE %d\n", v->minor); + return -ENOEXEC; } @@ -733,21 +715,20 @@ static int vpe_run(struct vpe * v) /* should check it is halted, and not activated */ if ((read_tc_c0_tcstatus() & TCSTATUS_A) || !(read_tc_c0_tchalt() & TCHALT_H)) { - printk(KERN_WARNING "VPE loader: TC %d is already doing something!\n", + evpe(vpeflags); + emt(dmt_flag); + local_irq_restore(flags); + + printk(KERN_WARNING "VPE loader: TC %d is already active!\n", t->index); - dump_tclist(); + return -ENOEXEC; } - /* - * Disable multi-threaded execution whilst we activate, clear the - * halt bit and bound the tc to the other VPE... - */ - dmt_flag = dmt(); - /* Write the address we want it to start running from in the TCPC register. */ write_tc_c0_tcrestart((unsigned long)v->__start); write_tc_c0_tccontext((unsigned long)0); + /* * Mark the TC as activated, not interrupt exempt and not dynamically * allocatable @@ -763,15 +744,15 @@ static int vpe_run(struct vpe * v) * here... Or set $a3 to zero and define DFLT_STACK_SIZE and * DFLT_HEAP_SIZE when you compile your program */ - mttgpr(7, physical_memsize); - + mttgpr(6, v->ntcs); + mttgpr(7, physical_memsize); /* set up VPE1 */ /* * bind the TC to VPE 1 as late as possible so we only have the final * VPE registers to set up, and so an EJTAG probe can trigger on it */ - write_tc_c0_tcbind((read_tc_c0_tcbind() & ~TCBIND_CURVPE) | v->minor); + write_tc_c0_tcbind((read_tc_c0_tcbind() & ~TCBIND_CURVPE) | 1); write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~(VPECONF0_VPA)); @@ -793,15 +774,16 @@ static int vpe_run(struct vpe * v) /* take system out of configuration state */ clear_c0_mvpcontrol(MVPCONTROL_VPC); - /* now safe to re-enable multi-threading */ - emt(dmt_flag); - - /* set it running */ +#ifdef CONFIG_SMP evpe(EVPE_ENABLE); +#else + evpe(vpeflags); +#endif + emt(dmt_flag); + local_irq_restore(flags); - list_for_each_entry(n, &v->notify, list) { - n->start(v->minor); - } + list_for_each_entry(n, &v->notify, list) + n->start(minor); return 0; } @@ -1023,23 +1005,15 @@ static int vpe_elfload(struct vpe * v) return 0; } -void __used dump_vpe(struct vpe * v) -{ - struct tc *t; - - settc(v->minor); - - printk(KERN_DEBUG "VPEControl 0x%lx\n", read_vpe_c0_vpecontrol()); - printk(KERN_DEBUG "VPEConf0 0x%lx\n", read_vpe_c0_vpeconf0()); - - list_for_each_entry(t, &vpecontrol.tc_list, list) - dump_tc(t); -} - static void cleanup_tc(struct tc *tc) { + unsigned long flags; + unsigned int mtflags, vpflags; int tmp; + local_irq_save(flags); + mtflags = dmt(); + vpflags = dvpe(); /* Put MVPE's into 'configuration state' */ set_c0_mvpcontrol(MVPCONTROL_VPC); @@ -1054,9 +1028,12 @@ static void cleanup_tc(struct tc *tc) write_tc_c0_tchalt(TCHALT_H); /* bind it to anything other than VPE1 */ - write_tc_c0_tcbind(read_tc_c0_tcbind() & ~TCBIND_CURVPE); // | TCBIND_CURVPE +// write_tc_c0_tcbind(read_tc_c0_tcbind() & ~TCBIND_CURVPE); // | TCBIND_CURVPE clear_c0_mvpcontrol(MVPCONTROL_VPC); + evpe(vpflags); + emt(mtflags); + local_irq_restore(flags); } static int getcwd(char *buff, int size) @@ -1077,36 +1054,32 @@ static int getcwd(char *buff, int size) /* checks VPE is unused and gets ready to load program */ static int vpe_open(struct inode *inode, struct file *filp) { - int minor, ret; enum vpe_state state; - struct vpe *v; struct vpe_notifications *not; + struct vpe *v; + int ret; - /* assume only 1 device at the mo. */ - if ((minor = iminor(inode)) != 1) { + if (minor != iminor(inode)) { + /* assume only 1 device at the moment. */ printk(KERN_WARNING "VPE loader: only vpe1 is supported\n"); return -ENODEV; } - if ((v = get_vpe(minor)) == NULL) { + if ((v = get_vpe(tclimit)) == NULL) { printk(KERN_WARNING "VPE loader: unable to get vpe\n"); return -ENODEV; } state = xchg(&v->state, VPE_STATE_INUSE); if (state != VPE_STATE_UNUSED) { - dvpe(); - printk(KERN_DEBUG "VPE loader: tc in use dumping regs\n"); - dump_tc(get_tc(minor)); - list_for_each_entry(not, &v->notify, list) { - not->stop(minor); + not->stop(tclimit); } release_progmem(v->load_addr); - cleanup_tc(get_tc(minor)); + cleanup_tc(get_tc(tclimit)); } /* this of-course trashes what was there before... */ @@ -1133,26 +1106,25 @@ static int vpe_open(struct inode *inode, struct file *filp) v->shared_ptr = NULL; v->__start = 0; + return 0; } static int vpe_release(struct inode *inode, struct file *filp) { - int minor, ret = 0; struct vpe *v; Elf_Ehdr *hdr; + int ret = 0; - minor = iminor(inode); - if ((v = get_vpe(minor)) == NULL) + v = get_vpe(tclimit); + if (v == NULL) return -ENODEV; - // simple case of fire and forget, so tell the VPE to run... - hdr = (Elf_Ehdr *) v->pbuffer; if (memcmp(hdr->e_ident, ELFMAG, 4) == 0) { - if (vpe_elfload(v) >= 0) + if (vpe_elfload(v) >= 0) { vpe_run(v); - else { + } else { printk(KERN_WARNING "VPE loader: ELF load failed.\n"); ret = -ENOEXEC; } @@ -1179,12 +1151,14 @@ static int vpe_release(struct inode *inode, struct file *filp) static ssize_t vpe_write(struct file *file, const char __user * buffer, size_t count, loff_t * ppos) { - int minor; size_t ret = count; struct vpe *v; - minor = iminor(file->f_path.dentry->d_inode); - if ((v = get_vpe(minor)) == NULL) + if (iminor(file->f_path.dentry->d_inode) != minor) + return -ENODEV; + + v = get_vpe(tclimit); + if (v == NULL) return -ENODEV; if (v->pbuffer == NULL) { @@ -1366,62 +1340,173 @@ static void kspd_sp_exit( int sp_id) } #endif -static struct device *vpe_dev; +static ssize_t store_kill(struct class_device *dev, const char *buf, size_t len) +{ + struct vpe *vpe = get_vpe(tclimit); + struct vpe_notifications *not; + + list_for_each_entry(not, &vpe->notify, list) { + not->stop(tclimit); + } + + release_progmem(vpe->load_addr); + cleanup_tc(get_tc(tclimit)); + vpe_stop(vpe); + vpe_free(vpe); + + return len; +} + +static ssize_t show_ntcs(struct class_device *cd, char *buf) +{ + struct vpe *vpe = get_vpe(tclimit); + + return sprintf(buf, "%d\n", vpe->ntcs); +} + +static ssize_t store_ntcs(struct class_device *dev, const char *buf, size_t len) +{ + struct vpe *vpe = get_vpe(tclimit); + unsigned long new; + char *endp; + + new = simple_strtoul(buf, &endp, 0); + if (endp == buf) + goto out_einval; + + if (new == 0 || new > (hw_tcs - tclimit)) + goto out_einval; + + vpe->ntcs = new; + + return len; + +out_einval: + return -EINVAL;; +} + +static struct class_device_attribute vpe_class_attributes[] = { + __ATTR(kill, S_IWUSR, NULL, store_kill), + __ATTR(ntcs, S_IRUGO | S_IWUSR, show_ntcs, store_ntcs), + {} +}; + +static void vpe_class_device_release(struct class_device *cd) +{ + kfree(cd); +} + +struct class vpe_class = { + .name = "vpe", + .owner = THIS_MODULE, + .release = vpe_class_device_release, + .class_dev_attrs = vpe_class_attributes, +}; + +struct class_device vpe_device; static int __init vpe_module_init(void) { + unsigned int mtflags, vpflags; + unsigned long flags, val; struct vpe *v = NULL; - struct device *dev; struct tc *t; - unsigned long val; - int i, err; + int tc, err; if (!cpu_has_mipsmt) { printk("VPE loader: not a MIPS MT capable processor\n"); return -ENODEV; } + if (vpelimit == 0) { + printk(KERN_WARNING "No VPEs reserved for AP/SP, not " + "initializing VPE loader.\nPass maxvpes=<n> argument as " + "kernel argument\n"); + + return -ENODEV; + } + + if (tclimit == 0) { + printk(KERN_WARNING "No TCs reserved for AP/SP, not " + "initializing VPE loader.\nPass maxtcs=<n> argument as " + "kernel argument\n"); + + return -ENODEV; + } + major = register_chrdev(0, module_name, &vpe_fops); if (major < 0) { printk("VPE loader: unable to register character device\n"); return major; } - dev = device_create(mt_class, NULL, MKDEV(major, minor), - "tc%d", minor); - if (IS_ERR(dev)) { - err = PTR_ERR(dev); + err = class_register(&vpe_class); + if (err) { + printk(KERN_ERR "vpe_class registration failed\n"); goto out_chrdev; } - vpe_dev = dev; - dmt(); - dvpe(); + class_device_initialize(&vpe_device); + vpe_device.class = &vpe_class, + vpe_device.parent = NULL, + strlcpy(vpe_device.class_id, "vpe1", BUS_ID_SIZE); + vpe_device.devt = MKDEV(major, minor); + err = class_device_add(&vpe_device); + if (err) { + printk(KERN_ERR "Adding vpe_device failed\n"); + goto out_class; + } + + local_irq_save(flags); + mtflags = dmt(); + vpflags = dvpe(); /* Put MVPE's into 'configuration state' */ set_c0_mvpcontrol(MVPCONTROL_VPC); /* dump_mtregs(); */ - val = read_c0_mvpconf0(); - for (i = 0; i < ((val & MVPCONF0_PTC) + 1); i++) { - t = alloc_tc(i); + hw_tcs = (val & MVPCONF0_PTC) + 1; + hw_vpes = ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1; + + for (tc = tclimit; tc < hw_tcs; tc++) { + /* + * Must re-enable multithreading temporarily or in case we + * reschedule send IPIs or similar we might hang. + */ + clear_c0_mvpcontrol(MVPCONTROL_VPC); + evpe(vpflags); + emt(mtflags); + local_irq_restore(flags); + t = alloc_tc(tc); + if (!t) { + err = -ENOMEM; + goto out; + } + + local_irq_save(flags); + mtflags = dmt(); + vpflags = dvpe(); + set_c0_mvpcontrol(MVPCONTROL_VPC); /* VPE's */ - if (i < ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1) { - settc(i); + if (tc < hw_tcs) { + settc(tc); - if ((v = alloc_vpe(i)) == NULL) { + if ((v = alloc_vpe(tc)) == NULL) { printk(KERN_WARNING "VPE: unable to allocate VPE\n"); - return -ENODEV; + + goto out_reenable; } + v->ntcs = hw_tcs - tclimit; + /* add the tc to the list of this vpe's tc's. */ list_add(&t->tc, &v->tc); /* deactivate all but vpe0 */ - if (i != 0) { + if (tc >= tclimit) { unsigned long tmp = read_vpe_c0_vpeconf0(); tmp &= ~VPECONF0_VPA; @@ -1434,7 +1519,7 @@ static int __init vpe_module_init(void) /* disable multi-threading with TC's */ write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE); - if (i != 0) { + if (tc >= vpelimit) { /* * Set config to be the same as vpe0, * particularly kseg0 coherency alg @@ -1446,10 +1531,10 @@ static int __init vpe_module_init(void) /* TC's */ t->pvpe = v; /* set the parent vpe */ - if (i != 0) { + if (tc >= tclimit) { unsigned long tmp; - settc(i); + settc(tc); /* Any TC that is bound to VPE0 gets left as is - in case we are running SMTC on VPE0. A TC that is bound to any @@ -1479,17 +1564,25 @@ static int __init vpe_module_init(void) } } +out_reenable: /* release config state */ clear_c0_mvpcontrol(MVPCONTROL_VPC); + evpe(vpflags); + emt(mtflags); + local_irq_restore(flags); + #ifdef CONFIG_MIPS_APSP_KSPD kspd_events.kspd_sp_exit = kspd_sp_exit; #endif return 0; +out_class: + class_unregister(&vpe_class); out_chrdev: unregister_chrdev(major, module_name); +out: return err; } @@ -1503,7 +1596,7 @@ static void __exit vpe_module_exit(void) } } - device_destroy(mt_class, MKDEV(major, minor)); + class_device_del(&vpe_device); unregister_chrdev(major, module_name); } diff --git a/arch/mips/lemote/lm2e/Makefile b/arch/mips/lemote/lm2e/Makefile index fb1b48c48cb3..dcaf6f4c3a37 100644 --- a/arch/mips/lemote/lm2e/Makefile +++ b/arch/mips/lemote/lm2e/Makefile @@ -3,5 +3,6 @@ # obj-y += setup.o prom.o reset.o irq.o pci.o bonito-irq.o dbg_io.o mem.o -EXTRA_AFLAGS := $(CFLAGS) +EXTRA_AFLAGS := $(CFLAGS) +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/lemote/lm2e/irq.c b/arch/mips/lemote/lm2e/irq.c index 05693bceaeaf..3e0b7beb1009 100644 --- a/arch/mips/lemote/lm2e/irq.c +++ b/arch/mips/lemote/lm2e/irq.c @@ -25,7 +25,6 @@ */ #include <linux/delay.h> #include <linux/io.h> -#include <linux/irq.h> #include <linux/init.h> #include <linux/interrupt.h> #include <linux/irq.h> diff --git a/arch/mips/lemote/lm2e/prom.c b/arch/mips/lemote/lm2e/prom.c index 67312d7acf2a..3efb1cf111f2 100644 --- a/arch/mips/lemote/lm2e/prom.c +++ b/arch/mips/lemote/lm2e/prom.c @@ -15,15 +15,11 @@ * option) any later version. */ #include <linux/init.h> -#include <linux/mm.h> -#include <linux/sched.h> #include <linux/bootmem.h> - -#include <asm/addrspace.h> #include <asm/bootinfo.h> extern unsigned long bus_clock; -extern unsigned long cpu_clock; +extern unsigned long cpu_clock_freq; extern unsigned int memsize, highmemsize; extern int putDebugChar(unsigned char byte); @@ -81,7 +77,7 @@ do { \ l = (long)*env; while (l != 0) { parse_even_earlier(bus_clock, "busclock", l); - parse_even_earlier(cpu_clock, "cpuclock", l); + parse_even_earlier(cpu_clock_freq, "cpuclock", l); parse_even_earlier(memsize, "memsize", l); parse_even_earlier(highmemsize, "highmemsize", l); env++; @@ -91,7 +87,7 @@ do { \ memsize = 256; pr_info("busclock=%ld, cpuclock=%ld,memsize=%d,highmemsize=%d\n", - bus_clock, cpu_clock, memsize, highmemsize); + bus_clock, cpu_clock_freq, memsize, highmemsize); } void __init prom_free_prom_memory(void) diff --git a/arch/mips/lemote/lm2e/setup.c b/arch/mips/lemote/lm2e/setup.c index 0e4d1fa572b5..f34350a4f271 100644 --- a/arch/mips/lemote/lm2e/setup.c +++ b/arch/mips/lemote/lm2e/setup.c @@ -28,17 +28,7 @@ */ #include <linux/bootmem.h> #include <linux/init.h> -#include <linux/io.h> -#include <linux/ioport.h> -#include <linux/interrupt.h> #include <linux/irq.h> -#include <linux/kernel.h> -#include <linux/mc146818rtc.h> -#include <linux/mm.h> -#include <linux/module.h> -#include <linux/pci.h> -#include <linux/tty.h> -#include <linux/types.h> #include <asm/bootinfo.h> #include <asm/mc146818-time.h> @@ -58,7 +48,7 @@ extern void mips_reboot_setup(void); #define PTR_PAD(p) (p) #endif -unsigned long cpu_clock; +unsigned long cpu_clock_freq; unsigned long bus_clock; unsigned int memsize; unsigned int highmemsize = 0; @@ -71,7 +61,7 @@ void __init plat_timer_setup(struct irqaction *irq) static void __init loongson2e_time_init(void) { /* setup mips r4k timer */ - mips_hpt_frequency = cpu_clock / 2; + mips_hpt_frequency = cpu_clock_freq / 2; } static unsigned long __init mips_rtc_get_time(void) diff --git a/arch/mips/math-emu/Makefile b/arch/mips/math-emu/Makefile index 121a848a3594..d547efdeedc2 100644 --- a/arch/mips/math-emu/Makefile +++ b/arch/mips/math-emu/Makefile @@ -9,3 +9,5 @@ obj-y := cp1emu.o ieee754m.o ieee754d.o ieee754dp.o ieee754sp.o ieee754.o \ sp_div.o sp_mul.o sp_sub.o sp_add.o sp_fdp.o sp_cmp.o sp_logb.o \ sp_scalb.o sp_simple.o sp_tint.o sp_fint.o sp_tlong.o sp_flong.o \ dp_sqrt.o sp_sqrt.o kernel_linkage.o dsemul.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/mips-boards/atlas/Makefile b/arch/mips/mips-boards/atlas/Makefile index d8dab75906bf..f71c2dd1041a 100644 --- a/arch/mips/mips-boards/atlas/Makefile +++ b/arch/mips/mips-boards/atlas/Makefile @@ -18,3 +18,5 @@ obj-y := atlas_int.o atlas_setup.o obj-$(CONFIG_KGDB) += atlas_gdb.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/mips-boards/atlas/atlas_int.c b/arch/mips/mips-boards/atlas/atlas_int.c index 6c8f0255e85d..3c692abc2553 100644 --- a/arch/mips/mips-boards/atlas/atlas_int.c +++ b/arch/mips/mips-boards/atlas/atlas_int.c @@ -245,6 +245,7 @@ void __init arch_init_irq(void) case MIPS_REVISION_CORID_CORE_MSC: case MIPS_REVISION_CORID_CORE_FPGA2: case MIPS_REVISION_CORID_CORE_FPGA3: + case MIPS_REVISION_CORID_CORE_FPGA4: case MIPS_REVISION_CORID_CORE_24K: case MIPS_REVISION_CORID_CORE_EMUL_MSC: if (cpu_has_veic) diff --git a/arch/mips/mips-boards/generic/Makefile b/arch/mips/mips-boards/generic/Makefile index aade36d78787..b31d8dfed1be 100644 --- a/arch/mips/mips-boards/generic/Makefile +++ b/arch/mips/mips-boards/generic/Makefile @@ -24,3 +24,5 @@ obj-y := reset.o display.o init.o memory.o \ obj-$(CONFIG_EARLY_PRINTK) += console.o obj-$(CONFIG_PCI) += pci.o obj-$(CONFIG_KGDB) += gdb_hook.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/mips-boards/generic/init.c b/arch/mips/mips-boards/generic/init.c index 4eabc1eadd23..e2c7147fedf7 100644 --- a/arch/mips/mips-boards/generic/init.c +++ b/arch/mips/mips-boards/generic/init.c @@ -294,6 +294,7 @@ void __init prom_init(void) case MIPS_REVISION_CORID_CORE_MSC: case MIPS_REVISION_CORID_CORE_FPGA2: case MIPS_REVISION_CORID_CORE_FPGA3: + case MIPS_REVISION_CORID_CORE_FPGA4: case MIPS_REVISION_CORID_CORE_24K: case MIPS_REVISION_CORID_CORE_EMUL_MSC: mips_revision_sconid = MIPS_REVISION_SCON_SOCIT; diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c index c45d556aa96b..d7bff9ca5356 100644 --- a/arch/mips/mips-boards/generic/time.c +++ b/arch/mips/mips-boards/generic/time.c @@ -55,7 +55,7 @@ unsigned long cpu_khz; static int mips_cpu_timer_irq; extern int cp0_perfcount_irq; -extern void smtc_timer_broadcast(int); +extern void smtc_timer_broadcast(void); static void mips_timer_dispatch(void) { @@ -131,7 +131,7 @@ irqreturn_t mips_timer_interrupt(int irq, void *dev_id) (mips_hpt_frequency/HZ)); local_timer_interrupt(irq, dev_id); } - smtc_timer_broadcast(cpu_data[cpu].vpe_id); + smtc_timer_broadcast(); } #else /* CONFIG_MIPS_MT_SMTC */ int r2 = cpu_has_mips_r2; diff --git a/arch/mips/mips-boards/malta/Makefile b/arch/mips/mips-boards/malta/Makefile index a242b0fc377d..931ca4600a63 100644 --- a/arch/mips/mips-boards/malta/Makefile +++ b/arch/mips/mips-boards/malta/Makefile @@ -23,3 +23,5 @@ obj-y := malta_int.o malta_platform.o malta_setup.o obj-$(CONFIG_MTD) += malta_mtd.o obj-$(CONFIG_MIPS_MT_SMTC) += malta_smtc.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c index c78d48349600..97aeb8c4e601 100644 --- a/arch/mips/mips-boards/malta/malta_int.c +++ b/arch/mips/mips-boards/malta/malta_int.c @@ -330,6 +330,18 @@ void __init arch_init_irq(void) (0x100 << MIPSCPU_INT_I8259A)); setup_irq_smtc (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI)); + /* + * Temporary hack to ensure that the subsidiary device + * interrupts coing in via the i8259A, but associated + * with low IRQ numbers, will restore the Status.IM + * value associated with the i8259A. + */ + { + int i; + + for (i = 0; i < 16; i++) + irq_hwmask[i] = (0x100 << MIPSCPU_INT_I8259A); + } #else /* Not SMTC */ setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); diff --git a/arch/mips/mips-boards/malta/malta_smtc.c b/arch/mips/mips-boards/malta/malta_smtc.c index d1c80f631100..0fb4c269901c 100644 --- a/arch/mips/mips-boards/malta/malta_smtc.c +++ b/arch/mips/mips-boards/malta/malta_smtc.c @@ -58,7 +58,7 @@ void prom_init_secondary(void) * but it may be multithreaded. */ -void plat_smp_setup(void) +void __cpuinit plat_smp_setup(void) { if (read_c0_config3() & (1<<2)) mipsmt_build_cpu_map(0); diff --git a/arch/mips/mips-boards/sead/Makefile b/arch/mips/mips-boards/sead/Makefile index 224bb848f16b..3682fe217bd5 100644 --- a/arch/mips/mips-boards/sead/Makefile +++ b/arch/mips/mips-boards/sead/Makefile @@ -24,3 +24,5 @@ # obj-y := sead_int.o sead_setup.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/mipssim/Makefile b/arch/mips/mipssim/Makefile index dc0bfda11427..75568b584df4 100644 --- a/arch/mips/mipssim/Makefile +++ b/arch/mips/mipssim/Makefile @@ -22,3 +22,5 @@ obj-y := sim_platform.o sim_setup.o sim_mem.o sim_time.o sim_int.o \ obj-$(CONFIG_EARLY_PRINTK) += sim_console.o obj-$(CONFIG_SMP) += sim_smp.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/mipssim/sim_setup.c b/arch/mips/mipssim/sim_setup.c index 17819b594105..d012719c4d24 100644 --- a/arch/mips/mipssim/sim_setup.c +++ b/arch/mips/mipssim/sim_setup.c @@ -22,7 +22,6 @@ #include <linux/io.h> #include <linux/irq.h> #include <linux/ioport.h> -#include <linux/serial.h> #include <linux/tty.h> #include <linux/serial.h> #include <linux/serial_core.h> diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile index 19a0e544c4e9..43e4810dcaa8 100644 --- a/arch/mips/mm/Makefile +++ b/arch/mips/mm/Makefile @@ -32,3 +32,5 @@ obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o obj-$(CONFIG_RM7000_CPU_SCACHE) += sc-rm7k.o obj-$(CONFIG_MIPS_CPU_SCACHE) += sc-mips.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index be96231dccb6..bad571971bf6 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -23,6 +23,7 @@ #include <asm/page.h> #include <asm/pgtable.h> #include <asm/r4kcache.h> +#include <asm/sections.h> #include <asm/system.h> #include <asm/mmu_context.h> #include <asm/war.h> @@ -1010,7 +1011,6 @@ static void __init probe_pcache(void) */ static int __init probe_scache(void) { - extern unsigned long stext; unsigned long flags, addr, begin, end, pow2; unsigned int config = read_c0_config(); struct cpuinfo_mips *c = ¤t_cpu_data; @@ -1019,7 +1019,7 @@ static int __init probe_scache(void) if (config & CONF_SC) return 0; - begin = (unsigned long) &stext; + begin = (unsigned long) &_stext; begin &= ~((4 * 1024 * 1024) - 1); end = begin + (4 * 1024 * 1024); diff --git a/arch/mips/oprofile/op_model_rm9000.c b/arch/mips/oprofile/op_model_rm9000.c index 7dc9bf6f1321..d29040a56aea 100644 --- a/arch/mips/oprofile/op_model_rm9000.c +++ b/arch/mips/oprofile/op_model_rm9000.c @@ -83,6 +83,7 @@ static void rm9000_cpu_stop(void *args) static irqreturn_t rm9000_perfcount_handler(int irq, void * dev_id) { unsigned int control = read_c0_perfcontrol(); + struct pt_regs *regs = get_irq_regs(); uint32_t counter1, counter2; uint64_t counters; diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index c58bd3d036f4..4ee6800e67e6 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -19,7 +19,6 @@ obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o # These are still pretty much in the old state, watch, go blind. # obj-$(CONFIG_BASLER_EXCITE) += ops-titan.o pci-excite.o fixup-excite.o -obj-$(CONFIG_DDB5477) += fixup-ddb5477.o pci-ddb5477.o ops-ddb5477.o obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o @@ -27,7 +26,6 @@ obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o obj-$(CONFIG_LEMOTE_FULONG) += fixup-lm2e.o ops-bonito64.o obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o -obj-$(CONFIG_MOMENCO_OCELOT) += fixup-ocelot.o pci-ocelot.o obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o obj-$(CONFIG_PMC_MSP7120_FPGA) += fixup-pmcmsp.o ops-pmcmsp.o diff --git a/arch/mips/pci/fixup-ddb5477.c b/arch/mips/pci/fixup-ddb5477.c deleted file mode 100644 index 2f1444e60654..000000000000 --- a/arch/mips/pci/fixup-ddb5477.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * Board specific pci fixups. - * - * Copyright 2001, 2002, 2003 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include <linux/types.h> -#include <linux/pci.h> -#include <linux/kernel.h> -#include <linux/init.h> - -static void ddb5477_fixup(struct pci_dev *dev) -{ - u8 old; - - printk(KERN_NOTICE "Enabling ALI M1533/35 PS2 keyboard/mouse.\n"); - pci_read_config_byte(dev, 0x41, &old); - pci_write_config_byte(dev, 0x41, old | 0xd0); -} - -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, - ddb5477_fixup); -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1535, - ddb5477_fixup); - -/* - * Fixup baseboard AMD chip so that tx does not underflow. - * bcr_18 |= 0x0800 - * This sets NOUFLO bit which makes tx not start until whole pkt - * is fetched to the chip. - */ -#define PCNET32_WIO_RDP 0x10 -#define PCNET32_WIO_RAP 0x12 -#define PCNET32_WIO_RESET 0x14 -#define PCNET32_WIO_BDP 0x16 - -static void ddb5477_amd_lance_fixup(struct pci_dev *dev) -{ - unsigned long ioaddr; - u16 temp; - - ioaddr = pci_resource_start(dev, 0); - - inw(ioaddr + PCNET32_WIO_RESET); /* reset chip */ - - /* bcr_18 |= 0x0800 */ - outw(18, ioaddr + PCNET32_WIO_RAP); - temp = inw(ioaddr + PCNET32_WIO_BDP); - temp |= 0x0800; - outw(18, ioaddr + PCNET32_WIO_RAP); - outw(temp, ioaddr + PCNET32_WIO_BDP); -} - -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE, - ddb5477_amd_lance_fixup); diff --git a/arch/mips/pci/fixup-ocelot.c b/arch/mips/pci/fixup-ocelot.c deleted file mode 100644 index 99629bd047ce..000000000000 --- a/arch/mips/pci/fixup-ocelot.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * arch/mips/gt64120/momenco_ocelot/pci.c - * Board-specific PCI routines for gt64120 controller. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include <linux/types.h> -#include <linux/pci.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <asm/pci.h> - - -void __devinit pcibios_fixup_bus(struct pci_bus *bus) -{ - struct pci_bus *current_bus = bus; - struct pci_dev *devices; - struct list_head *devices_link; - u16 cmd; - - list_for_each(devices_link, &(current_bus->devices)) { - - devices = pci_dev_b(devices_link); - if (devices == NULL) - continue; - - if (PCI_SLOT(devices->devfn) == 1) { - /* - * Slot 1 is primary ether port, i82559 - * we double-check against that assumption - */ - if ((devices->vendor != 0x8086) || - (devices->device != 0x1209)) { - panic("pcibios_fixup_bus: found " - "unexpected PCI device in slot 1."); - } - devices->irq = 2; /* irq_nr is 2 for INT0 */ - } else if (PCI_SLOT(devices->devfn) == 2) { - /* - * Slot 2 is secondary ether port, i21143 - * we double-check against that assumption - */ - if ((devices->vendor != 0x1011) || - (devices->device != 0x19)) { - panic("galileo_pcibios_fixup_bus: " - "found unexpected PCI device in slot 2."); - } - devices->irq = 3; /* irq_nr is 3 for INT1 */ - } else if (PCI_SLOT(devices->devfn) == 4) { - /* PMC Slot 1 */ - devices->irq = 8; /* irq_nr is 8 for INT6 */ - } else if (PCI_SLOT(devices->devfn) == 5) { - /* PMC Slot 1 */ - devices->irq = 9; /* irq_nr is 9 for INT7 */ - } else { - /* We don't have assign interrupts for other devices. */ - devices->irq = 0xff; - } - - /* Assign an interrupt number for the device */ - bus->ops->write_byte(devices, PCI_INTERRUPT_LINE, - devices->irq); - - /* enable master */ - bus->ops->read_word(devices, PCI_COMMAND, &cmd); - cmd |= PCI_COMMAND_MASTER; - bus->ops->write_word(devices, PCI_COMMAND, cmd); - } -} diff --git a/arch/mips/pci/fixup-rbtx4927.c b/arch/mips/pci/fixup-rbtx4927.c index 3cdbecb8e714..7450c335b387 100644 --- a/arch/mips/pci/fixup-rbtx4927.c +++ b/arch/mips/pci/fixup-rbtx4927.c @@ -79,7 +79,7 @@ static unsigned char backplane_pci_irq[4][4] = { TX4927_IRQ_IOC_PCIC} }; -int pci_get_irq(struct pci_dev *dev, int pin) +static int pci_get_irq(const struct pci_dev *dev, int pin) { unsigned char irq = pin; diff --git a/arch/mips/pci/fixup-tx4938.c b/arch/mips/pci/fixup-tx4938.c index 2485f47dfe6f..f2ba06ee0c10 100644 --- a/arch/mips/pci/fixup-tx4938.c +++ b/arch/mips/pci/fixup-tx4938.c @@ -18,7 +18,7 @@ extern struct pci_controller tx4938_pci_controller[]; -int pci_get_irq(struct pci_dev *dev, int pin) +static int pci_get_irq(const struct pci_dev *dev, int pin) { int irq = pin; u8 slot = PCI_SLOT(dev->devfn); diff --git a/arch/mips/pci/ops-ddb5477.c b/arch/mips/pci/ops-ddb5477.c deleted file mode 100644 index 8e57d4c5d90f..000000000000 --- a/arch/mips/pci/ops-ddb5477.c +++ /dev/null @@ -1,278 +0,0 @@ -/*********************************************************************** - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * arch/mips/ddb5xxx/ddb5477/pci_ops.c - * Define the pci_ops for DB5477. - * - * Much of the code is derived from the original DDB5074 port by - * Geert Uytterhoeven <geert@sonycom.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - *********************************************************************** - */ - -/* - * DDB5477 has two PCI channels, external PCI and IOPIC (internal) - * Therefore we provide two sets of pci_ops. - */ -#include <linux/pci.h> -#include <linux/kernel.h> -#include <linux/types.h> - -#include <asm/addrspace.h> -#include <asm/debug.h> - -#include <asm/ddb5xxx/ddb5xxx.h> - -/* - * config_swap structure records what set of pdar/pmr are used - * to access pci config space. It also provides a place hold the - * original values for future restoring. - */ -struct pci_config_swap { - u32 pdar; - u32 pmr; - u32 config_base; - u32 config_size; - u32 pdar_backup; - u32 pmr_backup; -}; - -/* - * On DDB5477, we have two sets of swap registers, for ext PCI and IOPCI. - */ -struct pci_config_swap ext_pci_swap = { - DDB_PCIW0, - DDB_PCIINIT00, - DDB_PCI0_CONFIG_BASE, - DDB_PCI0_CONFIG_SIZE -}; -struct pci_config_swap io_pci_swap = { - DDB_IOPCIW0, - DDB_PCIINIT01, - DDB_PCI1_CONFIG_BASE, - DDB_PCI1_CONFIG_SIZE -}; - - -/* - * access config space - */ -static inline u32 ddb_access_config_base(struct pci_config_swap *swap, u32 bus, /* 0 means top level bus */ - u32 slot_num) -{ - u32 pci_addr = 0; - u32 pciinit_offset = 0; - u32 virt_addr; - u32 option; - - /* minimum pdar (window) size is 2MB */ - db_assert(swap->config_size >= (2 << 20)); - - db_assert(slot_num < (1 << 5)); - db_assert(bus < (1 << 8)); - - /* backup registers */ - swap->pdar_backup = ddb_in32(swap->pdar); - swap->pmr_backup = ddb_in32(swap->pmr); - - /* set the pdar (pci window) register */ - ddb_set_pdar(swap->pdar, swap->config_base, swap->config_size, 32, /* 32 bit wide */ - 0, /* not on local memory bus */ - 0); /* not visible from PCI bus (N/A) */ - - /* - * calcuate the absolute pci config addr; - * according to the spec, we start scanning from adr:11 (0x800) - */ - if (bus == 0) { - /* type 0 config */ - pci_addr = 0x800 << slot_num; - } else { - /* type 1 config */ - pci_addr = (bus << 16) | (slot_num << 11); - } - - /* - * if pci_addr is less than pci config window size, we set - * pciinit_offset to 0 and adjust the virt_address. - * Otherwise we will try to adjust pciinit_offset. - */ - if (pci_addr < swap->config_size) { - virt_addr = KSEG1ADDR(swap->config_base + pci_addr); - pciinit_offset = 0; - } else { - db_assert((pci_addr & (swap->config_size - 1)) == 0); - virt_addr = KSEG1ADDR(swap->config_base); - pciinit_offset = pci_addr; - } - - /* set the pmr register */ - option = DDB_PCI_ACCESS_32; - if (bus != 0) - option |= DDB_PCI_CFGTYPE1; - ddb_set_pmr(swap->pmr, DDB_PCICMD_CFG, pciinit_offset, option); - - return virt_addr; -} - -static inline void ddb_close_config_base(struct pci_config_swap *swap) -{ - ddb_out32(swap->pdar, swap->pdar_backup); - ddb_out32(swap->pmr, swap->pmr_backup); -} - -static int read_config_dword(struct pci_config_swap *swap, - struct pci_bus *bus, u32 devfn, u32 where, - u32 * val) -{ - u32 bus_num, slot_num, func_num; - u32 base; - - db_assert((where & 3) == 0); - db_assert(where < (1 << 8)); - - /* check if the bus is top-level */ - if (bus->parent != NULL) { - bus_num = bus->number; - db_assert(bus_num != 0); - } else { - bus_num = 0; - } - - slot_num = PCI_SLOT(devfn); - func_num = PCI_FUNC(devfn); - base = ddb_access_config_base(swap, bus_num, slot_num); - *val = *(volatile u32 *) (base + (func_num << 8) + where); - ddb_close_config_base(swap); - return PCIBIOS_SUCCESSFUL; -} - -static int read_config_word(struct pci_config_swap *swap, - struct pci_bus *bus, u32 devfn, u32 where, - u16 * val) -{ - int status; - u32 result; - - db_assert((where & 1) == 0); - - status = read_config_dword(swap, bus, devfn, where & ~3, &result); - if (where & 2) - result >>= 16; - *val = result & 0xffff; - return status; -} - -static int read_config_byte(struct pci_config_swap *swap, - struct pci_bus *bus, u32 devfn, u32 where, - u8 * val) -{ - int status; - u32 result; - - status = read_config_dword(swap, bus, devfn, where & ~3, &result); - if (where & 1) - result >>= 8; - if (where & 2) - result >>= 16; - *val = result & 0xff; - - return status; -} - -static int write_config_dword(struct pci_config_swap *swap, - struct pci_bus *bus, u32 devfn, u32 where, - u32 val) -{ - u32 bus_num, slot_num, func_num; - u32 base; - - db_assert((where & 3) == 0); - db_assert(where < (1 << 8)); - - /* check if the bus is top-level */ - if (bus->parent != NULL) { - bus_num = bus->number; - db_assert(bus_num != 0); - } else { - bus_num = 0; - } - - slot_num = PCI_SLOT(devfn); - func_num = PCI_FUNC(devfn); - base = ddb_access_config_base(swap, bus_num, slot_num); - *(volatile u32 *) (base + (func_num << 8) + where) = val; - ddb_close_config_base(swap); - return PCIBIOS_SUCCESSFUL; -} - -static int write_config_word(struct pci_config_swap *swap, - struct pci_bus *bus, u32 devfn, u32 where, u16 val) -{ - int status, shift = 0; - u32 result; - - db_assert((where & 1) == 0); - - status = read_config_dword(swap, bus, devfn, where & ~3, &result); - if (status != PCIBIOS_SUCCESSFUL) - return status; - - if (where & 2) - shift += 16; - result &= ~(0xffff << shift); - result |= val << shift; - return write_config_dword(swap, bus, devfn, where & ~3, result); -} - -static int write_config_byte(struct pci_config_swap *swap, - struct pci_bus *bus, u32 devfn, u32 where, u8 val) -{ - int status, shift = 0; - u32 result; - - status = read_config_dword(swap, bus, devfn, where & ~3, &result); - if (status != PCIBIOS_SUCCESSFUL) - return status; - - if (where & 2) - shift += 16; - if (where & 1) - shift += 8; - result &= ~(0xff << shift); - result |= val << shift; - return write_config_dword(swap, bus, devfn, where & ~3, result); -} - -#define MAKE_PCI_OPS(prefix, rw, pciswap, star) \ -static int prefix##_##rw##_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 star val) \ -{ \ - if (size == 1) \ - return rw##_config_byte(pciswap, bus, devfn, where, (u8 star)val); \ - else if (size == 2) \ - return rw##_config_word(pciswap, bus, devfn, where, (u16 star)val); \ - /* Size must be 4 */ \ - return rw##_config_dword(pciswap, bus, devfn, where, val); \ -} - -MAKE_PCI_OPS(extpci, read, &ext_pci_swap, *) -MAKE_PCI_OPS(extpci, write, &ext_pci_swap,) - -MAKE_PCI_OPS(iopci, read, &io_pci_swap, *) -MAKE_PCI_OPS(iopci, write, &io_pci_swap,) - -struct pci_ops ddb5477_ext_pci_ops = { - .read = extpci_read_config, - .write = extpci_write_config -}; - - -struct pci_ops ddb5477_io_pci_ops = { - .read = iopci_read_config, - .write = iopci_write_config -}; diff --git a/arch/mips/pci/ops-emma2rh.c b/arch/mips/pci/ops-emma2rh.c index 38f181625e10..d31bfc6d4150 100644 --- a/arch/mips/pci/ops-emma2rh.c +++ b/arch/mips/pci/ops-emma2rh.c @@ -45,7 +45,7 @@ static int check_args(struct pci_bus *bus, u32 devfn, u32 * bus_num) /* check if the bus is top-level */ if (bus->parent != NULL) { *bus_num = bus->number; - db_assert(bus_num != 0); + db_assert(bus_num != NULL); } else *bus_num = 0; diff --git a/arch/mips/pci/ops-pnx8550.c b/arch/mips/pci/ops-pnx8550.c index f556b7a8dccd..d61064652498 100644 --- a/arch/mips/pci/ops-pnx8550.c +++ b/arch/mips/pci/ops-pnx8550.c @@ -117,7 +117,7 @@ read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 * val) unsigned int data = 0; int err; - if (bus == 0) + if (bus == NULL) return -1; err = config_access(PCI_CMD_CONFIG_READ, bus, devfn, where, ~(1 << (where & 3)), &data); @@ -145,7 +145,7 @@ read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 * val) unsigned int data = 0; int err; - if (bus == 0) + if (bus == NULL) return -1; if (where & 0x01) @@ -168,7 +168,7 @@ static int read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 * val) { int err; - if (bus == 0) + if (bus == NULL) return -1; if (where & 0x03) @@ -185,7 +185,7 @@ write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val) unsigned int data = (unsigned int)val; int err; - if (bus == 0) + if (bus == NULL) return -1; switch (where & 0x03) { @@ -213,7 +213,7 @@ write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val) unsigned int data = (unsigned int)val; int err; - if (bus == 0) + if (bus == NULL) return -1; if (where & 0x01) @@ -235,7 +235,7 @@ static int write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val) { int err; - if (bus == 0) + if (bus == NULL) return -1; if (where & 0x03) diff --git a/arch/mips/pci/pci-ddb5477.c b/arch/mips/pci/pci-ddb5477.c deleted file mode 100644 index 7363e1877842..000000000000 --- a/arch/mips/pci/pci-ddb5477.c +++ /dev/null @@ -1,207 +0,0 @@ -/* - * PCI code for DDB5477. - * - * Copyright (C) 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/types.h> -#include <linux/pci.h> - -#include <asm/bootinfo.h> -#include <asm/debug.h> - -#include <asm/ddb5xxx/ddb5xxx.h> - -static struct resource extpci_io_resource = { - .start = DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + 0x4000, - .end = DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI0_IO_SIZE - 1, - .name = "ext pci IO space", - .flags = IORESOURCE_IO -}; - -static struct resource extpci_mem_resource = { - .start = DDB_PCI0_MEM_BASE + 0x100000, - .end = DDB_PCI0_MEM_BASE + DDB_PCI0_MEM_SIZE - 1, - .name = "ext pci memory space", - .flags = IORESOURCE_MEM -}; - -static struct resource iopci_io_resource = { - .start = DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE, - .end = DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI1_IO_SIZE - 1, - .name = "io pci IO space", - .flags = IORESOURCE_IO -}; - -static struct resource iopci_mem_resource = { - .start = DDB_PCI1_MEM_BASE, - .end = DDB_PCI1_MEM_BASE + DDB_PCI1_MEM_SIZE - 1, - .name = "ext pci memory space", - .flags = IORESOURCE_MEM -}; - -extern struct pci_ops ddb5477_ext_pci_ops; -extern struct pci_ops ddb5477_io_pci_ops; - -struct pci_controller ddb5477_ext_controller = { - .pci_ops = &ddb5477_ext_pci_ops, - .io_resource = &extpci_io_resource, - .mem_resource = &extpci_mem_resource -}; - -struct pci_controller ddb5477_io_controller = { - .pci_ops = &ddb5477_io_pci_ops, - .io_resource = &iopci_io_resource, - .mem_resource = &iopci_mem_resource -}; - - - -/* - * we fix up irqs based on the slot number. - * The first entry is at AD:11. - * Fortunately this works because, although we have two pci buses, - * they all have different slot numbers (except for rockhopper slot 20 - * which is handled below). - * - */ - -/* - * irq mapping : device -> pci int # -> vrc4377 irq# , - * ddb5477 board manual page 4 and vrc5477 manual page 46 - */ - -/* - * based on ddb5477 manual page 11 - */ -#define MAX_SLOT_NUM 21 -static unsigned char irq_map[MAX_SLOT_NUM] = { - /* SLOT: 0, AD:11 */ 0xff, - /* SLOT: 1, AD:12 */ 0xff, - /* SLOT: 2, AD:13 */ 0xff, - /* SLOT: 3, AD:14 */ 0xff, - /* SLOT: 4, AD:15 */ VRC5477_IRQ_INTA, /* onboard tulip */ - /* SLOT: 5, AD:16 */ VRC5477_IRQ_INTB, /* slot 1 */ - /* SLOT: 6, AD:17 */ VRC5477_IRQ_INTC, /* slot 2 */ - /* SLOT: 7, AD:18 */ VRC5477_IRQ_INTD, /* slot 3 */ - /* SLOT: 8, AD:19 */ VRC5477_IRQ_INTE, /* slot 4 */ - /* SLOT: 9, AD:20 */ 0xff, - /* SLOT: 10, AD:21 */ 0xff, - /* SLOT: 11, AD:22 */ 0xff, - /* SLOT: 12, AD:23 */ 0xff, - /* SLOT: 13, AD:24 */ 0xff, - /* SLOT: 14, AD:25 */ 0xff, - /* SLOT: 15, AD:26 */ 0xff, - /* SLOT: 16, AD:27 */ 0xff, - /* SLOT: 17, AD:28 */ 0xff, - /* SLOT: 18, AD:29 */ VRC5477_IRQ_IOPCI_INTC, /* vrc5477 ac97 */ - /* SLOT: 19, AD:30 */ VRC5477_IRQ_IOPCI_INTB, /* vrc5477 usb peri */ - /* SLOT: 20, AD:31 */ VRC5477_IRQ_IOPCI_INTA, /* vrc5477 usb host */ -}; -static unsigned char rockhopperII_irq_map[MAX_SLOT_NUM] = { - /* SLOT: 0, AD:11 */ 0xff, - /* SLOT: 1, AD:12 */ VRC5477_IRQ_INTB, /* onboard AMD PCNET */ - /* SLOT: 2, AD:13 */ 0xff, - /* SLOT: 3, AD:14 */ 0xff, - /* SLOT: 4, AD:15 */ 14, /* M5229 ide ISA irq */ - /* SLOT: 5, AD:16 */ VRC5477_IRQ_INTD, /* slot 3 */ - /* SLOT: 6, AD:17 */ VRC5477_IRQ_INTA, /* slot 4 */ - /* SLOT: 7, AD:18 */ VRC5477_IRQ_INTD, /* slot 5 */ - /* SLOT: 8, AD:19 */ 0, /* M5457 modem nop */ - /* SLOT: 9, AD:20 */ VRC5477_IRQ_INTA, /* slot 2 */ - /* SLOT: 10, AD:21 */ 0xff, - /* SLOT: 11, AD:22 */ 0xff, - /* SLOT: 12, AD:23 */ 0xff, - /* SLOT: 13, AD:24 */ 0xff, - /* SLOT: 14, AD:25 */ 0xff, - /* SLOT: 15, AD:26 */ 0xff, - /* SLOT: 16, AD:27 */ 0xff, - /* SLOT: 17, AD:28 */ 0, /* M7101 PMU nop */ - /* SLOT: 18, AD:29 */ VRC5477_IRQ_IOPCI_INTC, /* vrc5477 ac97 */ - /* SLOT: 19, AD:30 */ VRC5477_IRQ_IOPCI_INTB, /* vrc5477 usb peri */ - /* SLOT: 20, AD:31 */ VRC5477_IRQ_IOPCI_INTA, /* vrc5477 usb host */ -}; - -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - int slot_num; - unsigned char *slot_irq_map; - unsigned char irq; - - /* - * We ignore the swizzled slot and pin values. The original - * pci_fixup_irq() codes largely base irq number on the dev slot - * numbers because except for one case they are unique even - * though there are multiple pci buses. - */ - - if (mips_machtype == MACH_NEC_ROCKHOPPERII) - slot_irq_map = rockhopperII_irq_map; - else - slot_irq_map = irq_map; - - slot_num = PCI_SLOT(dev->devfn); - irq = slot_irq_map[slot_num]; - - db_assert(slot_num < MAX_SLOT_NUM); - - db_assert(irq != 0xff); - - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); - - if (mips_machtype == MACH_NEC_ROCKHOPPERII) { - /* hack to distinquish overlapping slot 20s, one - * on bus 0 (ALI USB on the M1535 on the backplane), - * and one on bus 2 (NEC USB controller on the CPU board) - * Make the M1535 USB - ISA IRQ number 9. - */ - if (slot_num == 20 && dev->bus->number == 0) { - pci_write_config_byte(dev, - PCI_INTERRUPT_LINE, - 9); - irq = 9; - } - - } - - return irq; -} - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} - -void ddb_pci_reset_bus(void) -{ - u32 temp; - - /* - * I am not sure about the "official" procedure, the following - * steps work as far as I know: - * We first set PCI cold reset bit (bit 31) in PCICTRL-H. - * Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H. - * The same is true for both PCI channels. - */ - temp = ddb_in32(DDB_PCICTL0_H); - temp |= 0x80000000; - ddb_out32(DDB_PCICTL0_H, temp); - temp &= ~0xc0000000; - ddb_out32(DDB_PCICTL0_H, temp); - - temp = ddb_in32(DDB_PCICTL1_H); - temp |= 0x80000000; - ddb_out32(DDB_PCICTL1_H, temp); - temp &= ~0xc0000000; - ddb_out32(DDB_PCICTL1_H, temp); -} diff --git a/arch/mips/pci/pci-ocelot.c b/arch/mips/pci/pci-ocelot.c deleted file mode 100644 index 1421d34535ef..000000000000 --- a/arch/mips/pci/pci-ocelot.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * Galileo Evaluation Boards PCI support. - * - * The general-purpose functions to read/write and configure the GT64120A's - * PCI registers (function names start with pci0 or pci1) are either direct - * copies of functions written by Galileo Technology, or are modifications - * of their functions to work with Linux 2.4 vs Linux 2.2. These functions - * are Copyright - Galileo Technology. - * - * Other functions are derived from other MIPS PCI implementations, or were - * written by RidgeRun, Inc, Copyright (C) 2000 RidgeRun, Inc. - * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com - * - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include <linux/init.h> -#include <linux/types.h> -#include <linux/pci.h> -#include <linux/kernel.h> -#include <linux/slab.h> -#include <linux/cache.h> -#include <asm/pci.h> -#include <asm/io.h> -#include <asm/gt64120.h> - -static inline unsigned int pci0ReadConfigReg(unsigned int offset) -{ - unsigned int DataForRegCf8; - unsigned int data; - - DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) | - (PCI_FUNC(device->devfn) << 8) | - (offset & ~0x3)) | 0x80000000; - GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8); - GT_READ(GT_PCI0_CFGDATA_OFS, &data); - - return data; -} - -static inline void pci0WriteConfigReg(unsigned int offset, unsigned int data) -{ - unsigned int DataForRegCf8; - - DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) | - (PCI_FUNC(device->devfn) << 8) | - (offset & ~0x3)) | 0x80000000; - GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8); - GT_WRITE(GT_PCI0_CFGDATA_OFS, data); -} - -static struct resource ocelot_mem_resource = { - .start = GT_PCI_MEM_BASE, - .end = GT_PCI_MEM_BASE + GT_PCI_MEM_BASE - 1, -}; - -static struct resource ocelot_io_resource = { - .start = GT_PCI_IO_BASE, - .end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1, -}; - -static struct pci_controller ocelot_pci_controller = { - .pci_ops = gt64xxx_pci0_ops, - .mem_resource = &ocelot_mem_resource, - .io_resource = &ocelot_io_resource, -}; - -static int __init ocelot_pcibios_init(void) -{ - u32 tmp; - - GT_READ(GT_PCI0_CMD_OFS, &tmp); - GT_READ(GT_PCI0_BARE_OFS, &tmp); - - /* - * You have to enable bus mastering to configure any other - * card on the bus. - */ - tmp = pci0ReadConfigReg(PCI_COMMAND); - tmp |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SERR; - pci0WriteConfigReg(PCI_COMMAND, tmp); - - register_pci_controller(&ocelot_pci_controller); -} - -arch_initcall(ocelot_pcibios_init); diff --git a/arch/mips/philips/pnx8550/common/Makefile b/arch/mips/philips/pnx8550/common/Makefile index b7c638166e9f..31cc1a5cec3b 100644 --- a/arch/mips/philips/pnx8550/common/Makefile +++ b/arch/mips/philips/pnx8550/common/Makefile @@ -25,3 +25,5 @@ obj-y := setup.o prom.o int.o reset.o time.o proc.o platform.o obj-$(CONFIG_PCI) += pci.o obj-$(CONFIG_KGDB) += gdb_hook.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/pmc-sierra/yosemite/Makefile b/arch/mips/pmc-sierra/yosemite/Makefile index e931e0d44229..8fd9a04e3534 100644 --- a/arch/mips/pmc-sierra/yosemite/Makefile +++ b/arch/mips/pmc-sierra/yosemite/Makefile @@ -2,7 +2,9 @@ # Makefile for the PMC-Sierra Titan # -obj-y += irq.o i2c-yosemite.o prom.o py-console.o setup.o +obj-y += irq.o prom.o py-console.o setup.o obj-$(CONFIG_KGDB) += dbg_io.o obj-$(CONFIG_SMP) += smp.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/pmc-sierra/yosemite/i2c-yosemite.c b/arch/mips/pmc-sierra/yosemite/i2c-yosemite.c deleted file mode 100644 index 85b14c73c226..000000000000 --- a/arch/mips/pmc-sierra/yosemite/i2c-yosemite.c +++ /dev/null @@ -1,188 +0,0 @@ -/* - * Copyright (C) 2003 PMC-Sierra Inc. - * Author: Manish Lachwani (lachwani@pmc-sierra.com) - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -/* - * Detailed Description: - * - * This block implements the I2C interface to the slave devices like the - * Atmel 24C32 EEPROM and the MAX 1619 Sensors device. The I2C Master interface - * can be controlled by the SCMB block. And the SCMB block kicks in only when - * using the Ethernet Mode of operation and __not__ the SysAD mode - * - * The SCMB controls the two modes: MDIO and the I2C. The MDIO mode is used to - * communicate with the Quad-PHY from Marvel. The I2C is used to communicate - * with the I2C slave devices. It seems that the driver does not explicitly - * deal with the control of SDA and SCL serial lines. So, the driver will set - * the slave address, drive the command and then the data. The SCMB will then - * control the two serial lines as required. - * - * It seems the documents are very unclear abt this. Hence, I took some time - * out to write the desciption to have an idea of how the I2C can actually - * work. Currently, this Linux driver wont be integrated into the generic Linux - * I2C framework. And finally, the I2C interface is also known as the 2BI - * interface. 2BI means 2-bit interface referring to SDA and SCL serial lines - * respectively. - * - * - Manish Lachwani (12/09/2003) - */ - -#include "i2c-yosemite.h" - -/* - * Poll the I2C interface for the BUSY bit. - */ -static int titan_i2c_poll(void) -{ - int i = 0; - unsigned long val = 0; - - for (i = 0; i < TITAN_I2C_MAX_POLL; i++) { - val = TITAN_I2C_READ(TITAN_I2C_COMMAND); - - if (!(val & 0x8000)) - return 0; - } - - return TITAN_I2C_ERR_TIMEOUT; -} - -/* - * Execute the I2C command - */ -int titan_i2c_xfer(unsigned int slave_addr, titan_i2c_command * cmd, - int size, unsigned int *addr) -{ - int loop, bytes = 0, i; - unsigned int *write_data, data, *read_data; - unsigned long reg_val, val; - - write_data = cmd->data; - read_data = addr; - - TITAN_I2C_WRITE(TITAN_I2C_SLAVE_ADDRESS, slave_addr); - - if (cmd->type == TITAN_I2C_CMD_WRITE) - loop = cmd->write_size; - else - loop = size; - - while (loop > 0) { - if ((cmd->type == TITAN_I2C_CMD_WRITE) || - (cmd->type == TITAN_I2C_CMD_READ_WRITE)) { - - reg_val = TITAN_I2C_DATA; - for (i = 0; i < TITAN_I2C_MAX_WORDS_PER_RW; - ++i, write_data += 2, reg_val += 4) { - if (bytes < cmd->write_size) { - data = write_data[0]; - ++data; - } - - if (bytes < cmd->write_size) { - data = write_data[1]; - ++data; - } - - TITAN_I2C_WRITE(reg_val, data); - } - } - - TITAN_I2C_WRITE(TITAN_I2C_COMMAND, - (unsigned int) (cmd->type << 13)); - if (titan_i2c_poll() != TITAN_I2C_ERR_OK) - return TITAN_I2C_ERR_TIMEOUT; - - if ((cmd->type == TITAN_I2C_CMD_READ) || - (cmd->type == TITAN_I2C_CMD_READ_WRITE)) { - - reg_val = TITAN_I2C_DATA; - for (i = 0; i < TITAN_I2C_MAX_WORDS_PER_RW; - ++i, read_data += 2, reg_val += 4) { - data = TITAN_I2C_READ(reg_val); - - if (bytes < size) { - read_data[0] = data & 0xff; - ++bytes; - } - - if (bytes < size) { - read_data[1] = - ((data >> 8) & 0xff); - ++bytes; - } - } - } - - loop -= (TITAN_I2C_MAX_WORDS_PER_RW * 2); - } - - /* - * Read the Interrupt status and then return the appropriate error code - */ - - val = TITAN_I2C_READ(TITAN_I2C_INTERRUPTS); - if (val & 0x0020) - return TITAN_I2C_ERR_ARB_LOST; - - if (val & 0x0040) - return TITAN_I2C_ERR_NO_RESP; - - if (val & 0x0080) - return TITAN_I2C_ERR_DATA_COLLISION; - - return TITAN_I2C_ERR_OK; -} - -/* - * Init the I2C subsystem of the PMC-Sierra Yosemite board - */ -int titan_i2c_init(titan_i2c_config * config) -{ - unsigned int val; - - /* - * Reset the SCMB and program into the I2C mode - */ - TITAN_I2C_WRITE(TITAN_I2C_SCMB_CONTROL, 0xA000); - TITAN_I2C_WRITE(TITAN_I2C_SCMB_CONTROL, 0x2000); - - /* - * Configure the filtera and clka values - */ - val = TITAN_I2C_READ(TITAN_I2C_SCMB_CLOCK_A); - val |= ((val & ~(0xF000)) | ((config->filtera << 12) & 0xF000)); - val |= ((val & ~(0x03FF)) | (config->clka & 0x03FF)); - TITAN_I2C_WRITE(TITAN_I2C_SCMB_CLOCK_A, val); - - /* - * Configure the filterb and clkb values - */ - val = TITAN_I2C_READ(TITAN_I2C_SCMB_CLOCK_B); - val |= ((val & ~(0xF000)) | ((config->filterb << 12) & 0xF000)); - val |= ((val & ~(0x03FF)) | (config->clkb & 0x03FF)); - TITAN_I2C_WRITE(TITAN_I2C_SCMB_CLOCK_B, val); - - return TITAN_I2C_ERR_OK; -} diff --git a/arch/mips/pmc-sierra/yosemite/irq.c b/arch/mips/pmc-sierra/yosemite/irq.c index 428d1f45a287..4decc2807867 100644 --- a/arch/mips/pmc-sierra/yosemite/irq.c +++ b/arch/mips/pmc-sierra/yosemite/irq.c @@ -56,6 +56,9 @@ #define HYPERTRANSPORT_INTC 0x7a /* INTC# */ #define HYPERTRANSPORT_INTD 0x7b /* INTD# */ +extern void titan_mailbox_irq(void); + +#ifdef CONFIG_HYPERTRANSPORT /* * Handle hypertransport & SMP interrupts. The interrupt lines are scarce. * For interprocessor interrupts, the best thing to do is to use the INTMSG @@ -107,6 +110,7 @@ static void ll_ht_smp_irq_handler(int irq) do_IRQ(irq); } +#endif asmlinkage void plat_irq_dispatch(void) { diff --git a/arch/mips/pmc-sierra/yosemite/prom.c b/arch/mips/pmc-sierra/yosemite/prom.c index 1e1685e415a4..0cd78f0f5f2d 100644 --- a/arch/mips/pmc-sierra/yosemite/prom.c +++ b/arch/mips/pmc-sierra/yosemite/prom.c @@ -34,7 +34,7 @@ extern void prom_grab_secondary(void); struct callvectors *debug_vectors; extern unsigned long yosemite_base; -extern unsigned long cpu_clock; +extern unsigned long cpu_clock_freq; const char *get_system_type(void) { @@ -119,7 +119,7 @@ void __init prom_init(void) 16); if (strncmp("cpuclock", *env, strlen("cpuclock")) == 0) - cpu_clock = + cpu_clock_freq = simple_strtol(*env + strlen("cpuclock="), NULL, 10); diff --git a/arch/mips/pmc-sierra/yosemite/setup.c b/arch/mips/pmc-sierra/yosemite/setup.c index f7f93ae24c34..58862c8d1d00 100644 --- a/arch/mips/pmc-sierra/yosemite/setup.c +++ b/arch/mips/pmc-sierra/yosemite/setup.c @@ -59,7 +59,7 @@ unsigned char titan_ge_mac_addr_base[6] = { 0x00, 0xe0, 0x04, 0x00, 0x00, 0x21 }; -unsigned long cpu_clock; +unsigned long cpu_clock_freq; unsigned long yosemite_base; static struct m48t37_rtc *m48t37_base; @@ -140,7 +140,7 @@ void __init plat_timer_setup(struct irqaction *irq) void yosemite_time_init(void) { - mips_hpt_frequency = cpu_clock / 2; + mips_hpt_frequency = cpu_clock_freq / 2; mips_hpt_frequency = 33000000 * 3 * 5; } diff --git a/arch/mips/pmc-sierra/yosemite/smp.c b/arch/mips/pmc-sierra/yosemite/smp.c index d83c4ada14f3..1c852d6a7654 100644 --- a/arch/mips/pmc-sierra/yosemite/smp.c +++ b/arch/mips/pmc-sierra/yosemite/smp.c @@ -106,23 +106,28 @@ void prom_smp_finish(void) { } -asmlinkage void titan_mailbox_irq(void) +void titan_mailbox_irq(void) { int cpu = smp_processor_id(); unsigned long status; - if (cpu == 0) { + switch (cpu) { + case 0: status = OCD_READ(RM9000x2_OCD_INTP0STATUS3); OCD_WRITE(RM9000x2_OCD_INTP0CLEAR3, status); - } - if (cpu == 1) { + if (status & 0x2) + smp_call_function_interrupt(); + break; + + case 1: status = OCD_READ(RM9000x2_OCD_INTP1STATUS3); OCD_WRITE(RM9000x2_OCD_INTP1CLEAR3, status); - } - if (status & 0x2) - smp_call_function_interrupt(); + if (status & 0x2) + smp_call_function_interrupt(); + break; + } } /* diff --git a/arch/mips/qemu/Makefile b/arch/mips/qemu/Makefile index 078cd3029c9f..cec24c117f6e 100644 --- a/arch/mips/qemu/Makefile +++ b/arch/mips/qemu/Makefile @@ -5,3 +5,5 @@ obj-y = q-firmware.o q-irq.o q-mem.o q-setup.o q-reset.o obj-$(CONFIG_SMP) += q-smp.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/sgi-ip27/Makefile b/arch/mips/sgi-ip27/Makefile index 7ce76e20beb9..e0a6871d56e4 100644 --- a/arch/mips/sgi-ip27/Makefile +++ b/arch/mips/sgi-ip27/Makefile @@ -9,3 +9,5 @@ obj-y := ip27-berr.o ip27-irq.o ip27-init.o ip27-klconfig.o ip27-klnuma.o \ obj-$(CONFIG_EARLY_PRINTK) += ip27-console.o obj-$(CONFIG_KGDB) += ip27-dbgio.o obj-$(CONFIG_SMP) += ip27-smp.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/sgi-ip27/ip27-klnuma.c b/arch/mips/sgi-ip27/ip27-klnuma.c index f9f404a8ddad..f10d9839006d 100644 --- a/arch/mips/sgi-ip27/ip27-klnuma.c +++ b/arch/mips/sgi-ip27/ip27-klnuma.c @@ -28,8 +28,6 @@ static cpumask_t ktext_repmask; */ void __init setup_replication_mask(void) { - cnodeid_t cnode; - /* Set only the master cnode's bit. The master cnode is always 0. */ cpus_clear(ktext_repmask); cpu_set(0, ktext_repmask); @@ -38,11 +36,15 @@ void __init setup_replication_mask(void) #ifndef CONFIG_MAPPED_KERNEL #error Kernel replication works with mapped kernel support. No calias support. #endif - for_each_online_node(cnode) { - if (cnode == 0) - continue; - /* Advertise that we have a copy of the kernel */ - cpu_set(cnode, ktext_repmask); + { + cnodeid_t cnode; + + for_each_online_node(cnode) { + if (cnode == 0) + continue; + /* Advertise that we have a copy of the kernel */ + cpu_set(cnode, ktext_repmask); + } } #endif /* Set up a GDA pointer to the replication mask. */ diff --git a/arch/mips/sgi-ip27/ip27-smp.c b/arch/mips/sgi-ip27/ip27-smp.c index 09fa7f5216f0..08e79141b47c 100644 --- a/arch/mips/sgi-ip27/ip27-smp.c +++ b/arch/mips/sgi-ip27/ip27-smp.c @@ -181,7 +181,7 @@ void __init prom_boot_secondary(int cpu, struct task_struct *idle) 0, (void *) sp, (void *) gp); } -void prom_init_secondary(void) +void __cpuinit prom_init_secondary(void) { per_cpu_init(); local_irq_enable(); diff --git a/arch/mips/sgi-ip32/Makefile b/arch/mips/sgi-ip32/Makefile index 60f0227425e7..31c9aa1bcb40 100644 --- a/arch/mips/sgi-ip32/Makefile +++ b/arch/mips/sgi-ip32/Makefile @@ -5,3 +5,5 @@ obj-y += ip32-berr.o ip32-irq.o ip32-platform.o ip32-setup.o ip32-reset.o \ crime.o ip32-memory.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/sgi-ip32/ip32-reset.c b/arch/mips/sgi-ip32/ip32-reset.c index db8084411538..624bbdbff2a8 100644 --- a/arch/mips/sgi-ip32/ip32-reset.c +++ b/arch/mips/sgi-ip32/ip32-reset.c @@ -195,7 +195,8 @@ static __init int ip32_reboot_setup(void) blink_timer.function = blink_timeout; atomic_notifier_chain_register(&panic_notifier_list, &panic_block); - request_irq(MACEISA_RTC_IRQ, ip32_rtc_int, 0, "rtc", NULL); + if (request_irq(MACEISA_RTC_IRQ, ip32_rtc_int, 0, "rtc", NULL)) + panic("Can't allocate MACEISA RTC IRQ"); return 0; } diff --git a/arch/mips/sibyte/bcm1480/Makefile b/arch/mips/sibyte/bcm1480/Makefile index cdc4c56c3e29..f292f7df0cfb 100644 --- a/arch/mips/sibyte/bcm1480/Makefile +++ b/arch/mips/sibyte/bcm1480/Makefile @@ -1,3 +1,5 @@ obj-y := setup.o irq.o time.o obj-$(CONFIG_SMP) += smp.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/sibyte/bcm1480/setup.c b/arch/mips/sibyte/bcm1480/setup.c index 89f29233cae1..bb28f28e8042 100644 --- a/arch/mips/sibyte/bcm1480/setup.c +++ b/arch/mips/sibyte/bcm1480/setup.c @@ -16,6 +16,7 @@ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include <linux/kernel.h> +#include <linux/module.h> #include <linux/reboot.h> #include <linux/string.h> diff --git a/arch/mips/sibyte/common/Makefile b/arch/mips/sibyte/common/Makefile index 8a06a4fb5212..f8ae30066a05 100644 --- a/arch/mips/sibyte/common/Makefile +++ b/arch/mips/sibyte/common/Makefile @@ -3,3 +3,4 @@ obj-y := obj-$(CONFIG_SIBYTE_TBPROF) += sb_tbprof.o EXTRA_AFLAGS := $(CFLAGS) +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/sibyte/sb1250/Makefile b/arch/mips/sibyte/sb1250/Makefile index df662c61473a..697793783a25 100644 --- a/arch/mips/sibyte/sb1250/Makefile +++ b/arch/mips/sibyte/sb1250/Makefile @@ -3,3 +3,5 @@ obj-y := setup.o irq.o time.o obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_SIBYTE_STANDALONE) += prom.o obj-$(CONFIG_SIBYTE_BUS_WATCHER) += bus_watcher.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/sni/Makefile b/arch/mips/sni/Makefile index 471418e4f446..3a99cd62c0bd 100644 --- a/arch/mips/sni/Makefile +++ b/arch/mips/sni/Makefile @@ -4,3 +4,5 @@ obj-y += irq.o reset.o setup.o a20r.o rm200.o pcimt.o pcit.o time.o obj-$(CONFIG_CPU_BIG_ENDIAN) += sniprom.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/tx4927/common/tx4927_irq.c b/arch/mips/tx4927/common/tx4927_irq.c index 3d25d010f3d5..00b0b975f349 100644 --- a/arch/mips/tx4927/common/tx4927_irq.c +++ b/arch/mips/tx4927/common/tx4927_irq.c @@ -43,6 +43,9 @@ #include <asm/mipsregs.h> #include <asm/system.h> #include <asm/tx4927/tx4927.h> +#ifdef CONFIG_TOSHIBA_RBTX4927 +#include <asm/tx4927/toshiba_rbtx4927.h> +#endif /* * DEBUG diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c index 5cc30c10e746..e265fcd31b60 100644 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c +++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c @@ -262,8 +262,6 @@ u32 bit2num(u32 num) int toshiba_rbtx4927_irq_nested(int sw_irq) { u32 level3; - u32 level4; - u32 level5; level3 = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; if (level3) { @@ -275,6 +273,8 @@ int toshiba_rbtx4927_irq_nested(int sw_irq) #ifdef CONFIG_TOSHIBA_FPCIB0 { if (tx4927_using_backplane) { + u32 level4; + u32 level5; outb(0x0A, 0x20); level4 = inb(0x20) & 0xff; if (level4) { diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c index ab72292a172e..ea5a70b252a0 100644 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c +++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c @@ -159,58 +159,6 @@ int tx4927_pci66 = 0; /* 0:auto */ char *toshiba_name = ""; #ifdef CONFIG_PCI -static void tx4927_pcierr_interrupt(int irq, void *dev_id) -{ -#ifdef CONFIG_BLK_DEV_IDEPCI - /* ignore MasterAbort for ide probing... */ - if (irq == TX4927_IRQ_IRC_PCIERR && - ((tx4927_pcicptr->pcistatus >> 16) & 0xf900) == - PCI_STATUS_REC_MASTER_ABORT) { - tx4927_pcicptr->pcistatus = - (tx4927_pcicptr-> - pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT - << 16); - - return; - } -#endif - printk("PCI error interrupt (irq 0x%x).\n", irq); - - printk("pcistat:%04x, g2pstatus:%08lx, pcicstatus:%08lx\n", - (unsigned short) (tx4927_pcicptr->pcistatus >> 16), - tx4927_pcicptr->g2pstatus, tx4927_pcicptr->pcicstatus); - printk("ccfg:%08lx, tear:%02lx_%08lx\n", - (unsigned long) tx4927_ccfgptr->ccfg, - (unsigned long) (tx4927_ccfgptr->tear >> 32), - (unsigned long) tx4927_ccfgptr->tear); - show_regs(get_irq_regs()); -} - -void __init toshiba_rbtx4927_pci_irq_init(void) -{ - return; -} - -void tx4927_reset_pci_pcic(void) -{ - /* Reset PCI Bus */ - *tx4927_pcireset_ptr = 1; - /* Reset PCIC */ - tx4927_ccfgptr->clkctr |= TX4927_CLKCTR_PCIRST; - udelay(10000); - /* clear PCIC reset */ - tx4927_ccfgptr->clkctr &= ~TX4927_CLKCTR_PCIRST; - *tx4927_pcireset_ptr = 0; -} -#endif /* CONFIG_PCI */ - -#ifdef CONFIG_PCI -void print_pci_status(void) -{ - printk("PCI STATUS %lx\n", tx4927_pcicptr->pcistatus); - printk("PCIC STATUS %lx\n", tx4927_pcicptr->pcicstatus); -} - extern struct pci_controller tx4927_controller; static struct pci_dev *fake_pci_dev(struct pci_controller *hose, @@ -239,10 +187,8 @@ static int early_##rw##_config_##size(struct pci_controller *hose, \ } EARLY_PCI_OP(read, byte, u8 *) -EARLY_PCI_OP(read, word, u16 *) EARLY_PCI_OP(read, dword, u32 *) EARLY_PCI_OP(write, byte, u8) -EARLY_PCI_OP(write, word, u16) EARLY_PCI_OP(write, dword, u32) static int __init tx4927_pcibios_init(void) @@ -269,7 +215,9 @@ static int __init tx4927_pcibios_init(void) u8 v08_64; u32 v32_b0; u8 v08_e1; +#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG char *s = " sb/isa --"; +#endif TOSHIBA_RBTX4927_SETUP_DPRINTK (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n", @@ -354,7 +302,9 @@ static int __init tx4927_pcibios_init(void) u8 v08_41; u8 v08_43; u8 v08_5c; +#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG char *s = " sb/ide --"; +#endif TOSHIBA_RBTX4927_SETUP_DPRINTK (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n", diff --git a/arch/mips/tx4938/toshiba_rbtx4938/setup.c b/arch/mips/tx4938/toshiba_rbtx4938/setup.c index 6ed39a5aea72..f9ad482749e4 100644 --- a/arch/mips/tx4938/toshiba_rbtx4938/setup.c +++ b/arch/mips/tx4938/toshiba_rbtx4938/setup.c @@ -657,7 +657,7 @@ void __init tx4938_board_setup(void) /* clocks */ if (txx9_master_clock) { - /* calculate gbus_clock and cpu_clock from master_clock */ + /* calculate gbus_clock and cpu_clock_freq from master_clock */ divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK; switch (divmode) { case TX4938_CCFG_DIVMODE_8: @@ -691,7 +691,7 @@ void __init tx4938_board_setup(void) if (txx9_cpu_clock == 0) { txx9_cpu_clock = 300000000; /* 300MHz */ } - /* calculate gbus_clock and master_clock from cpu_clock */ + /* calculate gbus_clock and master_clock from cpu_clock_freq */ cpuclk = txx9_cpu_clock; divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK; switch (divmode) { diff --git a/arch/mips/vr41xx/common/Makefile b/arch/mips/vr41xx/common/Makefile index d0d84ec8d63d..7d5d83b8c582 100644 --- a/arch/mips/vr41xx/common/Makefile +++ b/arch/mips/vr41xx/common/Makefile @@ -3,3 +3,5 @@ # obj-y += bcu.o cmu.o giu.o icu.o init.o irq.o pmu.o rtc.o siu.o type.o + +EXTRA_CFLAGS += -Werror diff --git a/drivers/input/evdev.c b/drivers/input/evdev.c index ab4b2d9b5327..f1c3d6cebd58 100644 --- a/drivers/input/evdev.c +++ b/drivers/input/evdev.c @@ -186,7 +186,7 @@ struct input_event_compat { #elif defined(CONFIG_S390) # define COMPAT_TEST test_thread_flag(TIF_31BIT) #elif defined(CONFIG_MIPS) -# define COMPAT_TEST (current->thread.mflags & MF_32BIT_ADDR) +# define COMPAT_TEST test_thread_flag(TIF_32BIT_ADDR) #else # define COMPAT_TEST test_thread_flag(TIF_32BIT) #endif diff --git a/drivers/mtd/devices/docprobe.c b/drivers/mtd/devices/docprobe.c index b96ac8e119dc..54aa75907640 100644 --- a/drivers/mtd/devices/docprobe.c +++ b/drivers/mtd/devices/docprobe.c @@ -81,9 +81,6 @@ static unsigned long __initdata doc_locations[] = { #endif /* CONFIG_MTD_DOCPROBE_HIGH */ #elif defined(__PPC__) 0xe4000000, -#elif defined(CONFIG_MOMENCO_OCELOT) - 0x2f000000, - 0xff000000, #elif defined(CONFIG_MOMENCO_OCELOT_G) 0xff000000, ##else diff --git a/drivers/mtd/nand/diskonchip.c b/drivers/mtd/nand/diskonchip.c index 17c868034aad..e96259f22cca 100644 --- a/drivers/mtd/nand/diskonchip.c +++ b/drivers/mtd/nand/diskonchip.c @@ -56,9 +56,6 @@ static unsigned long __initdata doc_locations[] = { #endif /* CONFIG_MTD_DOCPROBE_HIGH */ #elif defined(__PPC__) 0xe4000000, -#elif defined(CONFIG_MOMENCO_OCELOT) - 0x2f000000, - 0xff000000, #elif defined(CONFIG_MOMENCO_OCELOT_G) 0xff000000, #else diff --git a/include/asm-mips/a.out.h b/include/asm-mips/a.out.h index 1ad60ba186d0..bf55a5b34bef 100644 --- a/include/asm-mips/a.out.h +++ b/include/asm-mips/a.out.h @@ -38,7 +38,8 @@ struct exec #define STACK_TOP TASK_SIZE #endif #ifdef CONFIG_64BIT -#define STACK_TOP (current->thread.mflags & MF_32BIT_ADDR ? TASK_SIZE32 : TASK_SIZE) +#define STACK_TOP \ + (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE) #endif #define STACK_TOP_MAX TASK_SIZE diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h index 087126a5faf9..c0f052b37b9e 100644 --- a/include/asm-mips/bootinfo.h +++ b/include/asm-mips/bootinfo.h @@ -86,16 +86,6 @@ #define MACH_COBALT_27 0 /* Proto "27" hardware */ /* - * Valid machtype for group NEC DDB - */ -#define MACH_GROUP_NEC_DDB 8 /* NEC DDB */ -#define MACH_NEC_DDB5074 0 /* NEC DDB Vrc-5074 */ -#define MACH_NEC_DDB5476 1 /* NEC DDB Vrc-5476 */ -#define MACH_NEC_DDB5477 2 /* NEC DDB Vrc-5477 */ -#define MACH_NEC_ROCKHOPPER 3 /* Rockhopper base board */ -#define MACH_NEC_ROCKHOPPERII 4 /* Rockhopper II base board */ - -/* * Valid machtype for group BAGET */ #define MACH_GROUP_BAGET 9 /* Baget */ @@ -145,9 +135,6 @@ #define MACH_TOSHIBA_RBTX4937 5 #define MACH_TOSHIBA_RBTX4938 6 -#define GROUP_TOSHIBA_NAMES { "Pallas", "TopasCE", "JMR", "JMR TX3927", \ - "RBTX4927", "RBTX4937" } - /* * Valid machtype for group Alchemy */ diff --git a/include/asm-mips/ddb5xxx/ddb5477.h b/include/asm-mips/ddb5xxx/ddb5477.h deleted file mode 100644 index 6cf177caf6d5..000000000000 --- a/include/asm-mips/ddb5xxx/ddb5477.h +++ /dev/null @@ -1,342 +0,0 @@ -/*********************************************************************** - * - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * include/asm-mips/ddb5xxx/ddb5477.h - * DDB 5477 specific definitions and macros. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - *********************************************************************** - */ - -#ifndef __ASM_DDB5XXX_DDB5477_H -#define __ASM_DDB5XXX_DDB5477_H - -#include <irq.h> - -/* - * This contains macros that are specific to DDB5477 or renamed from - * DDB5476. - */ - -/* - * renamed PADRs - */ -#define DDB_LCS0 DDB_DCS2 -#define DDB_LCS1 DDB_DCS3 -#define DDB_LCS2 DDB_DCS4 -#define DDB_VRC5477 DDB_INTCS - -/* - * New CPU interface registers - */ -#define DDB_INTCTRL0 0x0400 /* Interrupt Control 0 */ -#define DDB_INTCTRL1 0x0404 /* Interrupt Control 1 */ -#define DDB_INTCTRL2 0x0408 /* Interrupt Control 2 */ -#define DDB_INTCTRL3 0x040c /* Interrupt Control 3 */ - -#define DDB_INT0STAT 0x0420 /* INT0 Status [R] */ -#define DDB_INT1STAT 0x0428 /* INT1 Status [R] */ -#define DDB_INT2STAT 0x0430 /* INT2 Status [R] */ -#define DDB_INT3STAT 0x0438 /* INT3 Status [R] */ -#define DDB_INT4STAT 0x0440 /* INT4 Status [R] */ -#define DDB_NMISTAT 0x0450 /* NMI Status [R] */ - -#define DDB_INTCLR32 0x0468 /* Interrupt Clear */ - -#define DDB_INTPPES0 0x0470 /* PCI0 Interrupt Control */ -#define DDB_INTPPES1 0x0478 /* PCI1 Interrupt Control */ - -#undef DDB_CPUSTAT /* duplicate in Vrc-5477 */ -#define DDB_CPUSTAT 0x0480 /* CPU Status [R] */ -#define DDB_BUSCTRL 0x0488 /* Internal Bus Control */ - - -/* - * Timer registers - */ -#define DDB_REFCTRL_L DDB_T0CTRL -#define DDB_REFCTRL_H (DDB_T0CTRL+4) -#define DDB_REFCNTR DDB_T0CNTR -#define DDB_SPT0CTRL_L DDB_T1CTRL -#define DDB_SPT0CTRL_H (DDB_T1CTRL+4) -#define DDB_SPT1CTRL_L DDB_T2CTRL -#define DDB_SPT1CTRL_H (DDB_T2CTRL+4) -#define DDB_SPT1CNTR DDB_T1CTRL -#define DDB_WDTCTRL_L DDB_T3CTRL -#define DDB_WDTCTRL_H (DDB_T3CTRL+4) -#define DDB_WDTCNTR DDB_T3CNTR - -/* - * DMA registers are moved. We don't care about it for now. TODO. - */ - -/* - * BARs for ext PCI (PCI0) - */ -#undef DDB_BARC -#undef DDB_BARB - -#define DDB_BARC0 0x0210 /* PCI0 Control */ -#define DDB_BARM010 0x0218 /* PCI0 SDRAM bank01 */ -#define DDB_BARM230 0x0220 /* PCI0 SDRAM bank23 */ -#define DDB_BAR00 0x0240 /* PCI0 LDCS0 */ -#define DDB_BAR10 0x0248 /* PCI0 LDCS1 */ -#define DDB_BAR20 0x0250 /* PCI0 LDCS2 */ -#define DDB_BAR30 0x0258 /* PCI0 LDCS3 */ -#define DDB_BAR40 0x0260 /* PCI0 LDCS4 */ -#define DDB_BAR50 0x0268 /* PCI0 LDCS5 */ -#define DDB_BARB0 0x0280 /* PCI0 BOOT */ -#define DDB_BARP00 0x0290 /* PCI0 for IOPCI Window0 */ -#define DDB_BARP10 0x0298 /* PCI0 for IOPCI Window1 */ - -/* - * BARs for IOPIC (PCI1) - */ -#define DDB_BARC1 0x0610 /* PCI1 Control */ -#define DDB_BARM011 0x0618 /* PCI1 SDRAM bank01 */ -#define DDB_BARM231 0x0620 /* PCI1 SDRAM bank23 */ -#define DDB_BAR01 0x0640 /* PCI1 LDCS0 */ -#define DDB_BAR11 0x0648 /* PCI1 LDCS1 */ -#define DDB_BAR21 0x0650 /* PCI1 LDCS2 */ -#define DDB_BAR31 0x0658 /* PCI1 LDCS3 */ -#define DDB_BAR41 0x0660 /* PCI1 LDCS4 */ -#define DDB_BAR51 0x0668 /* PCI1 LDCS5 */ -#define DDB_BARB1 0x0680 /* PCI1 BOOT */ -#define DDB_BARP01 0x0690 /* PCI1 for ext PCI Window0 */ -#define DDB_BARP11 0x0698 /* PCI1 for ext PCI Window1 */ - -/* - * Other registers for ext PCI (PCI0) - */ -#define DDB_PCIINIT00 0x02f0 /* PCI0 Initiator 0 */ -#define DDB_PCIINIT10 0x02f8 /* PCI0 Initiator 1 */ - -#define DDB_PCISWP0 0x02b0 /* PCI0 Swap */ -#define DDB_PCIERR0 0x02b8 /* PCI0 Error */ - -#define DDB_PCICTL0_L 0x02e0 /* PCI0 Control-L */ -#define DDB_PCICTL0_H 0x02e4 /* PCI0 Control-H */ -#define DDB_PCIARB0_L 0x02e8 /* PCI0 Arbitration-L */ -#define DDB_PCIARB0_H 0x02ec /* PCI0 Arbitration-H */ - -/* - * Other registers for IOPCI (PCI1) - */ -#define DDB_IOPCIW0 0x00d0 /* PCI Address Window 0 [R/W] */ -#define DDB_IOPCIW1 0x00d8 /* PCI Address Window 1 [R/W] */ - -#define DDB_PCIINIT01 0x06f0 /* PCI1 Initiator 0 */ -#define DDB_PCIINIT11 0x06f8 /* PCI1 Initiator 1 */ - -#define DDB_PCISWP1 0x06b0 /* PCI1 Swap */ -#define DDB_PCIERR1 0x06b8 /* PCI1 Error */ - -#define DDB_PCICTL1_L 0x06e0 /* PCI1 Control-L */ -#define DDB_PCICTL1_H 0x06e4 /* PCI1 Control-H */ -#define DDB_PCIARB1_L 0x06e8 /* PCI1 Arbitration-L */ -#define DDB_PCIARB1_H 0x06ec /* PCI1 Arbitration-H */ - -/* - * Local Bus - */ -#define DDB_LCST0 0x0110 /* LB Chip Select Timing 0 */ -#define DDB_LCST1 0x0118 /* LB Chip Select Timing 1 */ -#undef DDB_LCST2 -#define DDB_LCST2 0x0120 /* LB Chip Select Timing 2 */ -#undef DDB_LCST3 -#undef DDB_LCST4 -#undef DDB_LCST5 -#undef DDB_LCST6 -#undef DDB_LCST7 -#undef DDB_LCST8 -#define DDB_ERRADR 0x0150 /* Error Address Register */ -#define DDB_ERRCS 0x0160 -#define DDB_BTM 0x0170 /* Boot Time Mode value */ - -/* - * MISC registers - */ -#define DDB_GIUFUNSEL 0x4040 /* select dual-func pins */ -#define DDB_PIBMISC 0x0750 /* USB buffer enable / power saving */ - -/* - * Memory map (physical address) - * - * Note most of the following address must be properly aligned by the - * corresponding size. For example, if PCI_IO_SIZE is 16MB, then - * PCI_IO_BASE must be aligned along 16MB boundary. - */ - -/* the actual ram size is detected at run-time */ -#define DDB_SDRAM_BASE 0x00000000 -#define DDB_MAX_SDRAM_SIZE 0x08000000 /* less than 128MB */ - -#define DDB_PCI0_MEM_BASE 0x08000000 -#define DDB_PCI0_MEM_SIZE 0x08000000 /* 128 MB */ - -#define DDB_PCI1_MEM_BASE 0x10000000 -#define DDB_PCI1_MEM_SIZE 0x08000000 /* 128 MB */ - -#define DDB_PCI0_CONFIG_BASE 0x18000000 -#define DDB_PCI0_CONFIG_SIZE 0x01000000 /* 16 MB */ - -#define DDB_PCI1_CONFIG_BASE 0x19000000 -#define DDB_PCI1_CONFIG_SIZE 0x01000000 /* 16 MB */ - -#define DDB_PCI_IO_BASE 0x1a000000 /* we concatenate two IOs */ -#define DDB_PCI0_IO_BASE 0x1a000000 -#define DDB_PCI0_IO_SIZE 0x01000000 /* 16 MB */ -#define DDB_PCI1_IO_BASE 0x1b000000 -#define DDB_PCI1_IO_SIZE 0x01000000 /* 16 MB */ - -#define DDB_LCS0_BASE 0x1c000000 /* flash memory */ -#define DDB_LCS0_SIZE 0x01000000 /* 16 MB */ - -#define DDB_LCS1_BASE 0x1d000000 /* misc */ -#define DDB_LCS1_SIZE 0x01000000 /* 16 MB */ - -#define DDB_LCS2_BASE 0x1e000000 /* Mezzanine */ -#define DDB_LCS2_SIZE 0x01000000 /* 16 MB */ - -#define DDB_VRC5477_BASE 0x1fa00000 /* VRC5477 control regs */ -#define DDB_VRC5477_SIZE 0x00200000 /* 2MB */ - -#define DDB_BOOTCS_BASE 0x1fc00000 /* Boot ROM / EPROM /Flash */ -#define DDB_BOOTCS_SIZE 0x00200000 /* 2 MB - doc says 4MB */ - -#define DDB_LED DDB_LCS1_BASE + 0x10000 - - -/* - * DDB5477 specific functions - */ -#ifndef __ASSEMBLY__ -extern void ddb5477_irq_setup(void); - -/* route irq to cpu int pin */ -extern void ll_vrc5477_irq_route(int vrc5477_irq, int ip); - -/* low-level routine for enabling vrc5477 irq, bypassing high-level */ -extern void ll_vrc5477_irq_enable(int vrc5477_irq); -extern void ll_vrc5477_irq_disable(int vrc5477_irq); -#endif /* !__ASSEMBLY__ */ - -/* PCI intr ack share PCIW0 with PCI IO */ -#define DDB_PCI_IACK_BASE DDB_PCI_IO_BASE - -/* - * Interrupt mapping - * - * We have three interrupt controllers: - * - * . CPU itself - 8 sources - * . i8259 - 16 sources - * . vrc5477 - 32 sources - * - * They connected as follows: - * all vrc5477 interrupts are routed to cpu IP2 (by software setting) - * all i8359 are routed to INTC in vrc5477 (by hardware connection) - * - * All VRC5477 PCI interrupts are level-triggered (no ack needed). - * All PCI irq but INTC are active low. - */ - -/* - * irq number block assignment - */ - -#define NUM_CPU_IRQ 8 -#define NUM_VRC5477_IRQ 32 - -#define CPU_IRQ_BASE MIPS_CPU_IRQ_BASE -#define VRC5477_IRQ_BASE (CPU_IRQ_BASE + NUM_CPU_IRQ) - -/* - * vrc5477 irq defs - */ - -#define VRC5477_IRQ_CPCE (0 + VRC5477_IRQ_BASE) /* cpu parity error */ -#define VRC5477_IRQ_CNTD (1 + VRC5477_IRQ_BASE) /* cpu no target */ -#define VRC5477_IRQ_I2C (2 + VRC5477_IRQ_BASE) /* I2C */ -#define VRC5477_IRQ_DMA (3 + VRC5477_IRQ_BASE) /* DMA */ -#define VRC5477_IRQ_UART0 (4 + VRC5477_IRQ_BASE) -#define VRC5477_IRQ_WDOG (5 + VRC5477_IRQ_BASE) /* watchdog timer */ -#define VRC5477_IRQ_SPT1 (6 + VRC5477_IRQ_BASE) /* special purpose timer 1 */ -#define VRC5477_IRQ_LBRT (7 + VRC5477_IRQ_BASE) /* local bus read timeout */ -#define VRC5477_IRQ_INTA (8 + VRC5477_IRQ_BASE) /* PCI INT #A */ -#define VRC5477_IRQ_INTB (9 + VRC5477_IRQ_BASE) /* PCI INT #B */ -#define VRC5477_IRQ_INTC (10 + VRC5477_IRQ_BASE) /* PCI INT #C */ -#define VRC5477_IRQ_INTD (11 + VRC5477_IRQ_BASE) /* PCI INT #D */ -#define VRC5477_IRQ_INTE (12 + VRC5477_IRQ_BASE) /* PCI INT #E */ -#define VRC5477_IRQ_RESERVED_13 (13 + VRC5477_IRQ_BASE) /* reserved */ -#define VRC5477_IRQ_PCIS (14 + VRC5477_IRQ_BASE) /* PCI SERR # */ -#define VRC5477_IRQ_PCI (15 + VRC5477_IRQ_BASE) /* PCI internal error */ -#define VRC5477_IRQ_IOPCI_INTA (16 + VRC5477_IRQ_BASE) /* USB-H */ -#define VRC5477_IRQ_IOPCI_INTB (17 + VRC5477_IRQ_BASE) /* USB-P */ -#define VRC5477_IRQ_IOPCI_INTC (18 + VRC5477_IRQ_BASE) /* AC97 */ -#define VRC5477_IRQ_IOPCI_INTD (19 + VRC5477_IRQ_BASE) /* Reserved */ -#define VRC5477_IRQ_UART1 (20 + VRC5477_IRQ_BASE) -#define VRC5477_IRQ_SPT0 (21 + VRC5477_IRQ_BASE) /* special purpose timer 0 */ -#define VRC5477_IRQ_GPT0 (22 + VRC5477_IRQ_BASE) /* general purpose timer 0 */ -#define VRC5477_IRQ_GPT1 (23 + VRC5477_IRQ_BASE) /* general purpose timer 1 */ -#define VRC5477_IRQ_GPT2 (24 + VRC5477_IRQ_BASE) /* general purpose timer 2 */ -#define VRC5477_IRQ_GPT3 (25 + VRC5477_IRQ_BASE) /* general purpose timer 3 */ -#define VRC5477_IRQ_GPIO (26 + VRC5477_IRQ_BASE) -#define VRC5477_IRQ_SIO0 (27 + VRC5477_IRQ_BASE) -#define VRC5477_IRQ_SIO1 (28 + VRC5477_IRQ_BASE) -#define VRC5477_IRQ_RESERVED_29 (29 + VRC5477_IRQ_BASE) /* reserved */ -#define VRC5477_IRQ_IOPCISERR (30 + VRC5477_IRQ_BASE) /* IO PCI SERR # */ -#define VRC5477_IRQ_IOPCI (31 + VRC5477_IRQ_BASE) - -/* - * i2859 irq assignment - */ -#define I8259_IRQ_RESERVED_0 (0 + I8259A_IRQ_BASE) -#define I8259_IRQ_KEYBOARD (1 + I8259A_IRQ_BASE) /* M1543 default */ -#define I8259_IRQ_CASCADE (2 + I8259A_IRQ_BASE) -#define I8259_IRQ_UART_B (3 + I8259A_IRQ_BASE) /* M1543 default, may conflict with RTC according to schematic diagram */ -#define I8259_IRQ_UART_A (4 + I8259A_IRQ_BASE) /* M1543 default */ -#define I8259_IRQ_PARALLEL (5 + I8259A_IRQ_BASE) /* M1543 default */ -#define I8259_IRQ_RESERVED_6 (6 + I8259A_IRQ_BASE) -#define I8259_IRQ_RESERVED_7 (7 + I8259A_IRQ_BASE) -#define I8259_IRQ_RTC (8 + I8259A_IRQ_BASE) /* who set this? */ -#define I8259_IRQ_USB (9 + I8259A_IRQ_BASE) /* ddb_setup */ -#define I8259_IRQ_PMU (10 + I8259A_IRQ_BASE) /* ddb_setup */ -#define I8259_IRQ_RESERVED_11 (11 + I8259A_IRQ_BASE) -#define I8259_IRQ_RESERVED_12 (12 + I8259A_IRQ_BASE) /* m1543_irq_setup */ -#define I8259_IRQ_RESERVED_13 (13 + I8259A_IRQ_BASE) -#define I8259_IRQ_HDC1 (14 + I8259A_IRQ_BASE) /* default and ddb_setup */ -#define I8259_IRQ_HDC2 (15 + I8259A_IRQ_BASE) /* default */ - - -/* - * misc - */ -#define VRC5477_I8259_CASCADE (VRC5477_IRQ_INTC - VRC5477_IRQ_BASE) -#define CPU_VRC5477_CASCADE 2 - -/* - * debug routines - */ -#ifndef __ASSEMBLY__ -#if defined(CONFIG_RUNTIME_DEBUG) -extern void vrc5477_show_pdar_regs(void); -extern void vrc5477_show_pci_regs(void); -extern void vrc5477_show_bar_regs(void); -extern void vrc5477_show_int_regs(void); -extern void vrc5477_show_all_regs(void); -#endif - -/* - * RAM size - */ -extern int board_ram_size; -#endif /* !__ASSEMBLY__ */ - -#endif /* __ASM_DDB5XXX_DDB5477_H */ diff --git a/include/asm-mips/ddb5xxx/ddb5xxx.h b/include/asm-mips/ddb5xxx/ddb5xxx.h deleted file mode 100644 index e97fcc8d548b..000000000000 --- a/include/asm-mips/ddb5xxx/ddb5xxx.h +++ /dev/null @@ -1,263 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com> - * Sony Software Development Center Europe (SDCE), Brussels - * - * include/asm-mips/ddb5xxx/ddb5xxx.h - * Common header for all NEC DDB 5xxx boards, including 5074, 5476, 5477. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#ifndef __ASM_DDB5XXX_DDB5XXX_H -#define __ASM_DDB5XXX_DDB5XXX_H - -#include <linux/types.h> - -/* - * This file is based on the following documentation: - * - * NEC Vrc 5074 System Controller Data Sheet, June 1998 - * - * [jsun] It is modified so that this file only contains the macros - * that are true for all DDB 5xxx boards. The modification is based on - * - * uPD31577(VRC5477) VR5432-SDRAM/PCI Bridge (Luke) - * Preliminary Specification Decoment, Rev 1.1, 27 Dec, 2000 - * - */ - - -#define DDB_BASE 0xbfa00000 -#define DDB_SIZE 0x00200000 /* 2 MB */ - - -/* - * Physical Device Address Registers (PDARs) - */ - -#define DDB_SDRAM0 0x0000 /* SDRAM Bank 0 [R/W] */ -#define DDB_SDRAM1 0x0008 /* SDRAM Bank 1 [R/W] */ -#define DDB_DCS2 0x0010 /* Device Chip-Select 2 [R/W] */ -#define DDB_DCS3 0x0018 /* Device Chip-Select 3 [R/W] */ -#define DDB_DCS4 0x0020 /* Device Chip-Select 4 [R/W] */ -#define DDB_DCS5 0x0028 /* Device Chip-Select 5 [R/W] */ -#define DDB_DCS6 0x0030 /* Device Chip-Select 6 [R/W] */ -#define DDB_DCS7 0x0038 /* Device Chip-Select 7 [R/W] */ -#define DDB_DCS8 0x0040 /* Device Chip-Select 8 [R/W] */ -#define DDB_PCIW0 0x0060 /* PCI Address Window 0 [R/W] */ -#define DDB_PCIW1 0x0068 /* PCI Address Window 1 [R/W] */ -#define DDB_INTCS 0x0070 /* Controller Internal Registers and Devices */ - /* [R/W] */ -#define DDB_BOOTCS 0x0078 /* Boot ROM Chip-Select [R/W] */ -/* Vrc5477 has two more, IOPCIW0, IOPCIW1 */ - -/* - * CPU Interface Registers - */ -#define DDB_CPUSTAT 0x0080 /* CPU Status [R/W] */ -#define DDB_INTCTRL 0x0088 /* Interrupt Control [R/W] */ -#define DDB_INTSTAT0 0x0090 /* Interrupt Status 0 [R] */ -#define DDB_INTSTAT1 0x0098 /* Interrupt Status 1 and CPU Interrupt */ - /* Enable [R/W] */ -#define DDB_INTCLR 0x00A0 /* Interrupt Clear [R/W] */ -#define DDB_INTPPES 0x00A8 /* PCI Interrupt Control [R/W] */ - - -/* - * Memory-Interface Registers - */ -#define DDB_MEMCTRL 0x00C0 /* Memory Control */ -#define DDB_ACSTIME 0x00C8 /* Memory Access Timing [R/W] */ -#define DDB_CHKERR 0x00D0 /* Memory Check Error Status [R] */ - - -/* - * PCI-Bus Registers - */ -#define DDB_PCICTRL 0x00E0 /* PCI Control [R/W] */ -#define DDB_PCIARB 0x00E8 /* PCI Arbiter [R/W] */ -#define DDB_PCIINIT0 0x00F0 /* PCI Master (Initiator) 0 [R/W] */ -#define DDB_PCIINIT1 0x00F8 /* PCI Master (Initiator) 1 [R/W] */ -#define DDB_PCIERR 0x00B8 /* PCI Error [R/W] */ - - -/* - * Local-Bus Registers - */ -#define DDB_LCNFG 0x0100 /* Local Bus Configuration [R/W] */ -#define DDB_LCST2 0x0110 /* Local Bus Chip-Select Timing 2 [R/W] */ -#define DDB_LCST3 0x0118 /* Local Bus Chip-Select Timing 3 [R/W] */ -#define DDB_LCST4 0x0120 /* Local Bus Chip-Select Timing 4 [R/W] */ -#define DDB_LCST5 0x0128 /* Local Bus Chip-Select Timing 5 [R/W] */ -#define DDB_LCST6 0x0130 /* Local Bus Chip-Select Timing 6 [R/W] */ -#define DDB_LCST7 0x0138 /* Local Bus Chip-Select Timing 7 [R/W] */ -#define DDB_LCST8 0x0140 /* Local Bus Chip-Select Timing 8 [R/W] */ -#define DDB_DCSFN 0x0150 /* Device Chip-Select Muxing and Output */ - /* Enables [R/W] */ -#define DDB_DCSIO 0x0158 /* Device Chip-Selects As I/O Bits [R/W] */ -#define DDB_BCST 0x0178 /* Local Boot Chip-Select Timing [R/W] */ - - -/* - * DMA Registers - */ -#define DDB_DMACTRL0 0x0180 /* DMA Control 0 [R/W] */ -#define DDB_DMASRCA0 0x0188 /* DMA Source Address 0 [R/W] */ -#define DDB_DMADESA0 0x0190 /* DMA Destination Address 0 [R/W] */ -#define DDB_DMACTRL1 0x0198 /* DMA Control 1 [R/W] */ -#define DDB_DMASRCA1 0x01A0 /* DMA Source Address 1 [R/W] */ -#define DDB_DMADESA1 0x01A8 /* DMA Destination Address 1 [R/W] */ - - -/* - * Timer Registers - */ -#define DDB_T0CTRL 0x01C0 /* SDRAM Refresh Control [R/W] */ -#define DDB_T0CNTR 0x01C8 /* SDRAM Refresh Counter [R/W] */ -#define DDB_T1CTRL 0x01D0 /* CPU-Bus Read Time-Out Control [R/W] */ -#define DDB_T1CNTR 0x01D8 /* CPU-Bus Read Time-Out Counter [R/W] */ -#define DDB_T2CTRL 0x01E0 /* General-Purpose Timer Control [R/W] */ -#define DDB_T2CNTR 0x01E8 /* General-Purpose Timer Counter [R/W] */ -#define DDB_T3CTRL 0x01F0 /* Watchdog Timer Control [R/W] */ -#define DDB_T3CNTR 0x01F8 /* Watchdog Timer Counter [R/W] */ - - -/* - * PCI Configuration Space Registers - */ -#define DDB_PCI_BASE 0x0200 - -#define DDB_VID 0x0200 /* PCI Vendor ID [R] */ -#define DDB_DID 0x0202 /* PCI Device ID [R] */ -#define DDB_PCICMD 0x0204 /* PCI Command [R/W] */ -#define DDB_PCISTS 0x0206 /* PCI Status [R/W] */ -#define DDB_REVID 0x0208 /* PCI Revision ID [R] */ -#define DDB_CLASS 0x0209 /* PCI Class Code [R] */ -#define DDB_CLSIZ 0x020C /* PCI Cache Line Size [R/W] */ -#define DDB_MLTIM 0x020D /* PCI Latency Timer [R/W] */ -#define DDB_HTYPE 0x020E /* PCI Header Type [R] */ -#define DDB_BIST 0x020F /* BIST [R] (unimplemented) */ -#define DDB_BARC 0x0210 /* PCI Base Address Register Control [R/W] */ -#define DDB_BAR0 0x0218 /* PCI Base Address Register 0 [R/W] */ -#define DDB_BAR1 0x0220 /* PCI Base Address Register 1 [R/W] */ -#define DDB_CIS 0x0228 /* PCI Cardbus CIS Pointer [R] */ - /* (unimplemented) */ -#define DDB_SSVID 0x022C /* PCI Sub-System Vendor ID [R/W] */ -#define DDB_SSID 0x022E /* PCI Sub-System ID [R/W] */ -#define DDB_ROM 0x0230 /* Expansion ROM Base Address [R] */ - /* (unimplemented) */ -#define DDB_INTLIN 0x023C /* PCI Interrupt Line [R/W] */ -#define DDB_INTPIN 0x023D /* PCI Interrupt Pin [R] */ -#define DDB_MINGNT 0x023E /* PCI Min_Gnt [R] (unimplemented) */ -#define DDB_MAXLAT 0x023F /* PCI Max_Lat [R] (unimplemented) */ -#define DDB_BAR2 0x0240 /* PCI Base Address Register 2 [R/W] */ -#define DDB_BAR3 0x0248 /* PCI Base Address Register 3 [R/W] */ -#define DDB_BAR4 0x0250 /* PCI Base Address Register 4 [R/W] */ -#define DDB_BAR5 0x0258 /* PCI Base Address Register 5 [R/W] */ -#define DDB_BAR6 0x0260 /* PCI Base Address Register 6 [R/W] */ -#define DDB_BAR7 0x0268 /* PCI Base Address Register 7 [R/W] */ -#define DDB_BAR8 0x0270 /* PCI Base Address Register 8 [R/W] */ -#define DDB_BARB 0x0278 /* PCI Base Address Register BOOT [R/W] */ - - -/* - * Nile 4 Register Access - */ - -static inline void ddb_sync(void) -{ - volatile u32 *p = (volatile u32 *)0xbfc00000; - (void)(*p); -} - -static inline void ddb_out32(u32 offset, u32 val) -{ - *(volatile u32 *)(DDB_BASE+offset) = val; - ddb_sync(); -} - -static inline u32 ddb_in32(u32 offset) -{ - u32 val = *(volatile u32 *)(DDB_BASE+offset); - ddb_sync(); - return val; -} - -static inline void ddb_out16(u32 offset, u16 val) -{ - *(volatile u16 *)(DDB_BASE+offset) = val; - ddb_sync(); -} - -static inline u16 ddb_in16(u32 offset) -{ - u16 val = *(volatile u16 *)(DDB_BASE+offset); - ddb_sync(); - return val; -} - -static inline void ddb_out8(u32 offset, u8 val) -{ - *(volatile u8 *)(DDB_BASE+offset) = val; - ddb_sync(); -} - -static inline u8 ddb_in8(u32 offset) -{ - u8 val = *(volatile u8 *)(DDB_BASE+offset); - ddb_sync(); - return val; -} - - -/* - * Physical Device Address Registers - */ - -extern u32 -ddb_calc_pdar(u32 phys, u32 size, int width, int on_memory_bus, int pci_visible); -extern void -ddb_set_pdar(u32 pdar, u32 phys, u32 size, int width, - int on_memory_bus, int pci_visible); - -/* - * PCI Master Registers - */ - -#define DDB_PCICMD_IACK 0 /* PCI Interrupt Acknowledge */ -#define DDB_PCICMD_IO 1 /* PCI I/O Space */ -#define DDB_PCICMD_MEM 3 /* PCI Memory Space */ -#define DDB_PCICMD_CFG 5 /* PCI Configuration Space */ - -/* - * additional options for pci init reg (no shifting needed) - */ -#define DDB_PCI_CFGTYPE1 0x200 /* for pci init0/1 regs */ -#define DDB_PCI_ACCESS_32 0x10 /* for pci init0/1 regs */ - - -extern void ddb_set_pmr(u32 pmr, u32 type, u32 addr, u32 options); - -/* - * we need to reset pci bus when we start up and shutdown - */ -extern void ddb_pci_reset_bus(void); - - -/* - * include the board dependent part - */ -#if defined(CONFIG_DDB5477) -#include <asm/ddb5xxx/ddb5477.h> -#else -#error "Unknown DDB board!" -#endif - -#endif /* __ASM_DDB5XXX_DDB5XXX_H */ diff --git a/include/asm-mips/elf.h b/include/asm-mips/elf.h index ebd6bfb19d66..e7d95d48177d 100644 --- a/include/asm-mips/elf.h +++ b/include/asm-mips/elf.h @@ -265,7 +265,7 @@ do { \ #ifdef CONFIG_MIPS32_N32 #define __SET_PERSONALITY32_N32() \ do { \ - current->thread.mflags |= MF_N32; \ + set_thread_flag(TIF_32BIT_ADDR); \ current->thread.abi = &mips_abi_n32; \ } while (0) #else @@ -276,7 +276,8 @@ do { \ #ifdef CONFIG_MIPS32_O32 #define __SET_PERSONALITY32_O32() \ do { \ - current->thread.mflags |= MF_O32; \ + set_thread_flag(TIF_32BIT_REGS); \ + set_thread_flag(TIF_32BIT_ADDR); \ current->thread.abi = &mips_abi_32; \ } while (0) #else @@ -299,13 +300,13 @@ do { \ #define SET_PERSONALITY(ex, ibcs2) \ do { \ - current->thread.mflags &= ~MF_ABI_MASK; \ + clear_thread_flag(TIF_32BIT_REGS); \ + clear_thread_flag(TIF_32BIT_ADDR); \ + \ if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \ __SET_PERSONALITY32(ex); \ - else { \ - current->thread.mflags |= MF_N64; \ + else \ current->thread.abi = &mips_abi; \ - } \ \ if (ibcs2) \ set_personality(PER_SVR4); \ diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h index d9119f43f9aa..918a4894b587 100644 --- a/include/asm-mips/hazards.h +++ b/include/asm-mips/hazards.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2003, 2004 Ralf Baechle <ralf@linux-mips.org> + * Copyright (C) 2003, 04, 07 Ralf Baechle <ralf@linux-mips.org> * Copyright (C) MIPS Technologies, Inc. * written by Ralf Baechle <ralf@linux-mips.org> */ @@ -23,6 +23,11 @@ static inline void name(void) \ __asm__ __volatile__ (#name); \ } +/* + * MIPS R2 instruction hazard barrier. Needs to be called as a subroutine. + */ +extern void mips_ihb(void); + #endif ASMMACRO(_ssnop, diff --git a/include/asm-mips/mach-tx49xx/cpu-feature-overrides.h b/include/asm-mips/mach-tx49xx/cpu-feature-overrides.h new file mode 100644 index 000000000000..275eaf92c748 --- /dev/null +++ b/include/asm-mips/mach-tx49xx/cpu-feature-overrides.h @@ -0,0 +1,23 @@ +#ifndef __ASM_MACH_TX49XX_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_TX49XX_CPU_FEATURE_OVERRIDES_H + +#define cpu_has_llsc 1 +#define cpu_has_64bits 1 +#define cpu_has_inclusive_pcaches 0 + +#define cpu_has_mips16 0 +#define cpu_has_mdmx 0 +#define cpu_has_mips3d 0 +#define cpu_has_smartmips 0 +#define cpu_has_vtag_icache 0 +#define cpu_has_ic_fills_f_dc 0 +#define cpu_has_dsp 0 +#define cpu_has_mipsmt 0 +#define cpu_has_userlocal 0 + +#define cpu_has_mips32r1 0 +#define cpu_has_mips32r2 0 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 + +#endif /* __ASM_MACH_TX49XX_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mach-tx49xx/kmalloc.h b/include/asm-mips/mach-tx49xx/kmalloc.h new file mode 100644 index 000000000000..913ff196259d --- /dev/null +++ b/include/asm-mips/mach-tx49xx/kmalloc.h @@ -0,0 +1,8 @@ +#ifndef __ASM_MACH_TX49XX_KMALLOC_H +#define __ASM_MACH_TX49XX_KMALLOC_H + +/* + * All happy, no need to define ARCH_KMALLOC_MINALIGN + */ + +#endif /* __ASM_MACH_TX49XX_KMALLOC_H */ diff --git a/include/asm-mips/mips-boards/generic.h b/include/asm-mips/mips-boards/generic.h index c8ebcc3e1267..d58977483534 100644 --- a/include/asm-mips/mips-boards/generic.h +++ b/include/asm-mips/mips-boards/generic.h @@ -67,6 +67,7 @@ #define MIPS_REVISION_CORID_CORE_FPGAR2 8 #define MIPS_REVISION_CORID_CORE_FPGA3 9 #define MIPS_REVISION_CORID_CORE_24K 10 +#define MIPS_REVISION_CORID_CORE_FPGA4 11 /**** Artificial corid defines ****/ /* diff --git a/include/asm-mips/mips_mt.h b/include/asm-mips/mips_mt.h index 8045abc78d0f..ac7935203f89 100644 --- a/include/asm-mips/mips_mt.h +++ b/include/asm-mips/mips_mt.h @@ -8,6 +8,12 @@ #include <linux/cpumask.h> +/* + * How many VPEs and TCs is Linux allowed to use? 0 means no limit. + */ +extern int tclimit; +extern int vpelimit; + extern cpumask_t mt_fpu_cpumask; extern unsigned long mt_fpemul_threshold; diff --git a/include/asm-mips/pmon.h b/include/asm-mips/pmon.h index 260f3448ccf1..6ad519189ce2 100644 --- a/include/asm-mips/pmon.h +++ b/include/asm-mips/pmon.h @@ -22,7 +22,7 @@ struct callvectors { char* (*gets) (char*); union { int (*smpfork) (unsigned long cp, char *sp); - int (*cpustart) (long, long, long, long); + int (*cpustart) (long, void (*)(void), void *, long); } _s; int (*semlock) (int sem); void (*semunlock) (int sem); diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h index 1d8b9a8ae324..83bc94534084 100644 --- a/include/asm-mips/processor.h +++ b/include/asm-mips/processor.h @@ -62,8 +62,9 @@ extern unsigned int vced_count, vcei_count; * This decides where the kernel will search for a free chunk of vm * space during mmap's. */ -#define TASK_UNMAPPED_BASE ((current->thread.mflags & MF_32BIT_ADDR) ? \ - PAGE_ALIGN(TASK_SIZE32 / 3) : PAGE_ALIGN(TASK_SIZE / 3)) +#define TASK_UNMAPPED_BASE \ + (test_thread_flag(TIF_32BIT_ADDR) ? \ + PAGE_ALIGN(TASK_SIZE32 / 3) : PAGE_ALIGN(TASK_SIZE / 3)) #endif #define NUM_FPU_REGS 32 @@ -132,22 +133,11 @@ struct thread_struct { unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */ unsigned long error_code; unsigned long trap_no; -#define MF_FIXADE 1 /* Fix address errors in software */ -#define MF_LOGADE 2 /* Log address errors to syslog */ -#define MF_32BIT_REGS 4 /* also implies 16/32 fprs */ -#define MF_32BIT_ADDR 8 /* 32-bit address space (o32/n32) */ -#define MF_FPUBOUND 0x10 /* thread bound to FPU-full CPU set */ - unsigned long mflags; unsigned long irix_trampoline; /* Wheee... */ unsigned long irix_oldctx; struct mips_abi *abi; }; -#define MF_ABI_MASK (MF_32BIT_REGS | MF_32BIT_ADDR) -#define MF_O32 (MF_32BIT_REGS | MF_32BIT_ADDR) -#define MF_N32 MF_32BIT_ADDR -#define MF_N64 0 - #ifdef CONFIG_MIPS_MT_FPAFF #define FPAFF_INIT \ .emulated_fp = 0, \ @@ -200,10 +190,6 @@ struct thread_struct { .cp0_baduaddr = 0, \ .error_code = 0, \ .trap_no = 0, \ - /* \ - * For now the default is to fix address errors \ - */ \ - .mflags = MF_FIXADE, \ .irix_trampoline = 0, \ .irix_oldctx = 0, \ } diff --git a/include/asm-mips/seccomp.h b/include/asm-mips/seccomp.h new file mode 100644 index 000000000000..36ed44070256 --- /dev/null +++ b/include/asm-mips/seccomp.h @@ -0,0 +1,37 @@ +#ifndef __ASM_SECCOMP_H + +#include <linux/thread_info.h> +#include <linux/unistd.h> + +#define __NR_seccomp_read __NR_read +#define __NR_seccomp_write __NR_write +#define __NR_seccomp_exit __NR_exit +#define __NR_seccomp_sigreturn __NR_rt_sigreturn + +/* + * Kludge alert: + * + * The generic seccomp code currently allows only a single compat ABI. Until + * this is fixed we priorize O32 as the compat ABI over N32. + */ +#ifdef CONFIG_MIPS32_O32 + +#define TIF_32BIT TIF_32BIT_REGS + +#define __NR_seccomp_read_32 4003 +#define __NR_seccomp_write_32 4004 +#define __NR_seccomp_exit_32 4001 +#define __NR_seccomp_sigreturn_32 4193 /* rt_sigreturn */ + +#elif defined(CONFIG_MIPS32_N32) + +#define TIF_32BIT _TIF_32BIT_ADDR + +#define __NR_seccomp_read_32 6000 +#define __NR_seccomp_write_32 6001 +#define __NR_seccomp_exit_32 6058 +#define __NR_seccomp_sigreturn_32 6211 /* rt_sigreturn */ + +#endif /* CONFIG_MIPS32_O32 */ + +#endif /* __ASM_SECCOMP_H */ diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h index 8d0b1cd4a45e..357251f42518 100644 --- a/include/asm-mips/system.h +++ b/include/asm-mips/system.h @@ -46,10 +46,12 @@ struct task_struct; #define __mips_mt_fpaff_switch_to(prev) \ do { \ + struct thread_info *__prev_ti = task_thread_info(prev); \ + \ if (cpu_has_fpu && \ - (prev->thread.mflags & MF_FPUBOUND) && \ - (!(KSTK_STATUS(prev) & ST0_CU1))) { \ - prev->thread.mflags &= ~MF_FPUBOUND; \ + test_ti_thread_flag(__prev_ti, TIF_FPUBOUND) && \ + (!(KSTK_STATUS(prev) & ST0_CU1))) { \ + clear_ti_thread_flag(__prev_ti, TIF_FPUBOUND); \ prev->cpus_allowed = prev->thread.user_cpus_allowed; \ } \ next->thread.emulated_fp = 0; \ diff --git a/include/asm-mips/thread_info.h b/include/asm-mips/thread_info.h index 645e7e2a5665..b2772df1a1bd 100644 --- a/include/asm-mips/thread_info.h +++ b/include/asm-mips/thread_info.h @@ -46,7 +46,7 @@ struct thread_info { { \ .task = &tsk, \ .exec_domain = &default_exec_domain, \ - .flags = 0, \ + .flags = _TIF_FIXADE, \ .cpu = 0, \ .preempt_count = 1, \ .addr_limit = KERNEL_DS, \ @@ -87,9 +87,8 @@ register struct thread_info *__current_thread_info __asm__("$28"); ({ \ struct thread_info *ret; \ \ - ret = kmalloc(THREAD_SIZE, GFP_KERNEL); \ - if (ret) \ - memset(ret, 0, THREAD_SIZE); \ + ret = kzalloc(THREAD_SIZE, GFP_KERNEL); \ + \ ret; \ }) #else @@ -118,6 +117,11 @@ register struct thread_info *__current_thread_info __asm__("$28"); #define TIF_POLLING_NRFLAG 17 /* true if poll_idle() is polling TIF_NEED_RESCHED */ #define TIF_MEMDIE 18 #define TIF_FREEZE 19 +#define TIF_FIXADE 20 /* Fix address errors in software */ +#define TIF_LOGADE 21 /* Log address errors to syslog */ +#define TIF_32BIT_REGS 22 /* also implies 16/32 fprs */ +#define TIF_32BIT_ADDR 23 /* 32-bit address space (o32/n32) */ +#define TIF_FPUBOUND 24 /* thread bound to FPU-full CPU set */ #define TIF_SYSCALL_TRACE 31 /* syscall trace active */ #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) @@ -129,6 +133,11 @@ register struct thread_info *__current_thread_info __asm__("$28"); #define _TIF_USEDFPU (1<<TIF_USEDFPU) #define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) #define _TIF_FREEZE (1<<TIF_FREEZE) +#define _TIF_FIXADE (1<<TIF_FIXADE) +#define _TIF_LOGADE (1<<TIF_LOGADE) +#define _TIF_32BIT_REGS (1<<TIF_32BIT_REGS) +#define _TIF_32BIT_ADDR (1<<TIF_32BIT_ADDR) +#define _TIF_FPUBOUND (1<<TIF_FPUBOUND) /* work to do on interrupt/exception return */ #define _TIF_WORK_MASK (0x0000ffef & ~_TIF_SECCOMP) diff --git a/include/asm-mips/tx4927/toshiba_rbtx4927.h b/include/asm-mips/tx4927/toshiba_rbtx4927.h index 94bef03d9635..5dc40a867774 100644 --- a/include/asm-mips/tx4927/toshiba_rbtx4927.h +++ b/include/asm-mips/tx4927/toshiba_rbtx4927.h @@ -52,4 +52,6 @@ #define RBTX4927_RTL_8019_BASE (0x1c020280-TBTX4927_ISA_IO_OFFSET) #define RBTX4927_RTL_8019_IRQ (29) +int toshiba_rbtx4927_irq_nested(int sw_irq); + #endif /* __ASM_TX4927_TOSHIBA_RBTX4927_H */ diff --git a/include/asm-mips/unistd.h b/include/asm-mips/unistd.h index ed16de0a6398..fa9a587b3bf1 100644 --- a/include/asm-mips/unistd.h +++ b/include/asm-mips/unistd.h @@ -340,16 +340,17 @@ #define __NR_signalfd (__NR_Linux + 317) #define __NR_timerfd (__NR_Linux + 318) #define __NR_eventfd (__NR_Linux + 319) +#define __NR_fallocate (__NR_Linux + 320) /* * Offset of the last Linux o32 flavoured syscall */ -#define __NR_Linux_syscalls 319 +#define __NR_Linux_syscalls 320 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ #define __NR_O32_Linux 4000 -#define __NR_O32_Linux_syscalls 319 +#define __NR_O32_Linux_syscalls 320 #if _MIPS_SIM == _MIPS_SIM_ABI64 @@ -636,16 +637,17 @@ #define __NR_signalfd (__NR_Linux + 276) #define __NR_timerfd (__NR_Linux + 277) #define __NR_eventfd (__NR_Linux + 278) +#define __NR_fallocate (__NR_Linux + 279) /* * Offset of the last Linux 64-bit flavoured syscall */ -#define __NR_Linux_syscalls 278 +#define __NR_Linux_syscalls 279 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ #define __NR_64_Linux 5000 -#define __NR_64_Linux_syscalls 278 +#define __NR_64_Linux_syscalls 279 #if _MIPS_SIM == _MIPS_SIM_NABI32 @@ -936,16 +938,17 @@ #define __NR_signalfd (__NR_Linux + 280) #define __NR_timerfd (__NR_Linux + 281) #define __NR_eventfd (__NR_Linux + 282) +#define __NR_fallocate (__NR_Linux + 283) /* * Offset of the last N32 flavoured syscall */ -#define __NR_Linux_syscalls 282 +#define __NR_Linux_syscalls 283 #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ #define __NR_N32_Linux 6000 -#define __NR_N32_Linux_syscalls 282 +#define __NR_N32_Linux_syscalls 283 #ifdef __KERNEL__ diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h index 2883ccc69ed0..c0715d0a6b28 100644 --- a/include/asm-mips/war.h +++ b/include/asm-mips/war.h @@ -182,9 +182,8 @@ * exceptions. */ #if defined(CONFIG_BASLER_EXCITE) || defined(CONFIG_MIPS_ATLAS) || \ - defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MOMENCO_OCELOT) || \ - defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_SGI_IP32) || \ - defined(CONFIG_WR_PPMC) + defined(CONFIG_MIPS_MALTA) || defined(CONFIG_PMC_YOSEMITE) || \ + defined(CONFIG_SGI_IP32) || defined(CONFIG_WR_PPMC) #define ICACHE_REFILLS_WORKAROUND_WAR 1 #endif |