diff options
Diffstat (limited to 'Documentation/devicetree/bindings/memory-controllers')
17 files changed, 1032 insertions, 192 deletions
diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml new file mode 100644 index 000000000000..25ed0266f6dd --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml @@ -0,0 +1,223 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LPDDR2 SDRAM compliant to JEDEC JESD209-2 + +maintainers: + - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> + +properties: + compatible: + oneOf: + - items: + - enum: + - elpida,ECB240ABACN + - elpida,B8132B2PB-6D-F + - enum: + - jedec,lpddr2-s4 + - items: + - enum: + - jedec,lpddr2-s2 + - items: + - enum: + - jedec,lpddr2-nvm + + revision-id1: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 255 + description: | + Revision 1 value of SDRAM chip. Obtained from device datasheet. + + revision-id2: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 255 + description: | + Revision 2 value of SDRAM chip. Obtained from device datasheet. + + density: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Density in megabits of SDRAM chip. Obtained from device datasheet. + enum: + - 64 + - 128 + - 256 + - 512 + - 1024 + - 2048 + - 4096 + - 8192 + - 16384 + - 32768 + + io-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + IO bus width in bits of SDRAM chip. Obtained from device datasheet. + enum: + - 32 + - 16 + - 8 + + tRRD-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 16 + description: | + Active bank a to active bank b in terms of number of clock cycles. + Obtained from device datasheet. + + tWTR-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 16 + description: | + Internal WRITE-to-READ command delay in terms of number of clock cycles. + Obtained from device datasheet. + + tXP-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 16 + description: | + Exit power-down to next valid command delay in terms of number of clock + cycles. Obtained from device datasheet. + + tRTP-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 16 + description: | + Internal READ to PRECHARGE command delay in terms of number of clock + cycles. Obtained from device datasheet. + + tCKE-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 16 + description: | + CKE minimum pulse width (HIGH and LOW pulse width) in terms of number + of clock cycles. Obtained from device datasheet. + + tRPab-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 16 + description: | + Row precharge time (all banks) in terms of number of clock cycles. + Obtained from device datasheet. + + tRCD-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 16 + description: | + RAS-to-CAS delay in terms of number of clock cycles. Obtained from + device datasheet. + + tWR-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 16 + description: | + WRITE recovery time in terms of number of clock cycles. Obtained from + device datasheet. + + tRASmin-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 16 + description: | + Row active time in terms of number of clock cycles. Obtained from device + datasheet. + + tCKESR-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 16 + description: | + CKE minimum pulse width during SELF REFRESH (low pulse width during + SELF REFRESH) in terms of number of clock cycles. Obtained from device + datasheet. + + tFAW-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 16 + description: | + Four-bank activate window in terms of number of clock cycles. Obtained + from device datasheet. + +patternProperties: + "^lpddr2-timings": + type: object + description: | + The lpddr2 node may have one or more child nodes of type "lpddr2-timings". + "lpddr2-timings" provides AC timing parameters of the device for + a given speed-bin. The user may provide the timings for as many + speed-bins as is required. Please see Documentation/devicetree/ + bindings/memory-controllers/ddr/lpddr2-timings.txt for more information + on "lpddr2-timings". + +required: + - compatible + - density + - io-width + +additionalProperties: false + +examples: + - | + elpida_ECB240ABACN: lpddr2 { + compatible = "elpida,ECB240ABACN", "jedec,lpddr2-s4"; + density = <2048>; + io-width = <32>; + revision-id1 = <1>; + revision-id2 = <0>; + + tRPab-min-tck = <3>; + tRCD-min-tck = <3>; + tWR-min-tck = <3>; + tRASmin-min-tck = <3>; + tRRD-min-tck = <2>; + tWTR-min-tck = <2>; + tXP-min-tck = <2>; + tRTP-min-tck = <2>; + tCKE-min-tck = <3>; + tCKESR-min-tck = <3>; + tFAW-min-tck = <8>; + + timings_elpida_ECB240ABACN_400mhz: lpddr2-timings0 { + compatible = "jedec,lpddr2-timings"; + min-freq = <10000000>; + max-freq = <400000000>; + tRPab = <21000>; + tRCD = <18000>; + tWR = <15000>; + tRAS-min = <42000>; + tRRD = <10000>; + tWTR = <7500>; + tXP = <7500>; + tRTP = <7500>; + tCKESR = <15000>; + tDQSCK-max = <5500>; + tFAW = <50000>; + tZQCS = <90000>; + tZQCL = <360000>; + tZQinit = <1000000>; + tRAS-max-ns = <70000>; + }; + + timings_elpida_ECB240ABACN_200mhz: lpddr2-timings1 { + compatible = "jedec,lpddr2-timings"; + min-freq = <10000000>; + max-freq = <200000000>; + tRPab = <21000>; + tRCD = <18000>; + tWR = <15000>; + tRAS-min = <42000>; + tRRD = <10000>; + tWTR = <10000>; + tXP = <7500>; + tRTP = <7500>; + tCKESR = <15000>; + tDQSCK-max = <5500>; + tFAW = <50000>; + tZQCS = <90000>; + tZQCL = <360000>; + tZQinit = <1000000>; + tRAS-max-ns = <70000>; + }; + }; diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr2-timings.txt b/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr2-timings.txt new file mode 100644 index 000000000000..9ceb19e0c7fd --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr2-timings.txt @@ -0,0 +1,52 @@ +* AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin + +Required properties: +- compatible : Should be "jedec,lpddr2-timings" +- min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32> +- max-freq : maximum DDR clock frequency for the speed-bin. Type is <u32> + +Optional properties: + +The following properties represent AC timing parameters from the memory +data-sheet of the device for a given speed-bin. All these properties are +of type <u32> and the default unit is ps (pico seconds). Parameters with +a different unit have a suffix indicating the unit such as 'tRAS-max-ns' +- tRCD +- tWR +- tRAS-min +- tRRD +- tWTR +- tXP +- tRTP +- tDQSCK-max +- tFAW +- tZQCS +- tZQinit +- tRPab +- tZQCL +- tCKESR +- tRAS-max-ns +- tDQSCK-max-derated + +Example: + +timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 { + compatible = "jedec,lpddr2-timings"; + min-freq = <10000000>; + max-freq = <400000000>; + tRPab = <21000>; + tRCD = <18000>; + tWR = <15000>; + tRAS-min = <42000>; + tRRD = <10000>; + tWTR = <7500>; + tXP = <7500>; + tRTP = <7500>; + tCKESR = <15000>; + tDQSCK-max = <5500>; + tFAW = <50000>; + tZQCS = <90000>; + tZQCL = <360000>; + tZQinit = <1000000>; + tRAS-max-ns = <70000>; +}; diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3-timings.txt b/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3-timings.txt new file mode 100644 index 000000000000..84705e50a3fd --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3-timings.txt @@ -0,0 +1,58 @@ +* AC timing parameters of LPDDR3 memories for a given speed-bin. + +The structures are based on LPDDR2 and extended where needed. + +Required properties: +- compatible : Should be "jedec,lpddr3-timings" +- min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32> +- reg : maximum DDR clock frequency for the speed-bin. Type is <u32> + +Optional properties: + +The following properties represent AC timing parameters from the memory +data-sheet of the device for a given speed-bin. All these properties are +of type <u32> and the default unit is ps (pico seconds). +- tRFC +- tRRD +- tRPab +- tRPpb +- tRCD +- tRC +- tRAS +- tWTR +- tWR +- tRTP +- tW2W-C2C +- tR2R-C2C +- tFAW +- tXSR +- tXP +- tCKE +- tCKESR +- tMRD + +Example: + +timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { + compatible = "jedec,lpddr3-timings"; + reg = <800000000>; /* workaround: it shows max-freq */ + min-freq = <100000000>; + tRFC = <65000>; + tRRD = <6000>; + tRPab = <12000>; + tRPpb = <12000>; + tRCD = <10000>; + tRC = <33750>; + tRAS = <23000>; + tWTR = <3750>; + tWR = <7500>; + tRTP = <3750>; + tW2W-C2C = <0>; + tR2R-C2C = <0>; + tFAW = <25000>; + tXSR = <70000>; + tXP = <3750>; + tCKE = <3750>; + tCKESR = <3750>; + tMRD = <7000>; +}; diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3.txt b/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3.txt new file mode 100644 index 000000000000..031af5fb0379 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3.txt @@ -0,0 +1,107 @@ +* LPDDR3 SDRAM memories compliant to JEDEC JESD209-3C + +Required properties: +- compatible : Should be "<vendor>,<type>", and generic value "jedec,lpddr3". + Example "<vendor>,<type>" values: + "samsung,K3QF2F20DB" + +- density : <u32> representing density in Mb (Mega bits) +- io-width : <u32> representing bus width. Possible values are 8, 16, 32, 64 +- #address-cells: Must be set to 1 +- #size-cells: Must be set to 0 + +Optional properties: + +- manufacturer-id : <u32> Manufacturer ID value read from Mode Register 5 +- revision-id : <u32 u32> Revision IDs read from Mode Registers 6 and 7 + +The following optional properties represent the minimum value of some AC +timing parameters of the DDR device in terms of number of clock cycles. +These values shall be obtained from the device data-sheet. +- tRFC-min-tck +- tRRD-min-tck +- tRPab-min-tck +- tRPpb-min-tck +- tRCD-min-tck +- tRC-min-tck +- tRAS-min-tck +- tWTR-min-tck +- tWR-min-tck +- tRTP-min-tck +- tW2W-C2C-min-tck +- tR2R-C2C-min-tck +- tWL-min-tck +- tDQSCK-min-tck +- tRL-min-tck +- tFAW-min-tck +- tXSR-min-tck +- tXP-min-tck +- tCKE-min-tck +- tCKESR-min-tck +- tMRD-min-tck + +Child nodes: +- The lpddr3 node may have one or more child nodes of type "lpddr3-timings". + "lpddr3-timings" provides AC timing parameters of the device for + a given speed-bin. Please see + Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3-timings.txt + for more information on "lpddr3-timings" + +Example: + +samsung_K3QF2F20DB: lpddr3 { + compatible = "samsung,K3QF2F20DB", "jedec,lpddr3"; + density = <16384>; + io-width = <32>; + manufacturer-id = <1>; + revision-id = <123 234>; + #address-cells = <1>; + #size-cells = <0>; + + tRFC-min-tck = <17>; + tRRD-min-tck = <2>; + tRPab-min-tck = <2>; + tRPpb-min-tck = <2>; + tRCD-min-tck = <3>; + tRC-min-tck = <6>; + tRAS-min-tck = <5>; + tWTR-min-tck = <2>; + tWR-min-tck = <7>; + tRTP-min-tck = <2>; + tW2W-C2C-min-tck = <0>; + tR2R-C2C-min-tck = <0>; + tWL-min-tck = <8>; + tDQSCK-min-tck = <5>; + tRL-min-tck = <14>; + tFAW-min-tck = <5>; + tXSR-min-tck = <12>; + tXP-min-tck = <2>; + tCKE-min-tck = <2>; + tCKESR-min-tck = <2>; + tMRD-min-tck = <5>; + + timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { + compatible = "jedec,lpddr3-timings"; + /* workaround: 'reg' shows max-freq */ + reg = <800000000>; + min-freq = <100000000>; + tRFC = <65000>; + tRRD = <6000>; + tRPab = <12000>; + tRPpb = <12000>; + tRCD = <10000>; + tRC = <33750>; + tRAS = <23000>; + tWTR = <3750>; + tWR = <7500>; + tRTP = <3750>; + tW2W-C2C = <0>; + tR2R-C2C = <0>; + tFAW = <25000>; + tXSR = <70000>; + tXP = <3750>; + tCKE = <3750>; + tCKESR = <3750>; + tMRD = <7000>; + }; +} diff --git a/Documentation/devicetree/bindings/memory-controllers/fsl/ddr.txt b/Documentation/devicetree/bindings/memory-controllers/fsl/ddr.txt deleted file mode 100644 index dde6d837083a..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/fsl/ddr.txt +++ /dev/null @@ -1,29 +0,0 @@ -Freescale DDR memory controller - -Properties: - -- compatible : Should include "fsl,chip-memory-controller" where - chip is the processor (bsc9132, mpc8572 etc.), or - "fsl,qoriq-memory-controller". -- reg : Address and size of DDR controller registers -- interrupts : Error interrupt of DDR controller -- little-endian : Specifies little-endian access to registers - If omitted, big-endian will be used. - -Example 1: - - memory-controller@2000 { - compatible = "fsl,bsc9132-memory-controller"; - reg = <0x2000 0x1000>; - interrupts = <16 2 1 8>; - }; - - -Example 2: - - ddr1: memory-controller@8000 { - compatible = "fsl,qoriq-memory-controller-v4.7", - "fsl,qoriq-memory-controller"; - reg = <0x8000 0x1000>; - interrupts = <16 2 1 23>; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/fsl/fsl,ddr.yaml b/Documentation/devicetree/bindings/memory-controllers/fsl/fsl,ddr.yaml new file mode 100644 index 000000000000..af5147f9da72 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/fsl/fsl,ddr.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,ddr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale DDR memory controller + +maintainers: + - Borislav Petkov <bp@alien8.de> + - York Sun <york.sun@nxp.com> + +properties: + $nodename: + pattern: "^memory-controller@[0-9a-f]+$" + + compatible: + oneOf: + - items: + - enum: + - fsl,qoriq-memory-controller-v4.4 + - fsl,qoriq-memory-controller-v4.5 + - fsl,qoriq-memory-controller-v4.7 + - fsl,qoriq-memory-controller-v5.0 + - const: fsl,qoriq-memory-controller + - enum: + - fsl,bsc9132-memory-controller + - fsl,8540-memory-controller + - fsl,8541-memory-controller + - fsl,8544-memory-controller + - fsl,8548-memory-controller + - fsl,8555-memory-controller + - fsl,8568-memory-controller + - fsl,mpc8536-memory-controller + - fsl,mpc8540-memory-controller + - fsl,mpc8541-memory-controller + - fsl,mpc8544-memory-controller + - fsl,mpc8548-memory-controller + - fsl,mpc8555-memory-controller + - fsl,mpc8560-memory-controller + - fsl,mpc8568-memory-controller + - fsl,mpc8569-memory-controller + - fsl,mpc8572-memory-controller + - fsl,mpc8349-memory-controller + - fsl,p1020-memory-controller + - fsl,p1021-memory-controller + - fsl,p2020-memory-controller + - fsl,qoriq-memory-controller + + interrupts: + maxItems: 1 + + little-endian: + description: + Specifies little-endian access to registers. If omitted, big-endian will + be used. + type: boolean + + reg: + maxItems: 1 + +required: + - compatible + - interrupts + - reg + +additionalProperties: false + +examples: + - | + memory-controller@2000 { + compatible = "fsl,bsc9132-memory-controller"; + reg = <0x2000 0x1000>; + interrupts = <16 2 1 8>; + }; + + - | + memory-controller@8000 { + compatible = "fsl,qoriq-memory-controller-v4.7", + "fsl,qoriq-memory-controller"; + reg = <0x8000 0x1000>; + interrupts = <16 2 1 23>; + }; diff --git a/Documentation/devicetree/bindings/memory-controllers/ingenic,nemc.yaml b/Documentation/devicetree/bindings/memory-controllers/ingenic,nemc.yaml index fe0ce191a851..24f9e1982028 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ingenic,nemc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ingenic,nemc.yaml @@ -84,7 +84,7 @@ additionalProperties: false examples: - | - #include <dt-bindings/clock/jz4780-cgu.h> + #include <dt-bindings/clock/ingenic,jz4780-cgu.h> #include <dt-bindings/gpio/gpio.h> nemc: memory-controller@13410000 { compatible = "ingenic,jz4780-nemc"; diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,mt7621-memc.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,mt7621-memc.yaml new file mode 100644 index 000000000000..85e02854f083 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,mt7621-memc.yaml @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/mediatek,mt7621-memc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MT7621 SDRAM controller + +maintainers: + - Sergio Paracuellos <sergio.paracuellos@gmail.com> + +properties: + compatible: + const: mediatek,mt7621-memc + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + memory-controller@5000 { + compatible = "mediatek,mt7621-memc"; + reg = <0x5000 0x1000>; + }; diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml index e87e4382807c..3a82b0b27fa0 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml @@ -16,7 +16,7 @@ description: | MediaTek SMI have two generations of HW architecture, here is the list which generation the SoCs use: generation 1: mt2701 and mt7623. - generation 2: mt2712, mt6779, mt8167, mt8173, mt8183 and mt8192. + generation 2: mt2712, mt6779, mt8167, mt8173, mt8183, mt8192 and mt8195. There's slight differences between the two SMI, for generation 2, the register which control the iommu port is at each larb's register base. But @@ -36,6 +36,9 @@ properties: - mediatek,mt8173-smi-common - mediatek,mt8183-smi-common - mediatek,mt8192-smi-common + - mediatek,mt8195-smi-common-vdo + - mediatek,mt8195-smi-common-vpp + - mediatek,mt8195-smi-sub-common - description: for mt7623 items: @@ -65,6 +68,10 @@ properties: minItems: 2 maxItems: 4 + mediatek,smi: + $ref: /schemas/types.yaml#/definitions/phandle + description: a phandle to the smi-common node above. Only for sub-common. + required: - compatible - reg @@ -91,6 +98,29 @@ allOf: - const: smi - const: async + - if: # only for sub common + properties: + compatible: + contains: + enum: + - mediatek,mt8195-smi-sub-common + then: + required: + - mediatek,smi + properties: + clock: + items: + minItems: 3 + maxItems: 3 + clock-names: + items: + - const: apb + - const: smi + - const: gals0 + else: + properties: + mediatek,smi: false + - if: # for gen2 HW that have gals properties: compatible: @@ -98,6 +128,8 @@ allOf: - mediatek,mt6779-smi-common - mediatek,mt8183-smi-common - mediatek,mt8192-smi-common + - mediatek,mt8195-smi-common-vdo + - mediatek,mt8195-smi-common-vpp then: properties: diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml index 2353f6cf3c80..eaeff1ada7f8 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml @@ -24,6 +24,7 @@ properties: - mediatek,mt8173-smi-larb - mediatek,mt8183-smi-larb - mediatek,mt8192-smi-larb + - mediatek,mt8195-smi-larb - description: for mt7623 items: @@ -74,6 +75,7 @@ allOf: compatible: enum: - mediatek,mt8183-smi-larb + - mediatek,mt8195-smi-larb then: properties: @@ -108,6 +110,7 @@ allOf: - mediatek,mt6779-smi-larb - mediatek,mt8167-smi-larb - mediatek,mt8192-smi-larb + - mediatek,mt8195-smi-larb then: required: diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml index cac6842dc8f1..2fa44951cfde 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml @@ -164,12 +164,20 @@ patternProperties: "#size-cells": const: 0 + lpddr2: + $ref: "ddr/jedec,lpddr2.yaml#" + type: object + patternProperties: "^emc-table@[0-9]+$": $ref: "#/$defs/emc-table" - required: - - nvidia,ram-code + oneOf: + - required: + - nvidia,ram-code + + - required: + - lpddr2 additionalProperties: false @@ -227,4 +235,15 @@ examples: 0x00000000 0x00000000 0x00000000 0x00000000>; }; }; + + emc-tables@1 { + reg = <1>; + + lpddr2 { + compatible = "elpida,B8132B2PB-6D-F", "jedec,lpddr2-s4"; + revision-id1 = <1>; + density = <2048>; + io-width = <16>; + }; + }; }; diff --git a/Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt b/Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt deleted file mode 100644 index c1359f4d48d7..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt +++ /dev/null @@ -1,157 +0,0 @@ -Device tree bindings for OMAP general purpose memory controllers (GPMC) - -The actual devices are instantiated from the child nodes of a GPMC node. - -Required properties: - - - compatible: Should be set to one of the following: - - ti,omap2420-gpmc (omap2420) - ti,omap2430-gpmc (omap2430) - ti,omap3430-gpmc (omap3430 & omap3630) - ti,omap4430-gpmc (omap4430 & omap4460 & omap543x) - ti,am3352-gpmc (am335x devices) - - - reg: A resource specifier for the register space - (see the example below) - - ti,hwmods: Should be set to "ti,gpmc" until the DT transition is - completed. - - #address-cells: Must be set to 2 to allow memory address translation - - #size-cells: Must be set to 1 to allow CS address passing - - gpmc,num-cs: The maximum number of chip-select lines that controller - can support. - - gpmc,num-waitpins: The maximum number of wait pins that controller can - support. - - ranges: Must be set up to reflect the memory layout with four - integer values for each chip-select line in use: - - <cs-number> 0 <physical address of mapping> <size> - - Currently, calculated values derived from the contents - of the per-CS register GPMC_CONFIG7 (as set up by the - bootloader) are used for the physical address decoding. - As this will change in the future, filling correct - values here is a requirement. - - interrupt-controller: The GPMC driver implements and interrupt controller for - the NAND events "fifoevent" and "termcount" plus the - rising/falling edges on the GPMC_WAIT pins. - The interrupt number mapping is as follows - 0 - NAND_fifoevent - 1 - NAND_termcount - 2 - GPMC_WAIT0 pin edge - 3 - GPMC_WAIT1 pin edge, and so on. - - interrupt-cells: Must be set to 2 - - gpio-controller: The GPMC driver implements a GPIO controller for the - GPMC WAIT pins that can be used as general purpose inputs. - 0 maps to GPMC_WAIT0 pin. - - gpio-cells: Must be set to 2 - -Required properties when using NAND prefetch dma: - - dmas GPMC NAND prefetch dma channel - - dma-names Must be set to "rxtx" - -Timing properties for child nodes. All are optional and default to 0. - - - gpmc,sync-clk-ps: Minimum clock period for synchronous mode, in picoseconds - - Chip-select signal timings (in nanoseconds) corresponding to GPMC_CONFIG2: - - gpmc,cs-on-ns: Assertion time - - gpmc,cs-rd-off-ns: Read deassertion time - - gpmc,cs-wr-off-ns: Write deassertion time - - ADV signal timings (in nanoseconds) corresponding to GPMC_CONFIG3: - - gpmc,adv-on-ns: Assertion time - - gpmc,adv-rd-off-ns: Read deassertion time - - gpmc,adv-wr-off-ns: Write deassertion time - - gpmc,adv-aad-mux-on-ns: Assertion time for AAD - - gpmc,adv-aad-mux-rd-off-ns: Read deassertion time for AAD - - gpmc,adv-aad-mux-wr-off-ns: Write deassertion time for AAD - - WE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4: - - gpmc,we-on-ns Assertion time - - gpmc,we-off-ns: Deassertion time - - OE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4: - - gpmc,oe-on-ns: Assertion time - - gpmc,oe-off-ns: Deassertion time - - gpmc,oe-aad-mux-on-ns: Assertion time for AAD - - gpmc,oe-aad-mux-off-ns: Deassertion time for AAD - - Access time and cycle time timings (in nanoseconds) corresponding to - GPMC_CONFIG5: - - gpmc,page-burst-access-ns: Multiple access word delay - - gpmc,access-ns: Start-cycle to first data valid delay - - gpmc,rd-cycle-ns: Total read cycle time - - gpmc,wr-cycle-ns: Total write cycle time - - gpmc,bus-turnaround-ns: Turn-around time between successive accesses - - gpmc,cycle2cycle-delay-ns: Delay between chip-select pulses - - gpmc,clk-activation-ns: GPMC clock activation time - - gpmc,wait-monitoring-ns: Start of wait monitoring with regard to valid - data - -Boolean timing parameters. If property is present parameter enabled and -disabled if omitted: - - gpmc,adv-extra-delay: ADV signal is delayed by half GPMC clock - - gpmc,cs-extra-delay: CS signal is delayed by half GPMC clock - - gpmc,cycle2cycle-diffcsen: Add "cycle2cycle-delay" between successive - accesses to a different CS - - gpmc,cycle2cycle-samecsen: Add "cycle2cycle-delay" between successive - accesses to the same CS - - gpmc,oe-extra-delay: OE signal is delayed by half GPMC clock - - gpmc,we-extra-delay: WE signal is delayed by half GPMC clock - - gpmc,time-para-granularity: Multiply all access times by 2 - -The following are only applicable to OMAP3+ and AM335x: - - gpmc,wr-access-ns: In synchronous write mode, for single or - burst accesses, defines the number of - GPMC_FCLK cycles from start access time - to the GPMC_CLK rising edge used by the - memory device for the first data capture. - - gpmc,wr-data-mux-bus-ns: In address-data multiplex mode, specifies - the time when the first data is driven on - the address-data bus. - -GPMC chip-select settings properties for child nodes. All are optional. - -- gpmc,burst-length Page/burst length. Must be 4, 8 or 16. -- gpmc,burst-wrap Enables wrap bursting -- gpmc,burst-read Enables read page/burst mode -- gpmc,burst-write Enables write page/burst mode -- gpmc,device-width Total width of device(s) connected to a GPMC - chip-select in bytes. The GPMC supports 8-bit - and 16-bit devices and so this property must be - 1 or 2. -- gpmc,mux-add-data Address and data multiplexing configuration. - Valid values are 1 for address-address-data - multiplexing mode and 2 for address-data - multiplexing mode. -- gpmc,sync-read Enables synchronous read. Defaults to asynchronous - is this is not set. -- gpmc,sync-write Enables synchronous writes. Defaults to asynchronous - is this is not set. -- gpmc,wait-pin Wait-pin used by client. Must be less than - "gpmc,num-waitpins". -- gpmc,wait-on-read Enables wait monitoring on reads. -- gpmc,wait-on-write Enables wait monitoring on writes. - -Example for an AM33xx board: - - gpmc: gpmc@50000000 { - compatible = "ti,am3352-gpmc"; - ti,hwmods = "gpmc"; - reg = <0x50000000 0x2000>; - interrupts = <100>; - dmas = <&edma 52 0>; - dma-names = "rxtx"; - gpmc,num-cs = <8>; - gpmc,num-waitpins = <2>; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */ - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - - /* child nodes go here */ - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml b/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml index d25072c414e4..9da80e8f2444 100644 --- a/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml @@ -33,6 +33,7 @@ properties: - renesas,r8a77970-rpc-if # R-Car V3M - renesas,r8a77980-rpc-if # R-Car V3H - renesas,r8a77995-rpc-if # R-Car D3 + - renesas,r8a779a0-rpc-if # R-Car V3U - const: renesas,rcar-gen3-rpc-if # a generic R-Car gen3 or RZ/G2 device reg: diff --git a/Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml b/Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml index 6f4fd5814bf4..fe8639dcffab 100644 --- a/Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml @@ -51,7 +51,8 @@ properties: $ref: '/schemas/types.yaml#/definitions/phandle' description: | phandle of the connected DRAM memory device. For more information please - refer to documentation file: Documentation/devicetree/bindings/ddr/lpddr3.txt + refer to documentation file: + Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3.txt operating-points-v2: true diff --git a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml index cba74205846a..6b516d3895af 100644 --- a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml @@ -19,7 +19,7 @@ description: | Select. The FMC2 performs only one access at a time to an external device. maintainers: - - Christophe Kerello <christophe.kerello@st.com> + - Christophe Kerello <christophe.kerello@foss.st.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/memory-controllers/ti,gpmc-child.yaml b/Documentation/devicetree/bindings/memory-controllers/ti,gpmc-child.yaml new file mode 100644 index 000000000000..6e3995bb1630 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ti,gpmc-child.yaml @@ -0,0 +1,245 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: device tree bindings for children of the Texas Instruments GPMC + +maintainers: + - Tony Lindgren <tony@atomide.com> + - Roger Quadros <rogerq@kernel.org> + +description: + This binding is meant for the child nodes of the GPMC node. The node + represents any device connected to the GPMC bus. It may be a Flash chip, + RAM chip or Ethernet controller, etc. These properties are meant for + configuring the GPMC settings/timings and will accompany the bindings + supported by the respective device. + +properties: + reg: true + +# GPMC Timing properties for child nodes. All are optional and default to 0. + gpmc,sync-clk-ps: + description: Minimum clock period for synchronous mode + default: 0 + +# Chip-select signal timings corresponding to GPMC_CONFIG2: + gpmc,cs-on-ns: + description: Assertion time + default: 0 + + gpmc,cs-rd-off-ns: + description: Read deassertion time + default: 0 + + gpmc,cs-wr-off-ns: + description: Write deassertion time + default: 0 + +# ADV signal timings corresponding to GPMC_CONFIG3: + gpmc,adv-on-ns: + description: Assertion time + default: 0 + + gpmc,adv-rd-off-ns: + description: Read deassertion time + default: 0 + + gpmc,adv-wr-off-ns: + description: Write deassertion time + default: 0 + + gpmc,adv-aad-mux-on-ns: + description: Assertion time for AAD + default: 0 + + gpmc,adv-aad-mux-rd-off-ns: + description: Read deassertion time for AAD + default: 0 + + gpmc,adv-aad-mux-wr-off-ns: + description: Write deassertion time for AAD + default: 0 + +# WE signals timings corresponding to GPMC_CONFIG4: + gpmc,we-on-ns: + description: Assertion time + default: 0 + + gpmc,we-off-ns: + description: Deassertion time + default: 0 + +# OE signals timings corresponding to GPMC_CONFIG4: + gpmc,oe-on-ns: + description: Assertion time + default: 0 + + gpmc,oe-off-ns: + description: Deassertion time + default: 0 + + gpmc,oe-aad-mux-on-ns: + description: Assertion time for AAD + default: 0 + + gpmc,oe-aad-mux-off-ns: + description: Deassertion time for AAD + default: 0 + +# Access time and cycle time timings (in nanoseconds) corresponding to +# GPMC_CONFIG5: + gpmc,page-burst-access-ns: + description: Multiple access word delay + default: 0 + + gpmc,access-ns: + description: Start-cycle to first data valid delay + default: 0 + + gpmc,rd-cycle-ns: + description: Total read cycle time + default: 0 + + gpmc,wr-cycle-ns: + description: Total write cycle time + default: 0 + + gpmc,bus-turnaround-ns: + description: Turn-around time between successive accesses + default: 0 + + gpmc,cycle2cycle-delay-ns: + description: Delay between chip-select pulses + default: 0 + + gpmc,clk-activation-ns: + description: GPMC clock activation time + default: 0 + + gpmc,wait-monitoring-ns: + description: Start of wait monitoring with regard to valid data + default: 0 + +# Boolean timing parameters. If property is present, parameter is enabled +# otherwise disabled. + gpmc,adv-extra-delay: + description: ADV signal is delayed by half GPMC clock + type: boolean + + gpmc,cs-extra-delay: + description: CS signal is delayed by half GPMC clock + type: boolean + + gpmc,cycle2cycle-diffcsen: + description: | + Add "cycle2cycle-delay" between successive accesses + to a different CS + type: boolean + + gpmc,cycle2cycle-samecsen: + description: | + Add "cycle2cycle-delay" between successive accesses + to the same CS + type: boolean + + gpmc,oe-extra-delay: + description: OE signal is delayed by half GPMC clock + type: boolean + + gpmc,we-extra-delay: + description: WE signal is delayed by half GPMC clock + type: boolean + + gpmc,time-para-granularity: + description: Multiply all access times by 2 + type: boolean + +# The following two properties are applicable only to OMAP3+ and AM335x: + gpmc,wr-access-ns: + description: | + In synchronous write mode, for single or + burst accesses, defines the number of + GPMC_FCLK cycles from start access time + to the GPMC_CLK rising edge used by the + memory device for the first data capture. + default: 0 + + gpmc,wr-data-mux-bus-ns: + description: | + In address-data multiplex mode, specifies + the time when the first data is driven on + the address-data bus. + default: 0 + +# GPMC chip-select settings properties for child nodes. All are optional. + gpmc,burst-length: + description: Page/burst length. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 4, 8, 16] + default: 0 + + gpmc,burst-wrap: + description: Enables wrap bursting + type: boolean + + gpmc,burst-read: + description: Enables read page/burst mode + type: boolean + + gpmc,burst-write: + description: Enables write page/burst mode + type: boolean + + gpmc,device-width: + description: | + Total width of device(s) connected to a GPMC + chip-select in bytes. The GPMC supports 8-bit + and 16-bit devices and so this property must be + 1 or 2. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2] + default: 1 + + gpmc,mux-add-data: + description: | + Address and data multiplexing configuration. + Valid values are + 0 for Non multiplexed mode + 1 for address-address-data multiplexing mode and + 2 for address-data multiplexing mode. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + + gpmc,sync-read: + description: | + Enables synchronous read. Defaults to asynchronous + is this is not set. + type: boolean + + gpmc,sync-write: + description: | + Enables synchronous writes. Defaults to asynchronous + is this is not set. + type: boolean + + gpmc,wait-pin: + description: | + Wait-pin used by client. Must be less than "gpmc,num-waitpins". + $ref: /schemas/types.yaml#/definitions/uint32 + + gpmc,wait-on-read: + description: Enables wait monitoring on reads. + type: boolean + + gpmc,wait-on-write: + description: Enables wait monitoring on writes. + type: boolean + +required: + - reg + +# the GPMC child will have its own native properties +additionalProperties: true diff --git a/Documentation/devicetree/bindings/memory-controllers/ti,gpmc.yaml b/Documentation/devicetree/bindings/memory-controllers/ti,gpmc.yaml new file mode 100644 index 000000000000..25b42d68f9b3 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ti,gpmc.yaml @@ -0,0 +1,172 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/ti,gpmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments GPMC Memory Controller device-tree bindings + +maintainers: + - Tony Lindgren <tony@atomide.com> + - Roger Quadros <rogerq@kernel.org> + +description: + The GPMC is a unified memory controller dedicated for interfacing + with external memory devices like + - Asynchronous SRAM-like memories and ASICs + - Asynchronous, synchronous, and page mode burst NOR flash + - NAND flash + - Pseudo-SRAM devices + +properties: + compatible: + items: + - enum: + - ti,am3352-gpmc + - ti,omap2420-gpmc + - ti,omap2430-gpmc + - ti,omap3430-gpmc + - ti,omap4430-gpmc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + description: | + Functional clock. Used for bus timing calculations and + GPMC configuration. + + clock-names: + items: + - const: fck + + dmas: + items: + - description: DMA channel for GPMC NAND prefetch + + dma-names: + items: + - const: rxtx + + "#address-cells": true + + "#size-cells": true + + gpmc,num-cs: + description: maximum number of supported chip-select lines. + $ref: /schemas/types.yaml#/definitions/uint32 + + gpmc,num-waitpins: + description: maximum number of supported wait pins. + $ref: /schemas/types.yaml#/definitions/uint32 + + ranges: + minItems: 1 + description: | + Must be set up to reflect the memory layout with four + integer values for each chip-select line in use, + <cs-number> 0 <physical address of mapping> <size> + items: + - description: NAND bank 0 + - description: NOR/SRAM bank 0 + - description: NOR/SRAM bank 1 + + '#interrupt-cells': + const: 2 + + interrupt-controller: + description: | + The GPMC driver implements and interrupt controller for + the NAND events "fifoevent" and "termcount" plus the + rising/falling edges on the GPMC_WAIT pins. + The interrupt number mapping is as follows + 0 - NAND_fifoevent + 1 - NAND_termcount + 2 - GPMC_WAIT0 pin edge + 3 - GPMC_WAIT1 pin edge, and so on. + + '#gpio-cells': + const: 2 + + gpio-controller: + description: | + The GPMC driver implements a GPIO controller for the + GPMC WAIT pins that can be used as general purpose inputs. + 0 maps to GPMC_WAIT0 pin. + + ti,hwmods: + description: + Name of the HWMOD associated with GPMC. This is for legacy + omap2/3 platforms only. + $ref: /schemas/types.yaml#/definitions/string + deprecated: true + + ti,no-idle-on-init: + description: + Prevent idling the module at init. This is for legacy omap2/3 + platforms only. + type: boolean + deprecated: true + +patternProperties: + "@[0-7],[a-f0-9]+$": + type: object + description: | + The child device node represents the device connected to the GPMC + bus. The device can be a NAND chip, SRAM device, NOR device + or an ASIC. + + allOf: + - $ref: "ti,gpmc-child.yaml" + + unevaluatedProperties: false + +required: + - compatible + - reg + - gpmc,num-cs + - gpmc,num-waitpins + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/gpio/gpio.h> + + gpmc: memory-controller@50000000 { + compatible = "ti,am3352-gpmc"; + reg = <0x50000000 0x2000>; + interrupts = <100>; + clocks = <&l3s_clkctrl>; + clock-names = "fck"; + dmas = <&edma 52 0>; + dma-names = "rxtx"; + gpmc,num-cs = <8>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */ + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + ti,nand-xfer-type = "prefetch-dma"; + ti,nand-ecc-opt = "bch16"; + ti,elm-id = <&elm>; + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ + }; + }; |