aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts/exynos5260.dtsi
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/boot/dts/exynos5260.dtsi')
-rw-r--r--arch/arm/boot/dts/exynos5260.dtsi181
1 files changed, 167 insertions, 14 deletions
diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi
index 154df70128f3..ff1ee409eff3 100644
--- a/arch/arm/boot/dts/exynos5260.dtsi
+++ b/arch/arm/boot/dts/exynos5260.dtsi
@@ -34,42 +34,68 @@
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu2>;
+ };
+ core1 {
+ cpu = <&cpu3>;
+ };
+ core2 {
+ cpu = <&cpu4>;
+ };
+ core3 {
+ cpu = <&cpu5>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x0>;
cci-control-port = <&cci_control1>;
};
- cpu@1 {
+ cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x1>;
cci-control-port = <&cci_control1>;
};
- cpu@100 {
+ cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x100>;
cci-control-port = <&cci_control0>;
};
- cpu@101 {
+ cpu3: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x101>;
cci-control-port = <&cci_control0>;
};
- cpu@102 {
+ cpu4: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x102>;
cci-control-port = <&cci_control0>;
};
- cpu@103 {
+ cpu5: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x103>;
@@ -87,85 +113,211 @@
compatible = "samsung,exynos5260-clock-top";
reg = <0x10010000 0x10000>;
#clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&clock_mif MIF_DOUT_MEM_PLL>,
+ <&clock_mif MIF_DOUT_BUS_PLL>,
+ <&clock_mif MIF_DOUT_MEDIA_PLL>;
+ clock-names = "fin_pll",
+ "dout_mem_pll",
+ "dout_bus_pll",
+ "dout_media_pll";
};
clock_peri: clock-controller@10200000 {
compatible = "samsung,exynos5260-clock-peri";
reg = <0x10200000 0x10000>;
#clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&ioclk_pcm>,
+ <&ioclk_i2s>,
+ <&ioclk_spdif>,
+ <&fin_pll>,
+ <&clock_top TOP_DOUT_ACLK_PERI_66>,
+ <&clock_top TOP_DOUT_SCLK_PERI_UART0>,
+ <&clock_top TOP_DOUT_SCLK_PERI_UART1>,
+ <&clock_top TOP_DOUT_SCLK_PERI_UART2>,
+ <&clock_top TOP_DOUT_SCLK_PERI_SPI0_B>,
+ <&clock_top TOP_DOUT_SCLK_PERI_SPI1_B>,
+ <&clock_top TOP_DOUT_SCLK_PERI_SPI2_B>,
+ <&clock_top TOP_DOUT_ACLK_PERI_AUD>;
+ clock-names = "fin_pll",
+ "ioclk_pcm_extclk",
+ "ioclk_i2s_cdclk",
+ "ioclk_spdif_extclk",
+ "phyclk_hdmi_phy_ref_cko",
+ "dout_aclk_peri_66",
+ "dout_sclk_peri_uart0",
+ "dout_sclk_peri_uart1",
+ "dout_sclk_peri_uart2",
+ "dout_sclk_peri_spi0_b",
+ "dout_sclk_peri_spi1_b",
+ "dout_sclk_peri_spi2_b",
+ "dout_aclk_peri_aud";
};
clock_egl: clock-controller@10600000 {
compatible = "samsung,exynos5260-clock-egl";
reg = <0x10600000 0x10000>;
#clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&clock_mif MIF_DOUT_BUS_PLL>;
+ clock-names = "fin_pll",
+ "dout_bus_pll";
};
clock_kfc: clock-controller@10700000 {
compatible = "samsung,exynos5260-clock-kfc";
reg = <0x10700000 0x10000>;
#clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&clock_mif MIF_DOUT_MEDIA_PLL>;
+ clock-names = "fin_pll",
+ "dout_media_pll";
};
clock_g2d: clock-controller@10a00000 {
compatible = "samsung,exynos5260-clock-g2d";
reg = <0x10A00000 0x10000>;
#clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&clock_top TOP_DOUT_ACLK_G2D_333>;
+ clock-names = "fin_pll",
+ "dout_aclk_g2d_333";
};
clock_mif: clock-controller@10ce0000 {
compatible = "samsung,exynos5260-clock-mif";
reg = <0x10CE0000 0x10000>;
#clock-cells = <1>;
+ clocks = <&fin_pll>;
+ clock-names = "fin_pll";
};
clock_mfc: clock-controller@11090000 {
compatible = "samsung,exynos5260-clock-mfc";
reg = <0x11090000 0x10000>;
#clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&clock_top TOP_DOUT_ACLK_MFC_333>;
+ clock-names = "fin_pll",
+ "dout_aclk_mfc_333";
};
clock_g3d: clock-controller@11830000 {
compatible = "samsung,exynos5260-clock-g3d";
reg = <0x11830000 0x10000>;
#clock-cells = <1>;
+ clocks = <&fin_pll>;
+ clock-names = "fin_pll";
};
clock_fsys: clock-controller@122e0000 {
compatible = "samsung,exynos5260-clock-fsys";
reg = <0x122E0000 0x10000>;
#clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&clock_top TOP_DOUT_ACLK_FSYS_200>;
+ clock-names = "fin_pll",
+ "phyclk_usbhost20_phy_phyclock",
+ "phyclk_usbhost20_phy_freeclk",
+ "phyclk_usbhost20_phy_clk48mohci",
+ "phyclk_usbdrd30_udrd30_pipe_pclk",
+ "phyclk_usbdrd30_udrd30_phyclock",
+ "dout_aclk_fsys_200";
};
clock_aud: clock-controller@128c0000 {
compatible = "samsung,exynos5260-clock-aud";
reg = <0x128C0000 0x10000>;
#clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&clock_top TOP_FOUT_AUD_PLL>,
+ <&ioclk_i2s>,
+ <&ioclk_pcm>;
+ clock-names = "fin_pll",
+ "fout_aud_pll",
+ "ioclk_i2s_cdclk",
+ "ioclk_pcm_extclk";
};
clock_isp: clock-controller@133c0000 {
compatible = "samsung,exynos5260-clock-isp";
reg = <0x133C0000 0x10000>;
#clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&clock_top TOP_DOUT_ACLK_ISP1_266>,
+ <&clock_top TOP_DOUT_ACLK_ISP1_400>,
+ <&clock_top TOP_MOUT_ACLK_ISP1_266>;
+ clock-names = "fin_pll",
+ "dout_aclk_isp1_266",
+ "dout_aclk_isp1_400",
+ "mout_aclk_isp1_266";
};
clock_gscl: clock-controller@13f00000 {
compatible = "samsung,exynos5260-clock-gscl";
reg = <0x13F00000 0x10000>;
#clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&clock_top TOP_DOUT_ACLK_GSCL_400>,
+ <&clock_top TOP_DOUT_ACLK_GSCL_333>;
+ clock-names = "fin_pll",
+ "dout_aclk_gscl_400",
+ "dout_aclk_gscl_333";
};
clock_disp: clock-controller@14550000 {
compatible = "samsung,exynos5260-clock-disp";
reg = <0x14550000 0x10000>;
#clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&ioclk_spdif>,
+ <&clock_top TOP_DOUT_ACLK_PERI_AUD>,
+ <&clock_top TOP_DOUT_ACLK_DISP_222>,
+ <&clock_top TOP_DOUT_SCLK_DISP_PIXEL>,
+ <&clock_top TOP_DOUT_ACLK_DISP_333>;
+ clock-names = "fin_pll",
+ "phyclk_dptx_phy_ch3_txd_clk",
+ "phyclk_dptx_phy_ch2_txd_clk",
+ "phyclk_dptx_phy_ch1_txd_clk",
+ "phyclk_dptx_phy_ch0_txd_clk",
+ "phyclk_hdmi_phy_tmds_clko",
+ "phyclk_hdmi_phy_ref_clko",
+ "phyclk_hdmi_phy_pixel_clko",
+ "phyclk_hdmi_link_o_tmds_clkhi",
+ "phyclk_mipi_dphy_4l_m_txbyte_clkhs",
+ "phyclk_dptx_phy_o_ref_clk_24m",
+ "phyclk_dptx_phy_clk_div2",
+ "phyclk_mipi_dphy_4l_m_rxclkesc0",
+ "phyclk_hdmi_phy_ref_cko",
+ "ioclk_spdif_extclk",
+ "dout_aclk_peri_aud",
+ "dout_aclk_disp_222",
+ "dout_sclk_disp_pixel",
+ "dout_aclk_disp_333";
};
gic: interrupt-controller@10481000 {
- compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+ compatible = "arm,gic-400", "arm,cortex-a15-gic";
#interrupt-cells = <3>;
- #address-cells = <0>;
- #size-cells = <0>;
interrupt-controller;
reg = <0x10481000 0x1000>,
<0x10482000 0x2000>,
@@ -181,7 +333,8 @@
};
mct: timer@100b0000 {
- compatible = "samsung,exynos4210-mct";
+ compatible = "samsung,exynos5260-mct",
+ "samsung,exynos4210-mct";
reg = <0x100B0000 0x1000>;
clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>;
clock-names = "fin_pll", "mct";
@@ -344,7 +497,7 @@
status = "disabled";
};
- hsi2c_0: hsi2c@12da0000 {
+ hsi2c_0: i2c@12da0000 {
compatible = "samsung,exynos5260-hsi2c";
reg = <0x12DA0000 0x1000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
@@ -357,7 +510,7 @@
status = "disabled";
};
- hsi2c_1: hsi2c@12db0000 {
+ hsi2c_1: i2c@12db0000 {
compatible = "samsung,exynos5260-hsi2c";
reg = <0x12DB0000 0x1000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
@@ -370,7 +523,7 @@
status = "disabled";
};
- hsi2c_2: hsi2c@12dc0000 {
+ hsi2c_2: i2c@12dc0000 {
compatible = "samsung,exynos5260-hsi2c";
reg = <0x12DC0000 0x1000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
@@ -383,7 +536,7 @@
status = "disabled";
};
- hsi2c_3: hsi2c@12dd0000 {
+ hsi2c_3: i2c@12dd0000 {
compatible = "samsung,exynos5260-hsi2c";
reg = <0x12DD0000 0x1000>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.