diff options
Diffstat (limited to 'arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi | 34 |
1 files changed, 29 insertions, 5 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi index 4d18952658f8..28a805384668 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi @@ -78,17 +78,21 @@ }; &i2c3 { - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; clock-frequency = <400000>; status = "okay"; eeprom@50 { - compatible = "atmel,24c32"; + compatible = "st,24c32", "atmel,24c32"; + pagesize = <32>; reg = <0x50>; }; - pmic@58 { + pmic: pmic@58 { compatible = "dlg,da9062"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmic>; @@ -96,6 +100,8 @@ interrupt-parent = <&gpio1>; interrupts = <2 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; + gpio-controller; + #gpio-cells = <2>; da9062_rtc: rtc { compatible = "dlg,da9062-rtc"; @@ -107,12 +113,23 @@ watchdog { compatible = "dlg,da9062-watchdog"; + dlg,use-sw-pm; + }; + + thermal { + compatible = "dlg,da9062-thermal"; + status = "disabled"; + }; + + gpio { + compatible = "dlg,da9062-gpio"; + status = "disabled"; }; regulators { vdd_arm: buck1 { regulator-name = "vdd_arm"; - regulator-min-microvolt = <730000>; + regulator-min-microvolt = <925000>; regulator-max-microvolt = <1380000>; regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>; regulator-always-on; @@ -120,7 +137,7 @@ vdd_soc: buck2 { regulator-name = "vdd_soc"; - regulator-min-microvolt = <730000>; + regulator-min-microvolt = <1150000>; regulator-max-microvolt = <1380000>; regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>; regulator-always-on; @@ -255,6 +272,13 @@ >; }; + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1 + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 + >; + }; + pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 |