diff options
Diffstat (limited to 'arch/arm/boot/dts/qcom-ipq8064.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/qcom-ipq8064.dtsi | 1025 |
1 files changed, 864 insertions, 161 deletions
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 16c0da97932c..90c08b51680a 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -2,6 +2,8 @@ /dts-v1/; #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/mfd/qcom-rpm.h> +#include <dt-bindings/clock/qcom,rpmcc.h> #include <dt-bindings/clock/qcom,gcc-ipq806x.h> #include <dt-bindings/clock/qcom,lcc-ipq806x.h> #include <dt-bindings/gpio/gpio.h> @@ -20,7 +22,7 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v1"; device_type = "cpu"; @@ -30,7 +32,7 @@ qcom,saw = <&saw0>; }; - cpu@1 { + cpu1: cpu@1 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v1"; device_type = "cpu"; @@ -46,6 +48,228 @@ }; }; + thermal-zones { + sensor0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 0>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + sensor1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 1>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + sensor2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 2>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + sensor3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 3>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + sensor4-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 4>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + sensor5-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 5>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + sensor6-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 6>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + sensor7-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 7>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + sensor8-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 8>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + sensor9-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 9>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + sensor10-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 10>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + }; + memory { device_type = "memory"; reg = <0x0 0x0>; @@ -67,20 +291,23 @@ no-map; }; - smem@41000000 { + smem: smem@41000000 { + compatible = "qcom,smem"; reg = <0x41000000 0x200000>; no-map; + + hwlocks = <&sfpb_mutex 3>; }; }; clocks { - cxo_board { + cxo_board: cxo_board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; }; - pxo_board { + pxo_board: pxo_board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; @@ -93,32 +320,79 @@ }; }; + firmware { + scm { + compatible = "qcom,scm-ipq806x", "qcom,scm"; + }; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; ranges; compatible = "simple-bus"; - lpass@28100000 { - compatible = "qcom,lpass-cpu"; - status = "disabled"; - clocks = <&lcc AHBIX_CLK>, - <&lcc MI2S_OSR_CLK>, - <&lcc MI2S_BIT_CLK>; - clock-names = "ahbix-clk", - "mi2s-osr-clk", - "mi2s-bit-clk"; - interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "lpass-irq-lpaif"; - reg = <0x28100000 0x10000>; - reg-names = "lpass-lpaif"; + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <7>; + snps,rd_osr_lmt = <7>; + snps,blen = <16 0 0 0 0 0 0>; + }; + + vsdcc_fixed: vsdcc-regulator { + compatible = "regulator-fixed"; + regulator-name = "SDCC Power"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + rpm: rpm@108000 { + compatible = "qcom,rpm-ipq8064"; + reg = <0x00108000 0x1000>; + qcom,ipc = <&l2cc 0x8 2>; + + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ack", "err", "wakeup"; + + clocks = <&gcc RPM_MSG_RAM_H_CLK>; + clock-names = "ram"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc"; + #clock-cells = <1>; + }; + }; + + qcom,ssbi@500000 { + compatible = "qcom,ssbi"; + reg = <0x00500000 0x1000>; + qcom,controller-type = "pmic-arbiter"; + }; + + qfprom: qfprom@700000 { + compatible = "qcom,ipq8064-qfprom", "qcom,qfprom"; + reg = <0x00700000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + speedbin_efuse: speedbin@c0 { + reg = <0xc0 0x4>; + }; + tsens_calib: calib@400 { + reg = <0x400 0xb>; + }; + tsens_calib_backup: calib_backup@410 { + reg = <0x410 0xb>; + }; }; qcom_pinmux: pinmux@800000 { compatible = "qcom,ipq8064-pinctrl"; - reg = <0x800000 0x4000>; + reg = <0x00800000 0x4000>; gpio-controller; + gpio-ranges = <&qcom_pinmux 0 0 69>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; @@ -151,6 +425,13 @@ }; }; + i2c4_pins: i2c4-default { + pins = "gpio12", "gpio13"; + function = "gsbi4"; + drive-strength = <12>; + bias-disable; + }; + spi_pins: spi_pins { mux { pins = "gpio18", "gpio19", "gpio21"; @@ -178,6 +459,85 @@ bias-pull-up; }; }; + + nand_pins: nand_pins { + mux { + pins = "gpio34", "gpio35", "gpio36", + "gpio37", "gpio38", "gpio39", + "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", + "gpio46", "gpio47"; + function = "nand"; + drive-strength = <10>; + bias-disable; + }; + + pullups { + pins = "gpio39"; + function = "nand"; + drive-strength = <10>; + bias-pull-up; + }; + + hold { + pins = "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", + "gpio46", "gpio47"; + function = "nand"; + drive-strength = <10>; + bias-bus-hold; + }; + }; + + mdio0_pins: mdio0-pins { + mux { + pins = "gpio0", "gpio1"; + function = "mdio"; + drive-strength = <8>; + bias-disable; + }; + }; + + rgmii2_pins: rgmii2-pins { + mux { + pins = "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio32", + "gpio51", "gpio52", "gpio59", + "gpio60", "gpio61", "gpio62"; + function = "rgmii2"; + drive-strength = <8>; + bias-disable; + }; + }; + }; + + gcc: clock-controller@900000 { + compatible = "qcom,gcc-ipq8064", "syscon"; + clocks = <&pxo_board>, <&cxo_board>; + clock-names = "pxo", "cxo"; + reg = <0x00900000 0x4000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + tsens: thermal-sensor@900000 { + compatible = "qcom,ipq8064-tsens"; + + nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; + nvmem-cell-names = "calib", "calib_backup"; + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow"; + + #qcom,sensors = <11>; + #thermal-sensor-cells = <1>; + }; + }; + + sfpb_mutex: hwlock@1200600 { + compatible = "qcom,sfpb-mutex"; + reg = <0x01200600 0x100>; + + #hwlock-cells = <1>; }; intc: interrupt-controller@2000000 { @@ -209,14 +569,17 @@ cpu-offset = <0x80000>; }; - acc0: clock-controller@2088000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + l2cc: clock-controller@2011000 { + compatible = "qcom,kpss-gcc", "syscon"; + reg = <0x02011000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu_l2_aux"; }; - acc1: clock-controller@2098000 { + acc0: clock-controller@2088000 { compatible = "qcom,kpss-acc-v1"; - reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + reg = <0x02088000 0x1000>, <0x02008000 0x1000>; }; saw0: regulator@2089000 { @@ -225,12 +588,219 @@ regulator; }; + acc1: clock-controller@2098000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + }; + saw1: regulator@2099000 { compatible = "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; regulator; }; + nss_common: syscon@03000000 { + compatible = "syscon"; + reg = <0x03000000 0x0000FFFF>; + }; + + usb3_0: usb3@100f8800 { + compatible = "qcom,ipq8064-dwc3", "qcom,dwc3"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x100f8800 0x8000>; + clocks = <&gcc USB30_0_MASTER_CLK>; + clock-names = "core"; + + ranges; + + resets = <&gcc USB30_0_MASTER_RESET>; + reset-names = "master"; + + status = "disabled"; + + dwc3_0: dwc3@10000000 { + compatible = "snps,dwc3"; + reg = <0x10000000 0xcd00>; + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; + phys = <&hs_phy_0>, <&ss_phy_0>; + phy-names = "usb2-phy", "usb3-phy"; + dr_mode = "host"; + snps,dis_u3_susphy_quirk; + }; + }; + + hs_phy_0: phy@100f8800 { + compatible = "qcom,ipq806x-usb-phy-hs"; + reg = <0x100f8800 0x30>; + clocks = <&gcc USB30_0_UTMI_CLK>; + clock-names = "ref"; + #phy-cells = <0>; + + status = "disabled"; + }; + + ss_phy_0: phy@100f8830 { + compatible = "qcom,ipq806x-usb-phy-ss"; + reg = <0x100f8830 0x30>; + clocks = <&gcc USB30_0_MASTER_CLK>; + clock-names = "ref"; + #phy-cells = <0>; + + status = "disabled"; + }; + + usb3_1: usb3@110f8800 { + compatible = "qcom,ipq8064-dwc3", "qcom,dwc3"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x110f8800 0x8000>; + clocks = <&gcc USB30_1_MASTER_CLK>; + clock-names = "core"; + + ranges; + + resets = <&gcc USB30_1_MASTER_RESET>; + reset-names = "master"; + + status = "disabled"; + + dwc3_1: dwc3@11000000 { + compatible = "snps,dwc3"; + reg = <0x11000000 0xcd00>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + phys = <&hs_phy_1>, <&ss_phy_1>; + phy-names = "usb2-phy", "usb3-phy"; + dr_mode = "host"; + snps,dis_u3_susphy_quirk; + }; + }; + + hs_phy_1: phy@110f8800 { + compatible = "qcom,ipq806x-usb-phy-hs"; + reg = <0x110f8800 0x30>; + clocks = <&gcc USB30_1_UTMI_CLK>; + clock-names = "ref"; + #phy-cells = <0>; + + status = "disabled"; + }; + + ss_phy_1: phy@110f8830 { + compatible = "qcom,ipq806x-usb-phy-ss"; + reg = <0x110f8830 0x30>; + clocks = <&gcc USB30_1_MASTER_CLK>; + clock-names = "ref"; + #phy-cells = <0>; + + status = "disabled"; + }; + + sdcc3bam: dma-controller@12182000 { + compatible = "qcom,bam-v1.3.0"; + reg = <0x12182000 0x8000>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc SDC3_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + sdcc1bam: dma-controller@12402000 { + compatible = "qcom,bam-v1.3.0"; + reg = <0x12402000 0x8000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc SDC1_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + amba: amba { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sdcc3: mmc@12180000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + status = "disabled"; + reg = <0x12180000 0x2000>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <192000000>; + sd-uhs-sdr104; + sd-uhs-ddr50; + vqmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; + dma-names = "tx", "rx"; + }; + + sdcc1: mmc@12400000 { + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + reg = <0x12400000 0x2000>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <96000000>; + non-removable; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + vmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; + dma-names = "tx", "rx"; + }; + }; + + gsbi1: gsbi@12440000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x12440000 0x100>; + cell-index = <1>; + clocks = <&gcc GSBI1_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + + status = "disabled"; + + gsbi1_serial: serial@12450000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x12450000 0x100>, + <0x12400000 0x03>; + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; + clock-names = "core", "iface"; + + status = "disabled"; + }; + + gsbi1_i2c: i2c@12460000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x12460000 0x1000>; + interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + gsbi2: gsbi@12480000 { compatible = "qcom,gsbi-v1.0.0"; cell-index = <2>; @@ -244,7 +814,7 @@ syscon-tcsr = <&tcsr>; - serial@12490000 { + gsbi2_serial: serial@12490000 { compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x12490000 0x1000>, <0x12480000 0x1000>; @@ -254,7 +824,7 @@ status = "disabled"; }; - i2c@124a0000 { + gsbi2_i2c: i2c@124a0000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x124a0000 0x1000>; interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; @@ -266,7 +836,6 @@ #address-cells = <1>; #size-cells = <0>; }; - }; gsbi4: gsbi@16300000 { @@ -306,53 +875,46 @@ }; }; - gsbi5: gsbi@1a200000 { + gsbi6: gsbi@16500000 { compatible = "qcom,gsbi-v1.0.0"; - cell-index = <5>; - reg = <0x1a200000 0x100>; - clocks = <&gcc GSBI5_H_CLK>; + reg = <0x16500000 0x100>; + cell-index = <6>; + clocks = <&gcc GSBI6_H_CLK>; clock-names = "iface"; #address-cells = <1>; #size-cells = <1>; ranges; - status = "disabled"; syscon-tcsr = <&tcsr>; - serial@1a240000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x1a240000 0x1000>, - <0x1a200000 0x1000>; - interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; + status = "disabled"; - i2c@1a280000 { + gsbi6_i2c: i2c@16580000 { compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x1a280000 0x1000>; - interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x16580000 0x1000>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; + clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; clock-names = "core", "iface"; - status = "disabled"; #address-cells = <1>; #size-cells = <0>; + + status = "disabled"; }; - spi@1a280000 { + gsbi6_spi: spi@16580000 { compatible = "qcom,spi-qup-v1.1.1"; - reg = <0x1a280000 0x1000>; - interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x16580000 0x1000>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; + clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; clock-names = "core", "iface"; - status = "disabled"; #address-cells = <1>; #size-cells = <0>; + + status = "disabled"; }; }; @@ -377,52 +939,91 @@ clock-names = "core", "iface"; status = "disabled"; }; + + gsbi7_i2c: i2c@16680000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x16680000 0x1000>; + interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>; + clock-names = "core", "iface"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; }; - sata_phy: sata-phy@1b400000 { - compatible = "qcom,ipq806x-sata-phy"; - reg = <0x1b400000 0x200>; + adm_dma: dma-controller@18300000 { + compatible = "qcom,adm"; + reg = <0x18300000 0x100000>; + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; - clocks = <&gcc SATA_PHY_CFG_CLK>; - clock-names = "cfg"; + clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>; + clock-names = "core", "iface"; + + resets = <&gcc ADM0_RESET>, + <&gcc ADM0_PBUS_RESET>, + <&gcc ADM0_C0_RESET>, + <&gcc ADM0_C1_RESET>, + <&gcc ADM0_C2_RESET>; + reset-names = "clk", "pbus", "c0", "c1", "c2"; + qcom,ee = <0>; - #phy-cells = <0>; status = "disabled"; }; - sata@29000000 { - compatible = "qcom,ipq806x-ahci", "generic-ahci"; - reg = <0x29000000 0x180>; + gsbi5: gsbi@1a200000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <5>; + reg = <0x1a200000 0x100>; + clocks = <&gcc GSBI5_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; - interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; + #size-cells = <1>; + ranges; + status = "disabled"; - clocks = <&gcc SFAB_SATA_S_H_CLK>, - <&gcc SATA_H_CLK>, - <&gcc SATA_A_CLK>, - <&gcc SATA_RXOOB_CLK>, - <&gcc SATA_PMALIVE_CLK>; - clock-names = "slave_face", "iface", "core", - "rxoob", "pmalive"; + syscon-tcsr = <&tcsr>; - assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>; - assigned-clock-rates = <100000000>, <100000000>; + gsbi5_serial: serial@1a240000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x1a240000 0x1000>, + <0x1a200000 0x1000>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; - phys = <&sata_phy>; - phy-names = "sata-phy"; - status = "disabled"; - }; + i2c@1a280000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x1a280000 0x1000>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; - qcom,ssbi@500000 { - compatible = "qcom,ssbi"; - reg = <0x00500000 0x1000>; - qcom,controller-type = "pmic-arbiter"; - }; + clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; - gcc: clock-controller@900000 { - compatible = "qcom,gcc-ipq8064"; - reg = <0x00900000 0x4000>; - #clock-cells = <1>; - #reset-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi@1a280000 { + compatible = "qcom,spi-qup-v1.1.1"; + reg = <0x1a280000 0x1000>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; }; tcsr: syscon@1a400000 { @@ -430,11 +1031,44 @@ reg = <0x1a400000 0x100>; }; - lcc: clock-controller@28000000 { - compatible = "qcom,lcc-ipq8064"; - reg = <0x28000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; + rng@1a500000 { + compatible = "qcom,prng"; + reg = <0x1a500000 0x200>; + clocks = <&gcc PRNG_CLK>; + clock-names = "core"; + }; + + nand: nand-controller@1ac00000 { + compatible = "qcom,ipq806x-nand"; + reg = <0x1ac00000 0x800>; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + clocks = <&gcc EBI2_CLK>, + <&gcc EBI2_AON_CLK>; + clock-names = "core", "aon"; + + dmas = <&adm_dma 3>; + dma-names = "rxtx"; + qcom,cmd-crci = <15>; + qcom,data-crci = <3>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + sata_phy: sata-phy@1b400000 { + compatible = "qcom,ipq806x-sata-phy"; + reg = <0x1b400000 0x200>; + + clocks = <&gcc SATA_PHY_CFG_CLK>; + clock-names = "cfg"; + + #phy-cells = <0>; + status = "disabled"; }; pcie0: pci@1b500000 { @@ -451,7 +1085,7 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */ + ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; @@ -485,7 +1119,7 @@ pinctrl-names = "default"; status = "disabled"; - perst-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; + perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; }; pcie1: pci@1b700000 { @@ -502,7 +1136,7 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */ + ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; @@ -536,7 +1170,7 @@ pinctrl-names = "default"; status = "disabled"; - perst-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; + perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; }; pcie2: pci@1b900000 { @@ -553,7 +1187,7 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */ + ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; @@ -587,83 +1221,152 @@ pinctrl-names = "default"; status = "disabled"; - perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>; + perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>; }; - vsdcc_fixed: vsdcc-regulator { - compatible = "regulator-fixed"; - regulator-name = "SDCC Power"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; + qsgmii_csr: syscon@1bb00000 { + compatible = "syscon"; + reg = <0x1bb00000 0x000001FF>; }; - sdcc1bam:dma@12402000 { - compatible = "qcom,bam-v1.3.0"; - reg = <0x12402000 0x8000>; - interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc SDC1_H_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; + lcc: clock-controller@28000000 { + compatible = "qcom,lcc-ipq8064"; + reg = <0x28000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; }; - sdcc3bam:dma@12182000 { - compatible = "qcom,bam-v1.3.0"; - reg = <0x12182000 0x8000>; - interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc SDC3_H_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; + lpass@28100000 { + compatible = "qcom,lpass-cpu"; + status = "disabled"; + clocks = <&lcc AHBIX_CLK>, + <&lcc MI2S_OSR_CLK>, + <&lcc MI2S_BIT_CLK>; + clock-names = "ahbix-clk", + "mi2s-osr-clk", + "mi2s-bit-clk"; + interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "lpass-irq-lpaif"; + reg = <0x28100000 0x10000>; + reg-names = "lpass-lpaif"; }; - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; + sata: sata@29000000 { + compatible = "qcom,ipq806x-ahci", "generic-ahci"; + reg = <0x29000000 0x180>; - sdcc@12400000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - reg = <0x12400000 0x2000>; - interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <96000000>; - non-removable; - cap-sd-highspeed; - cap-mmc-highspeed; - mmc-ddr-1_8v; - vmmc-supply = <&vsdcc_fixed>; - dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; - dma-names = "tx", "rx"; - }; + interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; - sdcc@12180000 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12180000 0x2000>; - interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <192000000>; - #mmc-ddr-1_8v; - sd-uhs-sdr104; - sd-uhs-ddr50; - vqmmc-supply = <&vsdcc_fixed>; - dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; - dma-names = "tx", "rx"; - }; + clocks = <&gcc SFAB_SATA_S_H_CLK>, + <&gcc SATA_H_CLK>, + <&gcc SATA_A_CLK>, + <&gcc SATA_RXOOB_CLK>, + <&gcc SATA_PMALIVE_CLK>; + clock-names = "slave_face", "iface", "core", + "rxoob", "pmalive"; + + assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>; + assigned-clock-rates = <100000000>, <100000000>; + + phys = <&sata_phy>; + phy-names = "sata-phy"; + status = "disabled"; + }; + + gmac0: ethernet@37000000 { + device_type = "network"; + compatible = "qcom,ipq806x-gmac", "snps,dwmac"; + reg = <0x37000000 0x200000>; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + + snps,axi-config = <&stmmac_axi_setup>; + snps,pbl = <32>; + snps,aal; + + qcom,nss-common = <&nss_common>; + qcom,qsgmii-csr = <&qsgmii_csr>; + + clocks = <&gcc GMAC_CORE1_CLK>; + clock-names = "stmmaceth"; + + resets = <&gcc GMAC_CORE1_RESET>, + <&gcc GMAC_AHB_RESET>; + reset-names = "stmmaceth", "ahb"; + + status = "disabled"; + }; + + gmac1: ethernet@37200000 { + device_type = "network"; + compatible = "qcom,ipq806x-gmac", "snps,dwmac"; + reg = <0x37200000 0x200000>; + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + + snps,axi-config = <&stmmac_axi_setup>; + snps,pbl = <32>; + snps,aal; + + qcom,nss-common = <&nss_common>; + qcom,qsgmii-csr = <&qsgmii_csr>; + + clocks = <&gcc GMAC_CORE2_CLK>; + clock-names = "stmmaceth"; + + resets = <&gcc GMAC_CORE2_RESET>, + <&gcc GMAC_AHB_RESET>; + reset-names = "stmmaceth", "ahb"; + + status = "disabled"; + }; + + gmac2: ethernet@37400000 { + device_type = "network"; + compatible = "qcom,ipq806x-gmac", "snps,dwmac"; + reg = <0x37400000 0x200000>; + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + + snps,axi-config = <&stmmac_axi_setup>; + snps,pbl = <32>; + snps,aal; + + qcom,nss-common = <&nss_common>; + qcom,qsgmii-csr = <&qsgmii_csr>; + + clocks = <&gcc GMAC_CORE3_CLK>; + clock-names = "stmmaceth"; + + resets = <&gcc GMAC_CORE3_RESET>, + <&gcc GMAC_AHB_RESET>; + reset-names = "stmmaceth", "ahb"; + + status = "disabled"; + }; + + gmac3: ethernet@37600000 { + device_type = "network"; + compatible = "qcom,ipq806x-gmac", "snps,dwmac"; + reg = <0x37600000 0x200000>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + + snps,axi-config = <&stmmac_axi_setup>; + snps,pbl = <32>; + snps,aal; + + qcom,nss-common = <&nss_common>; + qcom,qsgmii-csr = <&qsgmii_csr>; + + clocks = <&gcc GMAC_CORE4_CLK>; + clock-names = "stmmaceth"; + + resets = <&gcc GMAC_CORE4_RESET>, + <&gcc GMAC_AHB_RESET>; + reset-names = "stmmaceth", "ahb"; + + status = "disabled"; }; }; }; |