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-rw-r--r--arch/arm/boot/dts/sun8i-a33.dtsi237
1 files changed, 53 insertions, 184 deletions
diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi
index c1cc8f09dd9a..1111a6498102 100644
--- a/arch/arm/boot/dts/sun8i-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a33.dtsi
@@ -131,14 +131,14 @@
#cooling-cells = <2>;
};
- cpu@1 {
+ cpu1: cpu@1 {
clocks = <&ccu CLK_CPUX>;
clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>;
};
- cpu@2 {
+ cpu2: cpu@2 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <2>;
@@ -148,7 +148,7 @@
#cooling-cells = <2>;
};
- cpu@3 {
+ cpu3: cpu@3 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <3>;
@@ -159,12 +159,6 @@
};
};
- de: display-engine {
- compatible = "allwinner,sun8i-a33-display-engine";
- allwinner,pipelines = <&fe0>;
- status = "disabled";
- };
-
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&ths>;
@@ -186,32 +180,13 @@
};
};
- memory {
- reg = <0x40000000 0x80000000>;
- };
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- /* Address must be kept in the lower 256 MiBs of DRAM for VE. */
- cma_pool: cma@4a000000 {
- compatible = "shared-dma-pool";
- size = <0x6000000>;
- alloc-ranges = <0x4a000000 0x6000000>;
- reusable;
- linux,cma-default;
- };
- };
-
sound: sound {
compatible = "simple-audio-card";
simple-audio-card,name = "sun8i-a33-audio";
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&link_codec>;
simple-audio-card,bitclock-master = <&link_codec>;
- simple-audio-card,mclk-fs = <512>;
+ simple-audio-card,mclk-fs = <128>;
simple-audio-card,aux-devs = <&codec_analog>;
simple-audio-card,routing =
"Left DAC", "AIF1 Slot 0 Left",
@@ -227,49 +202,8 @@
};
};
- soc@1c00000 {
- tcon0: lcd-controller@1c0c000 {
- compatible = "allwinner,sun8i-a33-tcon";
- reg = <0x01c0c000 0x1000>;
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_LCD>,
- <&ccu CLK_LCD_CH0>;
- clock-names = "ahb",
- "tcon-ch0";
- clock-output-names = "tcon-pixel-clock";
- resets = <&ccu RST_BUS_LCD>;
- reset-names = "lcd";
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- tcon0_in: port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
-
- tcon0_in_drc0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&drc0_out_tcon0>;
- };
- };
-
- tcon0_out: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
-
- tcon0_out_dsi: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&dsi_in_tcon0>;
- };
- };
- };
- };
-
- video-codec@01c0e000 {
+ soc {
+ video-codec@1c0e000 {
compatible = "allwinner,sun8i-a33-video-engine";
reg = <0x01c0e000 0x1000>;
clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
@@ -358,115 +292,6 @@
status = "disabled";
#phy-cells = <0>;
};
-
- fe0: display-frontend@1e00000 {
- compatible = "allwinner,sun8i-a33-display-frontend";
- reg = <0x01e00000 0x20000>;
- interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
- <&ccu CLK_DRAM_DE_FE>;
- clock-names = "ahb", "mod",
- "ram";
- resets = <&ccu RST_BUS_DE_FE>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- fe0_out: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
-
- fe0_out_be0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&be0_in_fe0>;
- };
- };
- };
- };
-
- be0: display-backend@1e60000 {
- compatible = "allwinner,sun8i-a33-display-backend";
- reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;
- reg-names = "be", "sat";
- interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
- <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;
- clock-names = "ahb", "mod",
- "ram", "sat";
- resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;
- reset-names = "be", "sat";
- assigned-clocks = <&ccu CLK_DE_BE>;
- assigned-clock-rates = <300000000>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- be0_in: port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
-
- be0_in_fe0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&fe0_out_be0>;
- };
- };
-
- be0_out: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
-
- be0_out_drc0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&drc0_in_be0>;
- };
- };
- };
- };
-
- drc0: drc@1e70000 {
- compatible = "allwinner,sun8i-a33-drc";
- reg = <0x01e70000 0x10000>;
- interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
- <&ccu CLK_DRAM_DRC>;
- clock-names = "ahb", "mod", "ram";
- resets = <&ccu RST_BUS_DRC>;
-
- assigned-clocks = <&ccu CLK_DRC>;
- assigned-clock-rates = <300000000>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- drc0_in: port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
-
- drc0_in_be0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&be0_out_drc0>;
- };
- };
-
- drc0_out: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
-
- drc0_out_tcon0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&tcon0_in_drc0>;
- };
- };
- };
- };
};
thermal-zones {
@@ -479,11 +304,17 @@
cooling-maps {
map0 {
trip = <&cpu_alert0>;
- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu_alert1>;
- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map2 {
@@ -537,10 +368,37 @@
};
};
+&be0 {
+ compatible = "allwinner,sun8i-a33-display-backend";
+ /* A33 has an extra "SAT" module packed inside the display backend */
+ reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;
+ reg-names = "be", "sat";
+ clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
+ <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;
+ clock-names = "ahb", "mod",
+ "ram", "sat";
+ resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;
+ reset-names = "be", "sat";
+ assigned-clocks = <&ccu CLK_DE_BE>;
+ assigned-clock-rates = <300000000>;
+};
+
&ccu {
compatible = "allwinner,sun8i-a33-ccu";
};
+&de {
+ compatible = "allwinner,sun8i-a33-display-engine";
+};
+
+&drc0 {
+ compatible = "allwinner,sun8i-a33-drc";
+};
+
+&fe0 {
+ compatible = "allwinner,sun8i-a33-display-frontend";
+};
+
&mali {
operating-points-v2 = <&mali_opp_table>;
};
@@ -550,13 +408,24 @@
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- uart0_pins_b: uart0@1 {
+ uart0_pb_pins: uart0-pb-pins {
pins = "PB0", "PB1";
function = "uart0";
};
};
+&tcon0 {
+ compatible = "allwinner,sun8i-a33-tcon";
+};
+
+&tcon0_out {
+ tcon0_out_dsi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&dsi_in_tcon0>;
+ };
+};
+
&usb_otg {
compatible = "allwinner,sun8i-a33-musb";
};
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