diff options
Diffstat (limited to 'arch/arm/boot')
28 files changed, 2528 insertions, 67 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 962c0eee3039..641b3c9a7028 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -59,6 +59,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ exynos5440-sd5v1.dtb \ exynos5250-smdk5250.dtb \ exynos5250-snow.dtb \ + exynos5420-smdk5420.dtb \ exynos5440-ssdk5440.dtb dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \ ecx-2000.dtb @@ -148,6 +149,9 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ imx28-sps1.dtb \ imx28-tx28.dtb dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb +dtb-$(CONFIG_ARCH_NSPIRE) += nspire-cx.dtb \ + nspire-tp.dtb \ + nspire-clp.dtb dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ omap3430-sdp.dtb \ omap3-beagle.dtb \ @@ -197,6 +201,10 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \ spear320-evb.dtb \ spear320-hmi.dtb dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb +dtb-$(CONFIG_ARCH_STI)+= stih415-b2000.dtb \ + stih416-b2000.dtb \ + stih415-b2020.dtb \ + stih416-b2020.dtb dtb-$(CONFIG_ARCH_SUNXI) += \ sun4i-a10-cubieboard.dtb \ sun4i-a10-mini-xplus.dtb \ diff --git a/arch/arm/boot/dts/da850-enbw-cmc.dts b/arch/arm/boot/dts/da850-enbw-cmc.dts index 422fdb3fcfc1..e750ab9086d5 100644 --- a/arch/arm/boot/dts/da850-enbw-cmc.dts +++ b/arch/arm/boot/dts/da850-enbw-cmc.dts @@ -10,7 +10,7 @@ * option) any later version. */ /dts-v1/; -/include/ "da850.dtsi" +#include "da850.dtsi" / { compatible = "enbw,cmc", "ti,da850"; diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts index c914357c0d89..5bce7cc55cf3 100644 --- a/arch/arm/boot/dts/da850-evm.dts +++ b/arch/arm/boot/dts/da850-evm.dts @@ -8,7 +8,7 @@ * Free Software Foundation, version 2. */ /dts-v1/; -/include/ "da850.dtsi" +#include "da850.dtsi" / { compatible = "ti,da850-evm", "ti,da850"; diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index 2c88313d2c7a..d70ba5504481 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi @@ -7,7 +7,7 @@ * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" / { arm { @@ -37,7 +37,7 @@ #size-cells = <0>; pinctrl-single,bit-per-mux; pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; + pinctrl-single,function-mask = <0xf>; status = "disabled"; nand_cs3_pins: pinmux_nand_pins { diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi new file mode 100644 index 000000000000..f65e124c04a6 --- /dev/null +++ b/arch/arm/boot/dts/exynos5.dtsi @@ -0,0 +1,111 @@ +/* + * Samsung's Exynos5 SoC series common device tree source + * + * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos5 SoC series device nodes are listed in this file. Particular + * SoCs from Exynos5 series can include this file and provide values for SoCs + * specfic bindings. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "skeleton.dtsi" + +/ { + interrupt-parent = <&gic>; + + chipid@10000000 { + compatible = "samsung,exynos4210-chipid"; + reg = <0x10000000 0x100>; + }; + + combiner:interrupt-controller@10440000 { + compatible = "samsung,exynos4210-combiner"; + #interrupt-cells = <2>; + interrupt-controller; + samsung,combiner-nr = <32>; + reg = <0x10440000 0x1000>; + interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, + <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, + <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, + <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, + <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, + <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>, + <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>, + <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; + }; + + gic:interrupt-controller@10481000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x10481000 0x1000>, + <0x10482000 0x1000>, + <0x10484000 0x2000>, + <0x10486000 0x2000>; + interrupts = <1 9 0xf04>; + }; + + dwmmc_0: dwmmc0@12200000 { + compatible = "samsung,exynos5250-dw-mshc"; + interrupts = <0 75 0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + dwmmc_1: dwmmc1@12210000 { + compatible = "samsung,exynos5250-dw-mshc"; + interrupts = <0 76 0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + dwmmc_2: dwmmc2@12220000 { + compatible = "samsung,exynos5250-dw-mshc"; + interrupts = <0 77 0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + serial@12C00000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C00000 0x100>; + interrupts = <0 51 0>; + }; + + serial@12C10000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C10000 0x100>; + interrupts = <0 52 0>; + }; + + serial@12C20000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C20000 0x100>; + interrupts = <0 53 0>; + }; + + serial@12C30000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C30000 0x100>; + interrupts = <0 54 0>; + }; + + rtc { + compatible = "samsung,s3c6410-rtc"; + reg = <0x101E0000 0x100>; + interrupts = <0 43 0>, <0 44 0>; + status = "disabled"; + }; + + watchdog { + compatible = "samsung,s3c2410-wdt"; + reg = <0x101D0000 0x100>; + interrupts = <0 42 0>; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 964158c1844f..41cd625b6020 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -17,14 +17,13 @@ * published by the Free Software Foundation. */ -#include "skeleton.dtsi" +#include "exynos5.dtsi" #include "exynos5250-pinctrl.dtsi" #include <dt-bindings/clk/exynos-audss-clk.h> / { compatible = "samsung,exynos5250"; - interrupt-parent = <&gic>; aliases { spi0 = &spi_0; @@ -53,9 +52,20 @@ pinctrl3 = &pinctrl_3; }; - chipid@10000000 { - compatible = "samsung,exynos4210-chipid"; - reg = <0x10000000 0x100>; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + }; }; pd_gsc: gsc-power-domain@0x10044000 { @@ -80,17 +90,6 @@ #clock-cells = <1>; }; - gic:interrupt-controller@10481000 { - compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x10481000 0x1000>, - <0x10482000 0x1000>, - <0x10484000 0x2000>, - <0x10486000 0x2000>; - interrupts = <1 9 0xf04>; - }; - timer { compatible = "arm,armv7-timer"; interrupts = <1 13 0xf08>, @@ -99,22 +98,6 @@ <1 10 0xf08>; }; - combiner:interrupt-controller@10440000 { - compatible = "samsung,exynos4210-combiner"; - #interrupt-cells = <2>; - interrupt-controller; - samsung,combiner-nr = <32>; - reg = <0x10440000 0x1000>; - interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, - <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, - <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, - <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, - <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, - <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>, - <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>, - <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; - }; - mct@101C0000 { compatible = "samsung,exynos4210-mct"; reg = <0x101C0000 0x800>; @@ -176,9 +159,6 @@ }; watchdog { - compatible = "samsung,s3c2410-wdt"; - reg = <0x101D0000 0x100>; - interrupts = <0 42 0>; clocks = <&clock 336>; clock-names = "watchdog"; }; @@ -191,12 +171,8 @@ }; rtc { - compatible = "samsung,s3c6410-rtc"; - reg = <0x101E0000 0x100>; - interrupts = <0 43 0>, <0 44 0>; clocks = <&clock 337>; clock-names = "rtc"; - status = "disabled"; }; tmu@10060000 { @@ -208,33 +184,21 @@ }; serial@12C00000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C00000 0x100>; - interrupts = <0 51 0>; clocks = <&clock 289>, <&clock 146>; clock-names = "uart", "clk_uart_baud0"; }; serial@12C10000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C10000 0x100>; - interrupts = <0 52 0>; clocks = <&clock 290>, <&clock 147>; clock-names = "uart", "clk_uart_baud0"; }; serial@12C20000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C20000 0x100>; - interrupts = <0 53 0>; clocks = <&clock 291>, <&clock 148>; clock-names = "uart", "clk_uart_baud0"; }; serial@12C30000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C30000 0x100>; - interrupts = <0 54 0>; clocks = <&clock 292>, <&clock 149>; clock-names = "uart", "clk_uart_baud0"; }; @@ -413,31 +377,19 @@ }; dwmmc_0: dwmmc0@12200000 { - compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12200000 0x1000>; - interrupts = <0 75 0>; - #address-cells = <1>; - #size-cells = <0>; clocks = <&clock 280>, <&clock 139>; clock-names = "biu", "ciu"; }; dwmmc_1: dwmmc1@12210000 { - compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12210000 0x1000>; - interrupts = <0 76 0>; - #address-cells = <1>; - #size-cells = <0>; clocks = <&clock 281>, <&clock 140>; clock-names = "biu", "ciu"; }; dwmmc_2: dwmmc2@12220000 { - compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12220000 0x1000>; - interrupts = <0 77 0>; - #address-cells = <1>; - #size-cells = <0>; clocks = <&clock 282>, <&clock 141>; clock-names = "biu", "ciu"; }; diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi new file mode 100644 index 000000000000..5848c425ae4d --- /dev/null +++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi @@ -0,0 +1,680 @@ +/* + * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device + * tree nodes are listed in this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/ { + pinctrl@13400000 { + gpy7: gpy7 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx0: gpx0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&combiner>; + #interrupt-cells = <2>; + interrupts = <23 0>, <24 0>, <25 0>, <25 1>, + <26 0>, <26 1>, <27 0>, <27 1>; + }; + + gpx1: gpx1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&combiner>; + #interrupt-cells = <2>; + interrupts = <28 0>, <28 1>, <29 0>, <29 1>, + <30 0>, <30 1>, <31 0>, <31 1>; + }; + + gpx2: gpx2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx3: gpx3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pinctrl@13410000 { + gpc0: gpc0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc2: gpc2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc3: gpc3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc4: gpc4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd1: gpd1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpy0: gpy0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy1: gpy1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy2: gpy2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy3: gpy3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy4: gpy4 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy5: gpy5 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy6: gpy6 { + gpio-controller; + #gpio-cells = <2>; + }; + + sd0_clk: sd0-clk { + samsung,pins = "gpc0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_cmd: sd0-cmd { + samsung,pins = "gpc0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_cd: sd0-cd { + samsung,pins = "gpc0-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus1: sd0-bus-width1 { + samsung,pins = "gpc0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus4: sd0-bus-width4 { + samsung,pins = "gpc0-4", "gpc0-5", "gpc0-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus8: sd0-bus-width8 { + samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_clk: sd1-clk { + samsung,pins = "gpc1-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd1_cmd: sd1-cmd { + samsung,pins = "gpc1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd1_cd: sd1-cd { + samsung,pins = "gpc1-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_int: sd1-int { + samsung,pins = "gpd1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + sd1_bus1: sd1-bus-width1 { + samsung,pins = "gpc1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_bus4: sd1-bus-width4 { + samsung,pins = "gpc1-4", "gpc1-5", "gpc1-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_bus8: sd1-bus-width8 { + samsung,pins = "gpd1-4", "gpd1-5", "gpd1-6", "gpd1-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_clk: sd2-clk { + samsung,pins = "gpc2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd2_cmd: sd2-cmd { + samsung,pins = "gpc2-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd2_cd: sd2-cd { + samsung,pins = "gpc2-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_bus1: sd2-bus-width1 { + samsung,pins = "gpc2-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_bus4: sd2-bus-width4 { + samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + }; + + pinctrl@14000000 { + gpe0: gpe0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe1: gpe1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg0: gpg0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg1: gpg1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg2: gpg2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpj4: gpj4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + cam_gpio_a: cam-gpio-a { + samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", + "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", + "gpe1-0", "gpe1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + cam_gpio_b: cam-gpio-b { + samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3", + "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + cam_i2c2_bus: cam-i2c2-bus { + samsung,pins = "gpf0-4", "gpf0-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + cam_spi1_bus: cam-spi1-bus { + samsung,pins = "gpe0-4", "gpe0-5", "gpf0-2", "gpf0-3"; + samsung,pin-function = <4>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + cam_i2c1_bus: cam-i2c1-bus { + samsung,pins = "gpf0-2", "gpf0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + cam_i2c0_bus: cam-i2c0-bus { + samsung,pins = "gpf0-0", "gpf0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + cam_spi0_bus: cam-spi0-bus { + samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + cam_bayrgb_bus: cam-bayrgb-bus { + samsung,pins = "gpg0-0", "gpg0-1", "gpg0-2", "gpg0-3", + "gpg0-4", "gpg0-5", "gpg0-6", "gpg0-7", + "gpg1-0", "gpg1-1", "gpg1-2", "gpg1-3", + "gpg1-4", "gpg1-5", "gpg1-6", "gpg1-7", + "gpg2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + }; + + pinctrl@14010000 { + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa2: gpa2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb0: gpb0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb1: gpb1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb2: gpb2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb3: gpb3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb4: gpb4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gph0: gph0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + uart0_data: uart0-data { + samsung,pins = "gpa0-0", "gpa0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart0_fctl: uart0-fctl { + samsung,pins = "gpa0-2", "gpa0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart1_data: uart1-data { + samsung,pins = "gpa0-4", "gpa0-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart1_fctl: uart1-fctl { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2c2_bus: i2c2-bus { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + uart2_data: uart2-data { + samsung,pins = "gpa1-0", "gpa1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart2_fctl: uart2-fctl { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2c3_bus: i2c3-bus { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + uart3_data: uart3-data { + samsung,pins = "gpa1-4", "gpa1-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + spi0_bus: spi0-bus { + samsung,pins = "gpa2-0", "gpa2-1", "gpa2-2", "gpa2-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi1_bus: spi1-bus { + samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c4_hs_bus: i2c4-hs-bus { + samsung,pins = "gpa2-0", "gpa2-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c5_hs_bus: i2c5-hs-bus { + samsung,pins = "gpa2-2", "gpa2-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2s1_bus: i2s1-bus { + samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", + "gpb0-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pcm1_bus: pcm1-bus { + samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", + "gpb0-4"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2s2_bus: i2s2-bus { + samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", + "gpb1-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pcm2_bus: pcm2-bus { + samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", + "gpb1-4"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + spdif_bus: spdif-bus { + samsung,pins = "gpb1-0", "gpb1-1"; + samsung,pin-function = <4>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + spi2_bus: spi2-bus { + samsung,pins = "gpb1-1", "gpb1-3", "gpb1-4"; + samsung,pin-function = <5>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c6_hs_bus: i2c6-hs-bus { + samsung,pins = "gpb1-3", "gpb1-4"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c7_hs_bus: i2c7-hs-bus { + samsung,pins = "gpb2-2", "gpb2-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c0_bus: i2c0-bus { + samsung,pins = "gpb3-0", "gpb3-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c1_bus: i2c1-bus { + samsung,pins = "gpb3-2", "gpb3-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c8_hs_bus: i2c8-hs-bus { + samsung,pins = "gpb3-4", "gpb3-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c9_hs_bus: i2c9-hs-bus { + samsung,pins = "gpb3-6", "gpb3-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c10_hs_bus: i2c10-hs-bus { + samsung,pins = "gpb4-0", "gpb4-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + }; + + pinctrl@03860000 { + gpz: gpz { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + i2s0_bus: i2s0-bus { + samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", + "gpz-4", "gpz-5", "gpz-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts new file mode 100644 index 000000000000..08607df6a180 --- /dev/null +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -0,0 +1,33 @@ +/* + * SAMSUNG SMDK5420 board device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/dts-v1/; +#include "exynos5420.dtsi" + +/ { + model = "Samsung SMDK5420 board based on EXYNOS5420"; + compatible = "samsung,smdk5420", "samsung,exynos5420"; + + memory { + reg = <0x20000000 0x80000000>; + }; + + chosen { + bootargs = "console=ttySAC2,115200 init=/linuxrc"; + }; + + fixed-rate-clocks { + oscclk { + compatible = "samsung,exynos5420-oscclk"; + clock-frequency = <24000000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi new file mode 100644 index 000000000000..8c54c4b74f0e --- /dev/null +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -0,0 +1,148 @@ +/* + * SAMSUNG EXYNOS5420 SoC device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file. + * EXYNOS5420 based board files can include this file and provide + * values for board specfic bindings. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "exynos5.dtsi" +/include/ "exynos5420-pinctrl.dtsi" +/ { + compatible = "samsung,exynos5420"; + + aliases { + pinctrl0 = &pinctrl_0; + pinctrl1 = &pinctrl_1; + pinctrl2 = &pinctrl_2; + pinctrl3 = &pinctrl_3; + pinctrl4 = &pinctrl_4; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x0>; + clock-frequency = <1800000000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x1>; + clock-frequency = <1800000000>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x2>; + clock-frequency = <1800000000>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x3>; + clock-frequency = <1800000000>; + }; + }; + + clock: clock-controller@0x10010000 { + compatible = "samsung,exynos5420-clock"; + reg = <0x10010000 0x30000>; + #clock-cells = <1>; + }; + + mct@101C0000 { + compatible = "samsung,exynos4210-mct"; + reg = <0x101C0000 0x800>; + interrupt-controller; + #interrups-cells = <1>; + interrupt-parent = <&mct_map>; + interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>; + clocks = <&clock 1>, <&clock 315>; + clock-names = "fin_pll", "mct"; + + mct_map: mct-map { + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = <0 &combiner 23 3>, + <1 &combiner 23 4>, + <2 &combiner 25 2>, + <3 &combiner 25 3>, + <4 &gic 0 120 0>, + <5 &gic 0 121 0>, + <6 &gic 0 122 0>, + <7 &gic 0 123 0>; + }; + }; + + pinctrl_0: pinctrl@13400000 { + compatible = "samsung,exynos5420-pinctrl"; + reg = <0x13400000 0x1000>; + interrupts = <0 45 0>; + + wakeup-interrupt-controller { + compatible = "samsung,exynos4210-wakeup-eint"; + interrupt-parent = <&gic>; + interrupts = <0 32 0>; + }; + }; + + pinctrl_1: pinctrl@13410000 { + compatible = "samsung,exynos5420-pinctrl"; + reg = <0x13410000 0x1000>; + interrupts = <0 78 0>; + }; + + pinctrl_2: pinctrl@14000000 { + compatible = "samsung,exynos5420-pinctrl"; + reg = <0x14000000 0x1000>; + interrupts = <0 46 0>; + }; + + pinctrl_3: pinctrl@14010000 { + compatible = "samsung,exynos5420-pinctrl"; + reg = <0x14010000 0x1000>; + interrupts = <0 50 0>; + }; + + pinctrl_4: pinctrl@03860000 { + compatible = "samsung,exynos5420-pinctrl"; + reg = <0x03860000 0x1000>; + interrupts = <0 47 0>; + }; + + serial@12C00000 { + clocks = <&clock 257>, <&clock 128>; + clock-names = "uart", "clk_uart_baud0"; + }; + + serial@12C10000 { + clocks = <&clock 258>, <&clock 129>; + clock-names = "uart", "clk_uart_baud0"; + }; + + serial@12C20000 { + clocks = <&clock 259>, <&clock 130>; + clock-names = "uart", "clk_uart_baud0"; + }; + + serial@12C30000 { + clocks = <&clock 260>, <&clock 131>; + clock-names = "uart", "clk_uart_baud0"; + }; +}; diff --git a/arch/arm/boot/dts/nspire-classic.dtsi b/arch/arm/boot/dts/nspire-classic.dtsi new file mode 100644 index 000000000000..9565199bce7a --- /dev/null +++ b/arch/arm/boot/dts/nspire-classic.dtsi @@ -0,0 +1,74 @@ +/* + * linux/arch/arm/boot/nspire-classic.dts + * + * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + */ + +/include/ "nspire.dtsi" + +&lcd { + lcd-type = "classic"; +}; + +&fast_timer { + /* compatible = "lsi,zevio-timer"; */ + reg = <0x90010000 0x1000>, <0x900A0010 0x8>; +}; + +&uart { + compatible = "ns16550"; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb_pclk>; + no-loopback-test; +}; + +&timer0 { + /* compatible = "lsi,zevio-timer"; */ + reg = <0x900C0000 0x1000>, <0x900A0018 0x8>; +}; + +&timer1 { + compatible = "lsi,zevio-timer"; + reg = <0x900D0000 0x1000>, <0x900A0020 0x8>; +}; + +&keypad { + active-low; + +}; + +&base_clk { + compatible = "lsi,nspire-classic-clock"; +}; + +&ahb_clk { + compatible = "lsi,nspire-classic-ahb-divider"; +}; + +/ { + memory { + device_type = "memory"; + reg = <0x10000000 0x2000000>; /* 32 MB */ + }; + + ahb { + #address-cells = <1>; + #size-cells = <1>; + + intc: interrupt-controller@DC000000 { + compatible = "lsi,zevio-intc"; + interrupt-controller; + reg = <0xDC000000 0x1000>; + #interrupt-cells = <1>; + }; + }; + chosen { + bootargs = "debug earlyprintk console=tty0 console=ttyS0,115200n8 root=/dev/ram0"; + }; +}; diff --git a/arch/arm/boot/dts/nspire-clp.dts b/arch/arm/boot/dts/nspire-clp.dts new file mode 100644 index 000000000000..fa5a044656de --- /dev/null +++ b/arch/arm/boot/dts/nspire-clp.dts @@ -0,0 +1,45 @@ +/* + * linux/arch/arm/boot/nspire-clp.dts + * + * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + */ +/dts-v1/; + +/include/ "nspire-classic.dtsi" + +&keypad { + linux,keymap = < + 0x0000001c 0x0001001c 0x00020039 + 0x0004002c 0x00050034 0x00060015 + 0x0007000b 0x0008002d 0x01000033 + 0x0101004e 0x01020011 0x01030004 + 0x0104002f 0x01050003 0x01060016 + 0x01070002 0x01080014 0x02000062 + 0x0201000c 0x0202001f 0x02030007 + 0x02040013 0x02050006 0x02060010 + 0x02070005 0x02080019 0x03000027 + 0x03010037 0x03020018 0x0303000a + 0x03040031 0x03050009 0x03060032 + 0x03070008 0x03080026 0x04000028 + 0x04010035 0x04020025 0x04040024 + 0x04060017 0x04080023 0x05000028 + 0x05020022 0x0503001b 0x05040021 + 0x0505001a 0x05060012 0x0507006f + 0x05080020 0x0509002a 0x0601001c + 0x0602002e 0x06030068 0x06040030 + 0x0605006d 0x0606001e 0x06070001 + 0x0608002b 0x0609000f 0x07000067 + 0x0702006a 0x0704006c 0x07060069 + 0x0707000e 0x0708001d 0x070a000d + >; +}; + +/ { + model = "TI-NSPIRE Clickpad"; + compatible = "ti,nspire-clp"; +}; diff --git a/arch/arm/boot/dts/nspire-cx.dts b/arch/arm/boot/dts/nspire-cx.dts new file mode 100644 index 000000000000..375b924f60d8 --- /dev/null +++ b/arch/arm/boot/dts/nspire-cx.dts @@ -0,0 +1,112 @@ +/* + * linux/arch/arm/boot/nspire-cx.dts + * + * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + */ +/dts-v1/; + +/include/ "nspire.dtsi" + +&lcd { + lcd-type = "cx"; +}; + +&fast_timer { + /* compatible = "arm,sp804", "arm,primecell"; */ +}; + +&uart { + compatible = "arm,pl011", "arm,primecell"; + + clocks = <&uart_clk>, <&apb_pclk>; + clock-names = "uart_clk", "apb_pclk"; +}; + +&timer0 { + compatible = "arm,sp804", "arm,primecell"; +}; + +&timer1 { + compatible = "arm,sp804", "arm,primecell"; +}; + +&base_clk { + compatible = "lsi,nspire-cx-clock"; +}; + +&ahb_clk { + compatible = "lsi,nspire-cx-ahb-divider"; +}; + +&keypad { + linux,keymap = < + 0x0000001c 0x0001001c 0x00040039 + 0x0005002c 0x00060015 0x0007000b + 0x0008000f 0x0100002d 0x01010011 + 0x0102002f 0x01030004 0x01040016 + 0x01050014 0x0106001f 0x01070002 + 0x010a006a 0x02000013 0x02010010 + 0x02020019 0x02030007 0x02040018 + 0x02050031 0x02060032 0x02070005 + 0x02080028 0x0209006c 0x03000026 + 0x03010025 0x03020024 0x0303000a + 0x03040017 0x03050023 0x03060022 + 0x03070008 0x03080035 0x03090069 + 0x04000021 0x04010012 0x04020020 + 0x0404002e 0x04050030 0x0406001e + 0x0407000d 0x04080037 0x04090067 + 0x05010038 0x0502000c 0x0503001b + 0x05040034 0x0505001a 0x05060006 + 0x05080027 0x0509000e 0x050a006f + 0x0600002b 0x0602004e 0x06030068 + 0x06040003 0x0605006d 0x06060009 + 0x06070001 0x0609000f 0x0708002a + 0x0709001d 0x070a0033 >; +}; + +/ { + model = "TI-NSPIRE CX"; + compatible = "ti,nspire-cx"; + + memory { + device_type = "memory"; + reg = <0x10000000 0x4000000>; /* 64 MB */ + }; + + uart_clk: uart_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12000000>; + }; + + ahb { + #address-cells = <1>; + #size-cells = <1>; + + intc: interrupt-controller@DC000000 { + compatible = "arm,pl190-vic"; + interrupt-controller; + reg = <0xDC000000 0x1000>; + #interrupt-cells = <1>; + }; + + apb@90000000 { + #address-cells = <1>; + #size-cells = <1>; + + i2c@90050000 { + compatible = "snps,designware-i2c"; + reg = <0x90050000 0x1000>; + interrupts = <20>; + }; + }; + }; + chosen { + bootargs = "debug earlyprintk console=tty0 console=ttyAMA0,115200n8 root=/dev/ram0"; + }; +}; diff --git a/arch/arm/boot/dts/nspire-tp.dts b/arch/arm/boot/dts/nspire-tp.dts new file mode 100644 index 000000000000..621391ce6ed6 --- /dev/null +++ b/arch/arm/boot/dts/nspire-tp.dts @@ -0,0 +1,44 @@ +/* + * linux/arch/arm/boot/nspire-tp.dts + * + * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + */ +/dts-v1/; + +/include/ "nspire-classic.dtsi" + +&keypad { + linux,keymap = < + 0x0000001c 0x0001001c 0x00040039 + 0x0005002c 0x00060015 0x0007000b + 0x0008000f 0x0100002d 0x01010011 + 0x0102002f 0x01030004 0x01040016 + 0x01050014 0x0106001f 0x01070002 + 0x010a006a 0x02000013 0x02010010 + 0x02020019 0x02030007 0x02040018 + 0x02050031 0x02060032 0x02070005 + 0x02080028 0x0209006c 0x03000026 + 0x03010025 0x03020024 0x0303000a + 0x03040017 0x03050023 0x03060022 + 0x03070008 0x03080035 0x03090069 + 0x04000021 0x04010012 0x04020020 + 0x0404002e 0x04050030 0x0406001e + 0x0407000d 0x04080037 0x04090067 + 0x05010038 0x0502000c 0x0503001b + 0x05040034 0x0505001a 0x05060006 + 0x05080027 0x0509000e 0x050a006f + 0x0600002b 0x0602004e 0x06030068 + 0x06040003 0x0605006d 0x06060009 + 0x06070001 0x0609000f 0x0708002a + 0x0709001d 0x070a0033 >; +}; + +/ { + model = "TI-NSPIRE Touchpad"; + compatible = "ti,nspire-tp"; +}; diff --git a/arch/arm/boot/dts/nspire.dtsi b/arch/arm/boot/dts/nspire.dtsi new file mode 100644 index 000000000000..a22ffe633b49 --- /dev/null +++ b/arch/arm/boot/dts/nspire.dtsi @@ -0,0 +1,175 @@ +/* + * linux/arch/arm/boot/nspire.dtsi + * + * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + */ + +/include/ "skeleton.dtsi" + +/ { + interrupt-parent = <&intc>; + + cpus { + cpu@0 { + compatible = "arm,arm926ejs"; + }; + }; + + bootrom: bootrom@00000000 { + reg = <0x00000000 0x80000>; + }; + + sram: sram@A4000000 { + device = "memory"; + reg = <0xA4000000 0x20000>; + }; + + timer_clk: timer_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + base_clk: base_clk { + #clock-cells = <0>; + reg = <0x900B0024 0x4>; + }; + + ahb_clk: ahb_clk { + #clock-cells = <0>; + reg = <0x900B0024 0x4>; + clocks = <&base_clk>; + }; + + apb_pclk: apb_pclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <2>; + clock-mult = <1>; + clocks = <&ahb_clk>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + spi: spi@A9000000 { + reg = <0xA9000000 0x1000>; + }; + + usb0: usb@B0000000 { + reg = <0xB0000000 0x1000>; + interrupts = <8>; + }; + + usb1: usb@B4000000 { + reg = <0xB4000000 0x1000>; + interrupts = <9>; + status = "disabled"; + }; + + lcd: lcd@C0000000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0xC0000000 0x1000>; + interrupts = <21>; + + clocks = <&apb_pclk>; + clock-names = "apb_pclk"; + }; + + adc: adc@C4000000 { + reg = <0xC4000000 0x1000>; + interrupts = <11>; + }; + + tdes: crypto@C8010000 { + reg = <0xC8010000 0x1000>; + }; + + sha256: crypto@CC000000 { + reg = <0xCC000000 0x1000>; + }; + + apb@90000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + clock-ranges; + ranges; + + gpio: gpio@90000000 { + reg = <0x90000000 0x1000>; + interrupts = <7>; + }; + + fast_timer: timer@90010000 { + reg = <0x90010000 0x1000>; + interrupts = <17>; + }; + + uart: serial@90020000 { + reg = <0x90020000 0x1000>; + interrupts = <1>; + }; + + timer0: timer@900C0000 { + reg = <0x900C0000 0x1000>; + + clocks = <&timer_clk>; + }; + + timer1: timer@900D0000 { + reg = <0x900D0000 0x1000>; + interrupts = <19>; + + clocks = <&timer_clk>; + }; + + watchdog: watchdog@90060000 { + compatible = "arm,amba-primecell"; + reg = <0x90060000 0x1000>; + interrupts = <3>; + }; + + rtc: rtc@90090000 { + reg = <0x90090000 0x1000>; + interrupts = <4>; + }; + + misc: misc@900A0000 { + reg = <0x900A0000 0x1000>; + }; + + pwr: pwr@900B0000 { + reg = <0x900B0000 0x1000>; + interrupts = <15>; + }; + + keypad: input@900E0000 { + compatible = "ti,nspire-keypad"; + reg = <0x900E0000 0x1000>; + interrupts = <16>; + + scan-interval = <1000>; + row-delay = <200>; + + clocks = <&apb_pclk>; + }; + + contrast: contrast@900F0000 { + reg = <0x900F0000 0x1000>; + }; + + led: led@90110000 { + reg = <0x90110000 0x1000>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/st-pincfg.h b/arch/arm/boot/dts/st-pincfg.h new file mode 100644 index 000000000000..8c45d85ac13e --- /dev/null +++ b/arch/arm/boot/dts/st-pincfg.h @@ -0,0 +1,71 @@ +#ifndef _ST_PINCFG_H_ +#define _ST_PINCFG_H_ + +/* Alternate functions */ +#define ALT1 1 +#define ALT2 2 +#define ALT3 3 +#define ALT4 4 +#define ALT5 5 +#define ALT6 6 +#define ALT7 7 + +/* Output enable */ +#define OE (1 << 27) +/* Pull Up */ +#define PU (1 << 26) +/* Open Drain */ +#define OD (1 << 26) +#define RT (1 << 23) +#define INVERTCLK (1 << 22) +#define CLKNOTDATA (1 << 21) +#define DOUBLE_EDGE (1 << 20) +#define CLK_A (0 << 18) +#define CLK_B (1 << 18) +#define CLK_C (2 << 18) +#define CLK_D (3 << 18) + +/* User-frendly defines for Pin Direction */ + /* oe = 0, pu = 0, od = 0 */ +#define IN (0) + /* oe = 0, pu = 1, od = 0 */ +#define IN_PU (PU) + /* oe = 1, pu = 0, od = 0 */ +#define OUT (OE) + /* oe = 1, pu = 0, od = 1 */ +#define BIDIR (OE | OD) + /* oe = 1, pu = 1, od = 1 */ +#define BIDIR_PU (OE | PU | OD) + +/* RETIME_TYPE */ +/* + * B Mode + * Bypass retime with optional delay parameter + */ +#define BYPASS (0) +/* + * R0, R1, R0D, R1D modes + * single-edge data non inverted clock, retime data with clk + */ +#define SE_NICLK_IO (RT) +/* + * RIV0, RIV1, RIV0D, RIV1D modes + * single-edge data inverted clock, retime data with clk + */ +#define SE_ICLK_IO (RT | INVERTCLK) +/* + * R0E, R1E, R0ED, R1ED modes + * double-edge data, retime data with clk + */ +#define DE_IO (RT | DOUBLE_EDGE) +/* + * CIV0, CIV1 modes with inverted clock + * Retiming the clk pins will park clock & reduce the noise within the core. + */ +#define ICLK (RT | CLKNOTDATA | INVERTCLK) +/* + * CLK0, CLK1 modes with non-inverted clock + * Retiming the clk pins will park clock & reduce the noise within the core. + */ +#define NICLK (RT | CLKNOTDATA) +#endif /* _ST_PINCFG_H_ */ diff --git a/arch/arm/boot/dts/stih415-b2000.dts b/arch/arm/boot/dts/stih415-b2000.dts new file mode 100644 index 000000000000..d4af53160435 --- /dev/null +++ b/arch/arm/boot/dts/stih415-b2000.dts @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2013 STMicroelectronics (R&D) Limited. + * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ +/dts-v1/; +#include "stih415.dtsi" +#include "stih41x-b2000.dtsi" +/ { + model = "STiH415 B2000 Board"; + compatible = "st,stih415", "st,stih415-b2000"; +}; diff --git a/arch/arm/boot/dts/stih415-b2020.dts b/arch/arm/boot/dts/stih415-b2020.dts new file mode 100644 index 000000000000..442b019e9a3a --- /dev/null +++ b/arch/arm/boot/dts/stih415-b2020.dts @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2013 STMicroelectronics (R&D) Limited. + * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ +/dts-v1/; +#include "stih415.dtsi" +#include "stih41x-b2020.dtsi" +/ { + model = "STiH415 B2020 Board"; + compatible = "st,stih415", "st,stih415-b2020"; +}; diff --git a/arch/arm/boot/dts/stih415-clock.dtsi b/arch/arm/boot/dts/stih415-clock.dtsi new file mode 100644 index 000000000000..174c799df741 --- /dev/null +++ b/arch/arm/boot/dts/stih415-clock.dtsi @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2013 STMicroelectronics (R&D) Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/ { + clocks { + /* + * Fixed 30MHz oscillator input to SoC + */ + CLK_SYSIN: CLK_SYSIN { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <30000000>; + }; + + /* + * ARM Peripheral clock for timers + */ + arm_periph_clk: arm_periph_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <500000000>; + }; + + /* + * Bootloader initialized system infrastructure clock for + * serial devices. + */ + CLKS_ICN_REG_0: CLKS_ICN_REG_0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi new file mode 100644 index 000000000000..1d322b24d1e4 --- /dev/null +++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi @@ -0,0 +1,268 @@ +/* + * Copyright (C) 2013 STMicroelectronics (R&D) Limited. + * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ +#include "st-pincfg.h" +/ { + + aliases { + gpio0 = &PIO0; + gpio1 = &PIO1; + gpio2 = &PIO2; + gpio3 = &PIO3; + gpio4 = &PIO4; + gpio5 = &PIO5; + gpio6 = &PIO6; + gpio7 = &PIO7; + gpio8 = &PIO8; + gpio9 = &PIO9; + gpio10 = &PIO10; + gpio11 = &PIO11; + gpio12 = &PIO12; + gpio13 = &PIO13; + gpio14 = &PIO14; + gpio15 = &PIO15; + gpio16 = &PIO16; + gpio17 = &PIO17; + gpio18 = &PIO18; + gpio19 = &PIO100; + gpio20 = &PIO101; + gpio21 = &PIO102; + gpio22 = &PIO103; + gpio23 = &PIO104; + gpio24 = &PIO105; + gpio25 = &PIO106; + gpio26 = &PIO107; + }; + + soc { + pin-controller-sbc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stih415-sbc-pinctrl"; + st,syscfg = <&syscfg_sbc>; + ranges = <0 0xfe610000 0x5000>; + + PIO0: gpio@fe610000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0 0x100>; + st,bank-name = "PIO0"; + }; + PIO1: gpio@fe611000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x1000 0x100>; + st,bank-name = "PIO1"; + }; + PIO2: gpio@fe612000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x2000 0x100>; + st,bank-name = "PIO2"; + }; + PIO3: gpio@fe613000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x3000 0x100>; + st,bank-name = "PIO3"; + }; + PIO4: gpio@fe614000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x4000 0x100>; + st,bank-name = "PIO4"; + }; + + sbc_serial1 { + pinctrl_sbc_serial1:sbc_serial1 { + st,pins { + tx = <&PIO2 6 ALT3 OUT>; + rx = <&PIO2 7 ALT3 IN>; + }; + }; + }; + }; + + pin-controller-front { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stih415-front-pinctrl"; + st,syscfg = <&syscfg_front>; + ranges = <0 0xfee00000 0x8000>; + + PIO5: gpio@fee00000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0 0x100>; + st,bank-name = "PIO5"; + }; + PIO6: gpio@fee01000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x1000 0x100>; + st,bank-name = "PIO6"; + }; + PIO7: gpio@fee02000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x2000 0x100>; + st,bank-name = "PIO7"; + }; + PIO8: gpio@fee03000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x3000 0x100>; + st,bank-name = "PIO8"; + }; + PIO9: gpio@fee04000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x4000 0x100>; + st,bank-name = "PIO9"; + }; + PIO10: gpio@fee05000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x5000 0x100>; + st,bank-name = "PIO10"; + }; + PIO11: gpio@fee06000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x6000 0x100>; + st,bank-name = "PIO11"; + }; + PIO12: gpio@fee07000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x7000 0x100>; + st,bank-name = "PIO12"; + }; + }; + + pin-controller-rear { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stih415-rear-pinctrl"; + st,syscfg = <&syscfg_rear>; + ranges = <0 0xfe820000 0x8000>; + + PIO13: gpio@fe820000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0 0x100>; + st,bank-name = "PIO13"; + }; + PIO14: gpio@fe821000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x1000 0x100>; + st,bank-name = "PIO14"; + }; + PIO15: gpio@fe822000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x2000 0x100>; + st,bank-name = "PIO15"; + }; + PIO16: gpio@fe823000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x3000 0x100>; + st,bank-name = "PIO16"; + }; + PIO17: gpio@fe824000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x4000 0x100>; + st,bank-name = "PIO17"; + }; + PIO18: gpio@fe825000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x5000 0x100>; + st,bank-name = "PIO18"; + }; + + serial2 { + pinctrl_serial2: serial2-0 { + st,pins { + tx = <&PIO17 4 ALT2 OUT>; + rx = <&PIO17 5 ALT2 IN>; + }; + }; + }; + }; + + pin-controller-left { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stih415-left-pinctrl"; + st,syscfg = <&syscfg_left>; + ranges = <0 0xfd6b0000 0x3000>; + + PIO100: gpio@fd6b0000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0 0x100>; + st,bank-name = "PIO100"; + }; + PIO101: gpio@fd6b1000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x1000 0x100>; + st,bank-name = "PIO101"; + }; + PIO102: gpio@fd6b2000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x2000 0x100>; + st,bank-name = "PIO102"; + }; + }; + + pin-controller-right { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stih415-right-pinctrl"; + st,syscfg = <&syscfg_right>; + ranges = <0 0xfd330000 0x5000>; + + PIO103: gpio@fd330000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0 0x100>; + st,bank-name = "PIO103"; + }; + PIO104: gpio@fd331000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x1000 0x100>; + st,bank-name = "PIO104"; + }; + PIO105: gpio@fd332000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x2000 0x100>; + st,bank-name = "PIO105"; + }; + PIO106: gpio@fd333000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x3000 0x100>; + st,bank-name = "PIO106"; + }; + PIO107: gpio@fd334000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x4000 0x100>; + st,bank-name = "PIO107"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi new file mode 100644 index 000000000000..74ab8ded4b49 --- /dev/null +++ b/arch/arm/boot/dts/stih415.dtsi @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2013 STMicroelectronics (R&D) Limited. + * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ +#include "stih41x.dtsi" +#include "stih415-clock.dtsi" +#include "stih415-pinctrl.dtsi" +/ { + + L2: cache-controller { + compatible = "arm,pl310-cache"; + reg = <0xfffe2000 0x1000>; + arm,data-latency = <3 2 2>; + arm,tag-latency = <1 1 1>; + cache-unified; + cache-level = <2>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + ranges; + compatible = "simple-bus"; + + syscfg_sbc: sbc-syscfg@fe600000{ + compatible = "st,stih415-sbc-syscfg", "syscon"; + reg = <0xfe600000 0xb4>; + }; + + syscfg_front: front-syscfg@fee10000{ + compatible = "st,stih415-front-syscfg", "syscon"; + reg = <0xfee10000 0x194>; + }; + + syscfg_rear: rear-syscfg@fe830000{ + compatible = "st,stih415-rear-syscfg", "syscon"; + reg = <0xfe830000 0x190>; + }; + + /* MPE syscfgs */ + syscfg_left: left-syscfg@fd690000{ + compatible = "st,stih415-left-syscfg", "syscon"; + reg = <0xfd690000 0x78>; + }; + + syscfg_right: right-syscfg@fd320000{ + compatible = "st,stih415-right-syscfg", "syscon"; + reg = <0xfd320000 0x180>; + }; + + syscfg_system: system-syscfg@fdde0000 { + compatible = "st,stih415-system-syscfg", "syscon"; + reg = <0xfdde0000 0x15c>; + }; + + syscfg_lpm: lpm-syscfg@fe4b5100{ + compatible = "st,stih415-lpm-syscfg", "syscon"; + reg = <0xfe4b5100 0x08>; + }; + + serial2: serial@fed32000 { + compatible = "st,asc"; + status = "disabled"; + reg = <0xfed32000 0x2c>; + interrupts = <0 197 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_serial2>; + clocks = <&CLKS_ICN_REG_0>; + }; + + /* SBC comms block ASCs in SASG1 */ + sbc_serial1: serial@fe531000 { + compatible = "st,asc"; + status = "disabled"; + reg = <0xfe531000 0x2c>; + interrupts = <0 210 0>; + clocks = <&CLK_SYSIN>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sbc_serial1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/stih416-b2000.dts b/arch/arm/boot/dts/stih416-b2000.dts new file mode 100644 index 000000000000..a5eb6eee10bf --- /dev/null +++ b/arch/arm/boot/dts/stih416-b2000.dts @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2013 STMicroelectronics (R&D) Limited. + * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ +/dts-v1/; +#include "stih416.dtsi" +#include "stih41x-b2000.dtsi" + +/ { + compatible = "st,stih416", "st,stih416-b2000"; + model = "STiH416 B2000"; +}; diff --git a/arch/arm/boot/dts/stih416-b2020.dts b/arch/arm/boot/dts/stih416-b2020.dts new file mode 100644 index 000000000000..276f28da573a --- /dev/null +++ b/arch/arm/boot/dts/stih416-b2020.dts @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2013 STMicroelectronics (R&D) Limited. + * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ +/dts-v1/; +#include "stih416.dtsi" +#include "stih41x-b2020.dtsi" +/ { + model = "STiH416 B2020"; + compatible = "st,stih416", "st,stih416-b2020"; + +}; diff --git a/arch/arm/boot/dts/stih416-clock.dtsi b/arch/arm/boot/dts/stih416-clock.dtsi new file mode 100644 index 000000000000..7026bf1158d8 --- /dev/null +++ b/arch/arm/boot/dts/stih416-clock.dtsi @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2013 STMicroelectronics R&D Limited + * <stlinux-devel@stlinux.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/ { + clocks { + /* + * Fixed 30MHz oscillator inputs to SoC + */ + CLK_SYSIN: CLK_SYSIN { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <30000000>; + clock-output-names = "CLK_SYSIN"; + }; + + /* + * ARM Peripheral clock for timers + */ + arm_periph_clk: arm_periph_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <600000000>; + }; + + /* + * Bootloader initialized system infrastructure clock for + * serial devices. + */ + CLK_S_ICN_REG_0: clockgenA0@4 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + clock-output-names = "CLK_S_ICN_REG_0"; + }; + }; +}; diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi new file mode 100644 index 000000000000..957b21a71b4b --- /dev/null +++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi @@ -0,0 +1,295 @@ + +/* + * Copyright (C) 2013 STMicroelectronics Limited. + * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ +#include "st-pincfg.h" +/ { + + aliases { + gpio0 = &PIO0; + gpio1 = &PIO1; + gpio2 = &PIO2; + gpio3 = &PIO3; + gpio4 = &PIO4; + gpio5 = &PIO40; + gpio6 = &PIO5; + gpio7 = &PIO6; + gpio8 = &PIO7; + gpio9 = &PIO8; + gpio10 = &PIO9; + gpio11 = &PIO10; + gpio12 = &PIO11; + gpio13 = &PIO12; + gpio14 = &PIO30; + gpio15 = &PIO31; + gpio16 = &PIO13; + gpio17 = &PIO14; + gpio18 = &PIO15; + gpio19 = &PIO16; + gpio20 = &PIO17; + gpio21 = &PIO18; + gpio22 = &PIO100; + gpio23 = &PIO101; + gpio24 = &PIO102; + gpio25 = &PIO103; + gpio26 = &PIO104; + gpio27 = &PIO105; + gpio28 = &PIO106; + gpio29 = &PIO107; + }; + + soc { + pin-controller-sbc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stih416-sbc-pinctrl"; + st,syscfg = <&syscfg_sbc>; + ranges = <0 0xfe610000 0x6000>; + + PIO0: gpio@fe610000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0 0x100>; + st,bank-name = "PIO0"; + }; + PIO1: gpio@fe611000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x1000 0x100>; + st,bank-name = "PIO1"; + }; + PIO2: gpio@fe612000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x2000 0x100>; + st,bank-name = "PIO2"; + }; + PIO3: gpio@fe613000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x3000 0x100>; + st,bank-name = "PIO3"; + }; + PIO4: gpio@fe614000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x4000 0x100>; + st,bank-name = "PIO4"; + }; + PIO40: gpio@fe615000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x5000 0x100>; + st,bank-name = "PIO40"; + st,retime-pin-mask = <0x7f>; + }; + + sbc_serial1 { + pinctrl_sbc_serial1: sbc_serial1 { + st,pins { + tx = <&PIO2 6 ALT3 OUT>; + rx = <&PIO2 7 ALT3 IN>; + }; + }; + }; + }; + + pin-controller-front { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stih416-front-pinctrl"; + st,syscfg = <&syscfg_front>; + ranges = <0 0xfee00000 0x10000>; + + PIO5: gpio@fee00000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0 0x100>; + st,bank-name = "PIO5"; + }; + PIO6: gpio@fee01000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x1000 0x100>; + st,bank-name = "PIO6"; + }; + PIO7: gpio@fee02000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x2000 0x100>; + st,bank-name = "PIO7"; + }; + PIO8: gpio@fee03000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x3000 0x100>; + st,bank-name = "PIO8"; + }; + PIO9: gpio@fee04000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x4000 0x100>; + st,bank-name = "PIO9"; + }; + PIO10: gpio@fee05000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x5000 0x100>; + st,bank-name = "PIO10"; + }; + PIO11: gpio@fee06000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x6000 0x100>; + st,bank-name = "PIO11"; + }; + PIO12: gpio@fee07000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x7000 0x100>; + st,bank-name = "PIO12"; + }; + PIO30: gpio@fee08000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x8000 0x100>; + st,bank-name = "PIO30"; + }; + PIO31: gpio@fee09000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x9000 0x100>; + st,bank-name = "PIO31"; + }; + }; + + pin-controller-rear { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stih416-rear-pinctrl"; + st,syscfg = <&syscfg_rear>; + ranges = <0 0xfe820000 0x6000>; + + PIO13: gpio@fe820000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0 0x100>; + st,bank-name = "PIO13"; + }; + PIO14: gpio@fe821000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x1000 0x100>; + st,bank-name = "PIO14"; + }; + PIO15: gpio@fe822000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x2000 0x100>; + st,bank-name = "PIO15"; + }; + PIO16: gpio@fe823000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x3000 0x100>; + st,bank-name = "PIO16"; + }; + PIO17: gpio@fe824000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x4000 0x100>; + st,bank-name = "PIO17"; + }; + PIO18: gpio@fe825000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x5000 0x100>; + st,bank-name = "PIO18"; + st,retime-pin-mask = <0xf>; + }; + + serial2 { + pinctrl_serial2: serial2-0 { + st,pins { + tx = <&PIO17 4 ALT2 OUT>; + rx = <&PIO17 5 ALT2 IN>; + output-enable = <&PIO11 3 ALT2 OUT>; + }; + }; + }; + }; + + pin-controller-fvdp-fe { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stih416-fvdp-fe-pinctrl"; + st,syscfg = <&syscfg_fvdp_fe>; + ranges = <0 0xfd6b0000 0x3000>; + + PIO100: gpio@fd6b0000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0 0x100>; + st,bank-name = "PIO100"; + }; + PIO101: gpio@fd6b1000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x1000 0x100>; + st,bank-name = "PIO101"; + }; + PIO102: gpio@fd6b2000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x2000 0x100>; + st,bank-name = "PIO102"; + }; + }; + + pin-controller-fvdp-lite { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stih416-fvdp-lite-pinctrl"; + st,syscfg = <&syscfg_fvdp_lite>; + ranges = <0 0xfd330000 0x5000>; + + PIO103: gpio@fd330000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0 0x100>; + st,bank-name = "PIO103"; + }; + PIO104: gpio@fd331000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x1000 0x100>; + st,bank-name = "PIO104"; + }; + PIO105: gpio@fd332000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x2000 0x100>; + st,bank-name = "PIO105"; + }; + PIO106: gpio@fd333000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x3000 0x100>; + st,bank-name = "PIO106"; + }; + + PIO107: gpio@fd334000 { + gpio-controller; + #gpio-cells = <1>; + reg = <0x4000 0x100>; + st,bank-name = "PIO107"; + st,retime-pin-mask = <0xf>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi new file mode 100644 index 000000000000..3cecd9689a49 --- /dev/null +++ b/arch/arm/boot/dts/stih416.dtsi @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2012 STMicroelectronics Limited. + * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ +#include "stih41x.dtsi" +#include "stih416-clock.dtsi" +#include "stih416-pinctrl.dtsi" +/ { + L2: cache-controller { + compatible = "arm,pl310-cache"; + reg = <0xfffe2000 0x1000>; + arm,data-latency = <3 3 3>; + arm,tag-latency = <2 2 2>; + cache-unified; + cache-level = <2>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + ranges; + compatible = "simple-bus"; + + syscfg_sbc:sbc-syscfg@fe600000{ + compatible = "st,stih416-sbc-syscfg", "syscon"; + reg = <0xfe600000 0x1000>; + }; + + syscfg_front:front-syscfg@fee10000{ + compatible = "st,stih416-front-syscfg", "syscon"; + reg = <0xfee10000 0x1000>; + }; + + syscfg_rear:rear-syscfg@fe830000{ + compatible = "st,stih416-rear-syscfg", "syscon"; + reg = <0xfe830000 0x1000>; + }; + + /* MPE */ + syscfg_fvdp_fe:fvdp-fe-syscfg@fddf0000{ + compatible = "st,stih416-fvdp-fe-syscfg", "syscon"; + reg = <0xfddf0000 0x1000>; + }; + + syscfg_fvdp_lite:fvdp-lite-syscfg@fd6a0000{ + compatible = "st,stih416-fvdp-lite-syscfg", "syscon"; + reg = <0xfd6a0000 0x1000>; + }; + + syscfg_cpu:cpu-syscfg@fdde0000{ + compatible = "st,stih416-cpu-syscfg", "syscon"; + reg = <0xfdde0000 0x1000>; + }; + + syscfg_compo:compo-syscfg@fd320000{ + compatible = "st,stih416-compo-syscfg", "syscon"; + reg = <0xfd320000 0x1000>; + }; + + syscfg_transport:transport-syscfg@fd690000{ + compatible = "st,stih416-transport-syscfg", "syscon"; + reg = <0xfd690000 0x1000>; + }; + + syscfg_lpm:lpm-syscfg@fe4b5100{ + compatible = "st,stih416-lpm-syscfg", "syscon"; + reg = <0xfe4b5100 0x8>; + }; + + serial2: serial@fed32000{ + compatible = "st,asc"; + status = "disabled"; + reg = <0xfed32000 0x2c>; + interrupts = <0 197 0>; + clocks = <&CLK_S_ICN_REG_0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_serial2>; + }; + + /* SBC_UART1 */ + sbc_serial1: serial@fe531000 { + compatible = "st,asc"; + status = "disabled"; + reg = <0xfe531000 0x2c>; + interrupts = <0 210 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sbc_serial1>; + clocks = <&CLK_SYSIN>; + }; + }; +}; diff --git a/arch/arm/boot/dts/stih41x-b2000.dtsi b/arch/arm/boot/dts/stih41x-b2000.dtsi new file mode 100644 index 000000000000..8e694d2b8f5b --- /dev/null +++ b/arch/arm/boot/dts/stih41x-b2000.dtsi @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2013 STMicroelectronics (R&D) Limited. + * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ +/ { + + memory{ + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + chosen { + bootargs = "console=ttyAS0,115200"; + linux,stdout-path = &serial2; + }; + + aliases { + ttyAS0 = &serial2; + }; + + soc { + serial2: serial@fed32000 { + status = "okay"; + }; + + leds { + compatible = "gpio-leds"; + fp_led { + #gpio-cells = <1>; + label = "Front Panel LED"; + gpios = <&PIO105 7>; + linux,default-trigger = "heartbeat"; + }; + }; + + }; +}; diff --git a/arch/arm/boot/dts/stih41x-b2020.dtsi b/arch/arm/boot/dts/stih41x-b2020.dtsi new file mode 100644 index 000000000000..133e18143b1b --- /dev/null +++ b/arch/arm/boot/dts/stih41x-b2020.dtsi @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2013 STMicroelectronics (R&D) Limited. + * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ +/ { + memory{ + device_type = "memory"; + reg = <0x40000000 0x80000000>; + }; + + chosen { + bootargs = "console=ttyAS0,115200"; + linux,stdout-path = &sbc_serial1; + }; + + aliases { + ttyAS0 = &sbc_serial1; + }; + soc { + sbc_serial1: serial@fe531000 { + status = "okay"; + }; + + leds { + compatible = "gpio-leds"; + red { + #gpio-cells = <1>; + label = "Front Panel LED"; + gpios = <&PIO4 1>; + linux,default-trigger = "heartbeat"; + }; + green { + gpios = <&PIO4 7>; + default-state = "off"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/stih41x.dtsi b/arch/arm/boot/dts/stih41x.dtsi new file mode 100644 index 000000000000..7321403cab8a --- /dev/null +++ b/arch/arm/boot/dts/stih41x.dtsi @@ -0,0 +1,38 @@ +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "arm,cortex-a9"; + reg = <0>; + }; + cpu@1 { + compatible = "arm,cortex-a9"; + reg = <1>; + }; + }; + + intc: interrupt-controller@fffe1000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xfffe1000 0x1000>, + <0xfffe0100 0x100>; + }; + + scu@fffe0000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xfffe0000 0x1000>; + }; + + timer@fffe0200 { + interrupt-parent = <&intc>; + compatible = "arm,cortex-a9-global-timer"; + reg = <0xfffe0200 0x100>; + interrupts = <1 11 0x04>; + clocks = <&arm_periph_clk>; + }; +}; |