diff options
Diffstat (limited to 'arch/arm/mach-omap1')
75 files changed, 2137 insertions, 2842 deletions
diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig index 208c700c2455..538a960257cc 100644 --- a/arch/arm/mach-omap1/Kconfig +++ b/arch/arm/mach-omap1/Kconfig @@ -1,4 +1,17 @@ # SPDX-License-Identifier: GPL-2.0-only +menuconfig ARCH_OMAP1 + bool "TI OMAP1" + depends on ARCH_MULTI_V4T || ARCH_MULTI_V5 + depends on CPU_LITTLE_ENDIAN + depends on ATAGS + select ARCH_HAS_HOLES_MEMORYMODEL + select ARCH_OMAP + select CLKSRC_MMIO + select FORCE_PCI if PCCARD + select GPIOLIB + help + Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) + if ARCH_OMAP1 menu "TI OMAP1 specific features" @@ -6,28 +19,41 @@ menu "TI OMAP1 specific features" comment "OMAP Core Type" config ARCH_OMAP730 + depends on ARCH_MULTI_V5 bool "OMAP730 Based System" select ARCH_OMAP_OTG select CPU_ARM926T select OMAP_MPU_TIMER config ARCH_OMAP850 + depends on ARCH_MULTI_V5 bool "OMAP850 Based System" select ARCH_OMAP_OTG select CPU_ARM926T config ARCH_OMAP15XX + depends on ARCH_MULTI_V4T default y bool "OMAP15xx Based System" select CPU_ARM925T select OMAP_MPU_TIMER config ARCH_OMAP16XX + depends on ARCH_MULTI_V5 bool "OMAP16xx Based System" select ARCH_OMAP_OTG select CPU_ARM926T select OMAP_DM_TIMER +config ARCH_OMAP1_ANY + select ARCH_OMAP + def_bool ARCH_OMAP730 || ARCH_OMAP850 || ARCH_OMAP15XX || ARCH_OMAP16XX + +config ARCH_OMAP + bool + +comment "OMAP Feature Selections" + config OMAP_MUX bool "OMAP multiplexing support" default y @@ -53,11 +79,60 @@ config OMAP_MUX_WARNINGS to change the pin multiplexing setup. When there are no warnings printed, it's safe to deselect OMAP_MUX for your product. +config OMAP_32K_TIMER + bool "Use 32KHz timer" + depends on ARCH_OMAP16XX + default ARCH_OMAP16XX + help + Select this option if you want to enable the OMAP 32KHz timer. + This timer saves power compared to the OMAP_MPU_TIMER, and has + support for no tick during idle. The 32KHz timer provides less + intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is + currently only available for OMAP16XX, 24XX, 34XX, OMAP4/5 and DRA7XX. + + On OMAP2PLUS this value is only used for CONFIG_HZ and + CLOCK_TICK_RATE compile time calculation. + The actual timer selection is done in the board file + through the (DT_)MACHINE_START structure. + +config OMAP_MPU_TIMER + bool "Use mpu timer" + depends on ARCH_OMAP1 + help + Select this option if you want to use the OMAP mpu timer. This + timer provides more intra-tick resolution than the 32KHz timer, + but consumes more power. + +config OMAP_SERIAL_WAKE + bool "Enable wake-up events for serial ports" + depends on ARCH_OMAP1 && OMAP_MUX + default y + help + Select this option if you want to have your system wake up + to data on the serial RX line. This allows you to wake the + system from serial console. + +config OMAP_RESET_CLOCKS + bool "Reset unused clocks during boot" + depends on ARCH_OMAP + help + Say Y if you want to reset unused clocks during boot. + This option saves power, but assumes all drivers are + using the clock framework. Broken drivers that do not + yet use clock framework may not work with this option. + If you are booting from another operating system, you + probably do not want this option enabled until your + device drivers work properly. + +config ARCH_OMAP_OTG + bool + comment "OMAP Board Type" config MACH_OMAP_INNOVATOR bool "TI Innovator" depends on ARCH_OMAP15XX || ARCH_OMAP16XX + depends on UNUSED_BOARD_FILES help TI OMAP 1510 or 1610 Innovator board support. Say Y here if you have such a board. @@ -65,6 +140,7 @@ config MACH_OMAP_INNOVATOR config MACH_OMAP_H2 bool "TI H2 Support" depends on ARCH_OMAP16XX + depends on UNUSED_BOARD_FILES help TI OMAP 1610/1611B H2 board support. Say Y here if you have such a board. @@ -72,6 +148,7 @@ config MACH_OMAP_H2 config MACH_OMAP_H3 bool "TI H3 Support" depends on ARCH_OMAP16XX + depends on UNUSED_BOARD_FILES help TI OMAP 1710 H3 board support. Say Y here if you have such a board. @@ -79,6 +156,7 @@ config MACH_OMAP_H3 config MACH_HERALD bool "HTC Herald" depends on ARCH_OMAP850 + depends on UNUSED_BOARD_FILES help HTC Herald smartphone support (AKA T-Mobile Wing, ...) @@ -92,6 +170,7 @@ config MACH_OMAP_OSK config OMAP_OSK_MISTRAL bool "Mistral QVGA board Support" depends on MACH_OMAP_OSK + depends on UNUSED_BOARD_FILES help The OSK supports an optional add-on board with a Quarter-VGA touchscreen, PDA-ish buttons, a resume button, bicolor LED, @@ -100,6 +179,7 @@ config OMAP_OSK_MISTRAL config MACH_OMAP_PERSEUS2 bool "TI Perseus2" depends on ARCH_OMAP730 + depends on UNUSED_BOARD_FILES help Support for TI OMAP 730 Perseus2 board. Say Y here if you have such a board. @@ -107,6 +187,7 @@ config MACH_OMAP_PERSEUS2 config MACH_OMAP_FSAMPLE bool "TI F-Sample" depends on ARCH_OMAP730 + depends on UNUSED_BOARD_FILES help Support for TI OMAP 850 F-Sample board. Say Y here if you have such a board. @@ -123,6 +204,7 @@ config MACH_OMAP_PALMTE config MACH_OMAP_PALMZ71 bool "Palm Zire71" depends on ARCH_OMAP15XX + depends on UNUSED_BOARD_FILES help Support for the Palm Zire71 PDA. To boot the kernel, you'll need a PalmOS compatible bootloader; check out @@ -132,6 +214,7 @@ config MACH_OMAP_PALMZ71 config MACH_OMAP_PALMTT bool "Palm Tungsten|T" depends on ARCH_OMAP15XX + depends on UNUSED_BOARD_FILES help Support for the Palm Tungsten|T PDA. To boot the kernel, you'll need a PalmOS compatible bootloader (Garux); check out @@ -172,6 +255,7 @@ config MACH_AMS_DELTA config MACH_OMAP_GENERIC bool "Generic OMAP board" depends on ARCH_OMAP15XX || ARCH_OMAP16XX + depends on UNUSED_BOARD_FILES help Support for generic OMAP-1510, 1610 or 1710 board with no FPGA. Can be used as template for porting Linux to diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile index c757a52d0801..506074b86333 100644 --- a/arch/arm/mach-omap1/Makefile +++ b/arch/arm/mach-omap1/Makefile @@ -3,9 +3,11 @@ # Makefile for the linux kernel. # +ifdef CONFIG_ARCH_OMAP1_ANY + # Common support obj-y := io.o id.o sram-init.o sram.o time.o irq.o mux.o flash.o \ - serial.o devices.o dma.o fb.o + serial.o devices.o dma.o omap-dma.o fb.o obj-y += clock.o clock_data.o opp_data.o reset.o pm_bus.o timer.o ifneq ($(CONFIG_SND_SOC_OMAP_MCBSP),) @@ -58,6 +60,4 @@ obj-$(CONFIG_ARCH_OMAP850) += gpio7xx.o obj-$(CONFIG_ARCH_OMAP15XX) += gpio15xx.o obj-$(CONFIG_ARCH_OMAP16XX) += gpio16xx.o -ifneq ($(CONFIG_FB_OMAP),) -obj-y += lcd_dma.o endif diff --git a/arch/arm/mach-omap1/Makefile.boot b/arch/arm/mach-omap1/Makefile.boot deleted file mode 100644 index 2c771515a606..000000000000 --- a/arch/arm/mach-omap1/Makefile.boot +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - zreladdr-y += 0x10008000 -params_phys-y := 0x10000100 -initrd_phys-y := 0x10800000 diff --git a/arch/arm/mach-omap1/ams-delta-fiq-handler.S b/arch/arm/mach-omap1/ams-delta-fiq-handler.S index f745a65d3bd7..35c2f9574dbd 100644 --- a/arch/arm/mach-omap1/ams-delta-fiq-handler.S +++ b/arch/arm/mach-omap1/ams-delta-fiq-handler.S @@ -13,14 +13,15 @@ #include <linux/linkage.h> #include <linux/platform_data/ams-delta-fiq.h> #include <linux/platform_data/gpio-omap.h> +#include <linux/soc/ti/omap1-io.h> #include <asm/assembler.h> #include <asm/irq.h> +#include "hardware.h" #include "ams-delta-fiq.h" #include "board-ams-delta.h" #include "iomap.h" -#include "soc.h" /* * OMAP1510 GPIO related symbol copied from arch/arm/mach-omap1/gpio15xx.c. diff --git a/arch/arm/mach-omap1/ams-delta-fiq.c b/arch/arm/mach-omap1/ams-delta-fiq.c index 4eea3e39e633..1f5852be057e 100644 --- a/arch/arm/mach-omap1/ams-delta-fiq.c +++ b/arch/arm/mach-omap1/ams-delta-fiq.c @@ -21,7 +21,9 @@ #include <linux/platform_device.h> #include <asm/fiq.h> +#include <linux/soc/ti/omap1-io.h> +#include "hardware.h" #include "ams-delta-fiq.h" #include "board-ams-delta.h" diff --git a/arch/arm/mach-omap1/ams-delta-fiq.h b/arch/arm/mach-omap1/ams-delta-fiq.h index fd76df3cce37..7f843caedb7c 100644 --- a/arch/arm/mach-omap1/ams-delta-fiq.h +++ b/arch/arm/mach-omap1/ams-delta-fiq.h @@ -16,7 +16,7 @@ #ifndef __AMS_DELTA_FIQ_H #define __AMS_DELTA_FIQ_H -#include <mach/irqs.h> +#include "irqs.h" /* * Interrupt number used for passing control from FIQ to IRQ. diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c index 1026a816dcc0..651c28d81132 100644 --- a/arch/arm/mach-omap1/board-ams-delta.c +++ b/arch/arm/mach-omap1/board-ams-delta.c @@ -28,6 +28,7 @@ #include <linux/omapfb.h> #include <linux/io.h> #include <linux/platform_data/gpio-omap.h> +#include <linux/soc/ti/omap1-mux.h> #include <asm/serial.h> #include <asm/mach-types.h> @@ -35,11 +36,9 @@ #include <asm/mach/map.h> #include <linux/platform_data/keypad-omap.h> -#include <mach/mux.h> - -#include <mach/hardware.h> -#include <mach/usb.h> +#include "hardware.h" +#include "usb.h" #include "ams-delta-fiq.h" #include "board-ams-delta.h" #include "iomap.h" @@ -407,9 +406,6 @@ static struct gpio_led gpio_leds[] __initdata = { [LATCH1_PIN_LED_CAMERA] = { .name = "camera", .default_state = LEDS_GPIO_DEFSTATE_OFF, -#ifdef CONFIG_LEDS_TRIGGERS - .default_trigger = "ams_delta_camera", -#endif }, [LATCH1_PIN_LED_ADVERT] = { .name = "advert", @@ -456,10 +452,6 @@ static struct gpiod_lookup_table leds_gpio_table = { }, }; -#ifdef CONFIG_LEDS_TRIGGERS -DEFINE_LED_TRIGGER(ams_delta_camera_led_trigger); -#endif - static struct platform_device ams_delta_audio_device = { .name = "ams-delta-audio", .id = -1, @@ -672,7 +664,7 @@ static void __init ams_delta_latch2_init(void) { u16 latch2 = 1 << LATCH2_PIN_MODEM_NRESET | 1 << LATCH2_PIN_MODEM_CODEC; - __raw_writew(latch2, LATCH2_VIRT); + __raw_writew(latch2, IOMEM(LATCH2_VIRT)); } static void __init ams_delta_init(void) @@ -705,10 +697,6 @@ static void __init ams_delta_init(void) omap_register_i2c_bus(1, 100, NULL, 0); omap1_usb_init(&ams_delta_usb_config); -#ifdef CONFIG_LEDS_TRIGGERS - led_trigger_register_simple("ams_delta_camera", - &ams_delta_camera_led_trigger); -#endif platform_add_devices(ams_delta_devices, ARRAY_SIZE(ams_delta_devices)); /* diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c index c3aa6f2e5546..f21e15c7b973 100644 --- a/arch/arm/mach-omap1/board-fsample.c +++ b/arch/arm/mach-omap1/board-fsample.c @@ -23,13 +23,13 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <mach/tc.h> -#include <mach/mux.h> -#include "flash.h" +#include <linux/soc/ti/omap1-io.h> #include <linux/platform_data/keypad-omap.h> +#include "tc.h" -#include <mach/hardware.h> - +#include "mux.h" +#include "flash.h" +#include "hardware.h" #include "iomap.h" #include "common.h" #include "fpga.h" diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c index c62554990115..3b2bcaf4bb01 100644 --- a/arch/arm/mach-omap1/board-generic.c +++ b/arch/arm/mach-omap1/board-generic.c @@ -14,15 +14,13 @@ #include <linux/init.h> #include <linux/platform_device.h> -#include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <mach/mux.h> - -#include <mach/usb.h> - +#include "hardware.h" +#include "mux.h" +#include "usb.h" #include "common.h" /* assume no Mini-AB port */ diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c index 977b0b744c22..f28a4c3ea501 100644 --- a/arch/arm/mach-omap1/board-h2.c +++ b/arch/arm/mach-omap1/board-h2.c @@ -28,22 +28,20 @@ #include <linux/mfd/tps65010.h> #include <linux/smc91x.h> #include <linux/omapfb.h> +#include <linux/omap-dma.h> #include <linux/platform_data/gpio-omap.h> +#include <linux/platform_data/keypad-omap.h> #include <linux/leds.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <mach/mux.h> -#include <linux/omap-dma.h> -#include <mach/tc.h> -#include <linux/platform_data/keypad-omap.h> +#include "tc.h" +#include "mux.h" #include "flash.h" - -#include <mach/hardware.h> -#include <mach/usb.h> - +#include "hardware.h" +#include "usb.h" #include "common.h" #include "board-h2.h" diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c index 4249984f9c30..1e4c57710fcc 100644 --- a/arch/arm/mach-omap1/board-h3.c +++ b/arch/arm/mach-omap1/board-h3.c @@ -29,6 +29,8 @@ #include <linux/smc91x.h> #include <linux/omapfb.h> #include <linux/platform_data/gpio-omap.h> +#include <linux/platform_data/keypad-omap.h> +#include <linux/omap-dma.h> #include <linux/leds.h> #include <asm/setup.h> @@ -37,16 +39,12 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <mach/mux.h> -#include <mach/tc.h> -#include <linux/platform_data/keypad-omap.h> -#include <linux/omap-dma.h> +#include "tc.h" +#include "mux.h" #include "flash.h" - -#include <mach/hardware.h> -#include <mach/irqs.h> -#include <mach/usb.h> - +#include "hardware.h" +#include "irqs.h" +#include "usb.h" #include "common.h" #include "board-h3.h" diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c index 258304edf23e..291d294b5824 100644 --- a/arch/arm/mach-omap1/board-htcherald.c +++ b/arch/arm/mach-omap1/board-htcherald.c @@ -23,16 +23,16 @@ #include <linux/spi/ads7846.h> #include <linux/omapfb.h> #include <linux/platform_data/keypad-omap.h> +#include <linux/soc/ti/omap1-io.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> -#include <mach/omap7xx.h> +#include "hardware.h" +#include "omap7xx.h" #include "mmc.h" - -#include <mach/irqs.h> -#include <mach/usb.h> - +#include "irqs.h" +#include "usb.h" #include "common.h" /* LCD register definition */ @@ -141,13 +141,6 @@ #define HTCPLD_GPIO_DOWN_DPAD HTCPLD_BASE(7, 4) #define HTCPLD_GPIO_ENTER_DPAD HTCPLD_BASE(7, 3) -/* - * The htcpld chip requires a gpio write to a specific line - * to re-enable interrupts after one has occurred. - */ -#define HTCPLD_GPIO_INT_RESET_HI HTCPLD_BASE(2, 7) -#define HTCPLD_GPIO_INT_RESET_LO HTCPLD_BASE(2, 0) - /* Chip 5 */ #define HTCPLD_IRQ_RIGHT_KBD HTCPLD_IRQ(0, 7) #define HTCPLD_IRQ_UP_KBD HTCPLD_IRQ(0, 6) @@ -170,7 +163,7 @@ static const unsigned int htc_herald_keymap[] = { KEY(3, 0, KEY_VOLUMEUP), /* Volume up */ KEY(4, 0, KEY_F2), /* Right bar (landscape) */ KEY(5, 0, KEY_MAIL), /* Win key (portrait) */ - KEY(6, 0, KEY_DIRECTORY), /* Right bar (protrait) */ + KEY(6, 0, KEY_DIRECTORY), /* Right bar (portrait) */ KEY(0, 1, KEY_LEFTCTRL), /* Windows key */ KEY(1, 1, KEY_COMMA), KEY(2, 1, KEY_M), @@ -348,8 +341,6 @@ static struct htcpld_chip_platform_data htcpld_chips[] = { }; static struct htcpld_core_platform_data htcpld_pfdata = { - .int_reset_gpio_hi = HTCPLD_GPIO_INT_RESET_HI, - .int_reset_gpio_lo = HTCPLD_GPIO_INT_RESET_LO, .i2c_adapter_id = 1, .chip = htcpld_chips, diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c index cbe093f969d5..6deb4ca079e9 100644 --- a/arch/arm/mach-omap1/board-innovator.c +++ b/arch/arm/mach-omap1/board-innovator.c @@ -23,19 +23,17 @@ #include <linux/input.h> #include <linux/smc91x.h> #include <linux/omapfb.h> +#include <linux/platform_data/keypad-omap.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <mach/mux.h> +#include "tc.h" +#include "mux.h" #include "flash.h" -#include <mach/tc.h> -#include <linux/platform_data/keypad-omap.h> - -#include <mach/hardware.h> -#include <mach/usb.h> - +#include "hardware.h" +#include "usb.h" #include "iomap.h" #include "common.h" #include "mmc.h" @@ -194,6 +192,9 @@ static struct platform_device innovator1510_smc91x_device = { static struct platform_device innovator1510_lcd_device = { .name = "lcd_inn1510", .id = -1, + .dev = { + .platform_data = (void __force *)OMAP1510_FPGA_LCD_PANEL_CONTROL, + } }; static struct platform_device innovator1510_spi_device = { @@ -287,6 +288,23 @@ static void __init innovator_init_smc91x(void) } #ifdef CONFIG_ARCH_OMAP15XX +/* + * Board specific gang-switched transceiver power on/off. + */ +static int innovator_omap_ohci_transceiver_power(int on) +{ + if (on) + __raw_writeb(__raw_readb(INNOVATOR_FPGA_CAM_USB_CONTROL) + | ((1 << 5/*usb1*/) | (1 << 3/*usb2*/)), + INNOVATOR_FPGA_CAM_USB_CONTROL); + else + __raw_writeb(__raw_readb(INNOVATOR_FPGA_CAM_USB_CONTROL) + & ~((1 << 5/*usb1*/) | (1 << 3/*usb2*/)), + INNOVATOR_FPGA_CAM_USB_CONTROL); + + return 0; +} + static struct omap_usb_config innovator1510_usb_config __initdata = { /* for bundled non-standard host and peripheral cables */ .hmc_mode = 4, @@ -297,6 +315,8 @@ static struct omap_usb_config innovator1510_usb_config __initdata = { .register_dev = 1, .pins[0] = 2, + + .transceiver_power = innovator_omap_ohci_transceiver_power, }; static const struct omap_lcd_config innovator1510_lcd_config __initconst = { diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c index 11511ae2e0a2..8e0e58495023 100644 --- a/arch/arm/mach-omap1/board-nokia770.c +++ b/arch/arm/mach-omap1/board-nokia770.c @@ -28,11 +28,9 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <mach/mux.h> - -#include <mach/hardware.h> -#include <mach/usb.h> - +#include "mux.h" +#include "hardware.h" +#include "usb.h" #include "common.h" #include "clock.h" #include "mmc.h" diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index e18b6f13300e..76684b7a4e87 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c @@ -42,18 +42,17 @@ #include <linux/mfd/tps65010.h> #include <linux/platform_data/gpio-omap.h> #include <linux/platform_data/omap1_bl.h> +#include <linux/soc/ti/omap1-io.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> +#include "tc.h" #include "flash.h" -#include <mach/mux.h> -#include <mach/tc.h> - -#include <mach/hardware.h> -#include <mach/usb.h> - +#include "mux.h" +#include "hardware.h" +#include "usb.h" #include "common.h" /* Name of the GPIO chip used by the OMAP for GPIOs 0..15 */ @@ -153,14 +152,14 @@ static struct resource osk5912_cf_resources[] = { [0] = { .flags = IORESOURCE_IRQ, }, + [1] = { + .flags = IORESOURCE_MEM, + }, }; static struct platform_device osk5912_cf_device = { .name = "omap_cf", .id = -1, - .dev = { - .platform_data = (void *) 2 /* CS2 */, - }, .num_resources = ARRAY_SIZE(osk5912_cf_resources), .resource = osk5912_cf_resources, }; @@ -275,13 +274,41 @@ static void __init osk_init_smc91x(void) omap_writel(l, EMIFS_CCS(1)); } -static void __init osk_init_cf(void) +static void __init osk_init_cf(int seg) { + struct resource *res = &osk5912_cf_resources[1]; + omap_cfg_reg(M7_1610_GPIO62); if ((gpio_request(62, "cf_irq")) < 0) { printk("Error requesting gpio 62 for CF irq\n"); return; } + + switch (seg) { + /* NOTE: CS0 could be configured too ... */ + case 1: + res->start = OMAP_CS1_PHYS; + break; + case 2: + res->start = OMAP_CS2_PHYS; + break; + case 3: + res->start = omap_cs3_phys(); + break; + } + + res->end = res->start + SZ_8K - 1; + osk5912_cf_device.dev.platform_data = (void *)(uintptr_t)seg; + + /* NOTE: better EMIFS setup might support more cards; but the + * TRM only shows how to affect regular flash signals, not their + * CF/PCMCIA variants... + */ + pr_debug("%s: cs%d, previous ccs %08x acs %08x\n", __func__, + seg, omap_readl(EMIFS_CCS(seg)), omap_readl(EMIFS_ACS(seg))); + omap_writel(0x0004a1b3, EMIFS_CCS(seg)); /* synch mode 4 etc */ + omap_writel(0x00000000, EMIFS_ACS(seg)); /* OE hold/setup */ + /* the CF I/O IRQ is really active-low */ irq_set_irq_type(gpio_to_irq(62), IRQ_TYPE_EDGE_FALLING); } @@ -580,7 +607,7 @@ static void __init osk_init(void) u32 l; osk_init_smc91x(); - osk_init_cf(); + osk_init_cf(2); /* CS2 */ /* Workaround for wrong CS3 (NOR flash) timing * There are some U-Boot versions out there which configure diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c index ce6f0fcd9d12..72e1979c7a8b 100644 --- a/arch/arm/mach-omap1/board-palmte.c +++ b/arch/arm/mach-omap1/board-palmte.c @@ -25,21 +25,19 @@ #include <linux/interrupt.h> #include <linux/apm-emulation.h> #include <linux/omapfb.h> +#include <linux/omap-dma.h> +#include <linux/platform_data/keypad-omap.h> #include <linux/platform_data/omap1_bl.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> +#include "tc.h" #include "flash.h" -#include <mach/mux.h> -#include <mach/tc.h> -#include <linux/omap-dma.h> -#include <linux/platform_data/keypad-omap.h> - -#include <mach/hardware.h> -#include <mach/usb.h> - +#include "mux.h" +#include "hardware.h" +#include "usb.h" #include "mmc.h" #include "common.h" diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c index 8a08311c4e05..537f0e6a2ff7 100644 --- a/arch/arm/mach-omap1/board-palmtt.c +++ b/arch/arm/mach-omap1/board-palmtt.c @@ -24,22 +24,20 @@ #include <linux/omapfb.h> #include <linux/spi/spi.h> #include <linux/spi/ads7846.h> +#include <linux/omap-dma.h> #include <linux/platform_data/omap1_bl.h> #include <linux/platform_data/leds-omap.h> +#include <linux/platform_data/keypad-omap.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> +#include "tc.h" #include "flash.h" -#include <mach/mux.h> -#include <linux/omap-dma.h> -#include <mach/tc.h> -#include <linux/platform_data/keypad-omap.h> - -#include <mach/hardware.h> -#include <mach/usb.h> - +#include "mux.h" +#include "hardware.h" +#include "usb.h" #include "common.h" #define PALMTT_USBDETECT_GPIO 0 diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c index 034e5bc6a029..47f08ae5a2f3 100644 --- a/arch/arm/mach-omap1/board-palmz71.c +++ b/arch/arm/mach-omap1/board-palmz71.c @@ -28,20 +28,18 @@ #include <linux/spi/spi.h> #include <linux/spi/ads7846.h> #include <linux/platform_data/omap1_bl.h> +#include <linux/platform_data/keypad-omap.h> +#include <linux/omap-dma.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> +#include "tc.h" #include "flash.h" -#include <mach/mux.h> -#include <linux/omap-dma.h> -#include <mach/tc.h> -#include <linux/platform_data/keypad-omap.h> - -#include <mach/hardware.h> -#include <mach/usb.h> - +#include "mux.h" +#include "hardware.h" +#include "usb.h" #include "common.h" #define PALMZ71_USBDETECT_GPIO 0 diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c index 1aeeb7337d29..b041e6f6e9cf 100644 --- a/arch/arm/mach-omap1/board-perseus2.c +++ b/arch/arm/mach-omap1/board-perseus2.c @@ -19,17 +19,16 @@ #include <linux/smc91x.h> #include <linux/omapfb.h> #include <linux/platform_data/keypad-omap.h> +#include <linux/soc/ti/omap1-io.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <mach/tc.h> -#include <mach/mux.h> +#include "tc.h" +#include "mux.h" #include "flash.h" - -#include <mach/hardware.h> - +#include "hardware.h" #include "iomap.h" #include "common.h" #include "fpga.h" @@ -289,6 +288,12 @@ static void __init omap_perseus2_init(void) omap_cfg_reg(F4_7XX_KBC3); omap_cfg_reg(E3_7XX_KBC4); + if (IS_ENABLED(CONFIG_SPI_OMAP_UWIRE)) { + /* configure pins: MPU_UW_nSCS1, MPU_UW_SDO, MPU_UW_SCLK */ + int val = omap_readl(OMAP7XX_IO_CONF_9) & ~0x00EEE000; + omap_writel(val | 0x00AAA000, OMAP7XX_IO_CONF_9); + } + platform_add_devices(devices, ARRAY_SIZE(devices)); omap_serial_init(); diff --git a/arch/arm/mach-omap1/board-sx1-mmc.c b/arch/arm/mach-omap1/board-sx1-mmc.c index 6192b1da75cb..f1c160924dfe 100644 --- a/arch/arm/mach-omap1/board-sx1-mmc.c +++ b/arch/arm/mach-omap1/board-sx1-mmc.c @@ -12,9 +12,8 @@ #include <linux/gpio.h> #include <linux/platform_device.h> -#include <mach/hardware.h> +#include "hardware.h" #include "board-sx1.h" - #include "mmc.h" #if IS_ENABLED(CONFIG_MMC_OMAP) diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c index bb9ec345e204..f0dbb0e8d8e7 100644 --- a/arch/arm/mach-omap1/board-sx1.c +++ b/arch/arm/mach-omap1/board-sx1.c @@ -26,20 +26,18 @@ #include <linux/export.h> #include <linux/omapfb.h> #include <linux/platform_data/keypad-omap.h> +#include <linux/omap-dma.h> +#include "tc.h" #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include "flash.h" -#include <mach/mux.h> -#include <linux/omap-dma.h> -#include <mach/tc.h> +#include "mux.h" #include "board-sx1.h" - -#include <mach/hardware.h> -#include <mach/usb.h> - +#include "hardware.h" +#include "usb.h" #include "common.h" /* Write to I2C device */ diff --git a/arch/arm/mach-omap1/board-sx1.h b/arch/arm/mach-omap1/board-sx1.h index 355adbdaae33..fafe54a2e444 100644 --- a/arch/arm/mach-omap1/board-sx1.h +++ b/arch/arm/mach-omap1/board-sx1.h @@ -1,15 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Siemens SX1 board definitions * * Copyright: Vovan888 at gmail com - * - * This package is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. */ #ifndef __ASM_ARCH_SX1_I2C_CHIPS_H diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index 9d4a0ab50a46..83381e23fab9 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c @@ -16,11 +16,13 @@ #include <linux/io.h> #include <linux/clk.h> #include <linux/clkdev.h> +#include <linux/clk-provider.h> +#include <linux/soc/ti/omap1-io.h> +#include <linux/spinlock.h> #include <asm/mach-types.h> -#include <mach/hardware.h> - +#include "hardware.h" #include "soc.h" #include "iomap.h" #include "clock.h" @@ -28,33 +30,37 @@ #include "sram.h" __u32 arm_idlect1_mask; -struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p; +/* provide direct internal access (not via clk API) to some clocks */ +struct omap1_clk *api_ck_p, *ck_dpll1_p, *ck_ref_p; -static LIST_HEAD(clocks); -static DEFINE_MUTEX(clocks_mutex); -static DEFINE_SPINLOCK(clockfw_lock); +/* protect registeres shared among clk_enable/disable() and clk_set_rate() operations */ +static DEFINE_SPINLOCK(arm_ckctl_lock); +static DEFINE_SPINLOCK(arm_idlect2_lock); +static DEFINE_SPINLOCK(mod_conf_ctrl_0_lock); +static DEFINE_SPINLOCK(mod_conf_ctrl_1_lock); +static DEFINE_SPINLOCK(swd_clk_div_ctrl_sel_lock); /* * Omap1 specific clock functions */ -unsigned long omap1_uart_recalc(struct clk *clk) +unsigned long omap1_uart_recalc(struct omap1_clk *clk, unsigned long p_rate) { unsigned int val = __raw_readl(clk->enable_reg); - return val & clk->enable_bit ? 48000000 : 12000000; + return val & 1 << clk->enable_bit ? 48000000 : 12000000; } -unsigned long omap1_sossi_recalc(struct clk *clk) +unsigned long omap1_sossi_recalc(struct omap1_clk *clk, unsigned long p_rate) { u32 div = omap_readl(MOD_CONF_CTRL_1); div = (div >> 17) & 0x7; div++; - return clk->parent->rate / div; + return p_rate / div; } -static void omap1_clk_allow_idle(struct clk *clk) +static void omap1_clk_allow_idle(struct omap1_clk *clk) { struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk; @@ -65,7 +71,7 @@ static void omap1_clk_allow_idle(struct clk *clk) arm_idlect1_mask |= 1 << iclk->idlect_shift; } -static void omap1_clk_deny_idle(struct clk *clk) +static void omap1_clk_deny_idle(struct omap1_clk *clk) { struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk; @@ -129,7 +135,7 @@ static __u16 verify_ckctl_value(__u16 newval) return newval; } -static int calc_dsor_exp(struct clk *clk, unsigned long rate) +static int calc_dsor_exp(unsigned long rate, unsigned long realrate) { /* Note: If target frequency is too low, this function will return 4, * which is invalid value. Caller must check for this value and act @@ -142,15 +148,11 @@ static int calc_dsor_exp(struct clk *clk, unsigned long rate) * DSP_CK >= TC_CK * DSPMMU_CK >= TC_CK */ - unsigned long realrate; - struct clk * parent; unsigned dsor_exp; - parent = clk->parent; - if (unlikely(parent == NULL)) + if (unlikely(realrate == 0)) return -EIO; - realrate = parent->rate; for (dsor_exp=0; dsor_exp<4; dsor_exp++) { if (realrate <= rate) break; @@ -161,16 +163,50 @@ static int calc_dsor_exp(struct clk *clk, unsigned long rate) return dsor_exp; } -unsigned long omap1_ckctl_recalc(struct clk *clk) +unsigned long omap1_ckctl_recalc(struct omap1_clk *clk, unsigned long p_rate) { /* Calculate divisor encoded as 2-bit exponent */ int dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset)); - return clk->parent->rate / dsor; + /* update locally maintained rate, required by arm_ck for omap1_show_rates() */ + clk->rate = p_rate / dsor; + return clk->rate; +} + +static int omap1_clk_is_enabled(struct clk_hw *hw) +{ + struct omap1_clk *clk = to_omap1_clk(hw); + bool api_ck_was_enabled = true; + __u32 regval32; + int ret; + + if (!clk->ops) /* no gate -- always enabled */ + return 1; + + if (clk->ops == &clkops_dspck) { + api_ck_was_enabled = omap1_clk_is_enabled(&api_ck_p->hw); + if (!api_ck_was_enabled) + if (api_ck_p->ops->enable(api_ck_p) < 0) + return 0; + } + + if (clk->flags & ENABLE_REG_32BIT) + regval32 = __raw_readl(clk->enable_reg); + else + regval32 = __raw_readw(clk->enable_reg); + + ret = regval32 & (1 << clk->enable_bit); + + if (!api_ck_was_enabled) + api_ck_p->ops->disable(api_ck_p); + + return ret; } -unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk) + +unsigned long omap1_ckctl_recalc_dsp_domain(struct omap1_clk *clk, unsigned long p_rate) { + bool api_ck_was_enabled; int dsor; /* Calculate divisor encoded as 2-bit exponent @@ -180,15 +216,18 @@ unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk) * Note that DSP_CKCTL virt addr = phys addr, so * we must use __raw_readw() instead of omap_readw(). */ - omap1_clk_enable(api_ck_p); + api_ck_was_enabled = omap1_clk_is_enabled(&api_ck_p->hw); + if (!api_ck_was_enabled) + api_ck_p->ops->enable(api_ck_p); dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset)); - omap1_clk_disable(api_ck_p); + if (!api_ck_was_enabled) + api_ck_p->ops->disable(api_ck_p); - return clk->parent->rate / dsor; + return p_rate / dsor; } /* MPU virtual clock functions */ -int omap1_select_table_rate(struct clk *clk, unsigned long rate) +int omap1_select_table_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate) { /* Find the highest supported frequency <= rate and switch to it */ struct mpu_rate * ptr; @@ -223,12 +262,12 @@ int omap1_select_table_rate(struct clk *clk, unsigned long rate) return 0; } -int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate) +int omap1_clk_set_rate_dsp_domain(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate) { int dsor_exp; u16 regval; - dsor_exp = calc_dsor_exp(clk, rate); + dsor_exp = calc_dsor_exp(rate, p_rate); if (dsor_exp > 3) dsor_exp = -EINVAL; if (dsor_exp < 0) @@ -238,42 +277,51 @@ int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate) regval &= ~(3 << clk->rate_offset); regval |= dsor_exp << clk->rate_offset; __raw_writew(regval, DSP_CKCTL); - clk->rate = clk->parent->rate / (1 << dsor_exp); + clk->rate = p_rate / (1 << dsor_exp); return 0; } -long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate) +long omap1_clk_round_rate_ckctl_arm(struct omap1_clk *clk, unsigned long rate, + unsigned long *p_rate) { - int dsor_exp = calc_dsor_exp(clk, rate); + int dsor_exp = calc_dsor_exp(rate, *p_rate); + if (dsor_exp < 0) return dsor_exp; if (dsor_exp > 3) dsor_exp = 3; - return clk->parent->rate / (1 << dsor_exp); + return *p_rate / (1 << dsor_exp); } -int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate) +int omap1_clk_set_rate_ckctl_arm(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate) { + unsigned long flags; int dsor_exp; u16 regval; - dsor_exp = calc_dsor_exp(clk, rate); + dsor_exp = calc_dsor_exp(rate, p_rate); if (dsor_exp > 3) dsor_exp = -EINVAL; if (dsor_exp < 0) return dsor_exp; + /* protect ARM_CKCTL register from concurrent access via clk_enable/disable() */ + spin_lock_irqsave(&arm_ckctl_lock, flags); + regval = omap_readw(ARM_CKCTL); regval &= ~(3 << clk->rate_offset); regval |= dsor_exp << clk->rate_offset; regval = verify_ckctl_value(regval); omap_writew(regval, ARM_CKCTL); - clk->rate = clk->parent->rate / (1 << dsor_exp); + clk->rate = p_rate / (1 << dsor_exp); + + spin_unlock_irqrestore(&arm_ckctl_lock, flags); + return 0; } -long omap1_round_to_table_rate(struct clk *clk, unsigned long rate) +long omap1_round_to_table_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate) { /* Find the highest supported frequency <= rate */ struct mpu_rate * ptr; @@ -324,26 +372,40 @@ static unsigned calc_ext_dsor(unsigned long rate) } /* XXX Only needed on 1510 */ -int omap1_set_uart_rate(struct clk *clk, unsigned long rate) +long omap1_round_uart_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate) +{ + return rate > 24000000 ? 48000000 : 12000000; +} + +int omap1_set_uart_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate) { + unsigned long flags; unsigned int val; - val = __raw_readl(clk->enable_reg); if (rate == 12000000) - val &= ~(1 << clk->enable_bit); + val = 0; else if (rate == 48000000) - val |= (1 << clk->enable_bit); + val = 1 << clk->enable_bit; else return -EINVAL; + + /* protect MOD_CONF_CTRL_0 register from concurrent access via clk_enable/disable() */ + spin_lock_irqsave(&mod_conf_ctrl_0_lock, flags); + + val |= __raw_readl(clk->enable_reg) & ~(1 << clk->enable_bit); __raw_writel(val, clk->enable_reg); + + spin_unlock_irqrestore(&mod_conf_ctrl_0_lock, flags); + clk->rate = rate; return 0; } /* External clock (MCLK & BCLK) functions */ -int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate) +int omap1_set_ext_clk_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate) { + unsigned long flags; unsigned dsor; __u16 ratio_bits; @@ -354,25 +416,53 @@ int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate) else ratio_bits = (dsor - 2) << 2; + /* protect SWD_CLK_DIV_CTRL_SEL register from concurrent access via clk_enable/disable() */ + spin_lock_irqsave(&swd_clk_div_ctrl_sel_lock, flags); + ratio_bits |= __raw_readw(clk->enable_reg) & ~0xfd; __raw_writew(ratio_bits, clk->enable_reg); + spin_unlock_irqrestore(&swd_clk_div_ctrl_sel_lock, flags); + return 0; } -int omap1_set_sossi_rate(struct clk *clk, unsigned long rate) +static int calc_div_sossi(unsigned long rate, unsigned long p_rate) { - u32 l; int div; - unsigned long p_rate; - p_rate = clk->parent->rate; /* Round towards slower frequency */ div = (p_rate + rate - 1) / rate; - div--; + + return --div; +} + +long omap1_round_sossi_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate) +{ + int div; + + div = calc_div_sossi(rate, *p_rate); + if (div < 0) + div = 0; + else if (div > 7) + div = 7; + + return *p_rate / (div + 1); +} + +int omap1_set_sossi_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate) +{ + unsigned long flags; + u32 l; + int div; + + div = calc_div_sossi(rate, p_rate); if (div < 0 || div > 7) return -EINVAL; + /* protect MOD_CONF_CTRL_1 register from concurrent access via clk_enable/disable() */ + spin_lock_irqsave(&mod_conf_ctrl_1_lock, flags); + l = omap_readl(MOD_CONF_CTRL_1); l &= ~(7 << 17); l |= div << 17; @@ -380,15 +470,17 @@ int omap1_set_sossi_rate(struct clk *clk, unsigned long rate) clk->rate = p_rate / (div + 1); + spin_unlock_irqrestore(&mod_conf_ctrl_1_lock, flags); + return 0; } -long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate) +long omap1_round_ext_clk_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate) { return 96000000 / calc_ext_dsor(rate); } -void omap1_init_ext_clk(struct clk *clk) +int omap1_init_ext_clk(struct omap1_clk *clk) { unsigned dsor; __u16 ratio_bits; @@ -404,59 +496,59 @@ void omap1_init_ext_clk(struct clk *clk) dsor = ratio_bits + 2; clk-> rate = 96000000 / dsor; + + return 0; } -int omap1_clk_enable(struct clk *clk) +static int omap1_clk_enable(struct clk_hw *hw) { + struct omap1_clk *clk = to_omap1_clk(hw), *parent = to_omap1_clk(clk_hw_get_parent(hw)); int ret = 0; - if (clk->usecount++ == 0) { - if (clk->parent) { - ret = omap1_clk_enable(clk->parent); - if (ret) - goto err; - - if (clk->flags & CLOCK_NO_IDLE_PARENT) - omap1_clk_deny_idle(clk->parent); - } + if (parent && clk->flags & CLOCK_NO_IDLE_PARENT) + omap1_clk_deny_idle(parent); + if (clk->ops && !(WARN_ON(!clk->ops->enable))) ret = clk->ops->enable(clk); - if (ret) { - if (clk->parent) - omap1_clk_disable(clk->parent); - goto err; - } - } - return ret; -err: - clk->usecount--; return ret; } -void omap1_clk_disable(struct clk *clk) +static void omap1_clk_disable(struct clk_hw *hw) { - if (clk->usecount > 0 && !(--clk->usecount)) { + struct omap1_clk *clk = to_omap1_clk(hw), *parent = to_omap1_clk(clk_hw_get_parent(hw)); + + if (clk->ops && !(WARN_ON(!clk->ops->disable))) clk->ops->disable(clk); - if (likely(clk->parent)) { - omap1_clk_disable(clk->parent); - if (clk->flags & CLOCK_NO_IDLE_PARENT) - omap1_clk_allow_idle(clk->parent); - } - } + + if (likely(parent) && clk->flags & CLOCK_NO_IDLE_PARENT) + omap1_clk_allow_idle(parent); } -static int omap1_clk_enable_generic(struct clk *clk) +static int omap1_clk_enable_generic(struct omap1_clk *clk) { + unsigned long flags; __u16 regval16; __u32 regval32; if (unlikely(clk->enable_reg == NULL)) { printk(KERN_ERR "clock.c: Enable for %s without enable code\n", - clk->name); + clk_hw_get_name(&clk->hw)); return -EINVAL; } + /* protect clk->enable_reg from concurrent access via clk_set_rate() */ + if (clk->enable_reg == OMAP1_IO_ADDRESS(ARM_CKCTL)) + spin_lock_irqsave(&arm_ckctl_lock, flags); + else if (clk->enable_reg == OMAP1_IO_ADDRESS(ARM_IDLECT2)) + spin_lock_irqsave(&arm_idlect2_lock, flags); + else if (clk->enable_reg == OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0)) + spin_lock_irqsave(&mod_conf_ctrl_0_lock, flags); + else if (clk->enable_reg == OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1)) + spin_lock_irqsave(&mod_conf_ctrl_1_lock, flags); + else if (clk->enable_reg == OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL)) + spin_lock_irqsave(&swd_clk_div_ctrl_sel_lock, flags); + if (clk->flags & ENABLE_REG_32BIT) { regval32 = __raw_readl(clk->enable_reg); regval32 |= (1 << clk->enable_bit); @@ -467,17 +559,41 @@ static int omap1_clk_enable_generic(struct clk *clk) __raw_writew(regval16, clk->enable_reg); } + if (clk->enable_reg == OMAP1_IO_ADDRESS(ARM_CKCTL)) + spin_unlock_irqrestore(&arm_ckctl_lock, flags); + else if (clk->enable_reg == OMAP1_IO_ADDRESS(ARM_IDLECT2)) + spin_unlock_irqrestore(&arm_idlect2_lock, flags); + else if (clk->enable_reg == OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0)) + spin_unlock_irqrestore(&mod_conf_ctrl_0_lock, flags); + else if (clk->enable_reg == OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1)) + spin_unlock_irqrestore(&mod_conf_ctrl_1_lock, flags); + else if (clk->enable_reg == OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL)) + spin_unlock_irqrestore(&swd_clk_div_ctrl_sel_lock, flags); + return 0; } -static void omap1_clk_disable_generic(struct clk *clk) +static void omap1_clk_disable_generic(struct omap1_clk *clk) { + unsigned long flags; __u16 regval16; __u32 regval32; if (clk->enable_reg == NULL) return; + /* protect clk->enable_reg from concurrent access via clk_set_rate() */ + if (clk->enable_reg == OMAP1_IO_ADDRESS(ARM_CKCTL)) + spin_lock_irqsave(&arm_ckctl_lock, flags); + else if (clk->enable_reg == OMAP1_IO_ADDRESS(ARM_IDLECT2)) + spin_lock_irqsave(&arm_idlect2_lock, flags); + else if (clk->enable_reg == OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0)) + spin_lock_irqsave(&mod_conf_ctrl_0_lock, flags); + else if (clk->enable_reg == OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1)) + spin_lock_irqsave(&mod_conf_ctrl_1_lock, flags); + else if (clk->enable_reg == OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL)) + spin_lock_irqsave(&swd_clk_div_ctrl_sel_lock, flags); + if (clk->flags & ENABLE_REG_32BIT) { regval32 = __raw_readl(clk->enable_reg); regval32 &= ~(1 << clk->enable_bit); @@ -487,6 +603,17 @@ static void omap1_clk_disable_generic(struct clk *clk) regval16 &= ~(1 << clk->enable_bit); __raw_writew(regval16, clk->enable_reg); } + + if (clk->enable_reg == OMAP1_IO_ADDRESS(ARM_CKCTL)) + spin_unlock_irqrestore(&arm_ckctl_lock, flags); + else if (clk->enable_reg == OMAP1_IO_ADDRESS(ARM_IDLECT2)) + spin_unlock_irqrestore(&arm_idlect2_lock, flags); + else if (clk->enable_reg == OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0)) + spin_unlock_irqrestore(&mod_conf_ctrl_0_lock, flags); + else if (clk->enable_reg == OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1)) + spin_unlock_irqrestore(&mod_conf_ctrl_1_lock, flags); + else if (clk->enable_reg == OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL)) + spin_unlock_irqrestore(&swd_clk_div_ctrl_sel_lock, flags); } const struct clkops clkops_generic = { @@ -494,25 +621,38 @@ const struct clkops clkops_generic = { .disable = omap1_clk_disable_generic, }; -static int omap1_clk_enable_dsp_domain(struct clk *clk) +static int omap1_clk_enable_dsp_domain(struct omap1_clk *clk) { - int retval; + bool api_ck_was_enabled; + int retval = 0; + + api_ck_was_enabled = omap1_clk_is_enabled(&api_ck_p->hw); + if (!api_ck_was_enabled) + retval = api_ck_p->ops->enable(api_ck_p); - retval = omap1_clk_enable(api_ck_p); if (!retval) { retval = omap1_clk_enable_generic(clk); - omap1_clk_disable(api_ck_p); + + if (!api_ck_was_enabled) + api_ck_p->ops->disable(api_ck_p); } return retval; } -static void omap1_clk_disable_dsp_domain(struct clk *clk) +static void omap1_clk_disable_dsp_domain(struct omap1_clk *clk) { - if (omap1_clk_enable(api_ck_p) == 0) { - omap1_clk_disable_generic(clk); - omap1_clk_disable(api_ck_p); - } + bool api_ck_was_enabled; + + api_ck_was_enabled = omap1_clk_is_enabled(&api_ck_p->hw); + if (!api_ck_was_enabled) + if (api_ck_p->ops->enable(api_ck_p) < 0) + return; + + omap1_clk_disable_generic(clk); + + if (!api_ck_was_enabled) + api_ck_p->ops->disable(api_ck_p); } const struct clkops clkops_dspck = { @@ -521,7 +661,7 @@ const struct clkops clkops_dspck = { }; /* XXX SYSC register handling does not belong in the clock framework */ -static int omap1_clk_enable_uart_functional_16xx(struct clk *clk) +static int omap1_clk_enable_uart_functional_16xx(struct omap1_clk *clk) { int ret; struct uart_clk *uclk; @@ -538,7 +678,7 @@ static int omap1_clk_enable_uart_functional_16xx(struct clk *clk) } /* XXX SYSC register handling does not belong in the clock framework */ -static void omap1_clk_disable_uart_functional_16xx(struct clk *clk) +static void omap1_clk_disable_uart_functional_16xx(struct omap1_clk *clk) { struct uart_clk *uclk; @@ -555,20 +695,33 @@ const struct clkops clkops_uart_16xx = { .disable = omap1_clk_disable_uart_functional_16xx, }; -long omap1_clk_round_rate(struct clk *clk, unsigned long rate) +static unsigned long omap1_clk_recalc_rate(struct clk_hw *hw, unsigned long p_rate) { - if (clk->round_rate != NULL) - return clk->round_rate(clk, rate); + struct omap1_clk *clk = to_omap1_clk(hw); + + if (clk->recalc) + return clk->recalc(clk, p_rate); return clk->rate; } -int omap1_clk_set_rate(struct clk *clk, unsigned long rate) +static long omap1_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *p_rate) +{ + struct omap1_clk *clk = to_omap1_clk(hw); + + if (clk->round_rate != NULL) + return clk->round_rate(clk, rate, p_rate); + + return omap1_clk_recalc_rate(hw, *p_rate); +} + +static int omap1_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long p_rate) { + struct omap1_clk *clk = to_omap1_clk(hw); int ret = -EINVAL; if (clk->set_rate) - ret = clk->set_rate(clk, rate); + ret = clk->set_rate(clk, rate, p_rate); return ret; } @@ -576,340 +729,105 @@ int omap1_clk_set_rate(struct clk *clk, unsigned long rate) * Omap1 clock reset and init functions */ +static int omap1_clk_init_op(struct clk_hw *hw) +{ + struct omap1_clk *clk = to_omap1_clk(hw); + + if (clk->init) + return clk->init(clk); + + return 0; +} + #ifdef CONFIG_OMAP_RESET_CLOCKS -void omap1_clk_disable_unused(struct clk *clk) +static void omap1_clk_disable_unused(struct clk_hw *hw) { - __u32 regval32; + struct omap1_clk *clk = to_omap1_clk(hw); + const char *name = clk_hw_get_name(hw); /* Clocks in the DSP domain need api_ck. Just assume bootloader * has not enabled any DSP clocks */ if (clk->enable_reg == DSP_IDLECT2) { - pr_info("Skipping reset check for DSP domain clock \"%s\"\n", - clk->name); + pr_info("Skipping reset check for DSP domain clock \"%s\"\n", name); return; } - /* Is the clock already disabled? */ - if (clk->flags & ENABLE_REG_32BIT) - regval32 = __raw_readl(clk->enable_reg); - else - regval32 = __raw_readw(clk->enable_reg); - - if ((regval32 & (1 << clk->enable_bit)) == 0) - return; - - printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name); - clk->ops->disable(clk); + pr_info("Disabling unused clock \"%s\"... ", name); + omap1_clk_disable(hw); printk(" done\n"); } #endif +const struct clk_ops omap1_clk_gate_ops = { + .enable = omap1_clk_enable, + .disable = omap1_clk_disable, + .is_enabled = omap1_clk_is_enabled, +#ifdef CONFIG_OMAP_RESET_CLOCKS + .disable_unused = omap1_clk_disable_unused, +#endif +}; -int clk_enable(struct clk *clk) -{ - unsigned long flags; - int ret; - - if (IS_ERR_OR_NULL(clk)) - return -EINVAL; - - spin_lock_irqsave(&clockfw_lock, flags); - ret = omap1_clk_enable(clk); - spin_unlock_irqrestore(&clockfw_lock, flags); - - return ret; -} -EXPORT_SYMBOL(clk_enable); - -void clk_disable(struct clk *clk) -{ - unsigned long flags; - - if (IS_ERR_OR_NULL(clk)) - return; - - spin_lock_irqsave(&clockfw_lock, flags); - if (clk->usecount == 0) { - pr_err("Trying disable clock %s with 0 usecount\n", - clk->name); - WARN_ON(1); - goto out; - } - - omap1_clk_disable(clk); - -out: - spin_unlock_irqrestore(&clockfw_lock, flags); -} -EXPORT_SYMBOL(clk_disable); - -unsigned long clk_get_rate(struct clk *clk) -{ - unsigned long flags; - unsigned long ret; - - if (IS_ERR_OR_NULL(clk)) - return 0; - - spin_lock_irqsave(&clockfw_lock, flags); - ret = clk->rate; - spin_unlock_irqrestore(&clockfw_lock, flags); - - return ret; -} -EXPORT_SYMBOL(clk_get_rate); - -/* - * Optional clock functions defined in include/linux/clk.h - */ - -long clk_round_rate(struct clk *clk, unsigned long rate) -{ - unsigned long flags; - long ret; - - if (IS_ERR_OR_NULL(clk)) - return 0; - - spin_lock_irqsave(&clockfw_lock, flags); - ret = omap1_clk_round_rate(clk, rate); - spin_unlock_irqrestore(&clockfw_lock, flags); - - return ret; -} -EXPORT_SYMBOL(clk_round_rate); - -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - unsigned long flags; - int ret = -EINVAL; - - if (IS_ERR_OR_NULL(clk)) - return ret; - - spin_lock_irqsave(&clockfw_lock, flags); - ret = omap1_clk_set_rate(clk, rate); - if (ret == 0) - propagate_rate(clk); - spin_unlock_irqrestore(&clockfw_lock, flags); - - return ret; -} -EXPORT_SYMBOL(clk_set_rate); - -int clk_set_parent(struct clk *clk, struct clk *parent) -{ - WARN_ONCE(1, "clk_set_parent() not implemented for OMAP1\n"); - - return -EINVAL; -} -EXPORT_SYMBOL(clk_set_parent); +const struct clk_ops omap1_clk_rate_ops = { + .recalc_rate = omap1_clk_recalc_rate, + .round_rate = omap1_clk_round_rate, + .set_rate = omap1_clk_set_rate, + .init = omap1_clk_init_op, +}; -struct clk *clk_get_parent(struct clk *clk) -{ - return clk->parent; -} -EXPORT_SYMBOL(clk_get_parent); +const struct clk_ops omap1_clk_full_ops = { + .enable = omap1_clk_enable, + .disable = omap1_clk_disable, + .is_enabled = omap1_clk_is_enabled, +#ifdef CONFIG_OMAP_RESET_CLOCKS + .disable_unused = omap1_clk_disable_unused, +#endif + .recalc_rate = omap1_clk_recalc_rate, + .round_rate = omap1_clk_round_rate, + .set_rate = omap1_clk_set_rate, + .init = omap1_clk_init_op, +}; /* * OMAP specific clock functions shared between omap1 and omap2 */ /* Used for clocks that always have same value as the parent clock */ -unsigned long followparent_recalc(struct clk *clk) +unsigned long followparent_recalc(struct omap1_clk *clk, unsigned long p_rate) { - return clk->parent->rate; + return p_rate; } /* * Used for clocks that have the same value as the parent clock, * divided by some factor */ -unsigned long omap_fixed_divisor_recalc(struct clk *clk) +unsigned long omap_fixed_divisor_recalc(struct omap1_clk *clk, unsigned long p_rate) { WARN_ON(!clk->fixed_div); - return clk->parent->rate / clk->fixed_div; -} - -void clk_reparent(struct clk *child, struct clk *parent) -{ - list_del_init(&child->sibling); - if (parent) - list_add(&child->sibling, &parent->children); - child->parent = parent; - - /* now do the debugfs renaming to reattach the child - to the proper parent */ + return p_rate / clk->fixed_div; } /* Propagate rate to children */ -void propagate_rate(struct clk *tclk) -{ - struct clk *clkp; - - list_for_each_entry(clkp, &tclk->children, sibling) { - if (clkp->recalc) - clkp->rate = clkp->recalc(clkp); - propagate_rate(clkp); - } -} - -static LIST_HEAD(root_clks); - -/** - * recalculate_root_clocks - recalculate and propagate all root clocks - * - * Recalculates all root clocks (clocks with no parent), which if the - * clock's .recalc is set correctly, should also propagate their rates. - * Called at init. - */ -void recalculate_root_clocks(void) +void propagate_rate(struct omap1_clk *tclk) { struct clk *clkp; - list_for_each_entry(clkp, &root_clks, sibling) { - if (clkp->recalc) - clkp->rate = clkp->recalc(clkp); - propagate_rate(clkp); - } -} - -/** - * clk_preinit - initialize any fields in the struct clk before clk init - * @clk: struct clk * to initialize - * - * Initialize any struct clk fields needed before normal clk initialization - * can run. No return value. - */ -void clk_preinit(struct clk *clk) -{ - INIT_LIST_HEAD(&clk->children); -} - -int clk_register(struct clk *clk) -{ - if (IS_ERR_OR_NULL(clk)) - return -EINVAL; - - /* - * trap out already registered clocks - */ - if (clk->node.next || clk->node.prev) - return 0; - - mutex_lock(&clocks_mutex); - if (clk->parent) - list_add(&clk->sibling, &clk->parent->children); - else - list_add(&clk->sibling, &root_clks); - - list_add(&clk->node, &clocks); - if (clk->init) - clk->init(clk); - mutex_unlock(&clocks_mutex); - - return 0; -} -EXPORT_SYMBOL(clk_register); - -void clk_unregister(struct clk *clk) -{ - if (IS_ERR_OR_NULL(clk)) + /* depend on CCF ability to recalculate new rates across whole clock subtree */ + if (WARN_ON(!(clk_hw_get_flags(&tclk->hw) & CLK_GET_RATE_NOCACHE))) return; - mutex_lock(&clocks_mutex); - list_del(&clk->sibling); - list_del(&clk->node); - mutex_unlock(&clocks_mutex); -} -EXPORT_SYMBOL(clk_unregister); - -void clk_enable_init_clocks(void) -{ - struct clk *clkp; - - list_for_each_entry(clkp, &clocks, node) - if (clkp->flags & ENABLE_ON_INIT) - clk_enable(clkp); -} - -/** - * omap_clk_get_by_name - locate OMAP struct clk by its name - * @name: name of the struct clk to locate - * - * Locate an OMAP struct clk by its name. Assumes that struct clk - * names are unique. Returns NULL if not found or a pointer to the - * struct clk if found. - */ -struct clk *omap_clk_get_by_name(const char *name) -{ - struct clk *c; - struct clk *ret = NULL; - - mutex_lock(&clocks_mutex); - - list_for_each_entry(c, &clocks, node) { - if (!strcmp(c->name, name)) { - ret = c; - break; - } - } - - mutex_unlock(&clocks_mutex); - - return ret; -} - -int omap_clk_enable_autoidle_all(void) -{ - struct clk *c; - unsigned long flags; - - spin_lock_irqsave(&clockfw_lock, flags); - - list_for_each_entry(c, &clocks, node) - if (c->ops->allow_idle) - c->ops->allow_idle(c); - - spin_unlock_irqrestore(&clockfw_lock, flags); - - return 0; -} - -int omap_clk_disable_autoidle_all(void) -{ - struct clk *c; - unsigned long flags; - - spin_lock_irqsave(&clockfw_lock, flags); - - list_for_each_entry(c, &clocks, node) - if (c->ops->deny_idle) - c->ops->deny_idle(c); - - spin_unlock_irqrestore(&clockfw_lock, flags); - - return 0; -} - -/* - * Low level helpers - */ -static int clkll_enable_null(struct clk *clk) -{ - return 0; -} + clkp = clk_get_sys(NULL, clk_hw_get_name(&tclk->hw)); + if (WARN_ON(!clkp)) + return; -static void clkll_disable_null(struct clk *clk) -{ + clk_get_rate(clkp); + clk_put(clkp); } -const struct clkops clkops_null = { - .enable = clkll_enable_null, - .disable = clkll_disable_null, +const struct clk_ops omap1_clk_null_ops = { }; /* @@ -917,115 +835,6 @@ const struct clkops clkops_null = { * * Used for clock aliases that are needed on some OMAPs, but not others */ -struct clk dummy_ck = { - .name = "dummy", - .ops = &clkops_null, +struct omap1_clk dummy_ck __refdata = { + .hw.init = CLK_HW_INIT_NO_PARENT("dummy", &omap1_clk_null_ops, 0), }; - -/* - * - */ - -#ifdef CONFIG_OMAP_RESET_CLOCKS -/* - * Disable any unused clocks left on by the bootloader - */ -static int __init clk_disable_unused(void) -{ - struct clk *ck; - unsigned long flags; - - pr_info("clock: disabling unused clocks to save power\n"); - - spin_lock_irqsave(&clockfw_lock, flags); - list_for_each_entry(ck, &clocks, node) { - if (ck->ops == &clkops_null) - continue; - - if (ck->usecount > 0 || !ck->enable_reg) - continue; - - omap1_clk_disable_unused(ck); - } - spin_unlock_irqrestore(&clockfw_lock, flags); - - return 0; -} -late_initcall(clk_disable_unused); -late_initcall(omap_clk_enable_autoidle_all); -#endif - -#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) -/* - * debugfs support to trace clock tree hierarchy and attributes - */ - -#include <linux/debugfs.h> -#include <linux/seq_file.h> - -static struct dentry *clk_debugfs_root; - -static int debug_clock_show(struct seq_file *s, void *unused) -{ - struct clk *c; - struct clk *pa; - - mutex_lock(&clocks_mutex); - seq_printf(s, "%-30s %-30s %-10s %s\n", - "clock-name", "parent-name", "rate", "use-count"); - - list_for_each_entry(c, &clocks, node) { - pa = c->parent; - seq_printf(s, "%-30s %-30s %-10lu %d\n", - c->name, pa ? pa->name : "none", c->rate, - c->usecount); - } - mutex_unlock(&clocks_mutex); - - return 0; -} - -DEFINE_SHOW_ATTRIBUTE(debug_clock); - -static void clk_debugfs_register_one(struct clk *c) -{ - struct dentry *d; - struct clk *pa = c->parent; - - d = debugfs_create_dir(c->name, pa ? pa->dent : clk_debugfs_root); - c->dent = d; - - debugfs_create_u8("usecount", S_IRUGO, c->dent, &c->usecount); - debugfs_create_ulong("rate", S_IRUGO, c->dent, &c->rate); - debugfs_create_x8("flags", S_IRUGO, c->dent, &c->flags); -} - -static void clk_debugfs_register(struct clk *c) -{ - struct clk *pa = c->parent; - - if (pa && !pa->dent) - clk_debugfs_register(pa); - - if (!c->dent) - clk_debugfs_register_one(c); -} - -static int __init clk_debugfs_init(void) -{ - struct clk *c; - struct dentry *d; - - d = debugfs_create_dir("clock", NULL); - clk_debugfs_root = d; - - list_for_each_entry(c, &clocks, node) - clk_debugfs_register(c); - - debugfs_create_file("summary", S_IRUGO, d, NULL, &debug_clock_fops); - - return 0; -} -late_initcall(clk_debugfs_init); - -#endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */ diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h index f3b8811f5ac0..16cfb2e86ee4 100644 --- a/arch/arm/mach-omap1/clock.h +++ b/arch/arm/mach-omap1/clock.h @@ -11,12 +11,11 @@ #define __ARCH_ARM_MACH_OMAP1_CLOCK_H #include <linux/clk.h> -#include <linux/list.h> - #include <linux/clkdev.h> +#include <linux/clk-provider.h> struct module; -struct clk; +struct omap1_clk; struct omap_clk { u16 cpu; @@ -29,7 +28,7 @@ struct omap_clk { .lk = { \ .dev_id = dev, \ .con_id = con, \ - .clk = ck, \ + .clk_hw = ck, \ }, \ } @@ -40,68 +39,30 @@ struct omap_clk { #define CK_16XX (1 << 3) /* 16xx, 17xx, 5912 */ #define CK_1710 (1 << 4) /* 1710 extra for rate selection */ - -/* Temporary, needed during the common clock framework conversion */ -#define __clk_get_name(clk) (clk->name) -#define __clk_get_parent(clk) (clk->parent) -#define __clk_get_rate(clk) (clk->rate) - /** * struct clkops - some clock function pointers * @enable: fn ptr that enables the current clock in hardware * @disable: fn ptr that enables the current clock in hardware - * @find_idlest: function returning the IDLEST register for the clock's IP blk - * @find_companion: function returning the "companion" clk reg for the clock * @allow_idle: fn ptr that enables autoidle for the current clock in hardware - * @deny_idle: fn ptr that disables autoidle for the current clock in hardware - * - * A "companion" clk is an accompanying clock to the one being queried - * that must be enabled for the IP module connected to the clock to - * become accessible by the hardware. Neither @find_idlest nor - * @find_companion should be needed; that information is IP - * block-specific; the hwmod code has been created to handle this, but - * until hwmod data is ready and drivers have been converted to use PM - * runtime calls in place of clk_enable()/clk_disable(), @find_idlest and - * @find_companion must, unfortunately, remain. */ struct clkops { - int (*enable)(struct clk *); - void (*disable)(struct clk *); - void (*find_idlest)(struct clk *, void __iomem **, - u8 *, u8 *); - void (*find_companion)(struct clk *, void __iomem **, - u8 *); - void (*allow_idle)(struct clk *); - void (*deny_idle)(struct clk *); + int (*enable)(struct omap1_clk *clk); + void (*disable)(struct omap1_clk *clk); }; /* * struct clk.flags possibilities * * XXX document the rest of the clock flags here - * - * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL - * bits share the same register. This flag allows the - * omap4_dpllmx*() code to determine which GATE_CTRL bit field - * should be used. This is a temporary solution - a better approach - * would be to associate clock type-specific data with the clock, - * similar to the struct dpll_data approach. */ #define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */ #define CLOCK_IDLE_CONTROL (1 << 1) #define CLOCK_NO_IDLE_PARENT (1 << 2) -#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */ -#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ -#define CLOCK_CLKOUTX2 (1 << 5) /** - * struct clk - OMAP struct clk - * @node: list_head connecting this clock into the full clock list + * struct omap1_clk - OMAP1 struct clk + * @hw: struct clk_hw for common clock framework integration * @ops: struct clkops * for this clock - * @name: the name of the clock in the hardware (used in hwmod data and debug) - * @parent: pointer to this clock's parent struct clk - * @children: list_head connecting to the child clks' @sibling list_heads - * @sibling: list_head connecting this clk to its parent clk's @children * @rate: current clock rate * @enable_reg: register to write to enable the clock (see @enable_bit) * @recalc: fn ptr that returns the clock's current rate @@ -109,123 +70,65 @@ struct clkops { * @round_rate: fn ptr that can round the clock's current rate * @init: fn ptr to do clock-specific initialization * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg) - * @usecount: number of users that have requested this clock to be enabled * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div * @flags: see "struct clk.flags possibilities" above * @rate_offset: bitshift for rate selection bitfield (OMAP1 only) - * @src_offset: bitshift for source selection bitfield (OMAP1 only) - * - * XXX @rate_offset, @src_offset should probably be removed and OMAP1 - * clock code converted to use clksel. - * - * XXX @usecount is poorly named. It should be "enable_count" or - * something similar. "users" in the description refers to kernel - * code (core code or drivers) that have called clk_enable() and not - * yet called clk_disable(); the usecount of parent clocks is also - * incremented by the clock code when clk_enable() is called on child - * clocks and decremented by the clock code when clk_disable() is - * called on child clocks. - * - * XXX @clkdm, @usecount, @children, @sibling should be marked for - * internal use only. - * - * @children and @sibling are used to optimize parent-to-child clock - * tree traversals. (child-to-parent traversals use @parent.) - * - * XXX The notion of the clock's current rate probably needs to be - * separated from the clock's target rate. */ -struct clk { - struct list_head node; +struct omap1_clk { + struct clk_hw hw; const struct clkops *ops; - const char *name; - struct clk *parent; - struct list_head children; - struct list_head sibling; /* node for children */ unsigned long rate; void __iomem *enable_reg; - unsigned long (*recalc)(struct clk *); - int (*set_rate)(struct clk *, unsigned long); - long (*round_rate)(struct clk *, unsigned long); - void (*init)(struct clk *); + unsigned long (*recalc)(struct omap1_clk *clk, unsigned long rate); + int (*set_rate)(struct omap1_clk *clk, unsigned long rate, + unsigned long p_rate); + long (*round_rate)(struct omap1_clk *clk, unsigned long rate, + unsigned long *p_rate); + int (*init)(struct omap1_clk *clk); u8 enable_bit; - s8 usecount; u8 fixed_div; u8 flags; u8 rate_offset; - u8 src_offset; -#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) - struct dentry *dent; /* For visible tree hierarchy */ -#endif -}; - -struct clk_functions { - int (*clk_enable)(struct clk *clk); - void (*clk_disable)(struct clk *clk); - long (*clk_round_rate)(struct clk *clk, unsigned long rate); - int (*clk_set_rate)(struct clk *clk, unsigned long rate); - int (*clk_set_parent)(struct clk *clk, struct clk *parent); - void (*clk_allow_idle)(struct clk *clk); - void (*clk_deny_idle)(struct clk *clk); - void (*clk_disable_unused)(struct clk *clk); }; +#define to_omap1_clk(_hw) container_of(_hw, struct omap1_clk, hw) -extern int clk_init(struct clk_functions *custom_clocks); -extern void clk_preinit(struct clk *clk); -extern int clk_register(struct clk *clk); -extern void clk_reparent(struct clk *child, struct clk *parent); -extern void clk_unregister(struct clk *clk); -extern void propagate_rate(struct clk *clk); -extern void recalculate_root_clocks(void); -extern unsigned long followparent_recalc(struct clk *clk); -extern void clk_enable_init_clocks(void); -unsigned long omap_fixed_divisor_recalc(struct clk *clk); -extern struct clk *omap_clk_get_by_name(const char *name); -extern int omap_clk_enable_autoidle_all(void); -extern int omap_clk_disable_autoidle_all(void); +void propagate_rate(struct omap1_clk *clk); +unsigned long followparent_recalc(struct omap1_clk *clk, unsigned long p_rate); +unsigned long omap_fixed_divisor_recalc(struct omap1_clk *clk, unsigned long p_rate); -extern const struct clkops clkops_null; - -extern struct clk dummy_ck; +extern struct omap1_clk dummy_ck; int omap1_clk_init(void); void omap1_clk_late_init(void); -extern int omap1_clk_enable(struct clk *clk); -extern void omap1_clk_disable(struct clk *clk); -extern long omap1_clk_round_rate(struct clk *clk, unsigned long rate); -extern int omap1_clk_set_rate(struct clk *clk, unsigned long rate); -extern unsigned long omap1_ckctl_recalc(struct clk *clk); -extern int omap1_set_sossi_rate(struct clk *clk, unsigned long rate); -extern unsigned long omap1_sossi_recalc(struct clk *clk); -extern unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk); -extern int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate); -extern int omap1_set_uart_rate(struct clk *clk, unsigned long rate); -extern unsigned long omap1_uart_recalc(struct clk *clk); -extern int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate); -extern long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate); -extern void omap1_init_ext_clk(struct clk *clk); -extern int omap1_select_table_rate(struct clk *clk, unsigned long rate); -extern long omap1_round_to_table_rate(struct clk *clk, unsigned long rate); -extern int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate); -extern long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate); -extern unsigned long omap1_watchdog_recalc(struct clk *clk); - -#ifdef CONFIG_OMAP_RESET_CLOCKS -extern void omap1_clk_disable_unused(struct clk *clk); -#else -#define omap1_clk_disable_unused NULL -#endif +unsigned long omap1_ckctl_recalc(struct omap1_clk *clk, unsigned long p_rate); +long omap1_round_sossi_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate); +int omap1_set_sossi_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate); +unsigned long omap1_sossi_recalc(struct omap1_clk *clk, unsigned long p_rate); +unsigned long omap1_ckctl_recalc_dsp_domain(struct omap1_clk *clk, unsigned long p_rate); +int omap1_clk_set_rate_dsp_domain(struct omap1_clk *clk, unsigned long rate, + unsigned long p_rate); +long omap1_round_uart_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate); +int omap1_set_uart_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate); +unsigned long omap1_uart_recalc(struct omap1_clk *clk, unsigned long p_rate); +int omap1_set_ext_clk_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate); +long omap1_round_ext_clk_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate); +int omap1_init_ext_clk(struct omap1_clk *clk); +int omap1_select_table_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate); +long omap1_round_to_table_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate); +int omap1_clk_set_rate_ckctl_arm(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate); +long omap1_clk_round_rate_ckctl_arm(struct omap1_clk *clk, unsigned long rate, + unsigned long *p_rate); struct uart_clk { - struct clk clk; - unsigned long sysc_addr; + struct omap1_clk clk; + unsigned long sysc_addr; }; /* Provide a method for preventing idling some ARM IDLECT clocks */ struct arm_idlect1_clk { - struct clk clk; - unsigned long no_idle_count; - __u8 idlect_shift; + struct omap1_clk clk; + unsigned long no_idle_count; + __u8 idlect_shift; }; /* ARM_CKCTL bit shifts */ @@ -275,14 +178,18 @@ struct arm_idlect1_clk { #define SOFT_REQ_REG2 0xfffe0880 extern __u32 arm_idlect1_mask; -extern struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p; +extern struct omap1_clk *api_ck_p, *ck_dpll1_p, *ck_ref_p; extern const struct clkops clkops_dspck; -extern const struct clkops clkops_dummy; extern const struct clkops clkops_uart_16xx; extern const struct clkops clkops_generic; /* used for passing SoC type to omap1_{select,round_to}_table_rate() */ extern u32 cpu_mask; +extern const struct clk_ops omap1_clk_null_ops; +extern const struct clk_ops omap1_clk_gate_ops; +extern const struct clk_ops omap1_clk_rate_ops; +extern const struct clk_ops omap1_clk_full_ops; + #endif diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c index 3ebcd96efbff..96d846c37c43 100644 --- a/arch/arm/mach-omap1/clock_data.c +++ b/arch/arm/mach-omap1/clock_data.c @@ -14,16 +14,17 @@ #include <linux/kernel.h> #include <linux/io.h> #include <linux/clk.h> +#include <linux/clkdev.h> +#include <linux/clk-provider.h> #include <linux/cpufreq.h> #include <linux/delay.h> +#include <linux/soc/ti/omap1-io.h> #include <asm/mach-types.h> /* for machine_is_* */ #include "soc.h" - -#include <mach/hardware.h> -#include <mach/usb.h> /* for OTG_BASE */ - +#include "hardware.h" +#include "usb.h" /* for OTG_BASE */ #include "iomap.h" #include "clock.h" #include "sram.h" @@ -72,16 +73,18 @@ * Omap1 clocks */ -static struct clk ck_ref = { - .name = "ck_ref", - .ops = &clkops_null, +static struct omap1_clk ck_ref = { + .hw.init = CLK_HW_INIT_NO_PARENT("ck_ref", &omap1_clk_rate_ops, 0), .rate = 12000000, }; -static struct clk ck_dpll1 = { - .name = "ck_dpll1", - .ops = &clkops_null, - .parent = &ck_ref, +static struct omap1_clk ck_dpll1 = { + .hw.init = CLK_HW_INIT("ck_dpll1", "ck_ref", &omap1_clk_rate_ops, + /* + * force recursive refresh of rates of the clock + * and its children when clk_get_rate() is called + */ + CLK_GET_RATE_NOCACHE), }; /* @@ -90,33 +93,28 @@ static struct clk ck_dpll1 = { */ static struct arm_idlect1_clk ck_dpll1out = { .clk = { - .name = "ck_dpll1out", + .hw.init = CLK_HW_INIT("ck_dpll1out", "ck_dpll1", &omap1_clk_gate_ops, 0), .ops = &clkops_generic, - .parent = &ck_dpll1, - .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT | - ENABLE_ON_INIT, + .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_CKOUT_ARM, - .recalc = &followparent_recalc, }, .idlect_shift = IDL_CLKOUT_ARM_SHIFT, }; -static struct clk sossi_ck = { - .name = "ck_sossi", +static struct omap1_clk sossi_ck = { + .hw.init = CLK_HW_INIT("ck_sossi", "ck_dpll1out", &omap1_clk_full_ops, 0), .ops = &clkops_generic, - .parent = &ck_dpll1out.clk, .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT, .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1), .enable_bit = CONF_MOD_SOSSI_CLK_EN_R, .recalc = &omap1_sossi_recalc, + .round_rate = &omap1_round_sossi_rate, .set_rate = &omap1_set_sossi_rate, }; -static struct clk arm_ck = { - .name = "arm_ck", - .ops = &clkops_null, - .parent = &ck_dpll1, +static struct omap1_clk arm_ck = { + .hw.init = CLK_HW_INIT("arm_ck", "ck_dpll1", &omap1_clk_rate_ops, 0), .rate_offset = CKCTL_ARMDIV_OFFSET, .recalc = &omap1_ckctl_recalc, .round_rate = omap1_clk_round_rate_ckctl_arm, @@ -125,9 +123,9 @@ static struct clk arm_ck = { static struct arm_idlect1_clk armper_ck = { .clk = { - .name = "armper_ck", + .hw.init = CLK_HW_INIT("armper_ck", "ck_dpll1", &omap1_clk_full_ops, + CLK_IS_CRITICAL), .ops = &clkops_generic, - .parent = &ck_dpll1, .flags = CLOCK_IDLE_CONTROL, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_PERCK, @@ -143,47 +141,41 @@ static struct arm_idlect1_clk armper_ck = { * FIXME: This clock seems to be necessary but no-one has asked for its * activation. [ GPIO code for 1510 ] */ -static struct clk arm_gpio_ck = { - .name = "ick", +static struct omap1_clk arm_gpio_ck = { + .hw.init = CLK_HW_INIT("ick", "ck_dpll1", &omap1_clk_gate_ops, CLK_IS_CRITICAL), .ops = &clkops_generic, - .parent = &ck_dpll1, - .flags = ENABLE_ON_INIT, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_GPIOCK, - .recalc = &followparent_recalc, }; static struct arm_idlect1_clk armxor_ck = { .clk = { - .name = "armxor_ck", + .hw.init = CLK_HW_INIT("armxor_ck", "ck_ref", &omap1_clk_gate_ops, + CLK_IS_CRITICAL), .ops = &clkops_generic, - .parent = &ck_ref, .flags = CLOCK_IDLE_CONTROL, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_XORPCK, - .recalc = &followparent_recalc, }, .idlect_shift = IDLXORP_ARM_SHIFT, }; static struct arm_idlect1_clk armtim_ck = { .clk = { - .name = "armtim_ck", + .hw.init = CLK_HW_INIT("armtim_ck", "ck_ref", &omap1_clk_gate_ops, + CLK_IS_CRITICAL), .ops = &clkops_generic, - .parent = &ck_ref, .flags = CLOCK_IDLE_CONTROL, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_TIMCK, - .recalc = &followparent_recalc, }, .idlect_shift = IDLTIM_ARM_SHIFT, }; static struct arm_idlect1_clk armwdt_ck = { .clk = { - .name = "armwdt_ck", + .hw.init = CLK_HW_INIT("armwdt_ck", "ck_ref", &omap1_clk_full_ops, 0), .ops = &clkops_generic, - .parent = &ck_ref, .flags = CLOCK_IDLE_CONTROL, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_WDTCK, @@ -193,11 +185,8 @@ static struct arm_idlect1_clk armwdt_ck = { .idlect_shift = IDLWDT_ARM_SHIFT, }; -static struct clk arminth_ck16xx = { - .name = "arminth_ck", - .ops = &clkops_null, - .parent = &arm_ck, - .recalc = &followparent_recalc, +static struct omap1_clk arminth_ck16xx = { + .hw.init = CLK_HW_INIT("arminth_ck", "arm_ck", &omap1_clk_null_ops, 0), /* Note: On 16xx the frequency can be divided by 2 by programming * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1 * @@ -205,10 +194,9 @@ static struct clk arminth_ck16xx = { */ }; -static struct clk dsp_ck = { - .name = "dsp_ck", +static struct omap1_clk dsp_ck = { + .hw.init = CLK_HW_INIT("dsp_ck", "ck_dpll1", &omap1_clk_full_ops, 0), .ops = &clkops_generic, - .parent = &ck_dpll1, .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL), .enable_bit = EN_DSPCK, .rate_offset = CKCTL_DSPDIV_OFFSET, @@ -217,20 +205,17 @@ static struct clk dsp_ck = { .set_rate = omap1_clk_set_rate_ckctl_arm, }; -static struct clk dspmmu_ck = { - .name = "dspmmu_ck", - .ops = &clkops_null, - .parent = &ck_dpll1, +static struct omap1_clk dspmmu_ck = { + .hw.init = CLK_HW_INIT("dspmmu_ck", "ck_dpll1", &omap1_clk_rate_ops, 0), .rate_offset = CKCTL_DSPMMUDIV_OFFSET, .recalc = &omap1_ckctl_recalc, .round_rate = omap1_clk_round_rate_ckctl_arm, .set_rate = omap1_clk_set_rate_ckctl_arm, }; -static struct clk dspper_ck = { - .name = "dspper_ck", +static struct omap1_clk dspper_ck = { + .hw.init = CLK_HW_INIT("dspper_ck", "ck_dpll1", &omap1_clk_full_ops, 0), .ops = &clkops_dspck, - .parent = &ck_dpll1, .enable_reg = DSP_IDLECT2, .enable_bit = EN_PERCK, .rate_offset = CKCTL_PERDIV_OFFSET, @@ -239,29 +224,23 @@ static struct clk dspper_ck = { .set_rate = &omap1_clk_set_rate_dsp_domain, }; -static struct clk dspxor_ck = { - .name = "dspxor_ck", +static struct omap1_clk dspxor_ck = { + .hw.init = CLK_HW_INIT("dspxor_ck", "ck_ref", &omap1_clk_gate_ops, 0), .ops = &clkops_dspck, - .parent = &ck_ref, .enable_reg = DSP_IDLECT2, .enable_bit = EN_XORPCK, - .recalc = &followparent_recalc, }; -static struct clk dsptim_ck = { - .name = "dsptim_ck", +static struct omap1_clk dsptim_ck = { + .hw.init = CLK_HW_INIT("dsptim_ck", "ck_ref", &omap1_clk_gate_ops, 0), .ops = &clkops_dspck, - .parent = &ck_ref, .enable_reg = DSP_IDLECT2, .enable_bit = EN_DSPTIMCK, - .recalc = &followparent_recalc, }; static struct arm_idlect1_clk tc_ck = { .clk = { - .name = "tc_ck", - .ops = &clkops_null, - .parent = &ck_dpll1, + .hw.init = CLK_HW_INIT("tc_ck", "ck_dpll1", &omap1_clk_rate_ops, 0), .flags = CLOCK_IDLE_CONTROL, .rate_offset = CKCTL_TCDIV_OFFSET, .recalc = &omap1_ckctl_recalc, @@ -271,117 +250,88 @@ static struct arm_idlect1_clk tc_ck = { .idlect_shift = IDLIF_ARM_SHIFT, }; -static struct clk arminth_ck1510 = { - .name = "arminth_ck", - .ops = &clkops_null, - .parent = &tc_ck.clk, - .recalc = &followparent_recalc, +static struct omap1_clk arminth_ck1510 = { + .hw.init = CLK_HW_INIT("arminth_ck", "tc_ck", &omap1_clk_null_ops, 0), /* Note: On 1510 the frequency follows TC_CK * * 16xx version is in MPU clocks. */ }; -static struct clk tipb_ck = { +static struct omap1_clk tipb_ck = { /* No-idle controlled by "tc_ck" */ - .name = "tipb_ck", - .ops = &clkops_null, - .parent = &tc_ck.clk, - .recalc = &followparent_recalc, + .hw.init = CLK_HW_INIT("tipb_ck", "tc_ck", &omap1_clk_null_ops, 0), }; -static struct clk l3_ocpi_ck = { +static struct omap1_clk l3_ocpi_ck = { /* No-idle controlled by "tc_ck" */ - .name = "l3_ocpi_ck", + .hw.init = CLK_HW_INIT("l3_ocpi_ck", "tc_ck", &omap1_clk_gate_ops, 0), .ops = &clkops_generic, - .parent = &tc_ck.clk, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), .enable_bit = EN_OCPI_CK, - .recalc = &followparent_recalc, }; -static struct clk tc1_ck = { - .name = "tc1_ck", +static struct omap1_clk tc1_ck = { + .hw.init = CLK_HW_INIT("tc1_ck", "tc_ck", &omap1_clk_gate_ops, 0), .ops = &clkops_generic, - .parent = &tc_ck.clk, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), .enable_bit = EN_TC1_CK, - .recalc = &followparent_recalc, }; /* * FIXME: This clock seems to be necessary but no-one has asked for its * activation. [ pm.c (SRAM), CCP, Camera ] */ -static struct clk tc2_ck = { - .name = "tc2_ck", + +static struct omap1_clk tc2_ck = { + .hw.init = CLK_HW_INIT("tc2_ck", "tc_ck", &omap1_clk_gate_ops, CLK_IS_CRITICAL), .ops = &clkops_generic, - .parent = &tc_ck.clk, - .flags = ENABLE_ON_INIT, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), .enable_bit = EN_TC2_CK, - .recalc = &followparent_recalc, }; -static struct clk dma_ck = { +static struct omap1_clk dma_ck = { /* No-idle controlled by "tc_ck" */ - .name = "dma_ck", - .ops = &clkops_null, - .parent = &tc_ck.clk, - .recalc = &followparent_recalc, + .hw.init = CLK_HW_INIT("dma_ck", "tc_ck", &omap1_clk_null_ops, 0), }; -static struct clk dma_lcdfree_ck = { - .name = "dma_lcdfree_ck", - .ops = &clkops_null, - .parent = &tc_ck.clk, - .recalc = &followparent_recalc, +static struct omap1_clk dma_lcdfree_ck = { + .hw.init = CLK_HW_INIT("dma_lcdfree_ck", "tc_ck", &omap1_clk_null_ops, 0), }; static struct arm_idlect1_clk api_ck = { .clk = { - .name = "api_ck", + .hw.init = CLK_HW_INIT("api_ck", "tc_ck", &omap1_clk_gate_ops, 0), .ops = &clkops_generic, - .parent = &tc_ck.clk, .flags = CLOCK_IDLE_CONTROL, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_APICK, - .recalc = &followparent_recalc, }, .idlect_shift = IDLAPI_ARM_SHIFT, }; static struct arm_idlect1_clk lb_ck = { .clk = { - .name = "lb_ck", + .hw.init = CLK_HW_INIT("lb_ck", "tc_ck", &omap1_clk_gate_ops, 0), .ops = &clkops_generic, - .parent = &tc_ck.clk, .flags = CLOCK_IDLE_CONTROL, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_LBCK, - .recalc = &followparent_recalc, }, .idlect_shift = IDLLB_ARM_SHIFT, }; -static struct clk rhea1_ck = { - .name = "rhea1_ck", - .ops = &clkops_null, - .parent = &tc_ck.clk, - .recalc = &followparent_recalc, +static struct omap1_clk rhea1_ck = { + .hw.init = CLK_HW_INIT("rhea1_ck", "tc_ck", &omap1_clk_null_ops, 0), }; -static struct clk rhea2_ck = { - .name = "rhea2_ck", - .ops = &clkops_null, - .parent = &tc_ck.clk, - .recalc = &followparent_recalc, +static struct omap1_clk rhea2_ck = { + .hw.init = CLK_HW_INIT("rhea2_ck", "tc_ck", &omap1_clk_null_ops, 0), }; -static struct clk lcd_ck_16xx = { - .name = "lcd_ck", +static struct omap1_clk lcd_ck_16xx = { + .hw.init = CLK_HW_INIT("lcd_ck", "ck_dpll1", &omap1_clk_full_ops, 0), .ops = &clkops_generic, - .parent = &ck_dpll1, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_LCDCK, .rate_offset = CKCTL_LCDDIV_OFFSET, @@ -392,9 +342,8 @@ static struct clk lcd_ck_16xx = { static struct arm_idlect1_clk lcd_ck_1510 = { .clk = { - .name = "lcd_ck", + .hw.init = CLK_HW_INIT("lcd_ck", "ck_dpll1", &omap1_clk_full_ops, 0), .ops = &clkops_generic, - .parent = &ck_dpll1, .flags = CLOCK_IDLE_CONTROL, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_LCDCK, @@ -406,37 +355,35 @@ static struct arm_idlect1_clk lcd_ck_1510 = { .idlect_shift = OMAP1510_IDLLCD_ARM_SHIFT, }; + /* * XXX The enable_bit here is misused - it simply switches between 12MHz - * and 48MHz. Reimplement with clksel. + * and 48MHz. Reimplement with clk_mux. * * XXX does this need SYSC register handling? */ -static struct clk uart1_1510 = { - .name = "uart1_ck", - .ops = &clkops_null, +static struct omap1_clk uart1_1510 = { /* Direct from ULPD, no real parent */ - .parent = &armper_ck.clk, - .rate = 12000000, + .hw.init = CLK_HW_INIT("uart1_ck", "armper_ck", &omap1_clk_full_ops, 0), .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), .enable_bit = CONF_MOD_UART1_CLK_MODE_R, + .round_rate = &omap1_round_uart_rate, .set_rate = &omap1_set_uart_rate, .recalc = &omap1_uart_recalc, }; /* * XXX The enable_bit here is misused - it simply switches between 12MHz - * and 48MHz. Reimplement with clksel. + * and 48MHz. Reimplement with clk_mux. * * XXX SYSC register handling does not belong in the clock framework */ static struct uart_clk uart1_16xx = { .clk = { - .name = "uart1_ck", .ops = &clkops_uart_16xx, /* Direct from ULPD, no real parent */ - .parent = &armper_ck.clk, + .hw.init = CLK_HW_INIT("uart1_ck", "armper_ck", &omap1_clk_full_ops, 0), .rate = 48000000, .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), @@ -447,54 +394,49 @@ static struct uart_clk uart1_16xx = { /* * XXX The enable_bit here is misused - it simply switches between 12MHz - * and 48MHz. Reimplement with clksel. + * and 48MHz. Reimplement with clk_mux. * * XXX does this need SYSC register handling? */ -static struct clk uart2_ck = { - .name = "uart2_ck", - .ops = &clkops_null, +static struct omap1_clk uart2_ck = { /* Direct from ULPD, no real parent */ - .parent = &armper_ck.clk, - .rate = 12000000, + .hw.init = CLK_HW_INIT("uart2_ck", "armper_ck", &omap1_clk_full_ops, 0), .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), .enable_bit = CONF_MOD_UART2_CLK_MODE_R, + .round_rate = &omap1_round_uart_rate, .set_rate = &omap1_set_uart_rate, .recalc = &omap1_uart_recalc, }; /* * XXX The enable_bit here is misused - it simply switches between 12MHz - * and 48MHz. Reimplement with clksel. + * and 48MHz. Reimplement with clk_mux. * * XXX does this need SYSC register handling? */ -static struct clk uart3_1510 = { - .name = "uart3_ck", - .ops = &clkops_null, +static struct omap1_clk uart3_1510 = { /* Direct from ULPD, no real parent */ - .parent = &armper_ck.clk, - .rate = 12000000, + .hw.init = CLK_HW_INIT("uart3_ck", "armper_ck", &omap1_clk_full_ops, 0), .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), .enable_bit = CONF_MOD_UART3_CLK_MODE_R, + .round_rate = &omap1_round_uart_rate, .set_rate = &omap1_set_uart_rate, .recalc = &omap1_uart_recalc, }; /* * XXX The enable_bit here is misused - it simply switches between 12MHz - * and 48MHz. Reimplement with clksel. + * and 48MHz. Reimplement with clk_mux. * * XXX SYSC register handling does not belong in the clock framework */ static struct uart_clk uart3_16xx = { .clk = { - .name = "uart3_ck", .ops = &clkops_uart_16xx, /* Direct from ULPD, no real parent */ - .parent = &armper_ck.clk, + .hw.init = CLK_HW_INIT("uart3_ck", "armper_ck", &omap1_clk_full_ops, 0), .rate = 48000000, .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), @@ -503,30 +445,30 @@ static struct uart_clk uart3_16xx = { .sysc_addr = 0xfffb9854, }; -static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */ - .name = "usb_clko", +static struct omap1_clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */ .ops = &clkops_generic, /* Direct from ULPD, no parent */ + .hw.init = CLK_HW_INIT_NO_PARENT("usb_clko", &omap1_clk_full_ops, 0), .rate = 6000000, .flags = ENABLE_REG_32BIT, .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL), .enable_bit = USB_MCLK_EN_BIT, }; -static struct clk usb_hhc_ck1510 = { - .name = "usb_hhc_ck", +static struct omap1_clk usb_hhc_ck1510 = { .ops = &clkops_generic, /* Direct from ULPD, no parent */ + .hw.init = CLK_HW_INIT_NO_PARENT("usb_hhc_ck", &omap1_clk_full_ops, 0), .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ .flags = ENABLE_REG_32BIT, .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), .enable_bit = USB_HOST_HHC_UHOST_EN, }; -static struct clk usb_hhc_ck16xx = { - .name = "usb_hhc_ck", +static struct omap1_clk usb_hhc_ck16xx = { .ops = &clkops_generic, /* Direct from ULPD, no parent */ + .hw.init = CLK_HW_INIT_NO_PARENT("usb_hhc_ck", &omap1_clk_full_ops, 0), .rate = 48000000, /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ .flags = ENABLE_REG_32BIT, @@ -534,46 +476,46 @@ static struct clk usb_hhc_ck16xx = { .enable_bit = OTG_SYSCON_2_UHOST_EN_SHIFT }; -static struct clk usb_dc_ck = { - .name = "usb_dc_ck", +static struct omap1_clk usb_dc_ck = { .ops = &clkops_generic, /* Direct from ULPD, no parent */ + .hw.init = CLK_HW_INIT_NO_PARENT("usb_dc_ck", &omap1_clk_full_ops, 0), .rate = 48000000, .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), .enable_bit = SOFT_USB_OTG_DPLL_REQ_SHIFT, }; -static struct clk uart1_7xx = { - .name = "uart1_ck", +static struct omap1_clk uart1_7xx = { .ops = &clkops_generic, /* Direct from ULPD, no parent */ + .hw.init = CLK_HW_INIT_NO_PARENT("uart1_ck", &omap1_clk_full_ops, 0), .rate = 12000000, .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), .enable_bit = 9, }; -static struct clk uart2_7xx = { - .name = "uart2_ck", +static struct omap1_clk uart2_7xx = { .ops = &clkops_generic, /* Direct from ULPD, no parent */ + .hw.init = CLK_HW_INIT_NO_PARENT("uart2_ck", &omap1_clk_full_ops, 0), .rate = 12000000, .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), .enable_bit = 11, }; -static struct clk mclk_1510 = { - .name = "mclk", +static struct omap1_clk mclk_1510 = { .ops = &clkops_generic, /* Direct from ULPD, no parent. May be enabled by ext hardware. */ + .hw.init = CLK_HW_INIT_NO_PARENT("mclk", &omap1_clk_full_ops, 0), .rate = 12000000, .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), .enable_bit = SOFT_COM_MCKO_REQ_SHIFT, }; -static struct clk mclk_16xx = { - .name = "mclk", +static struct omap1_clk mclk_16xx = { .ops = &clkops_generic, /* Direct from ULPD, no parent. May be enabled by ext hardware. */ + .hw.init = CLK_HW_INIT_NO_PARENT("mclk", &omap1_clk_full_ops, 0), .enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL), .enable_bit = COM_ULPD_PLL_CLK_REQ, .set_rate = &omap1_set_ext_clk_rate, @@ -581,17 +523,16 @@ static struct clk mclk_16xx = { .init = &omap1_init_ext_clk, }; -static struct clk bclk_1510 = { - .name = "bclk", - .ops = &clkops_generic, +static struct omap1_clk bclk_1510 = { /* Direct from ULPD, no parent. May be enabled by ext hardware. */ + .hw.init = CLK_HW_INIT_NO_PARENT("bclk", &omap1_clk_rate_ops, 0), .rate = 12000000, }; -static struct clk bclk_16xx = { - .name = "bclk", +static struct omap1_clk bclk_16xx = { .ops = &clkops_generic, /* Direct from ULPD, no parent. May be enabled by ext hardware. */ + .hw.init = CLK_HW_INIT_NO_PARENT("bclk", &omap1_clk_full_ops, 0), .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL), .enable_bit = SWD_ULPD_PLL_CLK_REQ, .set_rate = &omap1_set_ext_clk_rate, @@ -599,11 +540,10 @@ static struct clk bclk_16xx = { .init = &omap1_init_ext_clk, }; -static struct clk mmc1_ck = { - .name = "mmc1_ck", +static struct omap1_clk mmc1_ck = { .ops = &clkops_generic, /* Functional clock is direct from ULPD, interface clock is ARMPER */ - .parent = &armper_ck.clk, + .hw.init = CLK_HW_INIT("mmc1_ck", "armper_ck", &omap1_clk_full_ops, 0), .rate = 48000000, .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), @@ -614,32 +554,29 @@ static struct clk mmc1_ck = { * XXX MOD_CONF_CTRL_0 bit 20 is defined in the 1510 TRM as * CONF_MOD_MCBSP3_AUXON ?? */ -static struct clk mmc2_ck = { - .name = "mmc2_ck", +static struct omap1_clk mmc2_ck = { .ops = &clkops_generic, /* Functional clock is direct from ULPD, interface clock is ARMPER */ - .parent = &armper_ck.clk, + .hw.init = CLK_HW_INIT("mmc2_ck", "armper_ck", &omap1_clk_full_ops, 0), .rate = 48000000, .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), .enable_bit = 20, }; -static struct clk mmc3_ck = { - .name = "mmc3_ck", +static struct omap1_clk mmc3_ck = { .ops = &clkops_generic, /* Functional clock is direct from ULPD, interface clock is ARMPER */ - .parent = &armper_ck.clk, + .hw.init = CLK_HW_INIT("mmc3_ck", "armper_ck", &omap1_clk_full_ops, 0), .rate = 48000000, .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), .enable_bit = SOFT_MMC_DPLL_REQ_SHIFT, }; -static struct clk virtual_ck_mpu = { - .name = "mpu", - .ops = &clkops_null, - .parent = &arm_ck, /* Is smarter alias for */ +static struct omap1_clk virtual_ck_mpu = { + /* Is smarter alias for arm_ck */ + .hw.init = CLK_HW_INIT("mpu", "arm_ck", &omap1_clk_rate_ops, 0), .recalc = &followparent_recalc, .set_rate = &omap1_select_table_rate, .round_rate = &omap1_round_to_table_rate, @@ -647,20 +584,14 @@ static struct clk virtual_ck_mpu = { /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK remains active during MPU idle whenever this is enabled */ -static struct clk i2c_fck = { - .name = "i2c_fck", - .ops = &clkops_null, +static struct omap1_clk i2c_fck = { + .hw.init = CLK_HW_INIT("i2c_fck", "armxor_ck", &omap1_clk_gate_ops, 0), .flags = CLOCK_NO_IDLE_PARENT, - .parent = &armxor_ck.clk, - .recalc = &followparent_recalc, }; -static struct clk i2c_ick = { - .name = "i2c_ick", - .ops = &clkops_null, +static struct omap1_clk i2c_ick = { + .hw.init = CLK_HW_INIT("i2c_ick", "armper_ck", &omap1_clk_gate_ops, 0), .flags = CLOCK_NO_IDLE_PARENT, - .parent = &armper_ck.clk, - .recalc = &followparent_recalc, }; /* @@ -669,81 +600,81 @@ static struct clk i2c_ick = { static struct omap_clk omap_clks[] = { /* non-ULPD clocks */ - CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310 | CK_7XX), - CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310 | CK_7XX), + CLK(NULL, "ck_ref", &ck_ref.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX), + CLK(NULL, "ck_dpll1", &ck_dpll1.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX), /* CK_GEN1 clocks */ - CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX), - CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX), - CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310), - CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), - CLK("omap_gpio.0", "ick", &arm_gpio_ck, CK_1510 | CK_310), - CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), - CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310), - CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310), - CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX), - CLK("omap_wdt", "ick", &dummy_ck, CK_1510 | CK_310), - CLK(NULL, "arminth_ck", &arminth_ck1510, CK_1510 | CK_310), - CLK(NULL, "arminth_ck", &arminth_ck16xx, CK_16XX), + CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk.hw, CK_16XX), + CLK(NULL, "ck_sossi", &sossi_ck.hw, CK_16XX), + CLK(NULL, "arm_ck", &arm_ck.hw, CK_16XX | CK_1510 | CK_310), + CLK(NULL, "armper_ck", &armper_ck.clk.hw, CK_16XX | CK_1510 | CK_310), + CLK("omap_gpio.0", "ick", &arm_gpio_ck.hw, CK_1510 | CK_310), + CLK(NULL, "armxor_ck", &armxor_ck.clk.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX), + CLK(NULL, "armtim_ck", &armtim_ck.clk.hw, CK_16XX | CK_1510 | CK_310), + CLK("omap_wdt", "fck", &armwdt_ck.clk.hw, CK_16XX | CK_1510 | CK_310), + CLK("omap_wdt", "ick", &armper_ck.clk.hw, CK_16XX), + CLK("omap_wdt", "ick", &dummy_ck.hw, CK_1510 | CK_310), + CLK(NULL, "arminth_ck", &arminth_ck1510.hw, CK_1510 | CK_310), + CLK(NULL, "arminth_ck", &arminth_ck16xx.hw, CK_16XX), /* CK_GEN2 clocks */ - CLK(NULL, "dsp_ck", &dsp_ck, CK_16XX | CK_1510 | CK_310), - CLK(NULL, "dspmmu_ck", &dspmmu_ck, CK_16XX | CK_1510 | CK_310), - CLK(NULL, "dspper_ck", &dspper_ck, CK_16XX | CK_1510 | CK_310), - CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), - CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310), + CLK(NULL, "dsp_ck", &dsp_ck.hw, CK_16XX | CK_1510 | CK_310), + CLK(NULL, "dspmmu_ck", &dspmmu_ck.hw, CK_16XX | CK_1510 | CK_310), + CLK(NULL, "dspper_ck", &dspper_ck.hw, CK_16XX | CK_1510 | CK_310), + CLK(NULL, "dspxor_ck", &dspxor_ck.hw, CK_16XX | CK_1510 | CK_310), + CLK(NULL, "dsptim_ck", &dsptim_ck.hw, CK_16XX | CK_1510 | CK_310), /* CK_GEN3 clocks */ - CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), - CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310), - CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX | CK_7XX), - CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX), - CLK(NULL, "tc2_ck", &tc2_ck, CK_16XX), - CLK(NULL, "dma_ck", &dma_ck, CK_16XX | CK_1510 | CK_310), - CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX), - CLK(NULL, "api_ck", &api_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), - CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310), - CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX), - CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX), - CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_7XX), - CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310), + CLK(NULL, "tc_ck", &tc_ck.clk.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX), + CLK(NULL, "tipb_ck", &tipb_ck.hw, CK_1510 | CK_310), + CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck.hw, CK_16XX | CK_7XX), + CLK(NULL, "tc1_ck", &tc1_ck.hw, CK_16XX), + CLK(NULL, "tc2_ck", &tc2_ck.hw, CK_16XX), + CLK(NULL, "dma_ck", &dma_ck.hw, CK_16XX | CK_1510 | CK_310), + CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck.hw, CK_16XX), + CLK(NULL, "api_ck", &api_ck.clk.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX), + CLK(NULL, "lb_ck", &lb_ck.clk.hw, CK_1510 | CK_310), + CLK(NULL, "rhea1_ck", &rhea1_ck.hw, CK_16XX), + CLK(NULL, "rhea2_ck", &rhea2_ck.hw, CK_16XX), + CLK(NULL, "lcd_ck", &lcd_ck_16xx.hw, CK_16XX | CK_7XX), + CLK(NULL, "lcd_ck", &lcd_ck_1510.clk.hw, CK_1510 | CK_310), /* ULPD clocks */ - CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310), - CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX), - CLK(NULL, "uart1_ck", &uart1_7xx, CK_7XX), - CLK(NULL, "uart2_ck", &uart2_ck, CK_16XX | CK_1510 | CK_310), - CLK(NULL, "uart2_ck", &uart2_7xx, CK_7XX), - CLK(NULL, "uart3_ck", &uart3_1510, CK_1510 | CK_310), - CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX), - CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310), - CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310), - CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX), - CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX | CK_7XX), - CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310), - CLK(NULL, "mclk", &mclk_16xx, CK_16XX), - CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310), - CLK(NULL, "bclk", &bclk_16xx, CK_16XX), - CLK("mmci-omap.0", "fck", &mmc1_ck, CK_16XX | CK_1510 | CK_310), - CLK("mmci-omap.0", "fck", &mmc3_ck, CK_7XX), - CLK("mmci-omap.0", "ick", &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), - CLK("mmci-omap.1", "fck", &mmc2_ck, CK_16XX), - CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX), + CLK(NULL, "uart1_ck", &uart1_1510.hw, CK_1510 | CK_310), + CLK(NULL, "uart1_ck", &uart1_16xx.clk.hw, CK_16XX), + CLK(NULL, "uart1_ck", &uart1_7xx.hw, CK_7XX), + CLK(NULL, "uart2_ck", &uart2_ck.hw, CK_16XX | CK_1510 | CK_310), + CLK(NULL, "uart2_ck", &uart2_7xx.hw, CK_7XX), + CLK(NULL, "uart3_ck", &uart3_1510.hw, CK_1510 | CK_310), + CLK(NULL, "uart3_ck", &uart3_16xx.clk.hw, CK_16XX), + CLK(NULL, "usb_clko", &usb_clko.hw, CK_16XX | CK_1510 | CK_310), + CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510.hw, CK_1510 | CK_310), + CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx.hw, CK_16XX), + CLK(NULL, "usb_dc_ck", &usb_dc_ck.hw, CK_16XX | CK_7XX), + CLK(NULL, "mclk", &mclk_1510.hw, CK_1510 | CK_310), + CLK(NULL, "mclk", &mclk_16xx.hw, CK_16XX), + CLK(NULL, "bclk", &bclk_1510.hw, CK_1510 | CK_310), + CLK(NULL, "bclk", &bclk_16xx.hw, CK_16XX), + CLK("mmci-omap.0", "fck", &mmc1_ck.hw, CK_16XX | CK_1510 | CK_310), + CLK("mmci-omap.0", "fck", &mmc3_ck.hw, CK_7XX), + CLK("mmci-omap.0", "ick", &armper_ck.clk.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX), + CLK("mmci-omap.1", "fck", &mmc2_ck.hw, CK_16XX), + CLK("mmci-omap.1", "ick", &armper_ck.clk.hw, CK_16XX), /* Virtual clocks */ - CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310), - CLK("omap_i2c.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310 | CK_7XX), - CLK("omap_i2c.1", "ick", &i2c_ick, CK_16XX), - CLK("omap_i2c.1", "ick", &dummy_ck, CK_1510 | CK_310 | CK_7XX), - CLK("omap1_spi100k.1", "fck", &dummy_ck, CK_7XX), - CLK("omap1_spi100k.1", "ick", &dummy_ck, CK_7XX), - CLK("omap1_spi100k.2", "fck", &dummy_ck, CK_7XX), - CLK("omap1_spi100k.2", "ick", &dummy_ck, CK_7XX), - CLK("omap_uwire", "fck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310), - CLK("omap-mcbsp.1", "ick", &dspper_ck, CK_16XX), - CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_1510 | CK_310), - CLK("omap-mcbsp.2", "ick", &armper_ck.clk, CK_16XX), - CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_1510 | CK_310), - CLK("omap-mcbsp.3", "ick", &dspper_ck, CK_16XX), - CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_1510 | CK_310), - CLK("omap-mcbsp.1", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), - CLK("omap-mcbsp.2", "fck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), - CLK("omap-mcbsp.3", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), + CLK(NULL, "mpu", &virtual_ck_mpu.hw, CK_16XX | CK_1510 | CK_310), + CLK("omap_i2c.1", "fck", &i2c_fck.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX), + CLK("omap_i2c.1", "ick", &i2c_ick.hw, CK_16XX), + CLK("omap_i2c.1", "ick", &dummy_ck.hw, CK_1510 | CK_310 | CK_7XX), + CLK("omap1_spi100k.1", "fck", &dummy_ck.hw, CK_7XX), + CLK("omap1_spi100k.1", "ick", &dummy_ck.hw, CK_7XX), + CLK("omap1_spi100k.2", "fck", &dummy_ck.hw, CK_7XX), + CLK("omap1_spi100k.2", "ick", &dummy_ck.hw, CK_7XX), + CLK("omap_uwire", "fck", &armxor_ck.clk.hw, CK_16XX | CK_1510 | CK_310), + CLK("omap-mcbsp.1", "ick", &dspper_ck.hw, CK_16XX), + CLK("omap-mcbsp.1", "ick", &dummy_ck.hw, CK_1510 | CK_310), + CLK("omap-mcbsp.2", "ick", &armper_ck.clk.hw, CK_16XX), + CLK("omap-mcbsp.2", "ick", &dummy_ck.hw, CK_1510 | CK_310), + CLK("omap-mcbsp.3", "ick", &dspper_ck.hw, CK_16XX), + CLK("omap-mcbsp.3", "ick", &dummy_ck.hw, CK_1510 | CK_310), + CLK("omap-mcbsp.1", "fck", &dspxor_ck.hw, CK_16XX | CK_1510 | CK_310), + CLK("omap-mcbsp.2", "fck", &armper_ck.clk.hw, CK_16XX | CK_1510 | CK_310), + CLK("omap-mcbsp.3", "fck", &dspxor_ck.hw, CK_16XX | CK_1510 | CK_310), }; /* @@ -763,15 +694,14 @@ u32 cpu_mask; int __init omap1_clk_init(void) { struct omap_clk *c; - int crystal_type = 0; /* Default 12 MHz */ u32 reg; #ifdef CONFIG_DEBUG_LL - /* - * Resets some clocks that may be left on from bootloader, - * but leaves serial clocks on. - */ - omap_writel(0x3 << 29, MOD_CONF_CTRL_0); + /* Make sure UART clocks are enabled early */ + if (cpu_is_omap16xx()) + omap_writel(omap_readl(MOD_CONF_CTRL_0) | + CONF_MOD_UART1_CLK_MODE_R | + CONF_MOD_UART3_CLK_MODE_R, MOD_CONF_CTRL_0); #endif /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */ @@ -783,9 +713,6 @@ int __init omap1_clk_init(void) /* By default all idlect1 clocks are allowed to idle */ arm_idlect1_mask = ~0; - for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) - clk_preinit(c->lk.clk); - cpu_mask = 0; if (cpu_is_omap1710()) cpu_mask |= CK_1710; @@ -798,27 +725,19 @@ int __init omap1_clk_init(void) if (cpu_is_omap310()) cpu_mask |= CK_310; - for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) - if (c->cpu & cpu_mask) { - clkdev_add(&c->lk); - clk_register(c->lk.clk); - } - /* Pointers to these clocks are needed by code in clock.c */ - api_ck_p = clk_get(NULL, "api_ck"); - ck_dpll1_p = clk_get(NULL, "ck_dpll1"); - ck_ref_p = clk_get(NULL, "ck_ref"); + api_ck_p = &api_ck.clk; + ck_dpll1_p = &ck_dpll1; + ck_ref_p = &ck_ref; if (cpu_is_omap7xx()) ck_ref.rate = 13000000; - if (cpu_is_omap16xx() && crystal_type == 2) - ck_ref.rate = 19200000; pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), omap_readw(ARM_CKCTL)); - /* We want to be in syncronous scalable mode */ + /* We want to be in synchronous scalable mode */ omap_writew(0x1000, ARM_SYSST); @@ -851,10 +770,7 @@ int __init omap1_clk_init(void) } } } - propagate_rate(&ck_dpll1); - /* Cache rates for clocks connected to ck_ref (not dpll1) */ - propagate_rate(&ck_ref); - omap1_show_rates(); + if (machine_is_omap_perseus2() || machine_is_omap_fsample()) { /* Select slicer output as OMAP input clock */ omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, @@ -886,16 +802,28 @@ int __init omap1_clk_init(void) */ omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */ - /* - * Only enable those clocks we will need, let the drivers - * enable other clocks as necessary - */ - clk_enable(&armper_ck.clk); - clk_enable(&armxor_ck.clk); - clk_enable(&armtim_ck.clk); /* This should be done by timer code */ + for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) { + if (!(c->cpu & cpu_mask)) + continue; + + if (c->lk.clk_hw->init) { /* NULL if provider already registered */ + const struct clk_init_data *init = c->lk.clk_hw->init; + const char *name = c->lk.clk_hw->init->name; + int err; + + err = clk_hw_register(NULL, c->lk.clk_hw); + if (err < 0) { + pr_err("failed to register clock \"%s\"! (%d)\n", name, err); + /* may be tried again, restore init data */ + c->lk.clk_hw->init = init; + continue; + } + } + + clk_hw_register_clkdev(c->lk.clk_hw, c->lk.con_id, c->lk.dev_id); + } - if (cpu_is_omap15xx()) - clk_enable(&arm_gpio_ck); + omap1_show_rates(); return 0; } @@ -907,7 +835,7 @@ void __init omap1_clk_late_init(void) unsigned long rate = ck_dpll1.rate; /* Find the highest supported frequency and enable it */ - if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) { + if (omap1_select_table_rate(&virtual_ck_mpu, ~0, arm_ck.rate)) { pr_err("System frequencies not set, using default. Check your config.\n"); /* * Reprogramming the DPLL is tricky, it must be done from SRAM. diff --git a/arch/arm/mach-omap1/common.h b/arch/arm/mach-omap1/common.h index 504b959ba5cf..5ceff05e15c0 100644 --- a/arch/arm/mach-omap1/common.h +++ b/arch/arm/mach-omap1/common.h @@ -31,8 +31,7 @@ #include <asm/exception.h> -#include <mach/irqs.h> - +#include "irqs.h" #include "soc.h" #include "i2c.h" diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c index eb0f09edb3d1..80e94770582a 100644 --- a/arch/arm/mach-omap1/devices.c +++ b/arch/arm/mach-omap1/devices.c @@ -14,15 +14,15 @@ #include <linux/spi/spi.h> #include <linux/platform_data/omap-wd-timer.h> +#include <linux/soc/ti/omap1-io.h> #include <asm/mach/map.h> -#include <mach/tc.h> -#include <mach/mux.h> - -#include <mach/omap7xx.h> -#include <mach/hardware.h> +#include "tc.h" +#include "mux.h" +#include "omap7xx.h" +#include "hardware.h" #include "common.h" #include "clock.h" #include "mmc.h" @@ -356,7 +356,7 @@ static int __init omap1_init_devices(void) if (!cpu_class_is_omap1()) return -ENODEV; - omap_sram_init(); + omap1_sram_init(); omap1_clk_late_init(); /* please keep these calls, and their implementations above, diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c index 2bf659fb6099..c3f280c3c5d7 100644 --- a/arch/arm/mach-omap1/dma.c +++ b/arch/arm/mach-omap1/dma.c @@ -24,7 +24,7 @@ #include <linux/dma-mapping.h> #include <linux/dmaengine.h> #include <linux/omap-dma.h> -#include <mach/tc.h> +#include "tc.h" #include "soc.h" diff --git a/arch/arm/mach-omap1/fb.c b/arch/arm/mach-omap1/fb.c index 0e32a959f254..b6e952b03838 100644 --- a/arch/arm/mach-omap1/fb.c +++ b/arch/arm/mach-omap1/fb.c @@ -17,9 +17,12 @@ #include <linux/io.h> #include <linux/omapfb.h> #include <linux/dma-mapping.h> +#include <linux/irq.h> #include <asm/mach/map.h> +#include "irqs.h" + #if IS_ENABLED(CONFIG_FB_OMAP) static bool omapfb_lcd_configured; @@ -27,6 +30,19 @@ static struct omapfb_platform_data omapfb_config; static u64 omap_fb_dma_mask = ~(u32)0; +static struct resource omap_fb_resources[] = { + { + .name = "irq", + .start = INT_LCD_CTRL, + .flags = IORESOURCE_IRQ, + }, + { + .name = "irq", + .start = INT_SOSSI_MATCH, + .flags = IORESOURCE_IRQ, + }, +}; + static struct platform_device omap_fb_device = { .name = "omapfb", .id = -1, @@ -35,7 +51,8 @@ static struct platform_device omap_fb_device = { .coherent_dma_mask = DMA_BIT_MASK(32), .platform_data = &omapfb_config, }, - .num_resources = 0, + .num_resources = ARRAY_SIZE(omap_fb_resources), + .resource = omap_fb_resources, }; void __init omapfb_set_lcd_config(const struct omap_lcd_config *config) diff --git a/arch/arm/mach-omap1/flash.c b/arch/arm/mach-omap1/flash.c index 40e43ce5329f..0a3ddb3b66eb 100644 --- a/arch/arm/mach-omap1/flash.c +++ b/arch/arm/mach-omap1/flash.c @@ -6,11 +6,12 @@ #include <linux/io.h> #include <linux/mtd/mtd.h> #include <linux/mtd/map.h> +#include <linux/soc/ti/omap1-io.h> + +#include "tc.h" -#include <mach/tc.h> #include "flash.h" -#include <mach/hardware.h> void omap1_set_vpp(struct platform_device *pdev, int enable) { diff --git a/arch/arm/mach-omap1/fpga.c b/arch/arm/mach-omap1/fpga.c index f03ed523f20f..4c71a195969f 100644 --- a/arch/arm/mach-omap1/fpga.c +++ b/arch/arm/mach-omap1/fpga.c @@ -24,8 +24,7 @@ #include <asm/irq.h> #include <asm/mach/irq.h> -#include <mach/hardware.h> - +#include "hardware.h" #include "iomap.h" #include "common.h" #include "fpga.h" diff --git a/arch/arm/mach-omap1/gpio15xx.c b/arch/arm/mach-omap1/gpio15xx.c index 3ec08bd5d8a0..c675f11de99d 100644 --- a/arch/arm/mach-omap1/gpio15xx.c +++ b/arch/arm/mach-omap1/gpio15xx.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * OMAP15xx specific gpio init * @@ -5,21 +6,13 @@ * * Author: * Charulatha V <charu@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <linux/gpio.h> #include <linux/platform_data/gpio-omap.h> +#include <linux/soc/ti/omap1-soc.h> -#include <mach/irqs.h> +#include "irqs.h" #define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE #define OMAP1510_GPIO_BASE 0xFFFCE000 diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c index 500cfd416c42..cf052714b3f8 100644 --- a/arch/arm/mach-omap1/gpio16xx.c +++ b/arch/arm/mach-omap1/gpio16xx.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * OMAP16xx specific gpio init * @@ -5,22 +6,14 @@ * * Author: * Charulatha V <charu@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <linux/gpio.h> #include <linux/platform_data/gpio-omap.h> +#include <linux/soc/ti/omap1-io.h> -#include <mach/irqs.h> - +#include "hardware.h" +#include "irqs.h" #include "soc.h" #define OMAP1610_GPIO1_BASE 0xfffbe400 diff --git a/arch/arm/mach-omap1/gpio7xx.c b/arch/arm/mach-omap1/gpio7xx.c index aeb81c18ffcc..c372b357eab4 100644 --- a/arch/arm/mach-omap1/gpio7xx.c +++ b/arch/arm/mach-omap1/gpio7xx.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * OMAP7xx specific gpio init * @@ -5,22 +6,12 @@ * * Author: * Charulatha V <charu@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <linux/gpio.h> #include <linux/platform_data/gpio-omap.h> -#include <mach/irqs.h> - +#include "irqs.h" #include "soc.h" #define OMAP7XX_GPIO1_BASE 0xfffbc000 diff --git a/arch/arm/mach-omap1/include/mach/hardware.h b/arch/arm/mach-omap1/hardware.h index e7c8ac7d83e3..c228234a1ed4 100644 --- a/arch/arm/mach-omap1/include/mach/hardware.h +++ b/arch/arm/mach-omap1/hardware.h @@ -1,6 +1,4 @@ /* - * arch/arm/mach-omap1/include/mach/hardware.h - * * Hardware definitions for TI OMAP processors and boards * * NOTE: Please put device driver specific defines into a separate header @@ -37,21 +35,12 @@ #define __ASM_ARCH_OMAP_HARDWARE_H #include <linux/sizes.h> +#include <linux/soc/ti/omap1-io.h> #ifndef __ASSEMBLER__ #include <asm/types.h> -#include <mach/soc.h> +#include <linux/soc/ti/omap1-soc.h> -/* - * NOTE: Please use ioremap + __raw_read/write where possible instead of these - */ -extern u8 omap_readb(u32 pa); -extern u16 omap_readw(u32 pa); -extern u32 omap_readl(u32 pa); -extern void omap_writeb(u8 v, u32 pa); -extern void omap_writew(u16 v, u32 pa); -extern void omap_writel(u32 v, u32 pa); - -#include <mach/tc.h> +#include "tc.h" /* Almost all documentation for chip and board memory maps assumes * BM is clear. Most devel boards have a switch to control booting @@ -72,10 +61,10 @@ static inline u32 omap_cs3_phys(void) #endif /* ifndef __ASSEMBLER__ */ -#define OMAP1_IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */ +#define OMAP1_IO_OFFSET 0x00f00000 /* Virtual IO = 0xff0b0000 */ #define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET) -#include <mach/serial.h> +#include "serial.h" /* * --------------------------------------------------------------------------- @@ -99,66 +88,6 @@ static inline u32 omap_cs3_phys(void) #define MPU_TIMER_ST (1 << 0) /* - * ---------------------------------------------------------------------------- - * Clocks - * ---------------------------------------------------------------------------- - */ -#define CLKGEN_REG_BASE (0xfffece00) -#define ARM_CKCTL (CLKGEN_REG_BASE + 0x0) -#define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4) -#define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8) -#define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC) -#define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10) -#define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14) -#define ARM_SYSST (CLKGEN_REG_BASE + 0x18) -#define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24) - -#define CK_RATEF 1 -#define CK_IDLEF 2 -#define CK_ENABLEF 4 -#define CK_SELECTF 8 -#define SETARM_IDLE_SHIFT - -/* DPLL control registers */ -#define DPLL_CTL (0xfffecf00) - -/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */ -#define DSP_CONFIG_REG_BASE IOMEM(0xe1008000) -#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0) -#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4) -#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8) -#define DSP_RSTCT2 (DSP_CONFIG_REG_BASE + 0x14) - -/* - * --------------------------------------------------------------------------- - * UPLD - * --------------------------------------------------------------------------- - */ -#define ULPD_REG_BASE (0xfffe0800) -#define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14) -#define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24) -#define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30) -# define DIS_USB_PVCI_CLK (1 << 5) /* no USB/FAC synch */ -# define USB_MCLK_EN (1 << 4) /* enable W4_USB_CLKO */ -#define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34) -# define SOFT_UDC_REQ (1 << 4) -# define SOFT_USB_CLK_REQ (1 << 3) -# define SOFT_DPLL_REQ (1 << 0) -#define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c) -#define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40) -#define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c) -#define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50) -#define ULPD_SOFT_DISABLE_REQ_REG (ULPD_REG_BASE + 0x68) -# define DIS_MMC2_DPLL_REQ (1 << 11) -# define DIS_MMC1_DPLL_REQ (1 << 10) -# define DIS_UART3_DPLL_REQ (1 << 9) -# define DIS_UART2_DPLL_REQ (1 << 8) -# define DIS_UART1_DPLL_REQ (1 << 7) -# define DIS_USB_HOST_DPLL_REQ (1 << 6) -#define ULPD_SDW_CLK_DIV_CTRL_SEL (ULPD_REG_BASE + 0x74) -#define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c) - -/* * --------------------------------------------------------------------------- * Watchdog timer * --------------------------------------------------------------------------- @@ -213,52 +142,6 @@ static inline u32 omap_cs3_phys(void) #endif -/* - * ---------------------------------------------------------------------------- - * System control registers - * ---------------------------------------------------------------------------- - */ -#define MOD_CONF_CTRL_0 0xfffe1080 -#define MOD_CONF_CTRL_1 0xfffe1110 - -/* - * ---------------------------------------------------------------------------- - * Pin multiplexing registers - * ---------------------------------------------------------------------------- - */ -#define FUNC_MUX_CTRL_0 0xfffe1000 -#define FUNC_MUX_CTRL_1 0xfffe1004 -#define FUNC_MUX_CTRL_2 0xfffe1008 -#define COMP_MODE_CTRL_0 0xfffe100c -#define FUNC_MUX_CTRL_3 0xfffe1010 -#define FUNC_MUX_CTRL_4 0xfffe1014 -#define FUNC_MUX_CTRL_5 0xfffe1018 -#define FUNC_MUX_CTRL_6 0xfffe101C -#define FUNC_MUX_CTRL_7 0xfffe1020 -#define FUNC_MUX_CTRL_8 0xfffe1024 -#define FUNC_MUX_CTRL_9 0xfffe1028 -#define FUNC_MUX_CTRL_A 0xfffe102C -#define FUNC_MUX_CTRL_B 0xfffe1030 -#define FUNC_MUX_CTRL_C 0xfffe1034 -#define FUNC_MUX_CTRL_D 0xfffe1038 -#define PULL_DWN_CTRL_0 0xfffe1040 -#define PULL_DWN_CTRL_1 0xfffe1044 -#define PULL_DWN_CTRL_2 0xfffe1048 -#define PULL_DWN_CTRL_3 0xfffe104c -#define PULL_DWN_CTRL_4 0xfffe10ac - -/* OMAP-1610 specific multiplexing registers */ -#define FUNC_MUX_CTRL_E 0xfffe1090 -#define FUNC_MUX_CTRL_F 0xfffe1094 -#define FUNC_MUX_CTRL_10 0xfffe1098 -#define FUNC_MUX_CTRL_11 0xfffe109c -#define FUNC_MUX_CTRL_12 0xfffe10a0 -#define PU_PD_SEL_0 0xfffe10b4 -#define PU_PD_SEL_1 0xfffe10b8 -#define PU_PD_SEL_2 0xfffe10bc -#define PU_PD_SEL_3 0xfffe10c0 -#define PU_PD_SEL_4 0xfffe10c4 - /* Timer32K for 1610 and 1710*/ #define OMAP_TIMER32K_BASE 0xFFFBC400 @@ -300,15 +183,6 @@ static inline u32 omap_cs3_phys(void) #define OMAP_LPG2_PMR (OMAP_LPG2_BASE + 0x04) /* - * ---------------------------------------------------------------------------- - * Pulse-Width Light - * ---------------------------------------------------------------------------- - */ -#define OMAP_PWL_BASE 0xfffb5800 -#define OMAP_PWL_ENABLE (OMAP_PWL_BASE + 0x00) -#define OMAP_PWL_CLK_ENABLE (OMAP_PWL_BASE + 0x04) - -/* * --------------------------------------------------------------------------- * Processor specific defines * --------------------------------------------------------------------------- diff --git a/arch/arm/mach-omap1/i2c.c b/arch/arm/mach-omap1/i2c.c index 5e6d81b1624c..22f945360599 100644 --- a/arch/arm/mach-omap1/i2c.c +++ b/arch/arm/mach-omap1/i2c.c @@ -7,8 +7,10 @@ #include <linux/i2c.h> #include <linux/platform_data/i2c-omap.h> -#include <mach/mux.h> + +#include "mux.h" #include "soc.h" +#include "i2c.h" #define OMAP_I2C_SIZE 0x3f #define OMAP1_I2C_BASE 0xfffb3800 diff --git a/arch/arm/mach-omap1/id.c b/arch/arm/mach-omap1/id.c index 91556e374152..c3bb1b71fdf3 100644 --- a/arch/arm/mach-omap1/id.c +++ b/arch/arm/mach-omap1/id.c @@ -12,12 +12,11 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/io.h> +#include <linux/soc/ti/omap1-io.h> #include <asm/system_info.h> #include "soc.h" - -#include <mach/hardware.h> - +#include "hardware.h" #include "common.h" #define OMAP_DIE_ID_0 0xfffe1800 diff --git a/arch/arm/mach-omap1/include/mach/io.h b/arch/arm/mach-omap1/include/mach/io.h deleted file mode 100644 index ce4f8005b26f..000000000000 --- a/arch/arm/mach-omap1/include/mach/io.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * arch/arm/mach-omap1/include/mach/io.h - * - * IO definitions for TI OMAP processors and boards - * - * Copied from arch/arm/mach-sa1100/include/mach/io.h - * Copyright (C) 1997-1999 Russell King - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - * Modifications: - * 06-12-1997 RMK Created. - * 07-04-1999 RMK Major cleanup - */ - -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -#define IO_SPACE_LIMIT 0xffffffff - -/* - * We don't actually have real ISA nor PCI buses, but there is so many - * drivers out there that might just work if we fake them... - */ -#define __io(a) __typesafe_io(a) - -#endif diff --git a/arch/arm/mach-omap1/include/mach/lcd_dma.h b/arch/arm/mach-omap1/include/mach/lcd_dma.h deleted file mode 100644 index 1a3c0cf17899..000000000000 --- a/arch/arm/mach-omap1/include/mach/lcd_dma.h +++ /dev/null @@ -1,65 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * arch/arm/mach-omap1/include/mach/lcd_dma.h - * - * Extracted from arch/arm/plat-omap/include/plat/dma.h - * Copyright (C) 2003 Nokia Corporation - * Author: Juha Yrjölä <juha.yrjola@nokia.com> - */ -#ifndef __MACH_OMAP1_LCD_DMA_H__ -#define __MACH_OMAP1_LCD_DMA_H__ - -/* Hardware registers for LCD DMA */ -#define OMAP1510_DMA_LCD_BASE (0xfffedb00) -#define OMAP1510_DMA_LCD_CTRL (OMAP1510_DMA_LCD_BASE + 0x00) -#define OMAP1510_DMA_LCD_TOP_F1_L (OMAP1510_DMA_LCD_BASE + 0x02) -#define OMAP1510_DMA_LCD_TOP_F1_U (OMAP1510_DMA_LCD_BASE + 0x04) -#define OMAP1510_DMA_LCD_BOT_F1_L (OMAP1510_DMA_LCD_BASE + 0x06) -#define OMAP1510_DMA_LCD_BOT_F1_U (OMAP1510_DMA_LCD_BASE + 0x08) - -#define OMAP1610_DMA_LCD_BASE (0xfffee300) -#define OMAP1610_DMA_LCD_CSDP (OMAP1610_DMA_LCD_BASE + 0xc0) -#define OMAP1610_DMA_LCD_CCR (OMAP1610_DMA_LCD_BASE + 0xc2) -#define OMAP1610_DMA_LCD_CTRL (OMAP1610_DMA_LCD_BASE + 0xc4) -#define OMAP1610_DMA_LCD_TOP_B1_L (OMAP1610_DMA_LCD_BASE + 0xc8) -#define OMAP1610_DMA_LCD_TOP_B1_U (OMAP1610_DMA_LCD_BASE + 0xca) -#define OMAP1610_DMA_LCD_BOT_B1_L (OMAP1610_DMA_LCD_BASE + 0xcc) -#define OMAP1610_DMA_LCD_BOT_B1_U (OMAP1610_DMA_LCD_BASE + 0xce) -#define OMAP1610_DMA_LCD_TOP_B2_L (OMAP1610_DMA_LCD_BASE + 0xd0) -#define OMAP1610_DMA_LCD_TOP_B2_U (OMAP1610_DMA_LCD_BASE + 0xd2) -#define OMAP1610_DMA_LCD_BOT_B2_L (OMAP1610_DMA_LCD_BASE + 0xd4) -#define OMAP1610_DMA_LCD_BOT_B2_U (OMAP1610_DMA_LCD_BASE + 0xd6) -#define OMAP1610_DMA_LCD_SRC_EI_B1 (OMAP1610_DMA_LCD_BASE + 0xd8) -#define OMAP1610_DMA_LCD_SRC_FI_B1_L (OMAP1610_DMA_LCD_BASE + 0xda) -#define OMAP1610_DMA_LCD_SRC_EN_B1 (OMAP1610_DMA_LCD_BASE + 0xe0) -#define OMAP1610_DMA_LCD_SRC_FN_B1 (OMAP1610_DMA_LCD_BASE + 0xe4) -#define OMAP1610_DMA_LCD_LCH_CTRL (OMAP1610_DMA_LCD_BASE + 0xea) -#define OMAP1610_DMA_LCD_SRC_FI_B1_U (OMAP1610_DMA_LCD_BASE + 0xf4) - -/* LCD DMA block numbers */ -enum { - OMAP_LCD_DMA_B1_TOP, - OMAP_LCD_DMA_B1_BOTTOM, - OMAP_LCD_DMA_B2_TOP, - OMAP_LCD_DMA_B2_BOTTOM -}; - -/* LCD DMA functions */ -extern int omap_request_lcd_dma(void (*callback)(u16 status, void *data), - void *data); -extern void omap_free_lcd_dma(void); -extern void omap_setup_lcd_dma(void); -extern void omap_enable_lcd_dma(void); -extern void omap_stop_lcd_dma(void); -extern void omap_set_lcd_dma_ext_controller(int external); -extern void omap_set_lcd_dma_single_transfer(int single); -extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres, - int data_type); -extern void omap_set_lcd_dma_b1_rotation(int rotate); -extern void omap_set_lcd_dma_b1_vxres(unsigned long vxres); -extern void omap_set_lcd_dma_b1_mirror(int mirror); -extern void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale); - -extern int omap_lcd_dma_running(void); - -#endif /* __MACH_OMAP1_LCD_DMA_H__ */ diff --git a/arch/arm/mach-omap1/include/mach/lcdc.h b/arch/arm/mach-omap1/include/mach/lcdc.h deleted file mode 100644 index 7152db1f5361..000000000000 --- a/arch/arm/mach-omap1/include/mach/lcdc.h +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * arch/arm/mach-omap1/include/mach/lcdc.h - * - * Extracted from drivers/video/omap/lcdc.c - * Copyright (C) 2004 Nokia Corporation - * Author: Imre Deak <imre.deak@nokia.com> - */ -#ifndef __MACH_LCDC_H__ -#define __MACH_LCDC_H__ - -#define OMAP_LCDC_BASE 0xfffec000 -#define OMAP_LCDC_SIZE 256 -#define OMAP_LCDC_IRQ INT_LCD_CTRL - -#define OMAP_LCDC_CONTROL (OMAP_LCDC_BASE + 0x00) -#define OMAP_LCDC_TIMING0 (OMAP_LCDC_BASE + 0x04) -#define OMAP_LCDC_TIMING1 (OMAP_LCDC_BASE + 0x08) -#define OMAP_LCDC_TIMING2 (OMAP_LCDC_BASE + 0x0c) -#define OMAP_LCDC_STATUS (OMAP_LCDC_BASE + 0x10) -#define OMAP_LCDC_SUBPANEL (OMAP_LCDC_BASE + 0x14) -#define OMAP_LCDC_LINE_INT (OMAP_LCDC_BASE + 0x18) -#define OMAP_LCDC_DISPLAY_STATUS (OMAP_LCDC_BASE + 0x1c) - -#define OMAP_LCDC_STAT_DONE (1 << 0) -#define OMAP_LCDC_STAT_VSYNC (1 << 1) -#define OMAP_LCDC_STAT_SYNC_LOST (1 << 2) -#define OMAP_LCDC_STAT_ABC (1 << 3) -#define OMAP_LCDC_STAT_LINE_INT (1 << 4) -#define OMAP_LCDC_STAT_FUF (1 << 5) -#define OMAP_LCDC_STAT_LOADED_PALETTE (1 << 6) - -#define OMAP_LCDC_CTRL_LCD_EN (1 << 0) -#define OMAP_LCDC_CTRL_LCD_TFT (1 << 7) -#define OMAP_LCDC_CTRL_LINE_IRQ_CLR_SEL (1 << 10) - -#define OMAP_LCDC_IRQ_VSYNC (1 << 2) -#define OMAP_LCDC_IRQ_DONE (1 << 3) -#define OMAP_LCDC_IRQ_LOADED_PALETTE (1 << 4) -#define OMAP_LCDC_IRQ_LINE_NIRQ (1 << 5) -#define OMAP_LCDC_IRQ_LINE (1 << 6) -#define OMAP_LCDC_IRQ_MASK (((1 << 5) - 1) << 2) - -#endif /* __MACH_LCDC_H__ */ diff --git a/arch/arm/mach-omap1/include/mach/memory.h b/arch/arm/mach-omap1/include/mach/memory.h deleted file mode 100644 index ba3a350479c8..000000000000 --- a/arch/arm/mach-omap1/include/mach/memory.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * arch/arm/mach-omap1/include/mach/memory.h - */ - -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H - -/* REVISIT: omap1 legacy drivers still rely on this */ -#include <mach/soc.h> - -#endif diff --git a/arch/arm/mach-omap1/include/mach/mux.h b/arch/arm/mach-omap1/include/mach/mux.h deleted file mode 100644 index 3f6dc55d9898..000000000000 --- a/arch/arm/mach-omap1/include/mach/mux.h +++ /dev/null @@ -1,441 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * arch/arm/plat-omap/include/mach/mux.h - * - * Table of the Omap register configurations for the FUNC_MUX and - * PULL_DWN combinations. - * - * Copyright (C) 2004 - 2008 Texas Instruments Inc. - * Copyright (C) 2003 - 2008 Nokia Corporation - * - * Written by Tony Lindgren - * - * NOTE: Please use the following naming style for new pin entries. - * For example, W8_1610_MMC2_DAT0, where: - * - W8 = ball - * - 1610 = 1510 or 1610, none if common for both 1510 and 1610 - * - MMC2_DAT0 = function - */ - -#ifndef __ASM_ARCH_MUX_H -#define __ASM_ARCH_MUX_H - -#define PU_PD_SEL_NA 0 /* No pu_pd reg available */ -#define PULL_DWN_CTRL_NA 0 /* No pull-down control needed */ - -#ifdef CONFIG_OMAP_MUX_DEBUG -#define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \ - .mux_reg = FUNC_MUX_CTRL_##reg, \ - .mask_offset = mode_offset, \ - .mask = mode, - -#define PULL_REG(reg, bit, status) .pull_name = "PULL_DWN_CTRL_"#reg, \ - .pull_reg = PULL_DWN_CTRL_##reg, \ - .pull_bit = bit, \ - .pull_val = status, - -#define PU_PD_REG(reg, status) .pu_pd_name = "PU_PD_SEL_"#reg, \ - .pu_pd_reg = PU_PD_SEL_##reg, \ - .pu_pd_val = status, - -#define MUX_REG_7XX(reg, mode_offset, mode) .mux_reg_name = "OMAP7XX_IO_CONF_"#reg, \ - .mux_reg = OMAP7XX_IO_CONF_##reg, \ - .mask_offset = mode_offset, \ - .mask = mode, - -#define PULL_REG_7XX(reg, bit, status) .pull_name = "OMAP7XX_IO_CONF_"#reg, \ - .pull_reg = OMAP7XX_IO_CONF_##reg, \ - .pull_bit = bit, \ - .pull_val = status, - -#else - -#define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \ - .mask_offset = mode_offset, \ - .mask = mode, - -#define PULL_REG(reg, bit, status) .pull_reg = PULL_DWN_CTRL_##reg, \ - .pull_bit = bit, \ - .pull_val = status, - -#define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \ - .pu_pd_val = status, - -#define MUX_REG_7XX(reg, mode_offset, mode) \ - .mux_reg = OMAP7XX_IO_CONF_##reg, \ - .mask_offset = mode_offset, \ - .mask = mode, - -#define PULL_REG_7XX(reg, bit, status) .pull_reg = OMAP7XX_IO_CONF_##reg, \ - .pull_bit = bit, \ - .pull_val = status, - -#endif /* CONFIG_OMAP_MUX_DEBUG */ - -#define MUX_CFG(desc, mux_reg, mode_offset, mode, \ - pull_reg, pull_bit, pull_status, \ - pu_pd_reg, pu_pd_status, debug_status) \ -{ \ - .name = desc, \ - .debug = debug_status, \ - MUX_REG(mux_reg, mode_offset, mode) \ - PULL_REG(pull_reg, pull_bit, pull_status) \ - PU_PD_REG(pu_pd_reg, pu_pd_status) \ -}, - - -/* - * OMAP730/850 has a slightly different config for the pin mux. - * - config regs are the OMAP7XX_IO_CONF_x regs (see omap7xx.h) regs and - * not the FUNC_MUX_CTRL_x regs from hardware.h - * - for pull-up/down, only has one enable bit which is in the same register - * as mux config - */ -#define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode, \ - pull_bit, pull_status, debug_status)\ -{ \ - .name = desc, \ - .debug = debug_status, \ - MUX_REG_7XX(mux_reg, mode_offset, mode) \ - PULL_REG_7XX(mux_reg, pull_bit, pull_status) \ - PU_PD_REG(NA, 0) \ -}, - -struct pin_config { - char *name; - const unsigned int mux_reg; - unsigned char debug; - - const unsigned char mask_offset; - const unsigned char mask; - - const char *pull_name; - const unsigned int pull_reg; - const unsigned char pull_val; - const unsigned char pull_bit; - - const char *pu_pd_name; - const unsigned int pu_pd_reg; - const unsigned char pu_pd_val; - -#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS) - const char *mux_reg_name; -#endif - -}; - -enum omap7xx_index { - /* OMAP 730 keyboard */ - E2_7XX_KBR0, - J7_7XX_KBR1, - E1_7XX_KBR2, - F3_7XX_KBR3, - D2_7XX_KBR4, - C2_7XX_KBC0, - D3_7XX_KBC1, - E4_7XX_KBC2, - F4_7XX_KBC3, - E3_7XX_KBC4, - - /* USB */ - AA17_7XX_USB_DM, - W16_7XX_USB_PU_EN, - W17_7XX_USB_VBUSI, - W18_7XX_USB_DMCK_OUT, - W19_7XX_USB_DCRST, - - /* MMC */ - MMC_7XX_CMD, - MMC_7XX_CLK, - MMC_7XX_DAT0, - - /* I2C */ - I2C_7XX_SCL, - I2C_7XX_SDA, - - /* SPI */ - SPI_7XX_1, - SPI_7XX_2, - SPI_7XX_3, - SPI_7XX_4, - SPI_7XX_5, - SPI_7XX_6, - - /* UART */ - UART_7XX_1, - UART_7XX_2, -}; - -enum omap1xxx_index { - /* UART1 (BT_UART_GATING)*/ - UART1_TX = 0, - UART1_RTS, - - /* UART2 (COM_UART_GATING)*/ - UART2_TX, - UART2_RX, - UART2_CTS, - UART2_RTS, - - /* UART3 (GIGA_UART_GATING) */ - UART3_TX, - UART3_RX, - UART3_CTS, - UART3_RTS, - UART3_CLKREQ, - UART3_BCLK, /* 12MHz clock out */ - Y15_1610_UART3_RTS, - - /* PWT & PWL */ - PWT, - PWL, - - /* USB master generic */ - R18_USB_VBUS, - R18_1510_USB_GPIO0, - W4_USB_PUEN, - W4_USB_CLKO, - W4_USB_HIGHZ, - W4_GPIO58, - - /* USB1 master */ - USB1_SUSP, - USB1_SEO, - W13_1610_USB1_SE0, - USB1_TXEN, - USB1_TXD, - USB1_VP, - USB1_VM, - USB1_RCV, - USB1_SPEED, - R13_1610_USB1_SPEED, - R13_1710_USB1_SE0, - - /* USB2 master */ - USB2_SUSP, - USB2_VP, - USB2_TXEN, - USB2_VM, - USB2_RCV, - USB2_SEO, - USB2_TXD, - - /* OMAP-1510 GPIO */ - R18_1510_GPIO0, - R19_1510_GPIO1, - M14_1510_GPIO2, - - /* OMAP1610 GPIO */ - P18_1610_GPIO3, - Y15_1610_GPIO17, - - /* OMAP-1710 GPIO */ - R18_1710_GPIO0, - V2_1710_GPIO10, - N21_1710_GPIO14, - W15_1710_GPIO40, - - /* MPUIO */ - MPUIO2, - N15_1610_MPUIO2, - MPUIO4, - MPUIO5, - T20_1610_MPUIO5, - W11_1610_MPUIO6, - V10_1610_MPUIO7, - W11_1610_MPUIO9, - V10_1610_MPUIO10, - W10_1610_MPUIO11, - E20_1610_MPUIO13, - U20_1610_MPUIO14, - E19_1610_MPUIO15, - - /* MCBSP2 */ - MCBSP2_CLKR, - MCBSP2_CLKX, - MCBSP2_DR, - MCBSP2_DX, - MCBSP2_FSR, - MCBSP2_FSX, - - /* MCBSP3 */ - MCBSP3_CLKX, - - /* Misc ballouts */ - BALLOUT_V8_ARMIO3, - N20_HDQ, - - /* OMAP-1610 MMC2 */ - W8_1610_MMC2_DAT0, - V8_1610_MMC2_DAT1, - W15_1610_MMC2_DAT2, - R10_1610_MMC2_DAT3, - Y10_1610_MMC2_CLK, - Y8_1610_MMC2_CMD, - V9_1610_MMC2_CMDDIR, - V5_1610_MMC2_DATDIR0, - W19_1610_MMC2_DATDIR1, - R18_1610_MMC2_CLKIN, - - /* OMAP-1610 External Trace Interface */ - M19_1610_ETM_PSTAT0, - L15_1610_ETM_PSTAT1, - L18_1610_ETM_PSTAT2, - L19_1610_ETM_D0, - J19_1610_ETM_D6, - J18_1610_ETM_D7, - - /* OMAP16XX GPIO */ - P20_1610_GPIO4, - V9_1610_GPIO7, - W8_1610_GPIO9, - N20_1610_GPIO11, - N19_1610_GPIO13, - P10_1610_GPIO22, - V5_1610_GPIO24, - AA20_1610_GPIO_41, - W19_1610_GPIO48, - M7_1610_GPIO62, - V14_16XX_GPIO37, - R9_16XX_GPIO18, - L14_16XX_GPIO49, - - /* OMAP-1610 uWire */ - V19_1610_UWIRE_SCLK, - U18_1610_UWIRE_SDI, - W21_1610_UWIRE_SDO, - N14_1610_UWIRE_CS0, - P15_1610_UWIRE_CS3, - N15_1610_UWIRE_CS1, - - /* OMAP-1610 SPI */ - U19_1610_SPIF_SCK, - U18_1610_SPIF_DIN, - P20_1610_SPIF_DIN, - W21_1610_SPIF_DOUT, - R18_1610_SPIF_DOUT, - N14_1610_SPIF_CS0, - N15_1610_SPIF_CS1, - T19_1610_SPIF_CS2, - P15_1610_SPIF_CS3, - - /* OMAP-1610 Flash */ - L3_1610_FLASH_CS2B_OE, - M8_1610_FLASH_CS2B_WE, - - /* First MMC */ - MMC_CMD, - MMC_DAT1, - MMC_DAT2, - MMC_DAT0, - MMC_CLK, - MMC_DAT3, - - /* OMAP-1710 MMC CMDDIR and DATDIR0 */ - M15_1710_MMC_CLKI, - P19_1710_MMC_CMDDIR, - P20_1710_MMC_DATDIR0, - - /* OMAP-1610 USB0 alternate pin configuration */ - W9_USB0_TXEN, - AA9_USB0_VP, - Y5_USB0_RCV, - R9_USB0_VM, - V6_USB0_TXD, - W5_USB0_SE0, - V9_USB0_SPEED, - V9_USB0_SUSP, - - /* USB2 */ - W9_USB2_TXEN, - AA9_USB2_VP, - Y5_USB2_RCV, - R9_USB2_VM, - V6_USB2_TXD, - W5_USB2_SE0, - - /* 16XX UART */ - R13_1610_UART1_TX, - V14_16XX_UART1_RX, - R14_1610_UART1_CTS, - AA15_1610_UART1_RTS, - R9_16XX_UART2_RX, - L14_16XX_UART3_RX, - - /* I2C OMAP-1610 */ - I2C_SCL, - I2C_SDA, - - /* Keypad */ - F18_1610_KBC0, - D20_1610_KBC1, - D19_1610_KBC2, - E18_1610_KBC3, - C21_1610_KBC4, - G18_1610_KBR0, - F19_1610_KBR1, - H14_1610_KBR2, - E20_1610_KBR3, - E19_1610_KBR4, - N19_1610_KBR5, - - /* Power management */ - T20_1610_LOW_PWR, - - /* MCLK Settings */ - V5_1710_MCLK_ON, - V5_1710_MCLK_OFF, - R10_1610_MCLK_ON, - R10_1610_MCLK_OFF, - - /* CompactFlash controller */ - P11_1610_CF_CD2, - R11_1610_CF_IOIS16, - V10_1610_CF_IREQ, - W10_1610_CF_RESET, - W11_1610_CF_CD1, - - /* parallel camera */ - J15_1610_CAM_LCLK, - J18_1610_CAM_D7, - J19_1610_CAM_D6, - J14_1610_CAM_D5, - K18_1610_CAM_D4, - K19_1610_CAM_D3, - K15_1610_CAM_D2, - K14_1610_CAM_D1, - L19_1610_CAM_D0, - L18_1610_CAM_VS, - L15_1610_CAM_HS, - M19_1610_CAM_RSTZ, - Y15_1610_CAM_OUTCLK, - - /* serial camera */ - H19_1610_CAM_EXCLK, - Y12_1610_CCP_CLKP, - W13_1610_CCP_CLKM, - W14_1610_CCP_DATAP, - Y14_1610_CCP_DATAM, - -}; - -struct omap_mux_cfg { - struct pin_config *pins; - unsigned long size; - int (*cfg_reg)(const struct pin_config *cfg); -}; - -#ifdef CONFIG_OMAP_MUX -/* setup pin muxing in Linux */ -extern int omap1_mux_init(void); -extern int omap_mux_register(struct omap_mux_cfg *); -extern int omap_cfg_reg(unsigned long reg_cfg); -#else -/* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */ -static inline int omap1_mux_init(void) { return 0; } -static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; } -#endif - -extern int omap2_mux_init(void); - -#endif diff --git a/arch/arm/mach-omap1/include/mach/soc.h b/arch/arm/mach-omap1/include/mach/soc.h deleted file mode 100644 index 1897cbabfc93..000000000000 --- a/arch/arm/mach-omap1/include/mach/soc.h +++ /dev/null @@ -1,220 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * OMAP cpu type detection - * - * Copyright (C) 2004, 2008 Nokia Corporation - * - * Copyright (C) 2009-11 Texas Instruments. - * - * Written by Tony Lindgren <tony.lindgren@nokia.com> - * - * Added OMAP4/5 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com> - */ - -#ifndef __ASM_ARCH_OMAP_CPU_H -#define __ASM_ARCH_OMAP_CPU_H - -#include <asm/irq.h> -#include <mach/hardware.h> -#include <mach/irqs.h> - -#ifndef __ASSEMBLY__ - -#include <linux/bitops.h> - -/* - * Test if multicore OMAP support is needed - */ -#undef MULTI_OMAP1 -#undef OMAP_NAME - -#ifdef CONFIG_ARCH_OMAP730 -# ifdef OMAP_NAME -# undef MULTI_OMAP1 -# define MULTI_OMAP1 -# else -# define OMAP_NAME omap730 -# endif -#endif -#ifdef CONFIG_ARCH_OMAP850 -# ifdef OMAP_NAME -# undef MULTI_OMAP1 -# define MULTI_OMAP1 -# else -# define OMAP_NAME omap850 -# endif -#endif -#ifdef CONFIG_ARCH_OMAP15XX -# ifdef OMAP_NAME -# undef MULTI_OMAP1 -# define MULTI_OMAP1 -# else -# define OMAP_NAME omap1510 -# endif -#endif -#ifdef CONFIG_ARCH_OMAP16XX -# ifdef OMAP_NAME -# undef MULTI_OMAP1 -# define MULTI_OMAP1 -# else -# define OMAP_NAME omap16xx -# endif -#endif - -/* - * omap_rev bits: - * CPU id bits (0730, 1510, 1710, 2422...) [31:16] - * CPU revision (See _REV_ defined in cpu.h) [15:08] - * CPU class bits (15xx, 16xx, 24xx, 34xx...) [07:00] - */ -unsigned int omap_rev(void); - -/* - * Get the CPU revision for OMAP devices - */ -#define GET_OMAP_REVISION() ((omap_rev() >> 8) & 0xff) - -/* - * Macros to group OMAP into cpu classes. - * These can be used in most places. - * cpu_is_omap7xx(): True for OMAP730, OMAP850 - * cpu_is_omap15xx(): True for OMAP1510, OMAP5910 and OMAP310 - * cpu_is_omap16xx(): True for OMAP1610, OMAP5912 and OMAP1710 - */ -#define GET_OMAP_CLASS (omap_rev() & 0xff) - -#define IS_OMAP_CLASS(class, id) \ -static inline int is_omap ##class (void) \ -{ \ - return (GET_OMAP_CLASS == (id)) ? 1 : 0; \ -} - -#define GET_OMAP_SUBCLASS ((omap_rev() >> 20) & 0x0fff) - -#define IS_OMAP_SUBCLASS(subclass, id) \ -static inline int is_omap ##subclass (void) \ -{ \ - return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \ -} - -IS_OMAP_CLASS(7xx, 0x07) -IS_OMAP_CLASS(15xx, 0x15) -IS_OMAP_CLASS(16xx, 0x16) - -#define cpu_is_omap7xx() 0 -#define cpu_is_omap15xx() 0 -#define cpu_is_omap16xx() 0 - -#if defined(MULTI_OMAP1) -# if defined(CONFIG_ARCH_OMAP730) -# undef cpu_is_omap7xx -# define cpu_is_omap7xx() is_omap7xx() -# endif -# if defined(CONFIG_ARCH_OMAP850) -# undef cpu_is_omap7xx -# define cpu_is_omap7xx() is_omap7xx() -# endif -# if defined(CONFIG_ARCH_OMAP15XX) -# undef cpu_is_omap15xx -# define cpu_is_omap15xx() is_omap15xx() -# endif -# if defined(CONFIG_ARCH_OMAP16XX) -# undef cpu_is_omap16xx -# define cpu_is_omap16xx() is_omap16xx() -# endif -#else -# if defined(CONFIG_ARCH_OMAP730) -# undef cpu_is_omap7xx -# define cpu_is_omap7xx() 1 -# endif -# if defined(CONFIG_ARCH_OMAP850) -# undef cpu_is_omap7xx -# define cpu_is_omap7xx() 1 -# endif -# if defined(CONFIG_ARCH_OMAP15XX) -# undef cpu_is_omap15xx -# define cpu_is_omap15xx() 1 -# endif -# if defined(CONFIG_ARCH_OMAP16XX) -# undef cpu_is_omap16xx -# define cpu_is_omap16xx() 1 -# endif -#endif - -/* - * Macros to detect individual cpu types. - * These are only rarely needed. - * cpu_is_omap310(): True for OMAP310 - * cpu_is_omap1510(): True for OMAP1510 - * cpu_is_omap1610(): True for OMAP1610 - * cpu_is_omap1611(): True for OMAP1611 - * cpu_is_omap5912(): True for OMAP5912 - * cpu_is_omap1621(): True for OMAP1621 - * cpu_is_omap1710(): True for OMAP1710 - */ -#define GET_OMAP_TYPE ((omap_rev() >> 16) & 0xffff) - -#define IS_OMAP_TYPE(type, id) \ -static inline int is_omap ##type (void) \ -{ \ - return (GET_OMAP_TYPE == (id)) ? 1 : 0; \ -} - -IS_OMAP_TYPE(310, 0x0310) -IS_OMAP_TYPE(1510, 0x1510) -IS_OMAP_TYPE(1610, 0x1610) -IS_OMAP_TYPE(1611, 0x1611) -IS_OMAP_TYPE(5912, 0x1611) -IS_OMAP_TYPE(1621, 0x1621) -IS_OMAP_TYPE(1710, 0x1710) - -#define cpu_is_omap310() 0 -#define cpu_is_omap1510() 0 -#define cpu_is_omap1610() 0 -#define cpu_is_omap5912() 0 -#define cpu_is_omap1611() 0 -#define cpu_is_omap1621() 0 -#define cpu_is_omap1710() 0 - -/* These are needed to compile common code */ -#ifdef CONFIG_ARCH_OMAP1 -#define cpu_is_omap242x() 0 -#define cpu_is_omap2430() 0 -#define cpu_is_omap243x() 0 -#define cpu_is_omap24xx() 0 -#define cpu_is_omap34xx() 0 -#define cpu_is_omap44xx() 0 -#define soc_is_omap54xx() 0 -#define soc_is_dra7xx() 0 -#define soc_is_am33xx() 0 -#define cpu_class_is_omap1() 1 -#define cpu_class_is_omap2() 0 -#endif - -/* - * Whether we have MULTI_OMAP1 or not, we still need to distinguish - * between 310 vs. 1510 and 1611B/5912 vs. 1710. - */ - -#if defined(CONFIG_ARCH_OMAP15XX) -# undef cpu_is_omap310 -# undef cpu_is_omap1510 -# define cpu_is_omap310() is_omap310() -# define cpu_is_omap1510() is_omap1510() -#endif - -#if defined(CONFIG_ARCH_OMAP16XX) -# undef cpu_is_omap1610 -# undef cpu_is_omap1611 -# undef cpu_is_omap5912 -# undef cpu_is_omap1621 -# undef cpu_is_omap1710 -# define cpu_is_omap1610() is_omap1610() -# define cpu_is_omap1611() is_omap1611() -# define cpu_is_omap5912() is_omap5912() -# define cpu_is_omap1621() is_omap1621() -# define cpu_is_omap1710() is_omap1710() -#endif - -#endif /* __ASSEMBLY__ */ -#endif diff --git a/arch/arm/mach-omap1/include/mach/uncompress.h b/arch/arm/mach-omap1/include/mach/uncompress.h deleted file mode 100644 index 9cca6a56788f..000000000000 --- a/arch/arm/mach-omap1/include/mach/uncompress.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/uncompress.h - * - * Serial port stubs for kernel decompress status messages - * - * Initially based on: - * linux-2.4.15-rmk1-dsplinux1.6/arch/arm/plat-omap/include/mach1510/uncompress.h - * Copyright (C) 2000 RidgeRun, Inc. - * Author: Greg Lonnon <glonnon@ridgerun.com> - * - * Rewritten by: - * Author: <source@mvista.com> - * 2004 (c) MontaVista Software, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include <linux/types.h> -#include <linux/serial_reg.h> - -#include <asm/memory.h> -#include <asm/mach-types.h> - -#include "serial.h" - -#define MDR1_MODE_MASK 0x07 - -volatile u8 *uart_base; -int uart_shift; - -/* - * Store the DEBUG_LL uart number into memory. - * See also debug-macro.S, and serial.c for related code. - */ -static void set_omap_uart_info(unsigned char port) -{ - /* - * Get address of some.bss variable and round it down - * a la CONFIG_AUTO_ZRELADDR. - */ - u32 ram_start = (u32)&uart_shift & 0xf8000000; - u32 *uart_info = (u32 *)(ram_start + OMAP_UART_INFO_OFS); - *uart_info = port; -} - -static inline void putc(int c) -{ - if (!uart_base) - return; - - /* Check for UART 16x mode */ - if ((uart_base[UART_OMAP_MDR1 << uart_shift] & MDR1_MODE_MASK) != 0) - return; - - while (!(uart_base[UART_LSR << uart_shift] & UART_LSR_THRE)) - barrier(); - uart_base[UART_TX << uart_shift] = c; -} - -static inline void flush(void) -{ -} - -/* - * Macros to configure UART1 and debug UART - */ -#define _DEBUG_LL_ENTRY(mach, dbg_uart, dbg_shft, dbg_id) \ - if (machine_is_##mach()) { \ - uart_base = (volatile u8 *)(dbg_uart); \ - uart_shift = (dbg_shft); \ - port = (dbg_id); \ - set_omap_uart_info(port); \ - break; \ - } - -#define DEBUG_LL_OMAP7XX(p, mach) \ - _DEBUG_LL_ENTRY(mach, OMAP1_UART##p##_BASE, OMAP7XX_PORT_SHIFT, \ - OMAP1UART##p) - -#define DEBUG_LL_OMAP1(p, mach) \ - _DEBUG_LL_ENTRY(mach, OMAP1_UART##p##_BASE, OMAP_PORT_SHIFT, \ - OMAP1UART##p) - -static inline void arch_decomp_setup(void) -{ - int port = 0; - - /* - * Initialize the port based on the machine ID from the bootloader. - * Note that we're using macros here instead of switch statement - * as machine_is functions are optimized out for the boards that - * are not selected. - */ - do { - /* omap7xx/8xx based boards using UART1 with shift 0 */ - DEBUG_LL_OMAP7XX(1, herald); - DEBUG_LL_OMAP7XX(1, omap_perseus2); - - /* omap15xx/16xx based boards using UART1 */ - DEBUG_LL_OMAP1(1, ams_delta); - DEBUG_LL_OMAP1(1, nokia770); - DEBUG_LL_OMAP1(1, omap_h2); - DEBUG_LL_OMAP1(1, omap_h3); - DEBUG_LL_OMAP1(1, omap_innovator); - DEBUG_LL_OMAP1(1, omap_osk); - DEBUG_LL_OMAP1(1, omap_palmte); - DEBUG_LL_OMAP1(1, omap_palmz71); - - /* omap15xx/16xx based boards using UART2 */ - DEBUG_LL_OMAP1(2, omap_palmtt); - - /* omap15xx/16xx based boards using UART3 */ - DEBUG_LL_OMAP1(3, sx1); - } while (0); -} diff --git a/arch/arm/mach-omap1/include/mach/usb.h b/arch/arm/mach-omap1/include/mach/usb.h deleted file mode 100644 index 5429d86c7190..000000000000 --- a/arch/arm/mach-omap1/include/mach/usb.h +++ /dev/null @@ -1,128 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * FIXME correct answer depends on hmc_mode, - * as does (on omap1) any nonzero value for config->otg port number - */ -#if IS_ENABLED(CONFIG_USB_OMAP) -#define is_usb0_device(config) 1 -#else -#define is_usb0_device(config) 0 -#endif - -#include <linux/platform_data/usb-omap1.h> - -#if IS_ENABLED(CONFIG_USB_SUPPORT) -void omap1_usb_init(struct omap_usb_config *pdata); -#else -static inline void omap1_usb_init(struct omap_usb_config *pdata) -{ -} -#endif - -#define OMAP1_OTG_BASE 0xfffb0400 -#define OMAP1_UDC_BASE 0xfffb4000 -#define OMAP1_OHCI_BASE 0xfffba000 - -#define OMAP2_OHCI_BASE 0x4805e000 -#define OMAP2_UDC_BASE 0x4805e200 -#define OMAP2_OTG_BASE 0x4805e300 -#define OTG_BASE OMAP1_OTG_BASE -#define UDC_BASE OMAP1_UDC_BASE -#define OMAP_OHCI_BASE OMAP1_OHCI_BASE - -/* - * OTG and transceiver registers, for OMAPs starting with ARM926 - */ -#define OTG_REV (OTG_BASE + 0x00) -#define OTG_SYSCON_1 (OTG_BASE + 0x04) -# define USB2_TRX_MODE(w) (((w)>>24)&0x07) -# define USB1_TRX_MODE(w) (((w)>>20)&0x07) -# define USB0_TRX_MODE(w) (((w)>>16)&0x07) -# define OTG_IDLE_EN (1 << 15) -# define HST_IDLE_EN (1 << 14) -# define DEV_IDLE_EN (1 << 13) -# define OTG_RESET_DONE (1 << 2) -# define OTG_SOFT_RESET (1 << 1) -#define OTG_SYSCON_2 (OTG_BASE + 0x08) -# define OTG_EN (1 << 31) -# define USBX_SYNCHRO (1 << 30) -# define OTG_MST16 (1 << 29) -# define SRP_GPDATA (1 << 28) -# define SRP_GPDVBUS (1 << 27) -# define SRP_GPUVBUS(w) (((w)>>24)&0x07) -# define A_WAIT_VRISE(w) (((w)>>20)&0x07) -# define B_ASE_BRST(w) (((w)>>16)&0x07) -# define SRP_DPW (1 << 14) -# define SRP_DATA (1 << 13) -# define SRP_VBUS (1 << 12) -# define OTG_PADEN (1 << 10) -# define HMC_PADEN (1 << 9) -# define UHOST_EN (1 << 8) -# define HMC_TLLSPEED (1 << 7) -# define HMC_TLLATTACH (1 << 6) -# define OTG_HMC(w) (((w)>>0)&0x3f) -#define OTG_CTRL (OTG_BASE + 0x0c) -# define OTG_USB2_EN (1 << 29) -# define OTG_USB2_DP (1 << 28) -# define OTG_USB2_DM (1 << 27) -# define OTG_USB1_EN (1 << 26) -# define OTG_USB1_DP (1 << 25) -# define OTG_USB1_DM (1 << 24) -# define OTG_USB0_EN (1 << 23) -# define OTG_USB0_DP (1 << 22) -# define OTG_USB0_DM (1 << 21) -# define OTG_ASESSVLD (1 << 20) -# define OTG_BSESSEND (1 << 19) -# define OTG_BSESSVLD (1 << 18) -# define OTG_VBUSVLD (1 << 17) -# define OTG_ID (1 << 16) -# define OTG_DRIVER_SEL (1 << 15) -# define OTG_A_SETB_HNPEN (1 << 12) -# define OTG_A_BUSREQ (1 << 11) -# define OTG_B_HNPEN (1 << 9) -# define OTG_B_BUSREQ (1 << 8) -# define OTG_BUSDROP (1 << 7) -# define OTG_PULLDOWN (1 << 5) -# define OTG_PULLUP (1 << 4) -# define OTG_DRV_VBUS (1 << 3) -# define OTG_PD_VBUS (1 << 2) -# define OTG_PU_VBUS (1 << 1) -# define OTG_PU_ID (1 << 0) -#define OTG_IRQ_EN (OTG_BASE + 0x10) /* 16-bit */ -# define DRIVER_SWITCH (1 << 15) -# define A_VBUS_ERR (1 << 13) -# define A_REQ_TMROUT (1 << 12) -# define A_SRP_DETECT (1 << 11) -# define B_HNP_FAIL (1 << 10) -# define B_SRP_TMROUT (1 << 9) -# define B_SRP_DONE (1 << 8) -# define B_SRP_STARTED (1 << 7) -# define OPRT_CHG (1 << 0) -#define OTG_IRQ_SRC (OTG_BASE + 0x14) /* 16-bit */ - // same bits as in IRQ_EN -#define OTG_OUTCTRL (OTG_BASE + 0x18) /* 16-bit */ -# define OTGVPD (1 << 14) -# define OTGVPU (1 << 13) -# define OTGPUID (1 << 12) -# define USB2VDR (1 << 10) -# define USB2PDEN (1 << 9) -# define USB2PUEN (1 << 8) -# define USB1VDR (1 << 6) -# define USB1PDEN (1 << 5) -# define USB1PUEN (1 << 4) -# define USB0VDR (1 << 2) -# define USB0PDEN (1 << 1) -# define USB0PUEN (1 << 0) -#define OTG_TEST (OTG_BASE + 0x20) /* 16-bit */ -#define OTG_VENDOR_CODE (OTG_BASE + 0xfc) /* 16-bit */ - -/*-------------------------------------------------------------------------*/ - -/* OMAP1 */ -#define USB_TRANSCEIVER_CTRL (0xfffe1000 + 0x0064) -# define CONF_USB2_UNI_R (1 << 8) -# define CONF_USB1_UNI_R (1 << 7) -# define CONF_USB_PORT0_R(x) (((x)>>4)&0x7) -# define CONF_USB0_ISOLATE_R (1 << 3) -# define CONF_USB_PWRDN_DM_R (1 << 2) -# define CONF_USB_PWRDN_DP_R (1 << 1) diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c index 5a173fc2a1ca..d2db9b8aed3f 100644 --- a/arch/arm/mach-omap1/io.c +++ b/arch/arm/mach-omap1/io.c @@ -9,17 +9,14 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/io.h> +#include <linux/omap-dma.h> #include <asm/tlb.h> #include <asm/mach/map.h> -#include <mach/mux.h> -#include <mach/tc.h> -#include <linux/omap-dma.h> - +#include "tc.h" #include "iomap.h" #include "common.h" -#include "clock.h" /* * The machine specific code may provide the extra mapping besides the @@ -126,11 +123,6 @@ void __init omap1_init_early(void) */ omap_writew(0x0, MPU_PUBLIC_TIPB_CNTL); omap_writew(0x0, MPU_PRIVATE_TIPB_CNTL); - - /* Must init clocks early to assure that timer interrupt works - */ - omap1_clk_init(); - omap1_mux_init(); } void __init omap1_init_late(void) diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c index ee6a93083154..70868e9f19ac 100644 --- a/arch/arm/mach-omap1/irq.c +++ b/arch/arm/mach-omap1/irq.c @@ -47,9 +47,7 @@ #include <asm/mach/irq.h> #include "soc.h" - -#include <mach/hardware.h> - +#include "hardware.h" #include "common.h" #define IRQ_BANK(irq) ((irq) >> 5) diff --git a/arch/arm/mach-omap1/include/mach/irqs.h b/arch/arm/mach-omap1/irqs.h index 30bf007700cf..2851acfe5ff3 100644 --- a/arch/arm/mach-omap1/include/mach/irqs.h +++ b/arch/arm/mach-omap1/irqs.h @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ /* - * arch/arm/plat-omap/include/mach/irqs.h - * * Copyright (C) Greg Lonnon 2001 * Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com> * diff --git a/arch/arm/mach-omap1/lcd_dma.c b/arch/arm/mach-omap1/lcd_dma.c deleted file mode 100644 index a72ac0c02b4f..000000000000 --- a/arch/arm/mach-omap1/lcd_dma.c +++ /dev/null @@ -1,441 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-omap1/lcd_dma.c - * - * Extracted from arch/arm/plat-omap/dma.c - * Copyright (C) 2003 - 2008 Nokia Corporation - * Author: Juha Yrjölä <juha.yrjola@nokia.com> - * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com> - * Graphics DMA and LCD DMA graphics tranformations - * by Imre Deak <imre.deak@nokia.com> - * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc. - * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com> - * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc. - * - * Copyright (C) 2009 Texas Instruments - * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> - * - * Support functions for the OMAP internal DMA channels. - */ - -#include <linux/module.h> -#include <linux/spinlock.h> -#include <linux/interrupt.h> -#include <linux/io.h> - -#include <linux/omap-dma.h> - -#include <mach/hardware.h> -#include <mach/lcdc.h> - -int omap_lcd_dma_running(void) -{ - /* - * On OMAP1510, internal LCD controller will start the transfer - * when it gets enabled, so assume DMA running if LCD enabled. - */ - if (cpu_is_omap15xx()) - if (omap_readw(OMAP_LCDC_CONTROL) & OMAP_LCDC_CTRL_LCD_EN) - return 1; - - /* Check if LCD DMA is running */ - if (cpu_is_omap16xx()) - if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN) - return 1; - - return 0; -} - -static struct lcd_dma_info { - spinlock_t lock; - int reserved; - void (*callback)(u16 status, void *data); - void *cb_data; - - int active; - unsigned long addr; - int rotate, data_type, xres, yres; - int vxres; - int mirror; - int xscale, yscale; - int ext_ctrl; - int src_port; - int single_transfer; -} lcd_dma; - -void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres, - int data_type) -{ - lcd_dma.addr = addr; - lcd_dma.data_type = data_type; - lcd_dma.xres = fb_xres; - lcd_dma.yres = fb_yres; -} -EXPORT_SYMBOL(omap_set_lcd_dma_b1); - -void omap_set_lcd_dma_ext_controller(int external) -{ - lcd_dma.ext_ctrl = external; -} -EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller); - -void omap_set_lcd_dma_single_transfer(int single) -{ - lcd_dma.single_transfer = single; -} -EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer); - -void omap_set_lcd_dma_b1_rotation(int rotate) -{ - if (cpu_is_omap15xx()) { - printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n"); - BUG(); - return; - } - lcd_dma.rotate = rotate; -} -EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation); - -void omap_set_lcd_dma_b1_mirror(int mirror) -{ - if (cpu_is_omap15xx()) { - printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n"); - BUG(); - } - lcd_dma.mirror = mirror; -} -EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror); - -void omap_set_lcd_dma_b1_vxres(unsigned long vxres) -{ - if (cpu_is_omap15xx()) { - pr_err("DMA virtual resolution is not supported in 1510 mode\n"); - BUG(); - } - lcd_dma.vxres = vxres; -} -EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres); - -void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale) -{ - if (cpu_is_omap15xx()) { - printk(KERN_ERR "DMA scale is not supported in 1510 mode\n"); - BUG(); - } - lcd_dma.xscale = xscale; - lcd_dma.yscale = yscale; -} -EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale); - -static void set_b1_regs(void) -{ - unsigned long top, bottom; - int es; - u16 w; - unsigned long en, fn; - long ei, fi; - unsigned long vxres; - unsigned int xscale, yscale; - - switch (lcd_dma.data_type) { - case OMAP_DMA_DATA_TYPE_S8: - es = 1; - break; - case OMAP_DMA_DATA_TYPE_S16: - es = 2; - break; - case OMAP_DMA_DATA_TYPE_S32: - es = 4; - break; - default: - BUG(); - return; - } - - vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres; - xscale = lcd_dma.xscale ? lcd_dma.xscale : 1; - yscale = lcd_dma.yscale ? lcd_dma.yscale : 1; - BUG_ON(vxres < lcd_dma.xres); - -#define PIXADDR(x, y) (lcd_dma.addr + \ - ((y) * vxres * yscale + (x) * xscale) * es) -#define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1) - - switch (lcd_dma.rotate) { - case 0: - if (!lcd_dma.mirror) { - top = PIXADDR(0, 0); - bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1); - /* 1510 DMA requires the bottom address to be 2 more - * than the actual last memory access location. */ - if (cpu_is_omap15xx() && - lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32) - bottom += 2; - ei = PIXSTEP(0, 0, 1, 0); - fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1); - } else { - top = PIXADDR(lcd_dma.xres - 1, 0); - bottom = PIXADDR(0, lcd_dma.yres - 1); - ei = PIXSTEP(1, 0, 0, 0); - fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1); - } - en = lcd_dma.xres; - fn = lcd_dma.yres; - break; - case 90: - if (!lcd_dma.mirror) { - top = PIXADDR(0, lcd_dma.yres - 1); - bottom = PIXADDR(lcd_dma.xres - 1, 0); - ei = PIXSTEP(0, 1, 0, 0); - fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1); - } else { - top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1); - bottom = PIXADDR(0, 0); - ei = PIXSTEP(0, 1, 0, 0); - fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1); - } - en = lcd_dma.yres; - fn = lcd_dma.xres; - break; - case 180: - if (!lcd_dma.mirror) { - top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1); - bottom = PIXADDR(0, 0); - ei = PIXSTEP(1, 0, 0, 0); - fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0); - } else { - top = PIXADDR(0, lcd_dma.yres - 1); - bottom = PIXADDR(lcd_dma.xres - 1, 0); - ei = PIXSTEP(0, 0, 1, 0); - fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0); - } - en = lcd_dma.xres; - fn = lcd_dma.yres; - break; - case 270: - if (!lcd_dma.mirror) { - top = PIXADDR(lcd_dma.xres - 1, 0); - bottom = PIXADDR(0, lcd_dma.yres - 1); - ei = PIXSTEP(0, 0, 0, 1); - fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0); - } else { - top = PIXADDR(0, 0); - bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1); - ei = PIXSTEP(0, 0, 0, 1); - fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0); - } - en = lcd_dma.yres; - fn = lcd_dma.xres; - break; - default: - BUG(); - return; /* Suppress warning about uninitialized vars */ - } - - if (cpu_is_omap15xx()) { - omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U); - omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L); - omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U); - omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L); - - return; - } - - /* 1610 regs */ - omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U); - omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L); - omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U); - omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L); - - omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1); - omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1); - - w = omap_readw(OMAP1610_DMA_LCD_CSDP); - w &= ~0x03; - w |= lcd_dma.data_type; - omap_writew(w, OMAP1610_DMA_LCD_CSDP); - - w = omap_readw(OMAP1610_DMA_LCD_CTRL); - /* Always set the source port as SDRAM for now*/ - w &= ~(0x03 << 6); - if (lcd_dma.callback != NULL) - w |= 1 << 1; /* Block interrupt enable */ - else - w &= ~(1 << 1); - omap_writew(w, OMAP1610_DMA_LCD_CTRL); - - if (!(lcd_dma.rotate || lcd_dma.mirror || - lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale)) - return; - - w = omap_readw(OMAP1610_DMA_LCD_CCR); - /* Set the double-indexed addressing mode */ - w |= (0x03 << 12); - omap_writew(w, OMAP1610_DMA_LCD_CCR); - - omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1); - omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U); - omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L); -} - -static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id) -{ - u16 w; - - w = omap_readw(OMAP1610_DMA_LCD_CTRL); - if (unlikely(!(w & (1 << 3)))) { - printk(KERN_WARNING "Spurious LCD DMA IRQ\n"); - return IRQ_NONE; - } - /* Ack the IRQ */ - w |= (1 << 3); - omap_writew(w, OMAP1610_DMA_LCD_CTRL); - lcd_dma.active = 0; - if (lcd_dma.callback != NULL) - lcd_dma.callback(w, lcd_dma.cb_data); - - return IRQ_HANDLED; -} - -int omap_request_lcd_dma(void (*callback)(u16 status, void *data), - void *data) -{ - spin_lock_irq(&lcd_dma.lock); - if (lcd_dma.reserved) { - spin_unlock_irq(&lcd_dma.lock); - printk(KERN_ERR "LCD DMA channel already reserved\n"); - BUG(); - return -EBUSY; - } - lcd_dma.reserved = 1; - spin_unlock_irq(&lcd_dma.lock); - lcd_dma.callback = callback; - lcd_dma.cb_data = data; - lcd_dma.active = 0; - lcd_dma.single_transfer = 0; - lcd_dma.rotate = 0; - lcd_dma.vxres = 0; - lcd_dma.mirror = 0; - lcd_dma.xscale = 0; - lcd_dma.yscale = 0; - lcd_dma.ext_ctrl = 0; - lcd_dma.src_port = 0; - - return 0; -} -EXPORT_SYMBOL(omap_request_lcd_dma); - -void omap_free_lcd_dma(void) -{ - spin_lock(&lcd_dma.lock); - if (!lcd_dma.reserved) { - spin_unlock(&lcd_dma.lock); - printk(KERN_ERR "LCD DMA is not reserved\n"); - BUG(); - return; - } - if (!cpu_is_omap15xx()) - omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1, - OMAP1610_DMA_LCD_CCR); - lcd_dma.reserved = 0; - spin_unlock(&lcd_dma.lock); -} -EXPORT_SYMBOL(omap_free_lcd_dma); - -void omap_enable_lcd_dma(void) -{ - u16 w; - - /* - * Set the Enable bit only if an external controller is - * connected. Otherwise the OMAP internal controller will - * start the transfer when it gets enabled. - */ - if (cpu_is_omap15xx() || !lcd_dma.ext_ctrl) - return; - - w = omap_readw(OMAP1610_DMA_LCD_CTRL); - w |= 1 << 8; - omap_writew(w, OMAP1610_DMA_LCD_CTRL); - - lcd_dma.active = 1; - - w = omap_readw(OMAP1610_DMA_LCD_CCR); - w |= 1 << 7; - omap_writew(w, OMAP1610_DMA_LCD_CCR); -} -EXPORT_SYMBOL(omap_enable_lcd_dma); - -void omap_setup_lcd_dma(void) -{ - BUG_ON(lcd_dma.active); - if (!cpu_is_omap15xx()) { - /* Set some reasonable defaults */ - omap_writew(0x5440, OMAP1610_DMA_LCD_CCR); - omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP); - omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL); - } - set_b1_regs(); - if (!cpu_is_omap15xx()) { - u16 w; - - w = omap_readw(OMAP1610_DMA_LCD_CCR); - /* - * If DMA was already active set the end_prog bit to have - * the programmed register set loaded into the active - * register set. - */ - w |= 1 << 11; /* End_prog */ - if (!lcd_dma.single_transfer) - w |= (3 << 8); /* Auto_init, repeat */ - omap_writew(w, OMAP1610_DMA_LCD_CCR); - } -} -EXPORT_SYMBOL(omap_setup_lcd_dma); - -void omap_stop_lcd_dma(void) -{ - u16 w; - - lcd_dma.active = 0; - if (cpu_is_omap15xx() || !lcd_dma.ext_ctrl) - return; - - w = omap_readw(OMAP1610_DMA_LCD_CCR); - w &= ~(1 << 7); - omap_writew(w, OMAP1610_DMA_LCD_CCR); - - w = omap_readw(OMAP1610_DMA_LCD_CTRL); - w &= ~(1 << 8); - omap_writew(w, OMAP1610_DMA_LCD_CTRL); -} -EXPORT_SYMBOL(omap_stop_lcd_dma); - -static int __init omap_init_lcd_dma(void) -{ - int r; - - if (!cpu_class_is_omap1()) - return -ENODEV; - - if (cpu_is_omap16xx()) { - u16 w; - - /* this would prevent OMAP sleep */ - w = omap_readw(OMAP1610_DMA_LCD_CTRL); - w &= ~(1 << 8); - omap_writew(w, OMAP1610_DMA_LCD_CTRL); - } - - spin_lock_init(&lcd_dma.lock); - - r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0, - "LCD DMA", NULL); - if (r != 0) - pr_err("unable to request IRQ for LCD DMA (error %d)\n", r); - - return r; -} - -arch_initcall(omap_init_lcd_dma); - diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c index f36c34f47f11..05c25c432449 100644 --- a/arch/arm/mach-omap1/mcbsp.c +++ b/arch/arm/mach-omap1/mcbsp.c @@ -15,14 +15,13 @@ #include <linux/io.h> #include <linux/platform_device.h> #include <linux/slab.h> - #include <linux/omap-dma.h> -#include <mach/mux.h> -#include "soc.h" +#include <linux/soc/ti/omap1-io.h> #include <linux/platform_data/asoc-ti-mcbsp.h> -#include <mach/irqs.h> - +#include "mux.h" +#include "soc.h" +#include "irqs.h" #include "iomap.h" #define DPS_RSTCT2_PER_EN (1 << 0) @@ -44,8 +43,8 @@ static void omap1_mcbsp_request(unsigned int id) api_clk = clk_get(NULL, "api_ck"); dsp_clk = clk_get(NULL, "dsp_ck"); if (!IS_ERR(api_clk) && !IS_ERR(dsp_clk)) { - clk_enable(api_clk); - clk_enable(dsp_clk); + clk_prepare_enable(api_clk); + clk_prepare_enable(dsp_clk); /* * DSP external peripheral reset @@ -63,11 +62,11 @@ static void omap1_mcbsp_free(unsigned int id) if (id == 0 || id == 2) { if (--dsp_use == 0) { if (!IS_ERR(api_clk)) { - clk_disable(api_clk); + clk_disable_unprepare(api_clk); clk_put(api_clk); } if (!IS_ERR(dsp_clk)) { - clk_disable(dsp_clk); + clk_disable_unprepare(dsp_clk); clk_put(dsp_clk); } } diff --git a/arch/arm/mach-omap1/include/mach/mtd-xip.h b/arch/arm/mach-omap1/mtd-xip.h index d09b2bc4920f..5ae312ff08a1 100644 --- a/arch/arm/mach-omap1/include/mach/mtd-xip.h +++ b/arch/arm/mach-omap1/mtd-xip.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * MTD primitives for XIP support. Architecture specific functions. * @@ -5,16 +6,14 @@ * * Author: Vladimir Barinov <vbarinov@embeddedalley.com> * - * (c) 2005 MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express or - * implied. + * (c) 2005 MontaVista Software, Inc. */ #ifndef __ARCH_OMAP_MTD_XIP_H__ #define __ARCH_OMAP_MTD_XIP_H__ -#include <mach/hardware.h> +#include "hardware.h" +#include <linux/soc/ti/omap1-io.h> #define OMAP_MPU_TIMER_BASE (0xfffec500) #define OMAP_MPU_TIMER_OFFSET 0x100 diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c index 972665bf52d6..2d9458ff1d29 100644 --- a/arch/arm/mach-omap1/mux.c +++ b/arch/arm/mach-omap1/mux.c @@ -12,10 +12,10 @@ #include <linux/init.h> #include <linux/io.h> #include <linux/spinlock.h> +#include <linux/soc/ti/omap1-io.h> -#include <mach/hardware.h> - -#include <mach/mux.h> +#include "hardware.h" +#include "mux.h" #ifdef CONFIG_OMAP_MUX diff --git a/arch/arm/mach-omap1/mux.h b/arch/arm/mach-omap1/mux.h new file mode 100644 index 000000000000..3e7ed3348a55 --- /dev/null +++ b/arch/arm/mach-omap1/mux.h @@ -0,0 +1,144 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Table of the Omap register configurations for the FUNC_MUX and + * PULL_DWN combinations. + * + * Copyright (C) 2004 - 2008 Texas Instruments Inc. + * Copyright (C) 2003 - 2008 Nokia Corporation + * + * Written by Tony Lindgren + * + * NOTE: Please use the following naming style for new pin entries. + * For example, W8_1610_MMC2_DAT0, where: + * - W8 = ball + * - 1610 = 1510 or 1610, none if common for both 1510 and 1610 + * - MMC2_DAT0 = function + */ + +#ifndef __ASM_ARCH_MUX_H +#define __ASM_ARCH_MUX_H + +#include <linux/soc/ti/omap1-mux.h> + +#define PU_PD_SEL_NA 0 /* No pu_pd reg available */ +#define PULL_DWN_CTRL_NA 0 /* No pull-down control needed */ + +#ifdef CONFIG_OMAP_MUX_DEBUG +#define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \ + .mux_reg = FUNC_MUX_CTRL_##reg, \ + .mask_offset = mode_offset, \ + .mask = mode, + +#define PULL_REG(reg, bit, status) .pull_name = "PULL_DWN_CTRL_"#reg, \ + .pull_reg = PULL_DWN_CTRL_##reg, \ + .pull_bit = bit, \ + .pull_val = status, + +#define PU_PD_REG(reg, status) .pu_pd_name = "PU_PD_SEL_"#reg, \ + .pu_pd_reg = PU_PD_SEL_##reg, \ + .pu_pd_val = status, + +#define MUX_REG_7XX(reg, mode_offset, mode) .mux_reg_name = "OMAP7XX_IO_CONF_"#reg, \ + .mux_reg = OMAP7XX_IO_CONF_##reg, \ + .mask_offset = mode_offset, \ + .mask = mode, + +#define PULL_REG_7XX(reg, bit, status) .pull_name = "OMAP7XX_IO_CONF_"#reg, \ + .pull_reg = OMAP7XX_IO_CONF_##reg, \ + .pull_bit = bit, \ + .pull_val = status, + +#else + +#define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \ + .mask_offset = mode_offset, \ + .mask = mode, + +#define PULL_REG(reg, bit, status) .pull_reg = PULL_DWN_CTRL_##reg, \ + .pull_bit = bit, \ + .pull_val = status, + +#define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \ + .pu_pd_val = status, + +#define MUX_REG_7XX(reg, mode_offset, mode) \ + .mux_reg = OMAP7XX_IO_CONF_##reg, \ + .mask_offset = mode_offset, \ + .mask = mode, + +#define PULL_REG_7XX(reg, bit, status) .pull_reg = OMAP7XX_IO_CONF_##reg, \ + .pull_bit = bit, \ + .pull_val = status, + +#endif /* CONFIG_OMAP_MUX_DEBUG */ + +#define MUX_CFG(desc, mux_reg, mode_offset, mode, \ + pull_reg, pull_bit, pull_status, \ + pu_pd_reg, pu_pd_status, debug_status) \ +{ \ + .name = desc, \ + .debug = debug_status, \ + MUX_REG(mux_reg, mode_offset, mode) \ + PULL_REG(pull_reg, pull_bit, pull_status) \ + PU_PD_REG(pu_pd_reg, pu_pd_status) \ +}, + + +/* + * OMAP730/850 has a slightly different config for the pin mux. + * - config regs are the OMAP7XX_IO_CONF_x regs (see omap7xx.h) regs and + * not the FUNC_MUX_CTRL_x regs from hardware.h + * - for pull-up/down, only has one enable bit which is in the same register + * as mux config + */ +#define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode, \ + pull_bit, pull_status, debug_status)\ +{ \ + .name = desc, \ + .debug = debug_status, \ + MUX_REG_7XX(mux_reg, mode_offset, mode) \ + PULL_REG_7XX(mux_reg, pull_bit, pull_status) \ + PU_PD_REG(NA, 0) \ +}, + +struct pin_config { + char *name; + const unsigned int mux_reg; + unsigned char debug; + + const unsigned char mask_offset; + const unsigned char mask; + + const char *pull_name; + const unsigned int pull_reg; + const unsigned char pull_val; + const unsigned char pull_bit; + + const char *pu_pd_name; + const unsigned int pu_pd_reg; + const unsigned char pu_pd_val; + +#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS) + const char *mux_reg_name; +#endif + +}; + +struct omap_mux_cfg { + struct pin_config *pins; + unsigned long size; + int (*cfg_reg)(const struct pin_config *cfg); +}; + +#ifdef CONFIG_OMAP_MUX +/* setup pin muxing in Linux */ +extern int omap1_mux_init(void); +extern int omap_mux_register(struct omap_mux_cfg *); +#else +/* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */ +static inline int omap1_mux_init(void) { return 0; } +#endif + +extern int omap2_mux_init(void); + +#endif diff --git a/arch/arm/mach-omap1/ocpi.c b/arch/arm/mach-omap1/ocpi.c index 380ea2de58c1..d48f726571a4 100644 --- a/arch/arm/mach-omap1/ocpi.c +++ b/arch/arm/mach-omap1/ocpi.c @@ -20,9 +20,9 @@ #include <linux/err.h> #include <linux/clk.h> #include <linux/io.h> +#include <linux/soc/ti/omap1-io.h> -#include <mach/hardware.h> - +#include "hardware.h" #include "common.h" #define OCPI_BASE 0xfffec320 @@ -73,7 +73,7 @@ static int __init omap_ocpi_init(void) if (IS_ERR(ocpi_ck)) return PTR_ERR(ocpi_ck); - clk_enable(ocpi_ck); + clk_prepare_enable(ocpi_ck); ocpi_enable(); pr_info("OMAP OCPI interconnect driver loaded\n"); @@ -87,7 +87,7 @@ static void __exit omap_ocpi_exit(void) if (!cpu_is_omap16xx()) return; - clk_disable(ocpi_ck); + clk_disable_unprepare(ocpi_ck); clk_put(ocpi_ck); } diff --git a/arch/arm/mach-omap1/omap-dma.c b/arch/arm/mach-omap1/omap-dma.c new file mode 100644 index 000000000000..f7e62de427f3 --- /dev/null +++ b/arch/arm/mach-omap1/omap-dma.c @@ -0,0 +1,884 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * linux/arch/arm/plat-omap/dma.c + * + * Copyright (C) 2003 - 2008 Nokia Corporation + * Author: Juha Yrjölä <juha.yrjola@nokia.com> + * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com> + * Graphics DMA and LCD DMA graphics tranformations + * by Imre Deak <imre.deak@nokia.com> + * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc. + * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com> + * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc. + * + * Copyright (C) 2009 Texas Instruments + * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> + * + * Support functions for the OMAP internal DMA channels. + * + * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/ + * Converted DMA library into DMA platform driver. + * - G, Manjunath Kondaiah <manjugk@ti.com> + */ + +#include <linux/module.h> +#include <linux/init.h> +#include <linux/sched.h> +#include <linux/spinlock.h> +#include <linux/errno.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/io.h> +#include <linux/slab.h> +#include <linux/delay.h> + +#include <linux/omap-dma.h> + +#include <linux/soc/ti/omap1-io.h> +#include <linux/soc/ti/omap1-soc.h> + +#include "tc.h" + +/* + * MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA + * channels that an instance of the SDMA IP block can support. Used + * to size arrays. (The actual maximum on a particular SoC may be less + * than this -- for example, OMAP1 SDMA instances only support 17 logical + * DMA channels.) + */ +#define MAX_LOGICAL_DMA_CH_COUNT 32 + +#undef DEBUG + +#define OMAP_DMA_ACTIVE 0x01 + +#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec) + +static struct omap_system_dma_plat_info *p; +static struct omap_dma_dev_attr *d; +static int enable_1510_mode; +static u32 errata; + +struct dma_link_info { + int *linked_dmach_q; + int no_of_lchs_linked; + + int q_count; + int q_tail; + int q_head; + + int chain_state; + int chain_mode; + +}; + +static int dma_lch_count; +static int dma_chan_count; +static int omap_dma_reserve_channels; + +static DEFINE_SPINLOCK(dma_chan_lock); +static struct omap_dma_lch *dma_chan; + +static inline void omap_disable_channel_irq(int lch) +{ + /* disable channel interrupts */ + p->dma_write(0, CICR, lch); + /* Clear CSR */ + p->dma_read(CSR, lch); +} + +static inline void set_gdma_dev(int req, int dev) +{ + u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4; + int shift = ((req - 1) % 5) * 6; + u32 l; + + l = omap_readl(reg); + l &= ~(0x3f << shift); + l |= (dev - 1) << shift; + omap_writel(l, reg); +} + +#if IS_ENABLED(CONFIG_FB_OMAP) +void omap_set_dma_priority(int lch, int dst_port, int priority) +{ + unsigned long reg; + u32 l; + + if (dma_omap1()) { + switch (dst_port) { + case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */ + reg = OMAP_TC_OCPT1_PRIOR; + break; + case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */ + reg = OMAP_TC_OCPT2_PRIOR; + break; + case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */ + reg = OMAP_TC_EMIFF_PRIOR; + break; + case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */ + reg = OMAP_TC_EMIFS_PRIOR; + break; + default: + BUG(); + return; + } + l = omap_readl(reg); + l &= ~(0xf << 8); + l |= (priority & 0xf) << 8; + omap_writel(l, reg); + } +} +EXPORT_SYMBOL(omap_set_dma_priority); +#endif + +#if IS_ENABLED(CONFIG_USB_OMAP) +#ifdef CONFIG_ARCH_OMAP15XX +/* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */ +static int omap_dma_in_1510_mode(void) +{ + return enable_1510_mode; +} +#else +#define omap_dma_in_1510_mode() 0 +#endif + +void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, + int frame_count, int sync_mode, + int dma_trigger, int src_or_dst_synch) +{ + u32 l; + u16 ccr; + + l = p->dma_read(CSDP, lch); + l &= ~0x03; + l |= data_type; + p->dma_write(l, CSDP, lch); + + ccr = p->dma_read(CCR, lch); + ccr &= ~(1 << 5); + if (sync_mode == OMAP_DMA_SYNC_FRAME) + ccr |= 1 << 5; + p->dma_write(ccr, CCR, lch); + + ccr = p->dma_read(CCR2, lch); + ccr &= ~(1 << 2); + if (sync_mode == OMAP_DMA_SYNC_BLOCK) + ccr |= 1 << 2; + p->dma_write(ccr, CCR2, lch); + p->dma_write(elem_count, CEN, lch); + p->dma_write(frame_count, CFN, lch); +} +EXPORT_SYMBOL(omap_set_dma_transfer_params); + +void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode) +{ + if (!dma_omap15xx()) { + u32 l; + + l = p->dma_read(LCH_CTRL, lch); + l &= ~0x7; + l |= mode; + p->dma_write(l, LCH_CTRL, lch); + } +} +EXPORT_SYMBOL(omap_set_dma_channel_mode); + +/* Note that src_port is only for omap1 */ +void omap_set_dma_src_params(int lch, int src_port, int src_amode, + unsigned long src_start, + int src_ei, int src_fi) +{ + u32 l; + u16 w; + + w = p->dma_read(CSDP, lch); + w &= ~(0x1f << 2); + w |= src_port << 2; + p->dma_write(w, CSDP, lch); + + l = p->dma_read(CCR, lch); + l &= ~(0x03 << 12); + l |= src_amode << 12; + p->dma_write(l, CCR, lch); + + p->dma_write(src_start, CSSA, lch); + + p->dma_write(src_ei, CSEI, lch); + p->dma_write(src_fi, CSFI, lch); +} +EXPORT_SYMBOL(omap_set_dma_src_params); + +void omap_set_dma_src_data_pack(int lch, int enable) +{ + u32 l; + + l = p->dma_read(CSDP, lch); + l &= ~(1 << 6); + if (enable) + l |= (1 << 6); + p->dma_write(l, CSDP, lch); +} +EXPORT_SYMBOL(omap_set_dma_src_data_pack); + +void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) +{ + unsigned int burst = 0; + u32 l; + + l = p->dma_read(CSDP, lch); + l &= ~(0x03 << 7); + + switch (burst_mode) { + case OMAP_DMA_DATA_BURST_DIS: + break; + case OMAP_DMA_DATA_BURST_4: + burst = 0x2; + break; + case OMAP_DMA_DATA_BURST_8: + /* + * not supported by current hardware on OMAP1 + * w |= (0x03 << 7); + */ + fallthrough; + case OMAP_DMA_DATA_BURST_16: + /* OMAP1 don't support burst 16 */ + fallthrough; + default: + BUG(); + } + + l |= (burst << 7); + p->dma_write(l, CSDP, lch); +} +EXPORT_SYMBOL(omap_set_dma_src_burst_mode); + +/* Note that dest_port is only for OMAP1 */ +void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode, + unsigned long dest_start, + int dst_ei, int dst_fi) +{ + u32 l; + + l = p->dma_read(CSDP, lch); + l &= ~(0x1f << 9); + l |= dest_port << 9; + p->dma_write(l, CSDP, lch); + + l = p->dma_read(CCR, lch); + l &= ~(0x03 << 14); + l |= dest_amode << 14; + p->dma_write(l, CCR, lch); + + p->dma_write(dest_start, CDSA, lch); + + p->dma_write(dst_ei, CDEI, lch); + p->dma_write(dst_fi, CDFI, lch); +} +EXPORT_SYMBOL(omap_set_dma_dest_params); + +void omap_set_dma_dest_data_pack(int lch, int enable) +{ + u32 l; + + l = p->dma_read(CSDP, lch); + l &= ~(1 << 13); + if (enable) + l |= 1 << 13; + p->dma_write(l, CSDP, lch); +} +EXPORT_SYMBOL(omap_set_dma_dest_data_pack); + +void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) +{ + unsigned int burst = 0; + u32 l; + + l = p->dma_read(CSDP, lch); + l &= ~(0x03 << 14); + + switch (burst_mode) { + case OMAP_DMA_DATA_BURST_DIS: + break; + case OMAP_DMA_DATA_BURST_4: + burst = 0x2; + break; + case OMAP_DMA_DATA_BURST_8: + burst = 0x3; + break; + case OMAP_DMA_DATA_BURST_16: + /* OMAP1 don't support burst 16 */ + fallthrough; + default: + printk(KERN_ERR "Invalid DMA burst mode\n"); + BUG(); + return; + } + l |= (burst << 14); + p->dma_write(l, CSDP, lch); +} +EXPORT_SYMBOL(omap_set_dma_dest_burst_mode); + +static inline void omap_enable_channel_irq(int lch) +{ + /* Clear CSR */ + p->dma_read(CSR, lch); + + /* Enable some nice interrupts. */ + p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch); +} + +void omap_disable_dma_irq(int lch, u16 bits) +{ + dma_chan[lch].enabled_irqs &= ~bits; +} +EXPORT_SYMBOL(omap_disable_dma_irq); + +static inline void enable_lnk(int lch) +{ + u32 l; + + l = p->dma_read(CLNK_CTRL, lch); + + l &= ~(1 << 14); + + /* Set the ENABLE_LNK bits */ + if (dma_chan[lch].next_lch != -1) + l = dma_chan[lch].next_lch | (1 << 15); + + p->dma_write(l, CLNK_CTRL, lch); +} + +static inline void disable_lnk(int lch) +{ + u32 l; + + l = p->dma_read(CLNK_CTRL, lch); + + /* Disable interrupts */ + omap_disable_channel_irq(lch); + + /* Set the STOP_LNK bit */ + l |= 1 << 14; + + p->dma_write(l, CLNK_CTRL, lch); + dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE; +} +#endif + +int omap_request_dma(int dev_id, const char *dev_name, + void (*callback)(int lch, u16 ch_status, void *data), + void *data, int *dma_ch_out) +{ + int ch, free_ch = -1; + unsigned long flags; + struct omap_dma_lch *chan; + + WARN(strcmp(dev_name, "DMA engine"), "Using deprecated platform DMA API - please update to DMA engine"); + + spin_lock_irqsave(&dma_chan_lock, flags); + for (ch = 0; ch < dma_chan_count; ch++) { + if (free_ch == -1 && dma_chan[ch].dev_id == -1) { + free_ch = ch; + /* Exit after first free channel found */ + break; + } + } + if (free_ch == -1) { + spin_unlock_irqrestore(&dma_chan_lock, flags); + return -EBUSY; + } + chan = dma_chan + free_ch; + chan->dev_id = dev_id; + + if (p->clear_lch_regs) + p->clear_lch_regs(free_ch); + + spin_unlock_irqrestore(&dma_chan_lock, flags); + + chan->dev_name = dev_name; + chan->callback = callback; + chan->data = data; + chan->flags = 0; + + chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ; + + chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ; + + if (dma_omap16xx()) { + /* If the sync device is set, configure it dynamically. */ + if (dev_id != 0) { + set_gdma_dev(free_ch + 1, dev_id); + dev_id = free_ch + 1; + } + /* + * Disable the 1510 compatibility mode and set the sync device + * id. + */ + p->dma_write(dev_id | (1 << 10), CCR, free_ch); + } else { + p->dma_write(dev_id, CCR, free_ch); + } + + *dma_ch_out = free_ch; + + return 0; +} +EXPORT_SYMBOL(omap_request_dma); + +void omap_free_dma(int lch) +{ + unsigned long flags; + + if (dma_chan[lch].dev_id == -1) { + pr_err("omap_dma: trying to free unallocated DMA channel %d\n", + lch); + return; + } + + /* Disable all DMA interrupts for the channel. */ + omap_disable_channel_irq(lch); + + /* Make sure the DMA transfer is stopped. */ + p->dma_write(0, CCR, lch); + + spin_lock_irqsave(&dma_chan_lock, flags); + dma_chan[lch].dev_id = -1; + dma_chan[lch].next_lch = -1; + dma_chan[lch].callback = NULL; + spin_unlock_irqrestore(&dma_chan_lock, flags); +} +EXPORT_SYMBOL(omap_free_dma); + +/* + * Clears any DMA state so the DMA engine is ready to restart with new buffers + * through omap_start_dma(). Any buffers in flight are discarded. + */ +static void omap_clear_dma(int lch) +{ + unsigned long flags; + + local_irq_save(flags); + p->clear_dma(lch); + local_irq_restore(flags); +} + +#if IS_ENABLED(CONFIG_USB_OMAP) +void omap_start_dma(int lch) +{ + u32 l; + + /* + * The CPC/CDAC register needs to be initialized to zero + * before starting dma transfer. + */ + if (dma_omap15xx()) + p->dma_write(0, CPC, lch); + else + p->dma_write(0, CDAC, lch); + + if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { + int next_lch, cur_lch; + char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT]; + + /* Set the link register of the first channel */ + enable_lnk(lch); + + memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map)); + dma_chan_link_map[lch] = 1; + + cur_lch = dma_chan[lch].next_lch; + do { + next_lch = dma_chan[cur_lch].next_lch; + + /* The loop case: we've been here already */ + if (dma_chan_link_map[cur_lch]) + break; + /* Mark the current channel */ + dma_chan_link_map[cur_lch] = 1; + + enable_lnk(cur_lch); + omap_enable_channel_irq(cur_lch); + + cur_lch = next_lch; + } while (next_lch != -1); + } else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS)) + p->dma_write(lch, CLNK_CTRL, lch); + + omap_enable_channel_irq(lch); + + l = p->dma_read(CCR, lch); + + if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING)) + l |= OMAP_DMA_CCR_BUFFERING_DISABLE; + l |= OMAP_DMA_CCR_EN; + + /* + * As dma_write() uses IO accessors which are weakly ordered, there + * is no guarantee that data in coherent DMA memory will be visible + * to the DMA device. Add a memory barrier here to ensure that any + * such data is visible prior to enabling DMA. + */ + mb(); + p->dma_write(l, CCR, lch); + + dma_chan[lch].flags |= OMAP_DMA_ACTIVE; +} +EXPORT_SYMBOL(omap_start_dma); + +void omap_stop_dma(int lch) +{ + u32 l; + + /* Disable all interrupts on the channel */ + omap_disable_channel_irq(lch); + + l = p->dma_read(CCR, lch); + if (IS_DMA_ERRATA(DMA_ERRATA_i541) && + (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) { + int i = 0; + u32 sys_cf; + + /* Configure No-Standby */ + l = p->dma_read(OCP_SYSCONFIG, lch); + sys_cf = l; + l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK; + l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE); + p->dma_write(l , OCP_SYSCONFIG, 0); + + l = p->dma_read(CCR, lch); + l &= ~OMAP_DMA_CCR_EN; + p->dma_write(l, CCR, lch); + + /* Wait for sDMA FIFO drain */ + l = p->dma_read(CCR, lch); + while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE | + OMAP_DMA_CCR_WR_ACTIVE))) { + udelay(5); + i++; + l = p->dma_read(CCR, lch); + } + if (i >= 100) + pr_err("DMA drain did not complete on lch %d\n", lch); + /* Restore OCP_SYSCONFIG */ + p->dma_write(sys_cf, OCP_SYSCONFIG, lch); + } else { + l &= ~OMAP_DMA_CCR_EN; + p->dma_write(l, CCR, lch); + } + + /* + * Ensure that data transferred by DMA is visible to any access + * after DMA has been disabled. This is important for coherent + * DMA regions. + */ + mb(); + + if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { + int next_lch, cur_lch = lch; + char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT]; + + memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map)); + do { + /* The loop case: we've been here already */ + if (dma_chan_link_map[cur_lch]) + break; + /* Mark the current channel */ + dma_chan_link_map[cur_lch] = 1; + + disable_lnk(cur_lch); + + next_lch = dma_chan[cur_lch].next_lch; + cur_lch = next_lch; + } while (next_lch != -1); + } + + dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE; +} +EXPORT_SYMBOL(omap_stop_dma); + +/* + * Allows changing the DMA callback function or data. This may be needed if + * the driver shares a single DMA channel for multiple dma triggers. + */ +/* + * Returns current physical source address for the given DMA channel. + * If the channel is running the caller must disable interrupts prior calling + * this function and process the returned value before re-enabling interrupt to + * prevent races with the interrupt handler. Note that in continuous mode there + * is a chance for CSSA_L register overflow between the two reads resulting + * in incorrect return value. + */ +dma_addr_t omap_get_dma_src_pos(int lch) +{ + dma_addr_t offset = 0; + + if (dma_omap15xx()) + offset = p->dma_read(CPC, lch); + else + offset = p->dma_read(CSAC, lch); + + if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0) + offset = p->dma_read(CSAC, lch); + + if (!dma_omap15xx()) { + /* + * CDAC == 0 indicates that the DMA transfer on the channel has + * not been started (no data has been transferred so far). + * Return the programmed source start address in this case. + */ + if (likely(p->dma_read(CDAC, lch))) + offset = p->dma_read(CSAC, lch); + else + offset = p->dma_read(CSSA, lch); + } + + offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000); + + return offset; +} +EXPORT_SYMBOL(omap_get_dma_src_pos); + +/* + * Returns current physical destination address for the given DMA channel. + * If the channel is running the caller must disable interrupts prior calling + * this function and process the returned value before re-enabling interrupt to + * prevent races with the interrupt handler. Note that in continuous mode there + * is a chance for CDSA_L register overflow between the two reads resulting + * in incorrect return value. + */ +dma_addr_t omap_get_dma_dst_pos(int lch) +{ + dma_addr_t offset = 0; + + if (dma_omap15xx()) + offset = p->dma_read(CPC, lch); + else + offset = p->dma_read(CDAC, lch); + + /* + * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is + * read before the DMA controller finished disabling the channel. + */ + if (!dma_omap15xx() && offset == 0) { + offset = p->dma_read(CDAC, lch); + /* + * CDAC == 0 indicates that the DMA transfer on the channel has + * not been started (no data has been transferred so far). + * Return the programmed destination start address in this case. + */ + if (unlikely(!offset)) + offset = p->dma_read(CDSA, lch); + } + + offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000); + + return offset; +} +EXPORT_SYMBOL(omap_get_dma_dst_pos); + +int omap_get_dma_active_status(int lch) +{ + return (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) != 0; +} +EXPORT_SYMBOL(omap_get_dma_active_status); +#endif + +int omap_dma_running(void) +{ + int lch; + + if (omap_lcd_dma_running()) + return 1; + + for (lch = 0; lch < dma_chan_count; lch++) + if (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) + return 1; + + return 0; +} + +/*----------------------------------------------------------------------------*/ + +static int omap1_dma_handle_ch(int ch) +{ + u32 csr; + + if (enable_1510_mode && ch >= 6) { + csr = dma_chan[ch].saved_csr; + dma_chan[ch].saved_csr = 0; + } else + csr = p->dma_read(CSR, ch); + if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) { + dma_chan[ch + 6].saved_csr = csr >> 7; + csr &= 0x7f; + } + if ((csr & 0x3f) == 0) + return 0; + if (unlikely(dma_chan[ch].dev_id == -1)) { + pr_warn("Spurious interrupt from DMA channel %d (CSR %04x)\n", + ch, csr); + return 0; + } + if (unlikely(csr & OMAP1_DMA_TOUT_IRQ)) + pr_warn("DMA timeout with device %d\n", dma_chan[ch].dev_id); + if (unlikely(csr & OMAP_DMA_DROP_IRQ)) + pr_warn("DMA synchronization event drop occurred with device %d\n", + dma_chan[ch].dev_id); + if (likely(csr & OMAP_DMA_BLOCK_IRQ)) + dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE; + if (likely(dma_chan[ch].callback != NULL)) + dma_chan[ch].callback(ch, csr, dma_chan[ch].data); + + return 1; +} + +static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id) +{ + int ch = ((int) dev_id) - 1; + int handled = 0; + + for (;;) { + int handled_now = 0; + + handled_now += omap1_dma_handle_ch(ch); + if (enable_1510_mode && dma_chan[ch + 6].saved_csr) + handled_now += omap1_dma_handle_ch(ch + 6); + if (!handled_now) + break; + handled += handled_now; + } + + return handled ? IRQ_HANDLED : IRQ_NONE; +} + +struct omap_system_dma_plat_info *omap_get_plat_info(void) +{ + return p; +} +EXPORT_SYMBOL_GPL(omap_get_plat_info); + +static int omap_system_dma_probe(struct platform_device *pdev) +{ + int ch, ret = 0; + int dma_irq; + char irq_name[4]; + + p = pdev->dev.platform_data; + if (!p) { + dev_err(&pdev->dev, + "%s: System DMA initialized without platform data\n", + __func__); + return -EINVAL; + } + + d = p->dma_attr; + errata = p->errata; + + if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels + && (omap_dma_reserve_channels < d->lch_count)) + d->lch_count = omap_dma_reserve_channels; + + dma_lch_count = d->lch_count; + dma_chan_count = dma_lch_count; + enable_1510_mode = d->dev_caps & ENABLE_1510_MODE; + + dma_chan = devm_kcalloc(&pdev->dev, dma_lch_count, + sizeof(*dma_chan), GFP_KERNEL); + if (!dma_chan) + return -ENOMEM; + + for (ch = 0; ch < dma_chan_count; ch++) { + omap_clear_dma(ch); + + dma_chan[ch].dev_id = -1; + dma_chan[ch].next_lch = -1; + + if (ch >= 6 && enable_1510_mode) + continue; + + /* + * request_irq() doesn't like dev_id (ie. ch) being + * zero, so we have to kludge around this. + */ + sprintf(&irq_name[0], "%d", ch); + dma_irq = platform_get_irq_byname(pdev, irq_name); + + if (dma_irq < 0) { + ret = dma_irq; + goto exit_dma_irq_fail; + } + + /* INT_DMA_LCD is handled in lcd_dma.c */ + if (dma_irq == INT_DMA_LCD) + continue; + + ret = request_irq(dma_irq, + omap1_dma_irq_handler, 0, "DMA", + (void *) (ch + 1)); + if (ret != 0) + goto exit_dma_irq_fail; + } + + /* reserve dma channels 0 and 1 in high security devices on 34xx */ + if (d->dev_caps & HS_CHANNELS_RESERVED) { + pr_info("Reserving DMA channels 0 and 1 for HS ROM code\n"); + dma_chan[0].dev_id = 0; + dma_chan[1].dev_id = 1; + } + p->show_dma_caps(); + return 0; + +exit_dma_irq_fail: + return ret; +} + +static int omap_system_dma_remove(struct platform_device *pdev) +{ + int dma_irq, irq_rel = 0; + + for ( ; irq_rel < dma_chan_count; irq_rel++) { + dma_irq = platform_get_irq(pdev, irq_rel); + free_irq(dma_irq, (void *)(irq_rel + 1)); + } + + return 0; +} + +static struct platform_driver omap_system_dma_driver = { + .probe = omap_system_dma_probe, + .remove = omap_system_dma_remove, + .driver = { + .name = "omap_dma_system" + }, +}; + +static int __init omap_system_dma_init(void) +{ + return platform_driver_register(&omap_system_dma_driver); +} +arch_initcall(omap_system_dma_init); + +static void __exit omap_system_dma_exit(void) +{ + platform_driver_unregister(&omap_system_dma_driver); +} + +MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Texas Instruments Inc"); + +/* + * Reserve the omap SDMA channels using cmdline bootarg + * "omap_dma_reserve_ch=". The valid range is 1 to 32 + */ +static int __init omap_dma_cmdline_reserve_ch(char *str) +{ + if (get_option(&str, &omap_dma_reserve_channels) != 1) + omap_dma_reserve_channels = 0; + return 1; +} + +__setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch); + + diff --git a/arch/arm/mach-omap1/include/mach/omap1510.h b/arch/arm/mach-omap1/omap1510.h index 3d235244bf5c..3d235244bf5c 100644 --- a/arch/arm/mach-omap1/include/mach/omap1510.h +++ b/arch/arm/mach-omap1/omap1510.h diff --git a/arch/arm/mach-omap1/include/mach/omap16xx.h b/arch/arm/mach-omap1/omap16xx.h index cd1c724869c7..cd1c724869c7 100644 --- a/arch/arm/mach-omap1/include/mach/omap16xx.h +++ b/arch/arm/mach-omap1/omap16xx.h diff --git a/arch/arm/mach-omap1/include/mach/omap7xx.h b/arch/arm/mach-omap1/omap7xx.h index 63da994bc609..63da994bc609 100644 --- a/arch/arm/mach-omap1/include/mach/omap7xx.h +++ b/arch/arm/mach-omap1/omap7xx.h diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c index a745d64d4699..fce7d2b572bf 100644 --- a/arch/arm/mach-omap1/pm.c +++ b/arch/arm/mach-omap1/pm.c @@ -52,13 +52,14 @@ #include <asm/mach/time.h> #include <asm/mach/irq.h> -#include <mach/tc.h> -#include <mach/mux.h> +#include <linux/soc/ti/omap1-io.h> +#include "tc.h" #include <linux/omap-dma.h> #include <clocksource/timer-ti-dm.h> -#include <mach/irqs.h> - +#include "hardware.h" +#include "mux.h" +#include "irqs.h" #include "iomap.h" #include "clock.h" #include "pm.h" diff --git a/arch/arm/mach-omap1/pm.h b/arch/arm/mach-omap1/pm.h index cd926dcb5e7f..d9165709c532 100644 --- a/arch/arm/mach-omap1/pm.h +++ b/arch/arm/mach-omap1/pm.h @@ -34,6 +34,8 @@ #ifndef __ARCH_ARM_MACH_OMAP1_PM_H #define __ARCH_ARM_MACH_OMAP1_PM_H +#include <linux/soc/ti/omap1-io.h> + /* * ---------------------------------------------------------------------------- * Register and offset definitions to be used in PM assembler code diff --git a/arch/arm/mach-omap1/pm_bus.c b/arch/arm/mach-omap1/pm_bus.c index 667c1637ff91..c04619ac0631 100644 --- a/arch/arm/mach-omap1/pm_bus.c +++ b/arch/arm/mach-omap1/pm_bus.c @@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Runtime PM support code for OMAP1 * * Author: Kevin Hilman, Deep Root Systems, LLC * * Copyright (C) 2010 Texas Instruments, Inc. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ #include <linux/init.h> #include <linux/kernel.h> @@ -43,4 +40,3 @@ static int __init omap1_pm_runtime_init(void) return 0; } core_initcall(omap1_pm_runtime_init); - diff --git a/arch/arm/mach-omap1/reset.c b/arch/arm/mach-omap1/reset.c index af2c120b0c4e..2eee6a6965ff 100644 --- a/arch/arm/mach-omap1/reset.c +++ b/arch/arm/mach-omap1/reset.c @@ -6,8 +6,7 @@ #include <linux/io.h> #include <linux/reboot.h> -#include <mach/hardware.h> - +#include "hardware.h" #include "iomap.h" #include "common.h" diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c index 9eb591fbfd89..88928fc33b2e 100644 --- a/arch/arm/mach-omap1/serial.c +++ b/arch/arm/mach-omap1/serial.c @@ -19,8 +19,8 @@ #include <asm/mach-types.h> -#include <mach/mux.h> - +#include "serial.h" +#include "mux.h" #include "pm.h" #include "soc.h" @@ -141,7 +141,7 @@ void __init omap_serial_init(void) if (IS_ERR(uart1_ck)) printk("Could not get uart1_ck\n"); else { - clk_enable(uart1_ck); + clk_prepare_enable(uart1_ck); if (cpu_is_omap15xx()) clk_set_rate(uart1_ck, 12000000); } @@ -151,7 +151,7 @@ void __init omap_serial_init(void) if (IS_ERR(uart2_ck)) printk("Could not get uart2_ck\n"); else { - clk_enable(uart2_ck); + clk_prepare_enable(uart2_ck); if (cpu_is_omap15xx()) clk_set_rate(uart2_ck, 12000000); else @@ -163,7 +163,7 @@ void __init omap_serial_init(void) if (IS_ERR(uart3_ck)) printk("Could not get uart3_ck\n"); else { - clk_enable(uart3_ck); + clk_prepare_enable(uart3_ck); if (cpu_is_omap15xx()) clk_set_rate(uart3_ck, 12000000); } diff --git a/arch/arm/mach-omap1/include/mach/serial.h b/arch/arm/mach-omap1/serial.h index 4700e384c3d9..4700e384c3d9 100644 --- a/arch/arm/mach-omap1/include/mach/serial.h +++ b/arch/arm/mach-omap1/serial.h diff --git a/arch/arm/mach-omap1/sleep.S b/arch/arm/mach-omap1/sleep.S index a908c51839a4..f111b79512ce 100644 --- a/arch/arm/mach-omap1/sleep.S +++ b/arch/arm/mach-omap1/sleep.S @@ -36,7 +36,7 @@ #include <asm/assembler.h> -#include <mach/hardware.h> +#include "hardware.h" #include "iomap.h" #include "pm.h" diff --git a/arch/arm/mach-omap1/soc.h b/arch/arm/mach-omap1/soc.h index 69daf0187b1d..5fb57fdd9c2b 100644 --- a/arch/arm/mach-omap1/soc.h +++ b/arch/arm/mach-omap1/soc.h @@ -1,4 +1,6 @@ /* - * We can move mach/soc.h here once the drivers are fixed + * We can move linux/soc/ti/omap1-soc.h here once the drivers are fixed */ -#include <mach/soc.h> +#include "hardware.h" +#include "irqs.h" +#include <asm/irq.h> diff --git a/arch/arm/mach-omap1/sram-init.c b/arch/arm/mach-omap1/sram-init.c index 3bd60708c345..27c42e2a21cc 100644 --- a/arch/arm/mach-omap1/sram-init.c +++ b/arch/arm/mach-omap1/sram-init.c @@ -14,6 +14,7 @@ #include <asm/fncpy.h> #include <asm/tlb.h> #include <asm/cacheflush.h> +#include <asm/set_memory.h> #include <asm/mach/map.h> @@ -22,18 +23,77 @@ #define OMAP1_SRAM_PA 0x20000000 #define SRAM_BOOTLOADER_SZ 0x80 +#define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1))) + +static void __iomem *omap_sram_base; +static unsigned long omap_sram_start; +static unsigned long omap_sram_skip; +static unsigned long omap_sram_size; +static void __iomem *omap_sram_ceil; + +/* + * Memory allocator for SRAM: calculates the new ceiling address + * for pushing a function using the fncpy API. + * + * Note that fncpy requires the returned address to be aligned + * to an 8-byte boundary. + */ +static void *omap_sram_push_address(unsigned long size) +{ + unsigned long available, new_ceil = (unsigned long)omap_sram_ceil; + + available = omap_sram_ceil - (omap_sram_base + omap_sram_skip); + + if (size > available) { + pr_err("Not enough space in SRAM\n"); + return NULL; + } + + new_ceil -= size; + new_ceil = ROUND_DOWN(new_ceil, FNCPY_ALIGN); + omap_sram_ceil = IOMEM(new_ceil); + + return (void __force *)omap_sram_ceil; +} + +void *omap_sram_push(void *funcp, unsigned long size) +{ + void *sram; + unsigned long base; + int pages; + void *dst = NULL; + + sram = omap_sram_push_address(size); + if (!sram) + return NULL; + + base = (unsigned long)sram & PAGE_MASK; + pages = PAGE_ALIGN(size) / PAGE_SIZE; + + set_memory_rw(base, pages); + + dst = fncpy(sram, funcp, size); + + set_memory_ro(base, pages); + set_memory_x(base, pages); + + return dst; +} /* * The amount of SRAM depends on the core type. * Note that we cannot try to test for SRAM here because writes * to secure SRAM will hang the system. Also the SRAM is not * yet mapped at this point. + * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early. */ static void __init omap_detect_and_map_sram(void) { - unsigned long omap_sram_skip = SRAM_BOOTLOADER_SZ; - unsigned long omap_sram_start = OMAP1_SRAM_PA; - unsigned long omap_sram_size; + unsigned long base; + int pages; + + omap_sram_skip = SRAM_BOOTLOADER_SZ; + omap_sram_start = OMAP1_SRAM_PA; if (cpu_is_omap7xx()) omap_sram_size = 0x32000; /* 200K */ @@ -47,8 +107,27 @@ static void __init omap_detect_and_map_sram(void) omap_sram_size = 0x4000; } - omap_map_sram(omap_sram_start, omap_sram_size, - omap_sram_skip, 1); + omap_sram_start = ROUND_DOWN(omap_sram_start, PAGE_SIZE); + omap_sram_base = __arm_ioremap_exec(omap_sram_start, omap_sram_size, 1); + if (!omap_sram_base) { + pr_err("SRAM: Could not map\n"); + return; + } + + omap_sram_ceil = omap_sram_base + omap_sram_size; + + /* + * Looks like we need to preserve some bootloader code at the + * beginning of SRAM for jumping to flash for reboot to work... + */ + memset_io(omap_sram_base + omap_sram_skip, 0, + omap_sram_size - omap_sram_skip); + + base = (unsigned long)omap_sram_base; + pages = PAGE_ALIGN(omap_sram_size) / PAGE_SIZE; + + set_memory_ro(base, pages); + set_memory_x(base, pages); } static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl); @@ -62,7 +141,7 @@ void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl) _omap_sram_reprogram_clock(dpllctl, ckctl); } -int __init omap_sram_init(void) +int __init omap1_sram_init(void) { omap_detect_and_map_sram(); _omap_sram_reprogram_clock = diff --git a/arch/arm/mach-omap1/sram.S b/arch/arm/mach-omap1/sram.S index 37f34fcd65fb..89f4dc1b70f0 100644 --- a/arch/arm/mach-omap1/sram.S +++ b/arch/arm/mach-omap1/sram.S @@ -6,11 +6,11 @@ */ #include <linux/linkage.h> +#include <linux/soc/ti/omap1-io.h> #include <asm/assembler.h> -#include <mach/hardware.h> - +#include "hardware.h" #include "iomap.h" .text diff --git a/arch/arm/mach-omap1/sram.h b/arch/arm/mach-omap1/sram.h index 73efabd119e8..f45e6dd6d7e5 100644 --- a/arch/arm/mach-omap1/sram.h +++ b/arch/arm/mach-omap1/sram.h @@ -1,8 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0 */ -#include <plat/sram.h> extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl); +int omap1_sram_init(void); +void *omap_sram_push(void *funcp, unsigned long size); + /* Do not use these */ extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl); extern unsigned long omap1_sram_reprogram_clock_sz; diff --git a/arch/arm/mach-omap1/include/mach/tc.h b/arch/arm/mach-omap1/tc.h index adaab6a0bd08..243454bc0684 100644 --- a/arch/arm/mach-omap1/include/mach/tc.h +++ b/arch/arm/mach-omap1/tc.h @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ /* - * arch/arm/plat-omap/include/mach/tc.h - * * OMAP Traffic Controller * * Copyright (C) 2004 Nokia Corporation diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c index de590a85a42b..d5e127851dc7 100644 --- a/arch/arm/mach-omap1/time.c +++ b/arch/arm/mach-omap1/time.c @@ -47,12 +47,14 @@ #include <asm/irq.h> -#include <mach/hardware.h> #include <asm/mach/irq.h> #include <asm/mach/time.h> +#include "hardware.h" +#include "mux.h" #include "iomap.h" #include "common.h" +#include "clock.h" #ifdef CONFIG_OMAP_MPU_TIMER @@ -224,6 +226,9 @@ static inline void omap_mpu_timer_init(void) */ void __init omap1_timer_init(void) { + omap1_clk_init(); + omap1_mux_init(); + if (omap_32k_timer_init() != 0) omap_mpu_timer_init(); } diff --git a/arch/arm/mach-omap1/timer.c b/arch/arm/mach-omap1/timer.c index 0411d5508d63..f5cd4bbf7566 100644 --- a/arch/arm/mach-omap1/timer.c +++ b/arch/arm/mach-omap1/timer.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * OMAP1 Dual-Mode Timers - platform device registration * @@ -9,15 +10,6 @@ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ * Tarun Kanti DebBarma <tarun.kanti@ti.com> * Thara Gopinath <thara@ti.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <linux/clk.h> @@ -26,6 +18,7 @@ #include <linux/slab.h> #include <linux/platform_device.h> #include <linux/platform_data/dmtimer-omap.h> +#include <linux/soc/ti/omap1-io.h> #include <clocksource/timer-ti-dm.h> diff --git a/arch/arm/mach-omap1/timer32k.c b/arch/arm/mach-omap1/timer32k.c index 780fdf03c3ce..410d17d1d443 100644 --- a/arch/arm/mach-omap1/timer32k.c +++ b/arch/arm/mach-omap1/timer32k.c @@ -45,15 +45,13 @@ #include <linux/clocksource.h> #include <linux/clockchips.h> #include <linux/io.h> +#include <linux/sched_clock.h> #include <asm/irq.h> #include <asm/mach/irq.h> #include <asm/mach/time.h> -#include <plat/counter-32k.h> - -#include <mach/hardware.h> - +#include "hardware.h" #include "common.h" /* @@ -159,6 +157,98 @@ static __init void omap_init_32k_timer(void) OMAP_32K_TICKS_PER_SEC, 1, 0xfffffffe); } +/* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */ +#define OMAP2_32KSYNCNT_REV_OFF 0x0 +#define OMAP2_32KSYNCNT_REV_SCHEME (0x3 << 30) +#define OMAP2_32KSYNCNT_CR_OFF_LOW 0x10 +#define OMAP2_32KSYNCNT_CR_OFF_HIGH 0x30 + +/* + * 32KHz clocksource ... always available, on pretty most chips except + * OMAP 730 and 1510. Other timers could be used as clocksources, with + * higher resolution in free-running counter modes (e.g. 12 MHz xtal), + * but systems won't necessarily want to spend resources that way. + */ +static void __iomem *sync32k_cnt_reg; + +static u64 notrace omap_32k_read_sched_clock(void) +{ + return sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0; +} + +/** + * omap_read_persistent_clock64 - Return time from a persistent clock. + * + * Reads the time from a source which isn't disabled during PM, the + * 32k sync timer. Convert the cycles elapsed since last read into + * nsecs and adds to a monotonically increasing timespec64. + */ +static struct timespec64 persistent_ts; +static cycles_t cycles; +static unsigned int persistent_mult, persistent_shift; + +static void omap_read_persistent_clock64(struct timespec64 *ts) +{ + unsigned long long nsecs; + cycles_t last_cycles; + + last_cycles = cycles; + cycles = sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0; + + nsecs = clocksource_cyc2ns(cycles - last_cycles, + persistent_mult, persistent_shift); + + timespec64_add_ns(&persistent_ts, nsecs); + + *ts = persistent_ts; +} + +/** + * omap_init_clocksource_32k - setup and register counter 32k as a + * kernel clocksource + * @pbase: base addr of counter_32k module + * @size: size of counter_32k to map + * + * Returns 0 upon success or negative error code upon failure. + * + */ +static int __init omap_init_clocksource_32k(void __iomem *vbase) +{ + int ret; + + /* + * 32k sync Counter IP register offsets vary between the + * highlander version and the legacy ones. + * The 'SCHEME' bits(30-31) of the revision register is used + * to identify the version. + */ + if (readl_relaxed(vbase + OMAP2_32KSYNCNT_REV_OFF) & + OMAP2_32KSYNCNT_REV_SCHEME) + sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_HIGH; + else + sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_LOW; + + /* + * 120000 rough estimate from the calculations in + * __clocksource_update_freq_scale. + */ + clocks_calc_mult_shift(&persistent_mult, &persistent_shift, + 32768, NSEC_PER_SEC, 120000); + + ret = clocksource_mmio_init(sync32k_cnt_reg, "32k_counter", 32768, + 250, 32, clocksource_mmio_readl_up); + if (ret) { + pr_err("32k_counter: can't register clocksource\n"); + return ret; + } + + sched_clock_register(omap_32k_read_sched_clock, 32, 32768); + register_persistent_clock(omap_read_persistent_clock64); + pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n"); + + return 0; +} + /* * --------------------------------------------------------------------------- * Timer initialization @@ -180,7 +270,7 @@ int __init omap_32k_timer_init(void) sync32k_ick = clk_get(NULL, "omap_32ksync_ick"); if (!IS_ERR(sync32k_ick)) - clk_enable(sync32k_ick); + clk_prepare_enable(sync32k_ick); ret = omap_init_clocksource_32k(base); } diff --git a/arch/arm/mach-omap1/usb.c b/arch/arm/mach-omap1/usb.c index e60831c82b78..0119f3ddb7a6 100644 --- a/arch/arm/mach-omap1/usb.c +++ b/arch/arm/mach-omap1/usb.c @@ -12,13 +12,13 @@ #include <linux/dma-map-ops.h> #include <linux/io.h> #include <linux/delay.h> +#include <linux/soc/ti/omap1-io.h> #include <asm/irq.h> -#include <mach/mux.h> - -#include <mach/usb.h> - +#include "hardware.h" +#include "mux.h" +#include "usb.h" #include "common.h" /* These routines should handle the standard chip-specific modes diff --git a/arch/arm/mach-omap1/usb.h b/arch/arm/mach-omap1/usb.h new file mode 100644 index 000000000000..08c9344c46e3 --- /dev/null +++ b/arch/arm/mach-omap1/usb.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * fixme correct answer depends on hmc_mode, + * as does (on omap1) any nonzero value for config->otg port number + */ +#include <linux/platform_data/usb-omap1.h> +#include <linux/soc/ti/omap1-usb.h> + +#if IS_ENABLED(CONFIG_USB_OMAP) +#define is_usb0_device(config) 1 +#else +#define is_usb0_device(config) 0 +#endif + +#if IS_ENABLED(CONFIG_USB_SUPPORT) +void omap1_usb_init(struct omap_usb_config *pdata); +#else +static inline void omap1_usb_init(struct omap_usb_config *pdata) +{ +} +#endif + +#define OMAP1_OHCI_BASE 0xfffba000 +#define OMAP2_OHCI_BASE 0x4805e000 +#define OMAP_OHCI_BASE OMAP1_OHCI_BASE |