diff options
Diffstat (limited to 'arch/arm/mach-omap2/prm33xx.h')
| -rw-r--r-- | arch/arm/mach-omap2/prm33xx.h | 52 |
1 files changed, 2 insertions, 50 deletions
diff --git a/arch/arm/mach-omap2/prm33xx.h b/arch/arm/mach-omap2/prm33xx.h index 66302c6aba61..3081f3deb650 100644 --- a/arch/arm/mach-omap2/prm33xx.h +++ b/arch/arm/mach-omap2/prm33xx.h @@ -1,16 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * AM33XX PRM instance offset macros * - * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef __ARCH_ARM_MACH_OMAP2_PRM33XX_H @@ -35,63 +27,27 @@ #define AM33XX_PRM_GFX_MOD 0x1100 #define AM33XX_PRM_CEFUSE_MOD 0x1200 -/* PRM */ - -/* PRM.OCP_SOCKET_PRM register offsets */ -#define AM33XX_REVISION_PRM_OFFSET 0x0000 -#define AM33XX_REVISION_PRM AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0000) -#define AM33XX_PRM_IRQSTATUS_MPU_OFFSET 0x0004 -#define AM33XX_PRM_IRQSTATUS_MPU AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0004) -#define AM33XX_PRM_IRQENABLE_MPU_OFFSET 0x0008 -#define AM33XX_PRM_IRQENABLE_MPU AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0008) -#define AM33XX_PRM_IRQSTATUS_M3_OFFSET 0x000c -#define AM33XX_PRM_IRQSTATUS_M3 AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x000c) -#define AM33XX_PRM_IRQENABLE_M3_OFFSET 0x0010 -#define AM33XX_PRM_IRQENABLE_M3 AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0010) - /* PRM.PER_PRM register offsets */ -#define AM33XX_RM_PER_RSTCTRL_OFFSET 0x0000 -#define AM33XX_RM_PER_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0000) #define AM33XX_PM_PER_PWRSTST_OFFSET 0x0008 #define AM33XX_PM_PER_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0008) #define AM33XX_PM_PER_PWRSTCTRL_OFFSET 0x000c #define AM33XX_PM_PER_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x000c) /* PRM.WKUP_PRM register offsets */ -#define AM33XX_RM_WKUP_RSTCTRL_OFFSET 0x0000 -#define AM33XX_RM_WKUP_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0000) #define AM33XX_PM_WKUP_PWRSTCTRL_OFFSET 0x0004 #define AM33XX_PM_WKUP_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0004) #define AM33XX_PM_WKUP_PWRSTST_OFFSET 0x0008 #define AM33XX_PM_WKUP_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0008) -#define AM33XX_RM_WKUP_RSTST_OFFSET 0x000c -#define AM33XX_RM_WKUP_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x000c) /* PRM.MPU_PRM register offsets */ #define AM33XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000 #define AM33XX_PM_MPU_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0000) #define AM33XX_PM_MPU_PWRSTST_OFFSET 0x0004 #define AM33XX_PM_MPU_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0004) -#define AM33XX_RM_MPU_RSTST_OFFSET 0x0008 -#define AM33XX_RM_MPU_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0008) /* PRM.DEVICE_PRM register offsets */ #define AM33XX_PRM_RSTCTRL_OFFSET 0x0000 #define AM33XX_PRM_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0000) -#define AM33XX_PRM_RSTTIME_OFFSET 0x0004 -#define AM33XX_PRM_RSTTIME AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0004) -#define AM33XX_PRM_RSTST_OFFSET 0x0008 -#define AM33XX_PRM_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0008) -#define AM33XX_PRM_SRAM_COUNT_OFFSET 0x000c -#define AM33XX_PRM_SRAM_COUNT AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x000c) -#define AM33XX_PRM_LDO_SRAM_CORE_SETUP_OFFSET 0x0010 -#define AM33XX_PRM_LDO_SRAM_CORE_SETUP AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0010) -#define AM33XX_PRM_LDO_SRAM_CORE_CTRL_OFFSET 0x0014 -#define AM33XX_PRM_LDO_SRAM_CORE_CTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0014) -#define AM33XX_PRM_LDO_SRAM_MPU_SETUP_OFFSET 0x0018 -#define AM33XX_PRM_LDO_SRAM_MPU_SETUP AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0018) -#define AM33XX_PRM_LDO_SRAM_MPU_CTRL_OFFSET 0x001c -#define AM33XX_PRM_LDO_SRAM_MPU_CTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x001c) /* PRM.RTC_PRM register offsets */ #define AM33XX_PM_RTC_PWRSTCTRL_OFFSET 0x0000 @@ -102,12 +58,8 @@ /* PRM.GFX_PRM register offsets */ #define AM33XX_PM_GFX_PWRSTCTRL_OFFSET 0x0000 #define AM33XX_PM_GFX_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0000) -#define AM33XX_RM_GFX_RSTCTRL_OFFSET 0x0004 -#define AM33XX_RM_GFX_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0004) #define AM33XX_PM_GFX_PWRSTST_OFFSET 0x0010 #define AM33XX_PM_GFX_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0010) -#define AM33XX_RM_GFX_RSTST_OFFSET 0x0014 -#define AM33XX_RM_GFX_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0014) /* PRM.CEFUSE_PRM register offsets */ #define AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET 0x0000 |