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-rw-r--r--arch/arm/mach-sa1100/include/mach/SA-1100.h229
-rw-r--r--arch/arm/mach-sa1100/include/mach/assabet.h15
-rw-r--r--arch/arm/mach-sa1100/include/mach/cerf.h15
-rw-r--r--arch/arm/mach-sa1100/include/mach/dma.h117
-rw-r--r--arch/arm/mach-sa1100/include/mach/entry-macro.S6
-rw-r--r--arch/arm/mach-sa1100/include/mach/io.h20
-rw-r--r--arch/arm/mach-sa1100/include/mach/irqs.h27
-rw-r--r--arch/arm/mach-sa1100/include/mach/mcp.h2
-rw-r--r--arch/arm/mach-sa1100/include/mach/nanoengine.h12
-rw-r--r--arch/arm/mach-sa1100/include/mach/neponset.h52
-rw-r--r--arch/arm/mach-sa1100/include/mach/shannon.h14
-rw-r--r--arch/arm/mach-sa1100/include/mach/simpad.h6
-rw-r--r--arch/arm/mach-sa1100/include/mach/system.h9
13 files changed, 43 insertions, 481 deletions
diff --git a/arch/arm/mach-sa1100/include/mach/SA-1100.h b/arch/arm/mach-sa1100/include/mach/SA-1100.h
index bae8296f5dbf..3f2d1b60188c 100644
--- a/arch/arm/mach-sa1100/include/mach/SA-1100.h
+++ b/arch/arm/mach-sa1100/include/mach/SA-1100.h
@@ -1590,224 +1590,9 @@
/*
* Direct Memory Access (DMA) control registers
- *
- * Registers
- * DDAR0 Direct Memory Access (DMA) Device Address Register
- * channel 0 (read/write).
- * DCSR0 Direct Memory Access (DMA) Control and Status
- * Register channel 0 (read/write).
- * DBSA0 Direct Memory Access (DMA) Buffer Start address
- * register A channel 0 (read/write).
- * DBTA0 Direct Memory Access (DMA) Buffer Transfer count
- * register A channel 0 (read/write).
- * DBSB0 Direct Memory Access (DMA) Buffer Start address
- * register B channel 0 (read/write).
- * DBTB0 Direct Memory Access (DMA) Buffer Transfer count
- * register B channel 0 (read/write).
- *
- * DDAR1 Direct Memory Access (DMA) Device Address Register
- * channel 1 (read/write).
- * DCSR1 Direct Memory Access (DMA) Control and Status
- * Register channel 1 (read/write).
- * DBSA1 Direct Memory Access (DMA) Buffer Start address
- * register A channel 1 (read/write).
- * DBTA1 Direct Memory Access (DMA) Buffer Transfer count
- * register A channel 1 (read/write).
- * DBSB1 Direct Memory Access (DMA) Buffer Start address
- * register B channel 1 (read/write).
- * DBTB1 Direct Memory Access (DMA) Buffer Transfer count
- * register B channel 1 (read/write).
- *
- * DDAR2 Direct Memory Access (DMA) Device Address Register
- * channel 2 (read/write).
- * DCSR2 Direct Memory Access (DMA) Control and Status
- * Register channel 2 (read/write).
- * DBSA2 Direct Memory Access (DMA) Buffer Start address
- * register A channel 2 (read/write).
- * DBTA2 Direct Memory Access (DMA) Buffer Transfer count
- * register A channel 2 (read/write).
- * DBSB2 Direct Memory Access (DMA) Buffer Start address
- * register B channel 2 (read/write).
- * DBTB2 Direct Memory Access (DMA) Buffer Transfer count
- * register B channel 2 (read/write).
- *
- * DDAR3 Direct Memory Access (DMA) Device Address Register
- * channel 3 (read/write).
- * DCSR3 Direct Memory Access (DMA) Control and Status
- * Register channel 3 (read/write).
- * DBSA3 Direct Memory Access (DMA) Buffer Start address
- * register A channel 3 (read/write).
- * DBTA3 Direct Memory Access (DMA) Buffer Transfer count
- * register A channel 3 (read/write).
- * DBSB3 Direct Memory Access (DMA) Buffer Start address
- * register B channel 3 (read/write).
- * DBTB3 Direct Memory Access (DMA) Buffer Transfer count
- * register B channel 3 (read/write).
- *
- * DDAR4 Direct Memory Access (DMA) Device Address Register
- * channel 4 (read/write).
- * DCSR4 Direct Memory Access (DMA) Control and Status
- * Register channel 4 (read/write).
- * DBSA4 Direct Memory Access (DMA) Buffer Start address
- * register A channel 4 (read/write).
- * DBTA4 Direct Memory Access (DMA) Buffer Transfer count
- * register A channel 4 (read/write).
- * DBSB4 Direct Memory Access (DMA) Buffer Start address
- * register B channel 4 (read/write).
- * DBTB4 Direct Memory Access (DMA) Buffer Transfer count
- * register B channel 4 (read/write).
- *
- * DDAR5 Direct Memory Access (DMA) Device Address Register
- * channel 5 (read/write).
- * DCSR5 Direct Memory Access (DMA) Control and Status
- * Register channel 5 (read/write).
- * DBSA5 Direct Memory Access (DMA) Buffer Start address
- * register A channel 5 (read/write).
- * DBTA5 Direct Memory Access (DMA) Buffer Transfer count
- * register A channel 5 (read/write).
- * DBSB5 Direct Memory Access (DMA) Buffer Start address
- * register B channel 5 (read/write).
- * DBTB5 Direct Memory Access (DMA) Buffer Transfer count
- * register B channel 5 (read/write).
*/
-
-#define DMASp 0x00000020 /* DMA control reg. Space [byte] */
-
-#define DDAR(Nb) __REG(0xB0000000 + (Nb)*DMASp) /* DMA Device Address Reg. channel [0..5] */
-#define SetDCSR(Nb) __REG(0xB0000004 + (Nb)*DMASp) /* Set DMA Control & Status Reg. channel [0..5] (write) */
-#define ClrDCSR(Nb) __REG(0xB0000008 + (Nb)*DMASp) /* Clear DMA Control & Status Reg. channel [0..5] (write) */
-#define RdDCSR(Nb) __REG(0xB000000C + (Nb)*DMASp) /* Read DMA Control & Status Reg. channel [0..5] (read) */
-#define DBSA(Nb) __REG(0xB0000010 + (Nb)*DMASp) /* DMA Buffer Start address reg. A channel [0..5] */
-#define DBTA(Nb) __REG(0xB0000014 + (Nb)*DMASp) /* DMA Buffer Transfer count reg. A channel [0..5] */
-#define DBSB(Nb) __REG(0xB0000018 + (Nb)*DMASp) /* DMA Buffer Start address reg. B channel [0..5] */
-#define DBTB(Nb) __REG(0xB000001C + (Nb)*DMASp) /* DMA Buffer Transfer count reg. B channel [0..5] */
-
-#define DDAR_RW 0x00000001 /* device data Read/Write */
-#define DDAR_DevWr (DDAR_RW*0) /* Device data Write */
- /* (memory -> device) */
-#define DDAR_DevRd (DDAR_RW*1) /* Device data Read */
- /* (device -> memory) */
-#define DDAR_E 0x00000002 /* big/little Endian device */
-#define DDAR_LtlEnd (DDAR_E*0) /* Little Endian device */
-#define DDAR_BigEnd (DDAR_E*1) /* Big Endian device */
-#define DDAR_BS 0x00000004 /* device Burst Size */
-#define DDAR_Brst4 (DDAR_BS*0) /* Burst-of-4 device */
-#define DDAR_Brst8 (DDAR_BS*1) /* Burst-of-8 device */
-#define DDAR_DW 0x00000008 /* device Data Width */
-#define DDAR_8BitDev (DDAR_DW*0) /* 8-Bit Device */
-#define DDAR_16BitDev (DDAR_DW*1) /* 16-Bit Device */
-#define DDAR_DS Fld (4, 4) /* Device Select */
-#define DDAR_Ser0UDCTr /* Ser. port 0 UDC Transmit */ \
- (0x0 << FShft (DDAR_DS))
-#define DDAR_Ser0UDCRc /* Ser. port 0 UDC Receive */ \
- (0x1 << FShft (DDAR_DS))
-#define DDAR_Ser1SDLCTr /* Ser. port 1 SDLC Transmit */ \
- (0x2 << FShft (DDAR_DS))
-#define DDAR_Ser1SDLCRc /* Ser. port 1 SDLC Receive */ \
- (0x3 << FShft (DDAR_DS))
-#define DDAR_Ser1UARTTr /* Ser. port 1 UART Transmit */ \
- (0x4 << FShft (DDAR_DS))
-#define DDAR_Ser1UARTRc /* Ser. port 1 UART Receive */ \
- (0x5 << FShft (DDAR_DS))
-#define DDAR_Ser2ICPTr /* Ser. port 2 ICP Transmit */ \
- (0x6 << FShft (DDAR_DS))
-#define DDAR_Ser2ICPRc /* Ser. port 2 ICP Receive */ \
- (0x7 << FShft (DDAR_DS))
-#define DDAR_Ser3UARTTr /* Ser. port 3 UART Transmit */ \
- (0x8 << FShft (DDAR_DS))
-#define DDAR_Ser3UARTRc /* Ser. port 3 UART Receive */ \
- (0x9 << FShft (DDAR_DS))
-#define DDAR_Ser4MCP0Tr /* Ser. port 4 MCP 0 Transmit */ \
- /* (audio) */ \
- (0xA << FShft (DDAR_DS))
-#define DDAR_Ser4MCP0Rc /* Ser. port 4 MCP 0 Receive */ \
- /* (audio) */ \
- (0xB << FShft (DDAR_DS))
-#define DDAR_Ser4MCP1Tr /* Ser. port 4 MCP 1 Transmit */ \
- /* (telecom) */ \
- (0xC << FShft (DDAR_DS))
-#define DDAR_Ser4MCP1Rc /* Ser. port 4 MCP 1 Receive */ \
- /* (telecom) */ \
- (0xD << FShft (DDAR_DS))
-#define DDAR_Ser4SSPTr /* Ser. port 4 SSP Transmit */ \
- (0xE << FShft (DDAR_DS))
-#define DDAR_Ser4SSPRc /* Ser. port 4 SSP Receive */ \
- (0xF << FShft (DDAR_DS))
-#define DDAR_DA Fld (24, 8) /* Device Address */
-#define DDAR_DevAdd(Add) /* Device Address */ \
- (((Add) & 0xF0000000) | \
- (((Add) & 0X003FFFFC) << (FShft (DDAR_DA) - 2)))
-#define DDAR_Ser0UDCWr /* Ser. port 0 UDC Write */ \
- (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \
- DDAR_Ser0UDCTr + DDAR_DevAdd (__PREG(Ser0UDCDR)))
-#define DDAR_Ser0UDCRd /* Ser. port 0 UDC Read */ \
- (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \
- DDAR_Ser0UDCRc + DDAR_DevAdd (__PREG(Ser0UDCDR)))
-#define DDAR_Ser1UARTWr /* Ser. port 1 UART Write */ \
- (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
- DDAR_Ser1UARTTr + DDAR_DevAdd (__PREG(Ser1UTDR)))
-#define DDAR_Ser1UARTRd /* Ser. port 1 UART Read */ \
- (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
- DDAR_Ser1UARTRc + DDAR_DevAdd (__PREG(Ser1UTDR)))
-#define DDAR_Ser1SDLCWr /* Ser. port 1 SDLC Write */ \
- (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
- DDAR_Ser1SDLCTr + DDAR_DevAdd (__PREG(Ser1SDDR)))
-#define DDAR_Ser1SDLCRd /* Ser. port 1 SDLC Read */ \
- (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
- DDAR_Ser1SDLCRc + DDAR_DevAdd (__PREG(Ser1SDDR)))
-#define DDAR_Ser2UARTWr /* Ser. port 2 UART Write */ \
- (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
- DDAR_Ser2ICPTr + DDAR_DevAdd (__PREG(Ser2UTDR)))
-#define DDAR_Ser2UARTRd /* Ser. port 2 UART Read */ \
- (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
- DDAR_Ser2ICPRc + DDAR_DevAdd (__PREG(Ser2UTDR)))
-#define DDAR_Ser2HSSPWr /* Ser. port 2 HSSP Write */ \
- (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \
- DDAR_Ser2ICPTr + DDAR_DevAdd (__PREG(Ser2HSDR)))
-#define DDAR_Ser2HSSPRd /* Ser. port 2 HSSP Read */ \
- (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \
- DDAR_Ser2ICPRc + DDAR_DevAdd (__PREG(Ser2HSDR)))
-#define DDAR_Ser3UARTWr /* Ser. port 3 UART Write */ \
- (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
- DDAR_Ser3UARTTr + DDAR_DevAdd (__PREG(Ser3UTDR)))
-#define DDAR_Ser3UARTRd /* Ser. port 3 UART Read */ \
- (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
- DDAR_Ser3UARTRc + DDAR_DevAdd (__PREG(Ser3UTDR)))
-#define DDAR_Ser4MCP0Wr /* Ser. port 4 MCP 0 Write (audio) */ \
- (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
- DDAR_Ser4MCP0Tr + DDAR_DevAdd (__PREG(Ser4MCDR0)))
-#define DDAR_Ser4MCP0Rd /* Ser. port 4 MCP 0 Read (audio) */ \
- (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
- DDAR_Ser4MCP0Rc + DDAR_DevAdd (__PREG(Ser4MCDR0)))
-#define DDAR_Ser4MCP1Wr /* Ser. port 4 MCP 1 Write */ \
- /* (telecom) */ \
- (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
- DDAR_Ser4MCP1Tr + DDAR_DevAdd (__PREG(Ser4MCDR1)))
-#define DDAR_Ser4MCP1Rd /* Ser. port 4 MCP 1 Read */ \
- /* (telecom) */ \
- (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
- DDAR_Ser4MCP1Rc + DDAR_DevAdd (__PREG(Ser4MCDR1)))
-#define DDAR_Ser4SSPWr /* Ser. port 4 SSP Write (16 bits) */ \
- (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
- DDAR_Ser4SSPTr + DDAR_DevAdd (__PREG(Ser4SSDR)))
-#define DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */ \
- (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
- DDAR_Ser4SSPRc + DDAR_DevAdd (__PREG(Ser4SSDR)))
-
-#define DCSR_RUN 0x00000001 /* DMA running */
-#define DCSR_IE 0x00000002 /* DMA Interrupt Enable */
-#define DCSR_ERROR 0x00000004 /* DMA ERROR */
-#define DCSR_DONEA 0x00000008 /* DONE DMA transfer buffer A */
-#define DCSR_STRTA 0x00000010 /* STaRTed DMA transfer buffer A */
-#define DCSR_DONEB 0x00000020 /* DONE DMA transfer buffer B */
-#define DCSR_STRTB 0x00000040 /* STaRTed DMA transfer buffer B */
-#define DCSR_BIU 0x00000080 /* DMA Buffer In Use */
-#define DCSR_BufA (DCSR_BIU*0) /* DMA Buffer A in use */
-#define DCSR_BufB (DCSR_BIU*1) /* DMA Buffer B in use */
-
-#define DBT_TC Fld (13, 0) /* Transfer Count */
-#define DBTA_TCA DBT_TC /* Transfer Count buffer A */
-#define DBTB_TCB DBT_TC /* Transfer Count buffer B */
+#define DMA_SIZE (6 * 0x20)
+#define DMA_PHYS 0xb0000000
/*
@@ -1903,16 +1688,6 @@
#define LCD_Int100_0A 0xF /* LCD Intensity = 100.0% = 1 */
/* (Alternative) */
-#define LCCR0 __REG(0xB0100000) /* LCD Control Reg. 0 */
-#define LCSR __REG(0xB0100004) /* LCD Status Reg. */
-#define DBAR1 __REG(0xB0100010) /* LCD DMA Base Address Reg. channel 1 */
-#define DCAR1 __REG(0xB0100014) /* LCD DMA Current Address Reg. channel 1 */
-#define DBAR2 __REG(0xB0100018) /* LCD DMA Base Address Reg. channel 2 */
-#define DCAR2 __REG(0xB010001C) /* LCD DMA Current Address Reg. channel 2 */
-#define LCCR1 __REG(0xB0100020) /* LCD Control Reg. 1 */
-#define LCCR2 __REG(0xB0100024) /* LCD Control Reg. 2 */
-#define LCCR3 __REG(0xB0100028) /* LCD Control Reg. 3 */
-
#define LCCR0_LEN 0x00000001 /* LCD ENable */
#define LCCR0_CMS 0x00000002 /* Color/Monochrome display Select */
#define LCCR0_Color (LCCR0_CMS*0) /* Color display */
diff --git a/arch/arm/mach-sa1100/include/mach/assabet.h b/arch/arm/mach-sa1100/include/mach/assabet.h
index 28c2cf50c259..307391488c22 100644
--- a/arch/arm/mach-sa1100/include/mach/assabet.h
+++ b/arch/arm/mach-sa1100/include/mach/assabet.h
@@ -85,21 +85,18 @@ extern void ASSABET_BCR_frob(unsigned int mask, unsigned int set);
#define ASSABET_BSR_RAD_RI (1 << 31)
-/* GPIOs for which the generic definition doesn't say much */
+/* GPIOs (bitmasks) for which the generic definition doesn't say much */
#define ASSABET_GPIO_RADIO_IRQ GPIO_GPIO (14) /* Radio interrupt request */
#define ASSABET_GPIO_PS_MODE_SYNC GPIO_GPIO (16) /* Power supply mode/sync */
#define ASSABET_GPIO_STEREO_64FS_CLK GPIO_GPIO (19) /* SSP UDA1341 clock input */
-#define ASSABET_GPIO_CF_IRQ GPIO_GPIO (21) /* CF IRQ */
-#define ASSABET_GPIO_CF_CD GPIO_GPIO (22) /* CF CD */
-#define ASSABET_GPIO_CF_BVD2 GPIO_GPIO (24) /* CF BVD */
#define ASSABET_GPIO_GFX_IRQ GPIO_GPIO (24) /* Graphics IRQ */
-#define ASSABET_GPIO_CF_BVD1 GPIO_GPIO (25) /* CF BVD */
#define ASSABET_GPIO_BATT_LOW GPIO_GPIO (26) /* Low battery */
#define ASSABET_GPIO_RCLK GPIO_GPIO (26) /* CCLK/2 */
-#define ASSABET_IRQ_GPIO_CF_IRQ IRQ_GPIO21
-#define ASSABET_IRQ_GPIO_CF_CD IRQ_GPIO22
-#define ASSABET_IRQ_GPIO_CF_BVD2 IRQ_GPIO24
-#define ASSABET_IRQ_GPIO_CF_BVD1 IRQ_GPIO25
+/* These are gpiolib GPIO numbers, not bitmasks */
+#define ASSABET_GPIO_CF_IRQ 21 /* CF IRQ */
+#define ASSABET_GPIO_CF_CD 22 /* CF CD */
+#define ASSABET_GPIO_CF_BVD2 24 /* CF BVD / IOSPKR */
+#define ASSABET_GPIO_CF_BVD1 25 /* CF BVD / IOSTSCHG */
#endif
diff --git a/arch/arm/mach-sa1100/include/mach/cerf.h b/arch/arm/mach-sa1100/include/mach/cerf.h
index c3ac3d0f9465..88fd9c006ce0 100644
--- a/arch/arm/mach-sa1100/include/mach/cerf.h
+++ b/arch/arm/mach-sa1100/include/mach/cerf.h
@@ -14,15 +14,10 @@
#define CERF_ETH_IO 0xf0000000
#define CERF_ETH_IRQ IRQ_GPIO26
-#define CERF_GPIO_CF_BVD2 GPIO_GPIO (19)
-#define CERF_GPIO_CF_BVD1 GPIO_GPIO (20)
-#define CERF_GPIO_CF_RESET GPIO_GPIO (21)
-#define CERF_GPIO_CF_IRQ GPIO_GPIO (22)
-#define CERF_GPIO_CF_CD GPIO_GPIO (23)
-
-#define CERF_IRQ_GPIO_CF_BVD2 IRQ_GPIO19
-#define CERF_IRQ_GPIO_CF_BVD1 IRQ_GPIO20
-#define CERF_IRQ_GPIO_CF_IRQ IRQ_GPIO22
-#define CERF_IRQ_GPIO_CF_CD IRQ_GPIO23
+#define CERF_GPIO_CF_BVD2 19
+#define CERF_GPIO_CF_BVD1 20
+#define CERF_GPIO_CF_RESET 21
+#define CERF_GPIO_CF_IRQ 22
+#define CERF_GPIO_CF_CD 23
#endif // _INCLUDE_CERF_H_
diff --git a/arch/arm/mach-sa1100/include/mach/dma.h b/arch/arm/mach-sa1100/include/mach/dma.h
deleted file mode 100644
index dda1b351310d..000000000000
--- a/arch/arm/mach-sa1100/include/mach/dma.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * arch/arm/mach-sa1100/include/mach/dma.h
- *
- * Generic SA1100 DMA support
- *
- * Copyright (C) 2000 Nicolas Pitre
- *
- */
-
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H
-
-#include "hardware.h"
-
-
-/*
- * The SA1100 has six internal DMA channels.
- */
-#define SA1100_DMA_CHANNELS 6
-
-/*
- * Maximum physical DMA buffer size
- */
-#define MAX_DMA_SIZE 0x1fff
-#define CUT_DMA_SIZE 0x1000
-
-/*
- * All possible SA1100 devices a DMA channel can be attached to.
- */
-typedef enum {
- DMA_Ser0UDCWr = DDAR_Ser0UDCWr, /* Ser. port 0 UDC Write */
- DMA_Ser0UDCRd = DDAR_Ser0UDCRd, /* Ser. port 0 UDC Read */
- DMA_Ser1UARTWr = DDAR_Ser1UARTWr, /* Ser. port 1 UART Write */
- DMA_Ser1UARTRd = DDAR_Ser1UARTRd, /* Ser. port 1 UART Read */
- DMA_Ser1SDLCWr = DDAR_Ser1SDLCWr, /* Ser. port 1 SDLC Write */
- DMA_Ser1SDLCRd = DDAR_Ser1SDLCRd, /* Ser. port 1 SDLC Read */
- DMA_Ser2UARTWr = DDAR_Ser2UARTWr, /* Ser. port 2 UART Write */
- DMA_Ser2UARTRd = DDAR_Ser2UARTRd, /* Ser. port 2 UART Read */
- DMA_Ser2HSSPWr = DDAR_Ser2HSSPWr, /* Ser. port 2 HSSP Write */
- DMA_Ser2HSSPRd = DDAR_Ser2HSSPRd, /* Ser. port 2 HSSP Read */
- DMA_Ser3UARTWr = DDAR_Ser3UARTWr, /* Ser. port 3 UART Write */
- DMA_Ser3UARTRd = DDAR_Ser3UARTRd, /* Ser. port 3 UART Read */
- DMA_Ser4MCP0Wr = DDAR_Ser4MCP0Wr, /* Ser. port 4 MCP 0 Write (audio) */
- DMA_Ser4MCP0Rd = DDAR_Ser4MCP0Rd, /* Ser. port 4 MCP 0 Read (audio) */
- DMA_Ser4MCP1Wr = DDAR_Ser4MCP1Wr, /* Ser. port 4 MCP 1 Write */
- DMA_Ser4MCP1Rd = DDAR_Ser4MCP1Rd, /* Ser. port 4 MCP 1 Read */
- DMA_Ser4SSPWr = DDAR_Ser4SSPWr, /* Ser. port 4 SSP Write (16 bits) */
- DMA_Ser4SSPRd = DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */
-} dma_device_t;
-
-typedef struct {
- volatile u_long DDAR;
- volatile u_long SetDCSR;
- volatile u_long ClrDCSR;
- volatile u_long RdDCSR;
- volatile dma_addr_t DBSA;
- volatile u_long DBTA;
- volatile dma_addr_t DBSB;
- volatile u_long DBTB;
-} dma_regs_t;
-
-typedef void (*dma_callback_t)(void *data);
-
-/*
- * DMA function prototypes
- */
-
-extern int sa1100_request_dma( dma_device_t device, const char *device_id,
- dma_callback_t callback, void *data,
- dma_regs_t **regs );
-extern void sa1100_free_dma( dma_regs_t *regs );
-extern int sa1100_start_dma( dma_regs_t *regs, dma_addr_t dma_ptr, u_int size );
-extern dma_addr_t sa1100_get_dma_pos(dma_regs_t *regs);
-extern void sa1100_reset_dma(dma_regs_t *regs);
-
-/**
- * sa1100_stop_dma - stop DMA in progress
- * @regs: identifier for the channel to use
- *
- * This stops DMA without clearing buffer pointers. Unlike
- * sa1100_clear_dma() this allows subsequent use of sa1100_resume_dma()
- * or sa1100_get_dma_pos().
- *
- * The @regs identifier is provided by a successful call to
- * sa1100_request_dma().
- **/
-
-#define sa1100_stop_dma(regs) ((regs)->ClrDCSR = DCSR_IE|DCSR_RUN)
-
-/**
- * sa1100_resume_dma - resume DMA on a stopped channel
- * @regs: identifier for the channel to use
- *
- * This resumes DMA on a channel previously stopped with
- * sa1100_stop_dma().
- *
- * The @regs identifier is provided by a successful call to
- * sa1100_request_dma().
- **/
-
-#define sa1100_resume_dma(regs) ((regs)->SetDCSR = DCSR_IE|DCSR_RUN)
-
-/**
- * sa1100_clear_dma - clear DMA pointers
- * @regs: identifier for the channel to use
- *
- * This clear any DMA state so the DMA engine is ready to restart
- * with new buffers through sa1100_start_dma(). Any buffers in flight
- * are discarded.
- *
- * The @regs identifier is provided by a successful call to
- * sa1100_request_dma().
- **/
-
-#define sa1100_clear_dma(regs) ((regs)->ClrDCSR = DCSR_IE|DCSR_RUN|DCSR_STRTA|DCSR_STRTB)
-
-#endif /* _ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-sa1100/include/mach/entry-macro.S b/arch/arm/mach-sa1100/include/mach/entry-macro.S
index 6aa13c46c5d3..8cf7630bf024 100644
--- a/arch/arm/mach-sa1100/include/mach/entry-macro.S
+++ b/arch/arm/mach-sa1100/include/mach/entry-macro.S
@@ -8,17 +8,11 @@
* warranty of any kind, whether express or implied.
*/
- .macro disable_fiq
- .endm
-
.macro get_irqnr_preamble, base, tmp
mov \base, #0xfa000000 @ ICIP = 0xfa050000
add \base, \base, #0x00050000
.endm
- .macro arch_ret_to_user, tmp1, tmp2
- .endm
-
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \irqstat, [\base] @ get irqs
ldr \irqnr, [\base, #4] @ ICMR = 0xfa050004
diff --git a/arch/arm/mach-sa1100/include/mach/io.h b/arch/arm/mach-sa1100/include/mach/io.h
deleted file mode 100644
index dfc27ff08344..000000000000
--- a/arch/arm/mach-sa1100/include/mach/io.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * arch/arm/mach-sa1100/include/mach/io.h
- *
- * Copyright (C) 1997-1999 Russell King
- *
- * Modifications:
- * 06-12-1997 RMK Created.
- * 07-04-1999 RMK Major cleanup
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-/*
- * __io() is required to be an equivalent mapping to __mem_pci() for
- * SOC_COMMON to work.
- */
-#define __io(a) __typesafe_io(a)
-#define __mem_pci(a) (a)
-
-#endif
diff --git a/arch/arm/mach-sa1100/include/mach/irqs.h b/arch/arm/mach-sa1100/include/mach/irqs.h
index d18f21abef80..3790298b7142 100644
--- a/arch/arm/mach-sa1100/include/mach/irqs.h
+++ b/arch/arm/mach-sa1100/include/mach/irqs.h
@@ -71,22 +71,19 @@
/*
* Figure out the MAX IRQ number.
*
- * If we have an SA1111, the max IRQ is S1_BVD1_STSCHG+1.
- * If we have an LoCoMo, the max IRQ is IRQ_BOARD_START + 4
- * Otherwise, we have the standard IRQs only.
+ * Neponset, SA1111 and UCB1x00 are sparse IRQ aware, so can dynamically
+ * allocate their IRQs above NR_IRQS.
+ *
+ * LoCoMo has 4 additional IRQs, but is not sparse IRQ aware, and so has
+ * to be included in the NR_IRQS calculation.
*/
-#ifdef CONFIG_SA1111
-#define NR_IRQS (IRQ_BOARD_END + 55)
-#elif defined(CONFIG_SHARP_LOCOMO)
-#define NR_IRQS (IRQ_BOARD_START + 4)
+#ifdef CONFIG_SHARP_LOCOMO
+#define NR_IRQS_LOCOMO 4
#else
-#define NR_IRQS (IRQ_BOARD_START)
+#define NR_IRQS_LOCOMO 0
#endif
-/*
- * Board specific IRQs. Define them here.
- * Do not surround them with ifdefs.
- */
-#define IRQ_NEPONSET_SMC9196 (IRQ_BOARD_START + 0)
-#define IRQ_NEPONSET_USAR (IRQ_BOARD_START + 1)
-#define IRQ_NEPONSET_SA1111 (IRQ_BOARD_START + 2)
+#ifndef NR_IRQS
+#define NR_IRQS (IRQ_BOARD_START + NR_IRQS_LOCOMO)
+#endif
+#define SA1100_NR_IRQS (IRQ_BOARD_START + NR_IRQS_LOCOMO)
diff --git a/arch/arm/mach-sa1100/include/mach/mcp.h b/arch/arm/mach-sa1100/include/mach/mcp.h
index ed1a331508a7..4b2860ae3828 100644
--- a/arch/arm/mach-sa1100/include/mach/mcp.h
+++ b/arch/arm/mach-sa1100/include/mach/mcp.h
@@ -16,7 +16,7 @@ struct mcp_plat_data {
u32 mccr0;
u32 mccr1;
unsigned int sclk_rate;
- int gpio_base;
+ void *codec_pdata;
};
#endif
diff --git a/arch/arm/mach-sa1100/include/mach/nanoengine.h b/arch/arm/mach-sa1100/include/mach/nanoengine.h
index 14f8382d0665..5ebd469a31f2 100644
--- a/arch/arm/mach-sa1100/include/mach/nanoengine.h
+++ b/arch/arm/mach-sa1100/include/mach/nanoengine.h
@@ -16,12 +16,12 @@
#include <mach/irqs.h>
-#define GPIO_PC_READY0 GPIO_GPIO(11) /* ready for socket 0 (active high)*/
-#define GPIO_PC_READY1 GPIO_GPIO(12) /* ready for socket 1 (active high) */
-#define GPIO_PC_CD0 GPIO_GPIO(13) /* detect for socket 0 (active low) */
-#define GPIO_PC_CD1 GPIO_GPIO(14) /* detect for socket 1 (active low) */
-#define GPIO_PC_RESET0 GPIO_GPIO(15) /* reset socket 0 */
-#define GPIO_PC_RESET1 GPIO_GPIO(16) /* reset socket 1 */
+#define GPIO_PC_READY0 11 /* ready for socket 0 (active high)*/
+#define GPIO_PC_READY1 12 /* ready for socket 1 (active high) */
+#define GPIO_PC_CD0 13 /* detect for socket 0 (active low) */
+#define GPIO_PC_CD1 14 /* detect for socket 1 (active low) */
+#define GPIO_PC_RESET0 15 /* reset socket 0 */
+#define GPIO_PC_RESET1 16 /* reset socket 1 */
#define NANOENGINE_IRQ_GPIO_PCI IRQ_GPIO0
#define NANOENGINE_IRQ_GPIO_PC_READY0 IRQ_GPIO11
diff --git a/arch/arm/mach-sa1100/include/mach/neponset.h b/arch/arm/mach-sa1100/include/mach/neponset.h
index ffe2bc45eed0..5516a52a329d 100644
--- a/arch/arm/mach-sa1100/include/mach/neponset.h
+++ b/arch/arm/mach-sa1100/include/mach/neponset.h
@@ -15,54 +15,6 @@
/*
* Neponset definitions:
*/
-
-#define NEPONSET_CPLD_BASE (0x10000000)
-#define Nep_p2v( x ) ((x) - NEPONSET_CPLD_BASE + 0xf3000000)
-#define Nep_v2p( x ) ((x) - 0xf3000000 + NEPONSET_CPLD_BASE)
-
-#define _IRR 0x10000024 /* Interrupt Reason Register */
-#define _AUD_CTL 0x100000c0 /* Audio controls (RW) */
-#define _MDM_CTL_0 0x100000b0 /* Modem control 0 (RW) */
-#define _MDM_CTL_1 0x100000b4 /* Modem control 1 (RW) */
-#define _NCR_0 0x100000a0 /* Control Register (RW) */
-#define _KP_X_OUT 0x10000090 /* Keypad row write (RW) */
-#define _KP_Y_IN 0x10000080 /* Keypad column read (RO) */
-#define _SWPK 0x10000020 /* Switch pack (RO) */
-#define _WHOAMI 0x10000000 /* System ID Register (RO) */
-
-#define _LEDS 0x10000010 /* LEDs [31:0] (WO) */
-
-#define IRR (*((volatile u_char *) Nep_p2v(_IRR)))
-#define AUD_CTL (*((volatile u_char *) Nep_p2v(_AUD_CTL)))
-#define MDM_CTL_0 (*((volatile u_char *) Nep_p2v(_MDM_CTL_0)))
-#define MDM_CTL_1 (*((volatile u_char *) Nep_p2v(_MDM_CTL_1)))
-#define NCR_0 (*((volatile u_char *) Nep_p2v(_NCR_0)))
-#define KP_X_OUT (*((volatile u_char *) Nep_p2v(_KP_X_OUT)))
-#define KP_Y_IN (*((volatile u_char *) Nep_p2v(_KP_Y_IN)))
-#define SWPK (*((volatile u_char *) Nep_p2v(_SWPK)))
-#define WHOAMI (*((volatile u_char *) Nep_p2v(_WHOAMI)))
-
-#define LEDS (*((volatile Word *) Nep_p2v(_LEDS)))
-
-#define IRR_ETHERNET (1<<0)
-#define IRR_USAR (1<<1)
-#define IRR_SA1111 (1<<2)
-
-#define AUD_SEL_1341 (1<<0)
-#define AUD_MUTE_1341 (1<<1)
-
-#define MDM_CTL0_RTS1 (1 << 0)
-#define MDM_CTL0_DTR1 (1 << 1)
-#define MDM_CTL0_RTS2 (1 << 2)
-#define MDM_CTL0_DTR2 (1 << 3)
-
-#define MDM_CTL1_CTS1 (1 << 0)
-#define MDM_CTL1_DSR1 (1 << 1)
-#define MDM_CTL1_DCD1 (1 << 2)
-#define MDM_CTL1_CTS2 (1 << 3)
-#define MDM_CTL1_DSR2 (1 << 4)
-#define MDM_CTL1_DCD2 (1 << 5)
-
#define NCR_GP01_OFF (1<<0)
#define NCR_TP_PWR_EN (1<<1)
#define NCR_MS_PWR_EN (1<<2)
@@ -71,4 +23,8 @@
#define NCR_A0VPP (1<<5)
#define NCR_A1VPP (1<<6)
+void neponset_ncr_frob(unsigned int, unsigned int);
+#define neponset_ncr_set(v) neponset_ncr_frob(0, v)
+#define neponset_ncr_clear(v) neponset_ncr_frob(v, 0)
+
#endif
diff --git a/arch/arm/mach-sa1100/include/mach/shannon.h b/arch/arm/mach-sa1100/include/mach/shannon.h
index ec27d6e12140..fff39e02b496 100644
--- a/arch/arm/mach-sa1100/include/mach/shannon.h
+++ b/arch/arm/mach-sa1100/include/mach/shannon.h
@@ -21,16 +21,12 @@
#define SHANNON_GPIO_U3_RTS GPIO_GPIO (19) /* ?? */
#define SHANNON_GPIO_U3_CTS GPIO_GPIO (20) /* ?? */
#define SHANNON_GPIO_SENSE_12V GPIO_GPIO (21) /* Input, 12v flash unprotect detected */
-#define SHANNON_GPIO_DISP_EN GPIO_GPIO (22) /* out */
+#define SHANNON_GPIO_DISP_EN 22 /* out */
/* XXX GPIO 23 unaccounted for */
-#define SHANNON_GPIO_EJECT_0 GPIO_GPIO (24) /* in */
-#define SHANNON_IRQ_GPIO_EJECT_0 IRQ_GPIO24
-#define SHANNON_GPIO_EJECT_1 GPIO_GPIO (25) /* in */
-#define SHANNON_IRQ_GPIO_EJECT_1 IRQ_GPIO25
-#define SHANNON_GPIO_RDY_0 GPIO_GPIO (26) /* in */
-#define SHANNON_IRQ_GPIO_RDY_0 IRQ_GPIO26
-#define SHANNON_GPIO_RDY_1 GPIO_GPIO (27) /* in */
-#define SHANNON_IRQ_GPIO_RDY_1 IRQ_GPIO27
+#define SHANNON_GPIO_EJECT_0 24 /* in */
+#define SHANNON_GPIO_EJECT_1 25 /* in */
+#define SHANNON_GPIO_RDY_0 26 /* in */
+#define SHANNON_GPIO_RDY_1 27 /* in */
/* MCP UCB codec GPIO pins... */
diff --git a/arch/arm/mach-sa1100/include/mach/simpad.h b/arch/arm/mach-sa1100/include/mach/simpad.h
index db28118103eb..cdea671e8931 100644
--- a/arch/arm/mach-sa1100/include/mach/simpad.h
+++ b/arch/arm/mach-sa1100/include/mach/simpad.h
@@ -39,10 +39,8 @@
/*--- PCMCIA ---*/
-#define GPIO_CF_CD GPIO_GPIO24
-#define GPIO_CF_IRQ GPIO_GPIO1
-#define IRQ_GPIO_CF_IRQ IRQ_GPIO1
-#define IRQ_GPIO_CF_CD IRQ_GPIO24
+#define GPIO_CF_CD 24
+#define GPIO_CF_IRQ 1
/*--- SmartCard ---*/
#define GPIO_SMART_CARD GPIO_GPIO10
diff --git a/arch/arm/mach-sa1100/include/mach/system.h b/arch/arm/mach-sa1100/include/mach/system.h
deleted file mode 100644
index e17b208f76d4..000000000000
--- a/arch/arm/mach-sa1100/include/mach/system.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * arch/arm/mach-sa1100/include/mach/system.h
- *
- * Copyright (c) 1999 Nicolas Pitre <nico@fluxnic.net>
- */
-static inline void arch_idle(void)
-{
- cpu_do_idle();
-}
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.