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Diffstat (limited to 'arch/arm64/boot/dts/nvidia/tegra186.dtsi')
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra186.dtsi222
1 files changed, 193 insertions, 29 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 9ac4f0140700..6602fe421ee8 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -73,6 +73,48 @@
snps,rxpbl = <8>;
};
+ gpcdma: dma-controller@2600000 {
+ compatible = "nvidia,tegra186-gpcdma";
+ reg = <0x0 0x2600000 0x0 0x210000>;
+ resets = <&bpmp TEGRA186_RESET_GPCDMA>;
+ reset-names = "gpcdma";
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
+ dma-coherent;
+ status = "okay";
+ };
+
aconnect@2900000 {
compatible = "nvidia,tegra186-aconnect",
"nvidia,tegra210-aconnect";
@@ -467,6 +509,29 @@
status = "disabled";
};
+ tegra_ope1: processing-engine@2908000 {
+ compatible = "nvidia,tegra186-ope",
+ "nvidia,tegra210-ope";
+ reg = <0x2908000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ sound-name-prefix = "OPE1";
+ status = "disabled";
+
+ equalizer@2908100 {
+ compatible = "nvidia,tegra186-peq",
+ "nvidia,tegra210-peq";
+ reg = <0x2908100 0x100>;
+ };
+
+ dynamic-range-compressor@2908200 {
+ compatible = "nvidia,tegra186-mbdrc",
+ "nvidia,tegra210-mbdrc";
+ reg = <0x2908200 0x200>;
+ };
+ };
+
tegra_amixer: amixer@290bb00 {
compatible = "nvidia,tegra186-amixer",
"nvidia,tegra210-amixer";
@@ -474,12 +539,25 @@
sound-name-prefix = "MIXER1";
status = "disabled";
};
+
+ tegra_asrc: asrc@2910000 {
+ compatible = "nvidia,tegra186-asrc";
+ reg = <0x2910000 0x2000>;
+ sound-name-prefix = "ASRC1";
+ status = "disabled";
+ };
};
};
mc: memory-controller@2c00000 {
compatible = "nvidia,tegra186-mc";
- reg = <0x0 0x02c00000 0x0 0xb0000>;
+ reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
+ <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */
+ <0x0 0x02c20000 0x0 0x10000>, /* MC0 */
+ <0x0 0x02c30000 0x0 0x10000>, /* MC1 */
+ <0x0 0x02c40000 0x0 0x10000>, /* MC2 */
+ <0x0 0x02c50000 0x0 0x10000>; /* MC3 */
+ reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3";
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -508,6 +586,22 @@
};
};
+ timer@3010000 {
+ compatible = "nvidia,tegra186-timer";
+ reg = <0x0 0x03010000 0x0 0x000e0000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ status = "okay";
+ };
+
uarta: serial@3100000 {
compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
reg = <0x0 0x03100000 0x0 0x40>;
@@ -569,7 +663,7 @@
};
gen1_i2c: i2c@3160000 {
- compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
+ compatible = "nvidia,tegra186-i2c";
reg = <0x0 0x03160000 0x0 0x10000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -578,11 +672,15 @@
clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C1>;
reset-names = "i2c";
+ iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
+ dma-coherent;
+ dmas = <&gpcdma 21>, <&gpcdma 21>;
+ dma-names = "rx", "tx";
status = "disabled";
};
cam_i2c: i2c@3180000 {
- compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
+ compatible = "nvidia,tegra186-i2c";
reg = <0x0 0x03180000 0x0 0x10000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -591,12 +689,16 @@
clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C3>;
reset-names = "i2c";
+ iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
+ dma-coherent;
+ dmas = <&gpcdma 23>, <&gpcdma 23>;
+ dma-names = "rx", "tx";
status = "disabled";
};
/* shares pads with dpaux1 */
dp_aux_ch1_i2c: i2c@3190000 {
- compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
+ compatible = "nvidia,tegra186-i2c";
reg = <0x0 0x03190000 0x0 0x10000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -608,12 +710,16 @@
pinctrl-names = "default", "idle";
pinctrl-0 = <&state_dpaux1_i2c>;
pinctrl-1 = <&state_dpaux1_off>;
+ iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
+ dma-coherent;
+ dmas = <&gpcdma 26>, <&gpcdma 26>;
+ dma-names = "rx", "tx";
status = "disabled";
};
/* controlled by BPMP, should not be enabled */
pwr_i2c: i2c@31a0000 {
- compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
+ compatible = "nvidia,tegra186-i2c";
reg = <0x0 0x031a0000 0x0 0x10000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -627,7 +733,7 @@
/* shares pads with dpaux0 */
dp_aux_ch0_i2c: i2c@31b0000 {
- compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
+ compatible = "nvidia,tegra186-i2c";
reg = <0x0 0x031b0000 0x0 0x10000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -639,11 +745,15 @@
pinctrl-names = "default", "idle";
pinctrl-0 = <&state_dpaux_i2c>;
pinctrl-1 = <&state_dpaux_off>;
+ iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
+ dma-coherent;
+ dmas = <&gpcdma 30>, <&gpcdma 30>;
+ dma-names = "rx", "tx";
status = "disabled";
};
gen7_i2c: i2c@31c0000 {
- compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
+ compatible = "nvidia,tegra186-i2c";
reg = <0x0 0x031c0000 0x0 0x10000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -652,11 +762,15 @@
clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C7>;
reset-names = "i2c";
+ iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
+ dma-coherent;
+ dmas = <&gpcdma 27>, <&gpcdma 27>;
+ dma-names = "rx", "tx";
status = "disabled";
};
gen9_i2c: i2c@31e0000 {
- compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
+ compatible = "nvidia,tegra186-i2c";
reg = <0x0 0x031e0000 0x0 0x10000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -665,6 +779,10 @@
clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C9>;
reset-names = "i2c";
+ iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
+ dma-coherent;
+ dmas = <&gpcdma 31>, <&gpcdma 31>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -1073,7 +1191,7 @@
};
gen2_i2c: i2c@c240000 {
- compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
+ compatible = "nvidia,tegra186-i2c";
reg = <0x0 0x0c240000 0x0 0x10000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -1082,11 +1200,15 @@
clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C2>;
reset-names = "i2c";
+ iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
+ dma-coherent;
+ dmas = <&gpcdma 22>, <&gpcdma 22>;
+ dma-names = "rx", "tx";
status = "disabled";
};
gen8_i2c: i2c@c250000 {
- compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
+ compatible = "nvidia,tegra186-i2c";
reg = <0x0 0x0c250000 0x0 0x10000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -1095,6 +1217,10 @@
clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C8>;
reset-names = "i2c";
+ iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
+ dma-coherent;
+ dmas = <&gpcdma 0>, <&gpcdma 0>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -1199,7 +1325,7 @@
ccplex@e000000 {
compatible = "nvidia,tegra186-ccplex-cluster";
- reg = <0x0 0x0e000000 0x0 0x3fffff>;
+ reg = <0x0 0x0e000000 0x0 0x400000>;
nvidia,bpmp = <&bpmp>;
};
@@ -1390,6 +1516,16 @@
iommus = <&smmu TEGRA186_SID_HOST1X>;
+ /* Context isolation domains */
+ iommu-map = <0 &smmu TEGRA186_SID_HOST1X_CTX0 1>,
+ <1 &smmu TEGRA186_SID_HOST1X_CTX1 1>,
+ <2 &smmu TEGRA186_SID_HOST1X_CTX2 1>,
+ <3 &smmu TEGRA186_SID_HOST1X_CTX3 1>,
+ <4 &smmu TEGRA186_SID_HOST1X_CTX4 1>,
+ <5 &smmu TEGRA186_SID_HOST1X_CTX5 1>,
+ <6 &smmu TEGRA186_SID_HOST1X_CTX6 1>,
+ <7 &smmu TEGRA186_SID_HOST1X_CTX7 1>;
+
dpaux1: dpaux@15040000 {
compatible = "nvidia,tegra186-dpaux";
reg = <0x15040000 0x10000>;
@@ -1538,6 +1674,21 @@
iommus = <&smmu TEGRA186_SID_VIC>;
};
+ nvjpg@15380000 {
+ compatible = "nvidia,tegra186-nvjpg";
+ reg = <0x15380000 0x40000>;
+ clocks = <&bpmp TEGRA186_CLK_NVJPG>;
+ clock-names = "nvjpg";
+ resets = <&bpmp TEGRA186_RESET_NVJPG>;
+ reset-names = "nvjpg";
+
+ power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>;
+ interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>,
+ <&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA186_SID_NVJPG>;
+ };
+
dsib: dsi@15400000 {
compatible = "nvidia,tegra186-dsi";
reg = <0x15400000 0x10000>;
@@ -1569,6 +1720,21 @@
iommus = <&smmu TEGRA186_SID_NVDEC>;
};
+ nvenc@154c0000 {
+ compatible = "nvidia,tegra186-nvenc";
+ reg = <0x154c0000 0x40000>;
+ clocks = <&bpmp TEGRA186_CLK_NVENC>;
+ clock-names = "nvenc";
+ resets = <&bpmp TEGRA186_RESET_NVENC>;
+ reset-names = "nvenc";
+
+ power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>;
+ interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>,
+ <&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA186_SID_NVENC>;
+ };
+
sor0: sor@15540000 {
compatible = "nvidia,tegra186-sor";
reg = <0x15540000 0x10000>;
@@ -1719,6 +1885,7 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x30000000 0x50000>;
+ no-memory-wc;
cpu_bpmp_tx: sram@4e000 {
reg = <0x4e000 0x1000>;
@@ -1771,7 +1938,7 @@
iommus = <&smmu TEGRA186_SID_BPMP>;
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
TEGRA_HSP_DB_MASTER_BPMP>;
- shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
+ shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
@@ -1892,14 +2059,14 @@
};
pmu_denver {
- compatible = "nvidia,denver-pmu", "arm,armv8-pmuv3";
+ compatible = "nvidia,denver-pmu";
interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&denver_0 &denver_1>;
};
pmu_a57 {
- compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
+ compatible = "arm,cortex-a57-pmu";
interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
@@ -1930,12 +2097,12 @@
};
thermal-zones {
- a57 {
+ /* Cortex-A57 cluster */
+ cpu-thermal {
polling-delay = <0>;
polling-delay-passive = <1000>;
- thermal-sensors =
- <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>;
+ thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>;
trips {
critical {
@@ -1949,12 +2116,12 @@
};
};
- denver {
+ /* Denver cluster */
+ aux-thermal {
polling-delay = <0>;
polling-delay-passive = <1000>;
- thermal-sensors =
- <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>;
+ thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>;
trips {
critical {
@@ -1968,12 +2135,11 @@
};
};
- gpu {
+ gpu-thermal {
polling-delay = <0>;
polling-delay-passive = <1000>;
- thermal-sensors =
- <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>;
+ thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>;
trips {
critical {
@@ -1987,12 +2153,11 @@
};
};
- pll {
+ pll-thermal {
polling-delay = <0>;
polling-delay-passive = <1000>;
- thermal-sensors =
- <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>;
+ thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>;
trips {
critical {
@@ -2006,12 +2171,11 @@
};
};
- always_on {
+ ao-thermal {
polling-delay = <0>;
polling-delay-passive = <1000>;
- thermal-sensors =
- <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>;
+ thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>;
trips {
critical {
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