diff options
Diffstat (limited to 'arch/arm64/boot/dts/qcom/sc7180.dtsi')
-rw-r--r-- | arch/arm64/boot/dts/qcom/sc7180.dtsi | 135 |
1 files changed, 65 insertions, 70 deletions
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index faf8b807d0ff..58976a1ba06b 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -398,7 +398,7 @@ }; }; - cpu0_opp_table: cpu0_opp_table { + cpu0_opp_table: opp-table-cpu0 { compatible = "operating-points-v2"; opp-shared; @@ -453,7 +453,7 @@ }; }; - cpu6_opp_table: cpu6_opp_table { + cpu6_opp_table: opp-table-cpu6 { compatible = "operating-points-v2"; opp-shared; @@ -555,12 +555,6 @@ }; }; - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x1000>; - #hwlock-cells = <1>; - }; - smem { compatible = "qcom,smem"; memory-region = <&smem_mem>; @@ -693,7 +687,7 @@ }; }; - sdhc_1: sdhci@7c4000 { + sdhc_1: mmc@7c4000 { compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x7c4000 0 0x1000>, <0 0x07c5000 0 0x1000>; @@ -704,10 +698,10 @@ <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&rpmhcc RPMH_CXO_CLK>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>; interconnect-names = "sdhc-ddr","cpu-sdhc"; @@ -725,7 +719,7 @@ status = "disabled"; - sdhc1_opp_table: sdhc1-opp-table { + sdhc1_opp_table: opp-table { compatible = "operating-points-v2"; opp-100000000 { @@ -744,7 +738,7 @@ }; }; - qup_opp_table: qup-opp-table { + qup_opp_table: opp-table-qup { compatible = "operating-points-v2"; opp-75000000 { @@ -1421,13 +1415,6 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; - ipa_virt: interconnect@1e00000 { - compatible = "qcom,sc7180-ipa-virt"; - reg = <0 0x01e00000 0 0x1000>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - ipa: ipa@1e40000 { compatible = "qcom,sc7180-ipa"; @@ -1459,6 +1446,8 @@ "imem", "config"; + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&ipa_smp2p_out 0>, <&ipa_smp2p_out 1>; qcom,smem-state-names = "ipa-clock-enabled-valid", @@ -1467,13 +1456,19 @@ status = "disabled"; }; - tcsr_mutex_regs: syscon@1f40000 { - compatible = "syscon"; - reg = <0 0x01f40000 0 0x40000>; + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0 0x01f40000 0 0x20000>; + #hwlock-cells = <1>; + }; + + tcsr_regs_1: syscon@1f60000 { + compatible = "qcom,sc7180-tcsr", "syscon"; + reg = <0 0x01f60000 0 0x20000>; }; - tcsr_regs: syscon@1fc0000 { - compatible = "syscon"; + tcsr_regs_2: syscon@1fc0000 { + compatible = "qcom,sc7180-tcsr", "syscon"; reg = <0 0x01fc0000 0 0x40000>; }; @@ -1937,8 +1932,8 @@ <&pdc_reset PDC_MODEM_SYNC_RESET>; reset-names = "mss_restart", "pdc_reset"; - qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; - qcom,spare-regs = <&tcsr_regs 0xb3e4>; + qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; + qcom,spare-regs = <&tcsr_regs_2 0xb3e4>; status = "disabled"; @@ -1952,7 +1947,6 @@ gpu: gpu@5000000 { compatible = "qcom,adreno-618.0", "qcom,adreno"; - #stream-id-cells = <16>; reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>, <0 0x05061000 0 0x800>; reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; @@ -2054,7 +2048,7 @@ }; gmu: gmu@506a000 { - compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; + compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>, <0 0x0b490000 0 0x10000>; reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; @@ -2584,7 +2578,7 @@ }; }; - sdhc_2: sdhci@8804000 { + sdhc_2: mmc@8804000 { compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x08804000 0 0x1000>; @@ -2593,10 +2587,10 @@ <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, <&rpmhcc RPMH_CXO_CLK>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; @@ -2608,7 +2602,7 @@ status = "disabled"; - sdhc2_opp_table: sdhc2-opp-table { + sdhc2_opp_table: opp-table { compatible = "operating-points-v2"; opp-100000000 { @@ -2627,7 +2621,7 @@ }; }; - qspi_opp_table: qspi-opp-table { + qspi_opp_table: opp-table-qspi { compatible = "operating-points-v2"; opp-75000000 { @@ -2761,10 +2755,13 @@ clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>, <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_SLEEP_CLK>; - clock-names = "cfg_noc", "core", "iface", "mock_utmi", - "sleep"; + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi"; assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>; @@ -2785,7 +2782,7 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>; interconnect-names = "usb-ddr", "apps-usb"; - usb_1_dwc3: dwc3@a600000 { + usb_1_dwc3: usb@a600000 { compatible = "snps,dwc3"; reg = <0 0x0a600000 0 0xe000>; interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; @@ -2828,7 +2825,7 @@ compatible = "venus-encoder"; }; - venus_opp_table: venus-opp-table { + venus_opp_table: opp-table { compatible = "operating-points-v2"; opp-150000000 { @@ -2899,9 +2896,6 @@ <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "iface", "ahb", "core"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; - assigned-clock-rates = <300000000>; - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <1>; @@ -2917,7 +2911,7 @@ status = "disabled"; - mdp: mdp@ae01000 { + mdp: display-controller@ae01000 { compatible = "qcom,sc7180-dpu"; reg = <0 0x0ae01000 0 0x8f000>, <0 0x0aeb0000 0 0x2008>; @@ -2931,12 +2925,10 @@ <&dispcc DISP_CC_MDSS_VSYNC_CLK>; clock-names = "bus", "iface", "rot", "lut", "core", "vsync"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, <&dispcc DISP_CC_MDSS_ROT_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>; - assigned-clock-rates = <300000000>, - <19200000>, + assigned-clock-rates = <19200000>, <19200000>, <19200000>; operating-points-v2 = <&mdp_opp_table>; @@ -2966,7 +2958,7 @@ }; }; - mdp_opp_table: mdp-opp-table { + mdp_opp_table: opp-table { compatible = "operating-points-v2"; opp-200000000 { @@ -3045,7 +3037,7 @@ }; }; - dsi_opp_table: dsi-opp-table { + dsi_opp_table: opp-table { compatible = "operating-points-v2"; opp-187500000 { @@ -3088,7 +3080,11 @@ compatible = "qcom,sc7180-dp"; status = "disabled"; - reg = <0 0x0ae90000 0 0x1400>; + reg = <0 0xae90000 0 0x200>, + <0 0xae90200 0 0x200>, + <0 0xae90400 0 0xc00>, + <0 0xae91000 0 0x400>, + <0 0xae91400 0 0x400>; interrupt-parent = <&mdss>; interrupts = <12>; @@ -3100,7 +3096,6 @@ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", "stream_pixel"; - #clock-cells = <1>; assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; @@ -3218,7 +3213,7 @@ }; aoss_qmp: power-controller@c300000 { - compatible = "qcom,sc7180-aoss-qmp"; + compatible = "qcom,sc7180-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x400>; interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; mboxes = <&apss_shared 0>; @@ -3250,8 +3245,8 @@ cell-index = <0>; }; - imem@146aa000 { - compatible = "simple-mfd"; + sram@146aa000 { + compatible = "qcom,sc7180-imem", "syscon", "simple-mfd"; reg = <0 0x146aa000 0 0x2000>; #address-cells = <1>; @@ -3387,9 +3382,9 @@ }; timer@17c20000{ - #address-cells = <2>; - #size-cells = <2>; - ranges; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x20000000>; compatible = "arm,armv7-timer-mem"; reg = <0 0x17c20000 0 0x1000>; @@ -3397,49 +3392,49 @@ frame-number = <0>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17c21000 0 0x1000>, - <0 0x17c22000 0 0x1000>; + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; }; frame@17c23000 { frame-number = <1>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17c23000 0 0x1000>; + reg = <0x17c23000 0x1000>; status = "disabled"; }; frame@17c25000 { frame-number = <2>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17c25000 0 0x1000>; + reg = <0x17c25000 0x1000>; status = "disabled"; }; frame@17c27000 { frame-number = <3>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17c27000 0 0x1000>; + reg = <0x17c27000 0x1000>; status = "disabled"; }; frame@17c29000 { frame-number = <4>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17c29000 0 0x1000>; + reg = <0x17c29000 0x1000>; status = "disabled"; }; frame@17c2b000 { frame-number = <5>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17c2b000 0 0x1000>; + reg = <0x17c2b000 0x1000>; status = "disabled"; }; frame@17c2d000 { frame-number = <6>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17c2d000 0 0x1000>; + reg = <0x17c2d000 0x1000>; status = "disabled"; }; }; @@ -3521,7 +3516,7 @@ }; }; - apps_bcm_voter: bcm_voter { + apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; }; }; @@ -3587,7 +3582,7 @@ compatible = "qcom,sc7180-lpass-cpu"; reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>; - reg-names = "lpass-hdmiif", "lpass-lpaif"; + reg-names = "lpass-hdmiif", "lpass-lpaif"; iommus = <&apps_smmu 0x1020 0>, <&apps_smmu 0x1021 0>, |