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Diffstat (limited to 'arch/arm64/boot/dts/qcom/sdm845.dtsi')
-rw-r--r--arch/arm64/boot/dts/qcom/sdm845.dtsi16
1 files changed, 14 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 7395ef20b90e..0a86fe71a66d 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -1061,6 +1061,16 @@
gcc: clock-controller@100000 {
compatible = "qcom,gcc-sdm845";
reg = <0 0x00100000 0 0x1f0000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&sleep_clk>,
+ <&pcie0_lane>,
+ <&pcie1_lane>;
+ clock-names = "bi_tcxo",
+ "bi_tcxo_ao",
+ "sleep_clk",
+ "pcie_0_pipe_clk",
+ "pcie_1_pipe_clk";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
@@ -2062,6 +2072,7 @@
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
clock-names = "pipe0";
+ #clock-cells = <0>;
#phy-cells = <0>;
clock-output-names = "pcie_0_pipe_clk";
};
@@ -2170,6 +2181,7 @@
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
clock-names = "pipe0";
+ #clock-cells = <0>;
#phy-cells = <0>;
clock-output-names = "pcie_1_pipe_clk";
};
@@ -3673,7 +3685,6 @@
<0 0x088e8000 0 0x10>;
reg-names = "reg-base", "dp_com";
status = "disabled";
- #clock-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
@@ -3695,6 +3706,7 @@
<0 0x088e9600 0 0x128>,
<0 0x088e9800 0 0x200>,
<0 0x088e9a00 0 0x100>;
+ #clock-cells = <0>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
clock-names = "pipe0";
@@ -3706,7 +3718,6 @@
compatible = "qcom,sdm845-qmp-usb3-uni-phy";
reg = <0 0x088eb000 0 0x18c>;
status = "disabled";
- #clock-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
@@ -3726,6 +3737,7 @@
<0 0x088eb400 0 0x1fc>,
<0 0x088eb800 0 0x218>,
<0 0x088eb600 0 0x70>;
+ #clock-cells = <0>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
clock-names = "pipe0";