diff options
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r9a07g044.dtsi')
-rw-r--r-- | arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 457 |
1 files changed, 444 insertions, 13 deletions
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 485ef5f0fea1..2283d4fb8736 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -13,14 +13,14 @@ #address-cells = <2>; #size-cells = <2>; - audio_clk1: audio_clk1 { + audio_clk1: audio1-clk { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by boards that provide it */ clock-frequency = <0>; }; - audio_clk2: audio_clk2 { + audio_clk2: audio2-clk { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by boards that provide it */ @@ -28,23 +28,45 @@ }; /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { + can_clk: can-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ - extal_clk: extal { + extal_clk: extal-clk { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; }; - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + opp-suspend; + }; }; cpus { @@ -66,8 +88,11 @@ compatible = "arm,cortex-a55"; reg = <0>; device_type = "cpu"; + #cooling-cells = <2>; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A07G044_CLK_I>; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@100 { @@ -76,6 +101,8 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A07G044_CLK_I>; + operating-points-v2 = <&cluster0_opp>; }; L3_CA55: cache-controller-0 { @@ -85,6 +112,55 @@ }; }; + gpu_opp_table: opp-table-1 { + compatible = "operating-points-v2"; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <1100000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1100000>; + }; + + opp-250000000 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <1100000>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1100000>; + }; + + opp-125000000 { + opp-hz = /bits/ 64 <125000000>; + opp-microvolt = <1100000>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <1100000>; + }; + + opp-62500000 { + opp-hz = /bits/ 64 <62500000>; + opp-microvolt = <1100000>; + }; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + opp-microvolt = <1100000>; + }; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; @@ -176,6 +252,60 @@ status = "disabled"; }; + spi0: spi@1004ac00 { + compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz"; + reg = <0 0x1004ac00 0 0x400>; + interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A07G044_RSPI0_CLKB>; + resets = <&cpg R9A07G044_RSPI0_RST>; + dmas = <&dmac 0x2e95>, <&dmac 0x2e96>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@1004b000 { + compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz"; + reg = <0 0x1004b000 0 0x400>; + interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A07G044_RSPI1_CLKB>; + resets = <&cpg R9A07G044_RSPI1_RST>; + dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@1004b400 { + compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz"; + reg = <0 0x1004b400 0 0x400>; + interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A07G044_RSPI2_CLKB>; + resets = <&cpg R9A07G044_RSPI2_RST>; + dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + scif0: serial@1004b800 { compatible = "renesas,scif-r9a07g044"; reg = <0 0x1004b800 0 0x400>; @@ -194,6 +324,108 @@ status = "disabled"; }; + scif1: serial@1004bc00 { + compatible = "renesas,scif-r9a07g044"; + reg = <0 0x1004bc00 0 0x400>; + interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G044_SCIF1_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_SCIF1_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif2: serial@1004c000 { + compatible = "renesas,scif-r9a07g044"; + reg = <0 0x1004c000 0 0x400>; + interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G044_SCIF2_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_SCIF2_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif3: serial@1004c400 { + compatible = "renesas,scif-r9a07g044"; + reg = <0 0x1004c400 0 0x400>; + interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G044_SCIF3_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_SCIF3_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif4: serial@1004c800 { + compatible = "renesas,scif-r9a07g044"; + reg = <0 0x1004c800 0 0x400>; + interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G044_SCIF4_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_SCIF4_RST_SYSTEM_N>; + status = "disabled"; + }; + + sci0: serial@1004d000 { + compatible = "renesas,r9a07g044-sci", "renesas,sci"; + reg = <0 0x1004d000 0 0x400>; + interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_SCI0_RST>; + status = "disabled"; + }; + + sci1: serial@1004d400 { + compatible = "renesas,r9a07g044-sci", "renesas,sci"; + reg = <0 0x1004d400 0 0x400>; + interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD R9A07G044_SCI1_CLKP>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_SCI1_RST>; + status = "disabled"; + }; + canfd: can@10050000 { compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd"; reg = <0 0x10050000 0 0x8000>; @@ -358,6 +590,16 @@ }; }; + tsu: thermal@10059400 { + compatible = "renesas,r9a07g044-tsu", + "renesas,rzg2l-tsu"; + reg = <0 0x10059400 0 0x400>; + clocks = <&cpg CPG_MOD R9A07G044_TSU_PCLK>; + resets = <&cpg R9A07G044_TSU_PRESETN>; + power-domains = <&cpg>; + #thermal-sensor-cells = <1>; + }; + sbc: spi@10060000 { compatible = "renesas,r9a07g044-rpc-if", "renesas,rzg2l-rpc-if"; @@ -397,11 +639,15 @@ status = "disabled"; }; - pinctrl: pin-controller@11030000 { + pinctrl: pinctrl@11030000 { compatible = "renesas,r9a07g044-pinctrl"; reg = <0 0x11030000 0 0x10000>; gpio-controller; #gpio-cells = <2>; + #address-cells = <2>; + #interrupt-cells = <2>; + interrupt-parent = <&irqc>; + interrupt-controller; gpio-ranges = <&pinctrl 0 0 392>; clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>; power-domains = <&cpg>; @@ -410,6 +656,61 @@ <&cpg R9A07G044_GPIO_SPARE_RESETN>; }; + irqc: interrupt-controller@110a0000 { + compatible = "renesas,r9a07g044-irqc", + "renesas,rzg2l-irqc"; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0x110a0000 0 0x10000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>, + <&cpg CPG_MOD R9A07G044_IA55_PCLK>; + clock-names = "clk", "pclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_IA55_RESETN>; + }; + dmac: dma-controller@11820000 { compatible = "renesas,r9a07g044-dmac", "renesas,rz-dmac"; @@ -446,6 +747,27 @@ dma-channels = <16>; }; + gpu: gpu@11840000 { + compatible = "renesas,r9a07g044-mali", + "arm,mali-bifrost"; + reg = <0x0 0x11840000 0x0 0x10000>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "job", "mmu", "gpu", "event"; + clocks = <&cpg CPG_MOD R9A07G044_GPU_CLK>, + <&cpg CPG_MOD R9A07G044_GPU_AXI_CLK>, + <&cpg CPG_MOD R9A07G044_GPU_ACE_CLK>; + clock-names = "gpu", "bus", "bus_ace"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_GPU_RESETN>, + <&cpg R9A07G044_GPU_AXI_RESETN>, + <&cpg R9A07G044_GPU_ACE_RESETN>; + reset-names = "rst", "axi_rst", "ace_rst"; + operating-points-v2 = <&gpu_opp_table>; + }; + gic: interrupt-controller@11900000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; @@ -456,17 +778,17 @@ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; }; - sdhi0: mmc@11c00000 { + sdhi0: mmc@11c00000 { compatible = "renesas,sdhi-r9a07g044", "renesas,rcar-gen3-sdhi"; reg = <0x0 0x11c00000 0 0x10000>; interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK>, - <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>, <&cpg CPG_MOD R9A07G044_SDHI0_CLK_HS>, + <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>, <&cpg CPG_MOD R9A07G044_SDHI0_ACLK>; - clock-names = "imclk", "imclk2", "clk_hs", "aclk"; + clock-names = "core", "clkh", "cd", "aclk"; resets = <&cpg R9A07G044_SDHI0_IXRST>; power-domains = <&cpg>; status = "disabled"; @@ -479,10 +801,10 @@ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK>, - <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>, <&cpg CPG_MOD R9A07G044_SDHI1_CLK_HS>, + <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>, <&cpg CPG_MOD R9A07G044_SDHI1_ACLK>; - clock-names = "imclk", "imclk2", "clk_hs", "aclk"; + clock-names = "core", "clkh", "cd", "aclk"; resets = <&cpg R9A07G044_SDHI1_IXRST>; power-domains = <&cpg>; status = "disabled"; @@ -641,6 +963,115 @@ power-domains = <&cpg>; status = "disabled"; }; + + wdt0: watchdog@12800800 { + compatible = "renesas,r9a07g044-wdt", + "renesas,rzg2l-wdt"; + reg = <0 0x12800800 0 0x400>; + clocks = <&cpg CPG_MOD R9A07G044_WDT0_PCLK>, + <&cpg CPG_MOD R9A07G044_WDT0_CLK>; + clock-names = "pclk", "oscclk"; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "wdt", "perrout"; + resets = <&cpg R9A07G044_WDT0_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt1: watchdog@12800c00 { + compatible = "renesas,r9a07g044-wdt", + "renesas,rzg2l-wdt"; + reg = <0 0x12800C00 0 0x400>; + clocks = <&cpg CPG_MOD R9A07G044_WDT1_PCLK>, + <&cpg CPG_MOD R9A07G044_WDT1_CLK>; + clock-names = "pclk", "oscclk"; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "wdt", "perrout"; + resets = <&cpg R9A07G044_WDT1_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt2: watchdog@12800400 { + compatible = "renesas,r9a07g044-wdt", + "renesas,rzg2l-wdt"; + reg = <0 0x12800400 0 0x400>; + clocks = <&cpg CPG_MOD R9A07G044_WDT2_PCLK>, + <&cpg CPG_MOD R9A07G044_WDT2_CLK>; + clock-names = "pclk", "oscclk"; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "wdt", "perrout"; + resets = <&cpg R9A07G044_WDT2_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; + }; + + ostm0: timer@12801000 { + compatible = "renesas,r9a07g044-ostm", + "renesas,ostm"; + reg = <0x0 0x12801000 0x0 0x400>; + interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>; + clocks = <&cpg CPG_MOD R9A07G044_OSTM0_PCLK>; + resets = <&cpg R9A07G044_OSTM0_PRESETZ>; + power-domains = <&cpg>; + status = "disabled"; + }; + + ostm1: timer@12801400 { + compatible = "renesas,r9a07g044-ostm", + "renesas,ostm"; + reg = <0x0 0x12801400 0x0 0x400>; + interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>; + clocks = <&cpg CPG_MOD R9A07G044_OSTM1_PCLK>; + resets = <&cpg R9A07G044_OSTM1_PRESETZ>; + power-domains = <&cpg>; + status = "disabled"; + }; + + ostm2: timer@12801800 { + compatible = "renesas,r9a07g044-ostm", + "renesas,ostm"; + reg = <0x0 0x12801800 0x0 0x400>; + interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>; + clocks = <&cpg CPG_MOD R9A07G044_OSTM2_PCLK>; + resets = <&cpg R9A07G044_OSTM2_PRESETZ>; + power-domains = <&cpg>; + status = "disabled"; + }; + }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsu 0>; + sustainable-power = <717>; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cpu0 0 2>; + contribution = <1024>; + }; + }; + + trips { + sensor_crit: sensor-crit { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + + target: trip-point { + temperature = <100000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; }; timer { |