diff options
Diffstat (limited to 'arch/arm')
538 files changed, 10731 insertions, 5683 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7bab17ed2972..ade7e924bef5 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1,54 +1,60 @@ config ARM bool default y + select ARCH_BINFMT_ELF_RANDOMIZE_PIE + select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE select ARCH_HAVE_CUSTOM_GPIO_H - select HAVE_AOUT - select HAVE_DMA_API_DEBUG - select HAVE_IDE if PCI || ISA || PCMCIA - select HAVE_DMA_ATTRS - select HAVE_DMA_CONTIGUOUS if MMU - select HAVE_MEMBLOCK - select RTC_LIB - select SYS_SUPPORTS_APM_EMULATION + select ARCH_WANT_IPC_PARSE_VERSION + select CPU_PM if (SUSPEND || CPU_IDLE) + select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI) - select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE - select HAVE_OPROFILE if (HAVE_PERF_EVENTS) + select GENERIC_CLOCKEVENTS_BROADCAST if SMP + select GENERIC_IRQ_PROBE + select GENERIC_IRQ_SHOW + select GENERIC_KERNEL_THREAD + select GENERIC_KERNEL_EXECVE + select GENERIC_PCI_IOMAP + select GENERIC_SMP_IDLE_THREAD + select GENERIC_STRNCPY_FROM_USER + select GENERIC_STRNLEN_USER + select HARDIRQS_SW_RESEND + select HAVE_AOUT select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL select HAVE_ARCH_KGDB select HAVE_ARCH_TRACEHOOK - select HAVE_KPROBES if !XIP_KERNEL - select HAVE_KRETPROBES if (HAVE_KPROBES) - select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) - select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) + select HAVE_BPF_JIT + select HAVE_C_RECORDMCOUNT + select HAVE_DEBUG_KMEMLEAK + select HAVE_DMA_API_DEBUG + select HAVE_DMA_ATTRS + select HAVE_DMA_CONTIGUOUS if MMU select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) + select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) - select ARCH_BINFMT_ELF_RANDOMIZE_PIE + select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) select HAVE_GENERIC_DMA_COHERENT + select HAVE_GENERIC_HARDIRQS + select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) + select HAVE_IDE if PCI || ISA || PCMCIA + select HAVE_IRQ_WORK select HAVE_KERNEL_GZIP - select HAVE_KERNEL_LZO select HAVE_KERNEL_LZMA + select HAVE_KERNEL_LZO select HAVE_KERNEL_XZ - select HAVE_IRQ_WORK + select HAVE_KPROBES if !XIP_KERNEL + select HAVE_KRETPROBES if (HAVE_KPROBES) + select HAVE_MEMBLOCK + select HAVE_OPROFILE if (HAVE_PERF_EVENTS) select HAVE_PERF_EVENTS - select PERF_USE_VMALLOC select HAVE_REGS_AND_STACK_ACCESS_API - select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) - select HAVE_C_RECORDMCOUNT - select HAVE_GENERIC_HARDIRQS - select HARDIRQS_SW_RESEND - select GENERIC_IRQ_PROBE - select GENERIC_IRQ_SHOW - select ARCH_WANT_IPC_PARSE_VERSION - select HARDIRQS_SW_RESEND - select CPU_PM if (SUSPEND || CPU_IDLE) - select GENERIC_PCI_IOMAP - select HAVE_BPF_JIT - select GENERIC_SMP_IDLE_THREAD + select HAVE_SYSCALL_TRACEPOINTS + select HAVE_UID16 select KTIME_SCALAR - select GENERIC_CLOCKEVENTS_BROADCAST if SMP - select GENERIC_STRNCPY_FROM_USER - select GENERIC_STRNLEN_USER - select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN + select PERF_USE_VMALLOC + select RTC_LIB + select SYS_SUPPORTS_APM_EMULATION + select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND + select MODULES_USE_ELF_REL help The ARM series is a line of low-power-consumption RISC chip designs licensed by ARM Ltd and targeted at embedded applications and @@ -64,9 +70,9 @@ config NEED_SG_DMA_LENGTH bool config ARM_DMA_USE_IOMMU - select NEED_SG_DMA_LENGTH - select ARM_HAS_SG_CHAIN bool + select ARM_HAS_SG_CHAIN + select NEED_SG_DMA_LENGTH config HAVE_PWM bool @@ -258,69 +264,69 @@ choice config ARCH_MULTIPLATFORM bool "Allow multiple platforms to be selected" + depends on MMU select ARM_PATCH_PHYS_VIRT select AUTO_ZRELADDR select COMMON_CLK select MULTI_IRQ_HANDLER select SPARSE_IRQ select USE_OF - depends on MMU config ARCH_INTEGRATOR bool "ARM Ltd. Integrator family" - select ARM_AMBA select ARCH_HAS_CPUFREQ + select ARM_AMBA select COMMON_CLK select COMMON_CLK_VERSATILE + select GENERIC_CLOCKEVENTS select HAVE_TCM select ICST - select GENERIC_CLOCKEVENTS + select MULTI_IRQ_HANDLER + select NEED_MACH_MEMORY_H select PLAT_VERSATILE select PLAT_VERSATILE_FPGA_IRQ - select NEED_MACH_MEMORY_H select SPARSE_IRQ - select MULTI_IRQ_HANDLER help Support for ARM's Integrator platform. config ARCH_REALVIEW bool "ARM Ltd. RealView family" + select ARCH_WANT_OPTIONAL_GPIOLIB select ARM_AMBA + select ARM_TIMER_SP804 select COMMON_CLK select COMMON_CLK_VERSATILE - select ICST select GENERIC_CLOCKEVENTS - select ARCH_WANT_OPTIONAL_GPIOLIB - select PLAT_VERSATILE - select PLAT_VERSATILE_CLCD - select ARM_TIMER_SP804 select GPIO_PL061 if GPIOLIB + select ICST select NEED_MACH_MEMORY_H + select PLAT_VERSATILE + select PLAT_VERSATILE_CLCD help This enables support for ARM Ltd RealView boards. config ARCH_VERSATILE bool "ARM Ltd. Versatile family" + select ARCH_WANT_OPTIONAL_GPIOLIB select ARM_AMBA + select ARM_TIMER_SP804 select ARM_VIC select CLKDEV_LOOKUP + select GENERIC_CLOCKEVENTS select HAVE_MACH_CLKDEV select ICST - select GENERIC_CLOCKEVENTS - select ARCH_WANT_OPTIONAL_GPIOLIB select PLAT_VERSATILE - select PLAT_VERSATILE_CLOCK select PLAT_VERSATILE_CLCD + select PLAT_VERSATILE_CLOCK select PLAT_VERSATILE_FPGA_IRQ - select ARM_TIMER_SP804 help This enables support for ARM Ltd Versatile board. config ARCH_AT91 bool "Atmel AT91" select ARCH_REQUIRE_GPIOLIB - select HAVE_CLK select CLKDEV_LOOKUP + select HAVE_CLK select IRQ_DOMAIN select NEED_MACH_GPIO_H select NEED_MACH_IO_H if PCCARD @@ -345,43 +351,43 @@ config ARCH_BCM2835 This enables support for the Broadcom BCM2835 SoC. This SoC is use in the Raspberry Pi, and Roku 2 devices. -config ARCH_CLPS711X - bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" - select CPU_ARM720T - select ARCH_USES_GETTIMEOFFSET - select COMMON_CLK - select CLKDEV_LOOKUP - select NEED_MACH_MEMORY_H - help - Support for Cirrus Logic 711x/721x/731x based boards. - config ARCH_CNS3XXX bool "Cavium Networks CNS3XXX family" + select ARM_GIC select CPU_V6K select GENERIC_CLOCKEVENTS - select ARM_GIC select MIGHT_HAVE_CACHE_L2X0 select MIGHT_HAVE_PCI select PCI_DOMAINS if PCI help Support for Cavium Networks CNS3XXX platform. +config ARCH_CLPS711X + bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" + select ARCH_USES_GETTIMEOFFSET + select CLKDEV_LOOKUP + select COMMON_CLK + select CPU_ARM720T + select NEED_MACH_MEMORY_H + help + Support for Cirrus Logic 711x/721x/731x based boards. + config ARCH_GEMINI bool "Cortina Systems Gemini" - select CPU_FA526 select ARCH_REQUIRE_GPIOLIB select ARCH_USES_GETTIMEOFFSET + select CPU_FA526 help Support for the Cortina Systems Gemini family SoCs config ARCH_SIRF bool "CSR SiRF" - select NO_IOPORT select ARCH_REQUIRE_GPIOLIB - select GENERIC_CLOCKEVENTS select COMMON_CLK + select GENERIC_CLOCKEVENTS select GENERIC_IRQ_CHIP select MIGHT_HAVE_CACHE_L2X0 + select NO_IOPORT select PINCTRL select PINCTRL_SIRF select USE_OF @@ -390,12 +396,12 @@ config ARCH_SIRF config ARCH_EBSA110 bool "EBSA-110" + select ARCH_USES_GETTIMEOFFSET select CPU_SA110 select ISA - select NO_IOPORT - select ARCH_USES_GETTIMEOFFSET select NEED_MACH_IO_H select NEED_MACH_MEMORY_H + select NO_IOPORT help This is an evaluation board for the StrongARM processor available from Digital. It has limited hardware on-board, including an @@ -404,13 +410,13 @@ config ARCH_EBSA110 config ARCH_EP93XX bool "EP93xx-based" - select CPU_ARM920T + select ARCH_HAS_HOLES_MEMORYMODEL + select ARCH_REQUIRE_GPIOLIB + select ARCH_USES_GETTIMEOFFSET select ARM_AMBA select ARM_VIC select CLKDEV_LOOKUP - select ARCH_REQUIRE_GPIOLIB - select ARCH_HAS_HOLES_MEMORYMODEL - select ARCH_USES_GETTIMEOFFSET + select CPU_ARM920T select NEED_MACH_MEMORY_H help This enables support for the Cirrus EP93xx series of CPUs. @@ -429,10 +435,10 @@ config ARCH_FOOTBRIDGE config ARCH_MXC bool "Freescale MXC/iMX-based" - select GENERIC_CLOCKEVENTS select ARCH_REQUIRE_GPIOLIB select CLKDEV_LOOKUP select CLKSRC_MMIO + select GENERIC_CLOCKEVENTS select GENERIC_IRQ_CHIP select MULTI_IRQ_HANDLER select SPARSE_IRQ @@ -442,11 +448,11 @@ config ARCH_MXC config ARCH_MXS bool "Freescale MXS-based" - select GENERIC_CLOCKEVENTS select ARCH_REQUIRE_GPIOLIB select CLKDEV_LOOKUP select CLKSRC_MMIO select COMMON_CLK + select GENERIC_CLOCKEVENTS select HAVE_CLK_PREPARE select MULTI_IRQ_HANDLER select PINCTRL @@ -457,44 +463,43 @@ config ARCH_MXS config ARCH_NETX bool "Hilscher NetX based" + select ARM_VIC select CLKSRC_MMIO select CPU_ARM926T - select ARM_VIC select GENERIC_CLOCKEVENTS help This enables support for systems based on the Hilscher NetX Soc config ARCH_H720X bool "Hynix HMS720x-based" + select ARCH_USES_GETTIMEOFFSET select CPU_ARM720T select ISA_DMA_API - select ARCH_USES_GETTIMEOFFSET help This enables support for systems based on the Hynix HMS720x config ARCH_IOP13XX bool "IOP13xx-based" depends on MMU - select CPU_XSC3 - select PLAT_IOP - select PCI select ARCH_SUPPORTS_MSI - select VMSPLIT_1G + select CPU_XSC3 select NEED_MACH_MEMORY_H select NEED_RET_TO_USER + select PCI + select PLAT_IOP + select VMSPLIT_1G help Support for Intel's IOP13XX (XScale) family of processors. config ARCH_IOP32X bool "IOP32x-based" depends on MMU + select ARCH_REQUIRE_GPIOLIB select CPU_XSCALE select NEED_MACH_GPIO_H - select NEED_MACH_IO_H select NEED_RET_TO_USER - select PLAT_IOP select PCI - select ARCH_REQUIRE_GPIOLIB + select PLAT_IOP help Support for Intel's 80219 and IOP32X (XScale) family of processors. @@ -502,13 +507,12 @@ config ARCH_IOP32X config ARCH_IOP33X bool "IOP33x-based" depends on MMU + select ARCH_REQUIRE_GPIOLIB select CPU_XSCALE select NEED_MACH_GPIO_H - select NEED_MACH_IO_H select NEED_RET_TO_USER - select PLAT_IOP select PCI - select ARCH_REQUIRE_GPIOLIB + select PLAT_IOP help Support for Intel's IOP33X (XScale) family of processors. @@ -516,59 +520,45 @@ config ARCH_IXP4XX bool "IXP4xx-based" depends on MMU select ARCH_HAS_DMA_SET_COHERENT_MASK + select ARCH_REQUIRE_GPIOLIB select CLKSRC_MMIO select CPU_XSCALE - select ARCH_REQUIRE_GPIOLIB + select DMABOUNCE if PCI select GENERIC_CLOCKEVENTS select MIGHT_HAVE_PCI select NEED_MACH_IO_H - select DMABOUNCE if PCI help Support for Intel's IXP4XX (XScale) family of processors. config ARCH_DOVE bool "Marvell Dove" - select CPU_V7 - select PCI select ARCH_REQUIRE_GPIOLIB + select CPU_V7 select GENERIC_CLOCKEVENTS - select PLAT_ORION + select MIGHT_HAVE_PCI + select PLAT_ORION_LEGACY + select USB_ARCH_HAS_EHCI help Support for the Marvell Dove SoC 88AP510 config ARCH_KIRKWOOD bool "Marvell Kirkwood" - select CPU_FEROCEON - select PCI select ARCH_REQUIRE_GPIOLIB + select CPU_FEROCEON select GENERIC_CLOCKEVENTS - select PLAT_ORION + select PCI + select PLAT_ORION_LEGACY help Support for the following Marvell Kirkwood series SoCs: 88F6180, 88F6192 and 88F6281. -config ARCH_LPC32XX - bool "NXP LPC32XX" - select CLKSRC_MMIO - select CPU_ARM926T - select ARCH_REQUIRE_GPIOLIB - select HAVE_IDE - select ARM_AMBA - select USB_ARCH_HAS_OHCI - select CLKDEV_LOOKUP - select GENERIC_CLOCKEVENTS - select USE_OF - select HAVE_PWM - help - Support for the NXP LPC32XX family of processors - config ARCH_MV78XX0 bool "Marvell MV78xx0" - select CPU_FEROCEON - select PCI select ARCH_REQUIRE_GPIOLIB + select CPU_FEROCEON select GENERIC_CLOCKEVENTS - select PLAT_ORION + select PCI + select PLAT_ORION_LEGACY help Support for the following Marvell MV78xx0 series SoCs: MV781x0, MV782x0. @@ -576,11 +566,11 @@ config ARCH_MV78XX0 config ARCH_ORION5X bool "Marvell Orion" depends on MMU - select CPU_FEROCEON - select PCI select ARCH_REQUIRE_GPIOLIB + select CPU_FEROCEON select GENERIC_CLOCKEVENTS - select PLAT_ORION + select PCI + select PLAT_ORION_LEGACY help Support for the following Marvell Orion 5x series SoCs: Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), @@ -591,33 +581,33 @@ config ARCH_MMP depends on MMU select ARCH_REQUIRE_GPIOLIB select CLKDEV_LOOKUP + select GENERIC_ALLOCATOR select GENERIC_CLOCKEVENTS select GPIO_PXA select IRQ_DOMAIN + select NEED_MACH_GPIO_H select PLAT_PXA select SPARSE_IRQ - select GENERIC_ALLOCATOR - select NEED_MACH_GPIO_H help Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line. config ARCH_KS8695 bool "Micrel/Kendin KS8695" - select CPU_ARM922T select ARCH_REQUIRE_GPIOLIB - select NEED_MACH_MEMORY_H select CLKSRC_MMIO + select CPU_ARM922T select GENERIC_CLOCKEVENTS + select NEED_MACH_MEMORY_H help Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based System-on-Chip devices. config ARCH_W90X900 bool "Nuvoton W90X900 CPU" - select CPU_ARM926T select ARCH_REQUIRE_GPIOLIB select CLKDEV_LOOKUP select CLKSRC_MMIO + select CPU_ARM926T select GENERIC_CLOCKEVENTS help Support for Nuvoton (Winbond logic dept.) ARM9 processor, @@ -628,18 +618,33 @@ config ARCH_W90X900 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> +config ARCH_LPC32XX + bool "NXP LPC32XX" + select ARCH_REQUIRE_GPIOLIB + select ARM_AMBA + select CLKDEV_LOOKUP + select CLKSRC_MMIO + select CPU_ARM926T + select GENERIC_CLOCKEVENTS + select HAVE_IDE + select HAVE_PWM + select USB_ARCH_HAS_OHCI + select USE_OF + help + Support for the NXP LPC32XX family of processors + config ARCH_TEGRA bool "NVIDIA Tegra" + select ARCH_HAS_CPUFREQ select CLKDEV_LOOKUP select CLKSRC_MMIO + select COMMON_CLK select GENERIC_CLOCKEVENTS select GENERIC_GPIO select HAVE_CLK select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 - select ARCH_HAS_CPUFREQ select USE_OF - select COMMON_CLK help This enables support for NVIDIA Tegra based systems (Tegra APX, Tegra 6xx and Tegra 2 series). @@ -647,29 +652,29 @@ config ARCH_TEGRA config ARCH_PXA bool "PXA2xx/PXA3xx-based" depends on MMU - select ARCH_MTD_XIP select ARCH_HAS_CPUFREQ + select ARCH_MTD_XIP + select ARCH_REQUIRE_GPIOLIB + select ARM_CPU_SUSPEND if PM + select AUTO_ZRELADDR select CLKDEV_LOOKUP select CLKSRC_MMIO - select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS select GPIO_PXA - select PLAT_PXA - select SPARSE_IRQ - select AUTO_ZRELADDR - select MULTI_IRQ_HANDLER - select ARM_CPU_SUSPEND if PM select HAVE_IDE + select MULTI_IRQ_HANDLER select NEED_MACH_GPIO_H + select PLAT_PXA + select SPARSE_IRQ help Support for Intel/Marvell's PXA2xx/PXA3xx processor line. config ARCH_MSM bool "Qualcomm MSM" - select HAVE_CLK - select GENERIC_CLOCKEVENTS select ARCH_REQUIRE_GPIOLIB select CLKDEV_LOOKUP + select GENERIC_CLOCKEVENTS + select HAVE_CLK help Support for Qualcomm MSM/QSD based systems. This runs on the apps processor of the MSM/QSD and depends on a shared memory @@ -679,50 +684,50 @@ config ARCH_MSM config ARCH_SHMOBILE bool "Renesas SH-Mobile / R-Mobile" - select HAVE_CLK select CLKDEV_LOOKUP + select GENERIC_CLOCKEVENTS + select HAVE_CLK select HAVE_MACH_CLKDEV select HAVE_SMP - select GENERIC_CLOCKEVENTS select MIGHT_HAVE_CACHE_L2X0 - select NO_IOPORT - select SPARSE_IRQ select MULTI_IRQ_HANDLER - select PM_GENERIC_DOMAINS if PM select NEED_MACH_MEMORY_H + select NO_IOPORT + select PM_GENERIC_DOMAINS if PM + select SPARSE_IRQ help Support for Renesas's SH-Mobile and R-Mobile ARM platforms. config ARCH_RPC bool "RiscPC" select ARCH_ACORN - select FIQ select ARCH_MAY_HAVE_PC_FDC - select HAVE_PATA_PLATFORM - select ISA_DMA_API - select NO_IOPORT select ARCH_SPARSEMEM_ENABLE select ARCH_USES_GETTIMEOFFSET + select FIQ select HAVE_IDE + select HAVE_PATA_PLATFORM + select ISA_DMA_API select NEED_MACH_IO_H select NEED_MACH_MEMORY_H + select NO_IOPORT help On the Acorn Risc-PC, Linux can support the internal IDE disk and CD-ROM interface, serial and parallel port, and the floppy drive. config ARCH_SA1100 bool "SA1100-based" - select CLKSRC_MMIO - select CPU_SA1100 - select ISA - select ARCH_SPARSEMEM_ENABLE - select ARCH_MTD_XIP select ARCH_HAS_CPUFREQ + select ARCH_MTD_XIP + select ARCH_REQUIRE_GPIOLIB + select ARCH_SPARSEMEM_ENABLE + select CLKDEV_LOOKUP + select CLKSRC_MMIO select CPU_FREQ + select CPU_SA1100 select GENERIC_CLOCKEVENTS - select CLKDEV_LOOKUP - select ARCH_REQUIRE_GPIOLIB select HAVE_IDE + select ISA select NEED_MACH_GPIO_H select NEED_MACH_MEMORY_H select SPARSE_IRQ @@ -731,14 +736,14 @@ config ARCH_SA1100 config ARCH_S3C24XX bool "Samsung S3C24XX SoCs" - select GENERIC_GPIO select ARCH_HAS_CPUFREQ - select HAVE_CLK - select CLKDEV_LOOKUP select ARCH_USES_GETTIMEOFFSET + select CLKDEV_LOOKUP + select GENERIC_GPIO + select HAVE_CLK select HAVE_S3C2410_I2C if I2C - select HAVE_S3C_RTC if RTC_CLASS select HAVE_S3C2410_WATCHDOG if WATCHDOG + select HAVE_S3C_RTC if RTC_CLASS select NEED_MACH_GPIO_H select NEED_MACH_IO_H help @@ -749,38 +754,38 @@ config ARCH_S3C24XX config ARCH_S3C64XX bool "Samsung S3C64XX" - select PLAT_SAMSUNG - select CPU_V6 + select ARCH_HAS_CPUFREQ + select ARCH_REQUIRE_GPIOLIB + select ARCH_USES_GETTIMEOFFSET select ARM_VIC + select CLKDEV_LOOKUP + select CPU_V6 select HAVE_CLK + select HAVE_S3C2410_I2C if I2C + select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_TCM - select CLKDEV_LOOKUP + select NEED_MACH_GPIO_H select NO_IOPORT - select ARCH_USES_GETTIMEOFFSET - select ARCH_HAS_CPUFREQ - select ARCH_REQUIRE_GPIOLIB + select PLAT_SAMSUNG + select S3C_DEV_NAND + select S3C_GPIO_TRACK select SAMSUNG_CLKSRC + select SAMSUNG_GPIOLIB_4BIT select SAMSUNG_IRQ_VIC_TIMER - select S3C_GPIO_TRACK - select S3C_DEV_NAND select USB_ARCH_HAS_OHCI - select SAMSUNG_GPIOLIB_4BIT - select HAVE_S3C2410_I2C if I2C - select HAVE_S3C2410_WATCHDOG if WATCHDOG - select NEED_MACH_GPIO_H help Samsung S3C64XX series based systems config ARCH_S5P64X0 bool "Samsung S5P6440 S5P6450" - select CPU_V6 - select GENERIC_GPIO - select HAVE_CLK select CLKDEV_LOOKUP select CLKSRC_MMIO - select HAVE_S3C2410_WATCHDOG if WATCHDOG + select CPU_V6 select GENERIC_CLOCKEVENTS + select GENERIC_GPIO + select HAVE_CLK select HAVE_S3C2410_I2C if I2C + select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_S3C_RTC if RTC_CLASS select NEED_MACH_GPIO_H help @@ -789,50 +794,50 @@ config ARCH_S5P64X0 config ARCH_S5PC100 bool "Samsung S5PC100" - select GENERIC_GPIO - select HAVE_CLK + select ARCH_USES_GETTIMEOFFSET select CLKDEV_LOOKUP select CPU_V7 - select ARCH_USES_GETTIMEOFFSET + select GENERIC_GPIO + select HAVE_CLK select HAVE_S3C2410_I2C if I2C - select HAVE_S3C_RTC if RTC_CLASS select HAVE_S3C2410_WATCHDOG if WATCHDOG + select HAVE_S3C_RTC if RTC_CLASS select NEED_MACH_GPIO_H help Samsung S5PC100 series based systems config ARCH_S5PV210 bool "Samsung S5PV210/S5PC110" - select CPU_V7 - select ARCH_SPARSEMEM_ENABLE + select ARCH_HAS_CPUFREQ select ARCH_HAS_HOLES_MEMORYMODEL - select GENERIC_GPIO - select HAVE_CLK + select ARCH_SPARSEMEM_ENABLE select CLKDEV_LOOKUP select CLKSRC_MMIO - select ARCH_HAS_CPUFREQ + select CPU_V7 select GENERIC_CLOCKEVENTS + select GENERIC_GPIO + select HAVE_CLK select HAVE_S3C2410_I2C if I2C - select HAVE_S3C_RTC if RTC_CLASS select HAVE_S3C2410_WATCHDOG if WATCHDOG + select HAVE_S3C_RTC if RTC_CLASS select NEED_MACH_GPIO_H select NEED_MACH_MEMORY_H help Samsung S5PV210/S5PC110 series based systems config ARCH_EXYNOS - bool "SAMSUNG EXYNOS" - select CPU_V7 - select ARCH_SPARSEMEM_ENABLE + bool "Samsung EXYNOS" + select ARCH_HAS_CPUFREQ select ARCH_HAS_HOLES_MEMORYMODEL - select GENERIC_GPIO - select HAVE_CLK + select ARCH_SPARSEMEM_ENABLE select CLKDEV_LOOKUP - select ARCH_HAS_CPUFREQ + select CPU_V7 select GENERIC_CLOCKEVENTS - select HAVE_S3C_RTC if RTC_CLASS + select GENERIC_GPIO + select HAVE_CLK select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG + select HAVE_S3C_RTC if RTC_CLASS select NEED_MACH_GPIO_H select NEED_MACH_MEMORY_H help @@ -840,13 +845,13 @@ config ARCH_EXYNOS config ARCH_SHARK bool "Shark" + select ARCH_USES_GETTIMEOFFSET select CPU_SA110 select ISA select ISA_DMA - select ZONE_DMA - select PCI - select ARCH_USES_GETTIMEOFFSET select NEED_MACH_MEMORY_H + select PCI + select ZONE_DMA help Support for the StrongARM based Digital DNARD machine, also known as "Shark" (<http://www.shark-linux.de/shark.html>). @@ -854,17 +859,17 @@ config ARCH_SHARK config ARCH_U300 bool "ST-Ericsson U300 Series" depends on MMU - select CLKSRC_MMIO - select CPU_ARM926T - select HAVE_TCM + select ARCH_REQUIRE_GPIOLIB select ARM_AMBA select ARM_PATCH_PHYS_VIRT select ARM_VIC - select GENERIC_CLOCKEVENTS select CLKDEV_LOOKUP + select CLKSRC_MMIO select COMMON_CLK + select CPU_ARM926T + select GENERIC_CLOCKEVENTS select GENERIC_GPIO - select ARCH_REQUIRE_GPIOLIB + select HAVE_TCM select SPARSE_IRQ help Support for ST-Ericsson U300 series mobile platforms. @@ -872,12 +877,12 @@ config ARCH_U300 config ARCH_U8500 bool "ST-Ericsson U8500 Series" depends on MMU - select CPU_V7 + select ARCH_HAS_CPUFREQ + select ARCH_REQUIRE_GPIOLIB select ARM_AMBA - select GENERIC_CLOCKEVENTS select CLKDEV_LOOKUP - select ARCH_REQUIRE_GPIOLIB - select ARCH_HAS_CPUFREQ + select CPU_V7 + select GENERIC_CLOCKEVENTS select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 help @@ -885,78 +890,78 @@ config ARCH_U8500 config ARCH_NOMADIK bool "STMicroelectronics Nomadik" + select ARCH_REQUIRE_GPIOLIB select ARM_AMBA select ARM_VIC - select CPU_ARM926T select COMMON_CLK + select CPU_ARM926T select GENERIC_CLOCKEVENTS + select MIGHT_HAVE_CACHE_L2X0 select PINCTRL select PINCTRL_STN8815 - select MIGHT_HAVE_CACHE_L2X0 - select ARCH_REQUIRE_GPIOLIB help Support for the Nomadik platform by ST-Ericsson +config PLAT_SPEAR + bool "ST SPEAr" + select ARCH_REQUIRE_GPIOLIB + select ARM_AMBA + select CLKDEV_LOOKUP + select CLKSRC_MMIO + select COMMON_CLK + select GENERIC_CLOCKEVENTS + select HAVE_CLK + help + Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx). + config ARCH_DAVINCI bool "TI DaVinci" - select GENERIC_CLOCKEVENTS + select ARCH_HAS_HOLES_MEMORYMODEL select ARCH_REQUIRE_GPIOLIB - select ZONE_DMA - select HAVE_IDE select CLKDEV_LOOKUP select GENERIC_ALLOCATOR + select GENERIC_CLOCKEVENTS select GENERIC_IRQ_CHIP - select ARCH_HAS_HOLES_MEMORYMODEL + select HAVE_IDE select NEED_MACH_GPIO_H + select ZONE_DMA help Support for TI's DaVinci platform. config ARCH_OMAP bool "TI OMAP" depends on MMU - select HAVE_CLK - select ARCH_REQUIRE_GPIOLIB select ARCH_HAS_CPUFREQ - select CLKSRC_MMIO - select GENERIC_CLOCKEVENTS select ARCH_HAS_HOLES_MEMORYMODEL - select NEED_MACH_GPIO_H - help - Support for TI's OMAP platform (OMAP1/2/3/4). - -config PLAT_SPEAR - bool "ST SPEAr" - select ARM_AMBA select ARCH_REQUIRE_GPIOLIB - select CLKDEV_LOOKUP - select COMMON_CLK select CLKSRC_MMIO select GENERIC_CLOCKEVENTS select HAVE_CLK + select NEED_MACH_GPIO_H help - Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx). + Support for TI's OMAP platform (OMAP1/2/3/4). config ARCH_VT8500 bool "VIA/WonderMedia 85xx" - select CPU_ARM926T - select GENERIC_GPIO select ARCH_HAS_CPUFREQ - select GENERIC_CLOCKEVENTS select ARCH_REQUIRE_GPIOLIB - select USE_OF + select CLKDEV_LOOKUP select COMMON_CLK + select CPU_ARM926T + select GENERIC_CLOCKEVENTS + select GENERIC_GPIO select HAVE_CLK - select CLKDEV_LOOKUP + select USE_OF help Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip. config ARCH_ZYNQ bool "Xilinx Zynq ARM Cortex A9 Platform" + select ARM_AMBA + select ARM_GIC + select CLKDEV_LOOKUP select CPU_V7 select GENERIC_CLOCKEVENTS - select CLKDEV_LOOKUP - select ARM_GIC - select ARM_AMBA select ICST select MIGHT_HAVE_CACHE_L2X0 select USE_OF @@ -971,33 +976,33 @@ comment "CPU Core family selection" config ARCH_MULTI_V4 bool "ARMv4 based platforms (FA526, StrongARM)" - select ARCH_MULTI_V4_V5 depends on !ARCH_MULTI_V6_V7 + select ARCH_MULTI_V4_V5 config ARCH_MULTI_V4T bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" - select ARCH_MULTI_V4_V5 depends on !ARCH_MULTI_V6_V7 + select ARCH_MULTI_V4_V5 config ARCH_MULTI_V5 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" - select ARCH_MULTI_V4_V5 depends on !ARCH_MULTI_V6_V7 + select ARCH_MULTI_V4_V5 config ARCH_MULTI_V4_V5 bool config ARCH_MULTI_V6 bool "ARMv6 based platforms (ARM11, Scorpion, ...)" - select CPU_V6 select ARCH_MULTI_V6_V7 + select CPU_V6 config ARCH_MULTI_V7 bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)" - select CPU_V7 - select ARCH_VEXPRESS default y select ARCH_MULTI_V6_V7 + select ARCH_VEXPRESS + select CPU_V7 config ARCH_MULTI_V6_V7 bool @@ -1134,9 +1139,13 @@ config PLAT_IOP config PLAT_ORION bool select CLKSRC_MMIO + select COMMON_CLK select GENERIC_IRQ_CHIP select IRQ_DOMAIN - select COMMON_CLK + +config PLAT_ORION_LEGACY + bool + select PLAT_ORION config PLAT_PXA bool @@ -1397,6 +1406,16 @@ config PL310_ERRATA_769419 on systems with an outer cache, the store buffer is drained explicitly. +config ARM_ERRATA_775420 + bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" + depends on CPU_V7 + help + This option enables the workaround for the 775420 Cortex-A9 (r2p2, + r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance + operation aborts with MMU exception, it might cause the processor + to deadlock. This workaround puts DSB before executing ISB if + an abort may occur on cache maintenance. + endmenu source "arch/arm/common/Kconfig" @@ -1480,8 +1499,8 @@ config SMP depends on GENERIC_CLOCKEVENTS depends on HAVE_SMP depends on MMU - select USE_GENERIC_SMP_HELPERS select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP + select USE_GENERIC_SMP_HELPERS help This enables support for systems with more than one CPU. If you have a system with only one CPU, like most personal computers, say N. If @@ -1584,8 +1603,8 @@ config NR_CPUS default "4" config HOTPLUG_CPU - bool "Support for hot-pluggable CPUs (EXPERIMENTAL)" - depends on SMP && HOTPLUG && EXPERIMENTAL + bool "Support for hot-pluggable CPUs" + depends on SMP && HOTPLUG help Say Y here to experiment with turning CPUs off and on. CPUs can be controlled through /sys/devices/system/cpu. @@ -1626,8 +1645,8 @@ config HZ default 100 config THUMB2_KERNEL - bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)" - depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL + bool "Compile the kernel in Thumb-2 mode" + depends on CPU_V7 && !CPU_V6 && !CPU_V6K select AEABI select ARM_ASM_UNIFIED select ARM_UNWIND @@ -1753,6 +1772,7 @@ source "mm/Kconfig" config FORCE_MAX_ZONEORDER int "Maximum zone order" if ARCH_SHMOBILE range 11 64 if ARCH_SHMOBILE + default "12" if SOC_AM33XX default "9" if SA1111 default "11" help @@ -1781,8 +1801,8 @@ config ALIGNMENT_TRAP configuration it is safe to say N, otherwise say Y. config UACCESS_WITH_MEMCPY - bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)" - depends on MMU && EXPERIMENTAL + bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" + depends on MMU default y if CPU_FEROCEON help Implement faster copy_to_user and clear_user methods for CPU @@ -1823,11 +1843,16 @@ config CC_STACKPROTECTOR neutralized via a kernel panic. This feature requires gcc version 4.2 or above. -config DEPRECATED_PARAM_STRUCT - bool "Provide old way to pass kernel parameters" +config XEN_DOM0 + def_bool y + depends on XEN + +config XEN + bool "Xen guest support on ARM (EXPERIMENTAL)" + depends on EXPERIMENTAL && ARM && OF + depends on CPU_V7 && !CPU_V6 help - This was deprecated in 2001 and announced to live on for 5 years. - Some old boot loaders still use this way. + Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. endmenu @@ -1835,12 +1860,29 @@ menu "Boot options" config USE_OF bool "Flattened Device Tree support" + select IRQ_DOMAIN select OF select OF_EARLY_FLATTREE - select IRQ_DOMAIN help Include support for flattened device tree machine descriptions. +config ATAGS + bool "Support for the traditional ATAGS boot data passing" if USE_OF + default y + help + This is the traditional way of passing data to the kernel at boot + time. If you are solely relying on the flattened device tree (or + the ARM_ATAG_DTB_COMPAT option) then you may unselect this option + to remove ATAGS support from your kernel binary. If unsure, + leave this to y. + +config DEPRECATED_PARAM_STRUCT + bool "Provide old way to pass kernel parameters" + depends on ATAGS + help + This was deprecated in 2001 and announced to live on for 5 years. + Some old boot loaders still use this way. + # Compressed boot loader in ROM. Yes, we really want to ask about # TEXT and BSS so we preserve their values in the config files. config ZBOOT_ROM_TEXT @@ -1967,6 +2009,7 @@ config CMDLINE choice prompt "Kernel command line type" if CMDLINE != "" default CMDLINE_FROM_BOOTLOADER + depends on ATAGS config CMDLINE_FROM_BOOTLOADER bool "Use bootloader kernel arguments if available" @@ -2036,7 +2079,7 @@ config KEXEC config ATAGS_PROC bool "Export atags in procfs" - depends on KEXEC + depends on ATAGS && KEXEC default y help Should the atags used to boot the kernel be exported in an "atags" @@ -2101,8 +2144,8 @@ config CPU_FREQ_PXA bool depends on CPU_FREQ && ARCH_PXA && PXA25x default y - select CPU_FREQ_TABLE select CPU_FREQ_DEFAULT_GOV_USERSPACE + select CPU_FREQ_TABLE config CPU_FREQ_S3C bool diff --git a/arch/arm/Makefile b/arch/arm/Makefile index b86e57ef146b..5f914fca911b 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -21,8 +21,6 @@ endif OBJCOPYFLAGS :=-O binary -R .comment -S GZFLAGS :=-9 #KBUILD_CFLAGS +=-pipe -# Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb: -KBUILD_CFLAGS +=$(call cc-option,-marm,) # Never generate .eh_frame KBUILD_CFLAGS += $(call cc-option,-fno-dwarf2-cfi-asm) @@ -105,17 +103,20 @@ endif ifeq ($(CONFIG_THUMB2_KERNEL),y) AFLAGS_AUTOIT :=$(call as-option,-Wa$(comma)-mimplicit-it=always,-Wa$(comma)-mauto-it) AFLAGS_NOWARN :=$(call as-option,-Wa$(comma)-mno-warn-deprecated,-Wa$(comma)-W) -CFLAGS_THUMB2 :=-mthumb $(AFLAGS_AUTOIT) $(AFLAGS_NOWARN) -AFLAGS_THUMB2 :=$(CFLAGS_THUMB2) -Wa$(comma)-mthumb +CFLAGS_ISA :=-mthumb $(AFLAGS_AUTOIT) $(AFLAGS_NOWARN) +AFLAGS_ISA :=$(CFLAGS_ISA) -Wa$(comma)-mthumb # Work around buggy relocation from gas if requested: ifeq ($(CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11),y) CFLAGS_MODULE +=-fno-optimize-sibling-calls endif +else +CFLAGS_ISA :=$(call cc-option,-marm,) +AFLAGS_ISA :=$(CFLAGS_ISA) endif # Need -Uarm for gcc < 3.x -KBUILD_CFLAGS +=$(CFLAGS_ABI) $(CFLAGS_THUMB2) $(arch-y) $(tune-y) $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -msoft-float -Uarm -KBUILD_AFLAGS +=$(CFLAGS_ABI) $(AFLAGS_THUMB2) $(arch-y) $(tune-y) -include asm/unified.h -msoft-float +KBUILD_CFLAGS +=$(CFLAGS_ABI) $(CFLAGS_ISA) $(arch-y) $(tune-y) $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -msoft-float -Uarm +KBUILD_AFLAGS +=$(CFLAGS_ABI) $(AFLAGS_ISA) $(arch-y) $(tune-y) -include asm/unified.h -msoft-float CHECKFLAGS += -D__arm__ @@ -250,6 +251,7 @@ endif core-$(CONFIG_FPE_NWFPE) += arch/arm/nwfpe/ core-$(CONFIG_FPE_FASTFPE) += $(FASTFPE_OBJ) core-$(CONFIG_VFP) += arch/arm/vfp/ +core-$(CONFIG_XEN) += arch/arm/xen/ # If we have a machine-specific directory, then include it in the build. core-y += arch/arm/kernel/ arch/arm/mm/ arch/arm/common/ @@ -268,7 +270,12 @@ else KBUILD_IMAGE := zImage endif -all: $(KBUILD_IMAGE) +# Build the DT binary blobs if we have OF configured +ifeq ($(CONFIG_USE_OF),y) +KBUILD_DTBS := dtbs +endif + +all: $(KBUILD_IMAGE) $(KBUILD_DTBS) boot := arch/arm/boot @@ -306,7 +313,7 @@ define archhelp echo ' uImage - U-Boot wrapped zImage' echo ' bootpImage - Combined zImage and initial RAM disk' echo ' (supply initrd image via make variable INITRD=<path>)' - echo ' dtbs - Build device tree blobs for enabled boards' + echo '* dtbs - Build device tree blobs for enabled boards' echo ' install - Install uncompressed kernel' echo ' zinstall - Install compressed kernel' echo ' uinstall - Install U-Boot wrapped compressed kernel' diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile index 3fdab016aa5c..f2aa09eb658e 100644 --- a/arch/arm/boot/Makefile +++ b/arch/arm/boot/Makefile @@ -33,7 +33,7 @@ ifeq ($(CONFIG_XIP_KERNEL),y) $(obj)/xipImage: vmlinux FORCE $(call if_changed,objcopy) - @echo ' Kernel: $@ is ready (physical address: $(CONFIG_XIP_PHYS_ADDR))' + $(kecho) ' Kernel: $@ is ready (physical address: $(CONFIG_XIP_PHYS_ADDR))' $(obj)/Image $(obj)/zImage: FORCE @echo 'Kernel configured for XIP (CONFIG_XIP_KERNEL=y)' @@ -48,14 +48,14 @@ $(obj)/xipImage: FORCE $(obj)/Image: vmlinux FORCE $(call if_changed,objcopy) - @echo ' Kernel: $@ is ready' + $(kecho) ' Kernel: $@ is ready' $(obj)/compressed/vmlinux: $(obj)/Image FORCE $(Q)$(MAKE) $(build)=$(obj)/compressed $@ $(obj)/zImage: $(obj)/compressed/vmlinux FORCE $(call if_changed,objcopy) - @echo ' Kernel: $@ is ready' + $(kecho) ' Kernel: $@ is ready' endif @@ -90,7 +90,7 @@ fi $(obj)/uImage: $(obj)/zImage FORCE @$(check_for_multiple_loadaddr) $(call if_changed,uimage) - @echo ' Image $@ is ready' + $(kecho) ' Image $@ is ready' $(obj)/bootp/bootp: $(obj)/zImage initrd FORCE $(Q)$(MAKE) $(build)=$(obj)/bootp $@ @@ -98,7 +98,7 @@ $(obj)/bootp/bootp: $(obj)/zImage initrd FORCE $(obj)/bootpImage: $(obj)/bootp/bootp FORCE $(call if_changed,objcopy) - @echo ' Kernel: $@ is ready' + $(kecho) ' Kernel: $@ is ready' PHONY += initrd FORCE initrd: diff --git a/arch/arm/boot/compressed/.gitignore b/arch/arm/boot/compressed/.gitignore index d0d441c429ae..f79a08efe000 100644 --- a/arch/arm/boot/compressed/.gitignore +++ b/arch/arm/boot/compressed/.gitignore @@ -1,6 +1,7 @@ ashldi3.S font.c lib1funcs.S +hyp-stub.S piggy.gzip piggy.lzo piggy.lzma diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index bb267562e7ed..a517153a13ea 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -30,6 +30,10 @@ FONTC = $(srctree)/drivers/video/console/font_acorn_8x8.c OBJS += string.o CFLAGS_string.o := -Os +ifeq ($(CONFIG_ARM_VIRT_EXT),y) +OBJS += hyp-stub.o +endif + # # Architecture dependencies # @@ -126,7 +130,7 @@ KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS)) endif ccflags-y := -fpic -fno-builtin -I$(obj) -asflags-y := -Wa,-march=all +asflags-y := -Wa,-march=all -DZIMAGE # Supply kernel BSS size to the decompressor via a linker symbol. KBSS_SZ = $(shell $(CROSS_COMPILE)size $(obj)/../../../../vmlinux | \ @@ -198,3 +202,6 @@ $(obj)/font.c: $(FONTC) $(obj)/vmlinux.lds: $(obj)/vmlinux.lds.in arch/arm/boot/Makefile $(KCONFIG_CONFIG) @sed "$(SEDFLAGS)" < $< > $@ + +$(obj)/hyp-stub.S: $(srctree)/arch/$(SRCARCH)/kernel/hyp-stub.S + $(call cmd,shipped) diff --git a/arch/arm/boot/compressed/decompress.c b/arch/arm/boot/compressed/decompress.c index f41b38cafce8..9deb56a702ce 100644 --- a/arch/arm/boot/compressed/decompress.c +++ b/arch/arm/boot/compressed/decompress.c @@ -32,6 +32,9 @@ extern void error(char *); # define Tracecv(c,x) #endif +/* Not needed, but used in some headers pulled in by decompressors */ +extern char * strstr(const char * s1, const char *s2); + #ifdef CONFIG_KERNEL_GZIP #include "../../../../lib/decompress_inflate.c" #endif diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index bc67cbff3944..90275f036cd1 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -9,6 +9,7 @@ * published by the Free Software Foundation. */ #include <linux/linkage.h> +#include <asm/assembler.h> /* * Debugging stuff @@ -132,7 +133,12 @@ start: .word start @ absolute load/run zImage address .word _edata @ zImage end address THUMB( .thumb ) -1: mov r7, r1 @ save architecture ID +1: + mrs r9, cpsr +#ifdef CONFIG_ARM_VIRT_EXT + bl __hyp_stub_install @ get into SVC mode, reversibly +#endif + mov r7, r1 @ save architecture ID mov r8, r2 @ save atags pointer #ifndef __ARM_ARCH_2__ @@ -148,9 +154,9 @@ start: ARM( swi 0x123456 ) @ angel_SWI_ARM THUMB( svc 0xab ) @ angel_SWI_THUMB not_angel: - mrs r2, cpsr @ turn off interrupts to - orr r2, r2, #0xc0 @ prevent angel from running - msr cpsr_c, r2 + safe_svcmode_maskall r0 + msr spsr_cxsf, r9 @ Save the CPU boot mode in + @ SPSR #else teqp pc, #0x0c000003 @ turn off interrupts #endif @@ -350,6 +356,20 @@ dtb_check_done: adr r5, restart bic r5, r5, #31 +/* Relocate the hyp vector base if necessary */ +#ifdef CONFIG_ARM_VIRT_EXT + mrs r0, spsr + and r0, r0, #MODE_MASK + cmp r0, #HYP_MODE + bne 1f + + bl __hyp_get_vectors + sub r0, r0, r5 + add r0, r0, r10 + bl __hyp_set_vectors +1: +#endif + sub r9, r6, r5 @ size to copy add r9, r9, #31 @ rounded up to a multiple bic r9, r9, #31 @ ... of 32 bytes @@ -458,11 +478,29 @@ not_relocated: mov r0, #0 bl decompress_kernel bl cache_clean_flush bl cache_off - mov r0, #0 @ must be zero mov r1, r7 @ restore architecture number mov r2, r8 @ restore atags pointer - ARM( mov pc, r4 ) @ call kernel - THUMB( bx r4 ) @ entry point is always ARM + +#ifdef CONFIG_ARM_VIRT_EXT + mrs r0, spsr @ Get saved CPU boot mode + and r0, r0, #MODE_MASK + cmp r0, #HYP_MODE @ if not booted in HYP mode... + bne __enter_kernel @ boot kernel directly + + adr r12, .L__hyp_reentry_vectors_offset + ldr r0, [r12] + add r0, r0, r12 + + bl __hyp_set_vectors + __HVC(0) @ otherwise bounce to hyp mode + + b . @ should never be reached + + .align 2 +.L__hyp_reentry_vectors_offset: .long __hyp_reentry_vectors - . +#else + b __enter_kernel +#endif .align 2 .type LC0, #object @@ -1196,6 +1234,25 @@ memdump: mov r12, r0 #endif .ltorg + +#ifdef CONFIG_ARM_VIRT_EXT +.align 5 +__hyp_reentry_vectors: + W(b) . @ reset + W(b) . @ undef + W(b) . @ svc + W(b) . @ pabort + W(b) . @ dabort + W(b) __enter_kernel @ hyp + W(b) . @ irq + W(b) . @ fiq +#endif /* CONFIG_ARM_VIRT_EXT */ + +__enter_kernel: + mov r0, #0 @ must be 0 + ARM( mov pc, r4 ) @ call kernel + THUMB( bx r4 ) @ entry point is always ARM + reloc_code_end: .align diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 43c084c2cd66..f37cf9fa5fa0 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -17,26 +17,26 @@ dtb-$(CONFIG_ARCH_AT91) += aks-cdu.dtb \ usb_a9263.dtb \ usb_a9g20.dtb dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb +dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \ + dove-cubox.dtb \ + dove-dove-db.dtb dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ exynos4210-smdkv310.dtb \ exynos4210-trats.dtb \ exynos5250-smdk5250.dtb dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb -dtb-$(CONFIG_ARCH_IMX5) += imx51-babbage.dtb \ - imx53-ard.dtb \ - imx53-evk.dtb \ - imx53-qsb.dtb \ - imx53-smd.dtb -dtb-$(CONFIG_SOC_IMX6Q) += imx6q-arm2.dtb \ - imx6q-sabrelite.dtb \ - imx6q-sabresd.dtb +dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \ + integratorcp.dtb dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-dns320.dtb \ kirkwood-dns325.dtb \ + kirkwood-dockstar.dtb \ kirkwood-dreamplug.dtb \ kirkwood-goflexnet.dtb \ kirkwood-ib62x0.dtb \ kirkwood-iconnect.dtb \ + kirkwood-iomega_ix2_200.dtb \ + kirkwood-km_kirkwood.dtb \ kirkwood-lschlv2.dtb \ kirkwood-lsxhl.dtb \ kirkwood-ts219-6281.dtb \ @@ -70,7 +70,9 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ omap4-pandaES.dtb \ omap4-var_som.dtb \ omap4-sdp.dtb \ - omap5-evm.dtb + omap5-evm.dtb \ + am335x-evm.dtb \ + am335x-bone.dtb dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb dtb-$(CONFIG_ARCH_U8500) += snowball.dtb dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ @@ -96,6 +98,10 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \ vexpress-v2p-ca9.dtb \ vexpress-v2p-ca15-tc1.dtb \ - vexpress-v2p-ca15_a7.dtb + vexpress-v2p-ca15_a7.dtb \ + xenvm-4.2.dtb +dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \ + wm8505-ref.dtb \ + wm8650-mid.dtb endif diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 6b6b932a5a7d..16cc82cdaa81 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -63,6 +63,11 @@ reg = <0xd0020300 0x30>; interrupts = <37>, <38>, <39>, <40>; }; + + addr-decoding@d0020000 { + compatible = "marvell,armada-addr-decoding-controller"; + reg = <0xd0020000 0x258>; + }; }; }; diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index 3228ccc83332..2069151afe01 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -21,6 +21,12 @@ model = "Marvell Armada 370 family SoC"; compatible = "marvell,armada370", "marvell,armada-370-xp"; + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + }; + mpic: interrupt-controller@d0020000 { reg = <0xd0020a00 0x1d0>, <0xd0021870 0x58>; @@ -31,5 +37,43 @@ compatible = "marvell,armada-370-xp-system-controller"; reg = <0xd0018200 0x100>; }; + + pinctrl { + compatible = "marvell,mv88f6710-pinctrl"; + reg = <0xd0018000 0x38>; + }; + + gpio0: gpio@d0018100 { + compatible = "marvell,orion-gpio"; + reg = <0xd0018100 0x40>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupts-cells = <2>; + interrupts = <82>, <83>, <84>, <85>; + }; + + gpio1: gpio@d0018140 { + compatible = "marvell,orion-gpio"; + reg = <0xd0018140 0x40>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupts-cells = <2>; + interrupts = <87>, <88>, <89>, <90>; + }; + + gpio2: gpio@d0018180 { + compatible = "marvell,orion-gpio"; + reg = <0xd0018180 0x40>; + ngpios = <2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupts-cells = <2>; + interrupts = <91>; + }; }; }; diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts index f97040d4258d..b1fc728515e9 100644 --- a/arch/arm/boot/dts/armada-xp-db.dts +++ b/arch/arm/boot/dts/armada-xp-db.dts @@ -14,11 +14,11 @@ */ /dts-v1/; -/include/ "armada-xp.dtsi" +/include/ "armada-xp-mv78460.dtsi" / { model = "Marvell Armada XP Evaluation Board"; - compatible = "marvell,axp-db", "marvell,armadaxp", "marvell,armada-370-xp"; + compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; chosen { bootargs = "console=ttyS0,115200 earlyprintk"; diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi new file mode 100644 index 000000000000..ea355192be6f --- /dev/null +++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi @@ -0,0 +1,57 @@ +/* + * Device Tree Include file for Marvell Armada XP family SoC + * + * Copyright (C) 2012 Marvell + * + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * Contains definitions specific to the Armada XP MV78230 SoC that are not + * common to all Armada XP SoCs. + */ + +/include/ "armada-xp.dtsi" + +/ { + model = "Marvell Armada XP MV78230 SoC"; + compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp"; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + }; + + soc { + pinctrl { + compatible = "marvell,mv78230-pinctrl"; + reg = <0xd0018000 0x38>; + }; + + gpio0: gpio@d0018100 { + compatible = "marvell,armadaxp-gpio"; + reg = <0xd0018100 0x40>, + <0xd0018800 0x30>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupts-cells = <2>; + interrupts = <16>, <17>, <18>, <19>; + }; + + gpio1: gpio@d0018140 { + compatible = "marvell,armadaxp-gpio"; + reg = <0xd0018140 0x40>, + <0xd0018840 0x30>; + ngpios = <17>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupts-cells = <2>; + interrupts = <20>, <21>, <22>; + }; + }; +}; diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi new file mode 100644 index 000000000000..2057863f3dfa --- /dev/null +++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi @@ -0,0 +1,70 @@ +/* + * Device Tree Include file for Marvell Armada XP family SoC + * + * Copyright (C) 2012 Marvell + * + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * Contains definitions specific to the Armada XP MV78260 SoC that are not + * common to all Armada XP SoCs. + */ + +/include/ "armada-xp.dtsi" + +/ { + model = "Marvell Armada XP MV78260 SoC"; + compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp"; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + }; + + soc { + pinctrl { + compatible = "marvell,mv78260-pinctrl"; + reg = <0xd0018000 0x38>; + }; + + gpio0: gpio@d0018100 { + compatible = "marvell,armadaxp-gpio"; + reg = <0xd0018100 0x40>, + <0xd0018800 0x30>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupts-cells = <2>; + interrupts = <16>, <17>, <18>, <19>; + }; + + gpio1: gpio@d0018140 { + compatible = "marvell,armadaxp-gpio"; + reg = <0xd0018140 0x40>, + <0xd0018840 0x30>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupts-cells = <2>; + interrupts = <20>, <21>, <22>, <23>; + }; + + gpio2: gpio@d0018180 { + compatible = "marvell,armadaxp-gpio"; + reg = <0xd0018180 0x40>, + <0xd0018870 0x30>; + ngpios = <3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupts-cells = <2>; + interrupts = <24>; + }; + }; +}; diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi new file mode 100644 index 000000000000..ffac98373792 --- /dev/null +++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi @@ -0,0 +1,70 @@ +/* + * Device Tree Include file for Marvell Armada XP family SoC + * + * Copyright (C) 2012 Marvell + * + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * Contains definitions specific to the Armada XP MV78460 SoC that are not + * common to all Armada XP SoCs. + */ + +/include/ "armada-xp.dtsi" + +/ { + model = "Marvell Armada XP MV78460 SoC"; + compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + }; + + soc { + pinctrl { + compatible = "marvell,mv78460-pinctrl"; + reg = <0xd0018000 0x38>; + }; + + gpio0: gpio@d0018100 { + compatible = "marvell,armadaxp-gpio"; + reg = <0xd0018100 0x40>, + <0xd0018800 0x30>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupts-cells = <2>; + interrupts = <16>, <17>, <18>, <19>; + }; + + gpio1: gpio@d0018140 { + compatible = "marvell,armadaxp-gpio"; + reg = <0xd0018140 0x40>, + <0xd0018840 0x30>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupts-cells = <2>; + interrupts = <20>, <21>, <22>, <23>; + }; + + gpio2: gpio@d0018180 { + compatible = "marvell,armadaxp-gpio"; + reg = <0xd0018180 0x40>, + <0xd0018870 0x30>; + ngpios = <3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupts-cells = <2>; + interrupts = <24>; + }; + }; + }; diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index 7c95f76398de..d410581a5a85 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -28,6 +28,7 @@ gpio2 = &pioC; tcb0 = &tcb0; tcb1 = &tcb1; + i2c0 = &i2c0; }; cpus { cpu@0 { @@ -202,6 +203,15 @@ status = "disabled"; }; + i2c0: i2c@fffac000 { + compatible = "atmel,at91sam9260-i2c"; + reg = <0xfffac000 0x100>; + interrupts = <11 4 6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + adc0: adc@fffe0000 { compatible = "atmel,at91sam9260-adc"; reg = <0xfffe0000 0x100>; diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index 195019b7ca0e..3e6e5c1abbf3 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -24,6 +24,7 @@ gpio3 = &pioD; gpio4 = &pioE; tcb0 = &tcb0; + i2c0 = &i2c0; }; cpus { cpu@0 { @@ -185,6 +186,15 @@ interrupts = <24 4 2>; status = "disabled"; }; + + i2c0: i2c@fff88000 { + compatible = "atmel,at91sam9263-i2c"; + reg = <0xfff88000 0x100>; + interrupts = <13 4 6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; nand0: nand@40000000 { diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi index 2a1d1ca8bd86..75ce6e760016 100644 --- a/arch/arm/boot/dts/at91sam9g20.dtsi +++ b/arch/arm/boot/dts/at91sam9g20.dtsi @@ -18,6 +18,10 @@ ahb { apb { + i2c0: i2c@fffac000 { + compatible = "atmel,at91sam9g20-i2c"; + }; + adc0: adc@fffe0000 { atmel,adc-startup-time = <40>; }; diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi index b06c0db273b1..e6391a4e6649 100644 --- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi +++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi @@ -126,14 +126,14 @@ #size-cells = <0>; btn3 { - label = "Buttin 3"; + label = "Button 3"; gpios = <&pioA 30 1>; linux,code = <0x103>; gpio-key,wakeup; }; btn4 { - label = "Buttin 4"; + label = "Button 4"; gpios = <&pioA 31 1>; linux,code = <0x104>; gpio-key,wakeup; diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts index 96514c134e54..877c08f06763 100644 --- a/arch/arm/boot/dts/at91sam9g25ek.dts +++ b/arch/arm/boot/dts/at91sam9g25ek.dts @@ -32,6 +32,18 @@ phy-mode = "rmii"; status = "okay"; }; + + i2c0: i2c@f8010000 { + status = "okay"; + }; + + i2c1: i2c@f8014000 { + status = "okay"; + }; + + i2c2: i2c@f8018000 { + status = "okay"; + }; }; usb0: ohci@00600000 { diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 63751b1e744b..3add030d61f8 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -29,6 +29,8 @@ gpio4 = &pioE; tcb0 = &tcb0; tcb1 = &tcb1; + i2c0 = &i2c0; + i2c1 = &i2c1; }; cpus { cpu@0 { @@ -206,6 +208,24 @@ status = "disabled"; }; + i2c0: i2c@fff84000 { + compatible = "atmel,at91sam9g10-i2c"; + reg = <0xfff84000 0x100>; + interrupts = <12 4 6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@fff88000 { + compatible = "atmel,at91sam9g10-i2c"; + reg = <0xfff88000 0x100>; + interrupts = <13 4 6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + adc0: adc@fffb0000 { compatible = "atmel,at91sam9260-adc"; reg = <0xfffb0000 0x100>; diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts index a3633bd13111..15e1dd43f625 100644 --- a/arch/arm/boot/dts/at91sam9m10g45ek.dts +++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts @@ -46,6 +46,14 @@ phy-mode = "rmii"; status = "okay"; }; + + i2c0: i2c@fff84000 { + status = "okay"; + }; + + i2c1: i2c@fff88000 { + status = "okay"; + }; }; nand0: nand@40000000 { diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index ef9336ae9614..82508d68aa7e 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -26,6 +26,8 @@ gpio3 = &pioD; tcb0 = &tcb0; tcb1 = &tcb1; + i2c0 = &i2c0; + i2c1 = &i2c1; }; cpus { cpu@0 { @@ -182,6 +184,24 @@ atmel,use-dma-tx; status = "disabled"; }; + + i2c0: i2c@f8010000 { + compatible = "atmel,at91sam9x5-i2c"; + reg = <0xf8010000 0x100>; + interrupts = <9 4 6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@f8014000 { + compatible = "atmel,at91sam9x5-i2c"; + reg = <0xf8014000 0x100>; + interrupts = <10 4 6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; nand0: nand@40000000 { diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts index f4e43e38f3a1..912b2c283d6f 100644 --- a/arch/arm/boot/dts/at91sam9n12ek.dts +++ b/arch/arm/boot/dts/at91sam9n12ek.dts @@ -37,6 +37,14 @@ dbgu: serial@fffff200 { status = "okay"; }; + + i2c0: i2c@f8010000 { + status = "okay"; + }; + + i2c1: i2c@f8014000 { + status = "okay"; + }; }; nand0: nand@40000000 { diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 8a387a8d61b7..03fc136421c5 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -27,6 +27,9 @@ gpio3 = &pioD; tcb0 = &tcb0; tcb1 = &tcb1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; }; cpus { cpu@0 { @@ -196,6 +199,33 @@ status = "disabled"; }; + i2c0: i2c@f8010000 { + compatible = "atmel,at91sam9x5-i2c"; + reg = <0xf8010000 0x100>; + interrupts = <9 4 6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@f8014000 { + compatible = "atmel,at91sam9x5-i2c"; + reg = <0xf8014000 0x100>; + interrupts = <10 4 6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@f8018000 { + compatible = "atmel,at91sam9x5-i2c"; + reg = <0xf8018000 0x100>; + interrupts = <11 4 6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + adc0: adc@f804c000 { compatible = "atmel,at91sam9260-adc"; reg = <0xf804c000 0x100>; diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi index 748ba7aa746c..4b0e0ca08f40 100644 --- a/arch/arm/boot/dts/dbx5x0.dtsi +++ b/arch/arm/boot/dts/dbx5x0.dtsi @@ -483,6 +483,8 @@ compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; reg = <0x80004000 0x1000>; interrupts = <0 21 0x4>; + arm,primecell-periphid = <0x180024>; + #address-cells = <1>; #size-cells = <0>; v-i2c-supply = <&db8500_vape_reg>; @@ -494,6 +496,8 @@ compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; reg = <0x80122000 0x1000>; interrupts = <0 22 0x4>; + arm,primecell-periphid = <0x180024>; + #address-cells = <1>; #size-cells = <0>; v-i2c-supply = <&db8500_vape_reg>; @@ -505,6 +509,8 @@ compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; reg = <0x80128000 0x1000>; interrupts = <0 55 0x4>; + arm,primecell-periphid = <0x180024>; + #address-cells = <1>; #size-cells = <0>; v-i2c-supply = <&db8500_vape_reg>; @@ -516,6 +522,8 @@ compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; reg = <0x80110000 0x1000>; interrupts = <0 12 0x4>; + arm,primecell-periphid = <0x180024>; + #address-cells = <1>; #size-cells = <0>; v-i2c-supply = <&db8500_vape_reg>; @@ -527,6 +535,8 @@ compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; reg = <0x8012a000 0x1000>; interrupts = <0 51 0x4>; + arm,primecell-periphid = <0x180024>; + #address-cells = <1>; #size-cells = <0>; v-i2c-supply = <&db8500_vape_reg>; @@ -573,33 +583,38 @@ interrupts = <0 60 0x4>; status = "disabled"; }; + sdi@80118000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x80118000 0x1000>; interrupts = <0 50 0x4>; status = "disabled"; }; + sdi@80005000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x80005000 0x1000>; interrupts = <0 41 0x4>; status = "disabled"; }; + sdi@80119000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x80119000 0x1000>; interrupts = <0 59 0x4>; status = "disabled"; }; + sdi@80114000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x80114000 0x1000>; interrupts = <0 99 0x4>; status = "disabled"; }; + sdi@80008000 { compatible = "arm,pl18x", "arm,primecell"; - reg = <0x80114000 0x1000>; + reg = <0x80008000 0x1000>; interrupts = <0 100 0x4>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/dove-cm-a510.dts b/arch/arm/boot/dts/dove-cm-a510.dts new file mode 100644 index 000000000000..61a8062e56de --- /dev/null +++ b/arch/arm/boot/dts/dove-cm-a510.dts @@ -0,0 +1,38 @@ +/dts-v1/; + +/include/ "dove.dtsi" + +/ { + model = "Compulab CM-A510"; + compatible = "compulab,cm-a510", "marvell,dove"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x40000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + }; +}; + +&uart0 { status = "okay"; }; +&uart1 { status = "okay"; }; +&sdio0 { status = "okay"; }; +&sdio1 { status = "okay"; }; +&sata0 { status = "okay"; }; + +&spi0 { + status = "okay"; + + /* spi0.0: 4M Flash Winbond W25Q32BV */ + spi-flash@0 { + compatible = "st,w25q32"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&i2c0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts new file mode 100644 index 000000000000..0adbd5a38095 --- /dev/null +++ b/arch/arm/boot/dts/dove-cubox.dts @@ -0,0 +1,42 @@ +/dts-v1/; + +/include/ "dove.dtsi" + +/ { + model = "SolidRun CuBox"; + compatible = "solidrun,cubox", "marvell,dove"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x40000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + }; + + leds { + compatible = "gpio-leds"; + power { + label = "Power"; + gpios = <&gpio0 18 1>; + linux,default-trigger = "default-on"; + }; + }; +}; + +&uart0 { status = "okay"; }; +&sdio0 { status = "okay"; }; +&sata0 { status = "okay"; }; +&i2c0 { status = "okay"; }; + +&spi0 { + status = "okay"; + + /* spi0.0: 4M Flash Winbond W25Q32BV */ + spi-flash@0 { + compatible = "st,w25q32"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; diff --git a/arch/arm/boot/dts/dove-dove-db.dts b/arch/arm/boot/dts/dove-dove-db.dts new file mode 100644 index 000000000000..e5a920beab45 --- /dev/null +++ b/arch/arm/boot/dts/dove-dove-db.dts @@ -0,0 +1,38 @@ +/dts-v1/; + +/include/ "dove.dtsi" + +/ { + model = "Marvell DB-MV88AP510-BP Development Board"; + compatible = "marvell,dove-db", "marvell,dove"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x40000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + }; +}; + +&uart0 { status = "okay"; }; +&uart1 { status = "okay"; }; +&sdio0 { status = "okay"; }; +&sdio1 { status = "okay"; }; +&sata0 { status = "okay"; }; + +&spi0 { + status = "okay"; + + /* spi0.0: 4M Flash ST-M25P32-VMF6P */ + spi-flash@0 { + compatible = "st,m25p32"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&i2c0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi new file mode 100644 index 000000000000..5a00022383e7 --- /dev/null +++ b/arch/arm/boot/dts/dove.dtsi @@ -0,0 +1,158 @@ +/include/ "skeleton.dtsi" + +/ { + compatible = "marvell,dove"; + model = "Marvell Armada 88AP510 SoC"; + + soc@f1000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + ranges = <0xc8000000 0xc8000000 0x0100000 /* CESA SRAM 1M */ + 0xe0000000 0xe0000000 0x8000000 /* PCIe0 Mem 128M */ + 0xe8000000 0xe8000000 0x8000000 /* PCIe1 Mem 128M */ + 0xf0000000 0xf0000000 0x0100000 /* ScratchPad 1M */ + 0x00000000 0xf1000000 0x1000000 /* SB/NB regs 16M */ + 0xf2000000 0xf2000000 0x0100000 /* PCIe0 I/O 1M */ + 0xf2100000 0xf2100000 0x0100000 /* PCIe0 I/O 1M */ + 0xf8000000 0xf8000000 0x8000000>; /* BootROM 128M */ + + l2: l2-cache { + compatible = "marvell,tauros2-cache"; + marvell,tauros2-cache-features = <0>; + }; + + intc: interrupt-controller { + compatible = "marvell,orion-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x20204 0x04>, <0x20214 0x04>; + }; + + uart0: serial@12000 { + compatible = "ns16550a"; + reg = <0x12000 0x100>; + reg-shift = <2>; + interrupts = <7>; + clock-frequency = <166666667>; + status = "disabled"; + }; + + uart1: serial@12100 { + compatible = "ns16550a"; + reg = <0x12100 0x100>; + reg-shift = <2>; + interrupts = <8>; + clock-frequency = <166666667>; + status = "disabled"; + }; + + uart2: serial@12200 { + compatible = "ns16550a"; + reg = <0x12000 0x100>; + reg-shift = <2>; + interrupts = <9>; + clock-frequency = <166666667>; + status = "disabled"; + }; + + uart3: serial@12300 { + compatible = "ns16550a"; + reg = <0x12100 0x100>; + reg-shift = <2>; + interrupts = <10>; + clock-frequency = <166666667>; + status = "disabled"; + }; + + gpio0: gpio@d0400 { + compatible = "marvell,orion-gpio"; + #gpio-cells = <2>; + gpio-controller; + reg = <0xd0400 0x20>; + ngpio = <32>; + interrupts = <12>, <13>, <14>, <60>; + }; + + gpio1: gpio@d0420 { + compatible = "marvell,orion-gpio"; + #gpio-cells = <2>; + gpio-controller; + reg = <0xd0420 0x20>; + ngpio = <32>; + interrupts = <61>; + }; + + gpio2: gpio@e8400 { + compatible = "marvell,orion-gpio"; + #gpio-cells = <2>; + gpio-controller; + reg = <0xe8400 0x0c>; + ngpio = <8>; + }; + + spi0: spi@10600 { + compatible = "marvell,orion-spi"; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + interrupts = <6>; + reg = <0x10600 0x28>; + status = "disabled"; + }; + + spi1: spi@14600 { + compatible = "marvell,orion-spi"; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + interrupts = <5>; + reg = <0x14600 0x28>; + status = "disabled"; + }; + + i2c0: i2c@11000 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <11>; + clock-frequency = <400000>; + timeout-ms = <1000>; + status = "disabled"; + }; + + sdio0: sdio@92000 { + compatible = "marvell,dove-sdhci"; + reg = <0x92000 0x100>; + interrupts = <35>, <37>; + status = "disabled"; + }; + + sdio1: sdio@90000 { + compatible = "marvell,dove-sdhci"; + reg = <0x90000 0x100>; + interrupts = <36>, <38>; + status = "disabled"; + }; + + sata0: sata@a0000 { + compatible = "marvell,orion-sata"; + reg = <0xa0000 0x2400>; + interrupts = <62>; + nr-ports = <1>; + status = "disabled"; + }; + + crypto: crypto@30000 { + compatible = "marvell,orion-crypto"; + reg = <0x30000 0x10000>, + <0xc8000000 0x800>; + reg-names = "regs", "sram"; + interrupts = <31>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index 73567b843e72..a21511c14071 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -20,8 +20,10 @@ compatible = "samsung,trats", "samsung,exynos4210"; memory { - reg = <0x40000000 0x20000000 - 0x60000000 0x20000000>; + reg = <0x40000000 0x10000000 + 0x50000000 0x10000000 + 0x60000000 0x10000000 + 0x70000000 0x10000000>; }; chosen { diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index 9ca4ca70c1bc..6d31aa383460 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi @@ -69,6 +69,7 @@ interrupts = <13>, <56>; interrupt-names = "gpmi-dma", "bch"; clocks = <&clks 34>; + clock-names = "gpmi_io"; fsl,gpmi-dma-channel = <4>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 59fbfba23df8..55c57ea6169e 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -85,6 +85,7 @@ interrupts = <88>, <41>; interrupt-names = "gpmi-dma", "bch"; clocks = <&clks 50>; + clock-names = "gpmi_io"; fsl,gpmi-dma-channel = <4>; status = "disabled"; }; @@ -764,6 +765,7 @@ reg = <0x80058000 0x2000>; interrupts = <111 68>; clock-frequency = <100000>; + fsl,i2c-dma-channel = <6>; status = "disabled"; }; @@ -774,6 +776,7 @@ reg = <0x8005a000 0x2000>; interrupts = <110 69>; clock-frequency = <100000>; + fsl,i2c-dma-channel = <7>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 2f71a91ca98e..75d069fcf897 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -407,6 +407,13 @@ status = "disabled"; }; + nand@83fdb000 { + compatible = "fsl,imx51-nand"; + reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>; + interrupts = <8>; + status = "disabled"; + }; + ssi3: ssi@83fe8000 { compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; reg = <0x83fe8000 0x4000>; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 221cf3321b0a..76ebb1ad2675 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -518,6 +518,13 @@ status = "disabled"; }; + nand@63fdb000 { + compatible = "fsl,imx53-nand"; + reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>; + interrupts = <8>; + status = "disabled"; + }; + ssi3: ssi@63fe8000 { compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; reg = <0x63fe8000 0x4000>; diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts index 15df4c105e89..5bfa02a3f85c 100644 --- a/arch/arm/boot/dts/imx6q-arm2.dts +++ b/arch/arm/boot/dts/imx6q-arm2.dts @@ -37,6 +37,13 @@ pinctrl_hog: hoggrp { fsl,pins = < 176 0x80000000 /* MX6Q_PAD_EIM_D25__GPIO_3_25 */ + >; + }; + }; + + arm2 { + pinctrl_usdhc3_arm2: usdhc3grp-arm2 { + fsl,pins = < 1363 0x80000000 /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */ 1369 0x80000000 /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */ >; @@ -58,7 +65,8 @@ wp-gpios = <&gpio6 14 0>; vmmc-supply = <®_3p3v>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3_1>; + pinctrl-0 = <&pinctrl_usdhc3_1 + &pinctrl_usdhc3_arm2>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 35e5895ba3df..f3990b04fecf 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -400,8 +400,8 @@ #clock-cells = <1>; }; - anatop@020c8000 { - compatible = "fsl,imx6q-anatop"; + anatop: anatop@020c8000 { + compatible = "fsl,imx6q-anatop", "syscon", "simple-bus"; reg = <0x020c8000 0x1000>; interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>; @@ -531,6 +531,11 @@ interrupts = <0 89 0x04 0 90 0x04>; }; + gpr: iomuxc-gpr@020e0000 { + compatible = "fsl,imx6q-iomuxc-gpr", "syscon"; + reg = <0x020e0000 0x38>; + }; + iomuxc@020e0000 { compatible = "fsl,imx6q-iomuxc"; reg = <0x020e0000 0x4000>; diff --git a/arch/arm/boot/dts/integrator.dtsi b/arch/arm/boot/dts/integrator.dtsi new file mode 100644 index 000000000000..813b91d7bea2 --- /dev/null +++ b/arch/arm/boot/dts/integrator.dtsi @@ -0,0 +1,76 @@ +/* + * SoC core Device Tree for the ARM Integrator platforms + */ + +/include/ "skeleton.dtsi" + +/ { + timer@13000000 { + reg = <0x13000000 0x100>; + interrupt-parent = <&pic>; + interrupts = <5>; + }; + + timer@13000100 { + reg = <0x13000100 0x100>; + interrupt-parent = <&pic>; + interrupts = <6>; + }; + + timer@13000200 { + reg = <0x13000200 0x100>; + interrupt-parent = <&pic>; + interrupts = <7>; + }; + + pic@14000000 { + compatible = "arm,versatile-fpga-irq"; + #interrupt-cells = <1>; + interrupt-controller; + reg = <0x14000000 0x100>; + clear-mask = <0xffffffff>; + }; + + flash@24000000 { + compatible = "cfi-flash"; + reg = <0x24000000 0x02000000>; + }; + + fpga { + compatible = "arm,amba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-parent = <&pic>; + + /* + * These PrimeCells are in the same locations and using the + * same interrupts in all Integrators, however the silicon + * version deployed is different. + */ + rtc@15000000 { + reg = <0x15000000 0x1000>; + interrupts = <8>; + }; + + uart@16000000 { + reg = <0x16000000 0x1000>; + interrupts = <1>; + }; + + uart@17000000 { + reg = <0x17000000 0x1000>; + interrupts = <2>; + }; + + kmi@18000000 { + reg = <0x18000000 0x1000>; + interrupts = <3>; + }; + + kmi@19000000 { + reg = <0x19000000 0x1000>; + interrupts = <4>; + }; + }; +}; diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts new file mode 100644 index 000000000000..61767757b50a --- /dev/null +++ b/arch/arm/boot/dts/integratorap.dts @@ -0,0 +1,68 @@ +/* + * Device Tree for the ARM Integrator/AP platform + */ + +/dts-v1/; +/include/ "integrator.dtsi" + +/ { + model = "ARM Integrator/AP"; + compatible = "arm,integrator-ap"; + + aliases { + arm,timer-primary = &timer2; + arm,timer-secondary = &timer1; + }; + + chosen { + bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk"; + }; + + timer0: timer@13000000 { + compatible = "arm,integrator-timer"; + }; + + timer1: timer@13000100 { + compatible = "arm,integrator-timer"; + }; + + timer2: timer@13000200 { + compatible = "arm,integrator-timer"; + }; + + pic: pic@14000000 { + valid-mask = <0x003fffff>; + }; + + fpga { + /* + * The Integator/AP predates the idea to have magic numbers + * identifying the PrimeCell in hardware, thus we have to + * supply these from the device tree. + */ + rtc: rtc@15000000 { + compatible = "arm,pl030", "arm,primecell"; + arm,primecell-periphid = <0x00041030>; + }; + + uart0: uart@16000000 { + compatible = "arm,pl010", "arm,primecell"; + arm,primecell-periphid = <0x00041010>; + }; + + uart1: uart@17000000 { + compatible = "arm,pl010", "arm,primecell"; + arm,primecell-periphid = <0x00041010>; + }; + + kmi0: kmi@18000000 { + compatible = "arm,pl050", "arm,primecell"; + arm,primecell-periphid = <0x00041050>; + }; + + kmi1: kmi@19000000 { + compatible = "arm,pl050", "arm,primecell"; + arm,primecell-periphid = <0x00041050>; + }; + }; +}; diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts new file mode 100644 index 000000000000..2dd5e4e48481 --- /dev/null +++ b/arch/arm/boot/dts/integratorcp.dts @@ -0,0 +1,110 @@ +/* + * Device Tree for the ARM Integrator/CP platform + */ + +/dts-v1/; +/include/ "integrator.dtsi" + +/ { + model = "ARM Integrator/CP"; + compatible = "arm,integrator-cp"; + + aliases { + arm,timer-primary = &timer2; + arm,timer-secondary = &timer1; + }; + + chosen { + bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk"; + }; + + timer0: timer@13000000 { + compatible = "arm,sp804", "arm,primecell"; + }; + + timer1: timer@13000100 { + compatible = "arm,sp804", "arm,primecell"; + }; + + timer2: timer@13000200 { + compatible = "arm,sp804", "arm,primecell"; + }; + + pic: pic@14000000 { + valid-mask = <0x1fc003ff>; + }; + + cic: cic@10000040 { + compatible = "arm,versatile-fpga-irq"; + #interrupt-cells = <1>; + interrupt-controller; + reg = <0x10000040 0x100>; + clear-mask = <0xffffffff>; + valid-mask = <0x00000007>; + }; + + sic: sic@ca000000 { + compatible = "arm,versatile-fpga-irq"; + #interrupt-cells = <1>; + interrupt-controller; + reg = <0xca000000 0x100>; + clear-mask = <0x00000fff>; + valid-mask = <0x00000fff>; + }; + + ethernet@c8000000 { + compatible = "smsc,lan91c111"; + reg = <0xc8000000 0x10>; + interrupt-parent = <&pic>; + interrupts = <27>; + }; + + fpga { + /* + * These PrimeCells are at the same location and using + * the same interrupts in all Integrators, but in the CP + * slightly newer versions are deployed. + */ + rtc@15000000 { + compatible = "arm,pl031", "arm,primecell"; + }; + + uart@16000000 { + compatible = "arm,pl011", "arm,primecell"; + }; + + uart@17000000 { + compatible = "arm,pl011", "arm,primecell"; + }; + + kmi@18000000 { + compatible = "arm,pl050", "arm,primecell"; + }; + + kmi@19000000 { + compatible = "arm,pl050", "arm,primecell"; + }; + + /* + * These PrimeCells are only available on the Integrator/CP + */ + mmc@1c000000 { + compatible = "arm,pl180", "arm,primecell"; + reg = <0x1c000000 0x1000>; + interrupts = <23 24>; + max-frequency = <515633>; + }; + + aaci@1d000000 { + compatible = "arm,pl041", "arm,primecell"; + reg = <0x1d000000 0x1000>; + interrupts = <25>; + }; + + clcd@c0000000 { + compatible = "arm,pl110", "arm,primecell"; + reg = <0xC0000000 0x1000>; + interrupts = <22>; + }; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi index 7408655f91b5..9b32d0272825 100644 --- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi +++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi @@ -25,6 +25,16 @@ }; }; + gpio_fan { + /* Fan: ADDA AD045HB-G73 40mm 6000rpm@5v */ + compatible = "gpio-fan"; + gpios = <&gpio1 14 1 + &gpio1 13 1>; + gpio-fan,speed-map = <0 0 + 3000 1 + 6000 2>; + }; + ocp@f1000000 { sata@80000 { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts new file mode 100644 index 000000000000..08a582414b88 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-dockstar.dts @@ -0,0 +1,57 @@ +/dts-v1/; + +/include/ "kirkwood.dtsi" + +/ { + model = "Seagate FreeAgent Dockstar"; + compatible = "seagate,dockstar", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10"; + }; + + ocp@f1000000 { + serial@12000 { + clock-frequency = <200000000>; + status = "ok"; + }; + + nand@3000000 { + status = "okay"; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x100000>; + read-only; + }; + + partition@100000 { + label = "uImage"; + reg = <0x0100000 0x400000>; + }; + + partition@500000 { + label = "data"; + reg = <0x0500000 0xfb00000>; + }; + }; + }; + gpio-leds { + compatible = "gpio-leds"; + + health { + label = "status:green:health"; + gpios = <&gpio1 14 1>; + linux,default-trigger = "default-on"; + }; + fault { + label = "status:orange:fault"; + gpios = <&gpio1 15 1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts index f8ca6fa88192..d97cd9d4753e 100644 --- a/arch/arm/boot/dts/kirkwood-iconnect.dts +++ b/arch/arm/boot/dts/kirkwood-iconnect.dts @@ -12,7 +12,7 @@ }; chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk mtdparts=orion_nand:0xc0000@0x0(uboot),0x20000@0xa0000(env),0x300000@0x100000(zImage),0x300000@0x540000(initrd),0x1f400000@0x980000(boot)"; + bootargs = "console=ttyS0,115200n8 earlyprintk"; linux,initrd-start = <0x4500040>; linux,initrd-end = <0x4800000>; }; @@ -30,7 +30,37 @@ clock-frequency = <200000000>; status = "ok"; }; + + nand@3000000 { + status = "okay"; + + partition@0 { + label = "uboot"; + reg = <0x0000000 0xc0000>; + }; + + partition@a0000 { + label = "env"; + reg = <0xa0000 0x20000>; + }; + + partition@100000 { + label = "zImage"; + reg = <0x100000 0x300000>; + }; + + partition@540000 { + label = "initrd"; + reg = <0x540000 0x300000>; + }; + + partition@980000 { + label = "boot"; + reg = <0x980000 0x1f400000>; + }; + }; }; + gpio-leds { compatible = "gpio-leds"; @@ -69,4 +99,22 @@ gpios = <&gpio1 16 0>; }; }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + button@1 { + label = "OTB Button"; + linux,code = <133>; + gpios = <&gpio1 3 1>; + debounce-interval = <100>; + }; + button@2 { + label = "Reset"; + linux,code = <0x198>; + gpios = <&gpio0 12 1>; + debounce-interval = <100>; + }; + }; }; diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts new file mode 100644 index 000000000000..865aeec40a26 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts @@ -0,0 +1,105 @@ +/dts-v1/; + +/include/ "kirkwood.dtsi" + +/ { + model = "Iomega StorCenter ix2-200"; + compatible = "iom,ix2-200", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + }; + + ocp@f1000000 { + i2c@11000 { + status = "okay"; + + lm63: lm63@4c { + compatible = "national,lm63"; + reg = <0x4c>; + }; + }; + + serial@12000 { + clock-frequency = <200000000>; + status = "ok"; + }; + + nand@3000000 { + status = "okay"; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x100000>; + read-only; + }; + + partition@a0000 { + label = "env"; + reg = <0xa0000 0x20000>; + read-only; + }; + + partition@100000 { + label = "uImage"; + reg = <0x100000 0x300000>; + }; + + partition@400000 { + label = "uInitrd"; + reg = <0x540000 0x1000000>; + }; + }; + sata@80000 { + status = "okay"; + nr-ports = <2>; + }; + + }; + gpio-leds { + compatible = "gpio-leds"; + + power_led { + label = "status:white:power_led"; + gpios = <&gpio0 16 0>; + linux,default-trigger = "default-on"; + }; + health_led1 { + label = "status:red:health_led"; + gpios = <&gpio1 5 0>; + }; + health_led2 { + label = "status:white:health_led"; + gpios = <&gpio1 4 0>; + }; + backup_led { + label = "status:blue:backup_led"; + gpios = <&gpio0 15 0>; + }; + }; + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + Power { + label = "Power Button"; + linux,code = <116>; + gpios = <&gpio0 14 1>; + }; + Reset { + label = "Reset Button"; + linux,code = <0x198>; + gpios = <&gpio0 12 1>; + }; + OTB { + label = "OTB Button"; + linux,code = <133>; + gpios = <&gpio1 3 1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts new file mode 100644 index 000000000000..75bdb93fed26 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts @@ -0,0 +1,29 @@ +/dts-v1/; + +/include/ "kirkwood.dtsi" + +/ { + model = "Keymile Kirkwood Reference Design"; + compatible = "keymile,km_kirkwood", "marvell,kirkwood-98DX4122", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x08000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + }; + + ocp@f1000000 { + serial@12000 { + clock-frequency = <200000000>; + status = "ok"; + }; + + nand@3000000 { + status = "ok"; + chip-delay = <25>; + }; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi index 8ac51c08269d..8fea375c734d 100644 --- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi +++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi @@ -48,17 +48,19 @@ #size-cells = <0>; button@1 { label = "Function Button"; - linux,code = <132>; + linux,code = <357>; gpios = <&gpio1 9 1>; }; button@2 { label = "Power-on Switch"; - linux,code = <116>; + linux,code = <0>; + linux,input-type = <5>; gpios = <&gpio1 10 1>; }; button@3 { label = "Power-auto Switch"; - linux,code = <142>; + linux,code = <1>; + linux,input-type = <5>; gpios = <&gpio1 11 1>; }; }; @@ -67,28 +69,28 @@ compatible = "gpio-leds"; led@1 { - label = "lschlv2:blue:func"; + label = "lsxl:blue:func"; gpios = <&gpio1 4 1>; }; led@2 { - label = "lschlv2:red:alarm"; + label = "lsxl:red:alarm"; gpios = <&gpio1 5 1>; }; led@3 { - label = "lschlv2:amber:info"; + label = "lsxl:amber:info"; gpios = <&gpio1 6 1>; }; led@4 { - label = "lschlv2:blue:power"; + label = "lsxl:blue:power"; gpios = <&gpio1 7 1>; linux,default-trigger = "default-on"; }; led@5 { - label = "lschlv2:red:func"; + label = "lsxl:red:func"; gpios = <&gpio1 16 1>; }; }; diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index cef9616f330a..4e5b8154a5be 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -14,7 +14,8 @@ ocp@f1000000 { compatible = "simple-bus"; - ranges = <0 0xf1000000 0x4000000>; + ranges = <0x00000000 0xf1000000 0x4000000 + 0xf5000000 0xf5000000 0x0000400>; #address-cells = <1>; #size-cells = <1>; @@ -105,5 +106,14 @@ clock-frequency = <100000>; status = "disabled"; }; + + crypto@30000 { + compatible = "marvell,orion-crypto"; + reg = <0x30000 0x10000>, + <0xf5000000 0x800>; + reg-names = "regs", "sram"; + interrupts = <22>; + status = "okay"; + }; }; }; diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index f38ea8771b44..696e929d0304 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -257,7 +257,7 @@ interrupt-names = "common", "tx", "rx", "sidetone"; interrupt-parent = <&intc>; ti,buffer-size = <1280>; - ti,hwmods = "mcbsp2"; + ti,hwmods = "mcbsp2", "mcbsp2_sidetone"; }; mcbsp3: mcbsp@49024000 { @@ -272,7 +272,7 @@ interrupt-names = "common", "tx", "rx", "sidetone"; interrupt-parent = <&intc>; ti,buffer-size = <128>; - ti,hwmods = "mcbsp3"; + ti,hwmods = "mcbsp3", "mcbsp3_sidetone"; }; mcbsp4: mcbsp@49026000 { diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts index 20b966ee1bb3..e8f927cbb376 100644 --- a/arch/arm/boot/dts/omap4-panda.dts +++ b/arch/arm/boot/dts/omap4-panda.dts @@ -59,6 +59,41 @@ }; }; +&omap4_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = < + &twl6040_pins + &mcpdm_pins + &mcbsp1_pins + >; + + twl6040_pins: pinmux_twl6040_pins { + pinctrl-single,pins = < + 0xe0 0x3 /* hdq_sio.gpio_127 OUTPUT | MODE3 */ + 0x160 0x100 /* sys_nirq2.sys_nirq2 INPUT | MODE0 */ + >; + }; + + mcpdm_pins: pinmux_mcpdm_pins { + pinctrl-single,pins = < + 0xc6 0x108 /* abe_pdm_ul_data.abe_pdm_ul_data INPUT PULLDOWN | MODE0 */ + 0xc8 0x108 /* abe_pdm_dl_data.abe_pdm_dl_data INPUT PULLDOWN | MODE0 */ + 0xca 0x118 /* abe_pdm_frame.abe_pdm_frame INPUT PULLUP | MODE0 */ + 0xcc 0x108 /* abe_pdm_lb_clk.abe_pdm_lb_clk INPUT PULLDOWN | MODE0 */ + 0xce 0x108 /* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */ + >; + }; + + mcbsp1_pins: pinmux_mcbsp1_pins { + pinctrl-single,pins = < + 0xbe 0x100 /* abe_mcbsp1_clkx.abe_mcbsp1_clkx INPUT | MODE0 */ + 0xc0 0x108 /* abe_mcbsp1_dr.abe_mcbsp1_dr INPUT PULLDOWN | MODE0 */ + 0xc2 0x8 /* abe_mcbsp1_dx.abe_mcbsp1_dx OUTPUT PULLDOWN | MODE0 */ + 0xc4 0x100 /* abe_mcbsp1_fsx.abe_mcbsp1_fsx INPUT | MODE0 */ + >; + }; +}; + &i2c1 { clock-frequency = <400000>; @@ -137,3 +172,15 @@ cs1-used; device-handle = <&elpida_ECB240ABACN>; }; + +&mcbsp2 { + status = "disabled"; +}; + +&mcbsp3 { + status = "disabled"; +}; + +&dmic { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index 94a23b39033d..5b7e04fbff50 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts @@ -117,6 +117,15 @@ }; &omap4_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = < + &twl6040_pins + &mcpdm_pins + &dmic_pins + &mcbsp1_pins + &mcbsp2_pins + >; + uart2_pins: pinmux_uart2_pins { pinctrl-single,pins = < 0xd8 0x118 /* uart2_cts.uart2_cts INPUT_PULLUP | MODE0 */ @@ -141,6 +150,50 @@ 0x11e 0 /* uart4_tx.uart4_tx OUTPUT | MODE0 */ >; }; + + twl6040_pins: pinmux_twl6040_pins { + pinctrl-single,pins = < + 0xe0 0x3 /* hdq_sio.gpio_127 OUTPUT | MODE3 */ + 0x160 0x100 /* sys_nirq2.sys_nirq2 INPUT | MODE0 */ + >; + }; + + mcpdm_pins: pinmux_mcpdm_pins { + pinctrl-single,pins = < + 0xc6 0x108 /* abe_pdm_ul_data.abe_pdm_ul_data INPUT PULLDOWN | MODE0 */ + 0xc8 0x108 /* abe_pdm_dl_data.abe_pdm_dl_data INPUT PULLDOWN | MODE0 */ + 0xca 0x118 /* abe_pdm_frame.abe_pdm_frame INPUT PULLUP | MODE0 */ + 0xcc 0x108 /* abe_pdm_lb_clk.abe_pdm_lb_clk INPUT PULLDOWN | MODE0 */ + 0xce 0x108 /* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */ + >; + }; + + dmic_pins: pinmux_dmic_pins { + pinctrl-single,pins = < + 0xd0 0 /* abe_dmic_clk1.abe_dmic_clk1 OUTPUT | MODE0 */ + 0xd2 0x100 /* abe_dmic_din1.abe_dmic_din1 INPUT | MODE0 */ + 0xd4 0x100 /* abe_dmic_din2.abe_dmic_din2 INPUT | MODE0 */ + 0xd6 0x100 /* abe_dmic_din3.abe_dmic_din3 INPUT | MODE0 */ + >; + }; + + mcbsp1_pins: pinmux_mcbsp1_pins { + pinctrl-single,pins = < + 0xbe 0x100 /* abe_mcbsp1_clkx.abe_mcbsp1_clkx INPUT | MODE0 */ + 0xc0 0x108 /* abe_mcbsp1_dr.abe_mcbsp1_dr INPUT PULLDOWN | MODE0 */ + 0xc2 0x8 /* abe_mcbsp1_dx.abe_mcbsp1_dx OUTPUT PULLDOWN | MODE0 */ + 0xc4 0x100 /* abe_mcbsp1_fsx.abe_mcbsp1_fsx INPUT | MODE0 */ + >; + }; + + mcbsp2_pins: pinmux_mcbsp2_pins { + pinctrl-single,pins = < + 0xb6 0x100 /* abe_mcbsp2_clkx.abe_mcbsp2_clkx INPUT | MODE0 */ + 0xb8 0x108 /* abe_mcbsp2_dr.abe_mcbsp2_dr INPUT PULLDOWN | MODE0 */ + 0xba 0x8 /* abe_mcbsp2_dx.abe_mcbsp2_dx OUTPUT PULLDOWN | MODE0 */ + 0xbc 0x100 /* abe_mcbsp2_fsx.abe_mcbsp2_fsx INPUT | MODE0 */ + >; + }; }; &i2c1 { @@ -349,3 +402,7 @@ pinctrl-names = "default"; pinctrl-0 = <&uart4_pins>; }; + +&mcbsp3 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts index 9c41a3f311aa..c663eba73168 100644 --- a/arch/arm/boot/dts/omap5-evm.dts +++ b/arch/arm/boot/dts/omap5-evm.dts @@ -27,6 +27,60 @@ }; +&omap5_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = < + &twl6040_pins + &mcpdm_pins + &dmic_pins + &mcbsp1_pins + &mcbsp2_pins + >; + + twl6040_pins: pinmux_twl6040_pins { + pinctrl-single,pins = < + 0x18a 0x6 /* perslimbus2_clock.gpio5_145 OUTPUT | MODE6 */ + >; + }; + + mcpdm_pins: pinmux_mcpdm_pins { + pinctrl-single,pins = < + 0x142 0x108 /* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */ + 0x15c 0x108 /* abemcpdm_ul_data.abemcpdm_ul_data INPUT PULLDOWN | MODE0 */ + 0x15e 0x108 /* abemcpdm_dl_data.abemcpdm_dl_data INPUT PULLDOWN | MODE0 */ + 0x160 0x118 /* abemcpdm_frame.abemcpdm_frame INPUT PULLUP | MODE0 */ + 0x162 0x108 /* abemcpdm_lb_clk.abemcpdm_lb_clk INPUT PULLDOWN | MODE0 */ + >; + }; + + dmic_pins: pinmux_dmic_pins { + pinctrl-single,pins = < + 0x144 0x100 /* abedmic_din1.abedmic_din1 INPUT | MODE0 */ + 0x146 0x100 /* abedmic_din2.abedmic_din2 INPUT | MODE0 */ + 0x148 0x100 /* abedmic_din3.abedmic_din3 INPUT | MODE0 */ + 0x14a 0 /* abedmic_clk1.abedmic_clk1 OUTPUT | MODE0 */ + >; + }; + + mcbsp1_pins: pinmux_mcbsp1_pins { + pinctrl-single,pins = < + 0x14c 0x101 /* abedmic_clk2.abemcbsp1_fsx INPUT | MODE1 */ + 0x14e 0x9 /* abedmic_clk3.abemcbsp1_dx OUTPUT PULLDOWN | MODE1 */ + 0x150 0x101 /* abeslimbus1_clock.abemcbsp1_clkx INPUT | MODE0 */ + 0x152 0x109 /* abeslimbus1_data.abemcbsp1_dr INPUT PULLDOWN | MODE1 */ + >; + }; + + mcbsp2_pins: pinmux_mcbsp2_pins { + pinctrl-single,pins = < + 0x154 0x108 /* abemcbsp2_dr.abemcbsp2_dr INPUT PULLDOWN | MODE0 */ + 0x156 0x8 /* abemcbsp2_dx.abemcbsp2_dx OUTPUT PULLDOWN | MODE0 */ + 0x158 0x100 /* abemcbsp2_fsx.abemcbsp2_fsx INPUT | MODE0 */ + 0x15a 0x100 /* abemcbsp2_clkx.abemcbsp2_clkx INPUT | MODE0 */ + >; + }; +}; + &mmc1 { vmmc-supply = <&vmmcsd_fixed>; bus-width = <4>; @@ -82,3 +136,7 @@ 0x020700d9>; /* SEARCH */ linux,input-no-autorepeat; }; + +&mcbsp3 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 5db33f481a33..42c78beb4fdc 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -77,6 +77,23 @@ ranges; ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; + omap5_pmx_core: pinmux@4a002840 { + compatible = "ti,omap4-padconf", "pinctrl-single"; + reg = <0x4a002840 0x01b6>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0x7fff>; + }; + omap5_pmx_wkup: pinmux@4ae0c840 { + compatible = "ti,omap4-padconf", "pinctrl-single"; + reg = <0x4ae0c840 0x0038>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0x7fff>; + }; + gic: interrupt-controller@48211000 { compatible = "arm,cortex-a15-gic"; interrupt-controller; diff --git a/arch/arm/boot/dts/pxa910-dkb.dts b/arch/arm/boot/dts/pxa910-dkb.dts index e92be5a474e7..595492aa5053 100644 --- a/arch/arm/boot/dts/pxa910-dkb.dts +++ b/arch/arm/boot/dts/pxa910-dkb.dts @@ -29,6 +29,143 @@ }; twsi1: i2c@d4011000 { status = "okay"; + + pmic: 88pm860x@34 { + compatible = "marvell,88pm860x"; + reg = <0x34>; + interrupts = <4>; + interrupt-parent = <&intc>; + interrupt-controller; + #interrupt-cells = <1>; + + marvell,88pm860x-irq-read-clr; + marvell,88pm860x-slave-addr = <0x11>; + + regulators { + BUCK1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + BUCK2 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + BUCK3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + LDO1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <2800000>; + regulator-boot-on; + regulator-always-on; + }; + LDO2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + LDO3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + LDO4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + LDO5 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + LDO6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + LDO7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-boot-on; + regulator-always-on; + }; + LDO8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-boot-on; + regulator-always-on; + }; + LDO9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + LDO10 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + LDO12 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + LDO13 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + LDO14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + rtc { + marvell,88pm860x-vrtc = <1>; + }; + touch { + marvell,88pm860x-gpadc-prebias = <1>; + marvell,88pm860x-gpadc-slot-cycle = <1>; + marvell,88pm860x-tsi-prebias = <6>; + marvell,88pm860x-pen-prebias = <16>; + marvell,88pm860x-pen-prechg = <2>; + marvell,88pm860x-resistor-X = <300>; + }; + backlights { + backlight-0 { + marvell,88pm860x-iset = <4>; + marvell,88pm860x-pwm = <3>; + }; + backlight-2 { + }; + }; + leds { + led0-red { + marvell,88pm860x-iset = <12>; + }; + led0-green { + marvell,88pm860x-iset = <12>; + }; + led0-blue { + marvell,88pm860x-iset = <12>; + }; + }; + }; }; rtc: rtc@d4010000 { status = "okay"; diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/pxa910.dtsi index a3be44d86bcd..825aaca33034 100644 --- a/arch/arm/boot/dts/pxa910.dtsi +++ b/arch/arm/boot/dts/pxa910.dtsi @@ -120,6 +120,8 @@ twsi1: i2c@d4011000 { compatible = "mrvl,mmp-twsi"; + #address-cells = <1>; + #size-cells = <0>; reg = <0xd4011000 0x1000>; interrupts = <7>; mrvl,i2c-fast-mode; @@ -128,6 +130,8 @@ twsi2: i2c@d4037000 { compatible = "mrvl,mmp-twsi"; + #address-cells = <1>; + #size-cells = <0>; reg = <0xd4037000 0x1000>; interrupts = <54>; status = "disabled"; diff --git a/arch/arm/boot/dts/spear300-evb.dts b/arch/arm/boot/dts/spear300-evb.dts index d71b8d581e3d..1e7c7a8e2123 100644 --- a/arch/arm/boot/dts/spear300-evb.dts +++ b/arch/arm/boot/dts/spear300-evb.dts @@ -80,8 +80,7 @@ }; sdhci@70000000 { - int-gpio = <&gpio1 0 0>; - power-gpio = <&gpio1 2 1>; + cd-gpios = <&gpio1 0 0>; status = "okay"; }; diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts index e4e912f95024..082328bd64ab 100644 --- a/arch/arm/boot/dts/spear320-evb.dts +++ b/arch/arm/boot/dts/spear320-evb.dts @@ -103,8 +103,6 @@ }; sdhci@70000000 { - power-gpio = <&gpio0 2 1>; - power_always_enb; status = "okay"; }; diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index e60dc7124e92..f0ba901676ac 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -539,7 +539,7 @@ nvidia,invert-interrupt; }; - memory-controller@0x7000f400 { + memory-controller@7000f400 { emc-table@190000 { reg = <190000>; compatible = "nvidia,tegra20-emc-table"; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 67a6cd910b96..f3a09d0d45bc 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -170,7 +170,7 @@ reg = <0x7000e400 0x400>; }; - memory-controller@0x7000f000 { + memory-controller@7000f000 { compatible = "nvidia,tegra20-mc"; reg = <0x7000f000 0x024 0x7000f03c 0x3c4>; @@ -183,7 +183,7 @@ 0x58000000 0x02000000>; /* GART aperture */ }; - memory-controller@0x7000f400 { + memory-controller@7000f400 { compatible = "nvidia,tegra20-emc"; reg = <0x7000f400 0x200>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi index b459691655ab..330f833ac3b0 100644 --- a/arch/arm/boot/dts/wm8505.dtsi +++ b/arch/arm/boot/dts/wm8505.dtsi @@ -71,13 +71,13 @@ ehci@d8007100 { compatible = "via,vt8500-ehci"; reg = <0xd8007100 0x200>; - interrupts = <43>; + interrupts = <1>; }; uhci@d8007300 { compatible = "platform-uhci"; reg = <0xd8007300 0x200>; - interrupts = <43>; + interrupts = <0>; }; fb@d8050800 { diff --git a/arch/arm/boot/dts/xenvm-4.2.dts b/arch/arm/boot/dts/xenvm-4.2.dts new file mode 100644 index 000000000000..ec3f9528e180 --- /dev/null +++ b/arch/arm/boot/dts/xenvm-4.2.dts @@ -0,0 +1,68 @@ +/* + * Xen Virtual Machine for unprivileged guests + * + * Based on ARM Ltd. Versatile Express CoreTile Express (single CPU) + * Cortex-A15 MPCore (V2P-CA15) + * + */ + +/dts-v1/; + +/ { + model = "XENVM-4.2"; + compatible = "xen,xenvm-4.2", "xen,xenvm"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { + /* this field is going to be adjusted by the hypervisor */ + bootargs = "console=hvc0 root=/dev/xvda"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* this field is going to be adjusted by the hypervisor */ + reg = <0 0x80000000 0 0x08000000>; + }; + + gic: interrupt-controller@2c001000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0x2c001000 0 0x1000>, + <0 0x2c002000 0 0x100>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + }; + + hypervisor { + compatible = "xen,xen-4.2", "xen,xen"; + /* this field is going to be adjusted by the hypervisor */ + reg = <0 0xb0000000 0 0x20000>; + /* this field is going to be adjusted by the hypervisor */ + interrupts = <1 15 0xf08>; + }; + + motherboard { + arm,v2m-memory-map = "rs1"; + }; +}; diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig index 283fa1d804f4..45ceeb0e93e0 100644 --- a/arch/arm/common/Kconfig +++ b/arch/arm/common/Kconfig @@ -1,15 +1,15 @@ config ARM_GIC + bool select IRQ_DOMAIN select MULTI_IRQ_HANDLER - bool config GIC_NON_BANKED bool config ARM_VIC + bool select IRQ_DOMAIN select MULTI_IRQ_HANDLER - bool config ARM_VIC_NR int diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c index c4110d1b1f2d..001f4913799c 100644 --- a/arch/arm/common/it8152.c +++ b/arch/arm/common/it8152.c @@ -284,11 +284,17 @@ int dma_set_coherent_mask(struct device *dev, u64 mask) int __init it8152_pci_setup(int nr, struct pci_sys_data *sys) { - it8152_io.start = IT8152_IO_BASE + 0x12000; - it8152_io.end = IT8152_IO_BASE + 0x12000 + 0x100000; + /* + * FIXME: use pci_ioremap_io to remap the IO space here and + * move over to the generic io.h implementation. + * This requires solving the same problem for PXA PCMCIA + * support. + */ + it8152_io.start = (unsigned long)IT8152_IO_BASE + 0x12000; + it8152_io.end = (unsigned long)IT8152_IO_BASE + 0x12000 + 0x100000; sys->mem_offset = 0x10000000; - sys->io_offset = IT8152_IO_BASE; + sys->io_offset = (unsigned long)IT8152_IO_BASE; if (request_resource(&ioport_resource, &it8152_io)) { printk(KERN_ERR "PCI: unable to allocate IO region\n"); diff --git a/arch/arm/configs/cam60_defconfig b/arch/arm/configs/cam60_defconfig index cedc92ef88ab..14579711d8fc 100644 --- a/arch/arm/configs/cam60_defconfig +++ b/arch/arm/configs/cam60_defconfig @@ -49,7 +49,6 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y CONFIG_MTD_PLATRAM=m CONFIG_MTD_DATAFLASH=y CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_VERIFY_WRITE=y CONFIG_MTD_NAND_ATMEL=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y diff --git a/arch/arm/configs/corgi_defconfig b/arch/arm/configs/corgi_defconfig index e53c47563845..4b8a25d9e686 100644 --- a/arch/arm/configs/corgi_defconfig +++ b/arch/arm/configs/corgi_defconfig @@ -97,7 +97,6 @@ CONFIG_MTD_BLOCK=y CONFIG_MTD_ROM=y CONFIG_MTD_COMPLEX_MAPPINGS=y CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_VERIFY_WRITE=y CONFIG_MTD_NAND_SHARPSL=y CONFIG_BLK_DEV_LOOP=y CONFIG_IDE=y diff --git a/arch/arm/configs/ep93xx_defconfig b/arch/arm/configs/ep93xx_defconfig index 8e97b2f7ceec..806005a4c4c1 100644 --- a/arch/arm/configs/ep93xx_defconfig +++ b/arch/arm/configs/ep93xx_defconfig @@ -61,7 +61,6 @@ CONFIG_MTD_CFI_STAA=y CONFIG_MTD_ROM=y CONFIG_MTD_PHYSMAP=y CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_VERIFY_WRITE=y CONFIG_BLK_DEV_NBD=y CONFIG_EEPROM_LEGACY=y CONFIG_SCSI=y diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 565132d02105..394ded624e37 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -40,7 +40,6 @@ CONFIG_VMSPLIT_2G=y CONFIG_PREEMPT_VOLUNTARY=y CONFIG_AEABI=y # CONFIG_OABI_COMPAT is not set -CONFIG_DEFAULT_MMAP_MIN_ADDR=32768 CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" CONFIG_VFP=y CONFIG_NEON=y @@ -140,6 +139,7 @@ CONFIG_I2C_IMX=y CONFIG_SPI=y CONFIG_SPI_IMX=y CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_MC9S08DZ60=y # CONFIG_HWMON is not set CONFIG_WATCHDOG=y CONFIG_IMX2_WDT=y @@ -156,6 +156,7 @@ CONFIG_SOC_CAMERA=y CONFIG_SOC_CAMERA_OV2640=y CONFIG_VIDEO_MX3=y CONFIG_FB=y +CONFIG_LCD_PLATFORM=y CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_L4F00242T03=y @@ -177,6 +178,9 @@ CONFIG_SND_SOC_IMX_MC13783=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_MXC=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_MXS_PHY=y CONFIG_USB_STORAGE=y CONFIG_MMC=y CONFIG_MMC_SDHCI=y diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig index aeb3af541fed..74eee0c78f28 100644 --- a/arch/arm/configs/kirkwood_defconfig +++ b/arch/arm/configs/kirkwood_defconfig @@ -1,5 +1,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y CONFIG_LOG_BUF_SHIFT=19 CONFIG_PROFILING=y CONFIG_OPROFILE=y @@ -15,9 +17,19 @@ CONFIG_MACH_MV88F6281GTW_GE=y CONFIG_MACH_SHEEVAPLUG=y CONFIG_MACH_ESATA_SHEEVAPLUG=y CONFIG_MACH_GURUPLUG=y -CONFIG_MACH_DOCKSTAR=y +CONFIG_MACH_DREAMPLUG_DT=y +CONFIG_MACH_ICONNECT_DT=y +CONFIG_MACH_DLINK_KIRKWOOD_DT=y +CONFIG_MACH_IB62X0_DT=y +CONFIG_MACH_TS219_DT=y +CONFIG_MACH_DOCKSTAR_DT=y +CONFIG_MACH_GOFLEXNET_DT=y +CONFIG_MACH_LSXL_DT=y +CONFIG_MACH_IOMEGA_IX2_200_DT=y +CONFIG_MACH_KM_KIRKWOOD_DT=y CONFIG_MACH_TS219=y CONFIG_MACH_TS41X=y +CONFIG_MACH_DOCKSTAR=y CONFIG_MACH_OPENRD_BASE=y CONFIG_MACH_OPENRD_CLIENT=y CONFIG_MACH_OPENRD_ULTIMATE=y @@ -29,8 +41,6 @@ CONFIG_MACH_NET2BIG_V2=y CONFIG_MACH_NET5BIG_V2=y CONFIG_MACH_T5325=y # CONFIG_CPU_FEROCEON_OLD_ID is not set -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y CONFIG_PREEMPT=y CONFIG_AEABI=y # CONFIG_OABI_COMPAT is not set @@ -47,13 +57,11 @@ CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y # CONFIG_IPV6 is not set CONFIG_NET_DSA=y -CONFIG_NET_DSA_MV88E6123_61_65=y CONFIG_NET_PKTGEN=m CONFIG_CFG80211=y CONFIG_MAC80211=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y @@ -69,7 +77,6 @@ CONFIG_MTD_M25P80=y CONFIG_MTD_NAND=y CONFIG_MTD_NAND_ORION=y CONFIG_BLK_DEV_LOOP=y -# CONFIG_MISC_DEVICES is not set # CONFIG_SCSI_PROC_FS is not set CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SR=m @@ -78,22 +85,21 @@ CONFIG_ATA=y CONFIG_SATA_AHCI=y CONFIG_SATA_MV=y CONFIG_NETDEVICES=y -CONFIG_MARVELL_PHY=y -CONFIG_NET_ETHERNET=y CONFIG_MII=y -CONFIG_NET_PCI=y +CONFIG_NET_DSA_MV88E6123_61_65=y CONFIG_MV643XX_ETH=y -# CONFIG_NETDEV_10000 is not set +CONFIG_MARVELL_PHY=y CONFIG_LIBERTAS=y CONFIG_LIBERTAS_SDIO=y CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_GPIO=y # CONFIG_INPUT_MOUSE is not set +CONFIG_LEGACY_PTY_COUNT=16 # CONFIG_DEVKMEM is not set CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_RUNTIME_UARTS=2 -CONFIG_LEGACY_PTY_COUNT=16 +CONFIG_SERIAL_OF_PLATFORM=y # CONFIG_HW_RANDOM is not set CONFIG_I2C=y # CONFIG_I2C_COMPAT is not set @@ -103,7 +109,8 @@ CONFIG_SPI=y CONFIG_SPI_ORION=y CONFIG_GPIO_SYSFS=y # CONFIG_HWMON is not set -# CONFIG_VGA_CONSOLE is not set +CONFIG_WATCHDOG=y +CONFIG_ORION_WATCHDOG=y CONFIG_HID_DRAGONRISE=y CONFIG_HID_GYRATION=y CONFIG_HID_TWINHAN=y @@ -119,10 +126,8 @@ CONFIG_HID_TOPSEED=y CONFIG_HID_THRUSTMASTER=y CONFIG_HID_ZEROPLUS=y CONFIG_USB=y -CONFIG_USB_DEVICEFS=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y -CONFIG_USB_EHCI_TT_NEWSCHED=y CONFIG_USB_PRINTER=m CONFIG_USB_STORAGE=y CONFIG_USB_STORAGE_DATAFAB=y @@ -148,7 +153,6 @@ CONFIG_MV_XOR=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y # CONFIG_EXT3_FS_XATTR is not set -CONFIG_INOTIFY=y CONFIG_ISO9660_FS=m CONFIG_JOLIET=y CONFIG_UDF_FS=m @@ -158,7 +162,6 @@ CONFIG_TMPFS=y CONFIG_JFFS2_FS=y CONFIG_CRAMFS=y CONFIG_NFS_FS=y -CONFIG_NFS_V3=y CONFIG_ROOT_NFS=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_850=y @@ -171,11 +174,8 @@ CONFIG_DEBUG_KERNEL=y # CONFIG_SCHED_DEBUG is not set # CONFIG_DEBUG_PREEMPT is not set CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_SYSCTL_SYSCALL_CHECK=y # CONFIG_FTRACE is not set CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y CONFIG_DEBUG_LL=y CONFIG_CRYPTO_CBC=m CONFIG_CRYPTO_PCBC=m diff --git a/arch/arm/configs/lpc32xx_defconfig b/arch/arm/configs/lpc32xx_defconfig index e42a0e3d4c3a..92386b20bd09 100644 --- a/arch/arm/configs/lpc32xx_defconfig +++ b/arch/arm/configs/lpc32xx_defconfig @@ -133,7 +133,6 @@ CONFIG_SND_DEBUG_VERBOSE=y # CONFIG_SND_ARM is not set # CONFIG_SND_SPI is not set CONFIG_SND_SOC=y -# CONFIG_HID_SUPPORT is not set CONFIG_USB=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_STORAGE=y @@ -149,6 +148,7 @@ CONFIG_LEDS_CLASS=y CONFIG_LEDS_PCA9532=y CONFIG_LEDS_PCA9532_GPIO=y CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PWM=y CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y @@ -161,10 +161,13 @@ CONFIG_RTC_DRV_DS1374=y CONFIG_RTC_DRV_PCF8563=y CONFIG_RTC_DRV_LPC32XX=y CONFIG_DMADEVICES=y +CONFIG_AMBA_PL08X=y CONFIG_STAGING=y CONFIG_LPC32XX_ADC=y -CONFIG_MAX517=y CONFIG_IIO=y +CONFIG_MAX517=y +CONFIG_PWM=y +CONFIG_PWM_LPC32XX=y CONFIG_EXT2_FS=y CONFIG_AUTOFS4_FS=y CONFIG_MSDOS_FS=y diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig index f513acedc10a..53382b6c8bb4 100644 --- a/arch/arm/configs/marzen_defconfig +++ b/arch/arm/configs/marzen_defconfig @@ -1,13 +1,14 @@ # CONFIG_ARM_PATCH_PHYS_VIRT is not set CONFIG_EXPERIMENTAL=y CONFIG_KERNEL_LZMA=y +CONFIG_NO_HZ=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=16 CONFIG_SYSCTL_SYSCALL=y CONFIG_EMBEDDED=y CONFIG_SLAB=y -# CONFIG_BLOCK is not set +# CONFIG_IOSCHED_CFQ is not set CONFIG_ARCH_SHMOBILE=y CONFIG_ARCH_R8A7779=y CONFIG_MACH_MARZEN=y @@ -21,7 +22,6 @@ CONFIG_ARM_ERRATA_458693=y CONFIG_ARM_ERRATA_460075=y CONFIG_ARM_ERRATA_743622=y CONFIG_ARM_ERRATA_754322=y -CONFIG_NO_HZ=y CONFIG_SMP=y # CONFIG_ARM_CPU_TOPOLOGY is not set CONFIG_AEABI=y @@ -29,13 +29,16 @@ CONFIG_AEABI=y CONFIG_HIGHMEM=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel" +CONFIG_CMDLINE="console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on" CONFIG_CMDLINE_FORCE=y CONFIG_KEXEC=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_PM_RUNTIME=y CONFIG_NET=y +CONFIG_UNIX=y CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y # CONFIG_IPV6 is not set # CONFIG_WIRELESS is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" @@ -71,16 +74,18 @@ CONFIG_GPIO_SYSFS=y CONFIG_THERMAL=y CONFIG_RCAR_THERMAL=y CONFIG_SSB=y -# CONFIG_HID_SUPPORT is not set # CONFIG_USB_SUPPORT is not set +CONFIG_MMC=y +CONFIG_MMC_SDHI=y CONFIG_UIO=y CONFIG_UIO_PDRV_GENIRQ=y # CONFIG_IOMMU_SUPPORT is not set -# CONFIG_FILE_LOCKING is not set # CONFIG_DNOTIFY is not set # CONFIG_INOTIFY_USER is not set CONFIG_TMPFS=y # CONFIG_MISC_FILESYSTEMS is not set +CONFIG_NFS_FS=y +CONFIG_ROOT_NFS=y CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_INFO=y CONFIG_DEBUG_INFO_REDUCED=y diff --git a/arch/arm/configs/mini2440_defconfig b/arch/arm/configs/mini2440_defconfig index 082175c54e7c..00630e6af45c 100644 --- a/arch/arm/configs/mini2440_defconfig +++ b/arch/arm/configs/mini2440_defconfig @@ -102,7 +102,6 @@ CONFIG_MTD_CFI_STAA=y CONFIG_MTD_RAM=y CONFIG_MTD_ROM=y CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_VERIFY_WRITE=y CONFIG_MTD_NAND_S3C2410=y CONFIG_MTD_NAND_PLATFORM=y CONFIG_MTD_LPDDR=y diff --git a/arch/arm/configs/mv78xx0_defconfig b/arch/arm/configs/mv78xx0_defconfig index 7305ebddb510..1f08219c1b3c 100644 --- a/arch/arm/configs/mv78xx0_defconfig +++ b/arch/arm/configs/mv78xx0_defconfig @@ -49,7 +49,6 @@ CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_PHYSMAP=y CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_VERIFY_WRITE=y CONFIG_MTD_NAND_ORION=y CONFIG_BLK_DEV_LOOP=y # CONFIG_SCSI_PROC_FS is not set diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig index 2e86b31c33cf..3458752c4bb2 100644 --- a/arch/arm/configs/mvebu_defconfig +++ b/arch/arm/configs/mvebu_defconfig @@ -1,6 +1,6 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y -CONFIG_NO_HZ=y +CONFIG_IRQ_DOMAIN_DEBUG=y CONFIG_HIGH_RES_TIMERS=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y @@ -9,10 +9,12 @@ CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_ARCH_MVEBU=y -CONFIG_MACH_ARMADA_370_XP=y +CONFIG_MACH_ARMADA_370=y +CONFIG_MACH_ARMADA_XP=y +# CONFIG_CACHE_L2X0 is not set CONFIG_AEABI=y CONFIG_HIGHMEM=y -CONFIG_USE_OF=y +# CONFIG_COMPACTION is not set CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_ARM_APPENDED_DTB=y @@ -21,6 +23,10 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y +# CONFIG_USB_SUPPORT is not set +# CONFIG_IOMMU_SUPPORT is not set CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y # CONFIG_EXT3_FS_XATTR is not set diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig index 36d60dda310c..048aaca60814 100644 --- a/arch/arm/configs/mxs_defconfig +++ b/arch/arm/configs/mxs_defconfig @@ -53,6 +53,9 @@ CONFIG_DEVTMPFS=y # CONFIG_FIRMWARE_IN_KERNEL is not set # CONFIG_BLK_DEV is not set CONFIG_MTD=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_DATAFLASH=y +CONFIG_MTD_M25P80 CONFIG_MTD_NAND=y CONFIG_MTD_NAND_GPMI_NAND=y CONFIG_NETDEVICES=y @@ -82,13 +85,13 @@ CONFIG_I2C_CHARDEV=y CONFIG_I2C_MXS=y CONFIG_SPI=y CONFIG_SPI_GPIO=m +CONFIG_SPI_MXS=y CONFIG_DEBUG_GPIO=y CONFIG_GPIO_SYSFS=y # CONFIG_HWMON is not set # CONFIG_MFD_SUPPORT is not set CONFIG_DISPLAY_SUPPORT=m # CONFIG_HID_SUPPORT is not set -# CONFIG_USB_SUPPORT is not set CONFIG_SOUND=y CONFIG_SND=y CONFIG_SND_TIMER=y @@ -103,14 +106,45 @@ CONFIG_SND_SOC_I2C_AND_SPI=y CONFIG_SND_SOC_SGTL5000=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_FB=y +CONFIG_FB_MXS=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FONTS=y +CONFIG_LOGO=y +CONFIG_USB=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_STORAGE=y +CONFIG_USB_MXS_PHY=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y CONFIG_MMC=y CONFIG_MMC_MXS=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_ONESHOT=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_GPIO=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_DS1307=m CONFIG_RTC_DRV_STMP=y CONFIG_DMADEVICES=y CONFIG_MXS_DMA=y +CONFIG_STAGING=y +CONFIG_MXS_LRADC=y +CONFIG_IIO_SYSFS_TRIGGER=y CONFIG_COMMON_CLK_DEBUG=y +CONFIG_IIO=y +CONFIG_PWM=y +CONFIG_PWM_MXS=y CONFIG_EXT3_FS=y # CONFIG_DNOTIFY is not set CONFIG_FSCACHE=m diff --git a/arch/arm/configs/nhk8815_defconfig b/arch/arm/configs/nhk8815_defconfig index bf123c5384d4..240b25eea565 100644 --- a/arch/arm/configs/nhk8815_defconfig +++ b/arch/arm/configs/nhk8815_defconfig @@ -57,7 +57,6 @@ CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_NAND=y CONFIG_MTD_NAND_ECC_SMC=y -CONFIG_MTD_NAND_VERIFY_WRITE=y CONFIG_MTD_NAND_NOMADIK=y CONFIG_MTD_ONENAND=y CONFIG_MTD_ONENAND_VERIFY_WRITE=y diff --git a/arch/arm/configs/orion5x_defconfig b/arch/arm/configs/orion5x_defconfig index a288d7033950..cd5e6ba9a54d 100644 --- a/arch/arm/configs/orion5x_defconfig +++ b/arch/arm/configs/orion5x_defconfig @@ -72,7 +72,6 @@ CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_PHYSMAP=y CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_VERIFY_WRITE=y CONFIG_MTD_NAND_PLATFORM=y CONFIG_MTD_NAND_ORION=y CONFIG_BLK_DEV_LOOP=y diff --git a/arch/arm/configs/pxa3xx_defconfig b/arch/arm/configs/pxa3xx_defconfig index 1677a0607ca9..60e313834b3f 100644 --- a/arch/arm/configs/pxa3xx_defconfig +++ b/arch/arm/configs/pxa3xx_defconfig @@ -36,7 +36,6 @@ CONFIG_MTD_CONCAT=y CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_VERIFY_WRITE=y CONFIG_MTD_NAND_PXA3xx=y CONFIG_MTD_NAND_PXA3xx_BUILTIN=y CONFIG_MTD_ONENAND=y diff --git a/arch/arm/configs/s3c6400_defconfig b/arch/arm/configs/s3c6400_defconfig index ba6a515086b5..3a186d653dac 100644 --- a/arch/arm/configs/s3c6400_defconfig +++ b/arch/arm/configs/s3c6400_defconfig @@ -9,11 +9,14 @@ CONFIG_ARCH_S3C64XX=y CONFIG_S3C_BOOT_ERROR_RESET=y CONFIG_MACH_SMDK6400=y CONFIG_MACH_ANW6410=y +CONFIG_MACH_MINI6410=y +CONFIG_MACH_REAL6410=y CONFIG_MACH_SMDK6410=y CONFIG_MACH_NCP=y CONFIG_MACH_HMT=y CONFIG_MACH_SMARTQ5=y CONFIG_MACH_SMARTQ7=y +CONFIG_MACH_WLF_CRAGG_6410=y CONFIG_CPU_32v6K=y CONFIG_AEABI=y CONFIG_CMDLINE="console=ttySAC0,115200 root=/dev/ram init=/linuxrc initrd=0x51000000,6M ramdisk_size=6144" diff --git a/arch/arm/configs/spitz_defconfig b/arch/arm/configs/spitz_defconfig index 70158273c6dd..df77931a4326 100644 --- a/arch/arm/configs/spitz_defconfig +++ b/arch/arm/configs/spitz_defconfig @@ -94,7 +94,6 @@ CONFIG_MTD_BLOCK=y CONFIG_MTD_ROM=y CONFIG_MTD_COMPLEX_MAPPINGS=y CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_VERIFY_WRITE=y CONFIG_MTD_NAND_SHARPSL=y CONFIG_BLK_DEV_LOOP=y CONFIG_IDE=y diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig index 0d6bb738c6de..e2184f6c20b3 100644 --- a/arch/arm/configs/tegra_defconfig +++ b/arch/arm/configs/tegra_defconfig @@ -24,11 +24,11 @@ CONFIG_EFI_PARTITION=y # CONFIG_IOSCHED_DEADLINE is not set # CONFIG_IOSCHED_CFQ is not set CONFIG_ARCH_TEGRA=y +CONFIG_GPIO_PCA953X=y CONFIG_ARCH_TEGRA_2x_SOC=y CONFIG_ARCH_TEGRA_3x_SOC=y -CONFIG_MACH_HARMONY=y -CONFIG_MACH_PAZ00=y -CONFIG_MACH_TRIMSLICE=y +CONFIG_TEGRA_PCI=y +CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA=y CONFIG_TEGRA_EMC_SCALING_ENABLE=y CONFIG_SMP=y CONFIG_PREEMPT=y @@ -67,7 +67,18 @@ CONFIG_INET6_IPCOMP=y CONFIG_IPV6_MIP6=y CONFIG_IPV6_TUNNEL=y CONFIG_IPV6_MULTIPLE_TABLES=y -# CONFIG_WIRELESS is not set +CONFIG_BT=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_BNEP=y +CONFIG_BT_HIDP=y +CONFIG_BT_HCIBTUSB=m +CONFIG_CFG80211=y +CONFIG_MAC80211=y +CONFIG_RFKILL=y +CONFIG_RFKILL_INPUT=y +CONFIG_RFKILL_GPIO=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y # CONFIG_FIRMWARE_IN_KERNEL is not set CONFIG_PROC_DEVICETREE=y CONFIG_BLK_DEV_LOOP=y @@ -87,7 +98,8 @@ CONFIG_USB_PEGASUS=y CONFIG_USB_USBNET=y CONFIG_USB_NET_SMSC75XX=y CONFIG_USB_NET_SMSC95XX=y -# CONFIG_WLAN is not set +CONFIG_RT2X00=y +CONFIG_RT2800USB=m CONFIG_INPUT_EVDEV=y CONFIG_INPUT_MISC=y CONFIG_INPUT_MPU3050=y @@ -105,25 +117,31 @@ CONFIG_I2C_MUX_PINCTRL=y CONFIG_I2C_TEGRA=y CONFIG_SPI=y CONFIG_SPI_TEGRA=y -CONFIG_GPIO_TPS65910=y +CONFIG_GPIO_PCA953X_IRQ=y CONFIG_GPIO_TPS6586X=y +CONFIG_GPIO_TPS65910=y CONFIG_POWER_SUPPLY=y CONFIG_BATTERY_SBS=y CONFIG_SENSORS_LM90=y CONFIG_MFD_TPS6586X=y CONFIG_MFD_TPS65910=y +CONFIG_MFD_MAX8907=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_VIRTUAL_CONSUMER=y CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_MAX8907=y CONFIG_REGULATOR_TPS62360=y CONFIG_REGULATOR_TPS6586X=y CONFIG_REGULATOR_TPS65910=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=m CONFIG_SOUND=y CONFIG_SND=y # CONFIG_SND_SUPPORT_OLD_API is not set # CONFIG_SND_DRIVERS is not set -# CONFIG_SND_PCI is not set # CONFIG_SND_ARM is not set # CONFIG_SND_SPI is not set # CONFIG_SND_USB is not set @@ -136,13 +154,25 @@ CONFIG_SND_SOC_TEGRA_ALC5632=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_TEGRA=y +CONFIG_USB_ACM=y +CONFIG_USB_WDM=y CONFIG_USB_STORAGE=y CONFIG_MMC=y CONFIG_MMC_BLOCK_MINORS=16 CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_TEGRA=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_GPIO=y CONFIG_RTC_CLASS=y +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +CONFIG_RTC_DRV_MAX8907=y +CONFIG_RTC_DRV_TPS65910=y CONFIG_RTC_DRV_EM3027=y CONFIG_RTC_DRV_TEGRA=y CONFIG_DMADEVICES=y @@ -154,10 +184,14 @@ CONFIG_SENSORS_AK8975=y CONFIG_MFD_NVEC=y CONFIG_KEYBOARD_NVEC=y CONFIG_SERIO_NVEC_PS2=y +CONFIG_NVEC_POWER=y +CONFIG_NVEC_PAZ00=y CONFIG_TEGRA_IOMMU_GART=y CONFIG_TEGRA_IOMMU_SMMU=y CONFIG_MEMORY=y CONFIG_IIO=y +CONFIG_PWM=y +CONFIG_PWM_TEGRA=y CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y @@ -170,6 +204,7 @@ CONFIG_EXT4_FS=y # CONFIG_DNOTIFY is not set CONFIG_VFAT_FS=y CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y CONFIG_NFS_FS=y CONFIG_ROOT_NFS=y CONFIG_NLS_CODEPAGE_437=y @@ -188,8 +223,6 @@ CONFIG_DEBUG_VM=y CONFIG_DEBUG_SG=y CONFIG_DEBUG_LL=y CONFIG_EARLY_PRINTK=y -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_ARC4=y CONFIG_CRYPTO_TWOFISH=y # CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_DEV_TEGRA_AES=y diff --git a/arch/arm/configs/versatile_defconfig b/arch/arm/configs/versatile_defconfig index cdd4d2bd3962..2ba9e63d0f17 100644 --- a/arch/arm/configs/versatile_defconfig +++ b/arch/arm/configs/versatile_defconfig @@ -1,3 +1,4 @@ +CONFIG_ARCH_VERSATILE=y CONFIG_EXPERIMENTAL=y # CONFIG_LOCALVERSION_AUTO is not set CONFIG_SYSVIPC=y diff --git a/arch/arm/include/asm/Kbuild b/arch/arm/include/asm/Kbuild index 960abceb8e14..f70ae175a3d6 100644 --- a/arch/arm/include/asm/Kbuild +++ b/arch/arm/include/asm/Kbuild @@ -1,20 +1,35 @@ -include include/asm-generic/Kbuild.asm -header-y += hwcap.h generic-y += auxvec.h generic-y += bitsperlong.h generic-y += cputime.h +generic-y += current.h generic-y += emergency-restart.h generic-y += errno.h +generic-y += exec.h generic-y += ioctl.h +generic-y += ipcbuf.h generic-y += irq_regs.h generic-y += kdebug.h generic-y += local.h generic-y += local64.h +generic-y += msgbuf.h +generic-y += param.h +generic-y += parport.h generic-y += percpu.h generic-y += poll.h generic-y += resource.h generic-y += sections.h +generic-y += segment.h +generic-y += sembuf.h +generic-y += serial.h +generic-y += shmbuf.h generic-y += siginfo.h generic-y += sizes.h +generic-y += socket.h +generic-y += sockios.h +generic-y += termbits.h +generic-y += termios.h +generic-y += timex.h +generic-y += types.h +generic-y += unaligned.h diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h index 62e75475e57e..d40229d9a1c9 100644 --- a/arch/arm/include/asm/arch_timer.h +++ b/arch/arm/include/asm/arch_timer.h @@ -2,11 +2,12 @@ #define __ASMARM_ARCH_TIMER_H #include <asm/errno.h> +#include <linux/clocksource.h> #ifdef CONFIG_ARM_ARCH_TIMER -#define ARCH_HAS_READ_CURRENT_TIMER int arch_timer_of_register(void); int arch_timer_sched_clock_init(void); +struct timecounter *arch_timer_get_timecounter(void); #else static inline int arch_timer_of_register(void) { @@ -17,6 +18,11 @@ static inline int arch_timer_sched_clock_init(void) { return -ENXIO; } + +static inline struct timecounter *arch_timer_get_timecounter(void) +{ + return NULL; +} #endif #endif diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 5c8b3bf4d825..2ef95813fce0 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -22,6 +22,7 @@ #include <asm/ptrace.h> #include <asm/domain.h> +#include <asm/opcodes-virt.h> #define IOMEM(x) (x) @@ -240,6 +241,34 @@ #endif /* + * Helper macro to enter SVC mode cleanly and mask interrupts. reg is + * a scratch register for the macro to overwrite. + * + * This macro is intended for forcing the CPU into SVC mode at boot time. + * you cannot return to the original mode. + * + * Beware, it also clobers LR. + */ +.macro safe_svcmode_maskall reg:req + mrs \reg , cpsr + mov lr , \reg + and lr , lr , #MODE_MASK + cmp lr , #HYP_MODE + orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT + bic \reg , \reg , #MODE_MASK + orr \reg , \reg , #SVC_MODE +THUMB( orr \reg , \reg , #PSR_T_BIT ) + bne 1f + orr \reg, \reg, #PSR_A_BIT + adr lr, BSYM(2f) + msr spsr_cxsf, \reg + __MSR_ELR_HYP(14) + __ERET +1: msr cpsr_c, \reg +2: +.endm + +/* * STRT/LDRT access macros with ARM and Thumb-2 variants */ #ifdef CONFIG_THUMB2_KERNEL diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h index e4448e16046d..e1489c54cd12 100644 --- a/arch/arm/include/asm/cacheflush.h +++ b/arch/arm/include/asm/cacheflush.h @@ -49,6 +49,13 @@ * * Unconditionally clean and invalidate the entire cache. * + * flush_kern_louis() + * + * Flush data cache levels up to the level of unification + * inner shareable and invalidate the I-cache. + * Only needed from v7 onwards, falls back to flush_cache_all() + * for all other processor versions. + * * flush_user_all() * * Clean and invalidate all user space cache entries @@ -97,6 +104,7 @@ struct cpu_cache_fns { void (*flush_icache_all)(void); void (*flush_kern_all)(void); + void (*flush_kern_louis)(void); void (*flush_user_all)(void); void (*flush_user_range)(unsigned long, unsigned long, unsigned int); @@ -119,6 +127,7 @@ extern struct cpu_cache_fns cpu_cache; #define __cpuc_flush_icache_all cpu_cache.flush_icache_all #define __cpuc_flush_kern_all cpu_cache.flush_kern_all +#define __cpuc_flush_kern_louis cpu_cache.flush_kern_louis #define __cpuc_flush_user_all cpu_cache.flush_user_all #define __cpuc_flush_user_range cpu_cache.flush_user_range #define __cpuc_coherent_kern_range cpu_cache.coherent_kern_range @@ -139,6 +148,7 @@ extern struct cpu_cache_fns cpu_cache; extern void __cpuc_flush_icache_all(void); extern void __cpuc_flush_kern_all(void); +extern void __cpuc_flush_kern_louis(void); extern void __cpuc_flush_user_all(void); extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int); extern void __cpuc_coherent_kern_range(unsigned long, unsigned long); @@ -204,6 +214,11 @@ static inline void __flush_icache_all(void) __flush_icache_preferred(); } +/* + * Flush caches up to Level of Unification Inner Shareable + */ +#define flush_cache_louis() __cpuc_flush_kern_louis() + #define flush_cache_all() __cpuc_flush_kern_all() static inline void vivt_flush_cache_mm(struct mm_struct *mm) diff --git a/arch/arm/include/asm/current.h b/arch/arm/include/asm/current.h deleted file mode 100644 index 75d21e2a3ff7..000000000000 --- a/arch/arm/include/asm/current.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef _ASMARM_CURRENT_H -#define _ASMARM_CURRENT_H - -#include <linux/thread_info.h> - -static inline struct task_struct *get_current(void) __attribute_const__; - -static inline struct task_struct *get_current(void) -{ - return current_thread_info()->task; -} - -#define current (get_current()) - -#endif /* _ASMARM_CURRENT_H */ diff --git a/arch/arm/include/asm/delay.h b/arch/arm/include/asm/delay.h index dc6145120de3..ab98fdd083bd 100644 --- a/arch/arm/include/asm/delay.h +++ b/arch/arm/include/asm/delay.h @@ -15,6 +15,11 @@ #ifndef __ASSEMBLY__ +struct delay_timer { + unsigned long (*read_current_timer)(void); + unsigned long freq; +}; + extern struct arm_delay_ops { void (*delay)(unsigned long); void (*const_udelay)(unsigned long); @@ -56,6 +61,10 @@ extern void __loop_delay(unsigned long loops); extern void __loop_udelay(unsigned long usecs); extern void __loop_const_udelay(unsigned long); +/* Delay-loop timer registration. */ +#define ARCH_HAS_READ_CURRENT_TIMER +extern void register_current_timer_delay(const struct delay_timer *timer); + #endif /* __ASSEMBLY__ */ #endif /* defined(_ARM_DELAY_H) */ diff --git a/arch/arm/include/asm/exec.h b/arch/arm/include/asm/exec.h deleted file mode 100644 index 7c4fbef72b3a..000000000000 --- a/arch/arm/include/asm/exec.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __ASM_ARM_EXEC_H -#define __ASM_ARM_EXEC_H - -#define arch_align_stack(x) (x) - -#endif /* __ASM_ARM_EXEC_H */ diff --git a/arch/arm/include/asm/flat.h b/arch/arm/include/asm/flat.h index 59426a4595c9..e847d23351ed 100644 --- a/arch/arm/include/asm/flat.h +++ b/arch/arm/include/asm/flat.h @@ -8,7 +8,7 @@ #define flat_argvp_envp_on_stack() 1 #define flat_old_ram_flag(flags) (flags) #define flat_reloc_valid(reloc, size) ((reloc) <= (size)) -#define flat_get_addr_from_rp(rp, relval, flags, persistent) get_unaligned(rp) +#define flat_get_addr_from_rp(rp, relval, flags, persistent) ((void)persistent,get_unaligned(rp)) #define flat_put_addr_at_rp(rp, val, relval) put_unaligned(val,rp) #define flat_get_relocate_addr(rel) (rel) #define flat_set_persistent(relval, p) 0 diff --git a/arch/arm/include/asm/glue-cache.h b/arch/arm/include/asm/glue-cache.h index 7e30874377e6..cca9f15704ed 100644 --- a/arch/arm/include/asm/glue-cache.h +++ b/arch/arm/include/asm/glue-cache.h @@ -110,19 +110,19 @@ #endif #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) -//# ifdef _CACHE +# ifdef _CACHE # define MULTI_CACHE 1 -//# else -//# define _CACHE v6 -//# endif +# else +# define _CACHE v6 +# endif #endif #if defined(CONFIG_CPU_V7) -//# ifdef _CACHE +# ifdef _CACHE # define MULTI_CACHE 1 -//# else -//# define _CACHE v7 -//# endif +# else +# define _CACHE v7 +# endif #endif #if !defined(_CACHE) && !defined(MULTI_CACHE) @@ -132,6 +132,7 @@ #ifndef MULTI_CACHE #define __cpuc_flush_icache_all __glue(_CACHE,_flush_icache_all) #define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all) +#define __cpuc_flush_kern_louis __glue(_CACHE,_flush_kern_cache_louis) #define __cpuc_flush_user_all __glue(_CACHE,_flush_user_cache_all) #define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range) #define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range) diff --git a/arch/arm/include/asm/hardirq.h b/arch/arm/include/asm/hardirq.h index 436e60b2cf7a..2740c2a2df63 100644 --- a/arch/arm/include/asm/hardirq.h +++ b/arch/arm/include/asm/hardirq.h @@ -5,7 +5,7 @@ #include <linux/threads.h> #include <asm/irq.h> -#define NR_IPI 5 +#define NR_IPI 6 typedef struct { unsigned int __softirq_pending; diff --git a/arch/arm/include/asm/hardware/linkup-l1110.h b/arch/arm/include/asm/hardware/linkup-l1110.h deleted file mode 100644 index 7ec91168a576..000000000000 --- a/arch/arm/include/asm/hardware/linkup-l1110.h +++ /dev/null @@ -1,48 +0,0 @@ -/* -* -* Definitions for H3600 Handheld Computer -* -* Copyright 2001 Compaq Computer Corporation. -* -* Use consistent with the GNU GPL is permitted, -* provided that this copyright notice is -* preserved in its entirety in all copies and derived works. -* -* COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, -* AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS -* FITNESS FOR ANY PARTICULAR PURPOSE. -* -* Author: Jamey Hicks. -* -*/ - -/* LinkUp Systems PCCard/CompactFlash Interface for SA-1100 */ - -/* PC Card Status Register */ -#define LINKUP_PRS_S1 (1 << 0) /* voltage control bits S1-S4 */ -#define LINKUP_PRS_S2 (1 << 1) -#define LINKUP_PRS_S3 (1 << 2) -#define LINKUP_PRS_S4 (1 << 3) -#define LINKUP_PRS_BVD1 (1 << 4) -#define LINKUP_PRS_BVD2 (1 << 5) -#define LINKUP_PRS_VS1 (1 << 6) -#define LINKUP_PRS_VS2 (1 << 7) -#define LINKUP_PRS_RDY (1 << 8) -#define LINKUP_PRS_CD1 (1 << 9) -#define LINKUP_PRS_CD2 (1 << 10) - -/* PC Card Command Register */ -#define LINKUP_PRC_S1 (1 << 0) -#define LINKUP_PRC_S2 (1 << 1) -#define LINKUP_PRC_S3 (1 << 2) -#define LINKUP_PRC_S4 (1 << 3) -#define LINKUP_PRC_RESET (1 << 4) -#define LINKUP_PRC_APOE (1 << 5) /* Auto Power Off Enable: clears S1-S4 when either nCD goes high */ -#define LINKUP_PRC_CFE (1 << 6) /* CompactFlash mode Enable: addresses A[10:0] only, A[25:11] high */ -#define LINKUP_PRC_SOE (1 << 7) /* signal output driver enable */ -#define LINKUP_PRC_SSP (1 << 8) /* sock select polarity: 0 for socket 0, 1 for socket 1 */ -#define LINKUP_PRC_MBZ (1 << 15) /* must be zero */ - -struct linkup_l1110 { - volatile short prc; -}; diff --git a/arch/arm/include/asm/hwcap.h b/arch/arm/include/asm/hwcap.h index 917626128a1d..6ff56eca3f1f 100644 --- a/arch/arm/include/asm/hwcap.h +++ b/arch/arm/include/asm/hwcap.h @@ -1,31 +1,8 @@ #ifndef __ASMARM_HWCAP_H #define __ASMARM_HWCAP_H -/* - * HWCAP flags - for elf_hwcap (in kernel) and AT_HWCAP - */ -#define HWCAP_SWP (1 << 0) -#define HWCAP_HALF (1 << 1) -#define HWCAP_THUMB (1 << 2) -#define HWCAP_26BIT (1 << 3) /* Play it safe */ -#define HWCAP_FAST_MULT (1 << 4) -#define HWCAP_FPA (1 << 5) -#define HWCAP_VFP (1 << 6) -#define HWCAP_EDSP (1 << 7) -#define HWCAP_JAVA (1 << 8) -#define HWCAP_IWMMXT (1 << 9) -#define HWCAP_CRUNCH (1 << 10) -#define HWCAP_THUMBEE (1 << 11) -#define HWCAP_NEON (1 << 12) -#define HWCAP_VFPv3 (1 << 13) -#define HWCAP_VFPv3D16 (1 << 14) -#define HWCAP_TLS (1 << 15) -#define HWCAP_VFPv4 (1 << 16) -#define HWCAP_IDIVA (1 << 17) -#define HWCAP_IDIVT (1 << 18) -#define HWCAP_IDIV (HWCAP_IDIVA | HWCAP_IDIVT) +#include <uapi/asm/hwcap.h> -#if defined(__KERNEL__) #if !defined(__ASSEMBLY__) /* * This yields a mask that user programs can use to figure out what @@ -35,5 +12,3 @@ extern unsigned int elf_hwcap; #endif #endif - -#endif diff --git a/arch/arm/include/asm/hypervisor.h b/arch/arm/include/asm/hypervisor.h new file mode 100644 index 000000000000..b90d9e523d6f --- /dev/null +++ b/arch/arm/include/asm/hypervisor.h @@ -0,0 +1,6 @@ +#ifndef _ASM_ARM_HYPERVISOR_H +#define _ASM_ARM_HYPERVISOR_H + +#include <asm/xen/hypervisor.h> + +#endif diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 8f4db67533e5..35c1ed89b936 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -47,13 +47,68 @@ extern void __raw_readsb(const void __iomem *addr, void *data, int bytelen); extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen); extern void __raw_readsl(const void __iomem *addr, void *data, int longlen); -#define __raw_writeb(v,a) ((void)(__chk_io_ptr(a), *(volatile unsigned char __force *)(a) = (v))) -#define __raw_writew(v,a) ((void)(__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v))) -#define __raw_writel(v,a) ((void)(__chk_io_ptr(a), *(volatile unsigned int __force *)(a) = (v))) +#if __LINUX_ARM_ARCH__ < 6 +/* + * Half-word accesses are problematic with RiscPC due to limitations of + * the bus. Rather than special-case the machine, just let the compiler + * generate the access for CPUs prior to ARMv6. + */ +#define __raw_readw(a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a)) +#define __raw_writew(v,a) ((void)(__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v))) +#else +/* + * When running under a hypervisor, we want to avoid I/O accesses with + * writeback addressing modes as these incur a significant performance + * overhead (the address generation must be emulated in software). + */ +static inline void __raw_writew(u16 val, volatile void __iomem *addr) +{ + asm volatile("strh %1, %0" + : "+Qo" (*(volatile u16 __force *)addr) + : "r" (val)); +} + +static inline u16 __raw_readw(const volatile void __iomem *addr) +{ + u16 val; + asm volatile("ldrh %1, %0" + : "+Qo" (*(volatile u16 __force *)addr), + "=r" (val)); + return val; +} +#endif -#define __raw_readb(a) (__chk_io_ptr(a), *(volatile unsigned char __force *)(a)) -#define __raw_readw(a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a)) -#define __raw_readl(a) (__chk_io_ptr(a), *(volatile unsigned int __force *)(a)) +static inline void __raw_writeb(u8 val, volatile void __iomem *addr) +{ + asm volatile("strb %1, %0" + : "+Qo" (*(volatile u8 __force *)addr) + : "r" (val)); +} + +static inline void __raw_writel(u32 val, volatile void __iomem *addr) +{ + asm volatile("str %1, %0" + : "+Qo" (*(volatile u32 __force *)addr) + : "r" (val)); +} + +static inline u8 __raw_readb(const volatile void __iomem *addr) +{ + u8 val; + asm volatile("ldrb %1, %0" + : "+Qo" (*(volatile u8 __force *)addr), + "=r" (val)); + return val; +} + +static inline u32 __raw_readl(const volatile void __iomem *addr) +{ + u32 val; + asm volatile("ldr %1, %0" + : "+Qo" (*(volatile u32 __force *)addr), + "=r" (val)); + return val; +} /* * Architecture ioremap implementation. diff --git a/arch/arm/include/asm/ipcbuf.h b/arch/arm/include/asm/ipcbuf.h deleted file mode 100644 index 84c7e51cb6d0..000000000000 --- a/arch/arm/include/asm/ipcbuf.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/ipcbuf.h> diff --git a/arch/arm/include/asm/module.h b/arch/arm/include/asm/module.h index 6c6809f982f1..0d3a28dbc8e5 100644 --- a/arch/arm/include/asm/module.h +++ b/arch/arm/include/asm/module.h @@ -1,9 +1,7 @@ #ifndef _ASM_ARM_MODULE_H #define _ASM_ARM_MODULE_H -#define Elf_Shdr Elf32_Shdr -#define Elf_Sym Elf32_Sym -#define Elf_Ehdr Elf32_Ehdr +#include <asm-generic/module.h> struct unwind_table; @@ -16,13 +14,11 @@ enum { ARM_SEC_DEVEXIT, ARM_SEC_MAX, }; -#endif struct mod_arch_specific { -#ifdef CONFIG_ARM_UNWIND struct unwind_table *unwind[ARM_SEC_MAX]; -#endif }; +#endif /* * Add the ARM architecture version to the version magic string diff --git a/arch/arm/include/asm/msgbuf.h b/arch/arm/include/asm/msgbuf.h deleted file mode 100644 index 33b35b946eaa..000000000000 --- a/arch/arm/include/asm/msgbuf.h +++ /dev/null @@ -1,31 +0,0 @@ -#ifndef _ASMARM_MSGBUF_H -#define _ASMARM_MSGBUF_H - -/* - * The msqid64_ds structure for arm architecture. - * Note extra padding because this structure is passed back and forth - * between kernel and user space. - * - * Pad space is left for: - * - 64-bit time_t to solve y2038 problem - * - 2 miscellaneous 32-bit values - */ - -struct msqid64_ds { - struct ipc64_perm msg_perm; - __kernel_time_t msg_stime; /* last msgsnd time */ - unsigned long __unused1; - __kernel_time_t msg_rtime; /* last msgrcv time */ - unsigned long __unused2; - __kernel_time_t msg_ctime; /* last change time */ - unsigned long __unused3; - unsigned long msg_cbytes; /* current number of bytes on queue */ - unsigned long msg_qnum; /* number of messages in queue */ - unsigned long msg_qbytes; /* max number of bytes on queue */ - __kernel_pid_t msg_lspid; /* pid of last msgsnd */ - __kernel_pid_t msg_lrpid; /* last receive pid */ - unsigned long __unused4; - unsigned long __unused5; -}; - -#endif /* _ASMARM_MSGBUF_H */ diff --git a/arch/arm/include/asm/mutex.h b/arch/arm/include/asm/mutex.h index b1479fd04a95..87c044910fe0 100644 --- a/arch/arm/include/asm/mutex.h +++ b/arch/arm/include/asm/mutex.h @@ -9,8 +9,13 @@ #define _ASM_MUTEX_H /* * On pre-ARMv6 hardware this results in a swp-based implementation, - * which is the most efficient. For ARMv6+, we emit a pair of exclusive - * accesses instead. + * which is the most efficient. For ARMv6+, we have exclusive memory + * accessors and use atomic_dec to avoid the extra xchg operations + * on the locking slowpaths. */ +#if __LINUX_ARM_ARCH__ < 6 #include <asm-generic/mutex-xchg.h> +#else +#include <asm-generic/mutex-dec.h> #endif +#endif /* _ASM_MUTEX_H */ diff --git a/arch/arm/include/asm/opcodes-virt.h b/arch/arm/include/asm/opcodes-virt.h new file mode 100644 index 000000000000..efcfdf92d9d5 --- /dev/null +++ b/arch/arm/include/asm/opcodes-virt.h @@ -0,0 +1,39 @@ +/* + * opcodes-virt.h: Opcode definitions for the ARM virtualization extensions + * Copyright (C) 2012 Linaro Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#ifndef __ASM_ARM_OPCODES_VIRT_H +#define __ASM_ARM_OPCODES_VIRT_H + +#include <asm/opcodes.h> + +#define __HVC(imm16) __inst_arm_thumb32( \ + 0xE1400070 | (((imm16) & 0xFFF0) << 4) | ((imm16) & 0x000F), \ + 0xF7E08000 | (((imm16) & 0xF000) << 4) | ((imm16) & 0x0FFF) \ +) + +#define __ERET __inst_arm_thumb32( \ + 0xE160006E, \ + 0xF3DE8F00 \ +) + +#define __MSR_ELR_HYP(regnum) __inst_arm_thumb32( \ + 0xE12EF300 | regnum, \ + 0xF3808E30 | (regnum << 16) \ +) + +#endif /* ! __ASM_ARM_OPCODES_VIRT_H */ diff --git a/arch/arm/include/asm/opcodes.h b/arch/arm/include/asm/opcodes.h index 19c48deda70f..74e211a6fb24 100644 --- a/arch/arm/include/asm/opcodes.h +++ b/arch/arm/include/asm/opcodes.h @@ -19,6 +19,33 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr); /* + * Assembler opcode byteswap helpers. + * These are only intended for use by this header: don't use them directly, + * because they will be suboptimal in most cases. + */ +#define ___asm_opcode_swab32(x) ( \ + (((x) << 24) & 0xFF000000) \ + | (((x) << 8) & 0x00FF0000) \ + | (((x) >> 8) & 0x0000FF00) \ + | (((x) >> 24) & 0x000000FF) \ +) +#define ___asm_opcode_swab16(x) ( \ + (((x) << 8) & 0xFF00) \ + | (((x) >> 8) & 0x00FF) \ +) +#define ___asm_opcode_swahb32(x) ( \ + (((x) << 8) & 0xFF00FF00) \ + | (((x) >> 8) & 0x00FF00FF) \ +) +#define ___asm_opcode_swahw32(x) ( \ + (((x) << 16) & 0xFFFF0000) \ + | (((x) >> 16) & 0x0000FFFF) \ +) +#define ___asm_opcode_identity32(x) ((x) & 0xFFFFFFFF) +#define ___asm_opcode_identity16(x) ((x) & 0xFFFF) + + +/* * Opcode byteswap helpers * * These macros help with converting instructions between a canonical integer @@ -41,39 +68,163 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr); * Note that values in the range 0x0000E800..0xE7FFFFFF intentionally do not * represent any valid Thumb-2 instruction. For this range, * __opcode_is_thumb32() and __opcode_is_thumb16() will both be false. + * + * The ___asm variants are intended only for use by this header, in situations + * involving inline assembler. For .S files, the normal __opcode_*() macros + * should do the right thing. */ +#ifdef __ASSEMBLY__ -#ifndef __ASSEMBLY__ +#define ___opcode_swab32(x) ___asm_opcode_swab32(x) +#define ___opcode_swab16(x) ___asm_opcode_swab16(x) +#define ___opcode_swahb32(x) ___asm_opcode_swahb32(x) +#define ___opcode_swahw32(x) ___asm_opcode_swahw32(x) +#define ___opcode_identity32(x) ___asm_opcode_identity32(x) +#define ___opcode_identity16(x) ___asm_opcode_identity16(x) + +#else /* ! __ASSEMBLY__ */ #include <linux/types.h> #include <linux/swab.h> +#define ___opcode_swab32(x) swab32(x) +#define ___opcode_swab16(x) swab16(x) +#define ___opcode_swahb32(x) swahb32(x) +#define ___opcode_swahw32(x) swahw32(x) +#define ___opcode_identity32(x) ((u32)(x)) +#define ___opcode_identity16(x) ((u16)(x)) + +#endif /* ! __ASSEMBLY__ */ + + #ifdef CONFIG_CPU_ENDIAN_BE8 -#define __opcode_to_mem_arm(x) swab32(x) -#define __opcode_to_mem_thumb16(x) swab16(x) -#define __opcode_to_mem_thumb32(x) swahb32(x) -#else -#define __opcode_to_mem_arm(x) ((u32)(x)) -#define __opcode_to_mem_thumb16(x) ((u16)(x)) -#define __opcode_to_mem_thumb32(x) swahw32(x) + +#define __opcode_to_mem_arm(x) ___opcode_swab32(x) +#define __opcode_to_mem_thumb16(x) ___opcode_swab16(x) +#define __opcode_to_mem_thumb32(x) ___opcode_swahb32(x) +#define ___asm_opcode_to_mem_arm(x) ___asm_opcode_swab32(x) +#define ___asm_opcode_to_mem_thumb16(x) ___asm_opcode_swab16(x) +#define ___asm_opcode_to_mem_thumb32(x) ___asm_opcode_swahb32(x) + +#else /* ! CONFIG_CPU_ENDIAN_BE8 */ + +#define __opcode_to_mem_arm(x) ___opcode_identity32(x) +#define __opcode_to_mem_thumb16(x) ___opcode_identity16(x) +#define ___asm_opcode_to_mem_arm(x) ___asm_opcode_identity32(x) +#define ___asm_opcode_to_mem_thumb16(x) ___asm_opcode_identity16(x) +#ifndef CONFIG_CPU_ENDIAN_BE32 +/* + * On BE32 systems, using 32-bit accesses to store Thumb instructions will not + * work in all cases, due to alignment constraints. For now, a correct + * version is not provided for BE32. + */ +#define __opcode_to_mem_thumb32(x) ___opcode_swahw32(x) +#define ___asm_opcode_to_mem_thumb32(x) ___asm_opcode_swahw32(x) #endif +#endif /* ! CONFIG_CPU_ENDIAN_BE8 */ + #define __mem_to_opcode_arm(x) __opcode_to_mem_arm(x) #define __mem_to_opcode_thumb16(x) __opcode_to_mem_thumb16(x) +#ifndef CONFIG_CPU_ENDIAN_BE32 #define __mem_to_opcode_thumb32(x) __opcode_to_mem_thumb32(x) +#endif /* Operations specific to Thumb opcodes */ /* Instruction size checks: */ -#define __opcode_is_thumb32(x) ((u32)(x) >= 0xE8000000UL) -#define __opcode_is_thumb16(x) ((u32)(x) < 0xE800UL) +#define __opcode_is_thumb32(x) ( \ + ((x) & 0xF8000000) == 0xE8000000 \ + || ((x) & 0xF0000000) == 0xF0000000 \ +) +#define __opcode_is_thumb16(x) ( \ + ((x) & 0xFFFF0000) == 0 \ + && !(((x) & 0xF800) == 0xE800 || ((x) & 0xF000) == 0xF000) \ +) /* Operations to construct or split 32-bit Thumb instructions: */ -#define __opcode_thumb32_first(x) ((u16)((x) >> 16)) -#define __opcode_thumb32_second(x) ((u16)(x)) -#define __opcode_thumb32_compose(first, second) \ - (((u32)(u16)(first) << 16) | (u32)(u16)(second)) +#define __opcode_thumb32_first(x) (___opcode_identity16((x) >> 16)) +#define __opcode_thumb32_second(x) (___opcode_identity16(x)) +#define __opcode_thumb32_compose(first, second) ( \ + (___opcode_identity32(___opcode_identity16(first)) << 16) \ + | ___opcode_identity32(___opcode_identity16(second)) \ +) +#define ___asm_opcode_thumb32_first(x) (___asm_opcode_identity16((x) >> 16)) +#define ___asm_opcode_thumb32_second(x) (___asm_opcode_identity16(x)) +#define ___asm_opcode_thumb32_compose(first, second) ( \ + (___asm_opcode_identity32(___asm_opcode_identity16(first)) << 16) \ + | ___asm_opcode_identity32(___asm_opcode_identity16(second)) \ +) -#endif /* __ASSEMBLY__ */ +/* + * Opcode injection helpers + * + * In rare cases it is necessary to assemble an opcode which the + * assembler does not support directly, or which would normally be + * rejected because of the CFLAGS or AFLAGS used to build the affected + * file. + * + * Before using these macros, consider carefully whether it is feasible + * instead to change the build flags for your file, or whether it really + * makes sense to support old assembler versions when building that + * particular kernel feature. + * + * The macros defined here should only be used where there is no viable + * alternative. + * + * + * __inst_arm(x): emit the specified ARM opcode + * __inst_thumb16(x): emit the specified 16-bit Thumb opcode + * __inst_thumb32(x): emit the specified 32-bit Thumb opcode + * + * __inst_arm_thumb16(arm, thumb): emit either the specified arm or + * 16-bit Thumb opcode, depending on whether an ARM or Thumb-2 + * kernel is being built + * + * __inst_arm_thumb32(arm, thumb): emit either the specified arm or + * 32-bit Thumb opcode, depending on whether an ARM or Thumb-2 + * kernel is being built + * + * + * Note that using these macros directly is poor practice. Instead, you + * should use them to define human-readable wrapper macros to encode the + * instructions that you care about. In code which might run on ARMv7 or + * above, you can usually use the __inst_arm_thumb{16,32} macros to + * specify the ARM and Thumb alternatives at the same time. This ensures + * that the correct opcode gets emitted depending on the instruction set + * used for the kernel build. + * + * Look at opcodes-virt.h for an example of how to use these macros. + */ +#include <linux/stringify.h> + +#define __inst_arm(x) ___inst_arm(___asm_opcode_to_mem_arm(x)) +#define __inst_thumb32(x) ___inst_thumb32( \ + ___asm_opcode_to_mem_thumb16(___asm_opcode_thumb32_first(x)), \ + ___asm_opcode_to_mem_thumb16(___asm_opcode_thumb32_second(x)) \ +) +#define __inst_thumb16(x) ___inst_thumb16(___asm_opcode_to_mem_thumb16(x)) + +#ifdef CONFIG_THUMB2_KERNEL +#define __inst_arm_thumb16(arm_opcode, thumb_opcode) \ + __inst_thumb16(thumb_opcode) +#define __inst_arm_thumb32(arm_opcode, thumb_opcode) \ + __inst_thumb32(thumb_opcode) +#else +#define __inst_arm_thumb16(arm_opcode, thumb_opcode) __inst_arm(arm_opcode) +#define __inst_arm_thumb32(arm_opcode, thumb_opcode) __inst_arm(arm_opcode) +#endif + +/* Helpers for the helpers. Don't use these directly. */ +#ifdef __ASSEMBLY__ +#define ___inst_arm(x) .long x +#define ___inst_thumb16(x) .short x +#define ___inst_thumb32(first, second) .short first, second +#else +#define ___inst_arm(x) ".long " __stringify(x) "\n\t" +#define ___inst_thumb16(x) ".short " __stringify(x) "\n\t" +#define ___inst_thumb32(first, second) \ + ".short " __stringify(first) ", " __stringify(second) "\n\t" +#endif #endif /* __ASM_ARM_OPCODES_H */ diff --git a/arch/arm/include/asm/param.h b/arch/arm/include/asm/param.h deleted file mode 100644 index 8b24bf94c06b..000000000000 --- a/arch/arm/include/asm/param.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * arch/arm/include/asm/param.h - * - * Copyright (C) 1995-1999 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef __ASM_PARAM_H -#define __ASM_PARAM_H - -#ifdef __KERNEL__ -# define HZ CONFIG_HZ /* Internal kernel timer frequency */ -# define USER_HZ 100 /* User interfaces are in "ticks" */ -# define CLOCKS_PER_SEC (USER_HZ) /* like times() */ -#else -# define HZ 100 -#endif - -#define EXEC_PAGESIZE 4096 - -#ifndef NOGROUP -#define NOGROUP (-1) -#endif - -/* max length of hostname */ -#define MAXHOSTNAMELEN 64 - -#endif - diff --git a/arch/arm/include/asm/parport.h b/arch/arm/include/asm/parport.h deleted file mode 100644 index 26e94b09035a..000000000000 --- a/arch/arm/include/asm/parport.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * arch/arm/include/asm/parport.h: ARM-specific parport initialisation - * - * Copyright (C) 1999, 2000 Tim Waugh <tim@cyberelk.demon.co.uk> - * - * This file should only be included by drivers/parport/parport_pc.c. - */ - -#ifndef __ASMARM_PARPORT_H -#define __ASMARM_PARPORT_H - -static int __devinit parport_pc_find_isa_ports (int autoirq, int autodma); -static int __devinit parport_pc_find_nonpci_ports (int autoirq, int autodma) -{ - return parport_pc_find_isa_ports (autoirq, autodma); -} - -#endif /* !(_ASMARM_PARPORT_H) */ diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h index 99afa7498260..06e7d509eaac 100644 --- a/arch/arm/include/asm/processor.h +++ b/arch/arm/include/asm/processor.h @@ -85,11 +85,6 @@ unsigned long get_wchan(struct task_struct *p); #define cpu_relax() barrier() #endif -/* - * Create a new kernel thread - */ -extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); - #define task_pt_regs(p) \ ((struct pt_regs *)(THREAD_START_SP + task_stack_page(p)) - 1) diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h index 355ece523f41..3d52ee1bfb31 100644 --- a/arch/arm/include/asm/ptrace.h +++ b/arch/arm/include/asm/ptrace.h @@ -10,132 +10,12 @@ #ifndef __ASM_ARM_PTRACE_H #define __ASM_ARM_PTRACE_H -#include <asm/hwcap.h> - -#define PTRACE_GETREGS 12 -#define PTRACE_SETREGS 13 -#define PTRACE_GETFPREGS 14 -#define PTRACE_SETFPREGS 15 -/* PTRACE_ATTACH is 16 */ -/* PTRACE_DETACH is 17 */ -#define PTRACE_GETWMMXREGS 18 -#define PTRACE_SETWMMXREGS 19 -/* 20 is unused */ -#define PTRACE_OLDSETOPTIONS 21 -#define PTRACE_GET_THREAD_AREA 22 -#define PTRACE_SET_SYSCALL 23 -/* PTRACE_SYSCALL is 24 */ -#define PTRACE_GETCRUNCHREGS 25 -#define PTRACE_SETCRUNCHREGS 26 -#define PTRACE_GETVFPREGS 27 -#define PTRACE_SETVFPREGS 28 -#define PTRACE_GETHBPREGS 29 -#define PTRACE_SETHBPREGS 30 - -/* - * PSR bits - */ -#define USR26_MODE 0x00000000 -#define FIQ26_MODE 0x00000001 -#define IRQ26_MODE 0x00000002 -#define SVC26_MODE 0x00000003 -#define USR_MODE 0x00000010 -#define FIQ_MODE 0x00000011 -#define IRQ_MODE 0x00000012 -#define SVC_MODE 0x00000013 -#define ABT_MODE 0x00000017 -#define UND_MODE 0x0000001b -#define SYSTEM_MODE 0x0000001f -#define MODE32_BIT 0x00000010 -#define MODE_MASK 0x0000001f -#define PSR_T_BIT 0x00000020 -#define PSR_F_BIT 0x00000040 -#define PSR_I_BIT 0x00000080 -#define PSR_A_BIT 0x00000100 -#define PSR_E_BIT 0x00000200 -#define PSR_J_BIT 0x01000000 -#define PSR_Q_BIT 0x08000000 -#define PSR_V_BIT 0x10000000 -#define PSR_C_BIT 0x20000000 -#define PSR_Z_BIT 0x40000000 -#define PSR_N_BIT 0x80000000 - -/* - * Groups of PSR bits - */ -#define PSR_f 0xff000000 /* Flags */ -#define PSR_s 0x00ff0000 /* Status */ -#define PSR_x 0x0000ff00 /* Extension */ -#define PSR_c 0x000000ff /* Control */ - -/* - * ARMv7 groups of PSR bits - */ -#define APSR_MASK 0xf80f0000 /* N, Z, C, V, Q and GE flags */ -#define PSR_ISET_MASK 0x01000010 /* ISA state (J, T) mask */ -#define PSR_IT_MASK 0x0600fc00 /* If-Then execution state mask */ -#define PSR_ENDIAN_MASK 0x00000200 /* Endianness state mask */ - -/* - * Default endianness state - */ -#ifdef CONFIG_CPU_ENDIAN_BE8 -#define PSR_ENDSTATE PSR_E_BIT -#else -#define PSR_ENDSTATE 0 -#endif - -/* - * These are 'magic' values for PTRACE_PEEKUSR that return info about where a - * process is located in memory. - */ -#define PT_TEXT_ADDR 0x10000 -#define PT_DATA_ADDR 0x10004 -#define PT_TEXT_END_ADDR 0x10008 +#include <uapi/asm/ptrace.h> #ifndef __ASSEMBLY__ - -/* - * This struct defines the way the registers are stored on the - * stack during a system call. Note that sizeof(struct pt_regs) - * has to be a multiple of 8. - */ -#ifndef __KERNEL__ -struct pt_regs { - long uregs[18]; -}; -#else /* __KERNEL__ */ struct pt_regs { unsigned long uregs[18]; }; -#endif /* __KERNEL__ */ - -#define ARM_cpsr uregs[16] -#define ARM_pc uregs[15] -#define ARM_lr uregs[14] -#define ARM_sp uregs[13] -#define ARM_ip uregs[12] -#define ARM_fp uregs[11] -#define ARM_r10 uregs[10] -#define ARM_r9 uregs[9] -#define ARM_r8 uregs[8] -#define ARM_r7 uregs[7] -#define ARM_r6 uregs[6] -#define ARM_r5 uregs[5] -#define ARM_r4 uregs[4] -#define ARM_r3 uregs[3] -#define ARM_r2 uregs[2] -#define ARM_r1 uregs[1] -#define ARM_r0 uregs[0] -#define ARM_ORIG_r0 uregs[17] - -/* - * The size of the user-visible VFP state as seen by PTRACE_GET/SETVFPREGS - * and core dumps. - */ -#define ARM_VFPREGS_SIZE ( 32 * 8 /*fpregs*/ + 4 /*fpscr*/ ) - -#ifdef __KERNEL__ #define user_mode(regs) \ (((regs)->ARM_cpsr & 0xf) == 0) @@ -254,9 +134,10 @@ static inline unsigned long user_stack_pointer(struct pt_regs *regs) return regs->ARM_sp; } -#endif /* __KERNEL__ */ +#define current_pt_regs(void) ({ \ + register unsigned long sp asm ("sp"); \ + (struct pt_regs *)((sp | (THREAD_SIZE - 1)) - 7) - 1; \ +}) #endif /* __ASSEMBLY__ */ - #endif - diff --git a/arch/arm/include/asm/segment.h b/arch/arm/include/asm/segment.h deleted file mode 100644 index 9e24c21f6304..000000000000 --- a/arch/arm/include/asm/segment.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef __ASM_ARM_SEGMENT_H -#define __ASM_ARM_SEGMENT_H - -#define __KERNEL_CS 0x0 -#define __KERNEL_DS 0x0 - -#define __USER_CS 0x1 -#define __USER_DS 0x1 - -#endif /* __ASM_ARM_SEGMENT_H */ - diff --git a/arch/arm/include/asm/sembuf.h b/arch/arm/include/asm/sembuf.h deleted file mode 100644 index 1c0283954289..000000000000 --- a/arch/arm/include/asm/sembuf.h +++ /dev/null @@ -1,25 +0,0 @@ -#ifndef _ASMARM_SEMBUF_H -#define _ASMARM_SEMBUF_H - -/* - * The semid64_ds structure for arm architecture. - * Note extra padding because this structure is passed back and forth - * between kernel and user space. - * - * Pad space is left for: - * - 64-bit time_t to solve y2038 problem - * - 2 miscellaneous 32-bit values - */ - -struct semid64_ds { - struct ipc64_perm sem_perm; /* permissions .. see ipc.h */ - __kernel_time_t sem_otime; /* last semop time */ - unsigned long __unused1; - __kernel_time_t sem_ctime; /* last change time */ - unsigned long __unused2; - unsigned long sem_nsems; /* no. of semaphores in array */ - unsigned long __unused3; - unsigned long __unused4; -}; - -#endif /* _ASMARM_SEMBUF_H */ diff --git a/arch/arm/include/asm/serial.h b/arch/arm/include/asm/serial.h deleted file mode 100644 index ebb049091e26..000000000000 --- a/arch/arm/include/asm/serial.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * arch/arm/include/asm/serial.h - * - * Copyright (C) 1996 Russell King. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Changelog: - * 15-10-1996 RMK Created - */ - -#ifndef __ASM_SERIAL_H -#define __ASM_SERIAL_H - -#define BASE_BAUD (1843200 / 16) - -#endif diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h index 24d284a1bfc7..c50f05609501 100644 --- a/arch/arm/include/asm/setup.h +++ b/arch/arm/include/asm/setup.h @@ -14,176 +14,8 @@ #ifndef __ASMARM_SETUP_H #define __ASMARM_SETUP_H -#include <linux/types.h> +#include <uapi/asm/setup.h> -#define COMMAND_LINE_SIZE 1024 - -/* The list ends with an ATAG_NONE node. */ -#define ATAG_NONE 0x00000000 - -struct tag_header { - __u32 size; - __u32 tag; -}; - -/* The list must start with an ATAG_CORE node */ -#define ATAG_CORE 0x54410001 - -struct tag_core { - __u32 flags; /* bit 0 = read-only */ - __u32 pagesize; - __u32 rootdev; -}; - -/* it is allowed to have multiple ATAG_MEM nodes */ -#define ATAG_MEM 0x54410002 - -struct tag_mem32 { - __u32 size; - __u32 start; /* physical start address */ -}; - -/* VGA text type displays */ -#define ATAG_VIDEOTEXT 0x54410003 - -struct tag_videotext { - __u8 x; - __u8 y; - __u16 video_page; - __u8 video_mode; - __u8 video_cols; - __u16 video_ega_bx; - __u8 video_lines; - __u8 video_isvga; - __u16 video_points; -}; - -/* describes how the ramdisk will be used in kernel */ -#define ATAG_RAMDISK 0x54410004 - -struct tag_ramdisk { - __u32 flags; /* bit 0 = load, bit 1 = prompt */ - __u32 size; /* decompressed ramdisk size in _kilo_ bytes */ - __u32 start; /* starting block of floppy-based RAM disk image */ -}; - -/* describes where the compressed ramdisk image lives (virtual address) */ -/* - * this one accidentally used virtual addresses - as such, - * it's deprecated. - */ -#define ATAG_INITRD 0x54410005 - -/* describes where the compressed ramdisk image lives (physical address) */ -#define ATAG_INITRD2 0x54420005 - -struct tag_initrd { - __u32 start; /* physical start address */ - __u32 size; /* size of compressed ramdisk image in bytes */ -}; - -/* board serial number. "64 bits should be enough for everybody" */ -#define ATAG_SERIAL 0x54410006 - -struct tag_serialnr { - __u32 low; - __u32 high; -}; - -/* board revision */ -#define ATAG_REVISION 0x54410007 - -struct tag_revision { - __u32 rev; -}; - -/* initial values for vesafb-type framebuffers. see struct screen_info - * in include/linux/tty.h - */ -#define ATAG_VIDEOLFB 0x54410008 - -struct tag_videolfb { - __u16 lfb_width; - __u16 lfb_height; - __u16 lfb_depth; - __u16 lfb_linelength; - __u32 lfb_base; - __u32 lfb_size; - __u8 red_size; - __u8 red_pos; - __u8 green_size; - __u8 green_pos; - __u8 blue_size; - __u8 blue_pos; - __u8 rsvd_size; - __u8 rsvd_pos; -}; - -/* command line: \0 terminated string */ -#define ATAG_CMDLINE 0x54410009 - -struct tag_cmdline { - char cmdline[1]; /* this is the minimum size */ -}; - -/* acorn RiscPC specific information */ -#define ATAG_ACORN 0x41000101 - -struct tag_acorn { - __u32 memc_control_reg; - __u32 vram_pages; - __u8 sounddefault; - __u8 adfsdrives; -}; - -/* footbridge memory clock, see arch/arm/mach-footbridge/arch.c */ -#define ATAG_MEMCLK 0x41000402 - -struct tag_memclk { - __u32 fmemclk; -}; - -struct tag { - struct tag_header hdr; - union { - struct tag_core core; - struct tag_mem32 mem; - struct tag_videotext videotext; - struct tag_ramdisk ramdisk; - struct tag_initrd initrd; - struct tag_serialnr serialnr; - struct tag_revision revision; - struct tag_videolfb videolfb; - struct tag_cmdline cmdline; - - /* - * Acorn specific - */ - struct tag_acorn acorn; - - /* - * DC21285 specific - */ - struct tag_memclk memclk; - } u; -}; - -struct tagtable { - __u32 tag; - int (*parse)(const struct tag *); -}; - -#define tag_member_present(tag,member) \ - ((unsigned long)(&((struct tag *)0L)->member + 1) \ - <= (tag)->hdr.size * 4) - -#define tag_next(t) ((struct tag *)((__u32 *)(t) + (t)->hdr.size)) -#define tag_size(type) ((sizeof(struct tag_header) + sizeof(struct type)) >> 2) - -#define for_each_tag(t,base) \ - for (t = base; t->hdr.size; t = tag_next(t)) - -#ifdef __KERNEL__ #define __tag __used __attribute__((__section__(".taglist.init"))) #define __tagtable(tag, fn) \ @@ -221,6 +53,4 @@ extern int arm_add_memory(phys_addr_t start, phys_addr_t size); extern void early_print(const char *str, ...); extern void dump_machine_table(void); -#endif /* __KERNEL__ */ - #endif diff --git a/arch/arm/include/asm/shmbuf.h b/arch/arm/include/asm/shmbuf.h deleted file mode 100644 index 2e5c67ba1c97..000000000000 --- a/arch/arm/include/asm/shmbuf.h +++ /dev/null @@ -1,42 +0,0 @@ -#ifndef _ASMARM_SHMBUF_H -#define _ASMARM_SHMBUF_H - -/* - * The shmid64_ds structure for arm architecture. - * Note extra padding because this structure is passed back and forth - * between kernel and user space. - * - * Pad space is left for: - * - 64-bit time_t to solve y2038 problem - * - 2 miscellaneous 32-bit values - */ - -struct shmid64_ds { - struct ipc64_perm shm_perm; /* operation perms */ - size_t shm_segsz; /* size of segment (bytes) */ - __kernel_time_t shm_atime; /* last attach time */ - unsigned long __unused1; - __kernel_time_t shm_dtime; /* last detach time */ - unsigned long __unused2; - __kernel_time_t shm_ctime; /* last change time */ - unsigned long __unused3; - __kernel_pid_t shm_cpid; /* pid of creator */ - __kernel_pid_t shm_lpid; /* pid of last operator */ - unsigned long shm_nattch; /* no. of current attaches */ - unsigned long __unused4; - unsigned long __unused5; -}; - -struct shminfo64 { - unsigned long shmmax; - unsigned long shmmin; - unsigned long shmmni; - unsigned long shmseg; - unsigned long shmall; - unsigned long __unused1; - unsigned long __unused2; - unsigned long __unused3; - unsigned long __unused4; -}; - -#endif /* _ASMARM_SHMBUF_H */ diff --git a/arch/arm/include/asm/signal.h b/arch/arm/include/asm/signal.h index 43ba0fb1c8ad..5a7963dbd3fb 100644 --- a/arch/arm/include/asm/signal.h +++ b/arch/arm/include/asm/signal.h @@ -1,12 +1,8 @@ #ifndef _ASMARM_SIGNAL_H #define _ASMARM_SIGNAL_H -#include <linux/types.h> +#include <uapi/asm/signal.h> -/* Avoid too many header ordering problems. */ -struct siginfo; - -#ifdef __KERNEL__ /* Most things should be clean enough to redefine this at will, if care is taken to make libc match. */ @@ -20,100 +16,6 @@ typedef struct { unsigned long sig[_NSIG_WORDS]; } sigset_t; -#else -/* Here we must cater to libcs that poke about in kernel headers. */ - -#define NSIG 32 -typedef unsigned long sigset_t; - -#endif /* __KERNEL__ */ - -#define SIGHUP 1 -#define SIGINT 2 -#define SIGQUIT 3 -#define SIGILL 4 -#define SIGTRAP 5 -#define SIGABRT 6 -#define SIGIOT 6 -#define SIGBUS 7 -#define SIGFPE 8 -#define SIGKILL 9 -#define SIGUSR1 10 -#define SIGSEGV 11 -#define SIGUSR2 12 -#define SIGPIPE 13 -#define SIGALRM 14 -#define SIGTERM 15 -#define SIGSTKFLT 16 -#define SIGCHLD 17 -#define SIGCONT 18 -#define SIGSTOP 19 -#define SIGTSTP 20 -#define SIGTTIN 21 -#define SIGTTOU 22 -#define SIGURG 23 -#define SIGXCPU 24 -#define SIGXFSZ 25 -#define SIGVTALRM 26 -#define SIGPROF 27 -#define SIGWINCH 28 -#define SIGIO 29 -#define SIGPOLL SIGIO -/* -#define SIGLOST 29 -*/ -#define SIGPWR 30 -#define SIGSYS 31 -#define SIGUNUSED 31 - -/* These should not be considered constants from userland. */ -#define SIGRTMIN 32 -#define SIGRTMAX _NSIG - -#define SIGSWI 32 - -/* - * SA_FLAGS values: - * - * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. - * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. - * SA_SIGINFO deliver the signal with SIGINFO structs - * SA_THIRTYTWO delivers the signal in 32-bit mode, even if the task - * is running in 26-bit. - * SA_ONSTACK allows alternate signal stacks (see sigaltstack(2)). - * SA_RESTART flag to get restarting signals (which were the default long ago) - * SA_NODEFER prevents the current signal from being masked in the handler. - * SA_RESETHAND clears the handler when the signal is delivered. - * - * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single - * Unix names RESETHAND and NODEFER respectively. - */ -#define SA_NOCLDSTOP 0x00000001 -#define SA_NOCLDWAIT 0x00000002 -#define SA_SIGINFO 0x00000004 -#define SA_THIRTYTWO 0x02000000 -#define SA_RESTORER 0x04000000 -#define SA_ONSTACK 0x08000000 -#define SA_RESTART 0x10000000 -#define SA_NODEFER 0x40000000 -#define SA_RESETHAND 0x80000000 - -#define SA_NOMASK SA_NODEFER -#define SA_ONESHOT SA_RESETHAND - - -/* - * sigaltstack controls - */ -#define SS_ONSTACK 1 -#define SS_DISABLE 2 - -#define MINSIGSTKSZ 2048 -#define SIGSTKSZ 8192 - -#include <asm-generic/signal-defs.h> - -#ifdef __KERNEL__ struct old_sigaction { __sighandler_t sa_handler; old_sigset_t sa_mask; @@ -132,33 +34,6 @@ struct k_sigaction { struct sigaction sa; }; -#else -/* Here we must cater to libcs that poke about in kernel headers. */ - -struct sigaction { - union { - __sighandler_t _sa_handler; - void (*_sa_sigaction)(int, struct siginfo *, void *); - } _u; - sigset_t sa_mask; - unsigned long sa_flags; - void (*sa_restorer)(void); -}; - -#define sa_handler _u._sa_handler -#define sa_sigaction _u._sa_sigaction - -#endif /* __KERNEL__ */ - -typedef struct sigaltstack { - void __user *ss_sp; - int ss_flags; - size_t ss_size; -} stack_t; - -#ifdef __KERNEL__ #include <asm/sigcontext.h> #define ptrace_signal_deliver(regs, cookie) do { } while (0) #endif - -#endif diff --git a/arch/arm/include/asm/socket.h b/arch/arm/include/asm/socket.h deleted file mode 100644 index 6433cadb6ed4..000000000000 --- a/arch/arm/include/asm/socket.h +++ /dev/null @@ -1,72 +0,0 @@ -#ifndef _ASMARM_SOCKET_H -#define _ASMARM_SOCKET_H - -#include <asm/sockios.h> - -/* For setsockopt(2) */ -#define SOL_SOCKET 1 - -#define SO_DEBUG 1 -#define SO_REUSEADDR 2 -#define SO_TYPE 3 -#define SO_ERROR 4 -#define SO_DONTROUTE 5 -#define SO_BROADCAST 6 -#define SO_SNDBUF 7 -#define SO_RCVBUF 8 -#define SO_SNDBUFFORCE 32 -#define SO_RCVBUFFORCE 33 -#define SO_KEEPALIVE 9 -#define SO_OOBINLINE 10 -#define SO_NO_CHECK 11 -#define SO_PRIORITY 12 -#define SO_LINGER 13 -#define SO_BSDCOMPAT 14 -/* To add :#define SO_REUSEPORT 15 */ -#define SO_PASSCRED 16 -#define SO_PEERCRED 17 -#define SO_RCVLOWAT 18 -#define SO_SNDLOWAT 19 -#define SO_RCVTIMEO 20 -#define SO_SNDTIMEO 21 - -/* Security levels - as per NRL IPv6 - don't actually do anything */ -#define SO_SECURITY_AUTHENTICATION 22 -#define SO_SECURITY_ENCRYPTION_TRANSPORT 23 -#define SO_SECURITY_ENCRYPTION_NETWORK 24 - -#define SO_BINDTODEVICE 25 - -/* Socket filtering */ -#define SO_ATTACH_FILTER 26 -#define SO_DETACH_FILTER 27 - -#define SO_PEERNAME 28 -#define SO_TIMESTAMP 29 -#define SCM_TIMESTAMP SO_TIMESTAMP - -#define SO_ACCEPTCONN 30 - -#define SO_PEERSEC 31 -#define SO_PASSSEC 34 -#define SO_TIMESTAMPNS 35 -#define SCM_TIMESTAMPNS SO_TIMESTAMPNS - -#define SO_MARK 36 - -#define SO_TIMESTAMPING 37 -#define SCM_TIMESTAMPING SO_TIMESTAMPING - -#define SO_PROTOCOL 38 -#define SO_DOMAIN 39 - -#define SO_RXQ_OVFL 40 - -#define SO_WIFI_STATUS 41 -#define SCM_WIFI_STATUS SO_WIFI_STATUS -#define SO_PEEK_OFF 42 - -/* Instruct lower device to use last 4-bytes of skb data as FCS */ -#define SO_NOFCS 43 - -#endif /* _ASM_SOCKET_H */ diff --git a/arch/arm/include/asm/sockios.h b/arch/arm/include/asm/sockios.h deleted file mode 100644 index a2588a2512df..000000000000 --- a/arch/arm/include/asm/sockios.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef __ARCH_ARM_SOCKIOS_H -#define __ARCH_ARM_SOCKIOS_H - -/* Socket-level I/O control calls. */ -#define FIOSETOWN 0x8901 -#define SIOCSPGRP 0x8902 -#define FIOGETOWN 0x8903 -#define SIOCGPGRP 0x8904 -#define SIOCATMARK 0x8905 -#define SIOCGSTAMP 0x8906 /* Get stamp (timeval) */ -#define SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */ - -#endif diff --git a/arch/arm/include/asm/swab.h b/arch/arm/include/asm/swab.h index b859d82e30ca..537fc9b91889 100644 --- a/arch/arm/include/asm/swab.h +++ b/arch/arm/include/asm/swab.h @@ -15,14 +15,8 @@ #ifndef __ASM_ARM_SWAB_H #define __ASM_ARM_SWAB_H -#include <linux/compiler.h> -#include <linux/types.h> +#include <uapi/asm/swab.h> -#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) -# define __SWAB_64_THRU_32__ -#endif - -#if defined(__KERNEL__) #if __LINUX_ARM_ARCH__ >= 6 static inline __attribute_const__ __u32 __arch_swahb32(__u32 x) @@ -42,32 +36,3 @@ static inline __attribute_const__ __u32 __arch_swab32(__u32 x) #endif #endif - -#if !defined(__KERNEL__) || __LINUX_ARM_ARCH__ < 6 -static inline __attribute_const__ __u32 __arch_swab32(__u32 x) -{ - __u32 t; - -#ifndef __thumb__ - if (!__builtin_constant_p(x)) { - /* - * The compiler needs a bit of a hint here to always do the - * right thing and not screw it up to different degrees - * depending on the gcc version. - */ - asm ("eor\t%0, %1, %1, ror #16" : "=r" (t) : "r" (x)); - } else -#endif - t = x ^ ((x << 16) | (x >> 16)); /* eor r1,r0,r0,ror #16 */ - - x = (x << 24) | (x >> 8); /* mov r0,r0,ror #8 */ - t &= ~0x00FF0000; /* bic r1,r1,#0x00FF0000 */ - x ^= (t >> 8); /* eor r0,r0,r1,lsr #8 */ - - return x; -} -#define __arch_swab32 __arch_swab32 - -#endif - -#endif diff --git a/arch/arm/include/asm/sync_bitops.h b/arch/arm/include/asm/sync_bitops.h new file mode 100644 index 000000000000..63479eecbf76 --- /dev/null +++ b/arch/arm/include/asm/sync_bitops.h @@ -0,0 +1,27 @@ +#ifndef __ASM_SYNC_BITOPS_H__ +#define __ASM_SYNC_BITOPS_H__ + +#include <asm/bitops.h> +#include <asm/system.h> + +/* sync_bitops functions are equivalent to the SMP implementation of the + * original functions, independently from CONFIG_SMP being defined. + * + * We need them because _set_bit etc are not SMP safe if !CONFIG_SMP. But + * under Xen you might be communicating with a completely external entity + * who might be on another CPU (e.g. two uniprocessor guests communicating + * via event channels and grant tables). So we need a variant of the bit + * ops which are SMP safe even on a UP kernel. + */ + +#define sync_set_bit(nr, p) _set_bit(nr, p) +#define sync_clear_bit(nr, p) _clear_bit(nr, p) +#define sync_change_bit(nr, p) _change_bit(nr, p) +#define sync_test_and_set_bit(nr, p) _test_and_set_bit(nr, p) +#define sync_test_and_clear_bit(nr, p) _test_and_clear_bit(nr, p) +#define sync_test_and_change_bit(nr, p) _test_and_change_bit(nr, p) +#define sync_test_bit(nr, addr) test_bit(nr, addr) +#define sync_cmpxchg cmpxchg + + +#endif diff --git a/arch/arm/include/asm/syscall.h b/arch/arm/include/asm/syscall.h index c334a23ddf75..9fdded6b1089 100644 --- a/arch/arm/include/asm/syscall.h +++ b/arch/arm/include/asm/syscall.h @@ -8,6 +8,11 @@ #define _ASM_ARM_SYSCALL_H #include <linux/err.h> +#include <linux/sched.h> + +#include <asm/unistd.h> + +#define NR_syscalls (__NR_syscalls) extern const unsigned long sys_call_table[]; diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 74542c52f9be..368165e33c1c 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -2,7 +2,6 @@ #include <asm/barrier.h> #include <asm/compiler.h> #include <asm/cmpxchg.h> -#include <asm/exec.h> #include <asm/switch_to.h> #include <asm/system_info.h> #include <asm/system_misc.h> diff --git a/arch/arm/include/asm/termbits.h b/arch/arm/include/asm/termbits.h deleted file mode 100644 index 704135d28d1d..000000000000 --- a/arch/arm/include/asm/termbits.h +++ /dev/null @@ -1,198 +0,0 @@ -#ifndef __ASM_ARM_TERMBITS_H -#define __ASM_ARM_TERMBITS_H - -typedef unsigned char cc_t; -typedef unsigned int speed_t; -typedef unsigned int tcflag_t; - -#define NCCS 19 -struct termios { - tcflag_t c_iflag; /* input mode flags */ - tcflag_t c_oflag; /* output mode flags */ - tcflag_t c_cflag; /* control mode flags */ - tcflag_t c_lflag; /* local mode flags */ - cc_t c_line; /* line discipline */ - cc_t c_cc[NCCS]; /* control characters */ -}; - -struct termios2 { - tcflag_t c_iflag; /* input mode flags */ - tcflag_t c_oflag; /* output mode flags */ - tcflag_t c_cflag; /* control mode flags */ - tcflag_t c_lflag; /* local mode flags */ - cc_t c_line; /* line discipline */ - cc_t c_cc[NCCS]; /* control characters */ - speed_t c_ispeed; /* input speed */ - speed_t c_ospeed; /* output speed */ -}; - -struct ktermios { - tcflag_t c_iflag; /* input mode flags */ - tcflag_t c_oflag; /* output mode flags */ - tcflag_t c_cflag; /* control mode flags */ - tcflag_t c_lflag; /* local mode flags */ - cc_t c_line; /* line discipline */ - cc_t c_cc[NCCS]; /* control characters */ - speed_t c_ispeed; /* input speed */ - speed_t c_ospeed; /* output speed */ -}; - - -/* c_cc characters */ -#define VINTR 0 -#define VQUIT 1 -#define VERASE 2 -#define VKILL 3 -#define VEOF 4 -#define VTIME 5 -#define VMIN 6 -#define VSWTC 7 -#define VSTART 8 -#define VSTOP 9 -#define VSUSP 10 -#define VEOL 11 -#define VREPRINT 12 -#define VDISCARD 13 -#define VWERASE 14 -#define VLNEXT 15 -#define VEOL2 16 - -/* c_iflag bits */ -#define IGNBRK 0000001 -#define BRKINT 0000002 -#define IGNPAR 0000004 -#define PARMRK 0000010 -#define INPCK 0000020 -#define ISTRIP 0000040 -#define INLCR 0000100 -#define IGNCR 0000200 -#define ICRNL 0000400 -#define IUCLC 0001000 -#define IXON 0002000 -#define IXANY 0004000 -#define IXOFF 0010000 -#define IMAXBEL 0020000 -#define IUTF8 0040000 - -/* c_oflag bits */ -#define OPOST 0000001 -#define OLCUC 0000002 -#define ONLCR 0000004 -#define OCRNL 0000010 -#define ONOCR 0000020 -#define ONLRET 0000040 -#define OFILL 0000100 -#define OFDEL 0000200 -#define NLDLY 0000400 -#define NL0 0000000 -#define NL1 0000400 -#define CRDLY 0003000 -#define CR0 0000000 -#define CR1 0001000 -#define CR2 0002000 -#define CR3 0003000 -#define TABDLY 0014000 -#define TAB0 0000000 -#define TAB1 0004000 -#define TAB2 0010000 -#define TAB3 0014000 -#define XTABS 0014000 -#define BSDLY 0020000 -#define BS0 0000000 -#define BS1 0020000 -#define VTDLY 0040000 -#define VT0 0000000 -#define VT1 0040000 -#define FFDLY 0100000 -#define FF0 0000000 -#define FF1 0100000 - -/* c_cflag bit meaning */ -#define CBAUD 0010017 -#define B0 0000000 /* hang up */ -#define B50 0000001 -#define B75 0000002 -#define B110 0000003 -#define B134 0000004 -#define B150 0000005 -#define B200 0000006 -#define B300 0000007 -#define B600 0000010 -#define B1200 0000011 -#define B1800 0000012 -#define B2400 0000013 -#define B4800 0000014 -#define B9600 0000015 -#define B19200 0000016 -#define B38400 0000017 -#define EXTA B19200 -#define EXTB B38400 -#define CSIZE 0000060 -#define CS5 0000000 -#define CS6 0000020 -#define CS7 0000040 -#define CS8 0000060 -#define CSTOPB 0000100 -#define CREAD 0000200 -#define PARENB 0000400 -#define PARODD 0001000 -#define HUPCL 0002000 -#define CLOCAL 0004000 -#define CBAUDEX 0010000 -#define BOTHER 0010000 -#define B57600 0010001 -#define B115200 0010002 -#define B230400 0010003 -#define B460800 0010004 -#define B500000 0010005 -#define B576000 0010006 -#define B921600 0010007 -#define B1000000 0010010 -#define B1152000 0010011 -#define B1500000 0010012 -#define B2000000 0010013 -#define B2500000 0010014 -#define B3000000 0010015 -#define B3500000 0010016 -#define B4000000 0010017 -#define CIBAUD 002003600000 /* input baud rate */ -#define CMSPAR 010000000000 /* mark or space (stick) parity */ -#define CRTSCTS 020000000000 /* flow control */ - -#define IBSHIFT 16 - -/* c_lflag bits */ -#define ISIG 0000001 -#define ICANON 0000002 -#define XCASE 0000004 -#define ECHO 0000010 -#define ECHOE 0000020 -#define ECHOK 0000040 -#define ECHONL 0000100 -#define NOFLSH 0000200 -#define TOSTOP 0000400 -#define ECHOCTL 0001000 -#define ECHOPRT 0002000 -#define ECHOKE 0004000 -#define FLUSHO 0010000 -#define PENDIN 0040000 -#define IEXTEN 0100000 -#define EXTPROC 0200000 - -/* tcflow() and TCXONC use these */ -#define TCOOFF 0 -#define TCOON 1 -#define TCIOFF 2 -#define TCION 3 - -/* tcflush() and TCFLSH use these */ -#define TCIFLUSH 0 -#define TCOFLUSH 1 -#define TCIOFLUSH 2 - -/* tcsetattr uses these */ -#define TCSANOW 0 -#define TCSADRAIN 1 -#define TCSAFLUSH 2 - -#endif /* __ASM_ARM_TERMBITS_H */ diff --git a/arch/arm/include/asm/termios.h b/arch/arm/include/asm/termios.h deleted file mode 100644 index 293e3f1bc3f2..000000000000 --- a/arch/arm/include/asm/termios.h +++ /dev/null @@ -1,92 +0,0 @@ -#ifndef __ASM_ARM_TERMIOS_H -#define __ASM_ARM_TERMIOS_H - -#include <asm/termbits.h> -#include <asm/ioctls.h> - -struct winsize { - unsigned short ws_row; - unsigned short ws_col; - unsigned short ws_xpixel; - unsigned short ws_ypixel; -}; - -#define NCC 8 -struct termio { - unsigned short c_iflag; /* input mode flags */ - unsigned short c_oflag; /* output mode flags */ - unsigned short c_cflag; /* control mode flags */ - unsigned short c_lflag; /* local mode flags */ - unsigned char c_line; /* line discipline */ - unsigned char c_cc[NCC]; /* control characters */ -}; - -#ifdef __KERNEL__ -/* intr=^C quit=^| erase=del kill=^U - eof=^D vtime=\0 vmin=\1 sxtc=\0 - start=^Q stop=^S susp=^Z eol=\0 - reprint=^R discard=^U werase=^W lnext=^V - eol2=\0 -*/ -#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0" -#endif - -/* modem lines */ -#define TIOCM_LE 0x001 -#define TIOCM_DTR 0x002 -#define TIOCM_RTS 0x004 -#define TIOCM_ST 0x008 -#define TIOCM_SR 0x010 -#define TIOCM_CTS 0x020 -#define TIOCM_CAR 0x040 -#define TIOCM_RNG 0x080 -#define TIOCM_DSR 0x100 -#define TIOCM_CD TIOCM_CAR -#define TIOCM_RI TIOCM_RNG -#define TIOCM_OUT1 0x2000 -#define TIOCM_OUT2 0x4000 -#define TIOCM_LOOP 0x8000 - -/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */ - -#ifdef __KERNEL__ - -/* - * Translate a "termio" structure into a "termios". Ugh. - */ -#define SET_LOW_TERMIOS_BITS(termios, termio, x) { \ - unsigned short __tmp; \ - get_user(__tmp,&(termio)->x); \ - *(unsigned short *) &(termios)->x = __tmp; \ -} - -#define user_termio_to_kernel_termios(termios, termio) \ -({ \ - SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \ - SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \ - SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \ - SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \ - copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \ -}) - -/* - * Translate a "termios" structure into a "termio". Ugh. - */ -#define kernel_termios_to_user_termio(termio, termios) \ -({ \ - put_user((termios)->c_iflag, &(termio)->c_iflag); \ - put_user((termios)->c_oflag, &(termio)->c_oflag); \ - put_user((termios)->c_cflag, &(termio)->c_cflag); \ - put_user((termios)->c_lflag, &(termio)->c_lflag); \ - put_user((termios)->c_line, &(termio)->c_line); \ - copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \ -}) - -#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2)) -#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2)) -#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios)) -#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios)) - -#endif /* __KERNEL__ */ - -#endif /* __ASM_ARM_TERMIOS_H */ diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h index af7b0bda3355..8477b4c1d39f 100644 --- a/arch/arm/include/asm/thread_info.h +++ b/arch/arm/include/asm/thread_info.h @@ -59,7 +59,9 @@ struct thread_info { __u32 syscall; /* syscall number */ __u8 used_cp[16]; /* thread used copro */ unsigned long tp_value; +#ifdef CONFIG_CRUNCH struct crunch_state crunchstate; +#endif union fp_state fpstate __attribute__((aligned(8))); union vfp_state vfpstate; #ifdef CONFIG_ARM_THUMBEE @@ -148,7 +150,7 @@ extern int vfp_restore_user_hwstate(struct user_vfp __user *, #define TIF_NOTIFY_RESUME 2 /* callback before returning to user */ #define TIF_SYSCALL_TRACE 8 #define TIF_SYSCALL_AUDIT 9 -#define TIF_POLLING_NRFLAG 16 +#define TIF_SYSCALL_TRACEPOINT 10 #define TIF_USING_IWMMXT 17 #define TIF_MEMDIE 18 /* is terminating due to OOM killer */ #define TIF_RESTORE_SIGMASK 20 @@ -160,12 +162,12 @@ extern int vfp_restore_user_hwstate(struct user_vfp __user *, #define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME) #define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE) #define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT) -#define _TIF_POLLING_NRFLAG (1 << TIF_POLLING_NRFLAG) +#define _TIF_SYSCALL_TRACEPOINT (1 << TIF_SYSCALL_TRACEPOINT) #define _TIF_USING_IWMMXT (1 << TIF_USING_IWMMXT) #define _TIF_SECCOMP (1 << TIF_SECCOMP) /* Checks for any syscall work in entry-common.S */ -#define _TIF_SYSCALL_WORK (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT) +#define _TIF_SYSCALL_WORK (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | _TIF_SYSCALL_TRACEPOINT) /* * Change these and you break ASM code in entry-common.S diff --git a/arch/arm/include/asm/timex.h b/arch/arm/include/asm/timex.h index 963342acebb7..83f2aa83899c 100644 --- a/arch/arm/include/asm/timex.h +++ b/arch/arm/include/asm/timex.h @@ -12,7 +12,6 @@ #ifndef _ASMARM_TIMEX_H #define _ASMARM_TIMEX_H -#include <asm/arch_timer.h> #ifdef CONFIG_ARCH_MULTIPLATFORM #define CLOCK_TICK_RATE 1000000 #else @@ -20,11 +19,6 @@ #endif typedef unsigned long cycles_t; - -#ifdef ARCH_HAS_READ_CURRENT_TIMER #define get_cycles() ({ cycles_t c; read_current_timer(&c) ? 0 : c; }) -#else -#define get_cycles() (0) -#endif #endif diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h deleted file mode 100644 index 28beab917ffc..000000000000 --- a/arch/arm/include/asm/types.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef __ASM_ARM_TYPES_H -#define __ASM_ARM_TYPES_H - -#include <asm-generic/int-ll64.h> - -/* - * These aren't exported outside the kernel to avoid name space clashes - */ -#ifdef __KERNEL__ - -#define BITS_PER_LONG 32 - -#endif /* __KERNEL__ */ - -#endif - diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h index 77bd79f2ffdb..7e1f76027f66 100644 --- a/arch/arm/include/asm/uaccess.h +++ b/arch/arm/include/asm/uaccess.h @@ -200,8 +200,8 @@ extern int __put_user_8(void *, unsigned long long); #define USER_DS KERNEL_DS #define segment_eq(a,b) (1) -#define __addr_ok(addr) (1) -#define __range_ok(addr,size) (0) +#define __addr_ok(addr) ((void)(addr),1) +#define __range_ok(addr,size) ((void)(addr),0) #define get_fs() (KERNEL_DS) static inline void set_fs(mm_segment_t fs) diff --git a/arch/arm/include/asm/unaligned.h b/arch/arm/include/asm/unaligned.h deleted file mode 100644 index 44593a894903..000000000000 --- a/arch/arm/include/asm/unaligned.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef _ASM_ARM_UNALIGNED_H -#define _ASM_ARM_UNALIGNED_H - -#include <linux/unaligned/le_byteshift.h> -#include <linux/unaligned/be_byteshift.h> -#include <linux/unaligned/generic.h> - -/* - * Select endianness - */ -#ifndef __ARMEB__ -#define get_unaligned __get_unaligned_le -#define put_unaligned __put_unaligned_le -#else -#define get_unaligned __get_unaligned_be -#define put_unaligned __put_unaligned_be -#endif - -#endif /* _ASM_ARM_UNALIGNED_H */ diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h index 2fde5fd1acce..8f60b6e6bd41 100644 --- a/arch/arm/include/asm/unistd.h +++ b/arch/arm/include/asm/unistd.h @@ -13,439 +13,10 @@ #ifndef __ASM_ARM_UNISTD_H #define __ASM_ARM_UNISTD_H -#define __NR_OABI_SYSCALL_BASE 0x900000 +#include <uapi/asm/unistd.h> -#if defined(__thumb__) || defined(__ARM_EABI__) -#define __NR_SYSCALL_BASE 0 -#else -#define __NR_SYSCALL_BASE __NR_OABI_SYSCALL_BASE -#endif - -/* - * This file contains the system call numbers. - */ - -#define __NR_restart_syscall (__NR_SYSCALL_BASE+ 0) -#define __NR_exit (__NR_SYSCALL_BASE+ 1) -#define __NR_fork (__NR_SYSCALL_BASE+ 2) -#define __NR_read (__NR_SYSCALL_BASE+ 3) -#define __NR_write (__NR_SYSCALL_BASE+ 4) -#define __NR_open (__NR_SYSCALL_BASE+ 5) -#define __NR_close (__NR_SYSCALL_BASE+ 6) - /* 7 was sys_waitpid */ -#define __NR_creat (__NR_SYSCALL_BASE+ 8) -#define __NR_link (__NR_SYSCALL_BASE+ 9) -#define __NR_unlink (__NR_SYSCALL_BASE+ 10) -#define __NR_execve (__NR_SYSCALL_BASE+ 11) -#define __NR_chdir (__NR_SYSCALL_BASE+ 12) -#define __NR_time (__NR_SYSCALL_BASE+ 13) -#define __NR_mknod (__NR_SYSCALL_BASE+ 14) -#define __NR_chmod (__NR_SYSCALL_BASE+ 15) -#define __NR_lchown (__NR_SYSCALL_BASE+ 16) - /* 17 was sys_break */ - /* 18 was sys_stat */ -#define __NR_lseek (__NR_SYSCALL_BASE+ 19) -#define __NR_getpid (__NR_SYSCALL_BASE+ 20) -#define __NR_mount (__NR_SYSCALL_BASE+ 21) -#define __NR_umount (__NR_SYSCALL_BASE+ 22) -#define __NR_setuid (__NR_SYSCALL_BASE+ 23) -#define __NR_getuid (__NR_SYSCALL_BASE+ 24) -#define __NR_stime (__NR_SYSCALL_BASE+ 25) -#define __NR_ptrace (__NR_SYSCALL_BASE+ 26) -#define __NR_alarm (__NR_SYSCALL_BASE+ 27) - /* 28 was sys_fstat */ -#define __NR_pause (__NR_SYSCALL_BASE+ 29) -#define __NR_utime (__NR_SYSCALL_BASE+ 30) - /* 31 was sys_stty */ - /* 32 was sys_gtty */ -#define __NR_access (__NR_SYSCALL_BASE+ 33) -#define __NR_nice (__NR_SYSCALL_BASE+ 34) - /* 35 was sys_ftime */ -#define __NR_sync (__NR_SYSCALL_BASE+ 36) -#define __NR_kill (__NR_SYSCALL_BASE+ 37) -#define __NR_rename (__NR_SYSCALL_BASE+ 38) -#define __NR_mkdir (__NR_SYSCALL_BASE+ 39) -#define __NR_rmdir (__NR_SYSCALL_BASE+ 40) -#define __NR_dup (__NR_SYSCALL_BASE+ 41) -#define __NR_pipe (__NR_SYSCALL_BASE+ 42) -#define __NR_times (__NR_SYSCALL_BASE+ 43) - /* 44 was sys_prof */ -#define __NR_brk (__NR_SYSCALL_BASE+ 45) -#define __NR_setgid (__NR_SYSCALL_BASE+ 46) -#define __NR_getgid (__NR_SYSCALL_BASE+ 47) - /* 48 was sys_signal */ -#define __NR_geteuid (__NR_SYSCALL_BASE+ 49) -#define __NR_getegid (__NR_SYSCALL_BASE+ 50) -#define __NR_acct (__NR_SYSCALL_BASE+ 51) -#define __NR_umount2 (__NR_SYSCALL_BASE+ 52) - /* 53 was sys_lock */ -#define __NR_ioctl (__NR_SYSCALL_BASE+ 54) -#define __NR_fcntl (__NR_SYSCALL_BASE+ 55) - /* 56 was sys_mpx */ -#define __NR_setpgid (__NR_SYSCALL_BASE+ 57) - /* 58 was sys_ulimit */ - /* 59 was sys_olduname */ -#define __NR_umask (__NR_SYSCALL_BASE+ 60) -#define __NR_chroot (__NR_SYSCALL_BASE+ 61) -#define __NR_ustat (__NR_SYSCALL_BASE+ 62) -#define __NR_dup2 (__NR_SYSCALL_BASE+ 63) -#define __NR_getppid (__NR_SYSCALL_BASE+ 64) -#define __NR_getpgrp (__NR_SYSCALL_BASE+ 65) -#define __NR_setsid (__NR_SYSCALL_BASE+ 66) -#define __NR_sigaction (__NR_SYSCALL_BASE+ 67) - /* 68 was sys_sgetmask */ - /* 69 was sys_ssetmask */ -#define __NR_setreuid (__NR_SYSCALL_BASE+ 70) -#define __NR_setregid (__NR_SYSCALL_BASE+ 71) -#define __NR_sigsuspend (__NR_SYSCALL_BASE+ 72) -#define __NR_sigpending (__NR_SYSCALL_BASE+ 73) -#define __NR_sethostname (__NR_SYSCALL_BASE+ 74) -#define __NR_setrlimit (__NR_SYSCALL_BASE+ 75) -#define __NR_getrlimit (__NR_SYSCALL_BASE+ 76) /* Back compat 2GB limited rlimit */ -#define __NR_getrusage (__NR_SYSCALL_BASE+ 77) -#define __NR_gettimeofday (__NR_SYSCALL_BASE+ 78) -#define __NR_settimeofday (__NR_SYSCALL_BASE+ 79) -#define __NR_getgroups (__NR_SYSCALL_BASE+ 80) -#define __NR_setgroups (__NR_SYSCALL_BASE+ 81) -#define __NR_select (__NR_SYSCALL_BASE+ 82) -#define __NR_symlink (__NR_SYSCALL_BASE+ 83) - /* 84 was sys_lstat */ -#define __NR_readlink (__NR_SYSCALL_BASE+ 85) -#define __NR_uselib (__NR_SYSCALL_BASE+ 86) -#define __NR_swapon (__NR_SYSCALL_BASE+ 87) -#define __NR_reboot (__NR_SYSCALL_BASE+ 88) -#define __NR_readdir (__NR_SYSCALL_BASE+ 89) -#define __NR_mmap (__NR_SYSCALL_BASE+ 90) -#define __NR_munmap (__NR_SYSCALL_BASE+ 91) -#define __NR_truncate (__NR_SYSCALL_BASE+ 92) -#define __NR_ftruncate (__NR_SYSCALL_BASE+ 93) -#define __NR_fchmod (__NR_SYSCALL_BASE+ 94) -#define __NR_fchown (__NR_SYSCALL_BASE+ 95) -#define __NR_getpriority (__NR_SYSCALL_BASE+ 96) -#define __NR_setpriority (__NR_SYSCALL_BASE+ 97) - /* 98 was sys_profil */ -#define __NR_statfs (__NR_SYSCALL_BASE+ 99) -#define __NR_fstatfs (__NR_SYSCALL_BASE+100) - /* 101 was sys_ioperm */ -#define __NR_socketcall (__NR_SYSCALL_BASE+102) -#define __NR_syslog (__NR_SYSCALL_BASE+103) -#define __NR_setitimer (__NR_SYSCALL_BASE+104) -#define __NR_getitimer (__NR_SYSCALL_BASE+105) -#define __NR_stat (__NR_SYSCALL_BASE+106) -#define __NR_lstat (__NR_SYSCALL_BASE+107) -#define __NR_fstat (__NR_SYSCALL_BASE+108) - /* 109 was sys_uname */ - /* 110 was sys_iopl */ -#define __NR_vhangup (__NR_SYSCALL_BASE+111) - /* 112 was sys_idle */ -#define __NR_syscall (__NR_SYSCALL_BASE+113) /* syscall to call a syscall! */ -#define __NR_wait4 (__NR_SYSCALL_BASE+114) -#define __NR_swapoff (__NR_SYSCALL_BASE+115) -#define __NR_sysinfo (__NR_SYSCALL_BASE+116) -#define __NR_ipc (__NR_SYSCALL_BASE+117) -#define __NR_fsync (__NR_SYSCALL_BASE+118) -#define __NR_sigreturn (__NR_SYSCALL_BASE+119) -#define __NR_clone (__NR_SYSCALL_BASE+120) -#define __NR_setdomainname (__NR_SYSCALL_BASE+121) -#define __NR_uname (__NR_SYSCALL_BASE+122) - /* 123 was sys_modify_ldt */ -#define __NR_adjtimex (__NR_SYSCALL_BASE+124) -#define __NR_mprotect (__NR_SYSCALL_BASE+125) -#define __NR_sigprocmask (__NR_SYSCALL_BASE+126) - /* 127 was sys_create_module */ -#define __NR_init_module (__NR_SYSCALL_BASE+128) -#define __NR_delete_module (__NR_SYSCALL_BASE+129) - /* 130 was sys_get_kernel_syms */ -#define __NR_quotactl (__NR_SYSCALL_BASE+131) -#define __NR_getpgid (__NR_SYSCALL_BASE+132) -#define __NR_fchdir (__NR_SYSCALL_BASE+133) -#define __NR_bdflush (__NR_SYSCALL_BASE+134) -#define __NR_sysfs (__NR_SYSCALL_BASE+135) -#define __NR_personality (__NR_SYSCALL_BASE+136) - /* 137 was sys_afs_syscall */ -#define __NR_setfsuid (__NR_SYSCALL_BASE+138) -#define __NR_setfsgid (__NR_SYSCALL_BASE+139) -#define __NR__llseek (__NR_SYSCALL_BASE+140) -#define __NR_getdents (__NR_SYSCALL_BASE+141) -#define __NR__newselect (__NR_SYSCALL_BASE+142) -#define __NR_flock (__NR_SYSCALL_BASE+143) -#define __NR_msync (__NR_SYSCALL_BASE+144) -#define __NR_readv (__NR_SYSCALL_BASE+145) -#define __NR_writev (__NR_SYSCALL_BASE+146) -#define __NR_getsid (__NR_SYSCALL_BASE+147) -#define __NR_fdatasync (__NR_SYSCALL_BASE+148) -#define __NR__sysctl (__NR_SYSCALL_BASE+149) -#define __NR_mlock (__NR_SYSCALL_BASE+150) -#define __NR_munlock (__NR_SYSCALL_BASE+151) -#define __NR_mlockall (__NR_SYSCALL_BASE+152) -#define __NR_munlockall (__NR_SYSCALL_BASE+153) -#define __NR_sched_setparam (__NR_SYSCALL_BASE+154) -#define __NR_sched_getparam (__NR_SYSCALL_BASE+155) -#define __NR_sched_setscheduler (__NR_SYSCALL_BASE+156) -#define __NR_sched_getscheduler (__NR_SYSCALL_BASE+157) -#define __NR_sched_yield (__NR_SYSCALL_BASE+158) -#define __NR_sched_get_priority_max (__NR_SYSCALL_BASE+159) -#define __NR_sched_get_priority_min (__NR_SYSCALL_BASE+160) -#define __NR_sched_rr_get_interval (__NR_SYSCALL_BASE+161) -#define __NR_nanosleep (__NR_SYSCALL_BASE+162) -#define __NR_mremap (__NR_SYSCALL_BASE+163) -#define __NR_setresuid (__NR_SYSCALL_BASE+164) -#define __NR_getresuid (__NR_SYSCALL_BASE+165) - /* 166 was sys_vm86 */ - /* 167 was sys_query_module */ -#define __NR_poll (__NR_SYSCALL_BASE+168) -#define __NR_nfsservctl (__NR_SYSCALL_BASE+169) -#define __NR_setresgid (__NR_SYSCALL_BASE+170) -#define __NR_getresgid (__NR_SYSCALL_BASE+171) -#define __NR_prctl (__NR_SYSCALL_BASE+172) -#define __NR_rt_sigreturn (__NR_SYSCALL_BASE+173) -#define __NR_rt_sigaction (__NR_SYSCALL_BASE+174) -#define __NR_rt_sigprocmask (__NR_SYSCALL_BASE+175) -#define __NR_rt_sigpending (__NR_SYSCALL_BASE+176) -#define __NR_rt_sigtimedwait (__NR_SYSCALL_BASE+177) -#define __NR_rt_sigqueueinfo (__NR_SYSCALL_BASE+178) -#define __NR_rt_sigsuspend (__NR_SYSCALL_BASE+179) -#define __NR_pread64 (__NR_SYSCALL_BASE+180) -#define __NR_pwrite64 (__NR_SYSCALL_BASE+181) -#define __NR_chown (__NR_SYSCALL_BASE+182) -#define __NR_getcwd (__NR_SYSCALL_BASE+183) -#define __NR_capget (__NR_SYSCALL_BASE+184) -#define __NR_capset (__NR_SYSCALL_BASE+185) -#define __NR_sigaltstack (__NR_SYSCALL_BASE+186) -#define __NR_sendfile (__NR_SYSCALL_BASE+187) - /* 188 reserved */ - /* 189 reserved */ -#define __NR_vfork (__NR_SYSCALL_BASE+190) -#define __NR_ugetrlimit (__NR_SYSCALL_BASE+191) /* SuS compliant getrlimit */ -#define __NR_mmap2 (__NR_SYSCALL_BASE+192) -#define __NR_truncate64 (__NR_SYSCALL_BASE+193) -#define __NR_ftruncate64 (__NR_SYSCALL_BASE+194) -#define __NR_stat64 (__NR_SYSCALL_BASE+195) -#define __NR_lstat64 (__NR_SYSCALL_BASE+196) -#define __NR_fstat64 (__NR_SYSCALL_BASE+197) -#define __NR_lchown32 (__NR_SYSCALL_BASE+198) -#define __NR_getuid32 (__NR_SYSCALL_BASE+199) -#define __NR_getgid32 (__NR_SYSCALL_BASE+200) -#define __NR_geteuid32 (__NR_SYSCALL_BASE+201) -#define __NR_getegid32 (__NR_SYSCALL_BASE+202) -#define __NR_setreuid32 (__NR_SYSCALL_BASE+203) -#define __NR_setregid32 (__NR_SYSCALL_BASE+204) -#define __NR_getgroups32 (__NR_SYSCALL_BASE+205) -#define __NR_setgroups32 (__NR_SYSCALL_BASE+206) -#define __NR_fchown32 (__NR_SYSCALL_BASE+207) -#define __NR_setresuid32 (__NR_SYSCALL_BASE+208) -#define __NR_getresuid32 (__NR_SYSCALL_BASE+209) -#define __NR_setresgid32 (__NR_SYSCALL_BASE+210) -#define __NR_getresgid32 (__NR_SYSCALL_BASE+211) -#define __NR_chown32 (__NR_SYSCALL_BASE+212) -#define __NR_setuid32 (__NR_SYSCALL_BASE+213) -#define __NR_setgid32 (__NR_SYSCALL_BASE+214) -#define __NR_setfsuid32 (__NR_SYSCALL_BASE+215) -#define __NR_setfsgid32 (__NR_SYSCALL_BASE+216) -#define __NR_getdents64 (__NR_SYSCALL_BASE+217) -#define __NR_pivot_root (__NR_SYSCALL_BASE+218) -#define __NR_mincore (__NR_SYSCALL_BASE+219) -#define __NR_madvise (__NR_SYSCALL_BASE+220) -#define __NR_fcntl64 (__NR_SYSCALL_BASE+221) - /* 222 for tux */ - /* 223 is unused */ -#define __NR_gettid (__NR_SYSCALL_BASE+224) -#define __NR_readahead (__NR_SYSCALL_BASE+225) -#define __NR_setxattr (__NR_SYSCALL_BASE+226) -#define __NR_lsetxattr (__NR_SYSCALL_BASE+227) -#define __NR_fsetxattr (__NR_SYSCALL_BASE+228) -#define __NR_getxattr (__NR_SYSCALL_BASE+229) -#define __NR_lgetxattr (__NR_SYSCALL_BASE+230) -#define __NR_fgetxattr (__NR_SYSCALL_BASE+231) -#define __NR_listxattr (__NR_SYSCALL_BASE+232) -#define __NR_llistxattr (__NR_SYSCALL_BASE+233) -#define __NR_flistxattr (__NR_SYSCALL_BASE+234) -#define __NR_removexattr (__NR_SYSCALL_BASE+235) -#define __NR_lremovexattr (__NR_SYSCALL_BASE+236) -#define __NR_fremovexattr (__NR_SYSCALL_BASE+237) -#define __NR_tkill (__NR_SYSCALL_BASE+238) -#define __NR_sendfile64 (__NR_SYSCALL_BASE+239) -#define __NR_futex (__NR_SYSCALL_BASE+240) -#define __NR_sched_setaffinity (__NR_SYSCALL_BASE+241) -#define __NR_sched_getaffinity (__NR_SYSCALL_BASE+242) -#define __NR_io_setup (__NR_SYSCALL_BASE+243) -#define __NR_io_destroy (__NR_SYSCALL_BASE+244) -#define __NR_io_getevents (__NR_SYSCALL_BASE+245) -#define __NR_io_submit (__NR_SYSCALL_BASE+246) -#define __NR_io_cancel (__NR_SYSCALL_BASE+247) -#define __NR_exit_group (__NR_SYSCALL_BASE+248) -#define __NR_lookup_dcookie (__NR_SYSCALL_BASE+249) -#define __NR_epoll_create (__NR_SYSCALL_BASE+250) -#define __NR_epoll_ctl (__NR_SYSCALL_BASE+251) -#define __NR_epoll_wait (__NR_SYSCALL_BASE+252) -#define __NR_remap_file_pages (__NR_SYSCALL_BASE+253) - /* 254 for set_thread_area */ - /* 255 for get_thread_area */ -#define __NR_set_tid_address (__NR_SYSCALL_BASE+256) -#define __NR_timer_create (__NR_SYSCALL_BASE+257) -#define __NR_timer_settime (__NR_SYSCALL_BASE+258) -#define __NR_timer_gettime (__NR_SYSCALL_BASE+259) -#define __NR_timer_getoverrun (__NR_SYSCALL_BASE+260) -#define __NR_timer_delete (__NR_SYSCALL_BASE+261) -#define __NR_clock_settime (__NR_SYSCALL_BASE+262) -#define __NR_clock_gettime (__NR_SYSCALL_BASE+263) -#define __NR_clock_getres (__NR_SYSCALL_BASE+264) -#define __NR_clock_nanosleep (__NR_SYSCALL_BASE+265) -#define __NR_statfs64 (__NR_SYSCALL_BASE+266) -#define __NR_fstatfs64 (__NR_SYSCALL_BASE+267) -#define __NR_tgkill (__NR_SYSCALL_BASE+268) -#define __NR_utimes (__NR_SYSCALL_BASE+269) -#define __NR_arm_fadvise64_64 (__NR_SYSCALL_BASE+270) -#define __NR_pciconfig_iobase (__NR_SYSCALL_BASE+271) -#define __NR_pciconfig_read (__NR_SYSCALL_BASE+272) -#define __NR_pciconfig_write (__NR_SYSCALL_BASE+273) -#define __NR_mq_open (__NR_SYSCALL_BASE+274) -#define __NR_mq_unlink (__NR_SYSCALL_BASE+275) -#define __NR_mq_timedsend (__NR_SYSCALL_BASE+276) -#define __NR_mq_timedreceive (__NR_SYSCALL_BASE+277) -#define __NR_mq_notify (__NR_SYSCALL_BASE+278) -#define __NR_mq_getsetattr (__NR_SYSCALL_BASE+279) -#define __NR_waitid (__NR_SYSCALL_BASE+280) -#define __NR_socket (__NR_SYSCALL_BASE+281) -#define __NR_bind (__NR_SYSCALL_BASE+282) -#define __NR_connect (__NR_SYSCALL_BASE+283) -#define __NR_listen (__NR_SYSCALL_BASE+284) -#define __NR_accept (__NR_SYSCALL_BASE+285) -#define __NR_getsockname (__NR_SYSCALL_BASE+286) -#define __NR_getpeername (__NR_SYSCALL_BASE+287) -#define __NR_socketpair (__NR_SYSCALL_BASE+288) -#define __NR_send (__NR_SYSCALL_BASE+289) -#define __NR_sendto (__NR_SYSCALL_BASE+290) -#define __NR_recv (__NR_SYSCALL_BASE+291) -#define __NR_recvfrom (__NR_SYSCALL_BASE+292) -#define __NR_shutdown (__NR_SYSCALL_BASE+293) -#define __NR_setsockopt (__NR_SYSCALL_BASE+294) -#define __NR_getsockopt (__NR_SYSCALL_BASE+295) -#define __NR_sendmsg (__NR_SYSCALL_BASE+296) -#define __NR_recvmsg (__NR_SYSCALL_BASE+297) -#define __NR_semop (__NR_SYSCALL_BASE+298) -#define __NR_semget (__NR_SYSCALL_BASE+299) -#define __NR_semctl (__NR_SYSCALL_BASE+300) -#define __NR_msgsnd (__NR_SYSCALL_BASE+301) -#define __NR_msgrcv (__NR_SYSCALL_BASE+302) -#define __NR_msgget (__NR_SYSCALL_BASE+303) -#define __NR_msgctl (__NR_SYSCALL_BASE+304) -#define __NR_shmat (__NR_SYSCALL_BASE+305) -#define __NR_shmdt (__NR_SYSCALL_BASE+306) -#define __NR_shmget (__NR_SYSCALL_BASE+307) -#define __NR_shmctl (__NR_SYSCALL_BASE+308) -#define __NR_add_key (__NR_SYSCALL_BASE+309) -#define __NR_request_key (__NR_SYSCALL_BASE+310) -#define __NR_keyctl (__NR_SYSCALL_BASE+311) -#define __NR_semtimedop (__NR_SYSCALL_BASE+312) -#define __NR_vserver (__NR_SYSCALL_BASE+313) -#define __NR_ioprio_set (__NR_SYSCALL_BASE+314) -#define __NR_ioprio_get (__NR_SYSCALL_BASE+315) -#define __NR_inotify_init (__NR_SYSCALL_BASE+316) -#define __NR_inotify_add_watch (__NR_SYSCALL_BASE+317) -#define __NR_inotify_rm_watch (__NR_SYSCALL_BASE+318) -#define __NR_mbind (__NR_SYSCALL_BASE+319) -#define __NR_get_mempolicy (__NR_SYSCALL_BASE+320) -#define __NR_set_mempolicy (__NR_SYSCALL_BASE+321) -#define __NR_openat (__NR_SYSCALL_BASE+322) -#define __NR_mkdirat (__NR_SYSCALL_BASE+323) -#define __NR_mknodat (__NR_SYSCALL_BASE+324) -#define __NR_fchownat (__NR_SYSCALL_BASE+325) -#define __NR_futimesat (__NR_SYSCALL_BASE+326) -#define __NR_fstatat64 (__NR_SYSCALL_BASE+327) -#define __NR_unlinkat (__NR_SYSCALL_BASE+328) -#define __NR_renameat (__NR_SYSCALL_BASE+329) -#define __NR_linkat (__NR_SYSCALL_BASE+330) -#define __NR_symlinkat (__NR_SYSCALL_BASE+331) -#define __NR_readlinkat (__NR_SYSCALL_BASE+332) -#define __NR_fchmodat (__NR_SYSCALL_BASE+333) -#define __NR_faccessat (__NR_SYSCALL_BASE+334) -#define __NR_pselect6 (__NR_SYSCALL_BASE+335) -#define __NR_ppoll (__NR_SYSCALL_BASE+336) -#define __NR_unshare (__NR_SYSCALL_BASE+337) -#define __NR_set_robust_list (__NR_SYSCALL_BASE+338) -#define __NR_get_robust_list (__NR_SYSCALL_BASE+339) -#define __NR_splice (__NR_SYSCALL_BASE+340) -#define __NR_arm_sync_file_range (__NR_SYSCALL_BASE+341) -#define __NR_sync_file_range2 __NR_arm_sync_file_range -#define __NR_tee (__NR_SYSCALL_BASE+342) -#define __NR_vmsplice (__NR_SYSCALL_BASE+343) -#define __NR_move_pages (__NR_SYSCALL_BASE+344) -#define __NR_getcpu (__NR_SYSCALL_BASE+345) -#define __NR_epoll_pwait (__NR_SYSCALL_BASE+346) -#define __NR_kexec_load (__NR_SYSCALL_BASE+347) -#define __NR_utimensat (__NR_SYSCALL_BASE+348) -#define __NR_signalfd (__NR_SYSCALL_BASE+349) -#define __NR_timerfd_create (__NR_SYSCALL_BASE+350) -#define __NR_eventfd (__NR_SYSCALL_BASE+351) -#define __NR_fallocate (__NR_SYSCALL_BASE+352) -#define __NR_timerfd_settime (__NR_SYSCALL_BASE+353) -#define __NR_timerfd_gettime (__NR_SYSCALL_BASE+354) -#define __NR_signalfd4 (__NR_SYSCALL_BASE+355) -#define __NR_eventfd2 (__NR_SYSCALL_BASE+356) -#define __NR_epoll_create1 (__NR_SYSCALL_BASE+357) -#define __NR_dup3 (__NR_SYSCALL_BASE+358) -#define __NR_pipe2 (__NR_SYSCALL_BASE+359) -#define __NR_inotify_init1 (__NR_SYSCALL_BASE+360) -#define __NR_preadv (__NR_SYSCALL_BASE+361) -#define __NR_pwritev (__NR_SYSCALL_BASE+362) -#define __NR_rt_tgsigqueueinfo (__NR_SYSCALL_BASE+363) -#define __NR_perf_event_open (__NR_SYSCALL_BASE+364) -#define __NR_recvmmsg (__NR_SYSCALL_BASE+365) -#define __NR_accept4 (__NR_SYSCALL_BASE+366) -#define __NR_fanotify_init (__NR_SYSCALL_BASE+367) -#define __NR_fanotify_mark (__NR_SYSCALL_BASE+368) -#define __NR_prlimit64 (__NR_SYSCALL_BASE+369) -#define __NR_name_to_handle_at (__NR_SYSCALL_BASE+370) -#define __NR_open_by_handle_at (__NR_SYSCALL_BASE+371) -#define __NR_clock_adjtime (__NR_SYSCALL_BASE+372) -#define __NR_syncfs (__NR_SYSCALL_BASE+373) -#define __NR_sendmmsg (__NR_SYSCALL_BASE+374) -#define __NR_setns (__NR_SYSCALL_BASE+375) -#define __NR_process_vm_readv (__NR_SYSCALL_BASE+376) -#define __NR_process_vm_writev (__NR_SYSCALL_BASE+377) - /* 378 for kcmp */ - -/* - * The following SWIs are ARM private. - */ -#define __ARM_NR_BASE (__NR_SYSCALL_BASE+0x0f0000) -#define __ARM_NR_breakpoint (__ARM_NR_BASE+1) -#define __ARM_NR_cacheflush (__ARM_NR_BASE+2) -#define __ARM_NR_usr26 (__ARM_NR_BASE+3) -#define __ARM_NR_usr32 (__ARM_NR_BASE+4) -#define __ARM_NR_set_tls (__ARM_NR_BASE+5) - -/* - * *NOTE*: This is a ghost syscall private to the kernel. Only the - * __kuser_cmpxchg code in entry-armv.S should be aware of its - * existence. Don't ever use this from user code. - */ -#ifdef __KERNEL__ +#define __NR_syscalls (380) #define __ARM_NR_cmpxchg (__ARM_NR_BASE+0x00fff0) -#endif - -/* - * The following syscalls are obsolete and no longer available for EABI. - */ -#if !defined(__KERNEL__) -#if defined(__ARM_EABI__) -#undef __NR_time -#undef __NR_umount -#undef __NR_stime -#undef __NR_alarm -#undef __NR_utime -#undef __NR_getrlimit -#undef __NR_select -#undef __NR_readdir -#undef __NR_mmap -#undef __NR_socketcall -#undef __NR_syscall -#undef __NR_ipc -#endif -#endif - -#ifdef __KERNEL__ #define __ARCH_WANT_STAT64 #define __ARCH_WANT_SYS_GETHOSTNAME @@ -470,6 +41,7 @@ #define __ARCH_WANT_OLD_READDIR #define __ARCH_WANT_SYS_SOCKETCALL #endif +#define __ARCH_WANT_SYS_EXECVE /* * "Conditional" syscalls @@ -486,5 +58,4 @@ #define __IGNORE_migrate_pages #define __IGNORE_kcmp -#endif /* __KERNEL__ */ #endif /* __ASM_ARM_UNISTD_H */ diff --git a/arch/arm/include/asm/vfpmacros.h b/arch/arm/include/asm/vfpmacros.h index a7aadbd9a6dd..6a6f1e485f41 100644 --- a/arch/arm/include/asm/vfpmacros.h +++ b/arch/arm/include/asm/vfpmacros.h @@ -28,7 +28,7 @@ ldr \tmp, =elf_hwcap @ may not have MVFR regs ldr \tmp, [\tmp, #0] tst \tmp, #HWCAP_VFPv3D16 - ldceq p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31} + ldceql p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31} addne \base, \base, #32*4 @ step over unused register space #else VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0 @@ -52,7 +52,7 @@ ldr \tmp, =elf_hwcap @ may not have MVFR regs ldr \tmp, [\tmp, #0] tst \tmp, #HWCAP_VFPv3D16 - stceq p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31} + stceql p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31} addne \base, \base, #32*4 @ step over unused register space #else VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0 diff --git a/arch/arm/include/asm/virt.h b/arch/arm/include/asm/virt.h new file mode 100644 index 000000000000..86164df86cb4 --- /dev/null +++ b/arch/arm/include/asm/virt.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2012 Linaro Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef VIRT_H +#define VIRT_H + +#include <asm/ptrace.h> + +/* + * Flag indicating that the kernel was not entered in the same mode on every + * CPU. The zImage loader stashes this value in an SPSR, so we need an + * architecturally defined flag bit here (the N flag, as it happens) + */ +#define BOOT_CPU_MODE_MISMATCH (1<<31) + +#ifndef __ASSEMBLY__ + +#ifdef CONFIG_ARM_VIRT_EXT +/* + * __boot_cpu_mode records what mode the primary CPU was booted in. + * A correctly-implemented bootloader must start all CPUs in the same mode: + * if it fails to do this, the flag BOOT_CPU_MODE_MISMATCH is set to indicate + * that some CPU(s) were booted in a different mode. + * + * This allows the kernel to flag an error when the secondaries have come up. + */ +extern int __boot_cpu_mode; + +void __hyp_set_vectors(unsigned long phys_vector_base); +unsigned long __hyp_get_vectors(void); +#else +#define __boot_cpu_mode (SVC_MODE) +#endif + +#ifndef ZIMAGE +void hyp_mode_check(void); + +/* Reports the availability of HYP mode */ +static inline bool is_hyp_mode_available(void) +{ + return ((__boot_cpu_mode & MODE_MASK) == HYP_MODE && + !(__boot_cpu_mode & BOOT_CPU_MODE_MISMATCH)); +} + +/* Check if the bootloader has booted CPUs in different modes */ +static inline bool is_hyp_mode_mismatched(void) +{ + return !!(__boot_cpu_mode & BOOT_CPU_MODE_MISMATCH); +} +#endif + +#endif /* __ASSEMBLY__ */ + +#endif /* ! VIRT_H */ diff --git a/arch/arm/include/asm/xen/events.h b/arch/arm/include/asm/xen/events.h new file mode 100644 index 000000000000..94b4e9020b02 --- /dev/null +++ b/arch/arm/include/asm/xen/events.h @@ -0,0 +1,18 @@ +#ifndef _ASM_ARM_XEN_EVENTS_H +#define _ASM_ARM_XEN_EVENTS_H + +#include <asm/ptrace.h> + +enum ipi_vector { + XEN_PLACEHOLDER_VECTOR, + + /* Xen IPIs go here */ + XEN_NR_IPIS, +}; + +static inline int xen_irqs_disabled(struct pt_regs *regs) +{ + return raw_irqs_disabled_flags(regs->ARM_cpsr); +} + +#endif /* _ASM_ARM_XEN_EVENTS_H */ diff --git a/arch/arm/include/asm/xen/hypercall.h b/arch/arm/include/asm/xen/hypercall.h new file mode 100644 index 000000000000..8a823253d775 --- /dev/null +++ b/arch/arm/include/asm/xen/hypercall.h @@ -0,0 +1,69 @@ +/****************************************************************************** + * hypercall.h + * + * Linux-specific hypervisor handling. + * + * Stefano Stabellini <stefano.stabellini@eu.citrix.com>, Citrix, 2012 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation; or, when distributed + * separately from the Linux kernel or incorporated into other + * software packages, subject to the following license: + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this source file (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, modify, + * merge, publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#ifndef _ASM_ARM_XEN_HYPERCALL_H +#define _ASM_ARM_XEN_HYPERCALL_H + +#include <xen/interface/xen.h> + +long privcmd_call(unsigned call, unsigned long a1, + unsigned long a2, unsigned long a3, + unsigned long a4, unsigned long a5); +int HYPERVISOR_xen_version(int cmd, void *arg); +int HYPERVISOR_console_io(int cmd, int count, char *str); +int HYPERVISOR_grant_table_op(unsigned int cmd, void *uop, unsigned int count); +int HYPERVISOR_sched_op(int cmd, void *arg); +int HYPERVISOR_event_channel_op(int cmd, void *arg); +unsigned long HYPERVISOR_hvm_op(int op, void *arg); +int HYPERVISOR_memory_op(unsigned int cmd, void *arg); +int HYPERVISOR_physdev_op(int cmd, void *arg); + +static inline void +MULTI_update_va_mapping(struct multicall_entry *mcl, unsigned long va, + unsigned int new_val, unsigned long flags) +{ + BUG(); +} + +static inline void +MULTI_mmu_update(struct multicall_entry *mcl, struct mmu_update *req, + int count, int *success_count, domid_t domid) +{ + BUG(); +} + +static inline int +HYPERVISOR_multicall(void *call_list, int nr_calls) +{ + BUG(); +} +#endif /* _ASM_ARM_XEN_HYPERCALL_H */ diff --git a/arch/arm/include/asm/xen/hypervisor.h b/arch/arm/include/asm/xen/hypervisor.h new file mode 100644 index 000000000000..d7ab99a0c9eb --- /dev/null +++ b/arch/arm/include/asm/xen/hypervisor.h @@ -0,0 +1,19 @@ +#ifndef _ASM_ARM_XEN_HYPERVISOR_H +#define _ASM_ARM_XEN_HYPERVISOR_H + +extern struct shared_info *HYPERVISOR_shared_info; +extern struct start_info *xen_start_info; + +/* Lazy mode for batching updates / context switch */ +enum paravirt_lazy_mode { + PARAVIRT_LAZY_NONE, + PARAVIRT_LAZY_MMU, + PARAVIRT_LAZY_CPU, +}; + +static inline enum paravirt_lazy_mode paravirt_get_lazy_mode(void) +{ + return PARAVIRT_LAZY_NONE; +} + +#endif /* _ASM_ARM_XEN_HYPERVISOR_H */ diff --git a/arch/arm/include/asm/xen/interface.h b/arch/arm/include/asm/xen/interface.h new file mode 100644 index 000000000000..5000397134b4 --- /dev/null +++ b/arch/arm/include/asm/xen/interface.h @@ -0,0 +1,79 @@ +/****************************************************************************** + * Guest OS interface to ARM Xen. + * + * Stefano Stabellini <stefano.stabellini@eu.citrix.com>, Citrix, 2012 + */ + +#ifndef _ASM_ARM_XEN_INTERFACE_H +#define _ASM_ARM_XEN_INTERFACE_H + +#include <linux/types.h> + +#define uint64_aligned_t uint64_t __attribute__((aligned(8))) + +#define __DEFINE_GUEST_HANDLE(name, type) \ + typedef struct { union { type *p; uint64_aligned_t q; }; } \ + __guest_handle_ ## name + +#define DEFINE_GUEST_HANDLE_STRUCT(name) \ + __DEFINE_GUEST_HANDLE(name, struct name) +#define DEFINE_GUEST_HANDLE(name) __DEFINE_GUEST_HANDLE(name, name) +#define GUEST_HANDLE(name) __guest_handle_ ## name + +#define set_xen_guest_handle(hnd, val) \ + do { \ + if (sizeof(hnd) == 8) \ + *(uint64_t *)&(hnd) = 0; \ + (hnd).p = val; \ + } while (0) + +#ifndef __ASSEMBLY__ +/* Explicitly size integers that represent pfns in the interface with + * Xen so that we can have one ABI that works for 32 and 64 bit guests. + * Note that this means that the xen_pfn_t type may be capable of + * representing pfn's which the guest cannot represent in its own pfn + * type. However since pfn space is controlled by the guest this is + * fine since it simply wouldn't be able to create any sure pfns in + * the first place. + */ +typedef uint64_t xen_pfn_t; +#define PRI_xen_pfn "llx" +typedef uint64_t xen_ulong_t; +#define PRI_xen_ulong "llx" +/* Guest handles for primitive C types. */ +__DEFINE_GUEST_HANDLE(uchar, unsigned char); +__DEFINE_GUEST_HANDLE(uint, unsigned int); +DEFINE_GUEST_HANDLE(char); +DEFINE_GUEST_HANDLE(int); +DEFINE_GUEST_HANDLE(void); +DEFINE_GUEST_HANDLE(uint64_t); +DEFINE_GUEST_HANDLE(uint32_t); +DEFINE_GUEST_HANDLE(xen_pfn_t); + +/* Maximum number of virtual CPUs in multi-processor guests. */ +#define MAX_VIRT_CPUS 1 + +struct arch_vcpu_info { }; +struct arch_shared_info { }; + +/* TODO: Move pvclock definitions some place arch independent */ +struct pvclock_vcpu_time_info { + u32 version; + u32 pad0; + u64 tsc_timestamp; + u64 system_time; + u32 tsc_to_system_mul; + s8 tsc_shift; + u8 flags; + u8 pad[2]; +} __attribute__((__packed__)); /* 32 bytes */ + +/* It is OK to have a 12 bytes struct with no padding because it is packed */ +struct pvclock_wall_clock { + u32 version; + u32 sec; + u32 nsec; +} __attribute__((__packed__)); +#endif + +#endif /* _ASM_ARM_XEN_INTERFACE_H */ diff --git a/arch/arm/include/asm/xen/page.h b/arch/arm/include/asm/xen/page.h new file mode 100644 index 000000000000..c6b9096cef95 --- /dev/null +++ b/arch/arm/include/asm/xen/page.h @@ -0,0 +1,89 @@ +#ifndef _ASM_ARM_XEN_PAGE_H +#define _ASM_ARM_XEN_PAGE_H + +#include <asm/page.h> +#include <asm/pgtable.h> + +#include <linux/pfn.h> +#include <linux/types.h> + +#include <xen/interface/grant_table.h> + +#define pfn_to_mfn(pfn) (pfn) +#define phys_to_machine_mapping_valid(pfn) (1) +#define mfn_to_pfn(mfn) (mfn) +#define mfn_to_virt(m) (__va(mfn_to_pfn(m) << PAGE_SHIFT)) + +#define pte_mfn pte_pfn +#define mfn_pte pfn_pte + +/* Xen machine address */ +typedef struct xmaddr { + phys_addr_t maddr; +} xmaddr_t; + +/* Xen pseudo-physical address */ +typedef struct xpaddr { + phys_addr_t paddr; +} xpaddr_t; + +#define XMADDR(x) ((xmaddr_t) { .maddr = (x) }) +#define XPADDR(x) ((xpaddr_t) { .paddr = (x) }) + +#define INVALID_P2M_ENTRY (~0UL) + +static inline xmaddr_t phys_to_machine(xpaddr_t phys) +{ + unsigned offset = phys.paddr & ~PAGE_MASK; + return XMADDR(PFN_PHYS(pfn_to_mfn(PFN_DOWN(phys.paddr))) | offset); +} + +static inline xpaddr_t machine_to_phys(xmaddr_t machine) +{ + unsigned offset = machine.maddr & ~PAGE_MASK; + return XPADDR(PFN_PHYS(mfn_to_pfn(PFN_DOWN(machine.maddr))) | offset); +} +/* VIRT <-> MACHINE conversion */ +#define virt_to_machine(v) (phys_to_machine(XPADDR(__pa(v)))) +#define virt_to_pfn(v) (PFN_DOWN(__pa(v))) +#define virt_to_mfn(v) (pfn_to_mfn(virt_to_pfn(v))) +#define mfn_to_virt(m) (__va(mfn_to_pfn(m) << PAGE_SHIFT)) + +static inline xmaddr_t arbitrary_virt_to_machine(void *vaddr) +{ + /* TODO: assuming it is mapped in the kernel 1:1 */ + return virt_to_machine(vaddr); +} + +/* TODO: this shouldn't be here but it is because the frontend drivers + * are using it (its rolled in headers) even though we won't hit the code path. + * So for right now just punt with this. + */ +static inline pte_t *lookup_address(unsigned long address, unsigned int *level) +{ + BUG(); + return NULL; +} + +static inline int m2p_add_override(unsigned long mfn, struct page *page, + struct gnttab_map_grant_ref *kmap_op) +{ + return 0; +} + +static inline int m2p_remove_override(struct page *page, bool clear_pte) +{ + return 0; +} + +static inline bool __set_phys_to_machine(unsigned long pfn, unsigned long mfn) +{ + BUG_ON(pfn != mfn && mfn != INVALID_P2M_ENTRY); + return true; +} + +static inline bool set_phys_to_machine(unsigned long pfn, unsigned long mfn) +{ + return __set_phys_to_machine(pfn, mfn); +} +#endif /* _ASM_ARM_XEN_PAGE_H */ diff --git a/arch/arm/include/debug/8250_32.S b/arch/arm/include/debug/8250_32.S new file mode 100644 index 000000000000..8db01eeabbb4 --- /dev/null +++ b/arch/arm/include/debug/8250_32.S @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2011 Picochip Ltd., Jamie Iles + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Derived from arch/arm/mach-davinci/include/mach/debug-macro.S to use 32-bit + * accesses to the 8250. + */ + +#include <linux/serial_reg.h> + + .macro senduart,rd,rx + str \rd, [\rx, #UART_TX << UART_SHIFT] + .endm + + .macro busyuart,rd,rx +1002: ldr \rd, [\rx, #UART_LSR << UART_SHIFT] + and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE + teq \rd, #UART_LSR_TEMT | UART_LSR_THRE + bne 1002b + .endm + + /* The UART's don't have any flow control IO's wired up. */ + .macro waituart,rd,rx + .endm diff --git a/arch/arm/include/debug/picoxcell.S b/arch/arm/include/debug/picoxcell.S index 7419deb1b948..bc1f07c49cd4 100644 --- a/arch/arm/include/debug/picoxcell.S +++ b/arch/arm/include/debug/picoxcell.S @@ -5,10 +5,7 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * - * Derived from arch/arm/mach-davinci/include/mach/debug-macro.S to use 32-bit - * accesses to the 8250. */ -#include <linux/serial_reg.h> #define UART_SHIFT 2 #define PICOXCELL_UART1_BASE 0x80230000 @@ -19,17 +16,4 @@ ldr \rp, =PICOXCELL_UART1_BASE .endm - .macro senduart,rd,rx - str \rd, [\rx, #UART_TX << UART_SHIFT] - .endm - - .macro busyuart,rd,rx -1002: ldr \rd, [\rx, #UART_LSR << UART_SHIFT] - and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE - teq \rd, #UART_LSR_TEMT | UART_LSR_THRE - bne 1002b - .endm - - /* The UART's don't have any flow control IO's wired up. */ - .macro waituart,rd,rx - .endm +#include "8250_32.S" diff --git a/arch/arm/include/debug/socfpga.S b/arch/arm/include/debug/socfpga.S index d6f26d23374f..966b2f994946 100644 --- a/arch/arm/include/debug/socfpga.S +++ b/arch/arm/include/debug/socfpga.S @@ -7,6 +7,9 @@ * published by the Free Software Foundation. */ +#define UART_SHIFT 2 +#define DEBUG_LL_UART_OFFSET 0x00002000 + .macro addruart, rp, rv, tmp mov \rp, #DEBUG_LL_UART_OFFSET orr \rp, \rp, #0x00c00000 @@ -14,3 +17,5 @@ orr \rp, \rp, #0xff000000 @ physical base .endm +#include "8250_32.S" + diff --git a/arch/arm/include/uapi/asm/Kbuild b/arch/arm/include/uapi/asm/Kbuild index baebb3da1d44..47bcb2d254af 100644 --- a/arch/arm/include/uapi/asm/Kbuild +++ b/arch/arm/include/uapi/asm/Kbuild @@ -1,3 +1,19 @@ # UAPI Header export list include include/uapi/asm-generic/Kbuild.asm +header-y += a.out.h +header-y += byteorder.h +header-y += fcntl.h +header-y += hwcap.h +header-y += ioctls.h +header-y += kvm_para.h +header-y += mman.h +header-y += posix_types.h +header-y += ptrace.h +header-y += setup.h +header-y += sigcontext.h +header-y += signal.h +header-y += stat.h +header-y += statfs.h +header-y += swab.h +header-y += unistd.h diff --git a/arch/arm/include/asm/a.out.h b/arch/arm/include/uapi/asm/a.out.h index 083894b2e3bc..083894b2e3bc 100644 --- a/arch/arm/include/asm/a.out.h +++ b/arch/arm/include/uapi/asm/a.out.h diff --git a/arch/arm/include/asm/byteorder.h b/arch/arm/include/uapi/asm/byteorder.h index 77379748b171..77379748b171 100644 --- a/arch/arm/include/asm/byteorder.h +++ b/arch/arm/include/uapi/asm/byteorder.h diff --git a/arch/arm/include/asm/fcntl.h b/arch/arm/include/uapi/asm/fcntl.h index a80b6607b2ef..a80b6607b2ef 100644 --- a/arch/arm/include/asm/fcntl.h +++ b/arch/arm/include/uapi/asm/fcntl.h diff --git a/arch/arm/include/uapi/asm/hwcap.h b/arch/arm/include/uapi/asm/hwcap.h new file mode 100644 index 000000000000..f254f6503cce --- /dev/null +++ b/arch/arm/include/uapi/asm/hwcap.h @@ -0,0 +1,29 @@ +#ifndef _UAPI__ASMARM_HWCAP_H +#define _UAPI__ASMARM_HWCAP_H + +/* + * HWCAP flags - for elf_hwcap (in kernel) and AT_HWCAP + */ +#define HWCAP_SWP (1 << 0) +#define HWCAP_HALF (1 << 1) +#define HWCAP_THUMB (1 << 2) +#define HWCAP_26BIT (1 << 3) /* Play it safe */ +#define HWCAP_FAST_MULT (1 << 4) +#define HWCAP_FPA (1 << 5) +#define HWCAP_VFP (1 << 6) +#define HWCAP_EDSP (1 << 7) +#define HWCAP_JAVA (1 << 8) +#define HWCAP_IWMMXT (1 << 9) +#define HWCAP_CRUNCH (1 << 10) +#define HWCAP_THUMBEE (1 << 11) +#define HWCAP_NEON (1 << 12) +#define HWCAP_VFPv3 (1 << 13) +#define HWCAP_VFPv3D16 (1 << 14) +#define HWCAP_TLS (1 << 15) +#define HWCAP_VFPv4 (1 << 16) +#define HWCAP_IDIVA (1 << 17) +#define HWCAP_IDIVT (1 << 18) +#define HWCAP_IDIV (HWCAP_IDIVA | HWCAP_IDIVT) + + +#endif /* _UAPI__ASMARM_HWCAP_H */ diff --git a/arch/arm/include/asm/ioctls.h b/arch/arm/include/uapi/asm/ioctls.h index 9c9629816128..9c9629816128 100644 --- a/arch/arm/include/asm/ioctls.h +++ b/arch/arm/include/uapi/asm/ioctls.h diff --git a/arch/arm/include/asm/kvm_para.h b/arch/arm/include/uapi/asm/kvm_para.h index 14fab8f0b957..14fab8f0b957 100644 --- a/arch/arm/include/asm/kvm_para.h +++ b/arch/arm/include/uapi/asm/kvm_para.h diff --git a/arch/arm/include/asm/mman.h b/arch/arm/include/uapi/asm/mman.h index 41f99c573b93..41f99c573b93 100644 --- a/arch/arm/include/asm/mman.h +++ b/arch/arm/include/uapi/asm/mman.h diff --git a/arch/arm/include/asm/posix_types.h b/arch/arm/include/uapi/asm/posix_types.h index d2de9cbbcd9b..d2de9cbbcd9b 100644 --- a/arch/arm/include/asm/posix_types.h +++ b/arch/arm/include/uapi/asm/posix_types.h diff --git a/arch/arm/include/uapi/asm/ptrace.h b/arch/arm/include/uapi/asm/ptrace.h new file mode 100644 index 000000000000..96ee0929790f --- /dev/null +++ b/arch/arm/include/uapi/asm/ptrace.h @@ -0,0 +1,138 @@ +/* + * arch/arm/include/asm/ptrace.h + * + * Copyright (C) 1996-2003 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef _UAPI__ASM_ARM_PTRACE_H +#define _UAPI__ASM_ARM_PTRACE_H + +#include <asm/hwcap.h> + +#define PTRACE_GETREGS 12 +#define PTRACE_SETREGS 13 +#define PTRACE_GETFPREGS 14 +#define PTRACE_SETFPREGS 15 +/* PTRACE_ATTACH is 16 */ +/* PTRACE_DETACH is 17 */ +#define PTRACE_GETWMMXREGS 18 +#define PTRACE_SETWMMXREGS 19 +/* 20 is unused */ +#define PTRACE_OLDSETOPTIONS 21 +#define PTRACE_GET_THREAD_AREA 22 +#define PTRACE_SET_SYSCALL 23 +/* PTRACE_SYSCALL is 24 */ +#define PTRACE_GETCRUNCHREGS 25 +#define PTRACE_SETCRUNCHREGS 26 +#define PTRACE_GETVFPREGS 27 +#define PTRACE_SETVFPREGS 28 +#define PTRACE_GETHBPREGS 29 +#define PTRACE_SETHBPREGS 30 + +/* + * PSR bits + */ +#define USR26_MODE 0x00000000 +#define FIQ26_MODE 0x00000001 +#define IRQ26_MODE 0x00000002 +#define SVC26_MODE 0x00000003 +#define USR_MODE 0x00000010 +#define FIQ_MODE 0x00000011 +#define IRQ_MODE 0x00000012 +#define SVC_MODE 0x00000013 +#define ABT_MODE 0x00000017 +#define HYP_MODE 0x0000001a +#define UND_MODE 0x0000001b +#define SYSTEM_MODE 0x0000001f +#define MODE32_BIT 0x00000010 +#define MODE_MASK 0x0000001f +#define PSR_T_BIT 0x00000020 +#define PSR_F_BIT 0x00000040 +#define PSR_I_BIT 0x00000080 +#define PSR_A_BIT 0x00000100 +#define PSR_E_BIT 0x00000200 +#define PSR_J_BIT 0x01000000 +#define PSR_Q_BIT 0x08000000 +#define PSR_V_BIT 0x10000000 +#define PSR_C_BIT 0x20000000 +#define PSR_Z_BIT 0x40000000 +#define PSR_N_BIT 0x80000000 + +/* + * Groups of PSR bits + */ +#define PSR_f 0xff000000 /* Flags */ +#define PSR_s 0x00ff0000 /* Status */ +#define PSR_x 0x0000ff00 /* Extension */ +#define PSR_c 0x000000ff /* Control */ + +/* + * ARMv7 groups of PSR bits + */ +#define APSR_MASK 0xf80f0000 /* N, Z, C, V, Q and GE flags */ +#define PSR_ISET_MASK 0x01000010 /* ISA state (J, T) mask */ +#define PSR_IT_MASK 0x0600fc00 /* If-Then execution state mask */ +#define PSR_ENDIAN_MASK 0x00000200 /* Endianness state mask */ + +/* + * Default endianness state + */ +#ifdef CONFIG_CPU_ENDIAN_BE8 +#define PSR_ENDSTATE PSR_E_BIT +#else +#define PSR_ENDSTATE 0 +#endif + +/* + * These are 'magic' values for PTRACE_PEEKUSR that return info about where a + * process is located in memory. + */ +#define PT_TEXT_ADDR 0x10000 +#define PT_DATA_ADDR 0x10004 +#define PT_TEXT_END_ADDR 0x10008 + +#ifndef __ASSEMBLY__ + +/* + * This struct defines the way the registers are stored on the + * stack during a system call. Note that sizeof(struct pt_regs) + * has to be a multiple of 8. + */ +#ifndef __KERNEL__ +struct pt_regs { + long uregs[18]; +}; +#endif /* __KERNEL__ */ + +#define ARM_cpsr uregs[16] +#define ARM_pc uregs[15] +#define ARM_lr uregs[14] +#define ARM_sp uregs[13] +#define ARM_ip uregs[12] +#define ARM_fp uregs[11] +#define ARM_r10 uregs[10] +#define ARM_r9 uregs[9] +#define ARM_r8 uregs[8] +#define ARM_r7 uregs[7] +#define ARM_r6 uregs[6] +#define ARM_r5 uregs[5] +#define ARM_r4 uregs[4] +#define ARM_r3 uregs[3] +#define ARM_r2 uregs[2] +#define ARM_r1 uregs[1] +#define ARM_r0 uregs[0] +#define ARM_ORIG_r0 uregs[17] + +/* + * The size of the user-visible VFP state as seen by PTRACE_GET/SETVFPREGS + * and core dumps. + */ +#define ARM_VFPREGS_SIZE ( 32 * 8 /*fpregs*/ + 4 /*fpscr*/ ) + + +#endif /* __ASSEMBLY__ */ + +#endif /* _UAPI__ASM_ARM_PTRACE_H */ diff --git a/arch/arm/include/uapi/asm/setup.h b/arch/arm/include/uapi/asm/setup.h new file mode 100644 index 000000000000..979ff4016404 --- /dev/null +++ b/arch/arm/include/uapi/asm/setup.h @@ -0,0 +1,187 @@ +/* + * linux/include/asm/setup.h + * + * Copyright (C) 1997-1999 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Structure passed to kernel to tell it about the + * hardware it's running on. See Documentation/arm/Setup + * for more info. + */ +#ifndef _UAPI__ASMARM_SETUP_H +#define _UAPI__ASMARM_SETUP_H + +#include <linux/types.h> + +#define COMMAND_LINE_SIZE 1024 + +/* The list ends with an ATAG_NONE node. */ +#define ATAG_NONE 0x00000000 + +struct tag_header { + __u32 size; + __u32 tag; +}; + +/* The list must start with an ATAG_CORE node */ +#define ATAG_CORE 0x54410001 + +struct tag_core { + __u32 flags; /* bit 0 = read-only */ + __u32 pagesize; + __u32 rootdev; +}; + +/* it is allowed to have multiple ATAG_MEM nodes */ +#define ATAG_MEM 0x54410002 + +struct tag_mem32 { + __u32 size; + __u32 start; /* physical start address */ +}; + +/* VGA text type displays */ +#define ATAG_VIDEOTEXT 0x54410003 + +struct tag_videotext { + __u8 x; + __u8 y; + __u16 video_page; + __u8 video_mode; + __u8 video_cols; + __u16 video_ega_bx; + __u8 video_lines; + __u8 video_isvga; + __u16 video_points; +}; + +/* describes how the ramdisk will be used in kernel */ +#define ATAG_RAMDISK 0x54410004 + +struct tag_ramdisk { + __u32 flags; /* bit 0 = load, bit 1 = prompt */ + __u32 size; /* decompressed ramdisk size in _kilo_ bytes */ + __u32 start; /* starting block of floppy-based RAM disk image */ +}; + +/* describes where the compressed ramdisk image lives (virtual address) */ +/* + * this one accidentally used virtual addresses - as such, + * it's deprecated. + */ +#define ATAG_INITRD 0x54410005 + +/* describes where the compressed ramdisk image lives (physical address) */ +#define ATAG_INITRD2 0x54420005 + +struct tag_initrd { + __u32 start; /* physical start address */ + __u32 size; /* size of compressed ramdisk image in bytes */ +}; + +/* board serial number. "64 bits should be enough for everybody" */ +#define ATAG_SERIAL 0x54410006 + +struct tag_serialnr { + __u32 low; + __u32 high; +}; + +/* board revision */ +#define ATAG_REVISION 0x54410007 + +struct tag_revision { + __u32 rev; +}; + +/* initial values for vesafb-type framebuffers. see struct screen_info + * in include/linux/tty.h + */ +#define ATAG_VIDEOLFB 0x54410008 + +struct tag_videolfb { + __u16 lfb_width; + __u16 lfb_height; + __u16 lfb_depth; + __u16 lfb_linelength; + __u32 lfb_base; + __u32 lfb_size; + __u8 red_size; + __u8 red_pos; + __u8 green_size; + __u8 green_pos; + __u8 blue_size; + __u8 blue_pos; + __u8 rsvd_size; + __u8 rsvd_pos; +}; + +/* command line: \0 terminated string */ +#define ATAG_CMDLINE 0x54410009 + +struct tag_cmdline { + char cmdline[1]; /* this is the minimum size */ +}; + +/* acorn RiscPC specific information */ +#define ATAG_ACORN 0x41000101 + +struct tag_acorn { + __u32 memc_control_reg; + __u32 vram_pages; + __u8 sounddefault; + __u8 adfsdrives; +}; + +/* footbridge memory clock, see arch/arm/mach-footbridge/arch.c */ +#define ATAG_MEMCLK 0x41000402 + +struct tag_memclk { + __u32 fmemclk; +}; + +struct tag { + struct tag_header hdr; + union { + struct tag_core core; + struct tag_mem32 mem; + struct tag_videotext videotext; + struct tag_ramdisk ramdisk; + struct tag_initrd initrd; + struct tag_serialnr serialnr; + struct tag_revision revision; + struct tag_videolfb videolfb; + struct tag_cmdline cmdline; + + /* + * Acorn specific + */ + struct tag_acorn acorn; + + /* + * DC21285 specific + */ + struct tag_memclk memclk; + } u; +}; + +struct tagtable { + __u32 tag; + int (*parse)(const struct tag *); +}; + +#define tag_member_present(tag,member) \ + ((unsigned long)(&((struct tag *)0L)->member + 1) \ + <= (tag)->hdr.size * 4) + +#define tag_next(t) ((struct tag *)((__u32 *)(t) + (t)->hdr.size)) +#define tag_size(type) ((sizeof(struct tag_header) + sizeof(struct type)) >> 2) + +#define for_each_tag(t,base) \ + for (t = base; t->hdr.size; t = tag_next(t)) + + +#endif /* _UAPI__ASMARM_SETUP_H */ diff --git a/arch/arm/include/asm/sigcontext.h b/arch/arm/include/uapi/asm/sigcontext.h index fc0b80b6a6fc..fc0b80b6a6fc 100644 --- a/arch/arm/include/asm/sigcontext.h +++ b/arch/arm/include/uapi/asm/sigcontext.h diff --git a/arch/arm/include/uapi/asm/signal.h b/arch/arm/include/uapi/asm/signal.h new file mode 100644 index 000000000000..921c57fdc52e --- /dev/null +++ b/arch/arm/include/uapi/asm/signal.h @@ -0,0 +1,127 @@ +#ifndef _UAPI_ASMARM_SIGNAL_H +#define _UAPI_ASMARM_SIGNAL_H + +#include <linux/types.h> + +/* Avoid too many header ordering problems. */ +struct siginfo; + +#ifndef __KERNEL__ +/* Here we must cater to libcs that poke about in kernel headers. */ + +#define NSIG 32 +typedef unsigned long sigset_t; + +#endif /* __KERNEL__ */ + +#define SIGHUP 1 +#define SIGINT 2 +#define SIGQUIT 3 +#define SIGILL 4 +#define SIGTRAP 5 +#define SIGABRT 6 +#define SIGIOT 6 +#define SIGBUS 7 +#define SIGFPE 8 +#define SIGKILL 9 +#define SIGUSR1 10 +#define SIGSEGV 11 +#define SIGUSR2 12 +#define SIGPIPE 13 +#define SIGALRM 14 +#define SIGTERM 15 +#define SIGSTKFLT 16 +#define SIGCHLD 17 +#define SIGCONT 18 +#define SIGSTOP 19 +#define SIGTSTP 20 +#define SIGTTIN 21 +#define SIGTTOU 22 +#define SIGURG 23 +#define SIGXCPU 24 +#define SIGXFSZ 25 +#define SIGVTALRM 26 +#define SIGPROF 27 +#define SIGWINCH 28 +#define SIGIO 29 +#define SIGPOLL SIGIO +/* +#define SIGLOST 29 +*/ +#define SIGPWR 30 +#define SIGSYS 31 +#define SIGUNUSED 31 + +/* These should not be considered constants from userland. */ +#define SIGRTMIN 32 +#define SIGRTMAX _NSIG + +#define SIGSWI 32 + +/* + * SA_FLAGS values: + * + * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. + * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. + * SA_SIGINFO deliver the signal with SIGINFO structs + * SA_THIRTYTWO delivers the signal in 32-bit mode, even if the task + * is running in 26-bit. + * SA_ONSTACK allows alternate signal stacks (see sigaltstack(2)). + * SA_RESTART flag to get restarting signals (which were the default long ago) + * SA_NODEFER prevents the current signal from being masked in the handler. + * SA_RESETHAND clears the handler when the signal is delivered. + * + * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single + * Unix names RESETHAND and NODEFER respectively. + */ +#define SA_NOCLDSTOP 0x00000001 +#define SA_NOCLDWAIT 0x00000002 +#define SA_SIGINFO 0x00000004 +#define SA_THIRTYTWO 0x02000000 +#define SA_RESTORER 0x04000000 +#define SA_ONSTACK 0x08000000 +#define SA_RESTART 0x10000000 +#define SA_NODEFER 0x40000000 +#define SA_RESETHAND 0x80000000 + +#define SA_NOMASK SA_NODEFER +#define SA_ONESHOT SA_RESETHAND + + +/* + * sigaltstack controls + */ +#define SS_ONSTACK 1 +#define SS_DISABLE 2 + +#define MINSIGSTKSZ 2048 +#define SIGSTKSZ 8192 + +#include <asm-generic/signal-defs.h> + +#ifndef __KERNEL__ +/* Here we must cater to libcs that poke about in kernel headers. */ + +struct sigaction { + union { + __sighandler_t _sa_handler; + void (*_sa_sigaction)(int, struct siginfo *, void *); + } _u; + sigset_t sa_mask; + unsigned long sa_flags; + void (*sa_restorer)(void); +}; + +#define sa_handler _u._sa_handler +#define sa_sigaction _u._sa_sigaction + +#endif /* __KERNEL__ */ + +typedef struct sigaltstack { + void __user *ss_sp; + int ss_flags; + size_t ss_size; +} stack_t; + + +#endif /* _UAPI_ASMARM_SIGNAL_H */ diff --git a/arch/arm/include/asm/stat.h b/arch/arm/include/uapi/asm/stat.h index 42c0c13999d5..42c0c13999d5 100644 --- a/arch/arm/include/asm/stat.h +++ b/arch/arm/include/uapi/asm/stat.h diff --git a/arch/arm/include/asm/statfs.h b/arch/arm/include/uapi/asm/statfs.h index 079447c05ba7..079447c05ba7 100644 --- a/arch/arm/include/asm/statfs.h +++ b/arch/arm/include/uapi/asm/statfs.h diff --git a/arch/arm/include/uapi/asm/swab.h b/arch/arm/include/uapi/asm/swab.h new file mode 100644 index 000000000000..6fcb32a5c453 --- /dev/null +++ b/arch/arm/include/uapi/asm/swab.h @@ -0,0 +1,53 @@ +/* + * arch/arm/include/asm/byteorder.h + * + * ARM Endian-ness. In little endian mode, the data bus is connected such + * that byte accesses appear as: + * 0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31 + * and word accesses (data or instruction) appear as: + * d0...d31 + * + * When in big endian mode, byte accesses appear as: + * 0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7 + * and word accesses (data or instruction) appear as: + * d0...d31 + */ +#ifndef _UAPI__ASM_ARM_SWAB_H +#define _UAPI__ASM_ARM_SWAB_H + +#include <linux/compiler.h> +#include <linux/types.h> + +#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) +# define __SWAB_64_THRU_32__ +#endif + + +#if !defined(__KERNEL__) || __LINUX_ARM_ARCH__ < 6 +static inline __attribute_const__ __u32 __arch_swab32(__u32 x) +{ + __u32 t; + +#ifndef __thumb__ + if (!__builtin_constant_p(x)) { + /* + * The compiler needs a bit of a hint here to always do the + * right thing and not screw it up to different degrees + * depending on the gcc version. + */ + asm ("eor\t%0, %1, %1, ror #16" : "=r" (t) : "r" (x)); + } else +#endif + t = x ^ ((x << 16) | (x >> 16)); /* eor r1,r0,r0,ror #16 */ + + x = (x << 24) | (x >> 8); /* mov r0,r0,ror #8 */ + t &= ~0x00FF0000; /* bic r1,r1,#0x00FF0000 */ + x ^= (t >> 8); /* eor r0,r0,r1,lsr #8 */ + + return x; +} +#define __arch_swab32 __arch_swab32 + +#endif + +#endif /* _UAPI__ASM_ARM_SWAB_H */ diff --git a/arch/arm/include/uapi/asm/unistd.h b/arch/arm/include/uapi/asm/unistd.h new file mode 100644 index 000000000000..ac03bdb4ae44 --- /dev/null +++ b/arch/arm/include/uapi/asm/unistd.h @@ -0,0 +1,450 @@ +/* + * arch/arm/include/asm/unistd.h + * + * Copyright (C) 2001-2005 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Please forward _all_ changes to this file to rmk@arm.linux.org.uk, + * no matter what the change is. Thanks! + */ +#ifndef _UAPI__ASM_ARM_UNISTD_H +#define _UAPI__ASM_ARM_UNISTD_H + +#define __NR_OABI_SYSCALL_BASE 0x900000 + +#if defined(__thumb__) || defined(__ARM_EABI__) +#define __NR_SYSCALL_BASE 0 +#else +#define __NR_SYSCALL_BASE __NR_OABI_SYSCALL_BASE +#endif + +/* + * This file contains the system call numbers. + */ + +#define __NR_restart_syscall (__NR_SYSCALL_BASE+ 0) +#define __NR_exit (__NR_SYSCALL_BASE+ 1) +#define __NR_fork (__NR_SYSCALL_BASE+ 2) +#define __NR_read (__NR_SYSCALL_BASE+ 3) +#define __NR_write (__NR_SYSCALL_BASE+ 4) +#define __NR_open (__NR_SYSCALL_BASE+ 5) +#define __NR_close (__NR_SYSCALL_BASE+ 6) + /* 7 was sys_waitpid */ +#define __NR_creat (__NR_SYSCALL_BASE+ 8) +#define __NR_link (__NR_SYSCALL_BASE+ 9) +#define __NR_unlink (__NR_SYSCALL_BASE+ 10) +#define __NR_execve (__NR_SYSCALL_BASE+ 11) +#define __NR_chdir (__NR_SYSCALL_BASE+ 12) +#define __NR_time (__NR_SYSCALL_BASE+ 13) +#define __NR_mknod (__NR_SYSCALL_BASE+ 14) +#define __NR_chmod (__NR_SYSCALL_BASE+ 15) +#define __NR_lchown (__NR_SYSCALL_BASE+ 16) + /* 17 was sys_break */ + /* 18 was sys_stat */ +#define __NR_lseek (__NR_SYSCALL_BASE+ 19) +#define __NR_getpid (__NR_SYSCALL_BASE+ 20) +#define __NR_mount (__NR_SYSCALL_BASE+ 21) +#define __NR_umount (__NR_SYSCALL_BASE+ 22) +#define __NR_setuid (__NR_SYSCALL_BASE+ 23) +#define __NR_getuid (__NR_SYSCALL_BASE+ 24) +#define __NR_stime (__NR_SYSCALL_BASE+ 25) +#define __NR_ptrace (__NR_SYSCALL_BASE+ 26) +#define __NR_alarm (__NR_SYSCALL_BASE+ 27) + /* 28 was sys_fstat */ +#define __NR_pause (__NR_SYSCALL_BASE+ 29) +#define __NR_utime (__NR_SYSCALL_BASE+ 30) + /* 31 was sys_stty */ + /* 32 was sys_gtty */ +#define __NR_access (__NR_SYSCALL_BASE+ 33) +#define __NR_nice (__NR_SYSCALL_BASE+ 34) + /* 35 was sys_ftime */ +#define __NR_sync (__NR_SYSCALL_BASE+ 36) +#define __NR_kill (__NR_SYSCALL_BASE+ 37) +#define __NR_rename (__NR_SYSCALL_BASE+ 38) +#define __NR_mkdir (__NR_SYSCALL_BASE+ 39) +#define __NR_rmdir (__NR_SYSCALL_BASE+ 40) +#define __NR_dup (__NR_SYSCALL_BASE+ 41) +#define __NR_pipe (__NR_SYSCALL_BASE+ 42) +#define __NR_times (__NR_SYSCALL_BASE+ 43) + /* 44 was sys_prof */ +#define __NR_brk (__NR_SYSCALL_BASE+ 45) +#define __NR_setgid (__NR_SYSCALL_BASE+ 46) +#define __NR_getgid (__NR_SYSCALL_BASE+ 47) + /* 48 was sys_signal */ +#define __NR_geteuid (__NR_SYSCALL_BASE+ 49) +#define __NR_getegid (__NR_SYSCALL_BASE+ 50) +#define __NR_acct (__NR_SYSCALL_BASE+ 51) +#define __NR_umount2 (__NR_SYSCALL_BASE+ 52) + /* 53 was sys_lock */ +#define __NR_ioctl (__NR_SYSCALL_BASE+ 54) +#define __NR_fcntl (__NR_SYSCALL_BASE+ 55) + /* 56 was sys_mpx */ +#define __NR_setpgid (__NR_SYSCALL_BASE+ 57) + /* 58 was sys_ulimit */ + /* 59 was sys_olduname */ +#define __NR_umask (__NR_SYSCALL_BASE+ 60) +#define __NR_chroot (__NR_SYSCALL_BASE+ 61) +#define __NR_ustat (__NR_SYSCALL_BASE+ 62) +#define __NR_dup2 (__NR_SYSCALL_BASE+ 63) +#define __NR_getppid (__NR_SYSCALL_BASE+ 64) +#define __NR_getpgrp (__NR_SYSCALL_BASE+ 65) +#define __NR_setsid (__NR_SYSCALL_BASE+ 66) +#define __NR_sigaction (__NR_SYSCALL_BASE+ 67) + /* 68 was sys_sgetmask */ + /* 69 was sys_ssetmask */ +#define __NR_setreuid (__NR_SYSCALL_BASE+ 70) +#define __NR_setregid (__NR_SYSCALL_BASE+ 71) +#define __NR_sigsuspend (__NR_SYSCALL_BASE+ 72) +#define __NR_sigpending (__NR_SYSCALL_BASE+ 73) +#define __NR_sethostname (__NR_SYSCALL_BASE+ 74) +#define __NR_setrlimit (__NR_SYSCALL_BASE+ 75) +#define __NR_getrlimit (__NR_SYSCALL_BASE+ 76) /* Back compat 2GB limited rlimit */ +#define __NR_getrusage (__NR_SYSCALL_BASE+ 77) +#define __NR_gettimeofday (__NR_SYSCALL_BASE+ 78) +#define __NR_settimeofday (__NR_SYSCALL_BASE+ 79) +#define __NR_getgroups (__NR_SYSCALL_BASE+ 80) +#define __NR_setgroups (__NR_SYSCALL_BASE+ 81) +#define __NR_select (__NR_SYSCALL_BASE+ 82) +#define __NR_symlink (__NR_SYSCALL_BASE+ 83) + /* 84 was sys_lstat */ +#define __NR_readlink (__NR_SYSCALL_BASE+ 85) +#define __NR_uselib (__NR_SYSCALL_BASE+ 86) +#define __NR_swapon (__NR_SYSCALL_BASE+ 87) +#define __NR_reboot (__NR_SYSCALL_BASE+ 88) +#define __NR_readdir (__NR_SYSCALL_BASE+ 89) +#define __NR_mmap (__NR_SYSCALL_BASE+ 90) +#define __NR_munmap (__NR_SYSCALL_BASE+ 91) +#define __NR_truncate (__NR_SYSCALL_BASE+ 92) +#define __NR_ftruncate (__NR_SYSCALL_BASE+ 93) +#define __NR_fchmod (__NR_SYSCALL_BASE+ 94) +#define __NR_fchown (__NR_SYSCALL_BASE+ 95) +#define __NR_getpriority (__NR_SYSCALL_BASE+ 96) +#define __NR_setpriority (__NR_SYSCALL_BASE+ 97) + /* 98 was sys_profil */ +#define __NR_statfs (__NR_SYSCALL_BASE+ 99) +#define __NR_fstatfs (__NR_SYSCALL_BASE+100) + /* 101 was sys_ioperm */ +#define __NR_socketcall (__NR_SYSCALL_BASE+102) +#define __NR_syslog (__NR_SYSCALL_BASE+103) +#define __NR_setitimer (__NR_SYSCALL_BASE+104) +#define __NR_getitimer (__NR_SYSCALL_BASE+105) +#define __NR_stat (__NR_SYSCALL_BASE+106) +#define __NR_lstat (__NR_SYSCALL_BASE+107) +#define __NR_fstat (__NR_SYSCALL_BASE+108) + /* 109 was sys_uname */ + /* 110 was sys_iopl */ +#define __NR_vhangup (__NR_SYSCALL_BASE+111) + /* 112 was sys_idle */ +#define __NR_syscall (__NR_SYSCALL_BASE+113) /* syscall to call a syscall! */ +#define __NR_wait4 (__NR_SYSCALL_BASE+114) +#define __NR_swapoff (__NR_SYSCALL_BASE+115) +#define __NR_sysinfo (__NR_SYSCALL_BASE+116) +#define __NR_ipc (__NR_SYSCALL_BASE+117) +#define __NR_fsync (__NR_SYSCALL_BASE+118) +#define __NR_sigreturn (__NR_SYSCALL_BASE+119) +#define __NR_clone (__NR_SYSCALL_BASE+120) +#define __NR_setdomainname (__NR_SYSCALL_BASE+121) +#define __NR_uname (__NR_SYSCALL_BASE+122) + /* 123 was sys_modify_ldt */ +#define __NR_adjtimex (__NR_SYSCALL_BASE+124) +#define __NR_mprotect (__NR_SYSCALL_BASE+125) +#define __NR_sigprocmask (__NR_SYSCALL_BASE+126) + /* 127 was sys_create_module */ +#define __NR_init_module (__NR_SYSCALL_BASE+128) +#define __NR_delete_module (__NR_SYSCALL_BASE+129) + /* 130 was sys_get_kernel_syms */ +#define __NR_quotactl (__NR_SYSCALL_BASE+131) +#define __NR_getpgid (__NR_SYSCALL_BASE+132) +#define __NR_fchdir (__NR_SYSCALL_BASE+133) +#define __NR_bdflush (__NR_SYSCALL_BASE+134) +#define __NR_sysfs (__NR_SYSCALL_BASE+135) +#define __NR_personality (__NR_SYSCALL_BASE+136) + /* 137 was sys_afs_syscall */ +#define __NR_setfsuid (__NR_SYSCALL_BASE+138) +#define __NR_setfsgid (__NR_SYSCALL_BASE+139) +#define __NR__llseek (__NR_SYSCALL_BASE+140) +#define __NR_getdents (__NR_SYSCALL_BASE+141) +#define __NR__newselect (__NR_SYSCALL_BASE+142) +#define __NR_flock (__NR_SYSCALL_BASE+143) +#define __NR_msync (__NR_SYSCALL_BASE+144) +#define __NR_readv (__NR_SYSCALL_BASE+145) +#define __NR_writev (__NR_SYSCALL_BASE+146) +#define __NR_getsid (__NR_SYSCALL_BASE+147) +#define __NR_fdatasync (__NR_SYSCALL_BASE+148) +#define __NR__sysctl (__NR_SYSCALL_BASE+149) +#define __NR_mlock (__NR_SYSCALL_BASE+150) +#define __NR_munlock (__NR_SYSCALL_BASE+151) +#define __NR_mlockall (__NR_SYSCALL_BASE+152) +#define __NR_munlockall (__NR_SYSCALL_BASE+153) +#define __NR_sched_setparam (__NR_SYSCALL_BASE+154) +#define __NR_sched_getparam (__NR_SYSCALL_BASE+155) +#define __NR_sched_setscheduler (__NR_SYSCALL_BASE+156) +#define __NR_sched_getscheduler (__NR_SYSCALL_BASE+157) +#define __NR_sched_yield (__NR_SYSCALL_BASE+158) +#define __NR_sched_get_priority_max (__NR_SYSCALL_BASE+159) +#define __NR_sched_get_priority_min (__NR_SYSCALL_BASE+160) +#define __NR_sched_rr_get_interval (__NR_SYSCALL_BASE+161) +#define __NR_nanosleep (__NR_SYSCALL_BASE+162) +#define __NR_mremap (__NR_SYSCALL_BASE+163) +#define __NR_setresuid (__NR_SYSCALL_BASE+164) +#define __NR_getresuid (__NR_SYSCALL_BASE+165) + /* 166 was sys_vm86 */ + /* 167 was sys_query_module */ +#define __NR_poll (__NR_SYSCALL_BASE+168) +#define __NR_nfsservctl (__NR_SYSCALL_BASE+169) +#define __NR_setresgid (__NR_SYSCALL_BASE+170) +#define __NR_getresgid (__NR_SYSCALL_BASE+171) +#define __NR_prctl (__NR_SYSCALL_BASE+172) +#define __NR_rt_sigreturn (__NR_SYSCALL_BASE+173) +#define __NR_rt_sigaction (__NR_SYSCALL_BASE+174) +#define __NR_rt_sigprocmask (__NR_SYSCALL_BASE+175) +#define __NR_rt_sigpending (__NR_SYSCALL_BASE+176) +#define __NR_rt_sigtimedwait (__NR_SYSCALL_BASE+177) +#define __NR_rt_sigqueueinfo (__NR_SYSCALL_BASE+178) +#define __NR_rt_sigsuspend (__NR_SYSCALL_BASE+179) +#define __NR_pread64 (__NR_SYSCALL_BASE+180) +#define __NR_pwrite64 (__NR_SYSCALL_BASE+181) +#define __NR_chown (__NR_SYSCALL_BASE+182) +#define __NR_getcwd (__NR_SYSCALL_BASE+183) +#define __NR_capget (__NR_SYSCALL_BASE+184) +#define __NR_capset (__NR_SYSCALL_BASE+185) +#define __NR_sigaltstack (__NR_SYSCALL_BASE+186) +#define __NR_sendfile (__NR_SYSCALL_BASE+187) + /* 188 reserved */ + /* 189 reserved */ +#define __NR_vfork (__NR_SYSCALL_BASE+190) +#define __NR_ugetrlimit (__NR_SYSCALL_BASE+191) /* SuS compliant getrlimit */ +#define __NR_mmap2 (__NR_SYSCALL_BASE+192) +#define __NR_truncate64 (__NR_SYSCALL_BASE+193) +#define __NR_ftruncate64 (__NR_SYSCALL_BASE+194) +#define __NR_stat64 (__NR_SYSCALL_BASE+195) +#define __NR_lstat64 (__NR_SYSCALL_BASE+196) +#define __NR_fstat64 (__NR_SYSCALL_BASE+197) +#define __NR_lchown32 (__NR_SYSCALL_BASE+198) +#define __NR_getuid32 (__NR_SYSCALL_BASE+199) +#define __NR_getgid32 (__NR_SYSCALL_BASE+200) +#define __NR_geteuid32 (__NR_SYSCALL_BASE+201) +#define __NR_getegid32 (__NR_SYSCALL_BASE+202) +#define __NR_setreuid32 (__NR_SYSCALL_BASE+203) +#define __NR_setregid32 (__NR_SYSCALL_BASE+204) +#define __NR_getgroups32 (__NR_SYSCALL_BASE+205) +#define __NR_setgroups32 (__NR_SYSCALL_BASE+206) +#define __NR_fchown32 (__NR_SYSCALL_BASE+207) +#define __NR_setresuid32 (__NR_SYSCALL_BASE+208) +#define __NR_getresuid32 (__NR_SYSCALL_BASE+209) +#define __NR_setresgid32 (__NR_SYSCALL_BASE+210) +#define __NR_getresgid32 (__NR_SYSCALL_BASE+211) +#define __NR_chown32 (__NR_SYSCALL_BASE+212) +#define __NR_setuid32 (__NR_SYSCALL_BASE+213) +#define __NR_setgid32 (__NR_SYSCALL_BASE+214) +#define __NR_setfsuid32 (__NR_SYSCALL_BASE+215) +#define __NR_setfsgid32 (__NR_SYSCALL_BASE+216) +#define __NR_getdents64 (__NR_SYSCALL_BASE+217) +#define __NR_pivot_root (__NR_SYSCALL_BASE+218) +#define __NR_mincore (__NR_SYSCALL_BASE+219) +#define __NR_madvise (__NR_SYSCALL_BASE+220) +#define __NR_fcntl64 (__NR_SYSCALL_BASE+221) + /* 222 for tux */ + /* 223 is unused */ +#define __NR_gettid (__NR_SYSCALL_BASE+224) +#define __NR_readahead (__NR_SYSCALL_BASE+225) +#define __NR_setxattr (__NR_SYSCALL_BASE+226) +#define __NR_lsetxattr (__NR_SYSCALL_BASE+227) +#define __NR_fsetxattr (__NR_SYSCALL_BASE+228) +#define __NR_getxattr (__NR_SYSCALL_BASE+229) +#define __NR_lgetxattr (__NR_SYSCALL_BASE+230) +#define __NR_fgetxattr (__NR_SYSCALL_BASE+231) +#define __NR_listxattr (__NR_SYSCALL_BASE+232) +#define __NR_llistxattr (__NR_SYSCALL_BASE+233) +#define __NR_flistxattr (__NR_SYSCALL_BASE+234) +#define __NR_removexattr (__NR_SYSCALL_BASE+235) +#define __NR_lremovexattr (__NR_SYSCALL_BASE+236) +#define __NR_fremovexattr (__NR_SYSCALL_BASE+237) +#define __NR_tkill (__NR_SYSCALL_BASE+238) +#define __NR_sendfile64 (__NR_SYSCALL_BASE+239) +#define __NR_futex (__NR_SYSCALL_BASE+240) +#define __NR_sched_setaffinity (__NR_SYSCALL_BASE+241) +#define __NR_sched_getaffinity (__NR_SYSCALL_BASE+242) +#define __NR_io_setup (__NR_SYSCALL_BASE+243) +#define __NR_io_destroy (__NR_SYSCALL_BASE+244) +#define __NR_io_getevents (__NR_SYSCALL_BASE+245) +#define __NR_io_submit (__NR_SYSCALL_BASE+246) +#define __NR_io_cancel (__NR_SYSCALL_BASE+247) +#define __NR_exit_group (__NR_SYSCALL_BASE+248) +#define __NR_lookup_dcookie (__NR_SYSCALL_BASE+249) +#define __NR_epoll_create (__NR_SYSCALL_BASE+250) +#define __NR_epoll_ctl (__NR_SYSCALL_BASE+251) +#define __NR_epoll_wait (__NR_SYSCALL_BASE+252) +#define __NR_remap_file_pages (__NR_SYSCALL_BASE+253) + /* 254 for set_thread_area */ + /* 255 for get_thread_area */ +#define __NR_set_tid_address (__NR_SYSCALL_BASE+256) +#define __NR_timer_create (__NR_SYSCALL_BASE+257) +#define __NR_timer_settime (__NR_SYSCALL_BASE+258) +#define __NR_timer_gettime (__NR_SYSCALL_BASE+259) +#define __NR_timer_getoverrun (__NR_SYSCALL_BASE+260) +#define __NR_timer_delete (__NR_SYSCALL_BASE+261) +#define __NR_clock_settime (__NR_SYSCALL_BASE+262) +#define __NR_clock_gettime (__NR_SYSCALL_BASE+263) +#define __NR_clock_getres (__NR_SYSCALL_BASE+264) +#define __NR_clock_nanosleep (__NR_SYSCALL_BASE+265) +#define __NR_statfs64 (__NR_SYSCALL_BASE+266) +#define __NR_fstatfs64 (__NR_SYSCALL_BASE+267) +#define __NR_tgkill (__NR_SYSCALL_BASE+268) +#define __NR_utimes (__NR_SYSCALL_BASE+269) +#define __NR_arm_fadvise64_64 (__NR_SYSCALL_BASE+270) +#define __NR_pciconfig_iobase (__NR_SYSCALL_BASE+271) +#define __NR_pciconfig_read (__NR_SYSCALL_BASE+272) +#define __NR_pciconfig_write (__NR_SYSCALL_BASE+273) +#define __NR_mq_open (__NR_SYSCALL_BASE+274) +#define __NR_mq_unlink (__NR_SYSCALL_BASE+275) +#define __NR_mq_timedsend (__NR_SYSCALL_BASE+276) +#define __NR_mq_timedreceive (__NR_SYSCALL_BASE+277) +#define __NR_mq_notify (__NR_SYSCALL_BASE+278) +#define __NR_mq_getsetattr (__NR_SYSCALL_BASE+279) +#define __NR_waitid (__NR_SYSCALL_BASE+280) +#define __NR_socket (__NR_SYSCALL_BASE+281) +#define __NR_bind (__NR_SYSCALL_BASE+282) +#define __NR_connect (__NR_SYSCALL_BASE+283) +#define __NR_listen (__NR_SYSCALL_BASE+284) +#define __NR_accept (__NR_SYSCALL_BASE+285) +#define __NR_getsockname (__NR_SYSCALL_BASE+286) +#define __NR_getpeername (__NR_SYSCALL_BASE+287) +#define __NR_socketpair (__NR_SYSCALL_BASE+288) +#define __NR_send (__NR_SYSCALL_BASE+289) +#define __NR_sendto (__NR_SYSCALL_BASE+290) +#define __NR_recv (__NR_SYSCALL_BASE+291) +#define __NR_recvfrom (__NR_SYSCALL_BASE+292) +#define __NR_shutdown (__NR_SYSCALL_BASE+293) +#define __NR_setsockopt (__NR_SYSCALL_BASE+294) +#define __NR_getsockopt (__NR_SYSCALL_BASE+295) +#define __NR_sendmsg (__NR_SYSCALL_BASE+296) +#define __NR_recvmsg (__NR_SYSCALL_BASE+297) +#define __NR_semop (__NR_SYSCALL_BASE+298) +#define __NR_semget (__NR_SYSCALL_BASE+299) +#define __NR_semctl (__NR_SYSCALL_BASE+300) +#define __NR_msgsnd (__NR_SYSCALL_BASE+301) +#define __NR_msgrcv (__NR_SYSCALL_BASE+302) +#define __NR_msgget (__NR_SYSCALL_BASE+303) +#define __NR_msgctl (__NR_SYSCALL_BASE+304) +#define __NR_shmat (__NR_SYSCALL_BASE+305) +#define __NR_shmdt (__NR_SYSCALL_BASE+306) +#define __NR_shmget (__NR_SYSCALL_BASE+307) +#define __NR_shmctl (__NR_SYSCALL_BASE+308) +#define __NR_add_key (__NR_SYSCALL_BASE+309) +#define __NR_request_key (__NR_SYSCALL_BASE+310) +#define __NR_keyctl (__NR_SYSCALL_BASE+311) +#define __NR_semtimedop (__NR_SYSCALL_BASE+312) +#define __NR_vserver (__NR_SYSCALL_BASE+313) +#define __NR_ioprio_set (__NR_SYSCALL_BASE+314) +#define __NR_ioprio_get (__NR_SYSCALL_BASE+315) +#define __NR_inotify_init (__NR_SYSCALL_BASE+316) +#define __NR_inotify_add_watch (__NR_SYSCALL_BASE+317) +#define __NR_inotify_rm_watch (__NR_SYSCALL_BASE+318) +#define __NR_mbind (__NR_SYSCALL_BASE+319) +#define __NR_get_mempolicy (__NR_SYSCALL_BASE+320) +#define __NR_set_mempolicy (__NR_SYSCALL_BASE+321) +#define __NR_openat (__NR_SYSCALL_BASE+322) +#define __NR_mkdirat (__NR_SYSCALL_BASE+323) +#define __NR_mknodat (__NR_SYSCALL_BASE+324) +#define __NR_fchownat (__NR_SYSCALL_BASE+325) +#define __NR_futimesat (__NR_SYSCALL_BASE+326) +#define __NR_fstatat64 (__NR_SYSCALL_BASE+327) +#define __NR_unlinkat (__NR_SYSCALL_BASE+328) +#define __NR_renameat (__NR_SYSCALL_BASE+329) +#define __NR_linkat (__NR_SYSCALL_BASE+330) +#define __NR_symlinkat (__NR_SYSCALL_BASE+331) +#define __NR_readlinkat (__NR_SYSCALL_BASE+332) +#define __NR_fchmodat (__NR_SYSCALL_BASE+333) +#define __NR_faccessat (__NR_SYSCALL_BASE+334) +#define __NR_pselect6 (__NR_SYSCALL_BASE+335) +#define __NR_ppoll (__NR_SYSCALL_BASE+336) +#define __NR_unshare (__NR_SYSCALL_BASE+337) +#define __NR_set_robust_list (__NR_SYSCALL_BASE+338) +#define __NR_get_robust_list (__NR_SYSCALL_BASE+339) +#define __NR_splice (__NR_SYSCALL_BASE+340) +#define __NR_arm_sync_file_range (__NR_SYSCALL_BASE+341) +#define __NR_sync_file_range2 __NR_arm_sync_file_range +#define __NR_tee (__NR_SYSCALL_BASE+342) +#define __NR_vmsplice (__NR_SYSCALL_BASE+343) +#define __NR_move_pages (__NR_SYSCALL_BASE+344) +#define __NR_getcpu (__NR_SYSCALL_BASE+345) +#define __NR_epoll_pwait (__NR_SYSCALL_BASE+346) +#define __NR_kexec_load (__NR_SYSCALL_BASE+347) +#define __NR_utimensat (__NR_SYSCALL_BASE+348) +#define __NR_signalfd (__NR_SYSCALL_BASE+349) +#define __NR_timerfd_create (__NR_SYSCALL_BASE+350) +#define __NR_eventfd (__NR_SYSCALL_BASE+351) +#define __NR_fallocate (__NR_SYSCALL_BASE+352) +#define __NR_timerfd_settime (__NR_SYSCALL_BASE+353) +#define __NR_timerfd_gettime (__NR_SYSCALL_BASE+354) +#define __NR_signalfd4 (__NR_SYSCALL_BASE+355) +#define __NR_eventfd2 (__NR_SYSCALL_BASE+356) +#define __NR_epoll_create1 (__NR_SYSCALL_BASE+357) +#define __NR_dup3 (__NR_SYSCALL_BASE+358) +#define __NR_pipe2 (__NR_SYSCALL_BASE+359) +#define __NR_inotify_init1 (__NR_SYSCALL_BASE+360) +#define __NR_preadv (__NR_SYSCALL_BASE+361) +#define __NR_pwritev (__NR_SYSCALL_BASE+362) +#define __NR_rt_tgsigqueueinfo (__NR_SYSCALL_BASE+363) +#define __NR_perf_event_open (__NR_SYSCALL_BASE+364) +#define __NR_recvmmsg (__NR_SYSCALL_BASE+365) +#define __NR_accept4 (__NR_SYSCALL_BASE+366) +#define __NR_fanotify_init (__NR_SYSCALL_BASE+367) +#define __NR_fanotify_mark (__NR_SYSCALL_BASE+368) +#define __NR_prlimit64 (__NR_SYSCALL_BASE+369) +#define __NR_name_to_handle_at (__NR_SYSCALL_BASE+370) +#define __NR_open_by_handle_at (__NR_SYSCALL_BASE+371) +#define __NR_clock_adjtime (__NR_SYSCALL_BASE+372) +#define __NR_syncfs (__NR_SYSCALL_BASE+373) +#define __NR_sendmmsg (__NR_SYSCALL_BASE+374) +#define __NR_setns (__NR_SYSCALL_BASE+375) +#define __NR_process_vm_readv (__NR_SYSCALL_BASE+376) +#define __NR_process_vm_writev (__NR_SYSCALL_BASE+377) + /* 378 for kcmp */ + +/* + * This may need to be greater than __NR_last_syscall+1 in order to + * account for the padding in the syscall table + */ + +/* + * The following SWIs are ARM private. + */ +#define __ARM_NR_BASE (__NR_SYSCALL_BASE+0x0f0000) +#define __ARM_NR_breakpoint (__ARM_NR_BASE+1) +#define __ARM_NR_cacheflush (__ARM_NR_BASE+2) +#define __ARM_NR_usr26 (__ARM_NR_BASE+3) +#define __ARM_NR_usr32 (__ARM_NR_BASE+4) +#define __ARM_NR_set_tls (__ARM_NR_BASE+5) + +/* + * *NOTE*: This is a ghost syscall private to the kernel. Only the + * __kuser_cmpxchg code in entry-armv.S should be aware of its + * existence. Don't ever use this from user code. + */ + +/* + * The following syscalls are obsolete and no longer available for EABI. + */ +#if !defined(__KERNEL__) +#if defined(__ARM_EABI__) +#undef __NR_time +#undef __NR_umount +#undef __NR_stime +#undef __NR_alarm +#undef __NR_utime +#undef __NR_getrlimit +#undef __NR_select +#undef __NR_readdir +#undef __NR_mmap +#undef __NR_socketcall +#undef __NR_syscall +#undef __NR_ipc +#endif +#endif + +#endif /* _UAPI__ASM_ARM_UNISTD_H */ diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index d81f3a6d9ad8..5bbec7b8183e 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile @@ -19,7 +19,9 @@ obj-y := elf.o entry-armv.o entry-common.o irq.o opcodes.o \ process.o ptrace.o return_address.o sched_clock.o \ setup.o signal.o stacktrace.o sys_arm.o time.o traps.o -obj-$(CONFIG_DEPRECATED_PARAM_STRUCT) += compat.o +obj-$(CONFIG_ATAGS) += atags_parse.o +obj-$(CONFIG_ATAGS_PROC) += atags_proc.o +obj-$(CONFIG_DEPRECATED_PARAM_STRUCT) += atags_compat.o obj-$(CONFIG_OC_ETM) += etm.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o @@ -51,7 +53,6 @@ test-kprobes-objs += kprobes-test-thumb.o else test-kprobes-objs += kprobes-test-arm.o endif -obj-$(CONFIG_ATAGS_PROC) += atags.o obj-$(CONFIG_OABI_COMPAT) += sys_oabi-compat.o obj-$(CONFIG_ARM_THUMBEE) += thumbee.o obj-$(CONFIG_KGDB) += kgdb.o @@ -80,4 +81,6 @@ head-y := head$(MMUEXT).o obj-$(CONFIG_DEBUG_LL) += debug.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o +obj-$(CONFIG_ARM_VIRT_EXT) += hyp-stub.o + extra-y := $(head-y) vmlinux.lds diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c index cf258807160d..c8ef20747ee7 100644 --- a/arch/arm/kernel/arch_timer.c +++ b/arch/arm/kernel/arch_timer.c @@ -21,18 +21,28 @@ #include <linux/io.h> #include <asm/cputype.h> +#include <asm/delay.h> #include <asm/localtimer.h> #include <asm/arch_timer.h> #include <asm/system_info.h> #include <asm/sched_clock.h> static unsigned long arch_timer_rate; -static int arch_timer_ppi; -static int arch_timer_ppi2; + +enum ppi_nr { + PHYS_SECURE_PPI, + PHYS_NONSECURE_PPI, + VIRT_PPI, + HYP_PPI, + MAX_TIMER_PPI +}; + +static int arch_timer_ppi[MAX_TIMER_PPI]; static struct clock_event_device __percpu **arch_timer_evt; +static struct delay_timer arch_delay_timer; -extern void init_current_timer_delay(unsigned long freq); +static bool arch_timer_use_virtual = true; /* * Architected system timer support. @@ -46,50 +56,104 @@ extern void init_current_timer_delay(unsigned long freq); #define ARCH_TIMER_REG_FREQ 1 #define ARCH_TIMER_REG_TVAL 2 -static void arch_timer_reg_write(int reg, u32 val) +#define ARCH_TIMER_PHYS_ACCESS 0 +#define ARCH_TIMER_VIRT_ACCESS 1 + +/* + * These register accessors are marked inline so the compiler can + * nicely work out which register we want, and chuck away the rest of + * the code. At least it does so with a recent GCC (4.6.3). + */ +static inline void arch_timer_reg_write(const int access, const int reg, u32 val) { - switch (reg) { - case ARCH_TIMER_REG_CTRL: - asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val)); - break; - case ARCH_TIMER_REG_TVAL: - asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val)); - break; + if (access == ARCH_TIMER_PHYS_ACCESS) { + switch (reg) { + case ARCH_TIMER_REG_CTRL: + asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val)); + break; + case ARCH_TIMER_REG_TVAL: + asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val)); + break; + } + } + + if (access == ARCH_TIMER_VIRT_ACCESS) { + switch (reg) { + case ARCH_TIMER_REG_CTRL: + asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" (val)); + break; + case ARCH_TIMER_REG_TVAL: + asm volatile("mcr p15, 0, %0, c14, c3, 0" : : "r" (val)); + break; + } } isb(); } -static u32 arch_timer_reg_read(int reg) +static inline u32 arch_timer_reg_read(const int access, const int reg) { - u32 val; + u32 val = 0; + + if (access == ARCH_TIMER_PHYS_ACCESS) { + switch (reg) { + case ARCH_TIMER_REG_CTRL: + asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val)); + break; + case ARCH_TIMER_REG_TVAL: + asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val)); + break; + case ARCH_TIMER_REG_FREQ: + asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val)); + break; + } + } - switch (reg) { - case ARCH_TIMER_REG_CTRL: - asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val)); - break; - case ARCH_TIMER_REG_FREQ: - asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val)); - break; - case ARCH_TIMER_REG_TVAL: - asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val)); - break; - default: - BUG(); + if (access == ARCH_TIMER_VIRT_ACCESS) { + switch (reg) { + case ARCH_TIMER_REG_CTRL: + asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val)); + break; + case ARCH_TIMER_REG_TVAL: + asm volatile("mrc p15, 0, %0, c14, c3, 0" : "=r" (val)); + break; + } } return val; } -static irqreturn_t arch_timer_handler(int irq, void *dev_id) +static inline cycle_t arch_timer_counter_read(const int access) { - struct clock_event_device *evt = *(struct clock_event_device **)dev_id; - unsigned long ctrl; + cycle_t cval = 0; + + if (access == ARCH_TIMER_PHYS_ACCESS) + asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval)); + + if (access == ARCH_TIMER_VIRT_ACCESS) + asm volatile("mrrc p15, 1, %Q0, %R0, c14" : "=r" (cval)); + + return cval; +} + +static inline cycle_t arch_counter_get_cntpct(void) +{ + return arch_timer_counter_read(ARCH_TIMER_PHYS_ACCESS); +} - ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL); +static inline cycle_t arch_counter_get_cntvct(void) +{ + return arch_timer_counter_read(ARCH_TIMER_VIRT_ACCESS); +} + +static irqreturn_t inline timer_handler(const int access, + struct clock_event_device *evt) +{ + unsigned long ctrl; + ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL); if (ctrl & ARCH_TIMER_CTRL_IT_STAT) { ctrl |= ARCH_TIMER_CTRL_IT_MASK; - arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl); + arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl); evt->event_handler(evt); return IRQ_HANDLED; } @@ -97,63 +161,100 @@ static irqreturn_t arch_timer_handler(int irq, void *dev_id) return IRQ_NONE; } -static void arch_timer_disable(void) +static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id) { - unsigned long ctrl; + struct clock_event_device *evt = *(struct clock_event_device **)dev_id; - ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL); - ctrl &= ~ARCH_TIMER_CTRL_ENABLE; - arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl); + return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt); } -static void arch_timer_set_mode(enum clock_event_mode mode, - struct clock_event_device *clk) +static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id) { + struct clock_event_device *evt = *(struct clock_event_device **)dev_id; + + return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt); +} + +static inline void timer_set_mode(const int access, int mode) +{ + unsigned long ctrl; switch (mode) { case CLOCK_EVT_MODE_UNUSED: case CLOCK_EVT_MODE_SHUTDOWN: - arch_timer_disable(); + ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL); + ctrl &= ~ARCH_TIMER_CTRL_ENABLE; + arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl); break; default: break; } } -static int arch_timer_set_next_event(unsigned long evt, - struct clock_event_device *unused) +static void arch_timer_set_mode_virt(enum clock_event_mode mode, + struct clock_event_device *clk) { - unsigned long ctrl; + timer_set_mode(ARCH_TIMER_VIRT_ACCESS, mode); +} - ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL); +static void arch_timer_set_mode_phys(enum clock_event_mode mode, + struct clock_event_device *clk) +{ + timer_set_mode(ARCH_TIMER_PHYS_ACCESS, mode); +} + +static inline void set_next_event(const int access, unsigned long evt) +{ + unsigned long ctrl; + ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL); ctrl |= ARCH_TIMER_CTRL_ENABLE; ctrl &= ~ARCH_TIMER_CTRL_IT_MASK; + arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt); + arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl); +} - arch_timer_reg_write(ARCH_TIMER_REG_TVAL, evt); - arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl); +static int arch_timer_set_next_event_virt(unsigned long evt, + struct clock_event_device *unused) +{ + set_next_event(ARCH_TIMER_VIRT_ACCESS, evt); + return 0; +} +static int arch_timer_set_next_event_phys(unsigned long evt, + struct clock_event_device *unused) +{ + set_next_event(ARCH_TIMER_PHYS_ACCESS, evt); return 0; } static int __cpuinit arch_timer_setup(struct clock_event_device *clk) { - /* Be safe... */ - arch_timer_disable(); - clk->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP; clk->name = "arch_sys_timer"; clk->rating = 450; - clk->set_mode = arch_timer_set_mode; - clk->set_next_event = arch_timer_set_next_event; - clk->irq = arch_timer_ppi; + if (arch_timer_use_virtual) { + clk->irq = arch_timer_ppi[VIRT_PPI]; + clk->set_mode = arch_timer_set_mode_virt; + clk->set_next_event = arch_timer_set_next_event_virt; + } else { + clk->irq = arch_timer_ppi[PHYS_SECURE_PPI]; + clk->set_mode = arch_timer_set_mode_phys; + clk->set_next_event = arch_timer_set_next_event_phys; + } + + clk->set_mode(CLOCK_EVT_MODE_SHUTDOWN, NULL); clockevents_config_and_register(clk, arch_timer_rate, 0xf, 0x7fffffff); *__this_cpu_ptr(arch_timer_evt) = clk; - enable_percpu_irq(clk->irq, 0); - if (arch_timer_ppi2) - enable_percpu_irq(arch_timer_ppi2, 0); + if (arch_timer_use_virtual) + enable_percpu_irq(arch_timer_ppi[VIRT_PPI], 0); + else { + enable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI], 0); + if (arch_timer_ppi[PHYS_NONSECURE_PPI]) + enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], 0); + } return 0; } @@ -173,8 +274,8 @@ static int arch_timer_available(void) return -ENXIO; if (arch_timer_rate == 0) { - arch_timer_reg_write(ARCH_TIMER_REG_CTRL, 0); - freq = arch_timer_reg_read(ARCH_TIMER_REG_FREQ); + freq = arch_timer_reg_read(ARCH_TIMER_PHYS_ACCESS, + ARCH_TIMER_REG_FREQ); /* Check the timer frequency. */ if (freq == 0) { @@ -185,52 +286,57 @@ static int arch_timer_available(void) arch_timer_rate = freq; } - pr_info_once("Architected local timer running at %lu.%02luMHz.\n", - arch_timer_rate / 1000000, (arch_timer_rate / 10000) % 100); + pr_info_once("Architected local timer running at %lu.%02luMHz (%s).\n", + arch_timer_rate / 1000000, (arch_timer_rate / 10000) % 100, + arch_timer_use_virtual ? "virt" : "phys"); return 0; } -static inline cycle_t arch_counter_get_cntpct(void) +static u32 notrace arch_counter_get_cntpct32(void) { - u32 cvall, cvalh; - - asm volatile("mrrc p15, 0, %0, %1, c14" : "=r" (cvall), "=r" (cvalh)); + cycle_t cnt = arch_counter_get_cntpct(); - return ((cycle_t) cvalh << 32) | cvall; -} - -static inline cycle_t arch_counter_get_cntvct(void) -{ - u32 cvall, cvalh; - - asm volatile("mrrc p15, 1, %0, %1, c14" : "=r" (cvall), "=r" (cvalh)); - - return ((cycle_t) cvalh << 32) | cvall; + /* + * The sched_clock infrastructure only knows about counters + * with at most 32bits. Forget about the upper 24 bits for the + * time being... + */ + return (u32)cnt; } static u32 notrace arch_counter_get_cntvct32(void) { - cycle_t cntvct = arch_counter_get_cntvct(); + cycle_t cnt = arch_counter_get_cntvct(); /* * The sched_clock infrastructure only knows about counters * with at most 32bits. Forget about the upper 24 bits for the * time being... */ - return (u32)(cntvct & (u32)~0); + return (u32)cnt; } static cycle_t arch_counter_read(struct clocksource *cs) { + /* + * Always use the physical counter for the clocksource. + * CNTHCTL.PL1PCTEN must be set to 1. + */ return arch_counter_get_cntpct(); } -int read_current_timer(unsigned long *timer_val) +static unsigned long arch_timer_read_current_timer(void) { - if (!arch_timer_rate) - return -ENXIO; - *timer_val = arch_counter_get_cntpct(); - return 0; + return arch_counter_get_cntpct(); +} + +static cycle_t arch_counter_read_cc(const struct cyclecounter *cc) +{ + /* + * Always use the physical counter for the clocksource. + * CNTHCTL.PL1PCTEN must be set to 1. + */ + return arch_counter_get_cntpct(); } static struct clocksource clocksource_counter = { @@ -241,14 +347,32 @@ static struct clocksource clocksource_counter = { .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; +static struct cyclecounter cyclecounter = { + .read = arch_counter_read_cc, + .mask = CLOCKSOURCE_MASK(56), +}; + +static struct timecounter timecounter; + +struct timecounter *arch_timer_get_timecounter(void) +{ + return &timecounter; +} + static void __cpuinit arch_timer_stop(struct clock_event_device *clk) { pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n", clk->irq, smp_processor_id()); - disable_percpu_irq(clk->irq); - if (arch_timer_ppi2) - disable_percpu_irq(arch_timer_ppi2); - arch_timer_set_mode(CLOCK_EVT_MODE_UNUSED, clk); + + if (arch_timer_use_virtual) + disable_percpu_irq(arch_timer_ppi[VIRT_PPI]); + else { + disable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI]); + if (arch_timer_ppi[PHYS_NONSECURE_PPI]) + disable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI]); + } + + clk->set_mode(CLOCK_EVT_MODE_UNUSED, clk); } static struct local_timer_ops arch_timer_ops __cpuinitdata = { @@ -261,36 +385,48 @@ static struct clock_event_device arch_timer_global_evt; static int __init arch_timer_register(void) { int err; + int ppi; err = arch_timer_available(); if (err) - return err; + goto out; arch_timer_evt = alloc_percpu(struct clock_event_device *); - if (!arch_timer_evt) - return -ENOMEM; + if (!arch_timer_evt) { + err = -ENOMEM; + goto out; + } clocksource_register_hz(&clocksource_counter, arch_timer_rate); + cyclecounter.mult = clocksource_counter.mult; + cyclecounter.shift = clocksource_counter.shift; + timecounter_init(&timecounter, &cyclecounter, + arch_counter_get_cntpct()); + + if (arch_timer_use_virtual) { + ppi = arch_timer_ppi[VIRT_PPI]; + err = request_percpu_irq(ppi, arch_timer_handler_virt, + "arch_timer", arch_timer_evt); + } else { + ppi = arch_timer_ppi[PHYS_SECURE_PPI]; + err = request_percpu_irq(ppi, arch_timer_handler_phys, + "arch_timer", arch_timer_evt); + if (!err && arch_timer_ppi[PHYS_NONSECURE_PPI]) { + ppi = arch_timer_ppi[PHYS_NONSECURE_PPI]; + err = request_percpu_irq(ppi, arch_timer_handler_phys, + "arch_timer", arch_timer_evt); + if (err) + free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI], + arch_timer_evt); + } + } - err = request_percpu_irq(arch_timer_ppi, arch_timer_handler, - "arch_timer", arch_timer_evt); if (err) { pr_err("arch_timer: can't register interrupt %d (%d)\n", - arch_timer_ppi, err); + ppi, err); goto out_free; } - if (arch_timer_ppi2) { - err = request_percpu_irq(arch_timer_ppi2, arch_timer_handler, - "arch_timer", arch_timer_evt); - if (err) { - pr_err("arch_timer: can't register interrupt %d (%d)\n", - arch_timer_ppi2, err); - arch_timer_ppi2 = 0; - goto out_free_irq; - } - } - err = local_timer_register(&arch_timer_ops); if (err) { /* @@ -302,21 +438,29 @@ static int __init arch_timer_register(void) arch_timer_global_evt.cpumask = cpumask_of(0); err = arch_timer_setup(&arch_timer_global_evt); } - if (err) goto out_free_irq; - init_current_timer_delay(arch_timer_rate); + /* Use the architected timer for the delay loop. */ + arch_delay_timer.read_current_timer = &arch_timer_read_current_timer; + arch_delay_timer.freq = arch_timer_rate; + register_current_timer_delay(&arch_delay_timer); return 0; out_free_irq: - free_percpu_irq(arch_timer_ppi, arch_timer_evt); - if (arch_timer_ppi2) - free_percpu_irq(arch_timer_ppi2, arch_timer_evt); + if (arch_timer_use_virtual) + free_percpu_irq(arch_timer_ppi[VIRT_PPI], arch_timer_evt); + else { + free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI], + arch_timer_evt); + if (arch_timer_ppi[PHYS_NONSECURE_PPI]) + free_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], + arch_timer_evt); + } out_free: free_percpu(arch_timer_evt); - +out: return err; } @@ -329,6 +473,7 @@ int __init arch_timer_of_register(void) { struct device_node *np; u32 freq; + int i; np = of_find_matching_node(NULL, arch_timer_of_match); if (!np) { @@ -340,22 +485,40 @@ int __init arch_timer_of_register(void) if (!of_property_read_u32(np, "clock-frequency", &freq)) arch_timer_rate = freq; - arch_timer_ppi = irq_of_parse_and_map(np, 0); - arch_timer_ppi2 = irq_of_parse_and_map(np, 1); - pr_info("arch_timer: found %s irqs %d %d\n", - np->name, arch_timer_ppi, arch_timer_ppi2); + for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++) + arch_timer_ppi[i] = irq_of_parse_and_map(np, i); + + /* + * If no interrupt provided for virtual timer, we'll have to + * stick to the physical timer. It'd better be accessible... + */ + if (!arch_timer_ppi[VIRT_PPI]) { + arch_timer_use_virtual = false; + + if (!arch_timer_ppi[PHYS_SECURE_PPI] || + !arch_timer_ppi[PHYS_NONSECURE_PPI]) { + pr_warn("arch_timer: No interrupt available, giving up\n"); + return -EINVAL; + } + } return arch_timer_register(); } int __init arch_timer_sched_clock_init(void) { + u32 (*cnt32)(void); int err; err = arch_timer_available(); if (err) return err; - setup_sched_clock(arch_counter_get_cntvct32, 32, arch_timer_rate); + if (arch_timer_use_virtual) + cnt32 = arch_counter_get_cntvct32; + else + cnt32 = arch_counter_get_cntpct32; + + setup_sched_clock(cnt32, 32, arch_timer_rate); return 0; } diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c index 1429d8989fb9..c985b481192c 100644 --- a/arch/arm/kernel/asm-offsets.c +++ b/arch/arm/kernel/asm-offsets.c @@ -59,10 +59,12 @@ int main(void) DEFINE(TI_USED_CP, offsetof(struct thread_info, used_cp)); DEFINE(TI_TP_VALUE, offsetof(struct thread_info, tp_value)); DEFINE(TI_FPSTATE, offsetof(struct thread_info, fpstate)); +#ifdef CONFIG_VFP DEFINE(TI_VFPSTATE, offsetof(struct thread_info, vfpstate)); #ifdef CONFIG_SMP DEFINE(VFP_CPU, offsetof(union vfp_state, hard.cpu)); #endif +#endif #ifdef CONFIG_ARM_THUMBEE DEFINE(TI_THUMBEE_STATE, offsetof(struct thread_info, thumbee_state)); #endif diff --git a/arch/arm/kernel/atags.h b/arch/arm/kernel/atags.h index e5f028d214a1..9edc9692332d 100644 --- a/arch/arm/kernel/atags.h +++ b/arch/arm/kernel/atags.h @@ -3,3 +3,17 @@ extern void save_atags(struct tag *tags); #else static inline void save_atags(struct tag *tags) { } #endif + +void convert_to_tag_list(struct tag *tags); + +#ifdef CONFIG_ATAGS +struct machine_desc *setup_machine_tags(phys_addr_t __atags_pointer, unsigned int machine_nr); +#else +static inline struct machine_desc * +setup_machine_tags(phys_addr_t __atags_pointer, unsigned int machine_nr) +{ + early_print("no ATAGS support: can't continue\n"); + while (true); + unreachable(); +} +#endif diff --git a/arch/arm/kernel/compat.c b/arch/arm/kernel/atags_compat.c index 925652318b8b..5236ad38f417 100644 --- a/arch/arm/kernel/compat.c +++ b/arch/arm/kernel/atags_compat.c @@ -1,5 +1,5 @@ /* - * linux/arch/arm/kernel/compat.c + * linux/arch/arm/kernel/atags_compat.c * * Copyright (C) 2001 Russell King * @@ -26,7 +26,7 @@ #include <asm/mach/arch.h> -#include "compat.h" +#include "atags.h" /* * Usage: diff --git a/arch/arm/kernel/atags_parse.c b/arch/arm/kernel/atags_parse.c new file mode 100644 index 000000000000..14512e6931d8 --- /dev/null +++ b/arch/arm/kernel/atags_parse.c @@ -0,0 +1,238 @@ +/* + * Tag parsing. + * + * Copyright (C) 1995-2001 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * This is the traditional way of passing data to the kernel at boot time. Rather + * than passing a fixed inflexible structure to the kernel, we pass a list + * of variable-sized tags to the kernel. The first tag must be a ATAG_CORE + * tag for the list to be recognised (to distinguish the tagged list from + * a param_struct). The list is terminated with a zero-length tag (this tag + * is not parsed in any way). + */ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/fs.h> +#include <linux/root_dev.h> +#include <linux/screen_info.h> + +#include <asm/setup.h> +#include <asm/system_info.h> +#include <asm/page.h> +#include <asm/mach/arch.h> + +#include "atags.h" + +static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE; + +#ifndef MEM_SIZE +#define MEM_SIZE (16*1024*1024) +#endif + +static struct { + struct tag_header hdr1; + struct tag_core core; + struct tag_header hdr2; + struct tag_mem32 mem; + struct tag_header hdr3; +} default_tags __initdata = { + { tag_size(tag_core), ATAG_CORE }, + { 1, PAGE_SIZE, 0xff }, + { tag_size(tag_mem32), ATAG_MEM }, + { MEM_SIZE }, + { 0, ATAG_NONE } +}; + +static int __init parse_tag_core(const struct tag *tag) +{ + if (tag->hdr.size > 2) { + if ((tag->u.core.flags & 1) == 0) + root_mountflags &= ~MS_RDONLY; + ROOT_DEV = old_decode_dev(tag->u.core.rootdev); + } + return 0; +} + +__tagtable(ATAG_CORE, parse_tag_core); + +static int __init parse_tag_mem32(const struct tag *tag) +{ + return arm_add_memory(tag->u.mem.start, tag->u.mem.size); +} + +__tagtable(ATAG_MEM, parse_tag_mem32); + +#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE) +static int __init parse_tag_videotext(const struct tag *tag) +{ + screen_info.orig_x = tag->u.videotext.x; + screen_info.orig_y = tag->u.videotext.y; + screen_info.orig_video_page = tag->u.videotext.video_page; + screen_info.orig_video_mode = tag->u.videotext.video_mode; + screen_info.orig_video_cols = tag->u.videotext.video_cols; + screen_info.orig_video_ega_bx = tag->u.videotext.video_ega_bx; + screen_info.orig_video_lines = tag->u.videotext.video_lines; + screen_info.orig_video_isVGA = tag->u.videotext.video_isvga; + screen_info.orig_video_points = tag->u.videotext.video_points; + return 0; +} + +__tagtable(ATAG_VIDEOTEXT, parse_tag_videotext); +#endif + +#ifdef CONFIG_BLK_DEV_RAM +static int __init parse_tag_ramdisk(const struct tag *tag) +{ + extern int rd_size, rd_image_start, rd_prompt, rd_doload; + + rd_image_start = tag->u.ramdisk.start; + rd_doload = (tag->u.ramdisk.flags & 1) == 0; + rd_prompt = (tag->u.ramdisk.flags & 2) == 0; + + if (tag->u.ramdisk.size) + rd_size = tag->u.ramdisk.size; + + return 0; +} + +__tagtable(ATAG_RAMDISK, parse_tag_ramdisk); +#endif + +static int __init parse_tag_serialnr(const struct tag *tag) +{ + system_serial_low = tag->u.serialnr.low; + system_serial_high = tag->u.serialnr.high; + return 0; +} + +__tagtable(ATAG_SERIAL, parse_tag_serialnr); + +static int __init parse_tag_revision(const struct tag *tag) +{ + system_rev = tag->u.revision.rev; + return 0; +} + +__tagtable(ATAG_REVISION, parse_tag_revision); + +static int __init parse_tag_cmdline(const struct tag *tag) +{ +#if defined(CONFIG_CMDLINE_EXTEND) + strlcat(default_command_line, " ", COMMAND_LINE_SIZE); + strlcat(default_command_line, tag->u.cmdline.cmdline, + COMMAND_LINE_SIZE); +#elif defined(CONFIG_CMDLINE_FORCE) + pr_warning("Ignoring tag cmdline (using the default kernel command line)\n"); +#else + strlcpy(default_command_line, tag->u.cmdline.cmdline, + COMMAND_LINE_SIZE); +#endif + return 0; +} + +__tagtable(ATAG_CMDLINE, parse_tag_cmdline); + +/* + * Scan the tag table for this tag, and call its parse function. + * The tag table is built by the linker from all the __tagtable + * declarations. + */ +static int __init parse_tag(const struct tag *tag) +{ + extern struct tagtable __tagtable_begin, __tagtable_end; + struct tagtable *t; + + for (t = &__tagtable_begin; t < &__tagtable_end; t++) + if (tag->hdr.tag == t->tag) { + t->parse(tag); + break; + } + + return t < &__tagtable_end; +} + +/* + * Parse all tags in the list, checking both the global and architecture + * specific tag tables. + */ +static void __init parse_tags(const struct tag *t) +{ + for (; t->hdr.size; t = tag_next(t)) + if (!parse_tag(t)) + printk(KERN_WARNING + "Ignoring unrecognised tag 0x%08x\n", + t->hdr.tag); +} + +static void __init squash_mem_tags(struct tag *tag) +{ + for (; tag->hdr.size; tag = tag_next(tag)) + if (tag->hdr.tag == ATAG_MEM) + tag->hdr.tag = ATAG_NONE; +} + +struct machine_desc * __init setup_machine_tags(phys_addr_t __atags_pointer, + unsigned int machine_nr) +{ + struct tag *tags = (struct tag *)&default_tags; + struct machine_desc *mdesc = NULL, *p; + char *from = default_command_line; + + default_tags.mem.start = PHYS_OFFSET; + + /* + * locate machine in the list of supported machines. + */ + for_each_machine_desc(p) + if (machine_nr == p->nr) { + printk("Machine: %s\n", p->name); + mdesc = p; + break; + } + + if (!mdesc) { + early_print("\nError: unrecognized/unsupported machine ID" + " (r1 = 0x%08x).\n\n", machine_nr); + dump_machine_table(); /* does not return */ + } + + if (__atags_pointer) + tags = phys_to_virt(__atags_pointer); + else if (mdesc->atag_offset) + tags = (void *)(PAGE_OFFSET + mdesc->atag_offset); + +#if defined(CONFIG_DEPRECATED_PARAM_STRUCT) + /* + * If we have the old style parameters, convert them to + * a tag list. + */ + if (tags->hdr.tag != ATAG_CORE) + convert_to_tag_list(tags); +#endif + if (tags->hdr.tag != ATAG_CORE) { + early_print("Warning: Neither atags nor dtb found\n"); + tags = (struct tag *)&default_tags; + } + + if (mdesc->fixup) + mdesc->fixup(tags, &from, &meminfo); + + if (tags->hdr.tag == ATAG_CORE) { + if (meminfo.nr_banks != 0) + squash_mem_tags(tags); + save_atags(tags); + parse_tags(tags); + } + + /* parse_early_param needs a boot_command_line */ + strlcpy(boot_command_line, from, COMMAND_LINE_SIZE); + + return mdesc; +} diff --git a/arch/arm/kernel/atags.c b/arch/arm/kernel/atags_proc.c index 42a1a1415fa6..42a1a1415fa6 100644 --- a/arch/arm/kernel/atags.c +++ b/arch/arm/kernel/atags_proc.c diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S index e337879595e5..831cd38c8d99 100644 --- a/arch/arm/kernel/calls.S +++ b/arch/arm/kernel/calls.S @@ -20,7 +20,7 @@ CALL(sys_creat) CALL(sys_link) /* 10 */ CALL(sys_unlink) - CALL(sys_execve_wrapper) + CALL(sys_execve) CALL(sys_chdir) CALL(OBSOLETE(sys_time)) /* used by libc4 */ CALL(sys_mknod) diff --git a/arch/arm/kernel/compat.h b/arch/arm/kernel/compat.h deleted file mode 100644 index 39264ab1b9c6..000000000000 --- a/arch/arm/kernel/compat.h +++ /dev/null @@ -1,11 +0,0 @@ -/* - * linux/arch/arm/kernel/compat.h - * - * Copyright (C) 2001 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -extern void convert_to_tag_list(struct tag *tags); diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index 978eac57e04a..34711757ba59 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S @@ -86,14 +86,26 @@ ENDPROC(ret_to_user) */ ENTRY(ret_from_fork) bl schedule_tail - get_thread_info tsk - mov why, #1 + cmp r5, #0 + movne r0, r4 + adrne lr, BSYM(1f) + movne pc, r5 +1: get_thread_info tsk b ret_slow_syscall ENDPROC(ret_from_fork) .equ NR_syscalls,0 #define CALL(x) .equ NR_syscalls,NR_syscalls+1 #include "calls.S" + +/* + * Ensure that the system call table is equal to __NR_syscalls, + * which is the value the rest of the system sees + */ +.ifne NR_syscalls - __NR_syscalls +.error "__NR_syscalls is not equal to the size of the syscall table" +.endif + #undef CALL #define CALL(x) .long x @@ -508,11 +520,6 @@ sys_vfork_wrapper: b sys_vfork ENDPROC(sys_vfork_wrapper) -sys_execve_wrapper: - add r3, sp, #S_OFF - b sys_execve -ENDPROC(sys_execve_wrapper) - sys_clone_wrapper: add ip, sp, #S_OFF str ip, [sp, #4] diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 9874d0741191..4eee351f4668 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -83,8 +83,12 @@ ENTRY(stext) THUMB( .thumb ) @ switch to Thumb now. THUMB(1: ) - setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode - @ and irqs disabled +#ifdef CONFIG_ARM_VIRT_EXT + bl __hyp_stub_install +#endif + @ ensure svc mode and all interrupts masked + safe_svcmode_maskall r9 + mrc p15, 0, r9, c0, c0 @ get processor id bl __lookup_processor_type @ r5=procinfo r9=cpuid movs r10, r5 @ invalid processor (r5=0)? @@ -326,7 +330,11 @@ ENTRY(secondary_startup) * the processor type - there is no need to check the machine type * as it has already been validated by the primary processor. */ - setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 +#ifdef CONFIG_ARM_VIRT_EXT + bl __hyp_stub_install +#endif + safe_svcmode_maskall r9 + mrc p15, 0, r9, c0, c0 @ get processor id bl __lookup_processor_type movs r10, r5 @ invalid processor? diff --git a/arch/arm/kernel/hyp-stub.S b/arch/arm/kernel/hyp-stub.S new file mode 100644 index 000000000000..65b2417aebce --- /dev/null +++ b/arch/arm/kernel/hyp-stub.S @@ -0,0 +1,223 @@ +/* + * Copyright (c) 2012 Linaro Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/init.h> +#include <linux/linkage.h> +#include <asm/assembler.h> +#include <asm/virt.h> + +#ifndef ZIMAGE +/* + * For the kernel proper, we need to find out the CPU boot mode long after + * boot, so we need to store it in a writable variable. + * + * This is not in .bss, because we set it sufficiently early that the boot-time + * zeroing of .bss would clobber it. + */ +.data +ENTRY(__boot_cpu_mode) + .long 0 +.text + + /* + * Save the primary CPU boot mode. Requires 3 scratch registers. + */ + .macro store_primary_cpu_mode reg1, reg2, reg3 + mrs \reg1, cpsr + and \reg1, \reg1, #MODE_MASK + adr \reg2, .L__boot_cpu_mode_offset + ldr \reg3, [\reg2] + str \reg1, [\reg2, \reg3] + .endm + + /* + * Compare the current mode with the one saved on the primary CPU. + * If they don't match, record that fact. The Z bit indicates + * if there's a match or not. + * Requires 3 additionnal scratch registers. + */ + .macro compare_cpu_mode_with_primary mode, reg1, reg2, reg3 + adr \reg2, .L__boot_cpu_mode_offset + ldr \reg3, [\reg2] + ldr \reg1, [\reg2, \reg3] + cmp \mode, \reg1 @ matches primary CPU boot mode? + orrne r7, r7, #BOOT_CPU_MODE_MISMATCH + strne r7, [r5, r6] @ record what happened and give up + .endm + +#else /* ZIMAGE */ + + .macro store_primary_cpu_mode reg1:req, reg2:req, reg3:req + .endm + +/* + * The zImage loader only runs on one CPU, so we don't bother with mult-CPU + * consistency checking: + */ + .macro compare_cpu_mode_with_primary mode, reg1, reg2, reg3 + cmp \mode, \mode + .endm + +#endif /* ZIMAGE */ + +/* + * Hypervisor stub installation functions. + * + * These must be called with the MMU and D-cache off. + * They are not ABI compliant and are only intended to be called from the kernel + * entry points in head.S. + */ +@ Call this from the primary CPU +ENTRY(__hyp_stub_install) + store_primary_cpu_mode r4, r5, r6 +ENDPROC(__hyp_stub_install) + + @ fall through... + +@ Secondary CPUs should call here +ENTRY(__hyp_stub_install_secondary) + mrs r4, cpsr + and r4, r4, #MODE_MASK + + /* + * If the secondary has booted with a different mode, give up + * immediately. + */ + compare_cpu_mode_with_primary r4, r5, r6, r7 + bxne lr + + /* + * Once we have given up on one CPU, we do not try to install the + * stub hypervisor on the remaining ones: because the saved boot mode + * is modified, it can't compare equal to the CPSR mode field any + * more. + * + * Otherwise... + */ + + cmp r4, #HYP_MODE + bxne lr @ give up if the CPU is not in HYP mode + +/* + * Configure HSCTLR to set correct exception endianness/instruction set + * state etc. + * Turn off all traps + * Eventually, CPU-specific code might be needed -- assume not for now + * + * This code relies on the "eret" instruction to synchronize the + * various coprocessor accesses. + */ + @ Now install the hypervisor stub: + adr r7, __hyp_stub_vectors + mcr p15, 4, r7, c12, c0, 0 @ set hypervisor vector base (HVBAR) + + @ Disable all traps, so we don't get any nasty surprise + mov r7, #0 + mcr p15, 4, r7, c1, c1, 0 @ HCR + mcr p15, 4, r7, c1, c1, 2 @ HCPTR + mcr p15, 4, r7, c1, c1, 3 @ HSTR + +THUMB( orr r7, #(1 << 30) ) @ HSCTLR.TE +#ifdef CONFIG_CPU_BIG_ENDIAN + orr r7, #(1 << 9) @ HSCTLR.EE +#endif + mcr p15, 4, r7, c1, c0, 0 @ HSCTLR + + mrc p15, 4, r7, c1, c1, 1 @ HDCR + and r7, #0x1f @ Preserve HPMN + mcr p15, 4, r7, c1, c1, 1 @ HDCR + +#if !defined(ZIMAGE) && defined(CONFIG_ARM_ARCH_TIMER) + @ make CNTP_* and CNTPCT accessible from PL1 + mrc p15, 0, r7, c0, c1, 1 @ ID_PFR1 + lsr r7, #16 + and r7, #0xf + cmp r7, #1 + bne 1f + mrc p15, 4, r7, c14, c1, 0 @ CNTHCTL + orr r7, r7, #3 @ PL1PCEN | PL1PCTEN + mcr p15, 4, r7, c14, c1, 0 @ CNTHCTL +1: +#endif + + bic r7, r4, #MODE_MASK + orr r7, r7, #SVC_MODE +THUMB( orr r7, r7, #PSR_T_BIT ) + msr spsr_cxsf, r7 @ This is SPSR_hyp. + + __MSR_ELR_HYP(14) @ msr elr_hyp, lr + __ERET @ return, switching to SVC mode + @ The boot CPU mode is left in r4. +ENDPROC(__hyp_stub_install_secondary) + +__hyp_stub_do_trap: + cmp r0, #-1 + mrceq p15, 4, r0, c12, c0, 0 @ get HVBAR + mcrne p15, 4, r0, c12, c0, 0 @ set HVBAR + __ERET +ENDPROC(__hyp_stub_do_trap) + +/* + * __hyp_set_vectors: Call this after boot to set the initial hypervisor + * vectors as part of hypervisor installation. On an SMP system, this should + * be called on each CPU. + * + * r0 must be the physical address of the new vector table (which must lie in + * the bottom 4GB of physical address space. + * + * r0 must be 32-byte aligned. + * + * Before calling this, you must check that the stub hypervisor is installed + * everywhere, by waiting for any secondary CPUs to be brought up and then + * checking that BOOT_CPU_MODE_HAVE_HYP(__boot_cpu_mode) is true. + * + * If not, there is a pre-existing hypervisor, some CPUs failed to boot, or + * something else went wrong... in such cases, trying to install a new + * hypervisor is unlikely to work as desired. + * + * When you call into your shiny new hypervisor, sp_hyp will contain junk, + * so you will need to set that to something sensible at the new hypervisor's + * initialisation entry point. + */ +ENTRY(__hyp_get_vectors) + mov r0, #-1 +ENDPROC(__hyp_get_vectors) + @ fall through +ENTRY(__hyp_set_vectors) + __HVC(0) + bx lr +ENDPROC(__hyp_set_vectors) + +#ifndef ZIMAGE +.align 2 +.L__boot_cpu_mode_offset: + .long __boot_cpu_mode - . +#endif + +.align 5 +__hyp_stub_vectors: +__hyp_stub_reset: W(b) . +__hyp_stub_und: W(b) . +__hyp_stub_svc: W(b) . +__hyp_stub_pabort: W(b) . +__hyp_stub_dabort: W(b) . +__hyp_stub_trap: W(b) __hyp_stub_do_trap +__hyp_stub_irq: W(b) . +__hyp_stub_fiq: W(b) . +ENDPROC(__hyp_stub_vectors) + diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c index 16cedb42c0c3..896165096d6a 100644 --- a/arch/arm/kernel/irq.c +++ b/arch/arm/kernel/irq.c @@ -34,6 +34,7 @@ #include <linux/list.h> #include <linux/kallsyms.h> #include <linux/proc_fs.h> +#include <linux/export.h> #include <asm/exception.h> #include <asm/mach/arch.h> @@ -109,6 +110,7 @@ void set_irq_flags(unsigned int irq, unsigned int iflags) /* Order is clear bits in "clr" then set bits in "set" */ irq_modify_status(irq, clr, set & ~clr); } +EXPORT_SYMBOL_GPL(set_irq_flags); void __init init_IRQ(void) { diff --git a/arch/arm/kernel/kprobes-test-arm.c b/arch/arm/kernel/kprobes-test-arm.c index 38c1a3b103a0..839312905067 100644 --- a/arch/arm/kernel/kprobes-test-arm.c +++ b/arch/arm/kernel/kprobes-test-arm.c @@ -366,7 +366,9 @@ void kprobe_arm_test_cases(void) TEST_UNSUPPORTED(".word 0xe04f0392 @ umaal r0, pc, r2, r3") TEST_UNSUPPORTED(".word 0xe0500090 @ undef") TEST_UNSUPPORTED(".word 0xe05fff9f @ undef") +#endif +#if __LINUX_ARM_ARCH__ >= 7 TEST_RRR( "mls r0, r",1, VAL1,", r",2, VAL2,", r",3, VAL3,"") TEST_RRR( "mlshi r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"") TEST_RR( "mls lr, r",1, VAL2,", r",2, VAL3,", r13") @@ -456,6 +458,8 @@ void kprobe_arm_test_cases(void) TEST_UNSUPPORTED(".word 0xe1700090") /* Unallocated space */ #if __LINUX_ARM_ARCH__ >= 6 TEST_UNSUPPORTED("ldrex r2, [sp]") +#endif +#if (__LINUX_ARM_ARCH__ >= 7) || defined(CONFIG_CPU_32v6K) TEST_UNSUPPORTED("strexd r0, r2, r3, [sp]") TEST_UNSUPPORTED("ldrexd r2, r3, [sp]") TEST_UNSUPPORTED("strexb r0, r2, [sp]") diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c index dfcdb9f7c126..8ef8c9337809 100644 --- a/arch/arm/kernel/machine_kexec.c +++ b/arch/arm/kernel/machine_kexec.c @@ -8,7 +8,9 @@ #include <linux/reboot.h> #include <linux/io.h> #include <linux/irq.h> +#include <linux/memblock.h> #include <asm/pgtable.h> +#include <linux/of_fdt.h> #include <asm/pgalloc.h> #include <asm/mmu_context.h> #include <asm/cacheflush.h> @@ -32,6 +34,28 @@ static atomic_t waiting_for_crash_ipi; int machine_kexec_prepare(struct kimage *image) { + struct kexec_segment *current_segment; + __be32 header; + int i, err; + + /* + * No segment at default ATAGs address. try to locate + * a dtb using magic. + */ + for (i = 0; i < image->nr_segments; i++) { + current_segment = &image->segment[i]; + + if (!memblock_is_region_memory(current_segment->mem, + current_segment->memsz)) + return -EINVAL; + + err = get_user(header, (__be32*)current_segment->buf); + if (err) + return err; + + if (be32_to_cpu(header) == OF_DT_HEADER) + kexec_boot_atags = current_segment->mem; + } return 0; } @@ -122,7 +146,9 @@ void machine_kexec(struct kimage *image) kexec_start_address = image->start; kexec_indirection_page = page_list; kexec_mach_type = machine_arch_type; - kexec_boot_atags = image->start - KEXEC_ARM_ZIMAGE_OFFSET + KEXEC_ARM_ATAGS_OFFSET; + if (!kexec_boot_atags) + kexec_boot_atags = image->start - KEXEC_ARM_ZIMAGE_OFFSET + KEXEC_ARM_ATAGS_OFFSET; + /* copy our kernel relocation code to the control code page */ memcpy(reboot_code_buffer, diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c index 93971b1a4f0b..53c0304b734a 100644 --- a/arch/arm/kernel/perf_event.c +++ b/arch/arm/kernel/perf_event.c @@ -96,6 +96,10 @@ armpmu_event_set_period(struct perf_event *event, s64 period = hwc->sample_period; int ret = 0; + /* The period may have been changed by PERF_EVENT_IOC_PERIOD */ + if (unlikely(period != hwc->last_period)) + left = period - (hwc->last_period - left); + if (unlikely(left <= -period)) { left = period; local64_set(&hwc->period_left, left); diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c index 04eea22d7958..90084a6de35a 100644 --- a/arch/arm/kernel/process.c +++ b/arch/arm/kernel/process.c @@ -381,13 +381,20 @@ copy_thread(unsigned long clone_flags, unsigned long stack_start, struct thread_info *thread = task_thread_info(p); struct pt_regs *childregs = task_pt_regs(p); - *childregs = *regs; - childregs->ARM_r0 = 0; - childregs->ARM_sp = stack_start; - memset(&thread->cpu_context, 0, sizeof(struct cpu_context_save)); - thread->cpu_context.sp = (unsigned long)childregs; + + if (likely(regs)) { + *childregs = *regs; + childregs->ARM_r0 = 0; + childregs->ARM_sp = stack_start; + } else { + memset(childregs, 0, sizeof(struct pt_regs)); + thread->cpu_context.r4 = stk_sz; + thread->cpu_context.r5 = stack_start; + childregs->ARM_cpsr = SVC_MODE; + } thread->cpu_context.pc = (unsigned long)ret_from_fork; + thread->cpu_context.sp = (unsigned long)childregs; clear_ptrace_hw_breakpoint(p); @@ -423,63 +430,6 @@ int dump_fpu (struct pt_regs *regs, struct user_fp *fp) } EXPORT_SYMBOL(dump_fpu); -/* - * Shuffle the argument into the correct register before calling the - * thread function. r4 is the thread argument, r5 is the pointer to - * the thread function, and r6 points to the exit function. - */ -extern void kernel_thread_helper(void); -asm( ".pushsection .text\n" -" .align\n" -" .type kernel_thread_helper, #function\n" -"kernel_thread_helper:\n" -#ifdef CONFIG_TRACE_IRQFLAGS -" bl trace_hardirqs_on\n" -#endif -" msr cpsr_c, r7\n" -" mov r0, r4\n" -" mov lr, r6\n" -" mov pc, r5\n" -" .size kernel_thread_helper, . - kernel_thread_helper\n" -" .popsection"); - -#ifdef CONFIG_ARM_UNWIND -extern void kernel_thread_exit(long code); -asm( ".pushsection .text\n" -" .align\n" -" .type kernel_thread_exit, #function\n" -"kernel_thread_exit:\n" -" .fnstart\n" -" .cantunwind\n" -" bl do_exit\n" -" nop\n" -" .fnend\n" -" .size kernel_thread_exit, . - kernel_thread_exit\n" -" .popsection"); -#else -#define kernel_thread_exit do_exit -#endif - -/* - * Create a kernel thread. - */ -pid_t kernel_thread(int (*fn)(void *), void *arg, unsigned long flags) -{ - struct pt_regs regs; - - memset(®s, 0, sizeof(regs)); - - regs.ARM_r4 = (unsigned long)arg; - regs.ARM_r5 = (unsigned long)fn; - regs.ARM_r6 = (unsigned long)kernel_thread_exit; - regs.ARM_r7 = SVC_MODE | PSR_ENDSTATE | PSR_ISETSTATE; - regs.ARM_pc = (unsigned long)kernel_thread_helper; - regs.ARM_cpsr = regs.ARM_r7 | PSR_I_BIT; - - return do_fork(flags|CLONE_VM|CLONE_UNTRACED, 0, ®s, 0, NULL, NULL); -} -EXPORT_SYMBOL(kernel_thread); - unsigned long get_wchan(struct task_struct *p) { struct stackframe frame; diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c index 3e0fc5f7ed4b..739db3a1b2d2 100644 --- a/arch/arm/kernel/ptrace.c +++ b/arch/arm/kernel/ptrace.c @@ -30,6 +30,9 @@ #include <asm/pgtable.h> #include <asm/traps.h> +#define CREATE_TRACE_POINTS +#include <trace/events/syscalls.h> + #define REG_PC 15 #define REG_PSR 16 /* @@ -918,11 +921,11 @@ static int ptrace_syscall_trace(struct pt_regs *regs, int scno, { unsigned long ip; + current_thread_info()->syscall = scno; + if (!test_thread_flag(TIF_SYSCALL_TRACE)) return scno; - current_thread_info()->syscall = scno; - /* * IP is used to denote syscall entry/exit: * IP = 0 -> entry, =1 -> exit @@ -941,15 +944,19 @@ static int ptrace_syscall_trace(struct pt_regs *regs, int scno, asmlinkage int syscall_trace_enter(struct pt_regs *regs, int scno) { - int ret = ptrace_syscall_trace(regs, scno, PTRACE_SYSCALL_ENTER); + scno = ptrace_syscall_trace(regs, scno, PTRACE_SYSCALL_ENTER); + if (test_thread_flag(TIF_SYSCALL_TRACEPOINT)) + trace_sys_enter(regs, scno); audit_syscall_entry(AUDIT_ARCH_ARM, scno, regs->ARM_r0, regs->ARM_r1, regs->ARM_r2, regs->ARM_r3); - return ret; + return scno; } asmlinkage int syscall_trace_exit(struct pt_regs *regs, int scno) { - int ret = ptrace_syscall_trace(regs, scno, PTRACE_SYSCALL_EXIT); + scno = ptrace_syscall_trace(regs, scno, PTRACE_SYSCALL_EXIT); + if (test_thread_flag(TIF_SYSCALL_TRACEPOINT)) + trace_sys_exit(regs, scno); audit_syscall_exit(regs); - return ret; + return scno; } diff --git a/arch/arm/kernel/sched_clock.c b/arch/arm/kernel/sched_clock.c index f4515393248d..e21bac20d90d 100644 --- a/arch/arm/kernel/sched_clock.c +++ b/arch/arm/kernel/sched_clock.c @@ -9,6 +9,7 @@ #include <linux/init.h> #include <linux/jiffies.h> #include <linux/kernel.h> +#include <linux/moduleparam.h> #include <linux/sched.h> #include <linux/syscore_ops.h> #include <linux/timer.h> @@ -27,6 +28,9 @@ struct clock_data { static void sched_clock_poll(unsigned long wrap_ticks); static DEFINE_TIMER(sched_clock_timer, sched_clock_poll, 0, 0); +static int irqtime = -1; + +core_param(irqtime, irqtime, int, 0400); static struct clock_data cd = { .mult = NSEC_PER_SEC / HZ, @@ -157,6 +161,10 @@ void __init setup_sched_clock(u32 (*read)(void), int bits, unsigned long rate) */ cd.epoch_ns = 0; + /* Enable IRQ time accounting if we have a fast enough sched_clock */ + if (irqtime > 0 || (irqtime == -1 && rate >= 1000000)) + enable_sched_clock_irqtime(); + pr_debug("Registered %pF as sched_clock source\n", read); } diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 725f9f2a9541..da1d1aa20ad9 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -21,11 +21,9 @@ #include <linux/init.h> #include <linux/kexec.h> #include <linux/of_fdt.h> -#include <linux/root_dev.h> #include <linux/cpu.h> #include <linux/interrupt.h> #include <linux/smp.h> -#include <linux/fs.h> #include <linux/proc_fs.h> #include <linux/memblock.h> #include <linux/bug.h> @@ -55,16 +53,11 @@ #include <asm/traps.h> #include <asm/unwind.h> #include <asm/memblock.h> +#include <asm/virt.h> -#if defined(CONFIG_DEPRECATED_PARAM_STRUCT) -#include "compat.h" -#endif #include "atags.h" #include "tcm.h" -#ifndef MEM_SIZE -#define MEM_SIZE (16*1024*1024) -#endif #if defined(CONFIG_FPE_NWFPE) || defined(CONFIG_FPE_FASTFPE) char fpe_type[8]; @@ -145,7 +138,6 @@ static const char *machine_name; static char __initdata cmd_line[COMMAND_LINE_SIZE]; struct machine_desc *machine_desc __initdata; -static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE; static union { char c[4]; unsigned long l; } endian_test __initdata = { { 'l', '?', '?', 'b' } }; #define ENDIANNESS ((char)endian_test.l) @@ -583,21 +575,6 @@ static int __init early_mem(char *p) } early_param("mem", early_mem); -static void __init -setup_ramdisk(int doload, int prompt, int image_start, unsigned int rd_sz) -{ -#ifdef CONFIG_BLK_DEV_RAM - extern int rd_size, rd_image_start, rd_prompt, rd_doload; - - rd_image_start = image_start; - rd_prompt = prompt; - rd_doload = doload; - - if (rd_sz) - rd_size = rd_sz; -#endif -} - static void __init request_standard_resources(struct machine_desc *mdesc) { struct memblock_region *region; @@ -643,35 +620,6 @@ static void __init request_standard_resources(struct machine_desc *mdesc) request_resource(&ioport_resource, &lp2); } -/* - * Tag parsing. - * - * This is the new way of passing data to the kernel at boot time. Rather - * than passing a fixed inflexible structure to the kernel, we pass a list - * of variable-sized tags to the kernel. The first tag must be a ATAG_CORE - * tag for the list to be recognised (to distinguish the tagged list from - * a param_struct). The list is terminated with a zero-length tag (this tag - * is not parsed in any way). - */ -static int __init parse_tag_core(const struct tag *tag) -{ - if (tag->hdr.size > 2) { - if ((tag->u.core.flags & 1) == 0) - root_mountflags &= ~MS_RDONLY; - ROOT_DEV = old_decode_dev(tag->u.core.rootdev); - } - return 0; -} - -__tagtable(ATAG_CORE, parse_tag_core); - -static int __init parse_tag_mem32(const struct tag *tag) -{ - return arm_add_memory(tag->u.mem.start, tag->u.mem.size); -} - -__tagtable(ATAG_MEM, parse_tag_mem32); - #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE) struct screen_info screen_info = { .orig_video_lines = 30, @@ -681,117 +629,8 @@ struct screen_info screen_info = { .orig_video_isVGA = 1, .orig_video_points = 8 }; - -static int __init parse_tag_videotext(const struct tag *tag) -{ - screen_info.orig_x = tag->u.videotext.x; - screen_info.orig_y = tag->u.videotext.y; - screen_info.orig_video_page = tag->u.videotext.video_page; - screen_info.orig_video_mode = tag->u.videotext.video_mode; - screen_info.orig_video_cols = tag->u.videotext.video_cols; - screen_info.orig_video_ega_bx = tag->u.videotext.video_ega_bx; - screen_info.orig_video_lines = tag->u.videotext.video_lines; - screen_info.orig_video_isVGA = tag->u.videotext.video_isvga; - screen_info.orig_video_points = tag->u.videotext.video_points; - return 0; -} - -__tagtable(ATAG_VIDEOTEXT, parse_tag_videotext); #endif -static int __init parse_tag_ramdisk(const struct tag *tag) -{ - setup_ramdisk((tag->u.ramdisk.flags & 1) == 0, - (tag->u.ramdisk.flags & 2) == 0, - tag->u.ramdisk.start, tag->u.ramdisk.size); - return 0; -} - -__tagtable(ATAG_RAMDISK, parse_tag_ramdisk); - -static int __init parse_tag_serialnr(const struct tag *tag) -{ - system_serial_low = tag->u.serialnr.low; - system_serial_high = tag->u.serialnr.high; - return 0; -} - -__tagtable(ATAG_SERIAL, parse_tag_serialnr); - -static int __init parse_tag_revision(const struct tag *tag) -{ - system_rev = tag->u.revision.rev; - return 0; -} - -__tagtable(ATAG_REVISION, parse_tag_revision); - -static int __init parse_tag_cmdline(const struct tag *tag) -{ -#if defined(CONFIG_CMDLINE_EXTEND) - strlcat(default_command_line, " ", COMMAND_LINE_SIZE); - strlcat(default_command_line, tag->u.cmdline.cmdline, - COMMAND_LINE_SIZE); -#elif defined(CONFIG_CMDLINE_FORCE) - pr_warning("Ignoring tag cmdline (using the default kernel command line)\n"); -#else - strlcpy(default_command_line, tag->u.cmdline.cmdline, - COMMAND_LINE_SIZE); -#endif - return 0; -} - -__tagtable(ATAG_CMDLINE, parse_tag_cmdline); - -/* - * Scan the tag table for this tag, and call its parse function. - * The tag table is built by the linker from all the __tagtable - * declarations. - */ -static int __init parse_tag(const struct tag *tag) -{ - extern struct tagtable __tagtable_begin, __tagtable_end; - struct tagtable *t; - - for (t = &__tagtable_begin; t < &__tagtable_end; t++) - if (tag->hdr.tag == t->tag) { - t->parse(tag); - break; - } - - return t < &__tagtable_end; -} - -/* - * Parse all tags in the list, checking both the global and architecture - * specific tag tables. - */ -static void __init parse_tags(const struct tag *t) -{ - for (; t->hdr.size; t = tag_next(t)) - if (!parse_tag(t)) - printk(KERN_WARNING - "Ignoring unrecognised tag 0x%08x\n", - t->hdr.tag); -} - -/* - * This holds our defaults. - */ -static struct init_tags { - struct tag_header hdr1; - struct tag_core core; - struct tag_header hdr2; - struct tag_mem32 mem; - struct tag_header hdr3; -} init_tags __initdata = { - { tag_size(tag_core), ATAG_CORE }, - { 1, PAGE_SIZE, 0xff }, - { tag_size(tag_mem32), ATAG_MEM }, - { MEM_SIZE }, - { 0, ATAG_NONE } -}; - static int __init customize_machine(void) { /* customizes platform devices, or adds new ones */ @@ -858,78 +697,6 @@ static void __init reserve_crashkernel(void) static inline void reserve_crashkernel(void) {} #endif /* CONFIG_KEXEC */ -static void __init squash_mem_tags(struct tag *tag) -{ - for (; tag->hdr.size; tag = tag_next(tag)) - if (tag->hdr.tag == ATAG_MEM) - tag->hdr.tag = ATAG_NONE; -} - -static struct machine_desc * __init setup_machine_tags(unsigned int nr) -{ - struct tag *tags = (struct tag *)&init_tags; - struct machine_desc *mdesc = NULL, *p; - char *from = default_command_line; - - init_tags.mem.start = PHYS_OFFSET; - - /* - * locate machine in the list of supported machines. - */ - for_each_machine_desc(p) - if (nr == p->nr) { - printk("Machine: %s\n", p->name); - mdesc = p; - break; - } - - if (!mdesc) { - early_print("\nError: unrecognized/unsupported machine ID" - " (r1 = 0x%08x).\n\n", nr); - dump_machine_table(); /* does not return */ - } - - if (__atags_pointer) - tags = phys_to_virt(__atags_pointer); - else if (mdesc->atag_offset) - tags = (void *)(PAGE_OFFSET + mdesc->atag_offset); - -#if defined(CONFIG_DEPRECATED_PARAM_STRUCT) - /* - * If we have the old style parameters, convert them to - * a tag list. - */ - if (tags->hdr.tag != ATAG_CORE) - convert_to_tag_list(tags); -#endif - - if (tags->hdr.tag != ATAG_CORE) { -#if defined(CONFIG_OF) - /* - * If CONFIG_OF is set, then assume this is a reasonably - * modern system that should pass boot parameters - */ - early_print("Warning: Neither atags nor dtb found\n"); -#endif - tags = (struct tag *)&init_tags; - } - - if (mdesc->fixup) - mdesc->fixup(tags, &from, &meminfo); - - if (tags->hdr.tag == ATAG_CORE) { - if (meminfo.nr_banks != 0) - squash_mem_tags(tags); - save_atags(tags); - parse_tags(tags); - } - - /* parse_early_param needs a boot_command_line */ - strlcpy(boot_command_line, from, COMMAND_LINE_SIZE); - - return mdesc; -} - static int __init meminfo_cmp(const void *_a, const void *_b) { const struct membank *a = _a, *b = _b; @@ -937,6 +704,21 @@ static int __init meminfo_cmp(const void *_a, const void *_b) return cmp < 0 ? -1 : cmp > 0 ? 1 : 0; } +void __init hyp_mode_check(void) +{ +#ifdef CONFIG_ARM_VIRT_EXT + if (is_hyp_mode_available()) { + pr_info("CPU: All CPU(s) started in HYP mode.\n"); + pr_info("CPU: Virtualization extensions available.\n"); + } else if (is_hyp_mode_mismatched()) { + pr_warn("CPU: WARNING: CPU(s) started in wrong/inconsistent modes (primary CPU mode 0x%x)\n", + __boot_cpu_mode & MODE_MASK); + pr_warn("CPU: This may indicate a broken bootloader or firmware.\n"); + } else + pr_info("CPU: All CPU(s) started in SVC mode.\n"); +#endif +} + void __init setup_arch(char **cmdline_p) { struct machine_desc *mdesc; @@ -944,7 +726,7 @@ void __init setup_arch(char **cmdline_p) setup_processor(); mdesc = setup_machine_fdt(__atags_pointer); if (!mdesc) - mdesc = setup_machine_tags(machine_arch_type); + mdesc = setup_machine_tags(__atags_pointer, machine_arch_type); machine_desc = mdesc; machine_name = mdesc->name; @@ -982,6 +764,10 @@ void __init setup_arch(char **cmdline_p) smp_init_cpus(); } #endif + + if (!is_smp()) + hyp_mode_check(); + reserve_crashkernel(); tcm_init(); diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c index f27789e4e38a..56f72d257ebd 100644 --- a/arch/arm/kernel/signal.c +++ b/arch/arm/kernel/signal.c @@ -10,7 +10,6 @@ #include <linux/errno.h> #include <linux/signal.h> #include <linux/personality.h> -#include <linux/freezer.h> #include <linux/uaccess.h> #include <linux/tracehook.h> diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index dea7a925c7e2..fbc8b2623d82 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -43,6 +43,7 @@ #include <asm/ptrace.h> #include <asm/localtimer.h> #include <asm/smp_plat.h> +#include <asm/virt.h> #include <asm/mach/arch.h> /* @@ -59,7 +60,8 @@ struct secondary_data secondary_data; volatile int __cpuinitdata pen_release = -1; enum ipi_msg_type { - IPI_TIMER = 2, + IPI_WAKEUP, + IPI_TIMER, IPI_RESCHEDULE, IPI_CALL_FUNC, IPI_CALL_FUNC_SINGLE, @@ -201,8 +203,11 @@ int __cpuinit __cpu_disable(void) /* * Flush user cache and TLB mappings, and then remove this CPU * from the vm mask set of all processes. + * + * Caches are flushed to the Level of Unification Inner Shareable + * to write-back dirty lines to unified caches shared by all CPUs. */ - flush_cache_all(); + flush_cache_louis(); local_flush_tlb_all(); clear_tasks_mm_cpumask(cpu); @@ -289,18 +294,24 @@ static void percpu_timer_setup(void); asmlinkage void __cpuinit secondary_start_kernel(void) { struct mm_struct *mm = &init_mm; - unsigned int cpu = smp_processor_id(); + unsigned int cpu; + + /* + * The identity mapping is uncached (strongly ordered), so + * switch away from it before attempting any exclusive accesses. + */ + cpu_switch_mm(mm->pgd, mm); + enter_lazy_tlb(mm, current); + local_flush_tlb_all(); /* * All kernel threads share the same mm context; grab a * reference and switch to it. */ + cpu = smp_processor_id(); atomic_inc(&mm->mm_count); current->active_mm = mm; cpumask_set_cpu(cpu, mm_cpumask(mm)); - cpu_switch_mm(mm->pgd, mm); - enter_lazy_tlb(mm, current); - local_flush_tlb_all(); printk("CPU%u: Booted secondary processor\n", cpu); @@ -354,6 +365,8 @@ void __init smp_cpus_done(unsigned int max_cpus) num_online_cpus(), bogosum / (500000/HZ), (bogosum / (5000/HZ)) % 100); + + hyp_mode_check(); } void __init smp_prepare_boot_cpu(void) @@ -414,7 +427,8 @@ void arch_send_call_function_single_ipi(int cpu) } static const char *ipi_types[NR_IPI] = { -#define S(x,s) [x - IPI_TIMER] = s +#define S(x,s) [x] = s + S(IPI_WAKEUP, "CPU wakeup interrupts"), S(IPI_TIMER, "Timer broadcast interrupts"), S(IPI_RESCHEDULE, "Rescheduling interrupts"), S(IPI_CALL_FUNC, "Function call interrupts"), @@ -567,10 +581,13 @@ void handle_IPI(int ipinr, struct pt_regs *regs) unsigned int cpu = smp_processor_id(); struct pt_regs *old_regs = set_irq_regs(regs); - if (ipinr >= IPI_TIMER && ipinr < IPI_TIMER + NR_IPI) - __inc_irq_stat(cpu, ipi_irqs[ipinr - IPI_TIMER]); + if (ipinr < NR_IPI) + __inc_irq_stat(cpu, ipi_irqs[ipinr]); switch (ipinr) { + case IPI_WAKEUP: + break; + case IPI_TIMER: irq_enter(); ipi_timer(); diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c index e1f906989bb8..b22d700fea27 100644 --- a/arch/arm/kernel/smp_twd.c +++ b/arch/arm/kernel/smp_twd.c @@ -42,10 +42,10 @@ static void twd_set_mode(enum clock_event_mode mode, switch (mode) { case CLOCK_EVT_MODE_PERIODIC: - /* timer load already set up */ ctrl = TWD_TIMER_CONTROL_ENABLE | TWD_TIMER_CONTROL_IT_ENABLE | TWD_TIMER_CONTROL_PERIODIC; - __raw_writel(twd_timer_rate / HZ, twd_base + TWD_TIMER_LOAD); + __raw_writel(DIV_ROUND_CLOSEST(twd_timer_rate, HZ), + twd_base + TWD_TIMER_LOAD); break; case CLOCK_EVT_MODE_ONESHOT: /* period set, and timer enabled in 'next_event' hook */ diff --git a/arch/arm/kernel/suspend.c b/arch/arm/kernel/suspend.c index 1794cc3b0f18..358bca3a995e 100644 --- a/arch/arm/kernel/suspend.c +++ b/arch/arm/kernel/suspend.c @@ -17,6 +17,8 @@ extern void cpu_resume_mmu(void); */ void __cpu_suspend_save(u32 *ptr, u32 ptrsz, u32 sp, u32 *save_ptr) { + u32 *ctx = ptr; + *save_ptr = virt_to_phys(ptr); /* This must correspond to the LDM in cpu_resume() assembly */ @@ -26,7 +28,20 @@ void __cpu_suspend_save(u32 *ptr, u32 ptrsz, u32 sp, u32 *save_ptr) cpu_do_suspend(ptr); - flush_cache_all(); + flush_cache_louis(); + + /* + * flush_cache_louis does not guarantee that + * save_ptr and ptr are cleaned to main memory, + * just up to the Level of Unification Inner Shareable. + * Since the context pointer and context itself + * are to be retrieved with the MMU off that + * data must be cleaned from all cache levels + * to main memory using "area" cache primitives. + */ + __cpuc_flush_dcache_area(ctx, ptrsz); + __cpuc_flush_dcache_area(save_ptr, sizeof(*save_ptr)); + outer_clean_range(*save_ptr, *save_ptr + ptrsz); outer_clean_range(virt_to_phys(save_ptr), virt_to_phys(save_ptr) + sizeof(*save_ptr)); diff --git a/arch/arm/kernel/sys_arm.c b/arch/arm/kernel/sys_arm.c index 76cbb055dd05..c2a898aa57aa 100644 --- a/arch/arm/kernel/sys_arm.c +++ b/arch/arm/kernel/sys_arm.c @@ -59,69 +59,6 @@ asmlinkage int sys_vfork(struct pt_regs *regs) return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->ARM_sp, regs, 0, NULL, NULL); } -/* sys_execve() executes a new program. - * This is called indirectly via a small wrapper - */ -asmlinkage int sys_execve(const char __user *filenamei, - const char __user *const __user *argv, - const char __user *const __user *envp, struct pt_regs *regs) -{ - int error; - char * filename; - - filename = getname(filenamei); - error = PTR_ERR(filename); - if (IS_ERR(filename)) - goto out; - error = do_execve(filename, argv, envp, regs); - putname(filename); -out: - return error; -} - -int kernel_execve(const char *filename, - const char *const argv[], - const char *const envp[]) -{ - struct pt_regs regs; - int ret; - - memset(®s, 0, sizeof(struct pt_regs)); - ret = do_execve(filename, - (const char __user *const __user *)argv, - (const char __user *const __user *)envp, ®s); - if (ret < 0) - goto out; - - /* - * Save argc to the register structure for userspace. - */ - regs.ARM_r0 = ret; - - /* - * We were successful. We won't be returning to our caller, but - * instead to user space by manipulating the kernel stack. - */ - asm( "add r0, %0, %1\n\t" - "mov r1, %2\n\t" - "mov r2, %3\n\t" - "bl memmove\n\t" /* copy regs to top of stack */ - "mov r8, #0\n\t" /* not a syscall */ - "mov r9, %0\n\t" /* thread structure */ - "mov sp, r0\n\t" /* reposition stack pointer */ - "b ret_to_user" - : - : "r" (current_thread_info()), - "Ir" (THREAD_START_SP - sizeof(regs)), - "r" (®s), - "Ir" (sizeof(regs)) - : "r0", "r1", "r2", "r3", "r8", "r9", "ip", "lr", "memory"); - - out: - return ret; -} -EXPORT_SYMBOL(kernel_execve); - /* * Since loff_t is a 64 bit type we avoid a lot of ABI hassle * with a different argument ordering. diff --git a/arch/arm/lib/delay.c b/arch/arm/lib/delay.c index 395d5fbb8fa2..0dc53854a5d8 100644 --- a/arch/arm/lib/delay.c +++ b/arch/arm/lib/delay.c @@ -34,7 +34,19 @@ struct arm_delay_ops arm_delay_ops = { .udelay = __loop_udelay, }; -#ifdef ARCH_HAS_READ_CURRENT_TIMER +static const struct delay_timer *delay_timer; +static bool delay_calibrated; + +int read_current_timer(unsigned long *timer_val) +{ + if (!delay_timer) + return -ENXIO; + + *timer_val = delay_timer->read_current_timer(); + return 0; +} +EXPORT_SYMBOL_GPL(read_current_timer); + static void __timer_delay(unsigned long cycles) { cycles_t start = get_cycles(); @@ -55,18 +67,24 @@ static void __timer_udelay(unsigned long usecs) __timer_const_udelay(usecs * UDELAY_MULT); } -void __init init_current_timer_delay(unsigned long freq) +void __init register_current_timer_delay(const struct delay_timer *timer) { - pr_info("Switching to timer-based delay loop\n"); - lpj_fine = freq / HZ; - loops_per_jiffy = lpj_fine; - arm_delay_ops.delay = __timer_delay; - arm_delay_ops.const_udelay = __timer_const_udelay; - arm_delay_ops.udelay = __timer_udelay; + if (!delay_calibrated) { + pr_info("Switching to timer-based delay loop\n"); + delay_timer = timer; + lpj_fine = timer->freq / HZ; + loops_per_jiffy = lpj_fine; + arm_delay_ops.delay = __timer_delay; + arm_delay_ops.const_udelay = __timer_const_udelay; + arm_delay_ops.udelay = __timer_udelay; + delay_calibrated = true; + } else { + pr_info("Ignoring duplicate/late registration of read_current_timer delay\n"); + } } unsigned long __cpuinit calibrate_delay_is_known(void) { + delay_calibrated = true; return lpj_fine; } -#endif diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index c8050b14e615..043624219b55 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -19,75 +19,69 @@ config AT91_SAM9G45_RESET config SOC_AT91SAM9 bool - select GENERIC_CLOCKEVENTS select CPU_ARM926T + select GENERIC_CLOCKEVENTS + select MULTI_IRQ_HANDLER + select SPARSE_IRQ menu "Atmel AT91 System-on-Chip" comment "Atmel AT91 Processor" -config SOC_AT91SAM9 - bool - select CPU_ARM926T - select MULTI_IRQ_HANDLER - select SPARSE_IRQ - select AT91_SAM9_TIME - select AT91_SAM9_SMC - config SOC_AT91RM9200 bool "AT91RM9200" select CPU_ARM920T - select MULTI_IRQ_HANDLER - select SPARSE_IRQ select GENERIC_CLOCKEVENTS select HAVE_AT91_DBGU0 + select MULTI_IRQ_HANDLER + select SPARSE_IRQ config SOC_AT91SAM9260 bool "AT91SAM9260, AT91SAM9XE or AT91SAM9G20" - select SOC_AT91SAM9 select HAVE_AT91_DBGU0 select HAVE_NET_MACB + select SOC_AT91SAM9 help Select this if you are using one of Atmel's AT91SAM9260, AT91SAM9XE or AT91SAM9G20 SoC. config SOC_AT91SAM9261 bool "AT91SAM9261 or AT91SAM9G10" - select SOC_AT91SAM9 select HAVE_AT91_DBGU0 select HAVE_FB_ATMEL + select SOC_AT91SAM9 help Select this if you are using one of Atmel's AT91SAM9261 or AT91SAM9G10 SoC. config SOC_AT91SAM9263 bool "AT91SAM9263" - select SOC_AT91SAM9 select HAVE_AT91_DBGU1 select HAVE_FB_ATMEL select HAVE_NET_MACB + select SOC_AT91SAM9 config SOC_AT91SAM9RL bool "AT91SAM9RL" - select SOC_AT91SAM9 select HAVE_AT91_DBGU0 select HAVE_FB_ATMEL + select SOC_AT91SAM9 config SOC_AT91SAM9G45 bool "AT91SAM9G45 or AT91SAM9M10 families" - select SOC_AT91SAM9 select HAVE_AT91_DBGU1 select HAVE_FB_ATMEL select HAVE_NET_MACB + select SOC_AT91SAM9 help Select this if you are using one of Atmel's AT91SAM9G45 family SoC. This support covers AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11. config SOC_AT91SAM9X5 bool "AT91SAM9x5 family" - select SOC_AT91SAM9 select HAVE_AT91_DBGU0 select HAVE_FB_ATMEL select HAVE_NET_MACB + select SOC_AT91SAM9 help Select this if you are using one of Atmel's AT91SAM9x5 family SoC. This means that your SAM9 name finishes with a '5' (except if it is @@ -97,9 +91,9 @@ config SOC_AT91SAM9X5 config SOC_AT91SAM9N12 bool "AT91SAM9N12 family" - select SOC_AT91SAM9 select HAVE_AT91_DBGU0 select HAVE_FB_ATMEL + select SOC_AT91SAM9 help Select this if you are using Atmel's AT91SAM9N12 SoC. @@ -144,9 +138,9 @@ config ARCH_AT91SAM9G45 config ARCH_AT91X40 bool "AT91x40" depends on !MMU + select ARCH_USES_GETTIMEOFFSET select MULTI_IRQ_HANDLER select SPARSE_IRQ - select ARCH_USES_GETTIMEOFFSET endchoice diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c index 6f50c6722276..5269825194a8 100644 --- a/arch/arm/mach-at91/at91rm9200.c +++ b/arch/arm/mach-at91/at91rm9200.c @@ -187,6 +187,7 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk), + CLKDEV_CON_DEV_ID(NULL, "i2c-at91rm9200.0", &twi_clk), /* fake hclk clock */ CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk), CLKDEV_CON_ID("pioA", &pioA_clk), diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c index 9ac427a702da..1e122bcd7845 100644 --- a/arch/arm/mach-at91/at91rm9200_devices.c +++ b/arch/arm/mach-at91/at91rm9200_devices.c @@ -479,7 +479,7 @@ static struct i2c_gpio_platform_data pdata = { static struct platform_device at91rm9200_twi_device = { .name = "i2c-gpio", - .id = -1, + .id = 0, .dev.platform_data = &pdata, }; @@ -511,8 +511,8 @@ static struct resource twi_resources[] = { }; static struct platform_device at91rm9200_twi_device = { - .name = "at91_i2c", - .id = -1, + .name = "i2c-at91rm9200", + .id = 0, .resource = twi_resources, .num_resources = ARRAY_SIZE(twi_resources), }; diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c index 30c7f26a4668..f8202615f4a8 100644 --- a/arch/arm/mach-at91/at91sam9260.c +++ b/arch/arm/mach-at91/at91sam9260.c @@ -211,6 +211,8 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk), CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc_clk), + CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk), + CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi_clk), /* more usart lookup table for DT entries */ CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck), CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk), @@ -219,6 +221,7 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk), CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk), CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk), + CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi_clk), /* more tc lookup table for DT entries */ CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk), CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk), diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c index af50ff3281c7..aa1e58729885 100644 --- a/arch/arm/mach-at91/at91sam9260_devices.c +++ b/arch/arm/mach-at91/at91sam9260_devices.c @@ -389,7 +389,7 @@ static struct i2c_gpio_platform_data pdata = { static struct platform_device at91sam9260_twi_device = { .name = "i2c-gpio", - .id = -1, + .id = 0, .dev.platform_data = &pdata, }; @@ -421,14 +421,20 @@ static struct resource twi_resources[] = { }; static struct platform_device at91sam9260_twi_device = { - .name = "at91_i2c", - .id = -1, + .id = 0, .resource = twi_resources, .num_resources = ARRAY_SIZE(twi_resources), }; void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) { + /* IP version is not the same on 9260 and g20 */ + if (cpu_is_at91sam9g20()) { + at91sam9260_twi_device.name = "i2c-at91sam9g20"; + } else { + at91sam9260_twi_device.name = "i2c-at91sam9260"; + } + /* pins used for TWI interface */ at91_set_A_periph(AT91_PIN_PA23, 0); /* TWD */ at91_set_multi_drive(AT91_PIN_PA23, 1); diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c index f40762c5fede..04295c04b3e0 100644 --- a/arch/arm/mach-at91/at91sam9261.c +++ b/arch/arm/mach-at91/at91sam9261.c @@ -178,6 +178,8 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk), CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &hck0), + CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9261.0", &twi_clk), + CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi_clk), CLKDEV_CON_ID("pioA", &pioA_clk), CLKDEV_CON_ID("pioB", &pioB_clk), CLKDEV_CON_ID("pioC", &pioC_clk), diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c index 11e9fa835cde..b9487696b7be 100644 --- a/arch/arm/mach-at91/at91sam9261_devices.c +++ b/arch/arm/mach-at91/at91sam9261_devices.c @@ -285,7 +285,7 @@ static struct i2c_gpio_platform_data pdata = { static struct platform_device at91sam9261_twi_device = { .name = "i2c-gpio", - .id = -1, + .id = 0, .dev.platform_data = &pdata, }; @@ -317,20 +317,26 @@ static struct resource twi_resources[] = { }; static struct platform_device at91sam9261_twi_device = { - .name = "at91_i2c", - .id = -1, + .id = 0, .resource = twi_resources, .num_resources = ARRAY_SIZE(twi_resources), }; void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) { + /* IP version is not the same on 9261 and g10 */ + if (cpu_is_at91sam9g10()) { + at91sam9261_twi_device.name = "i2c-at91sam9g10"; + /* I2C PIO must not be configured as open-drain on this chip */ + } else { + at91sam9261_twi_device.name = "i2c-at91sam9261"; + at91_set_multi_drive(AT91_PIN_PA7, 1); + at91_set_multi_drive(AT91_PIN_PA8, 1); + } + /* pins used for TWI interface */ at91_set_A_periph(AT91_PIN_PA7, 0); /* TWD */ - at91_set_multi_drive(AT91_PIN_PA7, 1); - at91_set_A_periph(AT91_PIN_PA8, 0); /* TWCK */ - at91_set_multi_drive(AT91_PIN_PA8, 1); i2c_register_board_info(0, devices, nr_devices); platform_device_register(&at91sam9261_twi_device); diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c index 144ef5de51b6..d6f9c23927c4 100644 --- a/arch/arm/mach-at91/at91sam9263.c +++ b/arch/arm/mach-at91/at91sam9263.c @@ -193,6 +193,7 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk), CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk), + CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk), /* fake hclk clock */ CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk), CLKDEV_CON_ID("pioA", &pioA_clk), @@ -210,6 +211,7 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("hclk", "a00000.ohci", &ohci_clk), CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk), CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk), + CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi_clk), }; static struct clk_lookup usart_clocks_lookups[] = { diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c index 7c0898fe20fa..cb85da2eccea 100644 --- a/arch/arm/mach-at91/at91sam9263_devices.c +++ b/arch/arm/mach-at91/at91sam9263_devices.c @@ -567,7 +567,7 @@ static struct i2c_gpio_platform_data pdata = { static struct platform_device at91sam9263_twi_device = { .name = "i2c-gpio", - .id = -1, + .id = 0, .dev.platform_data = &pdata, }; @@ -599,8 +599,8 @@ static struct resource twi_resources[] = { }; static struct platform_device at91sam9263_twi_device = { - .name = "at91_i2c", - .id = -1, + .name = "i2c-at91sam9260", + .id = 0, .resource = twi_resources, .num_resources = ARRAY_SIZE(twi_resources), }; diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c index ef6cedd52e3c..84af1b506d92 100644 --- a/arch/arm/mach-at91/at91sam9g45.c +++ b/arch/arm/mach-at91/at91sam9g45.c @@ -237,6 +237,8 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk), CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk), CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk), + CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi0_clk), + CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.1", &twi1_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk), @@ -254,6 +256,8 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("t0_clk", "fffd4000.timer", &tcb0_clk), CLKDEV_CON_DEV_ID("hclk", "700000.ohci", &uhphs_clk), CLKDEV_CON_DEV_ID("ehci_clk", "800000.ehci", &uhphs_clk), + CLKDEV_CON_DEV_ID(NULL, "fff84000.i2c", &twi0_clk), + CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk), /* fake hclk clock */ CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk), CLKDEV_CON_ID("pioA", &pioA_clk), diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c index e4c3b3709204..b1596072dcc2 100644 --- a/arch/arm/mach-at91/at91sam9g45_devices.c +++ b/arch/arm/mach-at91/at91sam9g45_devices.c @@ -653,7 +653,7 @@ static struct resource twi0_resources[] = { }; static struct platform_device at91sam9g45_twi0_device = { - .name = "at91_i2c", + .name = "i2c-at91sam9g10", .id = 0, .resource = twi0_resources, .num_resources = ARRAY_SIZE(twi0_resources), @@ -673,7 +673,7 @@ static struct resource twi1_resources[] = { }; static struct platform_device at91sam9g45_twi1_device = { - .name = "at91_i2c", + .name = "i2c-at91sam9g10", .id = 1, .resource = twi1_resources, .num_resources = ARRAY_SIZE(twi1_resources), @@ -686,18 +686,12 @@ void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, in /* pins used for TWI interface */ if (i2c_id == 0) { at91_set_A_periph(AT91_PIN_PA20, 0); /* TWD */ - at91_set_multi_drive(AT91_PIN_PA20, 1); - at91_set_A_periph(AT91_PIN_PA21, 0); /* TWCK */ - at91_set_multi_drive(AT91_PIN_PA21, 1); platform_device_register(&at91sam9g45_twi0_device); } else { at91_set_A_periph(AT91_PIN_PB10, 0); /* TWD */ - at91_set_multi_drive(AT91_PIN_PB10, 1); - at91_set_A_periph(AT91_PIN_PB11, 0); /* TWCK */ - at91_set_multi_drive(AT91_PIN_PB11, 1); platform_device_register(&at91sam9g45_twi1_device); } diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c index 08494664ab78..732d3d3f4ec5 100644 --- a/arch/arm/mach-at91/at91sam9n12.c +++ b/arch/arm/mach-at91/at91sam9n12.c @@ -169,6 +169,8 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb_clk), CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb_clk), CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk), + CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk), + CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk), CLKDEV_CON_ID("pioA", &pioAB_clk), CLKDEV_CON_ID("pioB", &pioAB_clk), CLKDEV_CON_ID("pioC", &pioCD_clk), diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c index 72ce50a50de5..72e908412222 100644 --- a/arch/arm/mach-at91/at91sam9rl.c +++ b/arch/arm/mach-at91/at91sam9rl.c @@ -186,6 +186,8 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), + CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi0_clk), + CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.1", &twi1_clk), CLKDEV_CON_ID("pioA", &pioA_clk), CLKDEV_CON_ID("pioB", &pioB_clk), CLKDEV_CON_ID("pioC", &pioC_clk), diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c index deafea0e493d..5047bdc92adf 100644 --- a/arch/arm/mach-at91/at91sam9rl_devices.c +++ b/arch/arm/mach-at91/at91sam9rl_devices.c @@ -314,7 +314,7 @@ static struct i2c_gpio_platform_data pdata = { static struct platform_device at91sam9rl_twi_device = { .name = "i2c-gpio", - .id = -1, + .id = 0, .dev.platform_data = &pdata, }; @@ -346,8 +346,8 @@ static struct resource twi_resources[] = { }; static struct platform_device at91sam9rl_twi_device = { - .name = "at91_i2c", - .id = -1, + .name = "i2c-at91sam9g20", + .id = 0, .resource = twi_resources, .num_resources = ARRAY_SIZE(twi_resources), }; diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c index 477cf9d06672..e5035380dcbc 100644 --- a/arch/arm/mach-at91/at91sam9x5.c +++ b/arch/arm/mach-at91/at91sam9x5.c @@ -231,6 +231,9 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk), CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma0_clk), CLKDEV_CON_DEV_ID("dma_clk", "ffffee00.dma-controller", &dma1_clk), + CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk), + CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk), + CLKDEV_CON_DEV_ID(NULL, "f8018000.i2c", &twi2_clk), CLKDEV_CON_ID("pioA", &pioAB_clk), CLKDEV_CON_ID("pioB", &pioAB_clk), CLKDEV_CON_ID("pioC", &pioCD_clk), diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c index 6bd7300a2bc5..bb7f54474b92 100644 --- a/arch/arm/mach-at91/at91x40.c +++ b/arch/arm/mach-at91/at91x40.c @@ -88,6 +88,6 @@ void __init at91x40_init_interrupts(unsigned int priority[NR_AIC_IRQS]) if (!priority) priority = at91x40_default_irq_priority; - at91_aic_init(priority); + at91_aic_init(priority, at91_extern_irq); } diff --git a/arch/arm/mach-at91/board-neocore926.c b/arch/arm/mach-at91/board-neocore926.c index 9cda3fd346ae..6960778af4c2 100644 --- a/arch/arm/mach-at91/board-neocore926.c +++ b/arch/arm/mach-at91/board-neocore926.c @@ -129,7 +129,7 @@ static struct spi_board_info neocore926_spi_devices[] = { .max_speed_hz = 125000 * 16, .bus_num = 0, .platform_data = &ads_info, - .irq = AT91SAM9263_ID_IRQ1, + .irq = NR_IRQS_LEGACY + AT91SAM9263_ID_IRQ1, }, #endif }; diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c index 27b3af1a3047..a9167dd45f96 100644 --- a/arch/arm/mach-at91/board-sam9261ek.c +++ b/arch/arm/mach-at91/board-sam9261ek.c @@ -309,7 +309,7 @@ static struct spi_board_info ek_spi_devices[] = { .max_speed_hz = 125000 * 26, /* (max sample rate @ 3V) * (cmd + data + overhead) */ .bus_num = 0, .platform_data = &ads_info, - .irq = AT91SAM9261_ID_IRQ0, + .irq = NR_IRQS_LEGACY + AT91SAM9261_ID_IRQ0, .controller_data = (void *) AT91_PIN_PA28, /* CS pin */ }, #endif diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c index 073e17403d98..b87dbe2be0d6 100644 --- a/arch/arm/mach-at91/board-sam9263ek.c +++ b/arch/arm/mach-at91/board-sam9263ek.c @@ -132,7 +132,7 @@ static struct spi_board_info ek_spi_devices[] = { .max_speed_hz = 125000 * 26, /* (max sample rate @ 3V) * (cmd + data + overhead) */ .bus_num = 0, .platform_data = &ads_info, - .irq = AT91SAM9263_ID_IRQ1, + .irq = NR_IRQS_LEGACY + AT91SAM9263_ID_IRQ1, }, #endif }; diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c index 188c82971ebd..33361505c0cd 100644 --- a/arch/arm/mach-at91/clock.c +++ b/arch/arm/mach-at91/clock.c @@ -625,7 +625,7 @@ fail: return 0; } -static struct clk *const standard_pmc_clocks[] __initdata = { +static struct clk *const standard_pmc_clocks[] __initconst = { /* four primary clocks */ &clk32k, &main_clk, diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h index f49650677653..b62f560e6c75 100644 --- a/arch/arm/mach-at91/generic.h +++ b/arch/arm/mach-at91/generic.h @@ -26,7 +26,8 @@ extern void __init at91_dt_initialize(void); extern void __init at91_init_irq_default(void); extern void __init at91_init_interrupts(unsigned int priority[]); extern void __init at91x40_init_interrupts(unsigned int priority[]); -extern void __init at91_aic_init(unsigned int priority[]); +extern void __init at91_aic_init(unsigned int priority[], + unsigned int ext_irq_mask); extern int __init at91_aic_of_init(struct device_node *node, struct device_node *parent); extern int __init at91_aic5_of_init(struct device_node *node, diff --git a/arch/arm/mach-at91/include/mach/at91_twi.h b/arch/arm/mach-at91/include/mach/at91_twi.h deleted file mode 100644 index bb2880f6ba37..000000000000 --- a/arch/arm/mach-at91/include/mach/at91_twi.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * arch/arm/mach-at91/include/mach/at91_twi.h - * - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) SAN People - * - * Two-wire Interface (TWI) registers. - * Based on AT91RM9200 datasheet revision E. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_TWI_H -#define AT91_TWI_H - -#define AT91_TWI_CR 0x00 /* Control Register */ -#define AT91_TWI_START (1 << 0) /* Send a Start Condition */ -#define AT91_TWI_STOP (1 << 1) /* Send a Stop Condition */ -#define AT91_TWI_MSEN (1 << 2) /* Master Transfer Enable */ -#define AT91_TWI_MSDIS (1 << 3) /* Master Transfer Disable */ -#define AT91_TWI_SVEN (1 << 4) /* Slave Transfer Enable [SAM9260 only] */ -#define AT91_TWI_SVDIS (1 << 5) /* Slave Transfer Disable [SAM9260 only] */ -#define AT91_TWI_SWRST (1 << 7) /* Software Reset */ - -#define AT91_TWI_MMR 0x04 /* Master Mode Register */ -#define AT91_TWI_IADRSZ (3 << 8) /* Internal Device Address Size */ -#define AT91_TWI_IADRSZ_NO (0 << 8) -#define AT91_TWI_IADRSZ_1 (1 << 8) -#define AT91_TWI_IADRSZ_2 (2 << 8) -#define AT91_TWI_IADRSZ_3 (3 << 8) -#define AT91_TWI_MREAD (1 << 12) /* Master Read Direction */ -#define AT91_TWI_DADR (0x7f << 16) /* Device Address */ - -#define AT91_TWI_SMR 0x08 /* Slave Mode Register [SAM9260 only] */ -#define AT91_TWI_SADR (0x7f << 16) /* Slave Address */ - -#define AT91_TWI_IADR 0x0c /* Internal Address Register */ - -#define AT91_TWI_CWGR 0x10 /* Clock Waveform Generator Register */ -#define AT91_TWI_CLDIV (0xff << 0) /* Clock Low Divisor */ -#define AT91_TWI_CHDIV (0xff << 8) /* Clock High Divisor */ -#define AT91_TWI_CKDIV (7 << 16) /* Clock Divider */ - -#define AT91_TWI_SR 0x20 /* Status Register */ -#define AT91_TWI_TXCOMP (1 << 0) /* Transmission Complete */ -#define AT91_TWI_RXRDY (1 << 1) /* Receive Holding Register Ready */ -#define AT91_TWI_TXRDY (1 << 2) /* Transmit Holding Register Ready */ -#define AT91_TWI_SVREAD (1 << 3) /* Slave Read [SAM9260 only] */ -#define AT91_TWI_SVACC (1 << 4) /* Slave Access [SAM9260 only] */ -#define AT91_TWI_GACC (1 << 5) /* General Call Access [SAM9260 only] */ -#define AT91_TWI_OVRE (1 << 6) /* Overrun Error [AT91RM9200 only] */ -#define AT91_TWI_UNRE (1 << 7) /* Underrun Error [AT91RM9200 only] */ -#define AT91_TWI_NACK (1 << 8) /* Not Acknowledged */ -#define AT91_TWI_ARBLST (1 << 9) /* Arbitration Lost [SAM9260 only] */ -#define AT91_TWI_SCLWS (1 << 10) /* Clock Wait State [SAM9260 only] */ -#define AT91_TWI_EOSACC (1 << 11) /* End of Slave Address [SAM9260 only] */ - -#define AT91_TWI_IER 0x24 /* Interrupt Enable Register */ -#define AT91_TWI_IDR 0x28 /* Interrupt Disable Register */ -#define AT91_TWI_IMR 0x2c /* Interrupt Mask Register */ -#define AT91_TWI_RHR 0x30 /* Receive Holding Register */ -#define AT91_TWI_THR 0x34 /* Transmit Holding Register */ - -#endif - diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c index 1e02c0e49dcc..febc2ee901a5 100644 --- a/arch/arm/mach-at91/irq.c +++ b/arch/arm/mach-at91/irq.c @@ -502,14 +502,19 @@ int __init at91_aic5_of_init(struct device_node *node, /* * Initialize the AIC interrupt controller. */ -void __init at91_aic_init(unsigned int *priority) +void __init at91_aic_init(unsigned int *priority, unsigned int ext_irq_mask) { unsigned int i; int irq_base; - if (at91_aic_pm_init()) + at91_extern_irq = kzalloc(BITS_TO_LONGS(n_irqs) + * sizeof(*at91_extern_irq), GFP_KERNEL); + + if (at91_aic_pm_init() || at91_extern_irq == NULL) panic("Unable to allocate bit maps\n"); + *at91_extern_irq = ext_irq_mask; + at91_aic_base = ioremap(AT91_AIC, 512); if (!at91_aic_base) panic("Unable to ioremap AIC registers\n"); diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 2c2d86505a54..5315f05896e9 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -153,7 +153,9 @@ static int at91_pm_verify_clocks(void) } } -#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS + if (!IS_ENABLED(CONFIG_AT91_PROGRAMMABLE_CLOCKS)) + return 1; + /* PCK0..PCK3 must be disabled, or configured to use clk32k */ for (i = 0; i < 4; i++) { u32 css; @@ -167,7 +169,6 @@ static int at91_pm_verify_clocks(void) return 0; } } -#endif return 1; } diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c index e6f52de1062f..0b32c81730a5 100644 --- a/arch/arm/mach-at91/setup.c +++ b/arch/arm/mach-at91/setup.c @@ -47,7 +47,7 @@ void __init at91_init_irq_default(void) void __init at91_init_interrupts(unsigned int *priority) { /* Initialize the AIC interrupt controller */ - at91_aic_init(priority); + at91_aic_init(priority, at91_extern_irq); /* Enable GPIO interrupts */ at91_gpio_irq_setup(); @@ -87,7 +87,7 @@ void __init at91_init_sram(int bank, unsigned long base, unsigned int length) iotable_init(desc, 1); } -static struct map_desc at91_io_desc __initdata = { +static struct map_desc at91_io_desc __initdata __maybe_unused = { .virtual = (unsigned long)AT91_VA_BASE_SYS, .pfn = __phys_to_pfn(AT91_BASE_SYS), .length = SZ_16K, @@ -151,7 +151,7 @@ static void __init soc_detect(u32 dbgu_base) } /* at91sam9g10 */ - if ((cidr & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) { + if ((socid & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) { at91_soc_initdata.type = AT91_SOC_SAM9G10; at91_boot_soc = at91sam9261_soc; } diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig index e6135363765a..263242da2cb8 100644 --- a/arch/arm/mach-clps711x/Kconfig +++ b/arch/arm/mach-clps711x/Kconfig @@ -23,9 +23,9 @@ config ARCH_CLEP7312 config ARCH_EDB7211 bool "EDB7211" - select ISA - select ARCH_SPARSEMEM_ENABLE select ARCH_SELECT_MEMORY_MODEL + select ARCH_SPARSEMEM_ENABLE + select ISA help Say Y here if you intend to run this kernel on a Cirrus Logic EDB-7211 evaluation board. diff --git a/arch/arm/mach-clps711x/autcpu12.c b/arch/arm/mach-clps711x/autcpu12.c index 3fb79a1d0bde..32871918bb6e 100644 --- a/arch/arm/mach-clps711x/autcpu12.c +++ b/arch/arm/mach-clps711x/autcpu12.c @@ -23,6 +23,8 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/io.h> +#include <linux/ioport.h> +#include <linux/platform_device.h> #include <mach/hardware.h> #include <asm/sizes.h> @@ -62,9 +64,26 @@ void __init autcpu12_map_io(void) iotable_init(autcpu12_io_desc, ARRAY_SIZE(autcpu12_io_desc)); } +static struct resource autcpu12_nvram_resource[] __initdata = { + DEFINE_RES_MEM_NAMED(AUTCPU12_PHYS_NVRAM, SZ_128K, "SRAM"), +}; + +static struct platform_device autcpu12_nvram_pdev __initdata = { + .name = "autcpu12_nvram", + .id = -1, + .resource = autcpu12_nvram_resource, + .num_resources = ARRAY_SIZE(autcpu12_nvram_resource), +}; + +static void __init autcpu12_init(void) +{ + platform_device_register(&autcpu12_nvram_pdev); +} + MACHINE_START(AUTCPU12, "autronix autcpu12") /* Maintainer: Thomas Gleixner */ .atag_offset = 0x20000, + .init_machine = autcpu12_init, .map_io = autcpu12_map_io, .init_irq = clps711x_init_irq, .timer = &clps711x_timer, diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index ab99c3c3b752..f8eecb959413 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -4,12 +4,12 @@ config AINTC bool config CP_INTC - select IRQ_DOMAIN bool + select IRQ_DOMAIN config ARCH_DAVINCI_DMx - select CPU_ARM926T bool + select CPU_ARM926T menu "TI DaVinci Implementations" @@ -32,19 +32,19 @@ config ARCH_DAVINCI_DM646x config ARCH_DAVINCI_DA830 bool "DA830/OMAP-L137/AM17x based system" - select CP_INTC select ARCH_DAVINCI_DA8XX select CPU_DCACHE_WRITETHROUGH # needed on silicon revs 1.0, 1.1 + select CP_INTC config ARCH_DAVINCI_DA850 bool "DA850/OMAP-L138/AM18x based system" - select CP_INTC select ARCH_DAVINCI_DA8XX select ARCH_HAS_CPUFREQ + select CP_INTC config ARCH_DAVINCI_DA8XX - select CPU_ARM926T bool + select CPU_ARM926T config ARCH_DAVINCI_DM365 bool "DaVinci 365 based system" @@ -52,9 +52,9 @@ config ARCH_DAVINCI_DM365 select ARCH_DAVINCI_DMx config ARCH_DAVINCI_TNETV107X + bool "TNETV107X based system" select CPU_V6 select CP_INTC - bool "TNETV107X based system" comment "DaVinci Board Type" @@ -103,9 +103,9 @@ config MACH_DAVINCI_DM6467_EVM bool "TI DM6467 EVM" default ARCH_DAVINCI_DM646x depends on ARCH_DAVINCI_DM646x - select MACH_DAVINCI_DM6467TEVM select EEPROM_AT24 select I2C + select MACH_DAVINCI_DM6467TEVM help Configure this option to specify the whether the board used for development is a DM6467 EVM @@ -127,8 +127,8 @@ config MACH_DAVINCI_DA830_EVM bool "TI DA830/OMAP-L137/AM17x Reference Platform" default ARCH_DAVINCI_DA830 depends on ARCH_DAVINCI_DA830 - select GPIO_PCF857X select EEPROM_AT24 + select GPIO_PCF857X select I2C help Say Y here to select the TI DA830/OMAP-L137/AM17x Evaluation Module. @@ -186,6 +186,13 @@ config DA850_UI_RMII NOTE: Please take care while choosing this option, MII PHY will not be functional if RMII mode is selected. +config DA850_UI_SD_VIDEO_PORT + bool "Video Port Interface" + help + Say Y if you want to use Video Port Interface (VPIF) on the + DA850/OMAP-L138 EVM. The Video decoders/encoders are found on the + UI daughter card that is supplied with the EVM. + endchoice config DA850_WL12XX diff --git a/arch/arm/mach-davinci/asp.h b/arch/arm/mach-davinci/asp.h new file mode 100644 index 000000000000..d9b2acd12393 --- /dev/null +++ b/arch/arm/mach-davinci/asp.h @@ -0,0 +1,49 @@ +/* + * TI DaVinci Audio definitions + */ +#ifndef __ASM_ARCH_DAVINCI_ASP_H +#define __ASM_ARCH_DAVINCI_ASP_H + +/* Bases of dm644x and dm355 register banks */ +#define DAVINCI_ASP0_BASE 0x01E02000 +#define DAVINCI_ASP1_BASE 0x01E04000 + +/* Bases of dm365 register banks */ +#define DAVINCI_DM365_ASP0_BASE 0x01D02000 + +/* Bases of dm646x register banks */ +#define DAVINCI_DM646X_MCASP0_REG_BASE 0x01D01000 +#define DAVINCI_DM646X_MCASP1_REG_BASE 0x01D01800 + +/* Bases of da850/da830 McASP0 register banks */ +#define DAVINCI_DA8XX_MCASP0_REG_BASE 0x01D00000 + +/* Bases of da830 McASP1 register banks */ +#define DAVINCI_DA830_MCASP1_REG_BASE 0x01D04000 + +/* EDMA channels of dm644x and dm355 */ +#define DAVINCI_DMA_ASP0_TX 2 +#define DAVINCI_DMA_ASP0_RX 3 +#define DAVINCI_DMA_ASP1_TX 8 +#define DAVINCI_DMA_ASP1_RX 9 + +/* EDMA channels of dm646x */ +#define DAVINCI_DM646X_DMA_MCASP0_AXEVT0 6 +#define DAVINCI_DM646X_DMA_MCASP0_AREVT0 9 +#define DAVINCI_DM646X_DMA_MCASP1_AXEVT1 12 + +/* EDMA channels of da850/da830 McASP0 */ +#define DAVINCI_DA8XX_DMA_MCASP0_AREVT 0 +#define DAVINCI_DA8XX_DMA_MCASP0_AXEVT 1 + +/* EDMA channels of da830 McASP1 */ +#define DAVINCI_DA830_DMA_MCASP1_AREVT 2 +#define DAVINCI_DA830_DMA_MCASP1_AXEVT 3 + +/* Interrupts */ +#define DAVINCI_ASP0_RX_INT IRQ_MBRINT +#define DAVINCI_ASP0_TX_INT IRQ_MBXINT +#define DAVINCI_ASP1_RX_INT IRQ_MBRINT +#define DAVINCI_ASP1_TX_INT IRQ_MBXINT + +#endif /* __ASM_ARCH_DAVINCI_ASP_H */ diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index 1295e616ceee..32ee3f895967 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -45,6 +45,9 @@ #include <linux/platform_data/mtd-davinci-aemif.h> #include <linux/platform_data/spi-davinci.h> +#include <media/tvp514x.h> +#include <media/adv7343.h> + #define DA850_EVM_PHY_ID "davinci_mdio-0:00" #define DA850_LCD_PWR_PIN GPIO_TO_PIN(2, 8) #define DA850_LCD_BL_PIN GPIO_TO_PIN(2, 15) @@ -452,6 +455,15 @@ static void da850_evm_ui_keys_init(unsigned gpio) } } +#ifdef CONFIG_DA850_UI_SD_VIDEO_PORT +static inline void da850_evm_setup_video_port(int video_sel) +{ + gpio_set_value_cansleep(video_sel, 0); +} +#else +static inline void da850_evm_setup_video_port(int video_sel) { } +#endif + static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio, unsigned ngpio, void *c) { @@ -497,6 +509,8 @@ static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio, da850_evm_setup_emac_rmii(sel_a); + da850_evm_setup_video_port(sel_c); + return 0; exp_setup_keys_fail: @@ -1149,6 +1163,169 @@ static __init int da850_evm_init_cpufreq(void) static __init int da850_evm_init_cpufreq(void) { return 0; } #endif +#if defined(CONFIG_DA850_UI_SD_VIDEO_PORT) + +#define TVP5147_CH0 "tvp514x-0" +#define TVP5147_CH1 "tvp514x-1" + +/* VPIF capture configuration */ +static struct tvp514x_platform_data tvp5146_pdata = { + .clk_polarity = 0, + .hs_polarity = 1, + .vs_polarity = 1, +}; + +#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL) + +static const struct vpif_input da850_ch0_inputs[] = { + { + .input = { + .index = 0, + .name = "Composite", + .type = V4L2_INPUT_TYPE_CAMERA, + .capabilities = V4L2_IN_CAP_STD, + .std = TVP514X_STD_ALL, + }, + .input_route = INPUT_CVBS_VI2B, + .output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC, + .subdev_name = TVP5147_CH0, + }, +}; + +static const struct vpif_input da850_ch1_inputs[] = { + { + .input = { + .index = 0, + .name = "S-Video", + .type = V4L2_INPUT_TYPE_CAMERA, + .capabilities = V4L2_IN_CAP_STD, + .std = TVP514X_STD_ALL, + }, + .input_route = INPUT_SVIDEO_VI2C_VI1C, + .output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC, + .subdev_name = TVP5147_CH1, + }, +}; + +static struct vpif_subdev_info da850_vpif_capture_sdev_info[] = { + { + .name = TVP5147_CH0, + .board_info = { + I2C_BOARD_INFO("tvp5146", 0x5d), + .platform_data = &tvp5146_pdata, + }, + }, + { + .name = TVP5147_CH1, + .board_info = { + I2C_BOARD_INFO("tvp5146", 0x5c), + .platform_data = &tvp5146_pdata, + }, + }, +}; + +static struct vpif_capture_config da850_vpif_capture_config = { + .subdev_info = da850_vpif_capture_sdev_info, + .subdev_count = ARRAY_SIZE(da850_vpif_capture_sdev_info), + .chan_config[0] = { + .inputs = da850_ch0_inputs, + .input_count = ARRAY_SIZE(da850_ch0_inputs), + .vpif_if = { + .if_type = VPIF_IF_BT656, + .hd_pol = 1, + .vd_pol = 1, + .fid_pol = 0, + }, + }, + .chan_config[1] = { + .inputs = da850_ch1_inputs, + .input_count = ARRAY_SIZE(da850_ch1_inputs), + .vpif_if = { + .if_type = VPIF_IF_BT656, + .hd_pol = 1, + .vd_pol = 1, + .fid_pol = 0, + }, + }, + .card_name = "DA850/OMAP-L138 Video Capture", +}; + +/* VPIF display configuration */ +static struct vpif_subdev_info da850_vpif_subdev[] = { + { + .name = "adv7343", + .board_info = { + I2C_BOARD_INFO("adv7343", 0x2a), + }, + }, +}; + +static const struct vpif_output da850_ch0_outputs[] = { + { + .output = { + .index = 0, + .name = "Composite", + .type = V4L2_OUTPUT_TYPE_ANALOG, + .capabilities = V4L2_OUT_CAP_STD, + .std = V4L2_STD_ALL, + }, + .subdev_name = "adv7343", + .output_route = ADV7343_COMPOSITE_ID, + }, + { + .output = { + .index = 1, + .name = "S-Video", + .type = V4L2_OUTPUT_TYPE_ANALOG, + .capabilities = V4L2_OUT_CAP_STD, + .std = V4L2_STD_ALL, + }, + .subdev_name = "adv7343", + .output_route = ADV7343_SVIDEO_ID, + }, +}; + +static struct vpif_display_config da850_vpif_display_config = { + .subdevinfo = da850_vpif_subdev, + .subdev_count = ARRAY_SIZE(da850_vpif_subdev), + .chan_config[0] = { + .outputs = da850_ch0_outputs, + .output_count = ARRAY_SIZE(da850_ch0_outputs), + }, + .card_name = "DA850/OMAP-L138 Video Display", +}; + +static __init void da850_vpif_init(void) +{ + int ret; + + ret = da850_register_vpif(); + if (ret) + pr_warn("da850_evm_init: VPIF setup failed: %d\n", ret); + + ret = davinci_cfg_reg_list(da850_vpif_capture_pins); + if (ret) + pr_warn("da850_evm_init: VPIF capture mux setup failed: %d\n", + ret); + + ret = da850_register_vpif_capture(&da850_vpif_capture_config); + if (ret) + pr_warn("da850_evm_init: VPIF capture setup failed: %d\n", ret); + + ret = davinci_cfg_reg_list(da850_vpif_display_pins); + if (ret) + pr_warn("da850_evm_init: VPIF display mux setup failed: %d\n", + ret); + + ret = da850_register_vpif_display(&da850_vpif_display_config); + if (ret) + pr_warn("da850_evm_init: VPIF display setup failed: %d\n", ret); +} + +#else +static __init void da850_vpif_init(void) {} +#endif + #ifdef CONFIG_DA850_WL12XX static void wl12xx_set_power(int index, bool power_on) @@ -1375,6 +1552,8 @@ static __init void da850_evm_init(void) pr_warning("da850_evm_init: suspend registration failed: %d\n", ret); + da850_vpif_init(); + ret = da8xx_register_spi(1, da850evm_spi_info, ARRAY_SIZE(da850evm_spi_info)); if (ret) diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c index ca72fc4b8cca..f22572cee49d 100644 --- a/arch/arm/mach-davinci/board-dm644x-evm.c +++ b/arch/arm/mach-davinci/board-dm644x-evm.c @@ -23,6 +23,7 @@ #include <linux/phy.h> #include <linux/clk.h> #include <linux/videodev2.h> +#include <linux/v4l2-dv-timings.h> #include <linux/export.h> #include <media/tvp514x.h> @@ -620,7 +621,7 @@ static struct vpbe_enc_mode_info dm644xevm_enc_std_timing[] = { { .name = "ntsc", .timings_type = VPBE_ENC_STD, - .timings = {V4L2_STD_525_60}, + .std_id = V4L2_STD_525_60, .interlaced = 1, .xres = 720, .yres = 480, @@ -632,7 +633,7 @@ static struct vpbe_enc_mode_info dm644xevm_enc_std_timing[] = { { .name = "pal", .timings_type = VPBE_ENC_STD, - .timings = {V4L2_STD_625_50}, + .std_id = V4L2_STD_625_50, .interlaced = 1, .xres = 720, .yres = 576, @@ -647,8 +648,8 @@ static struct vpbe_enc_mode_info dm644xevm_enc_std_timing[] = { static struct vpbe_enc_mode_info dm644xevm_enc_preset_timing[] = { { .name = "480p59_94", - .timings_type = VPBE_ENC_DV_PRESET, - .timings = {V4L2_DV_480P59_94}, + .timings_type = VPBE_ENC_CUSTOM_TIMINGS, + .dv_timings = V4L2_DV_BT_CEA_720X480P59_94, .interlaced = 0, .xres = 720, .yres = 480, @@ -659,8 +660,8 @@ static struct vpbe_enc_mode_info dm644xevm_enc_preset_timing[] = { }, { .name = "576p50", - .timings_type = VPBE_ENC_DV_PRESET, - .timings = {V4L2_DV_576P50}, + .timings_type = VPBE_ENC_CUSTOM_TIMINGS, + .dv_timings = V4L2_DV_BT_CEA_720X576P50, .interlaced = 0, .xres = 720, .yres = 576, @@ -698,7 +699,7 @@ static struct vpbe_output dm644xevm_vpbe_outputs[] = { .index = 1, .name = "Component", .type = V4L2_OUTPUT_TYPE_ANALOG, - .capabilities = V4L2_OUT_CAP_PRESETS, + .capabilities = V4L2_OUT_CAP_DV_TIMINGS, }, .subdev_name = VPBE_VENC_SUBDEV_NAME, .default_mode = "480p59_94", diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c index 9944367b4931..1dbf85beed1b 100644 --- a/arch/arm/mach-davinci/board-dm646x-evm.c +++ b/arch/arm/mach-davinci/board-dm646x-evm.c @@ -26,6 +26,7 @@ #include <linux/i2c/pcf857x.h> #include <media/tvp514x.h> +#include <media/adv7343.h> #include <linux/mtd/mtd.h> #include <linux/mtd/nand.h> @@ -496,18 +497,49 @@ static struct vpif_subdev_info dm646x_vpif_subdev[] = { }, }; -static const char *output[] = { - "Composite", - "Component", - "S-Video", +static const struct vpif_output dm6467_ch0_outputs[] = { + { + .output = { + .index = 0, + .name = "Composite", + .type = V4L2_OUTPUT_TYPE_ANALOG, + .capabilities = V4L2_OUT_CAP_STD, + .std = V4L2_STD_ALL, + }, + .subdev_name = "adv7343", + .output_route = ADV7343_COMPOSITE_ID, + }, + { + .output = { + .index = 1, + .name = "Component", + .type = V4L2_OUTPUT_TYPE_ANALOG, + .capabilities = V4L2_OUT_CAP_CUSTOM_TIMINGS, + }, + .subdev_name = "adv7343", + .output_route = ADV7343_COMPONENT_ID, + }, + { + .output = { + .index = 2, + .name = "S-Video", + .type = V4L2_OUTPUT_TYPE_ANALOG, + .capabilities = V4L2_OUT_CAP_STD, + .std = V4L2_STD_ALL, + }, + .subdev_name = "adv7343", + .output_route = ADV7343_SVIDEO_ID, + }, }; static struct vpif_display_config dm646x_vpif_display_config = { .set_clock = set_vpif_clock, .subdevinfo = dm646x_vpif_subdev, .subdev_count = ARRAY_SIZE(dm646x_vpif_subdev), - .output = output, - .output_count = ARRAY_SIZE(output), + .chan_config[0] = { + .outputs = dm6467_ch0_outputs, + .output_count = ARRAY_SIZE(dm6467_ch0_outputs), + }, .card_name = "DM646x EVM", }; @@ -601,15 +633,6 @@ static struct vpif_subdev_info vpif_capture_sdev_info[] = { I2C_BOARD_INFO("tvp5146", 0x5d), .platform_data = &tvp5146_pdata, }, - .input = INPUT_CVBS_VI2B, - .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, - .can_route = 1, - .vpif_if = { - .if_type = VPIF_IF_BT656, - .hd_pol = 1, - .vd_pol = 1, - .fid_pol = 0, - }, }, { .name = TVP5147_CH1, @@ -617,15 +640,6 @@ static struct vpif_subdev_info vpif_capture_sdev_info[] = { I2C_BOARD_INFO("tvp5146", 0x5c), .platform_data = &tvp5146_pdata, }, - .input = INPUT_SVIDEO_VI2C_VI1C, - .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, - .can_route = 1, - .vpif_if = { - .if_type = VPIF_IF_BT656, - .hd_pol = 1, - .vd_pol = 1, - .fid_pol = 0, - }, }, }; @@ -635,9 +649,12 @@ static const struct vpif_input dm6467_ch0_inputs[] = { .index = 0, .name = "Composite", .type = V4L2_INPUT_TYPE_CAMERA, + .capabilities = V4L2_IN_CAP_STD, .std = TVP514X_STD_ALL, }, .subdev_name = TVP5147_CH0, + .input_route = INPUT_CVBS_VI2B, + .output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC, }, }; @@ -647,9 +664,12 @@ static const struct vpif_input dm6467_ch1_inputs[] = { .index = 0, .name = "S-Video", .type = V4L2_INPUT_TYPE_CAMERA, + .capabilities = V4L2_IN_CAP_STD, .std = TVP514X_STD_ALL, }, .subdev_name = TVP5147_CH1, + .input_route = INPUT_SVIDEO_VI2C_VI1C, + .output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC, }, }; @@ -661,10 +681,22 @@ static struct vpif_capture_config dm646x_vpif_capture_cfg = { .chan_config[0] = { .inputs = dm6467_ch0_inputs, .input_count = ARRAY_SIZE(dm6467_ch0_inputs), + .vpif_if = { + .if_type = VPIF_IF_BT656, + .hd_pol = 1, + .vd_pol = 1, + .fid_pol = 0, + }, }, .chan_config[1] = { .inputs = dm6467_ch1_inputs, .input_count = ARRAY_SIZE(dm6467_ch1_inputs), + .vpif_if = { + .if_type = VPIF_IF_BT656, + .hd_pol = 1, + .vd_pol = 1, + .fid_pol = 0, + }, }, }; diff --git a/arch/arm/mach-davinci/board-tnetv107x-evm.c b/arch/arm/mach-davinci/board-tnetv107x-evm.c index ac4e003ad863..be3099733b1f 100644 --- a/arch/arm/mach-davinci/board-tnetv107x-evm.c +++ b/arch/arm/mach-davinci/board-tnetv107x-evm.c @@ -88,7 +88,7 @@ static struct davinci_mmc_config mmc_config = { .version = MMC_CTLR_VERSION_1, }; -static const short sdio1_pins[] __initdata = { +static const short sdio1_pins[] __initconst = { TNETV107X_SDIO1_CLK_1, TNETV107X_SDIO1_CMD_1, TNETV107X_SDIO1_DATA0_1, TNETV107X_SDIO1_DATA1_1, TNETV107X_SDIO1_DATA2_1, TNETV107X_SDIO1_DATA3_1, @@ -96,12 +96,12 @@ static const short sdio1_pins[] __initdata = { -1 }; -static const short uart1_pins[] __initdata = { +static const short uart1_pins[] __initconst = { TNETV107X_UART1_RD, TNETV107X_UART1_TD, -1 }; -static const short ssp_pins[] __initdata = { +static const short ssp_pins[] __initconst = { TNETV107X_SSP0_0, TNETV107X_SSP0_1, TNETV107X_SSP0_2, TNETV107X_SSP1_0, TNETV107X_SSP1_1, TNETV107X_SSP1_2, TNETV107X_SSP1_3, -1 diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c index deee5c2da754..510648e0394b 100644 --- a/arch/arm/mach-davinci/da830.c +++ b/arch/arm/mach-davinci/da830.c @@ -838,7 +838,7 @@ static const struct mux_config da830_pins[] = { #endif }; -const short da830_emif25_pins[] __initdata = { +const short da830_emif25_pins[] __initconst = { DA830_EMA_D_0, DA830_EMA_D_1, DA830_EMA_D_2, DA830_EMA_D_3, DA830_EMA_D_4, DA830_EMA_D_5, DA830_EMA_D_6, DA830_EMA_D_7, DA830_EMA_D_8, DA830_EMA_D_9, DA830_EMA_D_10, DA830_EMA_D_11, @@ -853,19 +853,19 @@ const short da830_emif25_pins[] __initdata = { -1 }; -const short da830_spi0_pins[] __initdata = { +const short da830_spi0_pins[] __initconst = { DA830_SPI0_SOMI_0, DA830_SPI0_SIMO_0, DA830_SPI0_CLK, DA830_NSPI0_ENA, DA830_NSPI0_SCS_0, -1 }; -const short da830_spi1_pins[] __initdata = { +const short da830_spi1_pins[] __initconst = { DA830_SPI1_SOMI_0, DA830_SPI1_SIMO_0, DA830_SPI1_CLK, DA830_NSPI1_ENA, DA830_NSPI1_SCS_0, -1 }; -const short da830_mmc_sd_pins[] __initdata = { +const short da830_mmc_sd_pins[] __initconst = { DA830_MMCSD_DAT_0, DA830_MMCSD_DAT_1, DA830_MMCSD_DAT_2, DA830_MMCSD_DAT_3, DA830_MMCSD_DAT_4, DA830_MMCSD_DAT_5, DA830_MMCSD_DAT_6, DA830_MMCSD_DAT_7, DA830_MMCSD_CLK, @@ -873,32 +873,32 @@ const short da830_mmc_sd_pins[] __initdata = { -1 }; -const short da830_uart0_pins[] __initdata = { +const short da830_uart0_pins[] __initconst = { DA830_NUART0_CTS, DA830_NUART0_RTS, DA830_UART0_RXD, DA830_UART0_TXD, -1 }; -const short da830_uart1_pins[] __initdata = { +const short da830_uart1_pins[] __initconst = { DA830_UART1_RXD, DA830_UART1_TXD, -1 }; -const short da830_uart2_pins[] __initdata = { +const short da830_uart2_pins[] __initconst = { DA830_UART2_RXD, DA830_UART2_TXD, -1 }; -const short da830_usb20_pins[] __initdata = { +const short da830_usb20_pins[] __initconst = { DA830_USB0_DRVVBUS, DA830_USB_REFCLKIN, -1 }; -const short da830_usb11_pins[] __initdata = { +const short da830_usb11_pins[] __initconst = { DA830_USB_REFCLKIN, -1 }; -const short da830_uhpi_pins[] __initdata = { +const short da830_uhpi_pins[] __initconst = { DA830_UHPI_HD_0, DA830_UHPI_HD_1, DA830_UHPI_HD_2, DA830_UHPI_HD_3, DA830_UHPI_HD_4, DA830_UHPI_HD_5, DA830_UHPI_HD_6, DA830_UHPI_HD_7, DA830_UHPI_HD_8, DA830_UHPI_HD_9, DA830_UHPI_HD_10, DA830_UHPI_HD_11, @@ -909,14 +909,14 @@ const short da830_uhpi_pins[] __initdata = { -1 }; -const short da830_cpgmac_pins[] __initdata = { +const short da830_cpgmac_pins[] __initconst = { DA830_RMII_TXD_0, DA830_RMII_TXD_1, DA830_RMII_TXEN, DA830_RMII_CRS_DV, DA830_RMII_RXD_0, DA830_RMII_RXD_1, DA830_RMII_RXER, DA830_MDIO_CLK, DA830_MDIO_D, -1 }; -const short da830_emif3c_pins[] __initdata = { +const short da830_emif3c_pins[] __initconst = { DA830_EMB_SDCKE, DA830_EMB_CLK_GLUE, DA830_EMB_CLK, DA830_NEMB_CS_0, DA830_NEMB_CAS, DA830_NEMB_RAS, DA830_NEMB_WE, DA830_EMB_BA_1, DA830_EMB_BA_0, DA830_EMB_A_0, DA830_EMB_A_1, DA830_EMB_A_2, @@ -935,7 +935,7 @@ const short da830_emif3c_pins[] __initdata = { -1 }; -const short da830_mcasp0_pins[] __initdata = { +const short da830_mcasp0_pins[] __initconst = { DA830_AHCLKX0, DA830_ACLKX0, DA830_AFSX0, DA830_AHCLKR0, DA830_ACLKR0, DA830_AFSR0, DA830_AMUTE0, DA830_AXR0_0, DA830_AXR0_1, DA830_AXR0_2, DA830_AXR0_3, @@ -945,7 +945,7 @@ const short da830_mcasp0_pins[] __initdata = { -1 }; -const short da830_mcasp1_pins[] __initdata = { +const short da830_mcasp1_pins[] __initconst = { DA830_AHCLKX1, DA830_ACLKX1, DA830_AFSX1, DA830_AHCLKR1, DA830_ACLKR1, DA830_AFSR1, DA830_AMUTE1, DA830_AXR1_0, DA830_AXR1_1, DA830_AXR1_2, DA830_AXR1_3, @@ -954,24 +954,24 @@ const short da830_mcasp1_pins[] __initdata = { -1 }; -const short da830_mcasp2_pins[] __initdata = { +const short da830_mcasp2_pins[] __initconst = { DA830_AHCLKX2, DA830_ACLKX2, DA830_AFSX2, DA830_AHCLKR2, DA830_ACLKR2, DA830_AFSR2, DA830_AMUTE2, DA830_AXR2_0, DA830_AXR2_1, DA830_AXR2_2, DA830_AXR2_3, -1 }; -const short da830_i2c0_pins[] __initdata = { +const short da830_i2c0_pins[] __initconst = { DA830_I2C0_SDA, DA830_I2C0_SCL, -1 }; -const short da830_i2c1_pins[] __initdata = { +const short da830_i2c1_pins[] __initconst = { DA830_I2C1_SCL, DA830_I2C1_SDA, -1 }; -const short da830_lcdcntl_pins[] __initdata = { +const short da830_lcdcntl_pins[] __initconst = { DA830_LCD_D_0, DA830_LCD_D_1, DA830_LCD_D_2, DA830_LCD_D_3, DA830_LCD_D_4, DA830_LCD_D_5, DA830_LCD_D_6, DA830_LCD_D_7, DA830_LCD_D_8, DA830_LCD_D_9, DA830_LCD_D_10, DA830_LCD_D_11, @@ -981,34 +981,34 @@ const short da830_lcdcntl_pins[] __initdata = { -1 }; -const short da830_pwm_pins[] __initdata = { +const short da830_pwm_pins[] __initconst = { DA830_ECAP0_APWM0, DA830_ECAP1_APWM1, DA830_EPWM0B, DA830_EPWM0A, DA830_EPWMSYNCI, DA830_EPWMSYNC0, DA830_ECAP2_APWM2, DA830_EHRPWMGLUETZ, DA830_EPWM2B, DA830_EPWM2A, DA830_EPWM1B, DA830_EPWM1A, -1 }; -const short da830_ecap0_pins[] __initdata = { +const short da830_ecap0_pins[] __initconst = { DA830_ECAP0_APWM0, -1 }; -const short da830_ecap1_pins[] __initdata = { +const short da830_ecap1_pins[] __initconst = { DA830_ECAP1_APWM1, -1 }; -const short da830_ecap2_pins[] __initdata = { +const short da830_ecap2_pins[] __initconst = { DA830_ECAP2_APWM2, -1 }; -const short da830_eqep0_pins[] __initdata = { +const short da830_eqep0_pins[] __initconst = { DA830_EQEP0I, DA830_EQEP0S, DA830_EQEP0A, DA830_EQEP0B, -1 }; -const short da830_eqep1_pins[] __initdata = { +const short da830_eqep1_pins[] __initconst = { DA830_EQEP1I, DA830_EQEP1S, DA830_EQEP1A, DA830_EQEP1B, -1 }; diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index b44dc844e15e..b90c172d5541 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -347,6 +347,13 @@ static struct clk spi1_clk = { .flags = DA850_CLK_ASYNC3, }; +static struct clk vpif_clk = { + .name = "vpif", + .parent = &pll0_sysclk2, + .lpsc = DA850_LPSC1_VPIF, + .gpsc = 1, +}; + static struct clk sata_clk = { .name = "sata", .parent = &pll0_sysclk2, @@ -397,6 +404,7 @@ static struct clk_lookup da850_clks[] = { CLK(NULL, "usb20", &usb20_clk), CLK("spi_davinci.0", NULL, &spi0_clk), CLK("spi_davinci.1", NULL, &spi1_clk), + CLK("vpif", NULL, &vpif_clk), CLK("ahci", NULL, &sata_clk), CLK(NULL, NULL, NULL), }; @@ -573,20 +581,60 @@ static const struct mux_config da850_pins[] = { MUX_CFG(DA850, GPIO6_10, 13, 20, 15, 8, false) MUX_CFG(DA850, GPIO6_13, 13, 8, 15, 8, false) MUX_CFG(DA850, RTC_ALARM, 0, 28, 15, 2, false) + /* VPIF Capture */ + MUX_CFG(DA850, VPIF_DIN0, 15, 4, 15, 1, false) + MUX_CFG(DA850, VPIF_DIN1, 15, 0, 15, 1, false) + MUX_CFG(DA850, VPIF_DIN2, 14, 28, 15, 1, false) + MUX_CFG(DA850, VPIF_DIN3, 14, 24, 15, 1, false) + MUX_CFG(DA850, VPIF_DIN4, 14, 20, 15, 1, false) + MUX_CFG(DA850, VPIF_DIN5, 14, 16, 15, 1, false) + MUX_CFG(DA850, VPIF_DIN6, 14, 12, 15, 1, false) + MUX_CFG(DA850, VPIF_DIN7, 14, 8, 15, 1, false) + MUX_CFG(DA850, VPIF_DIN8, 16, 4, 15, 1, false) + MUX_CFG(DA850, VPIF_DIN9, 16, 0, 15, 1, false) + MUX_CFG(DA850, VPIF_DIN10, 15, 28, 15, 1, false) + MUX_CFG(DA850, VPIF_DIN11, 15, 24, 15, 1, false) + MUX_CFG(DA850, VPIF_DIN12, 15, 20, 15, 1, false) + MUX_CFG(DA850, VPIF_DIN13, 15, 16, 15, 1, false) + MUX_CFG(DA850, VPIF_DIN14, 15, 12, 15, 1, false) + MUX_CFG(DA850, VPIF_DIN15, 15, 8, 15, 1, false) + MUX_CFG(DA850, VPIF_CLKIN0, 14, 0, 15, 1, false) + MUX_CFG(DA850, VPIF_CLKIN1, 14, 4, 15, 1, false) + MUX_CFG(DA850, VPIF_CLKIN2, 19, 8, 15, 1, false) + MUX_CFG(DA850, VPIF_CLKIN3, 19, 16, 15, 1, false) + /* VPIF Display */ + MUX_CFG(DA850, VPIF_DOUT0, 17, 4, 15, 1, false) + MUX_CFG(DA850, VPIF_DOUT1, 17, 0, 15, 1, false) + MUX_CFG(DA850, VPIF_DOUT2, 16, 28, 15, 1, false) + MUX_CFG(DA850, VPIF_DOUT3, 16, 24, 15, 1, false) + MUX_CFG(DA850, VPIF_DOUT4, 16, 20, 15, 1, false) + MUX_CFG(DA850, VPIF_DOUT5, 16, 16, 15, 1, false) + MUX_CFG(DA850, VPIF_DOUT6, 16, 12, 15, 1, false) + MUX_CFG(DA850, VPIF_DOUT7, 16, 8, 15, 1, false) + MUX_CFG(DA850, VPIF_DOUT8, 18, 4, 15, 1, false) + MUX_CFG(DA850, VPIF_DOUT9, 18, 0, 15, 1, false) + MUX_CFG(DA850, VPIF_DOUT10, 17, 28, 15, 1, false) + MUX_CFG(DA850, VPIF_DOUT11, 17, 24, 15, 1, false) + MUX_CFG(DA850, VPIF_DOUT12, 17, 20, 15, 1, false) + MUX_CFG(DA850, VPIF_DOUT13, 17, 16, 15, 1, false) + MUX_CFG(DA850, VPIF_DOUT14, 17, 12, 15, 1, false) + MUX_CFG(DA850, VPIF_DOUT15, 17, 8, 15, 1, false) + MUX_CFG(DA850, VPIF_CLKO2, 19, 12, 15, 1, false) + MUX_CFG(DA850, VPIF_CLKO3, 19, 20, 15, 1, false) #endif }; -const short da850_i2c0_pins[] __initdata = { +const short da850_i2c0_pins[] __initconst = { DA850_I2C0_SDA, DA850_I2C0_SCL, -1 }; -const short da850_i2c1_pins[] __initdata = { +const short da850_i2c1_pins[] __initconst = { DA850_I2C1_SCL, DA850_I2C1_SDA, -1 }; -const short da850_lcdcntl_pins[] __initdata = { +const short da850_lcdcntl_pins[] __initconst = { DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3, DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7, DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11, @@ -595,6 +643,26 @@ const short da850_lcdcntl_pins[] __initdata = { -1 }; +const short da850_vpif_capture_pins[] __initdata = { + DA850_VPIF_DIN0, DA850_VPIF_DIN1, DA850_VPIF_DIN2, DA850_VPIF_DIN3, + DA850_VPIF_DIN4, DA850_VPIF_DIN5, DA850_VPIF_DIN6, DA850_VPIF_DIN7, + DA850_VPIF_DIN8, DA850_VPIF_DIN9, DA850_VPIF_DIN10, DA850_VPIF_DIN11, + DA850_VPIF_DIN12, DA850_VPIF_DIN13, DA850_VPIF_DIN14, DA850_VPIF_DIN15, + DA850_VPIF_CLKIN0, DA850_VPIF_CLKIN1, DA850_VPIF_CLKIN2, + DA850_VPIF_CLKIN3, + -1 +}; + +const short da850_vpif_display_pins[] __initdata = { + DA850_VPIF_DOUT0, DA850_VPIF_DOUT1, DA850_VPIF_DOUT2, DA850_VPIF_DOUT3, + DA850_VPIF_DOUT4, DA850_VPIF_DOUT5, DA850_VPIF_DOUT6, DA850_VPIF_DOUT7, + DA850_VPIF_DOUT8, DA850_VPIF_DOUT9, DA850_VPIF_DOUT10, + DA850_VPIF_DOUT11, DA850_VPIF_DOUT12, DA850_VPIF_DOUT13, + DA850_VPIF_DOUT14, DA850_VPIF_DOUT15, DA850_VPIF_CLKO2, + DA850_VPIF_CLKO3, + -1 +}; + /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = { [IRQ_DA8XX_COMMTX] = 7, @@ -939,7 +1007,7 @@ static struct platform_device da850_cpufreq_device = { unsigned int da850_max_speed = 300000; -int __init da850_register_cpufreq(char *async_clk) +int da850_register_cpufreq(char *async_clk) { int i; @@ -1064,6 +1132,90 @@ no_ddrpll_mem: return ret; } +/* VPIF resource, platform data */ +static u64 da850_vpif_dma_mask = DMA_BIT_MASK(32); + +static struct resource da850_vpif_resource[] = { + { + .start = DA8XX_VPIF_BASE, + .end = DA8XX_VPIF_BASE + 0xfff, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device da850_vpif_dev = { + .name = "vpif", + .id = -1, + .dev = { + .dma_mask = &da850_vpif_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = da850_vpif_resource, + .num_resources = ARRAY_SIZE(da850_vpif_resource), +}; + +static struct resource da850_vpif_display_resource[] = { + { + .start = IRQ_DA850_VPIFINT, + .end = IRQ_DA850_VPIFINT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device da850_vpif_display_dev = { + .name = "vpif_display", + .id = -1, + .dev = { + .dma_mask = &da850_vpif_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = da850_vpif_display_resource, + .num_resources = ARRAY_SIZE(da850_vpif_display_resource), +}; + +static struct resource da850_vpif_capture_resource[] = { + { + .start = IRQ_DA850_VPIFINT, + .end = IRQ_DA850_VPIFINT, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_DA850_VPIFINT, + .end = IRQ_DA850_VPIFINT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device da850_vpif_capture_dev = { + .name = "vpif_capture", + .id = -1, + .dev = { + .dma_mask = &da850_vpif_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = da850_vpif_capture_resource, + .num_resources = ARRAY_SIZE(da850_vpif_capture_resource), +}; + +int __init da850_register_vpif(void) +{ + return platform_device_register(&da850_vpif_dev); +} + +int __init da850_register_vpif_display(struct vpif_display_config + *display_config) +{ + da850_vpif_display_dev.dev.platform_data = display_config; + return platform_device_register(&da850_vpif_display_dev); +} + +int __init da850_register_vpif_capture(struct vpif_capture_config + *capture_config) +{ + da850_vpif_capture_dev.dev.platform_data = capture_config; + return platform_device_register(&da850_vpif_capture_dev); +} + static struct davinci_soc_info davinci_soc_info_da850 = { .io_desc = da850_io_desc, .io_desc_num = ARRAY_SIZE(da850_io_desc), diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h index a37fc44e29bc..12d544befcfa 100644 --- a/arch/arm/mach-davinci/davinci.h +++ b/arch/arm/mach-davinci/davinci.h @@ -22,10 +22,10 @@ #include <linux/davinci_emac.h> #include <linux/platform_device.h> #include <linux/spi/spi.h> - -#include <mach/asp.h> +#include <linux/platform_data/davinci_asp.h> #include <linux/platform_data/keyscan-davinci.h> #include <mach/hardware.h> +#include <mach/edma.h> #include <media/davinci/vpfe_capture.h> #include <media/davinci/vpif_types.h> diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c index 783eab6845c4..bd2f72b414bc 100644 --- a/arch/arm/mach-davinci/devices-da8xx.c +++ b/arch/arm/mach-davinci/devices-da8xx.c @@ -24,6 +24,7 @@ #include <mach/cpuidle.h> #include "clock.h" +#include "asp.h" #define DA8XX_TPCC_BASE 0x01c00000 #define DA8XX_TPTC0_BASE 0x01c08000 @@ -505,15 +506,8 @@ static struct platform_device da850_mcasp_device = { .resource = da850_mcasp_resources, }; -static struct platform_device davinci_pcm_device = { - .name = "davinci-pcm-audio", - .id = -1, -}; - void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata) { - platform_device_register(&davinci_pcm_device); - /* DA830/OMAP-L137 has 3 instances of McASP */ if (cpu_is_davinci_da830() && id == 1) { da830_mcasp1_device.dev.platform_data = pdata; diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c index 3a42b6f79aa9..4c48a36ee567 100644 --- a/arch/arm/mach-davinci/devices.c +++ b/arch/arm/mach-davinci/devices.c @@ -313,16 +313,6 @@ static void davinci_init_wdt(void) /*-------------------------------------------------------------------------*/ -static struct platform_device davinci_pcm_device = { - .name = "davinci-pcm-audio", - .id = -1, -}; - -static void davinci_init_pcm(void) -{ - platform_device_register(&davinci_pcm_device); -} - /*-------------------------------------------------------------------------*/ struct davinci_timer_instance davinci_timer_instance[2] = { @@ -345,7 +335,6 @@ static int __init davinci_init_devices(void) /* please keep these calls, and their implementations above, * in alphabetical order so they're easier to sort through. */ - davinci_init_pcm(); davinci_init_wdt(); return 0; diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index adbde33eca01..a255434908db 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -26,13 +26,13 @@ #include <mach/time.h> #include <mach/serial.h> #include <mach/common.h> -#include <mach/asp.h> #include <linux/platform_data/spi-davinci.h> #include <mach/gpio-davinci.h> #include "davinci.h" #include "clock.h" #include "mux.h" +#include "asp.h" #define DM355_UART2_BASE (IO_PHYS + 0x206000) diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index 719e22f2a37e..b680c832e0ba 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -29,7 +29,6 @@ #include <mach/time.h> #include <mach/serial.h> #include <mach/common.h> -#include <mach/asp.h> #include <linux/platform_data/keyscan-davinci.h> #include <linux/platform_data/spi-davinci.h> #include <mach/gpio-davinci.h> @@ -37,6 +36,7 @@ #include "davinci.h" #include "clock.h" #include "mux.h" +#include "asp.h" #define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */ diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index c8b866657fcb..cd0c8b1e1ecf 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -23,12 +23,12 @@ #include <mach/time.h> #include <mach/serial.h> #include <mach/common.h> -#include <mach/asp.h> #include <mach/gpio-davinci.h> #include "davinci.h" #include "clock.h" #include "mux.h" +#include "asp.h" /* * Device specific clocks @@ -701,7 +701,7 @@ static struct resource dm644x_venc_resources[] = { #define DM644X_VPSS_DACCLKEN BIT(4) static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type, - unsigned int mode) + unsigned int pclock) { int ret = 0; u32 v = DM644X_VPSS_VENCLKEN; @@ -711,27 +711,18 @@ static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type, v |= DM644X_VPSS_DACCLKEN; writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL)); break; - case VPBE_ENC_DV_PRESET: - switch (mode) { - case V4L2_DV_480P59_94: - case V4L2_DV_576P50: + case VPBE_ENC_CUSTOM_TIMINGS: + if (pclock <= 27000000) { v |= DM644X_VPSS_MUXSEL_PLL2_MODE | DM644X_VPSS_DACCLKEN; writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL)); - break; - case V4L2_DV_720P60: - case V4L2_DV_1080I60: - case V4L2_DV_1080P30: + } else { /* * For HD, use external clock source since * HD requires higher clock rate */ v |= DM644X_VPSS_MUXSEL_VPBECLK_MODE; writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL)); - break; - default: - ret = -EINVAL; - break; } break; default: diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index 9eb87c1d1edd..97c0f8e555bd 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c @@ -24,12 +24,12 @@ #include <mach/time.h> #include <mach/serial.h> #include <mach/common.h> -#include <mach/asp.h> #include <mach/gpio-davinci.h> #include "davinci.h" #include "clock.h" #include "mux.h" +#include "asp.h" #define DAVINCI_VPIF_BASE (0x01C12000) diff --git a/arch/arm/mach-davinci/include/mach/asp.h b/arch/arm/mach-davinci/include/mach/asp.h deleted file mode 100644 index 9aa240909a2c..000000000000 --- a/arch/arm/mach-davinci/include/mach/asp.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - * <mach/asp.h> - DaVinci Audio Serial Port support - */ -#ifndef __ASM_ARCH_DAVINCI_ASP_H -#define __ASM_ARCH_DAVINCI_ASP_H - -#include <mach/irqs.h> -#include <mach/edma.h> - -/* Bases of dm644x and dm355 register banks */ -#define DAVINCI_ASP0_BASE 0x01E02000 -#define DAVINCI_ASP1_BASE 0x01E04000 - -/* Bases of dm365 register banks */ -#define DAVINCI_DM365_ASP0_BASE 0x01D02000 - -/* Bases of dm646x register banks */ -#define DAVINCI_DM646X_MCASP0_REG_BASE 0x01D01000 -#define DAVINCI_DM646X_MCASP1_REG_BASE 0x01D01800 - -/* Bases of da850/da830 McASP0 register banks */ -#define DAVINCI_DA8XX_MCASP0_REG_BASE 0x01D00000 - -/* Bases of da830 McASP1 register banks */ -#define DAVINCI_DA830_MCASP1_REG_BASE 0x01D04000 - -/* EDMA channels of dm644x and dm355 */ -#define DAVINCI_DMA_ASP0_TX 2 -#define DAVINCI_DMA_ASP0_RX 3 -#define DAVINCI_DMA_ASP1_TX 8 -#define DAVINCI_DMA_ASP1_RX 9 - -/* EDMA channels of dm646x */ -#define DAVINCI_DM646X_DMA_MCASP0_AXEVT0 6 -#define DAVINCI_DM646X_DMA_MCASP0_AREVT0 9 -#define DAVINCI_DM646X_DMA_MCASP1_AXEVT1 12 - -/* EDMA channels of da850/da830 McASP0 */ -#define DAVINCI_DA8XX_DMA_MCASP0_AREVT 0 -#define DAVINCI_DA8XX_DMA_MCASP0_AXEVT 1 - -/* EDMA channels of da830 McASP1 */ -#define DAVINCI_DA830_DMA_MCASP1_AREVT 2 -#define DAVINCI_DA830_DMA_MCASP1_AXEVT 3 - -/* Interrupts */ -#define DAVINCI_ASP0_RX_INT IRQ_MBRINT -#define DAVINCI_ASP0_TX_INT IRQ_MBXINT -#define DAVINCI_ASP1_RX_INT IRQ_MBRINT -#define DAVINCI_ASP1_TX_INT IRQ_MBXINT - -struct snd_platform_data { - u32 tx_dma_offset; - u32 rx_dma_offset; - enum dma_event_q asp_chan_q; /* event queue number for ASP channel */ - enum dma_event_q ram_chan_q; /* event queue number for RAM channel */ - unsigned int codec_fmt; - /* - * Allowing this is more efficient and eliminates left and right swaps - * caused by underruns, but will swap the left and right channels - * when compared to previous behavior. - */ - unsigned enable_channel_combine:1; - unsigned sram_size_playback; - unsigned sram_size_capture; - - /* - * If McBSP peripheral gets the clock from an external pin, - * there are three chooses, that are MCBSP_CLKX, MCBSP_CLKR - * and MCBSP_CLKS. - * Depending on different hardware connections it is possible - * to use this setting to change the behaviour of McBSP - * driver. The dm365_clk_input_pin enum is available for dm365 - */ - int clk_input_pin; - - /* - * This flag works when both clock and FS are outputs for the cpu - * and makes clock more accurate (FS is not symmetrical and the - * clock is very fast. - * The clock becoming faster is named - * i2s continuous serial clock (I2S_SCK) and it is an externally - * visible bit clock. - * - * first line : WordSelect - * second line : ContinuousSerialClock - * third line: SerialData - * - * SYMMETRICAL APPROACH: - * _______________________ LEFT - * _| RIGHT |______________________| - * _ _ _ _ _ _ _ _ - * _| |_| |_ x16 _| |_| |_| |_| |_ x16 _| |_| |_ - * _ _ _ _ _ _ _ _ - * _/ \_/ \_ ... _/ \_/ \_/ \_/ \_ ... _/ \_/ \_ - * \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ - * - * ACCURATE CLOCK APPROACH: - * ______________ LEFT - * _| RIGHT |_______________________________| - * _ _ _ _ _ _ _ _ _ - * _| |_ x16 _| |_| |_ x16 _| |_| |_| |_| |_| |_| | - * _ _ _ _ dummy cycles - * _/ \_ ... _/ \_/ \_ ... _/ \__________________ - * \_/ \_/ \_/ \_/ - * - */ - bool i2s_accurate_sck; - - /* McASP specific fields */ - int tdm_slots; - u8 op_mode; - u8 num_serializer; - u8 *serial_dir; - u8 version; - u8 txnumevt; - u8 rxnumevt; -}; - -enum { - MCASP_VERSION_1 = 0, /* DM646x */ - MCASP_VERSION_2, /* DA8xx/OMAPL1x */ -}; - -enum dm365_clk_input_pin { - MCBSP_CLKR = 0, /* DM365 */ - MCBSP_CLKS, -}; - -#define INACTIVE_MODE 0 -#define TX_MODE 1 -#define RX_MODE 2 - -#define DAVINCI_MCASP_IIS_MODE 0 -#define DAVINCI_MCASP_DIT_MODE 1 - -#endif /* __ASM_ARCH_DAVINCI_ASP_H */ diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index 33e78ae2a254..aaccdc4528fc 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -16,16 +16,19 @@ #include <linux/platform_device.h> #include <linux/davinci_emac.h> #include <linux/spi/spi.h> +#include <linux/platform_data/davinci_asp.h> +#include <linux/videodev2.h> #include <mach/serial.h> #include <mach/edma.h> -#include <mach/asp.h> #include <mach/pm.h> #include <linux/platform_data/i2c-davinci.h> #include <linux/platform_data/mmc-davinci.h> #include <linux/platform_data/usb-davinci.h> #include <linux/platform_data/spi-davinci.h> +#include <media/davinci/vpif_types.h> + extern void __iomem *da8xx_syscfg0_base; extern void __iomem *da8xx_syscfg1_base; @@ -63,6 +66,7 @@ extern unsigned int da850_max_speed; #define DA8XX_PLL0_BASE 0x01c11000 #define DA8XX_TIMER64P0_BASE 0x01c20000 #define DA8XX_TIMER64P1_BASE 0x01c21000 +#define DA8XX_VPIF_BASE 0x01e17000 #define DA8XX_GPIO_BASE 0x01e26000 #define DA8XX_PSC1_BASE 0x01e27000 #define DA8XX_AEMIF_CS2_BASE 0x60000000 @@ -92,6 +96,11 @@ int da8xx_register_cpuidle(void); void __iomem * __init da8xx_get_mem_ctlr(void); int da850_register_pm(struct platform_device *pdev); int __init da850_register_sata(unsigned long refclkpn); +int __init da850_register_vpif(void); +int __init da850_register_vpif_display + (struct vpif_display_config *display_config); +int __init da850_register_vpif_capture + (struct vpif_capture_config *capture_config); void da8xx_restart(char mode, const char *cmd); extern struct platform_device da8xx_serial_device; @@ -126,6 +135,8 @@ extern const short da830_ecap1_pins[]; extern const short da830_ecap2_pins[]; extern const short da830_eqep0_pins[]; extern const short da830_eqep1_pins[]; +extern const short da850_vpif_capture_pins[]; +extern const short da850_vpif_display_pins[]; extern const short da850_i2c0_pins[]; extern const short da850_i2c1_pins[]; diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h index a7e92fca32e6..9e95b8a1edb6 100644 --- a/arch/arm/mach-davinci/include/mach/mux.h +++ b/arch/arm/mach-davinci/include/mach/mux.h @@ -928,6 +928,48 @@ enum davinci_da850_index { DA850_GPIO6_10, DA850_GPIO6_13, DA850_RTC_ALARM, + + /* VPIF Capture */ + DA850_VPIF_DIN0, + DA850_VPIF_DIN1, + DA850_VPIF_DIN2, + DA850_VPIF_DIN3, + DA850_VPIF_DIN4, + DA850_VPIF_DIN5, + DA850_VPIF_DIN6, + DA850_VPIF_DIN7, + DA850_VPIF_DIN8, + DA850_VPIF_DIN9, + DA850_VPIF_DIN10, + DA850_VPIF_DIN11, + DA850_VPIF_DIN12, + DA850_VPIF_DIN13, + DA850_VPIF_DIN14, + DA850_VPIF_DIN15, + DA850_VPIF_CLKIN0, + DA850_VPIF_CLKIN1, + DA850_VPIF_CLKIN2, + DA850_VPIF_CLKIN3, + + /* VPIF Display */ + DA850_VPIF_DOUT0, + DA850_VPIF_DOUT1, + DA850_VPIF_DOUT2, + DA850_VPIF_DOUT3, + DA850_VPIF_DOUT4, + DA850_VPIF_DOUT5, + DA850_VPIF_DOUT6, + DA850_VPIF_DOUT7, + DA850_VPIF_DOUT8, + DA850_VPIF_DOUT9, + DA850_VPIF_DOUT10, + DA850_VPIF_DOUT11, + DA850_VPIF_DOUT12, + DA850_VPIF_DOUT13, + DA850_VPIF_DOUT14, + DA850_VPIF_DOUT15, + DA850_VPIF_CLKO2, + DA850_VPIF_CLKO3, }; enum davinci_tnetv107x_index { diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h index 405318e35bf6..40a0027838e8 100644 --- a/arch/arm/mach-davinci/include/mach/psc.h +++ b/arch/arm/mach-davinci/include/mach/psc.h @@ -166,6 +166,7 @@ #define DA830_LPSC1_McASP1 8 #define DA850_LPSC1_SATA 8 #define DA830_LPSC1_McASP2 9 +#define DA850_LPSC1_VPIF 9 #define DA8XX_LPSC1_SPI1 10 #define DA8XX_LPSC1_I2C 11 #define DA8XX_LPSC1_UART1 12 diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig index dd937c526a45..00154e74ce6b 100644 --- a/arch/arm/mach-dove/Kconfig +++ b/arch/arm/mach-dove/Kconfig @@ -15,6 +15,13 @@ config MACH_CM_A510 Say 'Y' here if you want your kernel to support the CompuLab CM-A510 Board. +config MACH_DOVE_DT + bool "Marvell Dove Flattened Device Tree" + select USE_OF + help + Say 'Y' here if you want your kernel to support the + Marvell Dove using flattened device tree. + endmenu endif diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile index fa0f01856060..5e683baf96cf 100644 --- a/arch/arm/mach-dove/Makefile +++ b/arch/arm/mach-dove/Makefile @@ -1,4 +1,4 @@ -obj-y += common.o addr-map.o irq.o pcie.o mpp.o - +obj-y += common.o addr-map.o irq.o mpp.o +obj-$(CONFIG_PCI) += pcie.o obj-$(CONFIG_MACH_DOVE_DB) += dove-db-setup.o obj-$(CONFIG_MACH_CM_A510) += cm-a510.o diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index 950ad9533d19..f723fe13d0f0 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -16,6 +16,8 @@ #include <linux/clk-provider.h> #include <linux/ata_platform.h> #include <linux/gpio.h> +#include <linux/of.h> +#include <linux/of_platform.h> #include <asm/page.h> #include <asm/setup.h> #include <asm/timex.h> @@ -24,28 +26,28 @@ #include <asm/mach/time.h> #include <asm/mach/pci.h> #include <mach/dove.h> +#include <mach/pm.h> #include <mach/bridge-regs.h> #include <asm/mach/arch.h> #include <linux/irq.h> #include <plat/time.h> #include <linux/platform_data/usb-ehci-orion.h> +#include <plat/irq.h> #include <plat/common.h> #include <plat/addr-map.h> #include "common.h" -static int get_tclk(void); - /***************************************************************************** * I/O Address Mapping ****************************************************************************/ static struct map_desc dove_io_desc[] __initdata = { { - .virtual = DOVE_SB_REGS_VIRT_BASE, + .virtual = (unsigned long) DOVE_SB_REGS_VIRT_BASE, .pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE), .length = DOVE_SB_REGS_SIZE, .type = MT_DEVICE, }, { - .virtual = DOVE_NB_REGS_VIRT_BASE, + .virtual = (unsigned long) DOVE_NB_REGS_VIRT_BASE, .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE), .length = DOVE_NB_REGS_SIZE, .type = MT_DEVICE, @@ -60,14 +62,69 @@ void __init dove_map_io(void) /***************************************************************************** * CLK tree ****************************************************************************/ +static int dove_tclk; + +static DEFINE_SPINLOCK(gating_lock); static struct clk *tclk; -static void __init clk_init(void) +static struct clk __init *dove_register_gate(const char *name, + const char *parent, u8 bit_idx) { - tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT, - get_tclk()); + return clk_register_gate(NULL, name, parent, 0, + (void __iomem *)CLOCK_GATING_CONTROL, + bit_idx, 0, &gating_lock); +} + +static void __init dove_clk_init(void) +{ + struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1; + struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma; + struct clk *xor0, *xor1, *ge, *gephy; - orion_clkdev_init(tclk); + tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT, + dove_tclk); + + usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0); + usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1); + sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA); + pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0); + pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1); + sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0); + sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1); + nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND); + camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA); + i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0); + i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1); + crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO); + ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97); + pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA); + xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0); + xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1); + gephy = dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY); + ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE); + + orion_clkdev_add(NULL, "orion_spi.0", tclk); + orion_clkdev_add(NULL, "orion_spi.1", tclk); + orion_clkdev_add(NULL, "orion_wdt", tclk); + orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk); + + orion_clkdev_add(NULL, "orion-ehci.0", usb0); + orion_clkdev_add(NULL, "orion-ehci.1", usb1); + orion_clkdev_add(NULL, "mv643xx_eth_port.0", ge); + orion_clkdev_add(NULL, "sata_mv.0", sata); + orion_clkdev_add("0", "pcie", pex0); + orion_clkdev_add("1", "pcie", pex1); + orion_clkdev_add(NULL, "sdhci-dove.0", sdio0); + orion_clkdev_add(NULL, "sdhci-dove.1", sdio1); + orion_clkdev_add(NULL, "orion_nand", nand); + orion_clkdev_add(NULL, "cafe1000-ccic.0", camera); + orion_clkdev_add(NULL, "kirkwood-i2s.0", i2s0); + orion_clkdev_add(NULL, "kirkwood-i2s.1", i2s1); + orion_clkdev_add(NULL, "mv_crypto", crypto); + orion_clkdev_add(NULL, "dove-ac97", ac97); + orion_clkdev_add(NULL, "dove-pdma", pdma); + orion_clkdev_add(NULL, "mv_xor_shared.0", xor0); + orion_clkdev_add(NULL, "mv_xor_shared.1", xor1); } /***************************************************************************** @@ -178,16 +235,16 @@ void __init dove_init_early(void) orion_time_set_base(TIMER_VIRT_BASE); } -static int get_tclk(void) +static int __init dove_find_tclk(void) { - /* use DOVE_RESET_SAMPLE_HI/LO to detect tclk */ return 166666667; } static void __init dove_timer_init(void) { + dove_tclk = dove_find_tclk(); orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, - IRQ_DOVE_BRIDGE, get_tclk()); + IRQ_DOVE_BRIDGE, dove_tclk); } struct sys_timer dove_timer = { @@ -195,6 +252,15 @@ struct sys_timer dove_timer = { }; /***************************************************************************** + * Cryptographic Engines and Security Accelerator (CESA) + ****************************************************************************/ +void __init dove_crypto_init(void) +{ + orion_crypto_init(DOVE_CRYPT_PHYS_BASE, DOVE_CESA_PHYS_BASE, + DOVE_CESA_SIZE, IRQ_DOVE_CRYPTO); +} + +/***************************************************************************** * XOR 0 ****************************************************************************/ void __init dove_xor0_init(void) @@ -275,8 +341,8 @@ void __init dove_sdio1_init(void) void __init dove_init(void) { - printk(KERN_INFO "Dove 88AP510 SoC, "); - printk(KERN_INFO "TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000); + pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n", + (dove_tclk + 499999) / 1000000); #ifdef CONFIG_CACHE_TAUROS2 tauros2_init(0); @@ -284,7 +350,7 @@ void __init dove_init(void) dove_setup_cpu_mbus(); /* Setup root of clk tree */ - clk_init(); + dove_clk_init(); /* internal devices that every board has */ dove_rtc_init(); @@ -307,3 +373,66 @@ void dove_restart(char mode, const char *cmd) while (1) ; } + +#if defined(CONFIG_MACH_DOVE_DT) +/* + * Auxdata required until real OF clock provider + */ +struct of_dev_auxdata dove_auxdata_lookup[] __initdata = { + OF_DEV_AUXDATA("marvell,orion-spi", 0xf1010600, "orion_spi.0", NULL), + OF_DEV_AUXDATA("marvell,orion-spi", 0xf1014600, "orion_spi.1", NULL), + OF_DEV_AUXDATA("marvell,orion-wdt", 0xf1020300, "orion_wdt", NULL), + OF_DEV_AUXDATA("marvell,mv64xxx-i2c", 0xf1011000, "mv64xxx_i2c.0", + NULL), + OF_DEV_AUXDATA("marvell,orion-sata", 0xf10a0000, "sata_mv.0", NULL), + OF_DEV_AUXDATA("marvell,dove-sdhci", 0xf1092000, "sdhci-dove.0", NULL), + OF_DEV_AUXDATA("marvell,dove-sdhci", 0xf1090000, "sdhci-dove.1", NULL), + {}, +}; + +static struct mv643xx_eth_platform_data dove_dt_ge00_data = { + .phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT, +}; + +static void __init dove_dt_init(void) +{ + pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n", + (dove_tclk + 499999) / 1000000); + +#ifdef CONFIG_CACHE_TAUROS2 + tauros2_init(0); +#endif + dove_setup_cpu_mbus(); + + /* Setup root of clk tree */ + dove_clk_init(); + + /* Internal devices not ported to DT yet */ + dove_rtc_init(); + dove_xor0_init(); + dove_xor1_init(); + + dove_ge00_init(&dove_dt_ge00_data); + dove_ehci0_init(); + dove_ehci1_init(); + dove_pcie_init(1, 1); + + of_platform_populate(NULL, of_default_bus_match_table, + dove_auxdata_lookup, NULL); +} + +static const char * const dove_dt_board_compat[] = { + "marvell,dove", + NULL +}; + +DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)") + .map_io = dove_map_io, + .init_early = dove_init_early, + .init_irq = orion_dt_init_irq, + .timer = &dove_timer, + .init_machine = dove_dt_init, + .restart = dove_restart, + .dt_compat = dove_dt_board_compat, +MACHINE_END +#endif diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h index 6432a3ba864b..1a233404b735 100644 --- a/arch/arm/mach-dove/common.h +++ b/arch/arm/mach-dove/common.h @@ -26,7 +26,11 @@ void dove_init_irq(void); void dove_setup_cpu_mbus(void); void dove_ge00_init(struct mv643xx_eth_platform_data *eth_data); void dove_sata_init(struct mv_sata_platform_data *sata_data); +#ifdef CONFIG_PCI void dove_pcie_init(int init_port0, int init_port1); +#else +static inline void dove_pcie_init(int init_port0, int init_port1) { } +#endif void dove_ehci0_init(void); void dove_ehci1_init(void); void dove_uart0_init(void); diff --git a/arch/arm/mach-dove/include/mach/bridge-regs.h b/arch/arm/mach-dove/include/mach/bridge-regs.h index f953bb54aa9d..99f259e8cf33 100644 --- a/arch/arm/mach-dove/include/mach/bridge-regs.h +++ b/arch/arm/mach-dove/include/mach/bridge-regs.h @@ -13,22 +13,22 @@ #include <mach/dove.h> -#define CPU_CONFIG (BRIDGE_VIRT_BASE | 0x0000) +#define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0000) -#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104) +#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104) #define CPU_CTRL_PCIE0_LINK 0x00000001 #define CPU_RESET 0x00000002 #define CPU_CTRL_PCIE1_LINK 0x00000008 -#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) +#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108) #define SOFT_RESET_OUT_EN 0x00000004 -#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) +#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c) #define SOFT_RESET 0x00000001 #define BRIDGE_INT_TIMER1_CLR (~0x0004) -#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) +#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200) #define IRQ_CAUSE_LOW_OFF 0x0000 #define IRQ_MASK_LOW_OFF 0x0004 #define FIQ_MASK_LOW_OFF 0x0008 @@ -47,9 +47,9 @@ #define ENDPOINT_MASK_HIGH (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF) #define PCIE_INTERRUPT_MASK (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF) -#define POWER_MANAGEMENT (BRIDGE_VIRT_BASE | 0x011c) +#define POWER_MANAGEMENT (BRIDGE_VIRT_BASE + 0x011c) -#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) -#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE | 0x0300) +#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300) +#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300) #endif diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h index c91e3004a47b..661725e3115a 100644 --- a/arch/arm/mach-dove/include/mach/dove.h +++ b/arch/arm/mach-dove/include/mach/dove.h @@ -25,7 +25,7 @@ */ #define DOVE_CESA_PHYS_BASE 0xc8000000 -#define DOVE_CESA_VIRT_BASE 0xfdb00000 +#define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000) #define DOVE_CESA_SIZE SZ_1M #define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000 @@ -38,15 +38,15 @@ #define DOVE_BOOTROM_SIZE SZ_128M #define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000 -#define DOVE_SCRATCHPAD_VIRT_BASE 0xfdd00000 +#define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000) #define DOVE_SCRATCHPAD_SIZE SZ_1M #define DOVE_SB_REGS_PHYS_BASE 0xf1000000 -#define DOVE_SB_REGS_VIRT_BASE 0xfde00000 +#define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfde00000) #define DOVE_SB_REGS_SIZE SZ_8M #define DOVE_NB_REGS_PHYS_BASE 0xf1800000 -#define DOVE_NB_REGS_VIRT_BASE 0xfe600000 +#define DOVE_NB_REGS_VIRT_BASE IOMEM(0xfe600000) #define DOVE_NB_REGS_SIZE SZ_8M #define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000 @@ -62,75 +62,75 @@ */ /* SPI, I2C, UART */ -#define DOVE_I2C_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x11000) -#define DOVE_UART0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12000) -#define DOVE_UART0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12000) -#define DOVE_UART1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12100) -#define DOVE_UART1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12100) -#define DOVE_UART2_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12200) -#define DOVE_UART2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12200) -#define DOVE_UART3_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12300) -#define DOVE_UART3_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12300) -#define DOVE_SPI0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x10600) -#define DOVE_SPI1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x14600) +#define DOVE_I2C_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x11000) +#define DOVE_UART0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12000) +#define DOVE_UART0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12000) +#define DOVE_UART1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12100) +#define DOVE_UART1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12100) +#define DOVE_UART2_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12200) +#define DOVE_UART2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12200) +#define DOVE_UART3_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12300) +#define DOVE_UART3_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12300) +#define DOVE_SPI0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x10600) +#define DOVE_SPI1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x14600) /* North-South Bridge */ -#define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x20000) -#define BRIDGE_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x20000) +#define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x20000) +#define BRIDGE_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x20000) /* Cryptographic Engine */ -#define DOVE_CRYPT_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x30000) +#define DOVE_CRYPT_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x30000) /* PCIe 0 */ -#define DOVE_PCIE0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x40000) +#define DOVE_PCIE0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x40000) /* USB */ -#define DOVE_USB0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x50000) -#define DOVE_USB1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x51000) +#define DOVE_USB0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x50000) +#define DOVE_USB1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x51000) /* XOR 0 Engine */ -#define DOVE_XOR0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60800) -#define DOVE_XOR0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60800) -#define DOVE_XOR0_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60A00) -#define DOVE_XOR0_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60A00) +#define DOVE_XOR0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60800) +#define DOVE_XOR0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60800) +#define DOVE_XOR0_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60A00) +#define DOVE_XOR0_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60A00) /* XOR 1 Engine */ -#define DOVE_XOR1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60900) -#define DOVE_XOR1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60900) -#define DOVE_XOR1_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60B00) -#define DOVE_XOR1_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60B00) +#define DOVE_XOR1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60900) +#define DOVE_XOR1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60900) +#define DOVE_XOR1_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60B00) +#define DOVE_XOR1_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60B00) /* Gigabit Ethernet */ -#define DOVE_GE00_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x70000) +#define DOVE_GE00_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x70000) /* PCIe 1 */ -#define DOVE_PCIE1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x80000) +#define DOVE_PCIE1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x80000) /* CAFE */ -#define DOVE_SDIO0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x92000) -#define DOVE_SDIO1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x90000) -#define DOVE_CAM_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x94000) -#define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x98000) +#define DOVE_SDIO0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x92000) +#define DOVE_SDIO1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x90000) +#define DOVE_CAM_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x94000) +#define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x98000) /* SATA */ -#define DOVE_SATA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xa0000) +#define DOVE_SATA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xa0000) /* I2S/SPDIF */ -#define DOVE_AUD0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xb0000) -#define DOVE_AUD1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xb4000) +#define DOVE_AUD0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xb0000) +#define DOVE_AUD1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xb4000) /* NAND Flash Controller */ -#define DOVE_NFC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xc0000) +#define DOVE_NFC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xc0000) /* MPP, GPIO, Reset Sampling */ -#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0200) +#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0200) #define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10) -#define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE | 0x014) -#define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE | 0x018) -#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0400) -#define DOVE_GPIO_HI_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0420) -#define DOVE_GPIO2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe8400) -#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c) +#define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE + 0x014) +#define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE + 0x018) +#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0400) +#define DOVE_GPIO_HI_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0420) +#define DOVE_GPIO2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe8400) +#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe803c) #define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1) #define DOVE_NAND_GPIO_EN (1 << 0) #define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40) @@ -142,44 +142,44 @@ #define DOVE_SD0_GPIO_SEL (1 << 0) /* Power Management */ -#define DOVE_PMU_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0000) +#define DOVE_PMU_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0000) #define DOVE_PMU_SIG_CTRL (DOVE_PMU_VIRT_BASE + 0x802c) /* Real Time Clock */ -#define DOVE_RTC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xd8500) +#define DOVE_RTC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xd8500) /* AC97 */ -#define DOVE_AC97_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xe0000) -#define DOVE_AC97_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe0000) +#define DOVE_AC97_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xe0000) +#define DOVE_AC97_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe0000) /* Peripheral DMA */ -#define DOVE_PDMA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xe4000) -#define DOVE_PDMA_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe4000) +#define DOVE_PDMA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xe4000) +#define DOVE_PDMA_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe4000) -#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE | 0xe802C) +#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C) #define DOVE_TWSI_ENABLE_OPTION1 (1 << 7) -#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE | 0xe8030) +#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE + 0xe8030) #define DOVE_TWSI_ENABLE_OPTION2 (1 << 20) #define DOVE_TWSI_ENABLE_OPTION3 (1 << 21) #define DOVE_TWSI_OPTION3_GPIO (1 << 22) -#define DOVE_SSP_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xec000) -#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE | 0xe8034) +#define DOVE_SSP_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xec000) +#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE + 0xe8034) #define DOVE_SSP_ON_AU1 (1 << 0) #define DOVE_SSP_CLOCK_ENABLE (1 << 1) #define DOVE_SSP_BPB_CLOCK_SRC_SSP (1 << 11) /* Memory Controller */ -#define DOVE_MC_VIRT_BASE (DOVE_NB_REGS_VIRT_BASE | 0x00000) +#define DOVE_MC_VIRT_BASE (DOVE_NB_REGS_VIRT_BASE + 0x00000) /* LCD Controller */ -#define DOVE_LCD_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x10000) -#define DOVE_LCD1_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x20000) -#define DOVE_LCD2_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x10000) -#define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x30000) +#define DOVE_LCD_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x10000) +#define DOVE_LCD1_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x20000) +#define DOVE_LCD2_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x10000) +#define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x30000) /* Graphic Engine */ -#define DOVE_GPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x40000) +#define DOVE_GPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x40000) /* Video Engine */ -#define DOVE_VPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x400000) +#define DOVE_VPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x400000) #endif diff --git a/arch/arm/mach-dove/include/mach/pm.h b/arch/arm/mach-dove/include/mach/pm.h index 3ad9f946a9e8..7bcd0dfce4b1 100644 --- a/arch/arm/mach-dove/include/mach/pm.h +++ b/arch/arm/mach-dove/include/mach/pm.h @@ -13,24 +13,42 @@ #include <mach/irqs.h> #define CLOCK_GATING_CONTROL (DOVE_PMU_VIRT_BASE + 0x38) -#define CLOCK_GATING_USB0_MASK (1 << 0) -#define CLOCK_GATING_USB1_MASK (1 << 1) -#define CLOCK_GATING_GBE_MASK (1 << 2) -#define CLOCK_GATING_SATA_MASK (1 << 3) -#define CLOCK_GATING_PCIE0_MASK (1 << 4) -#define CLOCK_GATING_PCIE1_MASK (1 << 5) -#define CLOCK_GATING_SDIO0_MASK (1 << 8) -#define CLOCK_GATING_SDIO1_MASK (1 << 9) -#define CLOCK_GATING_NAND_MASK (1 << 10) -#define CLOCK_GATING_CAMERA_MASK (1 << 11) -#define CLOCK_GATING_I2S0_MASK (1 << 12) -#define CLOCK_GATING_I2S1_MASK (1 << 13) -#define CLOCK_GATING_CRYPTO_MASK (1 << 15) -#define CLOCK_GATING_AC97_MASK (1 << 21) -#define CLOCK_GATING_PDMA_MASK (1 << 22) -#define CLOCK_GATING_XOR0_MASK (1 << 23) -#define CLOCK_GATING_XOR1_MASK (1 << 24) -#define CLOCK_GATING_GIGA_PHY_MASK (1 << 30) +#define CLOCK_GATING_BIT_USB0 0 +#define CLOCK_GATING_BIT_USB1 1 +#define CLOCK_GATING_BIT_GBE 2 +#define CLOCK_GATING_BIT_SATA 3 +#define CLOCK_GATING_BIT_PCIE0 4 +#define CLOCK_GATING_BIT_PCIE1 5 +#define CLOCK_GATING_BIT_SDIO0 8 +#define CLOCK_GATING_BIT_SDIO1 9 +#define CLOCK_GATING_BIT_NAND 10 +#define CLOCK_GATING_BIT_CAMERA 11 +#define CLOCK_GATING_BIT_I2S0 12 +#define CLOCK_GATING_BIT_I2S1 13 +#define CLOCK_GATING_BIT_CRYPTO 15 +#define CLOCK_GATING_BIT_AC97 21 +#define CLOCK_GATING_BIT_PDMA 22 +#define CLOCK_GATING_BIT_XOR0 23 +#define CLOCK_GATING_BIT_XOR1 24 +#define CLOCK_GATING_BIT_GIGA_PHY 30 +#define CLOCK_GATING_USB0_MASK (1 << CLOCK_GATING_BIT_USB0) +#define CLOCK_GATING_USB1_MASK (1 << CLOCK_GATING_BIT_USB1) +#define CLOCK_GATING_GBE_MASK (1 << CLOCK_GATING_BIT_GBE) +#define CLOCK_GATING_SATA_MASK (1 << CLOCK_GATING_BIT_SATA) +#define CLOCK_GATING_PCIE0_MASK (1 << CLOCK_GATING_BIT_PCIE0) +#define CLOCK_GATING_PCIE1_MASK (1 << CLOCK_GATING_BIT_PCIE1) +#define CLOCK_GATING_SDIO0_MASK (1 << CLOCK_GATING_BIT_SDIO0) +#define CLOCK_GATING_SDIO1_MASK (1 << CLOCK_GATING_BIT_SDIO1) +#define CLOCK_GATING_NAND_MASK (1 << CLOCK_GATING_BIT_NAND) +#define CLOCK_GATING_CAMERA_MASK (1 << CLOCK_GATING_BIT_CAMERA) +#define CLOCK_GATING_I2S0_MASK (1 << CLOCK_GATING_BIT_I2S0) +#define CLOCK_GATING_I2S1_MASK (1 << CLOCK_GATING_BIT_I2S1) +#define CLOCK_GATING_CRYPTO_MASK (1 << CLOCK_GATING_BIT_CRYPTO) +#define CLOCK_GATING_AC97_MASK (1 << CLOCK_GATING_BIT_AC97) +#define CLOCK_GATING_PDMA_MASK (1 << CLOCK_GATING_BIT_PDMA) +#define CLOCK_GATING_XOR0_MASK (1 << CLOCK_GATING_BIT_XOR0) +#define CLOCK_GATING_XOR1_MASK (1 << CLOCK_GATING_BIT_XOR1) +#define CLOCK_GATING_GIGA_PHY_MASK (1 << CLOCK_GATING_BIT_GIGA_PHY) #define PMU_INTERRUPT_CAUSE (DOVE_PMU_VIRT_BASE + 0x50) #define PMU_INTERRUPT_MASK (DOVE_PMU_VIRT_BASE + 0x54) diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c index 186357f3b4db..087711524e8a 100644 --- a/arch/arm/mach-dove/irq.c +++ b/arch/arm/mach-dove/irq.c @@ -100,19 +100,19 @@ void __init dove_init_irq(void) { int i; - orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); - orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); + orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF); + orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF); /* * Initialize gpiolib for GPIOs 0-71. */ - orion_gpio_init(NULL, 0, 32, (void __iomem *)DOVE_GPIO_LO_VIRT_BASE, 0, + orion_gpio_init(NULL, 0, 32, DOVE_GPIO_LO_VIRT_BASE, 0, IRQ_DOVE_GPIO_START, gpio0_irqs); - orion_gpio_init(NULL, 32, 32, (void __iomem *)DOVE_GPIO_HI_VIRT_BASE, 0, + orion_gpio_init(NULL, 32, 32, DOVE_GPIO_HI_VIRT_BASE, 0, IRQ_DOVE_GPIO_START + 32, gpio1_irqs); - orion_gpio_init(NULL, 64, 8, (void __iomem *)DOVE_GPIO2_VIRT_BASE, 0, + orion_gpio_init(NULL, 64, 8, DOVE_GPIO2_VIRT_BASE, 0, IRQ_DOVE_GPIO_START + 64, gpio2_irqs); /* diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c index 355332d502cb..0ef4435b1657 100644 --- a/arch/arm/mach-dove/pcie.c +++ b/arch/arm/mach-dove/pcie.c @@ -10,6 +10,7 @@ #include <linux/kernel.h> #include <linux/pci.h> +#include <linux/clk.h> #include <video/vga.h> #include <asm/mach/pci.h> #include <asm/mach/arch.h> @@ -182,18 +183,22 @@ static struct hw_pci dove_pci __initdata = { .map_irq = dove_pcie_map_irq, }; -static void __init add_pcie_port(int index, unsigned long base) +static void __init add_pcie_port(int index, void __iomem *base) { printk(KERN_INFO "Dove PCIe port %d: ", index); - if (orion_pcie_link_up((void __iomem *)base)) { + if (orion_pcie_link_up(base)) { struct pcie_port *pp = &pcie_port[num_pcie_ports++]; + struct clk *clk = clk_get_sys("pcie", (index ? "1" : "0")); + + if (!IS_ERR(clk)) + clk_prepare_enable(clk); printk(KERN_INFO "link up\n"); pp->index = index; pp->root_bus_nr = -1; - pp->base = (void __iomem *)base; + pp->base = base; spin_lock_init(&pp->conf_lock); memset(&pp->res, 0, sizeof(pp->res)); } else { diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 4372075c551f..da55107033dd 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -31,11 +31,11 @@ config CPU_EXYNOS4210 bool "SAMSUNG EXYNOS4210" default y depends on ARCH_EXYNOS4 - select SAMSUNG_DMADEV select ARM_CPU_SUSPEND if PM + select PM_GENERIC_DOMAINS select S5P_PM if PM select S5P_SLEEP if PM - select PM_GENERIC_DOMAINS + select SAMSUNG_DMADEV help Enable EXYNOS4210 CPU support @@ -43,9 +43,9 @@ config SOC_EXYNOS4212 bool "SAMSUNG EXYNOS4212" default y depends on ARCH_EXYNOS4 - select SAMSUNG_DMADEV select S5P_PM if PM select S5P_SLEEP if PM + select SAMSUNG_DMADEV help Enable EXYNOS4212 SoC support @@ -61,9 +61,9 @@ config SOC_EXYNOS5250 bool "SAMSUNG EXYNOS5250" default y depends on ARCH_EXYNOS5 - select SAMSUNG_DMADEV select S5P_PM if PM select S5P_SLEEP if PM + select SAMSUNG_DMADEV help Enable EXYNOS5250 SoC support @@ -189,71 +189,71 @@ config MACH_SMDKC210 config MACH_SMDKV310 bool "SMDKV310" select CPU_EXYNOS4210 - select S5P_DEV_FIMD0 + select EXYNOS4_DEV_AHCI + select EXYNOS4_DEV_USB_OHCI + select EXYNOS4_SETUP_FIMD0 + select EXYNOS4_SETUP_I2C1 + select EXYNOS4_SETUP_KEYPAD + select EXYNOS4_SETUP_SDHCI + select EXYNOS4_SETUP_USB_PHY + select EXYNOS_DEV_DMA + select EXYNOS_DEV_DRM + select EXYNOS_DEV_SYSMMU + select S3C24XX_PWM + select S3C_DEV_HSMMC + select S3C_DEV_HSMMC1 + select S3C_DEV_HSMMC2 + select S3C_DEV_HSMMC3 + select S3C_DEV_I2C1 select S3C_DEV_RTC + select S3C_DEV_USB_HSOTG select S3C_DEV_WDT - select S3C_DEV_I2C1 select S5P_DEV_FIMC0 select S5P_DEV_FIMC1 select S5P_DEV_FIMC2 select S5P_DEV_FIMC3 + select S5P_DEV_FIMD0 select S5P_DEV_G2D select S5P_DEV_I2C_HDMIPHY select S5P_DEV_JPEG select S5P_DEV_MFC select S5P_DEV_TV select S5P_DEV_USB_EHCI - select S3C_DEV_HSMMC - select S3C_DEV_HSMMC1 - select S3C_DEV_HSMMC2 - select S3C_DEV_HSMMC3 - select S3C_DEV_USB_HSOTG select SAMSUNG_DEV_BACKLIGHT - select EXYNOS_DEV_DRM - select EXYNOS_DEV_SYSMMU - select EXYNOS4_DEV_AHCI select SAMSUNG_DEV_KEYPAD - select EXYNOS_DEV_DMA select SAMSUNG_DEV_PWM - select EXYNOS4_DEV_USB_OHCI - select EXYNOS4_SETUP_FIMD0 - select EXYNOS4_SETUP_I2C1 - select EXYNOS4_SETUP_KEYPAD - select EXYNOS4_SETUP_SDHCI - select EXYNOS4_SETUP_USB_PHY - select S3C24XX_PWM help Machine support for Samsung SMDKV310 config MACH_ARMLEX4210 bool "ARMLEX4210" select CPU_EXYNOS4210 - select S3C_DEV_RTC - select S3C_DEV_WDT + select EXYNOS4_DEV_AHCI + select EXYNOS4_SETUP_SDHCI + select EXYNOS_DEV_DMA select S3C_DEV_HSMMC select S3C_DEV_HSMMC2 select S3C_DEV_HSMMC3 - select EXYNOS4_DEV_AHCI - select EXYNOS_DEV_DMA - select EXYNOS4_SETUP_SDHCI + select S3C_DEV_RTC + select S3C_DEV_WDT help Machine support for Samsung ARMLEX4210 based on EXYNOS4210 config MACH_UNIVERSAL_C210 bool "Mobile UNIVERSAL_C210 Board" - select CPU_EXYNOS4210 - select S5P_HRT select CLKSRC_MMIO + select CPU_EXYNOS4210 + select EXYNOS4_SETUP_FIMC + select EXYNOS4_SETUP_FIMD0 + select EXYNOS4_SETUP_I2C1 + select EXYNOS4_SETUP_I2C3 + select EXYNOS4_SETUP_I2C5 + select EXYNOS4_SETUP_SDHCI + select EXYNOS4_SETUP_USB_PHY + select EXYNOS_DEV_DMA + select EXYNOS_DEV_DRM + select EXYNOS_DEV_SYSMMU select HAVE_SCHED_CLOCK - select S5P_GPIO_INT - select S5P_DEV_FIMC0 - select S5P_DEV_FIMC1 - select S5P_DEV_FIMC2 - select S5P_DEV_FIMC3 - select S5P_DEV_G2D - select S5P_DEV_CSIS0 - select S5P_DEV_JPEG - select S5P_DEV_FIMD0 select S3C_DEV_HSMMC select S3C_DEV_HSMMC2 select S3C_DEV_HSMMC3 @@ -261,21 +261,21 @@ config MACH_UNIVERSAL_C210 select S3C_DEV_I2C3 select S3C_DEV_I2C5 select S3C_DEV_USB_HSOTG + select S5P_DEV_CSIS0 + select S5P_DEV_FIMC0 + select S5P_DEV_FIMC1 + select S5P_DEV_FIMC2 + select S5P_DEV_FIMC3 + select S5P_DEV_FIMD0 + select S5P_DEV_G2D select S5P_DEV_I2C_HDMIPHY + select S5P_DEV_JPEG select S5P_DEV_MFC select S5P_DEV_ONENAND select S5P_DEV_TV - select EXYNOS_DEV_SYSMMU - select EXYNOS_DEV_DMA - select EXYNOS_DEV_DRM - select EXYNOS4_SETUP_FIMD0 - select EXYNOS4_SETUP_I2C1 - select EXYNOS4_SETUP_I2C3 - select EXYNOS4_SETUP_I2C5 - select EXYNOS4_SETUP_SDHCI - select EXYNOS4_SETUP_FIMC + select S5P_GPIO_INT + select S5P_HRT select S5P_SETUP_MIPIPHY - select EXYNOS4_SETUP_USB_PHY help Machine support for Samsung Mobile Universal S5PC210 Reference Board. @@ -283,10 +283,16 @@ config MACH_UNIVERSAL_C210 config MACH_NURI bool "Mobile NURI Board" select CPU_EXYNOS4210 - select S5P_GPIO_INT - select S3C_DEV_WDT - select S3C_DEV_RTC - select S5P_DEV_FIMD0 + select EXYNOS4_SETUP_FIMC + select EXYNOS4_SETUP_FIMD0 + select EXYNOS4_SETUP_I2C1 + select EXYNOS4_SETUP_I2C3 + select EXYNOS4_SETUP_I2C5 + select EXYNOS4_SETUP_I2C6 + select EXYNOS4_SETUP_SDHCI + select EXYNOS4_SETUP_USB_PHY + select EXYNOS_DEV_DMA + select EXYNOS_DEV_DRM select S3C_DEV_HSMMC select S3C_DEV_HSMMC2 select S3C_DEV_HSMMC3 @@ -294,41 +300,42 @@ config MACH_NURI select S3C_DEV_I2C3 select S3C_DEV_I2C5 select S3C_DEV_I2C6 + select S3C_DEV_RTC select S3C_DEV_USB_HSOTG + select S3C_DEV_WDT select S5P_DEV_CSIS0 - select S5P_DEV_JPEG select S5P_DEV_FIMC0 select S5P_DEV_FIMC1 select S5P_DEV_FIMC2 select S5P_DEV_FIMC3 + select S5P_DEV_FIMD0 select S5P_DEV_G2D + select S5P_DEV_JPEG select S5P_DEV_MFC select S5P_DEV_USB_EHCI + select S5P_GPIO_INT select S5P_SETUP_MIPIPHY - select EXYNOS_DEV_DMA - select EXYNOS_DEV_DRM - select EXYNOS4_SETUP_FIMC - select EXYNOS4_SETUP_FIMD0 - select EXYNOS4_SETUP_I2C1 - select EXYNOS4_SETUP_I2C3 - select EXYNOS4_SETUP_I2C5 - select EXYNOS4_SETUP_I2C6 - select EXYNOS4_SETUP_SDHCI - select EXYNOS4_SETUP_USB_PHY - select S5P_SETUP_MIPIPHY - select SAMSUNG_DEV_PWM select SAMSUNG_DEV_ADC + select SAMSUNG_DEV_PWM help Machine support for Samsung Mobile NURI Board. config MACH_ORIGEN bool "ORIGEN" select CPU_EXYNOS4210 - select S3C_DEV_RTC - select S3C_DEV_WDT + select EXYNOS4_DEV_USB_OHCI + select EXYNOS4_SETUP_FIMD0 + select EXYNOS4_SETUP_SDHCI + select EXYNOS4_SETUP_USB_PHY + select EXYNOS_DEV_DMA + select EXYNOS_DEV_DRM + select EXYNOS_DEV_SYSMMU + select S3C24XX_PWM select S3C_DEV_HSMMC select S3C_DEV_HSMMC2 + select S3C_DEV_RTC select S3C_DEV_USB_HSOTG + select S3C_DEV_WDT select S5P_DEV_FIMC0 select S5P_DEV_FIMC1 select S5P_DEV_FIMC2 @@ -342,14 +349,6 @@ config MACH_ORIGEN select S5P_DEV_USB_EHCI select SAMSUNG_DEV_BACKLIGHT select SAMSUNG_DEV_PWM - select EXYNOS_DEV_DRM - select EXYNOS_DEV_SYSMMU - select EXYNOS_DEV_DMA - select EXYNOS4_DEV_USB_OHCI - select EXYNOS4_SETUP_FIMD0 - select EXYNOS4_SETUP_SDHCI - select EXYNOS4_SETUP_USB_PHY - select S3C24XX_PWM help Machine support for ORIGEN based on Samsung EXYNOS4210 @@ -357,7 +356,17 @@ comment "EXYNOS4212 Boards" config MACH_SMDK4212 bool "SMDK4212" - select SOC_EXYNOS4212 + select EXYNOS4_SETUP_FIMD0 + select EXYNOS4_SETUP_I2C1 + select EXYNOS4_SETUP_I2C3 + select EXYNOS4_SETUP_I2C7 + select EXYNOS4_SETUP_KEYPAD + select EXYNOS4_SETUP_SDHCI + select EXYNOS4_SETUP_USB_PHY + select EXYNOS_DEV_DMA + select EXYNOS_DEV_DRM + select EXYNOS_DEV_SYSMMU + select S3C24XX_PWM select S3C_DEV_HSMMC2 select S3C_DEV_HSMMC3 select S3C_DEV_I2C1 @@ -375,17 +384,7 @@ config MACH_SMDK4212 select SAMSUNG_DEV_BACKLIGHT select SAMSUNG_DEV_KEYPAD select SAMSUNG_DEV_PWM - select EXYNOS_DEV_SYSMMU - select EXYNOS_DEV_DMA - select EXYNOS_DEV_DRM - select EXYNOS4_SETUP_FIMD0 - select EXYNOS4_SETUP_I2C1 - select EXYNOS4_SETUP_I2C3 - select EXYNOS4_SETUP_I2C7 - select EXYNOS4_SETUP_KEYPAD - select EXYNOS4_SETUP_SDHCI - select EXYNOS4_SETUP_USB_PHY - select S3C24XX_PWM + select SOC_EXYNOS4212 help Machine support for Samsung SMDK4212 @@ -393,8 +392,8 @@ comment "EXYNOS4412 Boards" config MACH_SMDK4412 bool "SMDK4412" - select SOC_EXYNOS4412 select MACH_SMDK4212 + select SOC_EXYNOS4412 help Machine support for Samsung SMDK4412 endif @@ -404,12 +403,12 @@ comment "Flattened Device Tree based board for EXYNOS SoCs" config MACH_EXYNOS4_DT bool "Samsung Exynos4 Machine using device tree" depends on ARCH_EXYNOS4 - select CPU_EXYNOS4210 - select USE_OF select ARM_AMBA + select CPU_EXYNOS4210 select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD select PINCTRL select PINCTRL_EXYNOS4 + select USE_OF help Machine support for Samsung Exynos4 machine with device tree enabled. Select this if a fdt blob is available for the Exynos4 SoC based board. @@ -419,9 +418,9 @@ config MACH_EXYNOS4_DT config MACH_EXYNOS5_DT bool "SAMSUNG EXYNOS5 Machine using device tree" depends on ARCH_EXYNOS5 + select ARM_AMBA select SOC_EXYNOS5250 select USE_OF - select ARM_AMBA help Machine support for Samsung EXYNOS5 machine with device tree enabled. Select this if a fdt blob is available for the EXYNOS5 SoC based board. diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 715b690e5009..1947be8e5f5b 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -47,6 +47,7 @@ #include <plat/fimc-core.h> #include <plat/iic-core.h> #include <plat/tv-core.h> +#include <plat/spi-core.h> #include <plat/regs-serial.h> #include "common.h" @@ -346,6 +347,8 @@ static void __init exynos4_map_io(void) s5p_fb_setname(0, "exynos4-fb"); s5p_hdmi_setname("exynos4-hdmi"); + + s3c64xx_spi_setname("exynos4210-spi"); } static void __init exynos5_map_io(void) @@ -366,6 +369,8 @@ static void __init exynos5_map_io(void) s3c_i2c0_setname("s3c2440-i2c"); s3c_i2c1_setname("s3c2440-i2c"); s3c_i2c2_setname("s3c2440-i2c"); + + s3c64xx_spi_setname("exynos4210-spi"); } static void __init exynos4_init_clocks(int xtal) diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c index f60b66dbcf84..21d568b3b149 100644 --- a/arch/arm/mach-exynos/dma.c +++ b/arch/arm/mach-exynos/dma.c @@ -303,10 +303,12 @@ static int __init exynos_dma_init(void) dma_cap_set(DMA_SLAVE, exynos_pdma0_pdata.cap_mask); dma_cap_set(DMA_CYCLIC, exynos_pdma0_pdata.cap_mask); + dma_cap_set(DMA_PRIVATE, exynos_pdma0_pdata.cap_mask); amba_device_register(&exynos_pdma0_device, &iomem_resource); dma_cap_set(DMA_SLAVE, exynos_pdma1_pdata.cap_mask); dma_cap_set(DMA_CYCLIC, exynos_pdma1_pdata.cap_mask); + dma_cap_set(DMA_PRIVATE, exynos_pdma1_pdata.cap_mask); amba_device_register(&exynos_pdma1_device, &iomem_resource); dma_cap_set(DMA_MEMCPY, exynos_mdma1_pdata.cap_mask); diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c index e58d786faf78..eadf4b59e7d2 100644 --- a/arch/arm/mach-exynos/mach-exynos4-dt.c +++ b/arch/arm/mach-exynos/mach-exynos4-dt.c @@ -99,6 +99,7 @@ static char const *exynos4_dt_compat[] __initdata = { DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)") /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */ + .smp = smp_ops(exynos_smp_ops), .init_irq = exynos4_init_irq, .map_io = exynos4_dt_map_io, .handle_irq = gic_handle_irq, diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c index 480cd78f1920..c05d7aa84031 100644 --- a/arch/arm/mach-exynos/mach-nuri.c +++ b/arch/arm/mach-exynos/mach-nuri.c @@ -29,6 +29,7 @@ #include <drm/exynos_drm.h> #include <video/platform_lcd.h> +#include <video/samsung_fimd.h> #include <media/m5mols.h> #include <media/s5k6aa.h> #include <media/s5p_fimc.h> @@ -39,7 +40,6 @@ #include <asm/mach-types.h> #include <plat/adc.h> -#include <plat/regs-fb-v4.h> #include <plat/regs-serial.h> #include <plat/cpu.h> #include <plat/devs.h> @@ -378,10 +378,10 @@ static struct regulator_consumer_supply __initdata max8997_ldo1_[] = { }; static struct regulator_consumer_supply __initdata max8997_ldo3_[] = { REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"), /* USB */ - REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"), /* MIPI */ + REGULATOR_SUPPLY("vddcore", "s5p-mipi-csis.0"), /* MIPI */ }; static struct regulator_consumer_supply __initdata max8997_ldo4_[] = { - REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"), /* MIPI */ + REGULATOR_SUPPLY("vddio", "s5p-mipi-csis.0"), /* MIPI */ }; static struct regulator_consumer_supply __initdata max8997_ldo5_[] = { REGULATOR_SUPPLY("vhsic", "modemctl"), /* MODEM */ @@ -1180,9 +1180,7 @@ static struct platform_device cam_8m_12v_fixed_rdev = { static struct s5p_platform_mipi_csis mipi_csis_platdata = { .clk_rate = 166000000UL, .lanes = 2, - .alignment = 32, .hs_settle = 12, - .phy_enable = s5p_csis_phy_enable, }; #define GPIO_CAM_MEGA_RST EXYNOS4_GPY3(7) /* ISP_RESET */ @@ -1226,7 +1224,6 @@ static struct s5p_fimc_isp_info nuri_camera_sensors[] = { .bus_type = FIMC_MIPI_CSI2, .board_info = &m5mols_board_info, .clk_frequency = 24000000UL, - .csi_data_align = 32, }, }; diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c index 67b50bb89c0f..9adf491674ea 100644 --- a/arch/arm/mach-exynos/mach-origen.c +++ b/arch/arm/mach-exynos/mach-origen.c @@ -30,9 +30,9 @@ #include <asm/mach-types.h> #include <video/platform_lcd.h> +#include <video/samsung_fimd.h> #include <plat/regs-serial.h> -#include <plat/regs-fb-v4.h> #include <plat/cpu.h> #include <plat/devs.h> #include <plat/sdhci.h> @@ -97,12 +97,12 @@ static struct s3c2410_uartcfg origen_uartcfgs[] __initdata = { }; static struct regulator_consumer_supply __initdata ldo3_consumer[] = { - REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"), /* MIPI */ + REGULATOR_SUPPLY("vddcore", "s5p-mipi-csis.0"), /* MIPI */ REGULATOR_SUPPLY("vdd", "exynos4-hdmi"), /* HDMI */ REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"), /* HDMI */ }; static struct regulator_consumer_supply __initdata ldo6_consumer[] = { - REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"), /* MIPI */ + REGULATOR_SUPPLY("vddio", "s5p-mipi-csis.0"), /* MIPI */ }; static struct regulator_consumer_supply __initdata ldo7_consumer[] = { REGULATOR_SUPPLY("avdd", "alc5625"), /* Realtek ALC5625 */ diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c index 7a265d1a82d3..730f1ac65928 100644 --- a/arch/arm/mach-exynos/mach-smdk4x12.c +++ b/arch/arm/mach-exynos/mach-smdk4x12.c @@ -27,6 +27,7 @@ #include <asm/hardware/gic.h> #include <asm/mach-types.h> +#include <video/samsung_fimd.h> #include <plat/backlight.h> #include <plat/clock.h> #include <plat/cpu.h> @@ -36,7 +37,6 @@ #include <linux/platform_data/i2c-s3c2410.h> #include <plat/keypad.h> #include <plat/mfc.h> -#include <plat/regs-fb.h> #include <plat/regs-serial.h> #include <plat/sdhci.h> diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c index c15d2238ceb0..ee4fb1a9cb72 100644 --- a/arch/arm/mach-exynos/mach-smdkv310.c +++ b/arch/arm/mach-exynos/mach-smdkv310.c @@ -27,9 +27,9 @@ #include <asm/mach-types.h> #include <video/platform_lcd.h> +#include <video/samsung_fimd.h> #include <plat/regs-serial.h> #include <plat/regs-srom.h> -#include <plat/regs-fb-v4.h> #include <plat/cpu.h> #include <plat/devs.h> #include <plat/fb.h> diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c index 98d3aced2289..ebc9dd339a38 100644 --- a/arch/arm/mach-exynos/mach-universal_c210.c +++ b/arch/arm/mach-exynos/mach-universal_c210.c @@ -30,6 +30,7 @@ #include <asm/hardware/gic.h> #include <asm/mach-types.h> +#include <video/samsung_fimd.h> #include <plat/regs-serial.h> #include <plat/clock.h> #include <plat/cpu.h> @@ -39,7 +40,6 @@ #include <plat/fb.h> #include <plat/mfc.h> #include <plat/sdhci.h> -#include <plat/regs-fb-v4.h> #include <plat/fimc-core.h> #include <plat/s5p-time.h> #include <plat/camport.h> @@ -209,7 +209,7 @@ static struct regulator_consumer_supply lp3974_ldo3_consumer[] = { REGULATOR_SUPPLY("vusb_a", "s3c-hsotg"), REGULATOR_SUPPLY("vdd", "exynos4-hdmi"), REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"), - REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"), + REGULATOR_SUPPLY("vddcore", "s5p-mipi-csis.0"), }; static struct regulator_init_data lp3974_ldo3_data = { @@ -273,7 +273,7 @@ static struct regulator_init_data lp3974_ldo6_data = { }; static struct regulator_consumer_supply lp3974_ldo7_consumer[] = { - REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"), + REGULATOR_SUPPLY("vddio", "s5p-mipi-csis.0"), }; static struct regulator_init_data lp3974_ldo7_data = { @@ -942,9 +942,7 @@ static struct platform_device cam_s_if_fixed_reg_dev = { static struct s5p_platform_mipi_csis mipi_csis_platdata = { .clk_rate = 166000000UL, .lanes = 2, - .alignment = 32, .hs_settle = 12, - .phy_enable = s5p_csis_phy_enable, }; #define GPIO_CAM_LEVEL_EN(n) EXYNOS4_GPE4(n + 3) @@ -1008,7 +1006,6 @@ static struct s5p_fimc_isp_info universal_camera_sensors[] = { .board_info = &m5mols_board_info, .i2c_bus_num = 0, .clk_frequency = 24000000UL, - .csi_data_align = 32, }, }; diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index 8d57e4223bdb..f93d820ecab5 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -134,7 +134,7 @@ static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct __raw_writel(virt_to_phys(exynos4_secondary_startup), CPU1_BOOT_REG); - gic_raise_softirq(cpumask_of(cpu), 1); + gic_raise_softirq(cpumask_of(cpu), 0); if (pen_release == -1) break; diff --git a/arch/arm/mach-exynos/setup-fimd0.c b/arch/arm/mach-exynos/setup-fimd0.c index 07a6dbeecdd0..5665bb4e980b 100644 --- a/arch/arm/mach-exynos/setup-fimd0.c +++ b/arch/arm/mach-exynos/setup-fimd0.c @@ -13,8 +13,8 @@ #include <linux/fb.h> #include <linux/gpio.h> +#include <video/samsung_fimd.h> #include <plat/gpio-cfg.h> -#include <plat/regs-fb-v4.h> #include <mach/map.h> diff --git a/arch/arm/mach-footbridge/Kconfig b/arch/arm/mach-footbridge/Kconfig index f643ef819da6..abda5a18a664 100644 --- a/arch/arm/mach-footbridge/Kconfig +++ b/arch/arm/mach-footbridge/Kconfig @@ -91,7 +91,7 @@ config FOOTBRIDGE_ADDIN # EBSA285 board in either host or addin mode config ARCH_EBSA285 - select ARCH_MAY_HAVE_PC_FDC bool + select ARCH_MAY_HAVE_PC_FDC endif diff --git a/arch/arm/mach-footbridge/include/mach/irqs.h b/arch/arm/mach-footbridge/include/mach/irqs.h index 400551e43e4e..61c714c4920e 100644 --- a/arch/arm/mach-footbridge/include/mach/irqs.h +++ b/arch/arm/mach-footbridge/include/mach/irqs.h @@ -89,8 +89,6 @@ #define IRQ_NETWINDER_VGA _ISA_IRQ(11) #define IRQ_NETWINDER_SOUND _ISA_IRQ(12) -#undef RTC_IRQ -#define RTC_IRQ IRQ_ISA_RTC_ALARM #define I8042_KBD_IRQ IRQ_ISA_KEYBOARD #define I8042_AUX_IRQ (machine_is_netwinder() ? IRQ_NETWINDER_PS2MOUSE : IRQ_ISA_PS2MOUSE) #define IRQ_FLOPPYDISK IRQ_ISA_FLOPPY diff --git a/arch/arm/mach-h720x/Kconfig b/arch/arm/mach-h720x/Kconfig index abf356c02343..6bb755bcb6f5 100644 --- a/arch/arm/mach-h720x/Kconfig +++ b/arch/arm/mach-h720x/Kconfig @@ -12,9 +12,9 @@ config ARCH_H7201 config ARCH_H7202 bool "hms30c7202" + depends on ARCH_H720X select CPU_H7202 select ZONE_DMA - depends on ARCH_H720X help Say Y here if you are using the Hynix HMS30C7202 Reference Board diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 3a2042fb9712..8d276584650e 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -41,68 +41,68 @@ config SOC_IMX1 config SOC_IMX21 bool - select MACH_MX21 - select CPU_ARM926T select COMMON_CLK + select CPU_ARM926T select IMX_HAVE_IOMUX_V1 + select MACH_MX21 select MXC_AVIC config SOC_IMX25 bool select ARCH_MX25 + select ARCH_MXC_IOMUX_V3 select COMMON_CLK select CPU_ARM926T select HAVE_CAN_FLEXCAN if CAN - select ARCH_MXC_IOMUX_V3 select MXC_AVIC config SOC_IMX27 bool - select MACH_MX27 - select CPU_ARM926T select COMMON_CLK + select CPU_ARM926T select IMX_HAVE_IOMUX_V1 + select MACH_MX27 select MXC_AVIC config SOC_IMX31 bool + select COMMON_CLK select CPU_V6 select IMX_HAVE_PLATFORM_MXC_RNGA select MXC_AVIC - select COMMON_CLK select SMP_ON_UP if SMP config SOC_IMX35 bool - select CPU_V6K select ARCH_MXC_IOMUX_V3 select COMMON_CLK + select CPU_V6K + select HAVE_CAN_FLEXCAN if CAN select HAVE_EPIT select MXC_AVIC select SMP_ON_UP if SMP - select HAVE_CAN_FLEXCAN if CAN config SOC_IMX5 - select CPU_V7 - select MXC_TZIC - select COMMON_CLK - select ARCH_MXC_IOMUX_V3 + bool select ARCH_HAS_CPUFREQ select ARCH_MX5 - bool + select ARCH_MXC_IOMUX_V3 + select COMMON_CLK + select CPU_V7 + select MXC_TZIC config SOC_IMX50 bool - select SOC_IMX5 select ARCH_MX50 + select SOC_IMX5 config SOC_IMX51 bool - select SOC_IMX5 select ARCH_MX5 select ARCH_MX51 select PINCTRL select PINCTRL_IMX51 + select SOC_IMX5 if ARCH_IMX_V4_V5 @@ -112,10 +112,10 @@ config MACH_MXLADS config ARCH_MX1ADS bool "MX1ADS platform" - select MACH_MXLADS - select SOC_IMX1 select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART + select MACH_MXLADS + select SOC_IMX1 help Say Y here if you are using Motorola MX1ADS/MXLADS boards @@ -127,9 +127,9 @@ config MACH_SCB9328 config MACH_APF9328 bool "APF9328" - select SOC_IMX1 select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART + select SOC_IMX1 help Say Yes here if you are using the Armadeus APF9328 development board @@ -137,11 +137,11 @@ comment "MX21 platforms:" config MACH_MX21ADS bool "MX21ADS platform" - select SOC_IMX21 select IMX_HAVE_PLATFORM_IMX_FB select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_MXC_MMC select IMX_HAVE_PLATFORM_MXC_NAND + select SOC_IMX21 help Include support for MX21ADS platform. This includes specific configurations for the board and its peripherals. @@ -150,22 +150,21 @@ comment "MX25 platforms:" config MACH_MX25_3DS bool "Support MX25PDK (3DS) Platform" - select SOC_IMX25 select IMX_HAVE_PLATFORM_FLEXCAN select IMX_HAVE_PLATFORM_FSL_USB2_UDC select IMX_HAVE_PLATFORM_IMX2_WDT select IMX_HAVE_PLATFORM_IMXDI_RTC - select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_FB + select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_KEYPAD select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_MXC_EHCI select IMX_HAVE_PLATFORM_MXC_NAND select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX + select SOC_IMX25 config MACH_EUKREA_CPUIMX25SD bool "Support Eukrea CPUIMX25 Platform" - select SOC_IMX25 select IMX_HAVE_PLATFORM_FLEXCAN select IMX_HAVE_PLATFORM_FSL_USB2_UDC select IMX_HAVE_PLATFORM_IMX2_WDT @@ -177,6 +176,7 @@ config MACH_EUKREA_CPUIMX25SD select IMX_HAVE_PLATFORM_MXC_NAND select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX select MXC_ULPI if USB_ULPI + select SOC_IMX25 choice prompt "Baseboard" @@ -199,20 +199,19 @@ comment "MX27 platforms:" config MACH_MX27ADS bool "MX27ADS platform" - select SOC_IMX27 select IMX_HAVE_PLATFORM_IMX_FB select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_MXC_MMC select IMX_HAVE_PLATFORM_MXC_NAND select IMX_HAVE_PLATFORM_MXC_W1 + select SOC_IMX27 help Include support for MX27ADS platform. This includes specific configurations for the board and its peripherals. config MACH_PCM038 bool "Phytec phyCORE-i.MX27 CPU module (pcm038)" - select SOC_IMX27 select IMX_HAVE_PLATFORM_IMX2_WDT select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART @@ -221,6 +220,7 @@ config MACH_PCM038 select IMX_HAVE_PLATFORM_MXC_W1 select IMX_HAVE_PLATFORM_SPI_IMX select MXC_ULPI if USB_ULPI + select SOC_IMX27 help Include support for phyCORE-i.MX27 (aka pcm038) platform. This includes specific configurations for the module and its peripherals. @@ -242,7 +242,6 @@ endchoice config MACH_CPUIMX27 bool "Eukrea CPUIMX27 module" - select SOC_IMX27 select IMX_HAVE_PLATFORM_FSL_USB2_UDC select IMX_HAVE_PLATFORM_IMX2_WDT select IMX_HAVE_PLATFORM_IMX_I2C @@ -251,6 +250,7 @@ config MACH_CPUIMX27 select IMX_HAVE_PLATFORM_MXC_NAND select IMX_HAVE_PLATFORM_MXC_W1 select MXC_ULPI if USB_ULPI + select SOC_IMX27 help Include support for Eukrea CPUIMX27 platform. This includes specific configurations for the module and its peripherals. @@ -292,7 +292,6 @@ endchoice config MACH_MX27_3DS bool "MX27PDK platform" - select SOC_IMX27 select IMX_HAVE_PLATFORM_FSL_USB2_UDC select IMX_HAVE_PLATFORM_IMX2_WDT select IMX_HAVE_PLATFORM_IMX_FB @@ -306,13 +305,13 @@ config MACH_MX27_3DS select IMX_HAVE_PLATFORM_SPI_IMX select MXC_DEBUG_BOARD select MXC_ULPI if USB_ULPI + select SOC_IMX27 help Include support for MX27PDK platform. This includes specific configurations for the board and its peripherals. config MACH_IMX27_VISSTRIM_M10 bool "Vista Silicon i.MX27 Visstrim_m10" - select SOC_IMX27 select IMX_HAVE_PLATFORM_GPIO_KEYS select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_SSI @@ -321,6 +320,7 @@ config MACH_IMX27_VISSTRIM_M10 select IMX_HAVE_PLATFORM_MXC_EHCI select IMX_HAVE_PLATFORM_MXC_MMC select LEDS_GPIO_REGISTER + select SOC_IMX27 help Include support for Visstrim_m10 platform and its different variants. This includes specific configurations for the board and its @@ -328,16 +328,15 @@ config MACH_IMX27_VISSTRIM_M10 config MACH_IMX27LITE bool "LogicPD MX27 LITEKIT platform" - select SOC_IMX27 - select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_IMX_SSI + select IMX_HAVE_PLATFORM_IMX_UART + select SOC_IMX27 help Include support for MX27 LITEKIT platform. This includes specific configurations for the board and its peripherals. config MACH_PCA100 bool "Phytec phyCARD-s (pca100)" - select SOC_IMX27 select IMX_HAVE_PLATFORM_FSL_USB2_UDC select IMX_HAVE_PLATFORM_IMX2_WDT select IMX_HAVE_PLATFORM_IMX_FB @@ -350,27 +349,28 @@ config MACH_PCA100 select IMX_HAVE_PLATFORM_MXC_W1 select IMX_HAVE_PLATFORM_SPI_IMX select MXC_ULPI if USB_ULPI + select SOC_IMX27 help Include support for phyCARD-s (aka pca100) platform. This includes specific configurations for the module and its peripherals. config MACH_MXT_TD60 bool "Maxtrack i-MXT TD60" - select SOC_IMX27 select IMX_HAVE_PLATFORM_IMX_FB select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_MXC_MMC select IMX_HAVE_PLATFORM_MXC_NAND + select SOC_IMX27 help Include support for i-MXT (aka td60) platform. This includes specific configurations for the module and its peripherals. config MACH_IMX27IPCAM bool "IMX27 IPCAM platform" - select SOC_IMX27 select IMX_HAVE_PLATFORM_IMX2_WDT select IMX_HAVE_PLATFORM_IMX_UART + select SOC_IMX27 help Include support for IMX27 IPCAM platform. This includes specific configurations for the board and its peripherals. @@ -390,11 +390,11 @@ comment "MX31 platforms:" config MACH_MX31ADS bool "Support MX31ADS platforms" - select SOC_IMX31 + default y select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_SSI select IMX_HAVE_PLATFORM_IMX_UART - default y + select SOC_IMX31 help Include support for MX31ADS platform. This includes specific configurations for the board and its peripherals. @@ -412,21 +412,19 @@ config MACH_MX31ADS_WM1133_EV1 config MACH_MX31LILLY bool "Support MX31 LILLY-1131 platforms (INCO startec)" - select SOC_IMX31 select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_IPU_CORE select IMX_HAVE_PLATFORM_MXC_EHCI select IMX_HAVE_PLATFORM_MXC_MMC select IMX_HAVE_PLATFORM_SPI_IMX select MXC_ULPI if USB_ULPI + select SOC_IMX31 help Include support for mx31 based LILLY1131 modules. This includes specific configurations for the board and its peripherals. config MACH_MX31LITE bool "Support MX31 LITEKIT (LogicPD)" - select SOC_IMX31 - select MXC_ULPI if USB_ULPI select IMX_HAVE_PLATFORM_IMX2_WDT select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_MXC_EHCI @@ -435,13 +433,14 @@ config MACH_MX31LITE select IMX_HAVE_PLATFORM_MXC_RTC select IMX_HAVE_PLATFORM_SPI_IMX select LEDS_GPIO_REGISTER + select MXC_ULPI if USB_ULPI + select SOC_IMX31 help Include support for MX31 LITEKIT platform. This includes specific configurations for the board and its peripherals. config MACH_PCM037 bool "Support Phytec pcm037 (i.MX31) platforms" - select SOC_IMX31 select IMX_HAVE_PLATFORM_FSL_USB2_UDC select IMX_HAVE_PLATFORM_IMX2_WDT select IMX_HAVE_PLATFORM_IMX_I2C @@ -452,6 +451,7 @@ config MACH_PCM037 select IMX_HAVE_PLATFORM_MXC_NAND select IMX_HAVE_PLATFORM_MXC_W1 select MXC_ULPI if USB_ULPI + select SOC_IMX31 help Include support for Phytec pcm037 platform. This includes specific configurations for the board and its peripherals. @@ -468,8 +468,6 @@ config MACH_PCM037_EET config MACH_MX31_3DS bool "Support MX31PDK (3DS)" - select SOC_IMX31 - select MXC_DEBUG_BOARD select IMX_HAVE_PLATFORM_FSL_USB2_UDC select IMX_HAVE_PLATFORM_IMX2_WDT select IMX_HAVE_PLATFORM_IMX_I2C @@ -481,7 +479,9 @@ config MACH_MX31_3DS select IMX_HAVE_PLATFORM_MXC_MMC select IMX_HAVE_PLATFORM_MXC_NAND select IMX_HAVE_PLATFORM_SPI_IMX + select MXC_DEBUG_BOARD select MXC_ULPI if USB_ULPI + select SOC_IMX31 help Include support for MX31PDK (3DS) platform. This includes specific configurations for the board and its peripherals. @@ -497,7 +497,6 @@ config MACH_MX31_3DS_MXC_NAND_USE_BBT config MACH_MX31MOBOARD bool "Support mx31moboard platforms (EPFL Mobots group)" - select SOC_IMX31 select IMX_HAVE_PLATFORM_FSL_USB2_UDC select IMX_HAVE_PLATFORM_IMX2_WDT select IMX_HAVE_PLATFORM_IMX_I2C @@ -509,22 +508,22 @@ config MACH_MX31MOBOARD select IMX_HAVE_PLATFORM_SPI_IMX select LEDS_GPIO_REGISTER select MXC_ULPI if USB_ULPI + select SOC_IMX31 help Include support for mx31moboard platform. This includes specific configurations for the board and its peripherals. config MACH_QONG bool "Support Dave/DENX QongEVB-LITE platform" - select SOC_IMX31 - select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_IMX2_WDT + select IMX_HAVE_PLATFORM_IMX_UART + select SOC_IMX31 help Include support for Dave/DENX QongEVB-LITE platform. This includes specific configurations for the board and its peripherals. config MACH_ARMADILLO5X0 bool "Support Atmark Armadillo-500 Development Base Board" - select SOC_IMX31 select IMX_HAVE_PLATFORM_GPIO_KEYS select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART @@ -533,23 +532,24 @@ config MACH_ARMADILLO5X0 select IMX_HAVE_PLATFORM_MXC_MMC select IMX_HAVE_PLATFORM_MXC_NAND select MXC_ULPI if USB_ULPI + select SOC_IMX31 help Include support for Atmark Armadillo-500 platform. This includes specific configurations for the board and its peripherals. config MACH_KZM_ARM11_01 bool "Support KZM-ARM11-01(Kyoto Microcomputer)" - select SOC_IMX31 select IMX_HAVE_PLATFORM_IMX_UART + select SOC_IMX31 help Include support for KZM-ARM11-01. This includes specific configurations for the board and its peripherals. config MACH_BUG bool "Support Buglabs BUGBase platform" - select SOC_IMX31 - select IMX_HAVE_PLATFORM_IMX_UART default y + select IMX_HAVE_PLATFORM_IMX_UART + select SOC_IMX31 help Include support for BUGBase 1.3 platform. This includes specific configurations for the board and its peripherals. @@ -565,7 +565,6 @@ comment "MX35 platforms:" config MACH_PCM043 bool "Support Phytec pcm043 (i.MX35) platforms" - select SOC_IMX35 select IMX_HAVE_PLATFORM_FLEXCAN select IMX_HAVE_PLATFORM_FSL_USB2_UDC select IMX_HAVE_PLATFORM_IMX2_WDT @@ -577,14 +576,13 @@ config MACH_PCM043 select IMX_HAVE_PLATFORM_MXC_NAND select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX select MXC_ULPI if USB_ULPI + select SOC_IMX35 help Include support for Phytec pcm043 platform. This includes specific configurations for the board and its peripherals. config MACH_MX35_3DS bool "Support MX35PDK platform" - select SOC_IMX35 - select MXC_DEBUG_BOARD select IMX_HAVE_PLATFORM_FSL_USB2_UDC select IMX_HAVE_PLATFORM_IMX2_WDT select IMX_HAVE_PLATFORM_IMX_FB @@ -595,13 +593,14 @@ config MACH_MX35_3DS select IMX_HAVE_PLATFORM_MXC_NAND select IMX_HAVE_PLATFORM_MXC_RTC select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX + select MXC_DEBUG_BOARD + select SOC_IMX35 help Include support for MX35PDK platform. This includes specific configurations for the board and its peripherals. config MACH_EUKREA_CPUIMX35SD bool "Support Eukrea CPUIMX35 Platform" - select SOC_IMX35 select IMX_HAVE_PLATFORM_FLEXCAN select IMX_HAVE_PLATFORM_FSL_USB2_UDC select IMX_HAVE_PLATFORM_IMX2_WDT @@ -611,6 +610,7 @@ config MACH_EUKREA_CPUIMX35SD select IMX_HAVE_PLATFORM_MXC_NAND select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX select MXC_ULPI if USB_ULPI + select SOC_IMX35 help Include support for Eukrea CPUIMX35 platform. This includes specific configurations for the board and its peripherals. @@ -635,16 +635,16 @@ endchoice config MACH_VPR200 bool "Support VPR200 platform" - select SOC_IMX35 select IMX_HAVE_PLATFORM_FSL_USB2_UDC select IMX_HAVE_PLATFORM_GPIO_KEYS select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_IPU_CORE select IMX_HAVE_PLATFORM_MXC_EHCI select IMX_HAVE_PLATFORM_MXC_NAND select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX + select SOC_IMX35 help Include support for VPR200 platform. This includes specific configurations for the board and its peripherals. @@ -654,11 +654,11 @@ comment "i.MX5 platforms:" config MACH_MX50_RDP bool "Support MX50 reference design platform" depends on BROKEN - select SOC_IMX50 select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX select IMX_HAVE_PLATFORM_SPI_IMX + select SOC_IMX50 help Include support for MX50 reference design platform (RDP) board. This includes specific configurations for the board and its peripherals. @@ -667,15 +667,14 @@ comment "i.MX51 machines:" config MACH_IMX51_DT bool "Support i.MX51 platforms from device tree" - select SOC_IMX51 select MACH_MX51_BABBAGE + select SOC_IMX51 help Include support for Freescale i.MX51 based platforms using the device tree for discovery config MACH_MX51_BABBAGE bool "Support MX51 BABBAGE platforms" - select SOC_IMX51 select IMX_HAVE_PLATFORM_FSL_USB2_UDC select IMX_HAVE_PLATFORM_IMX2_WDT select IMX_HAVE_PLATFORM_IMX_I2C @@ -683,6 +682,7 @@ config MACH_MX51_BABBAGE select IMX_HAVE_PLATFORM_MXC_EHCI select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX select IMX_HAVE_PLATFORM_SPI_IMX + select SOC_IMX51 help Include support for MX51 Babbage platform, also known as MX51EVK in u-boot. This includes specific configurations for the board and its @@ -690,27 +690,27 @@ config MACH_MX51_BABBAGE config MACH_MX51_3DS bool "Support MX51PDK (3DS)" - select SOC_IMX51 select IMX_HAVE_PLATFORM_IMX2_WDT select IMX_HAVE_PLATFORM_IMX_KEYPAD select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX select IMX_HAVE_PLATFORM_SPI_IMX select MXC_DEBUG_BOARD + select SOC_IMX51 help Include support for MX51PDK (3DS) platform. This includes specific configurations for the board and its peripherals. config MACH_EUKREA_CPUIMX51SD bool "Support Eukrea CPUIMX51SD module" - select SOC_IMX51 select IMX_HAVE_PLATFORM_FSL_USB2_UDC + select IMX_HAVE_PLATFORM_IMX2_WDT select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_IMX2_WDT select IMX_HAVE_PLATFORM_MXC_EHCI select IMX_HAVE_PLATFORM_MXC_NAND select IMX_HAVE_PLATFORM_SPI_IMX + select SOC_IMX51 help Include support for Eukrea CPUIMX51SD platform. This includes specific configurations for the module and its peripherals. @@ -736,12 +736,12 @@ comment "Device tree only" config SOC_IMX53 bool "i.MX53 support" - select SOC_IMX5 select ARCH_MX5 select ARCH_MX53 select HAVE_CAN_FLEXCAN if CAN select PINCTRL select PINCTRL_IMX53 + select SOC_IMX5 help This enables support for Freescale i.MX53 processor. @@ -758,7 +758,7 @@ config SOC_IMX6Q select HAVE_IMX_MMDC select HAVE_IMX_SRC select HAVE_SMP - select MFD_ANATOP + select MFD_SYSCON select PINCTRL select PINCTRL_IMX6Q diff --git a/arch/arm/mach-imx/clk-busy.c b/arch/arm/mach-imx/clk-busy.c index 1a7a8dd045a1..1ab91b5209e6 100644 --- a/arch/arm/mach-imx/clk-busy.c +++ b/arch/arm/mach-imx/clk-busy.c @@ -108,7 +108,7 @@ struct clk *imx_clk_busy_divider(const char *name, const char *parent_name, busy->div.hw.init = &init; clk = clk_register(NULL, &busy->div.hw); - if (!clk) + if (IS_ERR(clk)) kfree(busy); return clk; diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c index d20d4795f4ea..01e2f843bf2e 100644 --- a/arch/arm/mach-imx/clk-imx25.c +++ b/arch/arm/mach-imx/clk-imx25.c @@ -127,8 +127,8 @@ int __init mx25_clocks_init(void) clk[esdhc2_ipg_per] = imx_clk_gate("esdhc2_ipg_per", "per4", ccm(CCM_CGCR0), 4); clk[gpt_ipg_per] = imx_clk_gate("gpt_ipg_per", "per5", ccm(CCM_CGCR0), 5); clk[i2c_ipg_per] = imx_clk_gate("i2c_ipg_per", "per6", ccm(CCM_CGCR0), 6); - clk[lcdc_ipg_per] = imx_clk_gate("lcdc_ipg_per", "per8", ccm(CCM_CGCR0), 7); - clk[nfc_ipg_per] = imx_clk_gate("nfc_ipg_per", "ipg_per", ccm(CCM_CGCR0), 8); + clk[lcdc_ipg_per] = imx_clk_gate("lcdc_ipg_per", "per7", ccm(CCM_CGCR0), 7); + clk[nfc_ipg_per] = imx_clk_gate("nfc_ipg_per", "per8", ccm(CCM_CGCR0), 8); clk[ssi1_ipg_per] = imx_clk_gate("ssi1_ipg_per", "per13", ccm(CCM_CGCR0), 13); clk[ssi2_ipg_per] = imx_clk_gate("ssi2_ipg_per", "per14", ccm(CCM_CGCR0), 14); clk[uart_ipg_per] = imx_clk_gate("uart_ipg_per", "per15", ccm(CCM_CGCR0), 15); diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c index f69ca4680049..366e5d59d886 100644 --- a/arch/arm/mach-imx/clk-imx27.c +++ b/arch/arm/mach-imx/clk-imx27.c @@ -109,7 +109,7 @@ int __init mx27_clocks_init(unsigned long fref) clk[per3_div] = imx_clk_divider("per3_div", "mpll_main2", CCM_PCDR1, 16, 6); clk[per4_div] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6); clk[vpu_sel] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks)); - clk[vpu_div] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 3); + clk[vpu_div] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 6); clk[usb_div] = imx_clk_divider("usb_div", "spll", CCM_CSCR, 28, 3); clk[cpu_sel] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks)); clk[clko_sel] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks)); @@ -121,7 +121,7 @@ int __init mx27_clocks_init(unsigned long fref) clk[ssi1_sel] = imx_clk_mux("ssi1_sel", CCM_CSCR, 22, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks)); clk[ssi2_sel] = imx_clk_mux("ssi2_sel", CCM_CSCR, 23, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks)); clk[ssi1_div] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6); - clk[ssi2_div] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 3); + clk[ssi2_div] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6); clk[clko_en] = imx_clk_gate("clko_en", "clko_div", CCM_PCCR0, 0); clk[ssi2_ipg_gate] = imx_clk_gate("ssi2_ipg_gate", "ipg", CCM_PCCR0, 0); clk[ssi1_ipg_gate] = imx_clk_gate("ssi1_ipg_gate", "ipg", CCM_PCCR0, 1); @@ -239,8 +239,8 @@ int __init mx27_clocks_init(unsigned long fref) clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0"); clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1"); clk_register_clkdev(clk[nfc_baud_gate], NULL, "mxc_nand.0"); - clk_register_clkdev(clk[vpu_baud_gate], "per", "imx-vpu"); - clk_register_clkdev(clk[vpu_ahb_gate], "ahb", "imx-vpu"); + clk_register_clkdev(clk[vpu_baud_gate], "per", "coda-imx27.0"); + clk_register_clkdev(clk[vpu_ahb_gate], "ahb", "coda-imx27.0"); clk_register_clkdev(clk[dma_ahb_gate], "ahb", "imx-dma"); clk_register_clkdev(clk[dma_ipg_gate], "ipg", "imx-dma"); clk_register_clkdev(clk[fec_ipg_gate], "ipg", "imx27-fec.0"); diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c index e5165a84f93f..a0bf84803eac 100644 --- a/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/arch/arm/mach-imx/clk-imx51-imx53.c @@ -369,6 +369,7 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "83fcc000.ssi"); clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "70014000.ssi"); clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "83fe8000.ssi"); + clk_register_clkdev(clk[nfc_gate], NULL, "83fdb000.nand"); /* set the usboh3 parent to pll2_sw */ clk_set_parent(clk[usboh3_sel], clk[pll2_sw]); @@ -461,6 +462,7 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "63fcc000.ssi"); clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "50014000.ssi"); clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "63fd0000.ssi"); + clk_register_clkdev(clk[nfc_gate], NULL, "63fdb000.nand"); clk_register_clkdev(clk[can1_ipg_gate], "ipg", "53fc8000.can"); clk_register_clkdev(clk[can1_serial_gate], "per", "53fc8000.can"); clk_register_clkdev(clk[can2_ipg_gate], "ipg", "53fcc000.can"); diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h index 436c5720fe6a..04822932cdd1 100644 --- a/arch/arm/mach-imx/devices-imx27.h +++ b/arch/arm/mach-imx/devices-imx27.h @@ -17,6 +17,10 @@ extern const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data; #define imx27_add_fsl_usb2_udc(pdata) \ imx_add_fsl_usb2_udc(&imx27_fsl_usb2_udc_data, pdata) +extern const struct imx_imx27_coda_data imx27_coda_data; +#define imx27_add_coda() \ + imx_add_imx27_coda(&imx27_coda_data) + extern const struct imx_imx2_wdt_data imx27_imx2_wdt_data; #define imx27_add_imx2_wdt() \ imx_add_imx2_wdt(&imx27_imx2_wdt_data) diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c index fd3177f9e79a..98aef571b9f8 100644 --- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c +++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c @@ -348,4 +348,5 @@ void __init eukrea_mbimx27_baseboard_init(void) imx27_add_imx_keypad(&eukrea_mbimx27_keymap_data); gpio_led_register_device(-1, &eukrea_mbimx27_gpio_led_info); + imx_add_platform_device("eukrea_tlv320", 0, NULL, 0, NULL, 0); } diff --git a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c index dfd2da87c2df..0b84666792f0 100644 --- a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c +++ b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c @@ -306,4 +306,5 @@ void __init eukrea_mbimxsd25_baseboard_init(void) platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); gpio_led_register_device(-1, &eukrea_mbimxsd_led_info); imx_add_gpio_keys(&eukrea_mbimxsd_button_data); + imx_add_platform_device("eukrea_tlv320", 0, NULL, 0, NULL, 0); } diff --git a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c index 6e9dd12a6961..c6532a007d46 100644 --- a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c +++ b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c @@ -315,4 +315,5 @@ void __init eukrea_mbimxsd35_baseboard_init(void) platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); gpio_led_register_device(-1, &eukrea_mbimxsd_led_info); imx_add_gpio_keys(&eukrea_mbimxsd_button_data); + imx_add_platform_device("eukrea_tlv320", 0, NULL, 0, NULL, 0); } diff --git a/arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c index 96a24b73dc23..8b0de30d7a3f 100644 --- a/arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c +++ b/arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c @@ -228,4 +228,5 @@ void __init eukrea_mbimxsd51_baseboard_init(void) gpio_led_register_device(-1, &eukrea_mbimxsd51_led_info); imx_add_gpio_keys(&eukrea_mbimxsd51_button_data); + imx_add_platform_device("eukrea_tlv320", 0, NULL, 0, NULL, 0); } diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c index f264ddddd47c..141756f00ae5 100644 --- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c +++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c @@ -32,13 +32,14 @@ #include <linux/delay.h> #include <linux/dma-mapping.h> #include <linux/leds.h> -#include <linux/memblock.h> +#include <linux/platform_data/asoc-mx27vis.h> #include <media/soc_camera.h> #include <sound/tlv320aic32x4.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> #include <asm/system_info.h> +#include <asm/memblock.h> #include <mach/common.h> #include <mach/hardware.h> #include <mach/iomux-mx27.h> @@ -58,6 +59,11 @@ #define EXPBOARD_BIT1 (GPIO_PORTD + 27) #define EXPBOARD_BIT0 (GPIO_PORTD + 28) +#define AMP_GAIN_0 (GPIO_PORTF + 9) +#define AMP_GAIN_1 (GPIO_PORTF + 8) +#define AMP_MUTE_SDL (GPIO_PORTE + 5) +#define AMP_MUTE_SDR (GPIO_PORTF + 7) + static const int visstrim_m10_pins[] __initconst = { /* UART1 (console) */ PE12_PF_UART1_TXD, @@ -139,6 +145,11 @@ static const int visstrim_m10_pins[] __initconst = { EXPBOARD_BIT2 | GPIO_GPIO | GPIO_IN | GPIO_PUEN, EXPBOARD_BIT1 | GPIO_GPIO | GPIO_IN | GPIO_PUEN, EXPBOARD_BIT0 | GPIO_GPIO | GPIO_IN | GPIO_PUEN, + /* Audio AMP control */ + AMP_GAIN_0 | GPIO_GPIO | GPIO_OUT, + AMP_GAIN_1 | GPIO_GPIO | GPIO_OUT, + AMP_MUTE_SDL | GPIO_GPIO | GPIO_OUT, + AMP_MUTE_SDR | GPIO_GPIO | GPIO_OUT, }; static struct gpio visstrim_m10_version_gpios[] = { @@ -166,6 +177,26 @@ static const struct gpio visstrim_m10_gpios[] __initconst = { .flags = GPIOF_DIR_OUT | GPIOF_INIT_LOW, .label = "usbotg_cs", }, + { + .gpio = AMP_GAIN_0, + .flags = GPIOF_DIR_OUT, + .label = "amp-gain-0", + }, + { + .gpio = AMP_GAIN_1, + .flags = GPIOF_DIR_OUT, + .label = "amp-gain-1", + }, + { + .gpio = AMP_MUTE_SDL, + .flags = GPIOF_DIR_OUT, + .label = "amp-mute-sdl", + }, + { + .gpio = AMP_MUTE_SDR, + .flags = GPIOF_DIR_OUT, + .label = "amp-mute-sdr", + }, }; /* Camera */ @@ -233,10 +264,8 @@ static void __init visstrim_camera_init(void) static void __init visstrim_reserve(void) { /* reserve 4 MiB for mx2-camera */ - mx2_camera_base = memblock_alloc(MX2_CAMERA_BUF_SIZE, + mx2_camera_base = arm_memblock_steal(3 * MX2_CAMERA_BUF_SIZE, MX2_CAMERA_BUF_SIZE); - memblock_free(mx2_camera_base, MX2_CAMERA_BUF_SIZE); - memblock_remove(mx2_camera_base, MX2_CAMERA_BUF_SIZE); } /* GPIOs used as events for applications */ @@ -405,6 +434,55 @@ static const struct imx_ssi_platform_data visstrim_m10_ssi_pdata __initconst = { .flags = IMX_SSI_DMA | IMX_SSI_SYN, }; +/* coda */ + +static void __init visstrim_coda_init(void) +{ + struct platform_device *pdev; + int dma; + + pdev = imx27_add_coda(); + dma = dma_declare_coherent_memory(&pdev->dev, + mx2_camera_base + MX2_CAMERA_BUF_SIZE, + mx2_camera_base + MX2_CAMERA_BUF_SIZE, + MX2_CAMERA_BUF_SIZE, + DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE); + if (!(dma & DMA_MEMORY_MAP)) + return; +} + +/* DMA deinterlace */ +static struct platform_device visstrim_deinterlace = { + .name = "m2m-deinterlace", + .id = 0, +}; + +static void __init visstrim_deinterlace_init(void) +{ + int ret = -ENOMEM; + struct platform_device *pdev = &visstrim_deinterlace; + int dma; + + ret = platform_device_register(pdev); + + dma = dma_declare_coherent_memory(&pdev->dev, + mx2_camera_base + 2 * MX2_CAMERA_BUF_SIZE, + mx2_camera_base + 2 * MX2_CAMERA_BUF_SIZE, + MX2_CAMERA_BUF_SIZE, + DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE); + if (!(dma & DMA_MEMORY_MAP)) + return; +} + + +/* Audio */ +static const struct snd_mx27vis_platform_data snd_mx27vis_pdata __initconst = { + .amp_gain0_gpio = AMP_GAIN_0, + .amp_gain1_gpio = AMP_GAIN_1, + .amp_mutel_gpio = AMP_MUTE_SDL, + .amp_muter_gpio = AMP_MUTE_SDR, +}; + static void __init visstrim_m10_revision(void) { int exp_version = 0; @@ -463,11 +541,14 @@ static void __init visstrim_m10_board_init(void) imx27_add_fec(NULL); imx_add_gpio_keys(&visstrim_gpio_keys_platform_data); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); - imx_add_platform_device("mx27vis", 0, NULL, 0, NULL, 0); + imx_add_platform_device("mx27vis", 0, NULL, 0, &snd_mx27vis_pdata, + sizeof(snd_mx27vis_pdata)); platform_device_register_resndata(NULL, "soc-camera-pdrv", 0, NULL, 0, &iclink_tvp5150, sizeof(iclink_tvp5150)); gpio_led_register_device(0, &visstrim_m10_led_data); + visstrim_deinterlace_init(); visstrim_camera_init(); + visstrim_coda_init(); } static void __init visstrim_m10_timer_init(void) diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 36979d3dfe34..47c91f7185d2 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -23,8 +23,9 @@ #include <linux/of_irq.h> #include <linux/of_platform.h> #include <linux/phy.h> +#include <linux/regmap.h> #include <linux/micrel_phy.h> -#include <linux/mfd/anatop.h> +#include <linux/mfd/syscon.h> #include <asm/cpuidle.h> #include <asm/smp_twd.h> #include <asm/hardware/cache-l2x0.h> @@ -118,20 +119,7 @@ static void __init imx6q_sabrelite_init(void) static void __init imx6q_usb_init(void) { - struct device_node *np; - struct platform_device *pdev = NULL; - struct anatop *adata = NULL; - - np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); - if (np) - pdev = of_find_device_by_node(np); - if (pdev) - adata = platform_get_drvdata(pdev); - if (!adata) { - if (np) - of_node_put(np); - return; - } + struct regmap *anatop; #define HW_ANADIG_USB1_CHRG_DETECT 0x000001b0 #define HW_ANADIG_USB2_CHRG_DETECT 0x00000210 @@ -139,20 +127,21 @@ static void __init imx6q_usb_init(void) #define BM_ANADIG_USB_CHRG_DETECT_EN_B 0x00100000 #define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B 0x00080000 - /* - * The external charger detector needs to be disabled, - * or the signal at DP will be poor - */ - anatop_write_reg(adata, HW_ANADIG_USB1_CHRG_DETECT, - BM_ANADIG_USB_CHRG_DETECT_EN_B - | BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B, - ~0); - anatop_write_reg(adata, HW_ANADIG_USB2_CHRG_DETECT, - BM_ANADIG_USB_CHRG_DETECT_EN_B | - BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B, - ~0); - - of_node_put(np); + anatop = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop"); + if (!IS_ERR(anatop)) { + /* + * The external charger detector needs to be disabled, + * or the signal at DP will be poor + */ + regmap_write(anatop, HW_ANADIG_USB1_CHRG_DETECT, + BM_ANADIG_USB_CHRG_DETECT_EN_B + | BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B); + regmap_write(anatop, HW_ANADIG_USB2_CHRG_DETECT, + BM_ANADIG_USB_CHRG_DETECT_EN_B | + BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B); + } else { + pr_warn("failed to find fsl,imx6q-anatop regmap\n"); + } } static void __init imx6q_init_machine(void) diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c index 9d2c843bde02..b5deb0554552 100644 --- a/arch/arm/mach-imx/mm-imx3.c +++ b/arch/arm/mach-imx/mm-imx3.c @@ -108,9 +108,8 @@ void __init imx3_init_l2x0(void) } l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096); - if (IS_ERR(l2x0_base)) { - printk(KERN_ERR "remapping L2 cache area failed with %ld\n", - PTR_ERR(l2x0_base)); + if (!l2x0_base) { + printk(KERN_ERR "remapping L2 cache area failed\n"); return; } diff --git a/arch/arm/mach-integrator/common.h b/arch/arm/mach-integrator/common.h index 899561d8db28..c3ff21b5ea24 100644 --- a/arch/arm/mach-integrator/common.h +++ b/arch/arm/mach-integrator/common.h @@ -1,3 +1,6 @@ +#include <linux/amba/serial.h> +extern struct amba_pl010_data integrator_uart_data; void integrator_init_early(void); +int integrator_init(bool is_cp); void integrator_reserve(void); void integrator_restart(char, const char *); diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c index dad3cb74ed31..ea22a17246d7 100644 --- a/arch/arm/mach-integrator/core.c +++ b/arch/arm/mach-integrator/core.c @@ -32,7 +32,9 @@ #include <asm/mach/time.h> #include <asm/pgtable.h> -static struct amba_pl010_data integrator_uart_data; +#include "common.h" + +#ifdef CONFIG_ATAGS #define INTEGRATOR_RTC_IRQ { IRQ_RTCINT } #define INTEGRATOR_UART0_IRQ { IRQ_UARTINT0 } @@ -60,7 +62,7 @@ static struct amba_device *amba_devs[] __initdata = { &kmi1_device, }; -static int __init integrator_init(void) +int __init integrator_init(bool is_cp) { int i; @@ -69,7 +71,7 @@ static int __init integrator_init(void) * hard-code them. The Integator/CP and forward have proper cell IDs. * Else we leave them undefined to the bus driver can autoprobe them. */ - if (machine_is_integrator()) { + if (!is_cp) { rtc_device.periphid = 0x00041030; uart0_device.periphid = 0x00041010; uart1_device.periphid = 0x00041010; @@ -85,7 +87,7 @@ static int __init integrator_init(void) return 0; } -arch_initcall(integrator_init); +#endif /* * On the Integrator platform, the port RTS and DTR are provided by @@ -100,11 +102,14 @@ arch_initcall(integrator_init); static void integrator_uart_set_mctrl(struct amba_device *dev, void __iomem *base, unsigned int mctrl) { unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask; + u32 phybase = dev->res.start; - if (dev == &uart0_device) { + if (phybase == INTEGRATOR_UART0_BASE) { + /* UART0 */ rts_mask = 1 << 4; dtr_mask = 1 << 5; } else { + /* UART1 */ rts_mask = 1 << 6; dtr_mask = 1 << 7; } @@ -123,7 +128,7 @@ static void integrator_uart_set_mctrl(struct amba_device *dev, void __iomem *bas __raw_writel(ctrlc, SC_CTRLC); } -static struct amba_pl010_data integrator_uart_data = { +struct amba_pl010_data integrator_uart_data = { .set_mctrl = integrator_uart_set_mctrl, }; diff --git a/arch/arm/mach-integrator/include/mach/cm.h b/arch/arm/mach-integrator/include/mach/cm.h index 1a78692e32a4..202e6a57f100 100644 --- a/arch/arm/mach-integrator/include/mach/cm.h +++ b/arch/arm/mach-integrator/include/mach/cm.h @@ -3,7 +3,7 @@ */ void cm_control(u32, u32); -#define CM_CTRL IO_ADDRESS(INTEGRATOR_HDR_CTRL) +#define CM_CTRL __io_address(INTEGRATOR_HDR_CTRL) #define CM_CTRL_LED (1 << 0) #define CM_CTRL_nMBDET (1 << 1) diff --git a/arch/arm/mach-integrator/include/mach/platform.h b/arch/arm/mach-integrator/include/mach/platform.h index 4c0347526851..efeac5d0bc9e 100644 --- a/arch/arm/mach-integrator/include/mach/platform.h +++ b/arch/arm/mach-integrator/include/mach/platform.h @@ -324,9 +324,9 @@ */ #define PHYS_PCI_V3_BASE 0x62000000 -#define PCI_MEMORY_VADDR 0xe8000000 -#define PCI_CONFIG_VADDR 0xec000000 -#define PCI_V3_VADDR 0xed000000 +#define PCI_MEMORY_VADDR IOMEM(0xe8000000) +#define PCI_CONFIG_VADDR IOMEM(0xec000000) +#define PCI_V3_VADDR IOMEM(0xed000000) /* ------------------------------------------------------------------------ * Integrator Interrupt Controllers diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c index 2215d96cd735..e6617c134faf 100644 --- a/arch/arm/mach-integrator/integrator_ap.c +++ b/arch/arm/mach-integrator/integrator_ap.c @@ -34,6 +34,9 @@ #include <linux/mtd/physmap.h> #include <linux/clk.h> #include <linux/platform_data/clk-integrator.h> +#include <linux/of_irq.h> +#include <linux/of_address.h> +#include <linux/of_platform.h> #include <video/vga.h> #include <mach/hardware.h> @@ -154,27 +157,10 @@ static struct map_desc ap_io_desc[] __initdata = { static void __init ap_map_io(void) { iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc)); - vga_base = PCI_MEMORY_VADDR; + vga_base = (unsigned long)PCI_MEMORY_VADDR; pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE)); } -#define INTEGRATOR_SC_VALID_INT 0x003fffff - -static void __init ap_init_irq(void) -{ - /* Disable all interrupts initially. */ - /* Do the core module ones */ - writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR); - - /* do the header card stuff next */ - writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR); - writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR); - - fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START, - -1, INTEGRATOR_SC_VALID_INT, NULL); - integrator_clk_init(false); -} - #ifdef CONFIG_PM static unsigned long ic_irq_enable; @@ -267,50 +253,6 @@ static struct physmap_flash_data ap_flash_data = { .set_vpp = ap_flash_set_vpp, }; -static struct resource cfi_flash_resource = { - .start = INTEGRATOR_FLASH_BASE, - .end = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device cfi_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &ap_flash_data, - }, - .num_resources = 1, - .resource = &cfi_flash_resource, -}; - -static void __init ap_init(void) -{ - unsigned long sc_dec; - int i; - - platform_device_register(&cfi_flash_device); - - sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET); - for (i = 0; i < 4; i++) { - struct lm_device *lmdev; - - if ((sc_dec & (16 << i)) == 0) - continue; - - lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL); - if (!lmdev) - continue; - - lmdev->resource.start = 0xc0000000 + 0x10000000 * i; - lmdev->resource.end = lmdev->resource.start + 0x0fffffff; - lmdev->resource.flags = IORESOURCE_MEM; - lmdev->irq = IRQ_AP_EXPINT0 + i; - lmdev->id = i; - - lm_device_register(lmdev); - } -} - /* * Where is the timer (VA)? */ @@ -325,9 +267,9 @@ static u32 notrace integrator_read_sched_clock(void) return -readl((void __iomem *) TIMER2_VA_BASE + TIMER_VALUE); } -static void integrator_clocksource_init(unsigned long inrate) +static void integrator_clocksource_init(unsigned long inrate, + void __iomem *base) { - void __iomem *base = (void __iomem *)TIMER2_VA_BASE; u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC; unsigned long rate = inrate; @@ -344,7 +286,7 @@ static void integrator_clocksource_init(unsigned long inrate) setup_sched_clock(integrator_read_sched_clock, 16, rate); } -static void __iomem * const clkevt_base = (void __iomem *)TIMER1_VA_BASE; +static void __iomem * clkevt_base; /* * IRQ handler for the timer @@ -416,11 +358,13 @@ static struct irqaction integrator_timer_irq = { .dev_id = &integrator_clockevent, }; -static void integrator_clockevent_init(unsigned long inrate) +static void integrator_clockevent_init(unsigned long inrate, + void __iomem *base, int irq) { unsigned long rate = inrate; unsigned int ctrl = 0; + clkevt_base = base; /* Calculate and program a divisor */ if (rate > 0x100000 * HZ) { rate /= 256; @@ -432,7 +376,7 @@ static void integrator_clockevent_init(unsigned long inrate) timer_reload = rate / HZ; writel(ctrl, clkevt_base + TIMER_CTRL); - setup_irq(IRQ_TIMERINT1, &integrator_timer_irq); + setup_irq(irq, &integrator_timer_irq); clockevents_config_and_register(&integrator_clockevent, rate, 1, @@ -443,9 +387,153 @@ void __init ap_init_early(void) { } +#ifdef CONFIG_OF + +static void __init ap_init_timer_of(void) +{ + struct device_node *node; + const char *path; + void __iomem *base; + int err; + int irq; + struct clk *clk; + unsigned long rate; + + clk = clk_get_sys("ap_timer", NULL); + BUG_ON(IS_ERR(clk)); + clk_prepare_enable(clk); + rate = clk_get_rate(clk); + + err = of_property_read_string(of_aliases, + "arm,timer-primary", &path); + if (WARN_ON(err)) + return; + node = of_find_node_by_path(path); + base = of_iomap(node, 0); + if (WARN_ON(!base)) + return; + writel(0, base + TIMER_CTRL); + integrator_clocksource_init(rate, base); + + err = of_property_read_string(of_aliases, + "arm,timer-secondary", &path); + if (WARN_ON(err)) + return; + node = of_find_node_by_path(path); + base = of_iomap(node, 0); + if (WARN_ON(!base)) + return; + irq = irq_of_parse_and_map(node, 0); + writel(0, base + TIMER_CTRL); + integrator_clockevent_init(rate, base, irq); +} + +static struct sys_timer ap_of_timer = { + .init = ap_init_timer_of, +}; + +static const struct of_device_id fpga_irq_of_match[] __initconst = { + { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, }, + { /* Sentinel */ } +}; + +static void __init ap_init_irq_of(void) +{ + /* disable core module IRQs */ + writel(0xffffffffU, VA_CMIC_BASE + IRQ_ENABLE_CLEAR); + of_irq_init(fpga_irq_of_match); + integrator_clk_init(false); +} + +/* For the Device Tree, add in the UART callbacks as AUXDATA */ +static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = { + OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE, + "rtc", NULL), + OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE, + "uart0", &integrator_uart_data), + OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE, + "uart1", &integrator_uart_data), + OF_DEV_AUXDATA("arm,primecell", KMI0_BASE, + "kmi0", NULL), + OF_DEV_AUXDATA("arm,primecell", KMI1_BASE, + "kmi1", NULL), + OF_DEV_AUXDATA("cfi-flash", INTEGRATOR_FLASH_BASE, + "physmap-flash", &ap_flash_data), + { /* sentinel */ }, +}; + +static void __init ap_init_of(void) +{ + unsigned long sc_dec; + int i; + + of_platform_populate(NULL, of_default_bus_match_table, + ap_auxdata_lookup, NULL); + + sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET); + for (i = 0; i < 4; i++) { + struct lm_device *lmdev; + + if ((sc_dec & (16 << i)) == 0) + continue; + + lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL); + if (!lmdev) + continue; + + lmdev->resource.start = 0xc0000000 + 0x10000000 * i; + lmdev->resource.end = lmdev->resource.start + 0x0fffffff; + lmdev->resource.flags = IORESOURCE_MEM; + lmdev->irq = IRQ_AP_EXPINT0 + i; + lmdev->id = i; + + lm_device_register(lmdev); + } +} + +static const char * ap_dt_board_compat[] = { + "arm,integrator-ap", + NULL, +}; + +DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)") + .reserve = integrator_reserve, + .map_io = ap_map_io, + .nr_irqs = NR_IRQS_INTEGRATOR_AP, + .init_early = ap_init_early, + .init_irq = ap_init_irq_of, + .handle_irq = fpga_handle_irq, + .timer = &ap_of_timer, + .init_machine = ap_init_of, + .restart = integrator_restart, + .dt_compat = ap_dt_board_compat, +MACHINE_END + +#endif + +#ifdef CONFIG_ATAGS + /* - * Set up timer(s). + * This is where non-devicetree initialization code is collected and stashed + * for eventual deletion. */ + +static struct resource cfi_flash_resource = { + .start = INTEGRATOR_FLASH_BASE, + .end = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device cfi_flash_device = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &ap_flash_data, + }, + .num_resources = 1, + .resource = &cfi_flash_resource, +}; + static void __init ap_init_timer(void) { struct clk *clk; @@ -460,14 +548,62 @@ static void __init ap_init_timer(void) writel(0, TIMER1_VA_BASE + TIMER_CTRL); writel(0, TIMER2_VA_BASE + TIMER_CTRL); - integrator_clocksource_init(rate); - integrator_clockevent_init(rate); + integrator_clocksource_init(rate, (void __iomem *)TIMER2_VA_BASE); + integrator_clockevent_init(rate, (void __iomem *)TIMER1_VA_BASE, + IRQ_TIMERINT1); } static struct sys_timer ap_timer = { .init = ap_init_timer, }; +#define INTEGRATOR_SC_VALID_INT 0x003fffff + +static void __init ap_init_irq(void) +{ + /* Disable all interrupts initially. */ + /* Do the core module ones */ + writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR); + + /* do the header card stuff next */ + writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR); + writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR); + + fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START, + -1, INTEGRATOR_SC_VALID_INT, NULL); + integrator_clk_init(false); +} + +static void __init ap_init(void) +{ + unsigned long sc_dec; + int i; + + platform_device_register(&cfi_flash_device); + + sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET); + for (i = 0; i < 4; i++) { + struct lm_device *lmdev; + + if ((sc_dec & (16 << i)) == 0) + continue; + + lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL); + if (!lmdev) + continue; + + lmdev->resource.start = 0xc0000000 + 0x10000000 * i; + lmdev->resource.end = lmdev->resource.start + 0x0fffffff; + lmdev->resource.flags = IORESOURCE_MEM; + lmdev->irq = IRQ_AP_EXPINT0 + i; + lmdev->id = i; + + lm_device_register(lmdev); + } + + integrator_init(false); +} + MACHINE_START(INTEGRATOR, "ARM-Integrator") /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ .atag_offset = 0x100, @@ -481,3 +617,5 @@ MACHINE_START(INTEGRATOR, "ARM-Integrator") .init_machine = ap_init, .restart = integrator_restart, MACHINE_END + +#endif diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c index 3df5fc369361..5b08e8e4cc83 100644 --- a/arch/arm/mach-integrator/integrator_cp.c +++ b/arch/arm/mach-integrator/integrator_cp.c @@ -23,6 +23,9 @@ #include <linux/gfp.h> #include <linux/mtd/physmap.h> #include <linux/platform_data/clk-integrator.h> +#include <linux/of_irq.h> +#include <linux/of_address.h> +#include <linux/of_platform.h> #include <mach/hardware.h> #include <mach/platform.h> @@ -49,16 +52,9 @@ #include "common.h" #define INTCP_PA_FLASH_BASE 0x24000000 -#define INTCP_FLASH_SIZE SZ_32M #define INTCP_PA_CLCD_BASE 0xc0000000 -#define INTCP_VA_CIC_BASE __io_address(INTEGRATOR_HDR_BASE + 0x40) -#define INTCP_VA_PIC_BASE __io_address(INTEGRATOR_IC_BASE) -#define INTCP_VA_SIC_BASE __io_address(INTEGRATOR_CP_SIC_BASE) - -#define INTCP_ETH_SIZE 0x10 - #define INTCP_VA_CTRL_BASE __io_address(INTEGRATOR_CP_CTL_BASE) #define INTCP_FLASHPROG 0x04 #define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0) @@ -143,37 +139,6 @@ static void __init intcp_map_io(void) iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc)); } -static void __init intcp_init_irq(void) -{ - u32 pic_mask, cic_mask, sic_mask; - - /* These masks are for the HW IRQ registers */ - pic_mask = ~((~0u) << (11 - IRQ_PIC_START)); - pic_mask |= (~((~0u) << (29 - 22))) << 22; - cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START)); - sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START)); - - /* - * Disable all interrupt sources - */ - writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR); - writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR); - writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR); - writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR); - writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR); - writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR); - - fpga_irq_init(INTCP_VA_PIC_BASE, "PIC", IRQ_PIC_START, - -1, pic_mask, NULL); - - fpga_irq_init(INTCP_VA_CIC_BASE, "CIC", IRQ_CIC_START, - -1, cic_mask, NULL); - - fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START, - IRQ_CP_CPPLDINT, sic_mask, NULL); - integrator_clk_init(true); -} - /* * Flash handling. */ @@ -216,47 +181,6 @@ static struct physmap_flash_data intcp_flash_data = { .set_vpp = intcp_flash_set_vpp, }; -static struct resource intcp_flash_resource = { - .start = INTCP_PA_FLASH_BASE, - .end = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device intcp_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &intcp_flash_data, - }, - .num_resources = 1, - .resource = &intcp_flash_resource, -}; - -static struct resource smc91x_resources[] = { - [0] = { - .start = INTEGRATOR_CP_ETH_BASE, - .end = INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_CP_ETHINT, - .end = IRQ_CP_ETHINT, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device smc91x_device = { - .name = "smc91x", - .id = 0, - .num_resources = ARRAY_SIZE(smc91x_resources), - .resource = smc91x_resources, -}; - -static struct platform_device *intcp_devs[] __initdata = { - &intcp_flash_device, - &smc91x_device, -}; - /* * It seems that the card insertion interrupt remains active after * we've acknowledged it. We therefore ignore the interrupt, and @@ -278,16 +202,6 @@ static struct mmci_platform_data mmc_data = { .gpio_cd = -1, }; -#define INTEGRATOR_CP_MMC_IRQS { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 } -#define INTEGRATOR_CP_AACI_IRQS { IRQ_CP_AACIINT } - -static AMBA_APB_DEVICE(mmc, "mmci", 0, INTEGRATOR_CP_MMC_BASE, - INTEGRATOR_CP_MMC_IRQS, &mmc_data); - -static AMBA_APB_DEVICE(aaci, "aaci", 0, INTEGRATOR_CP_AACI_BASE, - INTEGRATOR_CP_AACI_IRQS, NULL); - - /* * CLCD support */ @@ -338,15 +252,6 @@ static struct clcd_board clcd_data = { .remove = versatile_clcd_remove_dma, }; -static AMBA_AHB_DEVICE(clcd, "clcd", 0, INTCP_PA_CLCD_BASE, - { IRQ_CP_CLCDCINT }, &clcd_data); - -static struct amba_device *amba_devs[] __initdata = { - &mmc_device, - &aaci_device, - &clcd_device, -}; - #define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28) static void __init intcp_init_early(void) @@ -356,16 +261,193 @@ static void __init intcp_init_early(void) #endif } -static void __init intcp_init(void) +#ifdef CONFIG_OF + +static void __init intcp_timer_init_of(void) { - int i; + struct device_node *node; + const char *path; + void __iomem *base; + int err; + int irq; + + err = of_property_read_string(of_aliases, + "arm,timer-primary", &path); + if (WARN_ON(err)) + return; + node = of_find_node_by_path(path); + base = of_iomap(node, 0); + if (WARN_ON(!base)) + return; + writel(0, base + TIMER_CTRL); + sp804_clocksource_init(base, node->name); + + err = of_property_read_string(of_aliases, + "arm,timer-secondary", &path); + if (WARN_ON(err)) + return; + node = of_find_node_by_path(path); + base = of_iomap(node, 0); + if (WARN_ON(!base)) + return; + irq = irq_of_parse_and_map(node, 0); + writel(0, base + TIMER_CTRL); + sp804_clockevents_init(base, irq, node->name); +} - platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs)); +static struct sys_timer cp_of_timer = { + .init = intcp_timer_init_of, +}; - for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { - struct amba_device *d = amba_devs[i]; - amba_device_register(d, &iomem_resource); - } +static const struct of_device_id fpga_irq_of_match[] __initconst = { + { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, }, + { /* Sentinel */ } +}; + +static void __init intcp_init_irq_of(void) +{ + of_irq_init(fpga_irq_of_match); + integrator_clk_init(true); +} + +/* + * For the Device Tree, add in the UART, MMC and CLCD specifics as AUXDATA + * and enforce the bus names since these are used for clock lookups. + */ +static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = { + OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE, + "rtc", NULL), + OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE, + "uart0", &integrator_uart_data), + OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE, + "uart1", &integrator_uart_data), + OF_DEV_AUXDATA("arm,primecell", KMI0_BASE, + "kmi0", NULL), + OF_DEV_AUXDATA("arm,primecell", KMI1_BASE, + "kmi1", NULL), + OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_MMC_BASE, + "mmci", &mmc_data), + OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_AACI_BASE, + "aaci", &mmc_data), + OF_DEV_AUXDATA("arm,primecell", INTCP_PA_CLCD_BASE, + "clcd", &clcd_data), + OF_DEV_AUXDATA("cfi-flash", INTCP_PA_FLASH_BASE, + "physmap-flash", &intcp_flash_data), + { /* sentinel */ }, +}; + +static void __init intcp_init_of(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, + intcp_auxdata_lookup, NULL); +} + +static const char * intcp_dt_board_compat[] = { + "arm,integrator-cp", + NULL, +}; + +DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)") + .reserve = integrator_reserve, + .map_io = intcp_map_io, + .nr_irqs = NR_IRQS_INTEGRATOR_CP, + .init_early = intcp_init_early, + .init_irq = intcp_init_irq_of, + .handle_irq = fpga_handle_irq, + .timer = &cp_of_timer, + .init_machine = intcp_init_of, + .restart = integrator_restart, + .dt_compat = intcp_dt_board_compat, +MACHINE_END + +#endif + +#ifdef CONFIG_ATAGS + +/* + * This is where non-devicetree initialization code is collected and stashed + * for eventual deletion. + */ + +#define INTCP_FLASH_SIZE SZ_32M + +static struct resource intcp_flash_resource = { + .start = INTCP_PA_FLASH_BASE, + .end = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device intcp_flash_device = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &intcp_flash_data, + }, + .num_resources = 1, + .resource = &intcp_flash_resource, +}; + +#define INTCP_ETH_SIZE 0x10 + +static struct resource smc91x_resources[] = { + [0] = { + .start = INTEGRATOR_CP_ETH_BASE, + .end = INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_CP_ETHINT, + .end = IRQ_CP_ETHINT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device smc91x_device = { + .name = "smc91x", + .id = 0, + .num_resources = ARRAY_SIZE(smc91x_resources), + .resource = smc91x_resources, +}; + +static struct platform_device *intcp_devs[] __initdata = { + &intcp_flash_device, + &smc91x_device, +}; + +#define INTCP_VA_CIC_BASE __io_address(INTEGRATOR_HDR_BASE + 0x40) +#define INTCP_VA_PIC_BASE __io_address(INTEGRATOR_IC_BASE) +#define INTCP_VA_SIC_BASE __io_address(INTEGRATOR_CP_SIC_BASE) + +static void __init intcp_init_irq(void) +{ + u32 pic_mask, cic_mask, sic_mask; + + /* These masks are for the HW IRQ registers */ + pic_mask = ~((~0u) << (11 - IRQ_PIC_START)); + pic_mask |= (~((~0u) << (29 - 22))) << 22; + cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START)); + sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START)); + + /* + * Disable all interrupt sources + */ + writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR); + writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR); + writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR); + writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR); + writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR); + writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR); + + fpga_irq_init(INTCP_VA_PIC_BASE, "PIC", IRQ_PIC_START, + -1, pic_mask, NULL); + + fpga_irq_init(INTCP_VA_CIC_BASE, "CIC", IRQ_CIC_START, + -1, cic_mask, NULL); + + fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START, + IRQ_CP_CPPLDINT, sic_mask, NULL); + + integrator_clk_init(true); } #define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE) @@ -386,6 +468,37 @@ static struct sys_timer cp_timer = { .init = intcp_timer_init, }; +#define INTEGRATOR_CP_MMC_IRQS { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 } +#define INTEGRATOR_CP_AACI_IRQS { IRQ_CP_AACIINT } + +static AMBA_APB_DEVICE(mmc, "mmci", 0, INTEGRATOR_CP_MMC_BASE, + INTEGRATOR_CP_MMC_IRQS, &mmc_data); + +static AMBA_APB_DEVICE(aaci, "aaci", 0, INTEGRATOR_CP_AACI_BASE, + INTEGRATOR_CP_AACI_IRQS, NULL); + +static AMBA_AHB_DEVICE(clcd, "clcd", 0, INTCP_PA_CLCD_BASE, + { IRQ_CP_CLCDCINT }, &clcd_data); + +static struct amba_device *amba_devs[] __initdata = { + &mmc_device, + &aaci_device, + &clcd_device, +}; + +static void __init intcp_init(void) +{ + int i; + + platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs)); + + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { + struct amba_device *d = amba_devs[i]; + amba_device_register(d, &iomem_resource); + } + integrator_init(true); +} + MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP") /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ .atag_offset = 0x100, @@ -399,3 +512,5 @@ MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP") .init_machine = intcp_init, .restart = integrator_restart, MACHINE_END + +#endif diff --git a/arch/arm/mach-iop13xx/iq81340sc.c b/arch/arm/mach-iop13xx/iq81340sc.c index 060cddde2fd4..e94744111634 100644 --- a/arch/arm/mach-iop13xx/iq81340sc.c +++ b/arch/arm/mach-iop13xx/iq81340sc.c @@ -30,7 +30,7 @@ extern int init_atu; static int __init -iq81340sc_atux_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) +iq81340sc_atux_map_irq(const struct pci_dev *dev, u8 idsel, u8 pin) { WARN_ON(idsel < 1 || idsel > 2); diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c index 9082b84aeebb..2f28018c4447 100644 --- a/arch/arm/mach-iop13xx/pci.c +++ b/arch/arm/mach-iop13xx/pci.c @@ -504,7 +504,7 @@ iop13xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs) /* Scan an IOP13XX PCI bus. nr selects which ATU we use. */ -struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *sys) +struct pci_bus * __devinit iop13xx_scan_bus(int nr, struct pci_sys_data *sys) { int which_atu; struct pci_bus *bus = NULL; diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig index fd5e7b6881bf..73a2d905af8a 100644 --- a/arch/arm/mach-ixp4xx/Kconfig +++ b/arch/arm/mach-ixp4xx/Kconfig @@ -234,8 +234,8 @@ config IXP4XX_QMGR config IXP4XX_NPE tristate "IXP4xx Network Processor Engine support" - select HOTPLUG select FW_LOADER + select HOTPLUG help This driver supports IXP4xx built-in network coprocessors and is automatically selected by Ethernet and HSS drivers. diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index ca5c15a4e626..50bca5032b7e 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -94,6 +94,13 @@ config MACH_TS219_DT or MV6282. If you have the wrong one, the buttons will not work. +config MACH_DOCKSTAR_DT + bool "Seagate FreeAgent Dockstar (Flattened Device Tree)" + select ARCH_KIRKWOOD_DT + help + Say 'Y' here if you want your kernel to support the + Seagate FreeAgent Dockstar (Flattened Device Tree). + config MACH_GOFLEXNET_DT bool "Seagate GoFlex Net (Flattened Device Tree)" select ARCH_KIRKWOOD_DT @@ -109,6 +116,20 @@ config MACH_LSXL_DT Buffalo Linkstation LS-XHL & LS-CHLv2 devices, using Flattened Device Tree. +config MACH_IOMEGA_IX2_200_DT + bool "Iomega StorCenter ix2-200 (Flattened Device Tree)" + select ARCH_KIRKWOOD_DT + help + Say 'Y' here if you want your kernel to support the + Iomega StorCenter ix2-200 (Flattened Device Tree). + +config MACH_KM_KIRKWOOD_DT + bool "Keymile Kirkwood Reference Design (Flattened Device Tree)" + select ARCH_KIRKWOOD_DT + help + Say 'Y' here if you want your kernel to support the + Keymile Kirkwood Reference Desgin, using Flattened Device Tree. + config MACH_TS219 bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS" help diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile index 055c85a1cc46..294779f892d9 100644 --- a/arch/arm/mach-kirkwood/Makefile +++ b/arch/arm/mach-kirkwood/Makefile @@ -26,5 +26,8 @@ obj-$(CONFIG_MACH_ICONNECT_DT) += board-iconnect.o obj-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += board-dnskw.o obj-$(CONFIG_MACH_IB62X0_DT) += board-ib62x0.o obj-$(CONFIG_MACH_TS219_DT) += board-ts219.o tsx1x-common.o +obj-$(CONFIG_MACH_DOCKSTAR_DT) += board-dockstar.o obj-$(CONFIG_MACH_GOFLEXNET_DT) += board-goflexnet.o obj-$(CONFIG_MACH_LSXL_DT) += board-lsxl.o +obj-$(CONFIG_MACH_IOMEGA_IX2_200_DT) += board-iomega_ix2_200.o +obj-$(CONFIG_MACH_KM_KIRKWOOD_DT) += board-km_kirkwood.o diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c index e9a7180863d9..8f0d162a1e1d 100644 --- a/arch/arm/mach-kirkwood/addr-map.c +++ b/arch/arm/mach-kirkwood/addr-map.c @@ -86,5 +86,6 @@ void __init kirkwood_setup_cpu_mbus(void) /* * Setup MBUS dram target info. */ - orion_setup_cpu_mbus_target(&addr_map_cfg, DDR_WINDOW_CPU_BASE); + orion_setup_cpu_mbus_target(&addr_map_cfg, + (void __iomem *) DDR_WINDOW_CPU_BASE); } diff --git a/arch/arm/mach-kirkwood/board-dnskw.c b/arch/arm/mach-kirkwood/board-dnskw.c index 4ab35065a144..43d16d6714b8 100644 --- a/arch/arm/mach-kirkwood/board-dnskw.c +++ b/arch/arm/mach-kirkwood/board-dnskw.c @@ -14,18 +14,8 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/platform_device.h> -#include <linux/ata_platform.h> #include <linux/mv643xx_eth.h> -#include <linux/of.h> #include <linux/gpio.h> -#include <linux/input.h> -#include <linux/gpio-fan.h> -#include <linux/leds.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <mach/kirkwood.h> -#include <mach/bridge-regs.h> #include "common.h" #include "mpp.h" @@ -67,29 +57,6 @@ static unsigned int dnskw_mpp_config[] __initdata = { 0 }; -/* Fan: ADDA AD045HB-G73 40mm 6000rpm@5v */ -static struct gpio_fan_speed dnskw_fan_speed[] = { - { 0, 0 }, - { 3000, 1 }, - { 6000, 2 }, -}; -static unsigned dnskw_fan_pins[] = {46, 45}; - -static struct gpio_fan_platform_data dnskw_fan_data = { - .num_ctrl = ARRAY_SIZE(dnskw_fan_pins), - .ctrl = dnskw_fan_pins, - .num_speed = ARRAY_SIZE(dnskw_fan_speed), - .speed = dnskw_fan_speed, -}; - -static struct platform_device dnskw_fan_device = { - .name = "gpio-fan", - .id = -1, - .dev = { - .platform_data = &dnskw_fan_data, - }, -}; - static void dnskw_power_off(void) { gpio_set_value(36, 1); @@ -114,8 +81,6 @@ void __init dnskw_init(void) kirkwood_ehci_init(); kirkwood_ge00_init(&dnskw_ge00_data); - platform_device_register(&dnskw_fan_device); - /* Register power-off GPIO. */ if (gpio_request(36, "dnskw:power:off") == 0 && gpio_direction_output(36, 0) == 0) diff --git a/arch/arm/mach-kirkwood/board-dockstar.c b/arch/arm/mach-kirkwood/board-dockstar.c new file mode 100644 index 000000000000..f2fbb023e679 --- /dev/null +++ b/arch/arm/mach-kirkwood/board-dockstar.c @@ -0,0 +1,61 @@ +/* + * arch/arm/mach-kirkwood/board-dockstar.c + * + * Seagate FreeAgent Dockstar Board Init for drivers not converted to + * flattened device tree yet. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * Copied and modified for Seagate GoFlex Net support by + * Joshua Coombs <josh.coombs@gmail.com> based on ArchLinux ARM's + * GoFlex kernel patches. + * + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/ata_platform.h> +#include <linux/mv643xx_eth.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_fdt.h> +#include <linux/of_irq.h> +#include <linux/of_platform.h> +#include <linux/gpio.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <mach/kirkwood.h> +#include <mach/bridge-regs.h> +#include <linux/platform_data/mmc-mvsdio.h> +#include "common.h" +#include "mpp.h" + +static struct mv643xx_eth_platform_data dockstar_ge00_data = { + .phy_addr = MV643XX_ETH_PHY_ADDR(0), +}; + +static unsigned int dockstar_mpp_config[] __initdata = { + MPP29_GPIO, /* USB Power Enable */ + MPP46_GPIO, /* LED green */ + MPP47_GPIO, /* LED orange */ + 0 +}; + +void __init dockstar_dt_init(void) +{ + /* + * Basic setup. Needs to be called early. + */ + kirkwood_mpp_conf(dockstar_mpp_config); + + if (gpio_request(29, "USB Power Enable") != 0 || + gpio_direction_output(29, 1) != 0) + pr_err("can't setup GPIO 29 (USB Power Enable)\n"); + kirkwood_ehci_init(); + + kirkwood_ge00_init(&dockstar_ge00_data); +} diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c index e4eb450de301..d94872fed8c0 100644 --- a/arch/arm/mach-kirkwood/board-dt.c +++ b/arch/arm/mach-kirkwood/board-dt.c @@ -33,6 +33,7 @@ struct of_dev_auxdata kirkwood_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("marvell,orion-wdt", 0xf1020300, "orion_wdt", NULL), OF_DEV_AUXDATA("marvell,orion-sata", 0xf1080000, "sata_mv.0", NULL), OF_DEV_AUXDATA("marvell,orion-nand", 0xf4000000, "orion_nand", NULL), + OF_DEV_AUXDATA("marvell,orion-crypto", 0xf1030000, "mv_crypto", NULL), {}, }; @@ -50,9 +51,7 @@ static void __init kirkwood_dt_init(void) kirkwood_setup_cpu_mbus(); -#ifdef CONFIG_CACHE_FEROCEON_L2 kirkwood_l2_init(); -#endif /* Setup root of clk tree */ kirkwood_clk_init(); @@ -60,7 +59,6 @@ static void __init kirkwood_dt_init(void) /* internal devices that every board has */ kirkwood_xor0_init(); kirkwood_xor1_init(); - kirkwood_crypto_init(); #ifdef CONFIG_KEXEC kexec_reinit = kirkwood_enable_pcie; @@ -81,12 +79,21 @@ static void __init kirkwood_dt_init(void) if (of_machine_is_compatible("qnap,ts219")) qnap_dt_ts219_init(); + if (of_machine_is_compatible("seagate,dockstar")) + dockstar_dt_init(); + if (of_machine_is_compatible("seagate,goflexnet")) goflexnet_init(); if (of_machine_is_compatible("buffalo,lsxl")) lsxl_init(); + if (of_machine_is_compatible("iom,ix2-200")) + iomega_ix2_200_init(); + + if (of_machine_is_compatible("keymile,km_kirkwood")) + km_kirkwood_init(); + of_platform_populate(NULL, kirkwood_dt_match_table, kirkwood_auxdata_lookup, NULL); } @@ -98,8 +105,11 @@ static const char *kirkwood_dt_board_compat[] = { "iom,iconnect", "raidsonic,ib-nas62x0", "qnap,ts219", + "seagate,dockstar", "seagate,goflexnet", "buffalo,lsxl", + "iom,ix2-200", + "keymile,km_kirkwood", NULL }; diff --git a/arch/arm/mach-kirkwood/board-iconnect.c b/arch/arm/mach-kirkwood/board-iconnect.c index d7a9198ed300..d084b1e2943a 100644 --- a/arch/arm/mach-kirkwood/board-iconnect.c +++ b/arch/arm/mach-kirkwood/board-iconnect.c @@ -16,11 +16,8 @@ #include <linux/of_fdt.h> #include <linux/of_irq.h> #include <linux/of_platform.h> -#include <linux/mtd/partitions.h> #include <linux/mv643xx_eth.h> #include <linux/gpio.h> -#include <linux/input.h> -#include <linux/gpio_keys.h> #include <asm/mach/arch.h> #include <mach/kirkwood.h> #include "common.h" @@ -44,57 +41,12 @@ static unsigned int iconnect_mpp_config[] __initdata = { 0 }; -static struct mtd_partition iconnect_nand_parts[] = { - { - .name = "flash", - .offset = 0, - .size = MTDPART_SIZ_FULL, - }, -}; - -/* yikes... theses are the original input buttons */ -/* but I'm not convinced by the sw event choices */ -static struct gpio_keys_button iconnect_buttons[] = { - { - .type = EV_SW, - .code = SW_LID, - .gpio = 12, - .desc = "Reset Button", - .active_low = 1, - .debounce_interval = 100, - }, { - .type = EV_SW, - .code = SW_TABLET_MODE, - .gpio = 35, - .desc = "OTB Button", - .active_low = 1, - .debounce_interval = 100, - }, -}; - -static struct gpio_keys_platform_data iconnect_button_data = { - .buttons = iconnect_buttons, - .nbuttons = ARRAY_SIZE(iconnect_buttons), -}; - -static struct platform_device iconnect_button_device = { - .name = "gpio-keys", - .id = -1, - .num_resources = 0, - .dev = { - .platform_data = &iconnect_button_data, - }, -}; - void __init iconnect_init(void) { kirkwood_mpp_conf(iconnect_mpp_config); - kirkwood_nand_init(ARRAY_AND_SIZE(iconnect_nand_parts), 25); kirkwood_ehci_init(); kirkwood_ge00_init(&iconnect_ge00_data); - - platform_device_register(&iconnect_button_device); } static int __init iconnect_pci_init(void) diff --git a/arch/arm/mach-kirkwood/board-iomega_ix2_200.c b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c new file mode 100644 index 000000000000..158fb97d0397 --- /dev/null +++ b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c @@ -0,0 +1,57 @@ +/* + * arch/arm/mach-kirkwood/board-iomega_ix2_200.c + * + * Iomega StorCenter ix2-200 + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/mv643xx_eth.h> +#include <linux/ethtool.h> +#include <mach/kirkwood.h> +#include "common.h" +#include "mpp.h" + +static struct mv643xx_eth_platform_data iomega_ix2_200_ge00_data = { + .phy_addr = MV643XX_ETH_PHY_NONE, + .speed = SPEED_1000, + .duplex = DUPLEX_FULL, +}; + +static unsigned int iomega_ix2_200_mpp_config[] __initdata = { + MPP12_GPIO, /* Reset Button */ + MPP14_GPIO, /* Power Button */ + MPP15_GPIO, /* Backup LED (blue) */ + MPP16_GPIO, /* Power LED (white) */ + MPP35_GPIO, /* OTB Button */ + MPP36_GPIO, /* Rebuild LED (white) */ + MPP37_GPIO, /* Health LED (red) */ + MPP38_GPIO, /* SATA LED brightness control 1 */ + MPP39_GPIO, /* SATA LED brightness control 2 */ + MPP40_GPIO, /* Backup LED brightness control 1 */ + MPP41_GPIO, /* Backup LED brightness control 2 */ + MPP42_GPIO, /* Power LED brightness control 1 */ + MPP43_GPIO, /* Power LED brightness control 2 */ + MPP44_GPIO, /* Health LED brightness control 1 */ + MPP45_GPIO, /* Health LED brightness control 2 */ + MPP46_GPIO, /* Rebuild LED brightness control 1 */ + MPP47_GPIO, /* Rebuild LED brightness control 2 */ + 0 +}; + +void __init iomega_ix2_200_init(void) +{ + /* + * Basic setup. Needs to be called early. + */ + kirkwood_mpp_conf(iomega_ix2_200_mpp_config); + + kirkwood_ehci_init(); + + kirkwood_ge01_init(&iomega_ix2_200_ge00_data); +} diff --git a/arch/arm/mach-kirkwood/board-km_kirkwood.c b/arch/arm/mach-kirkwood/board-km_kirkwood.c new file mode 100644 index 000000000000..f7d32834b757 --- /dev/null +++ b/arch/arm/mach-kirkwood/board-km_kirkwood.c @@ -0,0 +1,57 @@ +/* + * Copyright 2012 2012 KEYMILE AG, CH-3097 Bern + * Valentin Longchamp <valentin.longchamp@keymile.com> + * + * arch/arm/mach-kirkwood/board-km_kirkwood.c + * + * Keymile km_kirkwood Reference Desing Init for drivers not converted to + * flattened device tree yet. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/mv643xx_eth.h> +#include <linux/clk.h> +#include <linux/clk-private.h> +#include "common.h" +#include "mpp.h" + +static struct mv643xx_eth_platform_data km_kirkwood_ge00_data = { + .phy_addr = MV643XX_ETH_PHY_ADDR(0), +}; + +static unsigned int km_kirkwood_mpp_config[] __initdata = { + MPP8_GPIO, /* I2C SDA */ + MPP9_GPIO, /* I2C SCL */ + 0 +}; + +void __init km_kirkwood_init(void) +{ + struct clk *sata_clk; + /* + * Basic setup. Needs to be called early. + */ + kirkwood_mpp_conf(km_kirkwood_mpp_config); + + /* + * Our variant of kirkwood (integrated in the Bobcat) hangs on accessing + * SATA bits (14-15) of the Clock Gating Control Register. Since these + * devices are also not present in this variant, their clocks get + * disabled because unused when clk_disable_unused() gets called. + * That's why we change the flags to these clocks to CLK_IGNORE_UNUSED + */ + sata_clk = clk_get_sys("sata_mv.0", "0"); + if (!IS_ERR(sata_clk)) + sata_clk->flags |= CLK_IGNORE_UNUSED; + sata_clk = clk_get_sys("sata_mv.0", "1"); + if (!IS_ERR(sata_clk)) + sata_clk->flags |= CLK_IGNORE_UNUSED; + + kirkwood_ehci_init(); + kirkwood_ge00_init(&km_kirkwood_ge00_data); +} diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index 5c38c94b79a2..2c6c218fb79e 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -42,7 +42,7 @@ ****************************************************************************/ static struct map_desc kirkwood_io_desc[] __initdata = { { - .virtual = KIRKWOOD_REGS_VIRT_BASE, + .virtual = (unsigned long) KIRKWOOD_REGS_VIRT_BASE, .pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE), .length = KIRKWOOD_REGS_SIZE, .type = MT_DEVICE, @@ -205,8 +205,7 @@ static struct clk *tclk; static struct clk __init *kirkwood_register_gate(const char *name, u8 bit_idx) { - return clk_register_gate(NULL, name, "tclk", 0, - (void __iomem *)CLOCK_GATING_CTRL, + return clk_register_gate(NULL, name, "tclk", 0, CLOCK_GATING_CTRL, bit_idx, 0, &gating_lock); } @@ -215,8 +214,7 @@ static struct clk __init *kirkwood_register_gate_fn(const char *name, void (*fn_en)(void), void (*fn_dis)(void)) { - return clk_register_gate_fn(NULL, name, "tclk", 0, - (void __iomem *)CLOCK_GATING_CTRL, + return clk_register_gate_fn(NULL, name, "tclk", 0, CLOCK_GATING_CTRL, bit_idx, 0, &gating_lock, fn_en, fn_dis); } @@ -635,6 +633,7 @@ char * __init kirkwood_id(void) void __init kirkwood_l2_init(void) { +#ifdef CONFIG_CACHE_FEROCEON_L2 #ifdef CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH writel(readl(L2_CONFIG_REG) | L2_WRITETHROUGH, L2_CONFIG_REG); feroceon_l2_init(1); @@ -642,6 +641,7 @@ void __init kirkwood_l2_init(void) writel(readl(L2_CONFIG_REG) & ~L2_WRITETHROUGH, L2_CONFIG_REG); feroceon_l2_init(0); #endif +#endif } void __init kirkwood_init(void) @@ -659,9 +659,7 @@ void __init kirkwood_init(void) kirkwood_setup_cpu_mbus(); -#ifdef CONFIG_CACHE_FEROCEON_L2 kirkwood_l2_init(); -#endif /* Setup root of clk tree */ kirkwood_clk_init(); diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h index 304dd1abfdca..bcffd7ca1ca2 100644 --- a/arch/arm/mach-kirkwood/common.h +++ b/arch/arm/mach-kirkwood/common.h @@ -82,6 +82,12 @@ void ib62x0_init(void); static inline void ib62x0_init(void) {}; #endif +#ifdef CONFIG_MACH_DOCKSTAR_DT +void dockstar_dt_init(void); +#else +static inline void dockstar_dt_init(void) {}; +#endif + #ifdef CONFIG_MACH_GOFLEXNET_DT void goflexnet_init(void); #else @@ -94,6 +100,18 @@ void lsxl_init(void); static inline void lsxl_init(void) {}; #endif +#ifdef CONFIG_MACH_IOMEGA_IX2_200_DT +void iomega_ix2_200_init(void); +#else +static inline void iomega_ix2_200_init(void) {}; +#endif + +#ifdef CONFIG_MACH_KM_KIRKWOOD_DT +void km_kirkwood_init(void); +#else +static inline void km_kirkwood_init(void) {}; +#endif + /* early init functions not converted to fdt yet */ char *kirkwood_id(void); void kirkwood_l2_init(void); diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h index a115142f8690..5c82b7dce4e2 100644 --- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h +++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h @@ -13,37 +13,37 @@ #include <mach/kirkwood.h> -#define CPU_CONFIG (BRIDGE_VIRT_BASE | 0x0100) +#define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0100) #define CPU_CONFIG_ERROR_PROP 0x00000004 -#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104) +#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104) #define CPU_RESET 0x00000002 -#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) +#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108) #define WDT_RESET_OUT_EN 0x00000002 #define SOFT_RESET_OUT_EN 0x00000004 -#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) +#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c) #define SOFT_RESET 0x00000001 -#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110) +#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE + 0x0110) #define WDT_INT_REQ 0x0008 #define BRIDGE_INT_TIMER1_CLR (~0x0004) -#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) +#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200) #define IRQ_CAUSE_LOW_OFF 0x0000 #define IRQ_MASK_LOW_OFF 0x0004 #define IRQ_CAUSE_HIGH_OFF 0x0010 #define IRQ_MASK_HIGH_OFF 0x0014 -#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) -#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE | 0x0300) +#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300) +#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300) -#define L2_CONFIG_REG (BRIDGE_VIRT_BASE | 0x0128) +#define L2_CONFIG_REG (BRIDGE_VIRT_BASE + 0x0128) #define L2_WRITETHROUGH 0x00000010 -#define CLOCK_GATING_CTRL (BRIDGE_VIRT_BASE | 0x11c) +#define CLOCK_GATING_CTRL (BRIDGE_VIRT_BASE + 0x11c) #define CGC_BIT_GE0 (0) #define CGC_BIT_PEX0 (2) #define CGC_BIT_USB0 (3) diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h index af4f0000dcef..041653a04a9c 100644 --- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h +++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h @@ -45,7 +45,7 @@ #define KIRKWOOD_PCIE_IO_SIZE SZ_64K #define KIRKWOOD_REGS_PHYS_BASE 0xf1000000 -#define KIRKWOOD_REGS_VIRT_BASE 0xfed00000 +#define KIRKWOOD_REGS_VIRT_BASE IOMEM(0xfed00000) #define KIRKWOOD_REGS_SIZE SZ_1M #define KIRKWOOD_PCIE_MEM_PHYS_BASE 0xe0000000 @@ -59,61 +59,61 @@ /* * Register Map */ -#define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x00000) -#define DDR_WINDOW_CPU_BASE (DDR_VIRT_BASE | 0x1500) -#define DDR_OPERATION_BASE (DDR_VIRT_BASE | 0x1418) - -#define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x10000) -#define DEV_BUS_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x10000) -#define SAMPLE_AT_RESET (DEV_BUS_VIRT_BASE | 0x0030) -#define DEVICE_ID (DEV_BUS_VIRT_BASE | 0x0034) -#define GPIO_LOW_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x0100) -#define GPIO_HIGH_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x0140) -#define RTC_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0300) -#define SPI_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0600) -#define I2C_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1000) -#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000) -#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000) -#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100) -#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100) - -#define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x20000) -#define BRIDGE_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x20000) - -#define CRYPTO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x30000) - -#define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x40000) -#define PCIE_LINK_CTRL (PCIE_VIRT_BASE | 0x70) -#define PCIE_STATUS (PCIE_VIRT_BASE | 0x1a04) -#define PCIE1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x44000) -#define PCIE1_LINK_CTRL (PCIE1_VIRT_BASE | 0x70) -#define PCIE1_STATUS (PCIE1_VIRT_BASE | 0x1a04) - -#define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x50000) - -#define XOR0_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x60800) -#define XOR0_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x60800) -#define XOR1_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x60900) -#define XOR1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x60900) -#define XOR0_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x60A00) -#define XOR0_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x60A00) -#define XOR1_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x60B00) -#define XOR1_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x60B00) - -#define GE00_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x70000) -#define GE01_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x74000) - -#define SATA_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x80000) -#define SATA_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x80000) -#define SATA0_IF_CTRL (SATA_VIRT_BASE | 0x2050) -#define SATA0_PHY_MODE_2 (SATA_VIRT_BASE | 0x2330) -#define SATA1_IF_CTRL (SATA_VIRT_BASE | 0x4050) -#define SATA1_PHY_MODE_2 (SATA_VIRT_BASE | 0x4330) - -#define SDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x90000) - -#define AUDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0xA0000) -#define AUDIO_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0xA0000) +#define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x00000) +#define DDR_WINDOW_CPU_BASE (DDR_VIRT_BASE + 0x1500) +#define DDR_OPERATION_BASE (DDR_VIRT_BASE + 0x1418) + +#define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x10000) +#define DEV_BUS_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x10000) +#define SAMPLE_AT_RESET (DEV_BUS_VIRT_BASE + 0x0030) +#define DEVICE_ID (DEV_BUS_VIRT_BASE + 0x0034) +#define GPIO_LOW_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0100) +#define GPIO_HIGH_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0140) +#define RTC_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x0300) +#define SPI_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x0600) +#define I2C_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1000) +#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2000) +#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2000) +#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2100) +#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2100) + +#define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x20000) +#define BRIDGE_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x20000) + +#define CRYPTO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x30000) + +#define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x40000) +#define PCIE_LINK_CTRL (PCIE_VIRT_BASE + 0x70) +#define PCIE_STATUS (PCIE_VIRT_BASE + 0x1a04) +#define PCIE1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x44000) +#define PCIE1_LINK_CTRL (PCIE1_VIRT_BASE + 0x70) +#define PCIE1_STATUS (PCIE1_VIRT_BASE + 0x1a04) + +#define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x50000) + +#define XOR0_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60800) +#define XOR0_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60800) +#define XOR1_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60900) +#define XOR1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60900) +#define XOR0_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60A00) +#define XOR0_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60A00) +#define XOR1_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60B00) +#define XOR1_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60B00) + +#define GE00_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x70000) +#define GE01_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x74000) + +#define SATA_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x80000) +#define SATA_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x80000) +#define SATA0_IF_CTRL (SATA_VIRT_BASE + 0x2050) +#define SATA0_PHY_MODE_2 (SATA_VIRT_BASE + 0x2330) +#define SATA1_IF_CTRL (SATA_VIRT_BASE + 0x4050) +#define SATA1_PHY_MODE_2 (SATA_VIRT_BASE + 0x4330) + +#define SDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x90000) + +#define AUDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0xA0000) +#define AUDIO_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0xA0000) /* * Supported devices and revisions. diff --git a/arch/arm/mach-kirkwood/irq.c b/arch/arm/mach-kirkwood/irq.c index 20149a7fd280..884703535a0a 100644 --- a/arch/arm/mach-kirkwood/irq.c +++ b/arch/arm/mach-kirkwood/irq.c @@ -10,6 +10,7 @@ #include <linux/gpio.h> #include <linux/kernel.h> #include <linux/irq.h> +#include <linux/io.h> #include <mach/bridge-regs.h> #include <plat/orion-gpio.h> #include <plat/irq.h> @@ -30,14 +31,14 @@ static int __initdata gpio1_irqs[4] = { void __init kirkwood_init_irq(void) { - orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); - orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); + orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF); + orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF); /* * Initialize gpiolib for GPIOs 0-49. */ - orion_gpio_init(NULL, 0, 32, (void __iomem *)GPIO_LOW_VIRT_BASE, 0, + orion_gpio_init(NULL, 0, 32, GPIO_LOW_VIRT_BASE, 0, IRQ_KIRKWOOD_GPIO_START, gpio0_irqs); - orion_gpio_init(NULL, 32, 18, (void __iomem *)GPIO_HIGH_VIRT_BASE, 0, + orion_gpio_init(NULL, 32, 18, GPIO_HIGH_VIRT_BASE, 0, IRQ_KIRKWOOD_GPIO_START + 32, gpio1_irqs); } diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c index 532d8acb38f9..ec544918b12c 100644 --- a/arch/arm/mach-kirkwood/pcie.c +++ b/arch/arm/mach-kirkwood/pcie.c @@ -47,8 +47,8 @@ void kirkwood_enable_pcie(void) void kirkwood_pcie_id(u32 *dev, u32 *rev) { kirkwood_enable_pcie(); - *dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE); - *rev = orion_pcie_rev((void __iomem *)PCIE_VIRT_BASE); + *dev = orion_pcie_dev_id(PCIE_VIRT_BASE); + *rev = orion_pcie_rev(PCIE_VIRT_BASE); } struct pcie_port { @@ -133,7 +133,7 @@ static struct pci_ops pcie_ops = { static void __init pcie0_ioresources_init(struct pcie_port *pp) { - pp->base = (void __iomem *)PCIE_VIRT_BASE; + pp->base = PCIE_VIRT_BASE; pp->irq = IRQ_KIRKWOOD_PCIE; /* @@ -147,7 +147,7 @@ static void __init pcie0_ioresources_init(struct pcie_port *pp) static void __init pcie1_ioresources_init(struct pcie_port *pp) { - pp->base = (void __iomem *)PCIE1_VIRT_BASE; + pp->base = PCIE1_VIRT_BASE; pp->irq = IRQ_KIRKWOOD_PCIE1; /* @@ -255,11 +255,11 @@ static struct hw_pci kirkwood_pci __initdata = { .map_irq = kirkwood_pcie_map_irq, }; -static void __init add_pcie_port(int index, unsigned long base) +static void __init add_pcie_port(int index, void __iomem *base) { printk(KERN_INFO "Kirkwood PCIe port %d: ", index); - if (orion_pcie_link_up((void __iomem *)base)) { + if (orion_pcie_link_up(base)) { printk(KERN_INFO "link up\n"); pcie_port_map[num_pcie_ports++] = index; } else diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c index 5bbca2680442..367a9400f532 100644 --- a/arch/arm/mach-kirkwood/ts41x-setup.c +++ b/arch/arm/mach-kirkwood/ts41x-setup.c @@ -20,6 +20,7 @@ #include <linux/gpio.h> #include <linux/gpio_keys.h> #include <linux/input.h> +#include <linux/io.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <mach/kirkwood.h> @@ -161,7 +162,7 @@ static int __init ts41x_pci_init(void) * (Marvell 88sx7042/sata_mv) is known to stop working * after a few minutes. */ - orion_pcie_reset((void __iomem *)PCIE_VIRT_BASE); + orion_pcie_reset(PCIE_VIRT_BASE); kirkwood_pcie_id(&dev, &rev); if (dev == MV88F6282_DEV_ID) diff --git a/arch/arm/mach-ks8695/include/mach/memory.h b/arch/arm/mach-ks8695/include/mach/memory.h index f7e1b9bce345..95e731a7ed6a 100644 --- a/arch/arm/mach-ks8695/include/mach/memory.h +++ b/arch/arm/mach-ks8695/include/mach/memory.h @@ -34,7 +34,8 @@ extern struct bus_type platform_bus_type; #define __arch_dma_to_virt(dev, x) ({ (void *) (is_lbus_device(dev) ? \ __phys_to_virt(x) : __bus_to_virt(x)); }) #define __arch_virt_to_dma(dev, x) ({ is_lbus_device(dev) ? \ - (dma_addr_t)__virt_to_phys(x) : (dma_addr_t)__virt_to_bus(x); }) + (dma_addr_t)__virt_to_phys((unsigned long)x) \ + : (dma_addr_t)__virt_to_bus(x); }) #define __arch_pfn_to_dma(dev, pfn) \ ({ dma_addr_t __dma = __pfn_to_phys(pfn); \ if (!is_lbus_device(dev)) \ diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig index d697d07a1bf0..178d4daa5e1d 100644 --- a/arch/arm/mach-mmp/Kconfig +++ b/arch/arm/mach-mmp/Kconfig @@ -107,22 +107,22 @@ endmenu config CPU_PXA168 bool - select CPU_MOHAWK select COMMON_CLK + select CPU_MOHAWK help Select code specific to PXA168 config CPU_PXA910 bool - select CPU_MOHAWK select COMMON_CLK + select CPU_MOHAWK help Select code specific to PXA910 config CPU_MMP2 bool - select CPU_PJ4 select COMMON_CLK + select CPU_PJ4 help Select code specific to MMP2. MMP2 is ARMv7 compatible. diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index 7902de151cc5..b61908594b47 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig @@ -10,35 +10,35 @@ choice config ARCH_MSM7X00A bool "MSM7x00A / MSM7x01A" - select MACH_TROUT if !MACH_HALIBUT select ARCH_MSM_ARM11 - select MSM_SMD - select MSM_SMD_PKG3 select CPU_V6 select GPIO_MSM_V1 + select MACH_TROUT if !MACH_HALIBUT select MSM_PROC_COMM + select MSM_SMD + select MSM_SMD_PKG3 config ARCH_MSM7X30 bool "MSM7x30" - select MACH_MSM7X30_SURF # if ! select ARCH_MSM_SCORPION - select MSM_SMD - select MSM_VIC select CPU_V7 - select MSM_GPIOMUX select GPIO_MSM_V1 + select MACH_MSM7X30_SURF # if ! + select MSM_GPIOMUX select MSM_PROC_COMM + select MSM_SMD + select MSM_VIC config ARCH_QSD8X50 bool "QSD8X50" - select MACH_QSD8X50_SURF if !MACH_QSD8X50A_ST1_5 select ARCH_MSM_SCORPION - select MSM_SMD - select MSM_VIC select CPU_V7 - select MSM_GPIOMUX select GPIO_MSM_V1 + select MACH_QSD8X50_SURF if !MACH_QSD8X50A_ST1_5 + select MSM_GPIOMUX select MSM_PROC_COMM + select MSM_SMD + select MSM_VIC endchoice @@ -47,10 +47,10 @@ config ARCH_MSM8X60 select ARCH_MSM_SCORPIONMP select ARM_GIC select CPU_V7 - select MSM_V2_TLMM select GPIO_MSM_V2 select MSM_GPIOMUX select MSM_SCM if SMP + select MSM_V2_TLMM select USE_OF config ARCH_MSM8960 @@ -58,9 +58,9 @@ config ARCH_MSM8960 select ARCH_MSM_SCORPIONMP select ARM_GIC select CPU_V7 - select MSM_V2_TLMM select MSM_GPIOMUX select MSM_SCM if SMP + select MSM_V2_TLMM select USE_OF config MSM_HAS_DEBUG_UART_HS @@ -110,8 +110,8 @@ config MACH_QSD8X50_SURF config MACH_QSD8X50A_ST1_5 depends on ARCH_QSD8X50 - select MSM_SOC_REV_A bool "QSD8x50A ST1.5" + select MSM_SOC_REV_A help Support for the Qualcomm ST1.5. diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c index a344a373928b..2448fcf09eb1 100644 --- a/arch/arm/mach-msm/board-qsd8x50.c +++ b/arch/arm/mach-msm/board-qsd8x50.c @@ -37,8 +37,8 @@ #include "devices.h" #include "common.h" -static const resource_size_t qsd8x50_surf_smc91x_base __initdata = 0x70000300; -static const unsigned qsd8x50_surf_smc91x_gpio __initdata = 156; +static const resource_size_t qsd8x50_surf_smc91x_base __initconst = 0x70000300; +static const unsigned qsd8x50_surf_smc91x_gpio __initconst = 156; /* Leave smc91x resources empty here, as we'll fill them in * at run-time: they vary from board to board, and the true diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c index 137e479d15a0..26e9876b50e9 100644 --- a/arch/arm/mach-mv78xx0/addr-map.c +++ b/arch/arm/mach-mv78xx0/addr-map.c @@ -48,13 +48,13 @@ static void __init __iomem *win_cfg_base(const struct orion_addr_map_cfg *cfg, i * so we don't need to take that into account here. */ - return (void __iomem *)((win < 8) ? WIN0_OFF(win) : WIN8_OFF(win)); + return (win < 8) ? WIN0_OFF(win) : WIN8_OFF(win); } /* * Description of the windows needed by the platform code */ -static struct __initdata orion_addr_map_cfg addr_map_cfg = { +static struct orion_addr_map_cfg addr_map_cfg __initdata = { .num_wins = 14, .remappable_wins = 8, .win_cfg_base = win_cfg_base, @@ -72,10 +72,10 @@ void __init mv78xx0_setup_cpu_mbus(void) */ if (mv78xx0_core_index() == 0) orion_setup_cpu_mbus_target(&addr_map_cfg, - DDR_WINDOW_CPU0_BASE); + (void __iomem *) DDR_WINDOW_CPU0_BASE); else orion_setup_cpu_mbus_target(&addr_map_cfg, - DDR_WINDOW_CPU1_BASE); + (void __iomem *) DDR_WINDOW_CPU1_BASE); } void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size, diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index a6f3cd21e8c2..d0cb4857b4b3 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c @@ -130,12 +130,12 @@ static int get_tclk(void) ****************************************************************************/ static struct map_desc mv78xx0_io_desc[] __initdata = { { - .virtual = MV78XX0_CORE_REGS_VIRT_BASE, + .virtual = (unsigned long) MV78XX0_CORE_REGS_VIRT_BASE, .pfn = 0, .length = MV78XX0_CORE_REGS_SIZE, .type = MT_DEVICE, }, { - .virtual = MV78XX0_REGS_VIRT_BASE, + .virtual = (unsigned long) MV78XX0_REGS_VIRT_BASE, .pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE), .length = MV78XX0_REGS_SIZE, .type = MT_DEVICE, @@ -336,7 +336,7 @@ void __init mv78xx0_init_early(void) orion_time_set_base(TIMER_VIRT_BASE); } -static void mv78xx0_timer_init(void) +static void __init_refok mv78xx0_timer_init(void) { orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, IRQ_MV78XX0_TIMER_1, get_tclk()); diff --git a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h index eb187e0e059b..5f03484584d4 100644 --- a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h +++ b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h @@ -11,18 +11,18 @@ #include <mach/mv78xx0.h> -#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104) +#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104) #define L2_WRITETHROUGH 0x00020000 -#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) +#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108) #define SOFT_RESET_OUT_EN 0x00000004 -#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) +#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c) #define SOFT_RESET 0x00000001 #define BRIDGE_INT_TIMER1_CLR (~0x0004) -#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) +#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200) #define IRQ_CAUSE_ERR_OFF 0x0000 #define IRQ_CAUSE_LOW_OFF 0x0004 #define IRQ_CAUSE_HIGH_OFF 0x0008 @@ -30,7 +30,7 @@ #define IRQ_MASK_LOW_OFF 0x0010 #define IRQ_MASK_HIGH_OFF 0x0014 -#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) -#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE | 0x0300) +#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300) +#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300) #endif diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h index bd03fed1128e..46200a183cf2 100644 --- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h +++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h @@ -41,7 +41,7 @@ */ #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 -#define MV78XX0_CORE_REGS_VIRT_BASE 0xfe400000 +#define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000) #define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000 #define MV78XX0_CORE_REGS_SIZE SZ_16K @@ -49,7 +49,7 @@ #define MV78XX0_PCIE_IO_SIZE SZ_1M #define MV78XX0_REGS_PHYS_BASE 0xf1000000 -#define MV78XX0_REGS_VIRT_BASE 0xfd000000 +#define MV78XX0_REGS_VIRT_BASE IOMEM(0xfd000000) #define MV78XX0_REGS_SIZE SZ_1M #define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000 @@ -64,47 +64,47 @@ /* * Register Map */ -#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x00000) -#define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE | 0x1500) -#define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE | 0x1570) - -#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x10000) -#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x10000) -#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE | 0x0030) -#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE | 0x0034) -#define GPIO_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x0100) -#define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1000) -#define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1100) -#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000) -#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000) -#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100) -#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100) -#define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2200) -#define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2200) -#define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2300) -#define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2300) - -#define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x30000) -#define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x34000) - -#define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x40000) -#define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x44000) -#define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x48000) -#define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x4c000) - -#define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x50000) -#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x51000) -#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x52000) - -#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x70000) -#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x74000) - -#define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x80000) -#define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x84000) -#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x88000) -#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x8c000) - -#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0xa0000) +#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x00000) +#define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE + 0x1500) +#define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE + 0x1570) + +#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x10000) +#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x10000) +#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE + 0x0030) +#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE + 0x0034) +#define GPIO_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0100) +#define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1000) +#define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1100) +#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2000) +#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2000) +#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2100) +#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2100) +#define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2200) +#define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2200) +#define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2300) +#define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2300) + +#define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x30000) +#define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x34000) + +#define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x40000) +#define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x44000) +#define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x48000) +#define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x4c000) + +#define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x50000) +#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x51000) +#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x52000) + +#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x70000) +#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x74000) + +#define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x80000) +#define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x84000) +#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x88000) +#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x8c000) + +#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0xa0000) /* * Supported devices and revisions. diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c index 4d720f2aedba..32073444024b 100644 --- a/arch/arm/mach-mv78xx0/irq.c +++ b/arch/arm/mach-mv78xx0/irq.c @@ -10,6 +10,7 @@ #include <linux/gpio.h> #include <linux/kernel.h> #include <linux/irq.h> +#include <linux/io.h> #include <mach/bridge-regs.h> #include <plat/orion-gpio.h> #include <plat/irq.h> @@ -24,16 +25,16 @@ static int __initdata gpio0_irqs[4] = { void __init mv78xx0_init_irq(void) { - orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); - orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); - orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF)); + orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF); + orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF); + orion_irq_init(64, IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF); /* * Initialize gpiolib for GPIOs 0-31. (The GPIO interrupt mask * registers for core #1 are at an offset of 0x18 from those of * core #0.) */ - orion_gpio_init(NULL, 0, 32, (void __iomem *)GPIO_VIRT_BASE, + orion_gpio_init(NULL, 0, 32, GPIO_VIRT_BASE, mv78xx0_core_index() ? 0x18 : 0, IRQ_MV78XX0_GPIO_START, gpio0_irqs); } diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c index 26a059b4f472..a9a154a646dd 100644 --- a/arch/arm/mach-mv78xx0/pcie.c +++ b/arch/arm/mach-mv78xx0/pcie.c @@ -34,8 +34,8 @@ static struct resource pcie_io_space; void __init mv78xx0_pcie_id(u32 *dev, u32 *rev) { - *dev = orion_pcie_dev_id((void __iomem *)PCIE00_VIRT_BASE); - *rev = orion_pcie_rev((void __iomem *)PCIE00_VIRT_BASE); + *dev = orion_pcie_dev_id(PCIE00_VIRT_BASE); + *rev = orion_pcie_rev(PCIE00_VIRT_BASE); } u32 pcie_port_size[8] = { @@ -223,11 +223,11 @@ static struct hw_pci mv78xx0_pci __initdata = { .map_irq = mv78xx0_pcie_map_irq, }; -static void __init add_pcie_port(int maj, int min, unsigned long base) +static void __init add_pcie_port(int maj, int min, void __iomem *base) { printk(KERN_INFO "MV78xx0 PCIe port %d.%d: ", maj, min); - if (orion_pcie_link_up((void __iomem *)base)) { + if (orion_pcie_link_up(base)) { struct pcie_port *pp = &pcie_port[num_pcie_ports++]; printk("link up\n"); @@ -235,7 +235,7 @@ static void __init add_pcie_port(int maj, int min, unsigned long base) pp->maj = maj; pp->min = min; pp->root_bus_nr = -1; - pp->base = (void __iomem *)base; + pp->base = base; spin_lock_init(&pp->conf_lock); memset(&pp->res, 0, sizeof(pp->res)); } else { @@ -249,7 +249,7 @@ void __init mv78xx0_pcie_init(int init_port0, int init_port1) if (init_port0) { add_pcie_port(0, 0, PCIE00_VIRT_BASE); - if (!orion_pcie_x4_mode((void __iomem *)PCIE00_VIRT_BASE)) { + if (!orion_pcie_x4_mode(PCIE00_VIRT_BASE)) { add_pcie_port(0, 1, PCIE01_VIRT_BASE); add_pcie_port(0, 2, PCIE02_VIRT_BASE); add_pcie_port(0, 3, PCIE03_VIRT_BASE); diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 7b270358536e..416d46ef7ebd 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -6,6 +6,8 @@ config ARCH_MVEBU select GENERIC_IRQ_CHIP select IRQ_DOMAIN select MULTI_IRQ_HANDLER + select PINCTRL + select PLAT_ORION select SPARSE_IRQ if ARCH_MVEBU @@ -13,13 +15,25 @@ if ARCH_MVEBU menu "Marvell SOC with device tree" config MACH_ARMADA_370_XP - bool "Marvell Armada 370 and Aramada XP boards" + bool select ARMADA_370_XP_TIMER select CPU_V7 + +config MACH_ARMADA_370 + bool "Marvell Armada 370 boards" + select MACH_ARMADA_370_XP + select PINCTRL_ARMADA_370 help + Say 'Y' here if you want your kernel to support boards based + on the Marvell Armada 370 SoC with device tree. - Say 'Y' here if you want your kernel to support boards based on - Marvell Armada 370 or Armada XP with device tree. +config MACH_ARMADA_XP + bool "Marvell Armada XP boards" + select MACH_ARMADA_370_XP + select PINCTRL_ARMADA_XP + help + Say 'Y' here if you want your kernel to support boards based + on the Marvell Armada XP SoC with device tree. endmenu diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index 6ea8998ab8f1..57f996b6aa0e 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@ -1,4 +1,5 @@ -ccflags-$(ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include +ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \ + -I$(srctree)/arch/arm/plat-orion/include obj-y += system-controller.o -obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o +obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o diff --git a/arch/arm/mach-mvebu/addr-map.c b/arch/arm/mach-mvebu/addr-map.c new file mode 100644 index 000000000000..fe454a4430be --- /dev/null +++ b/arch/arm/mach-mvebu/addr-map.c @@ -0,0 +1,134 @@ +/* + * Address map functions for Marvell 370 / XP SoCs + * + * Copyright (C) 2012 Marvell + * + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/mbus.h> +#include <linux/io.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <plat/addr-map.h> + +/* + * Generic Address Decode Windows bit settings + */ +#define ARMADA_XP_TARGET_DEV_BUS 1 +#define ARMADA_XP_ATTR_DEV_BOOTROM 0x1D +#define ARMADA_XP_TARGET_ETH1 3 +#define ARMADA_XP_TARGET_PCIE_0_2 4 +#define ARMADA_XP_TARGET_ETH0 7 +#define ARMADA_XP_TARGET_PCIE_1_3 8 + +#define ARMADA_370_TARGET_DEV_BUS 1 +#define ARMADA_370_ATTR_DEV_BOOTROM 0x1D +#define ARMADA_370_TARGET_PCIE_0 4 +#define ARMADA_370_TARGET_PCIE_1 8 + +#define ARMADA_WINDOW_8_PLUS_OFFSET 0x90 +#define ARMADA_SDRAM_ADDR_DECODING_OFFSET 0x180 + +static const struct __initdata orion_addr_map_info +armada_xp_addr_map_info[] = { + /* + * Window for the BootROM, needed for SMP on Armada XP + */ + { 0, 0xfff00000, SZ_1M, ARMADA_XP_TARGET_DEV_BUS, + ARMADA_XP_ATTR_DEV_BOOTROM, -1 }, + /* End marker */ + { -1, 0, 0, 0, 0, 0 }, +}; + +static const struct __initdata orion_addr_map_info +armada_370_addr_map_info[] = { + /* End marker */ + { -1, 0, 0, 0, 0, 0 }, +}; + +static struct of_device_id of_addr_decoding_controller_table[] = { + { .compatible = "marvell,armada-addr-decoding-controller" }, + { /* end of list */ }, +}; + +static void __iomem * +armada_cfg_base(const struct orion_addr_map_cfg *cfg, int win) +{ + unsigned int offset; + + /* The register layout is a bit annoying and the below code + * tries to cope with it. + * - At offset 0x0, there are the registers for the first 8 + * windows, with 4 registers of 32 bits per window (ctrl, + * base, remap low, remap high) + * - Then at offset 0x80, there is a hole of 0x10 bytes for + * the internal registers base address and internal units + * sync barrier register. + * - Then at offset 0x90, there the registers for 12 + * windows, with only 2 registers of 32 bits per window + * (ctrl, base). + */ + if (win < 8) + offset = (win << 4); + else + offset = ARMADA_WINDOW_8_PLUS_OFFSET + (win << 3); + + return cfg->bridge_virt_base + offset; +} + +static struct __initdata orion_addr_map_cfg addr_map_cfg = { + .num_wins = 20, + .remappable_wins = 8, + .win_cfg_base = armada_cfg_base, +}; + +static int __init armada_setup_cpu_mbus(void) +{ + struct device_node *np; + void __iomem *mbus_unit_addr_decoding_base; + void __iomem *sdram_addr_decoding_base; + + np = of_find_matching_node(NULL, of_addr_decoding_controller_table); + if (!np) + return -ENODEV; + + mbus_unit_addr_decoding_base = of_iomap(np, 0); + BUG_ON(!mbus_unit_addr_decoding_base); + + sdram_addr_decoding_base = + mbus_unit_addr_decoding_base + + ARMADA_SDRAM_ADDR_DECODING_OFFSET; + + addr_map_cfg.bridge_virt_base = mbus_unit_addr_decoding_base; + + /* + * Disable, clear and configure windows. + */ + if (of_machine_is_compatible("marvell,armadaxp")) + orion_config_wins(&addr_map_cfg, armada_xp_addr_map_info); + else if (of_machine_is_compatible("marvell,armada370")) + orion_config_wins(&addr_map_cfg, armada_370_addr_map_info); + else { + pr_err("Unsupported SoC\n"); + return -EINVAL; + } + + /* + * Setup MBUS dram target info. + */ + orion_setup_cpu_mbus_target(&addr_map_cfg, + sdram_addr_decoding_base); + return 0; +} + +/* Using a early_initcall is needed so that this initialization gets + * done before the SMP initialization, which requires the BootROM to + * be remapped. */ +early_initcall(armada_setup_cpu_mbus); diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c index b46418a8b352..49d791548ad6 100644 --- a/arch/arm/mach-mvebu/armada-370-xp.c +++ b/arch/arm/mach-mvebu/armada-370-xp.c @@ -25,7 +25,7 @@ static struct map_desc armada_370_xp_io_desc[] __initdata = { { - .virtual = ARMADA_370_XP_REGS_VIRT_BASE, + .virtual = (unsigned long) ARMADA_370_XP_REGS_VIRT_BASE, .pfn = __phys_to_pfn(ARMADA_370_XP_REGS_PHYS_BASE), .length = ARMADA_370_XP_REGS_SIZE, .type = MT_DEVICE, diff --git a/arch/arm/mach-mvebu/armada-370-xp.h b/arch/arm/mach-mvebu/armada-370-xp.h index 25f0ca8d7820..aac9bebc6b03 100644 --- a/arch/arm/mach-mvebu/armada-370-xp.h +++ b/arch/arm/mach-mvebu/armada-370-xp.h @@ -16,7 +16,7 @@ #define __MACH_ARMADA_370_XP_H #define ARMADA_370_XP_REGS_PHYS_BASE 0xd0000000 -#define ARMADA_370_XP_REGS_VIRT_BASE 0xfeb00000 +#define ARMADA_370_XP_REGS_VIRT_BASE IOMEM(0xfeb00000) #define ARMADA_370_XP_REGS_SIZE SZ_1M #endif /* __MACH_ARMADA_370_XP_H */ diff --git a/arch/arm/mach-mvebu/include/mach/gpio.h b/arch/arm/mach-mvebu/include/mach/gpio.h new file mode 100644 index 000000000000..40a8c178f10d --- /dev/null +++ b/arch/arm/mach-mvebu/include/mach/gpio.h @@ -0,0 +1 @@ +/* empty */ diff --git a/arch/arm/mach-nomadik/Kconfig b/arch/arm/mach-nomadik/Kconfig index 365879b47c0e..c744946ef022 100644 --- a/arch/arm/mach-nomadik/Kconfig +++ b/arch/arm/mach-nomadik/Kconfig @@ -4,8 +4,8 @@ menu "Nomadik boards" config MACH_NOMADIK_8815NHK bool "ST 8815 Nomadik Hardware Kit (evaluation board)" - select NOMADIK_8815 select HAS_MTU + select NOMADIK_8815 endmenu @@ -16,7 +16,7 @@ config I2C_BITBANG_8815NHK tristate "Driver for bit-bang busses found on the 8815 NHK" depends on I2C && MACH_NOMADIK_8815NHK depends on PINCTRL_NOMADIK - select I2C_ALGOBIT default y + select I2C_ALGOBIT endif diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig index cba3f7191cfc..903da8eb886c 100644 --- a/arch/arm/mach-omap1/Kconfig +++ b/arch/arm/mach-omap1/Kconfig @@ -8,15 +8,15 @@ comment "OMAP Core Type" config ARCH_OMAP730 depends on ARCH_OMAP1 bool "OMAP730 Based System" + select ARCH_OMAP_OTG select CPU_ARM926T select OMAP_MPU_TIMER - select ARCH_OMAP_OTG config ARCH_OMAP850 depends on ARCH_OMAP1 bool "OMAP850 Based System" - select CPU_ARM926T select ARCH_OMAP_OTG + select CPU_ARM926T config ARCH_OMAP15XX depends on ARCH_OMAP1 @@ -28,8 +28,8 @@ config ARCH_OMAP15XX config ARCH_OMAP16XX depends on ARCH_OMAP1 bool "OMAP16xx Based System" - select CPU_ARM926T select ARCH_OMAP_OTG + select CPU_ARM926T comment "OMAP Board Type" depends on ARCH_OMAP1 @@ -132,8 +132,8 @@ config MACH_OMAP_PALMTT config MACH_SX1 bool "Siemens SX1" - select I2C depends on ARCH_OMAP1 && ARCH_OMAP15XX + select I2C help Support for the Siemens SX1 phone. To boot the kernel, you'll need a SX1 compatible bootloader; check out diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c index 9518bf5996dc..e255164ff087 100644 --- a/arch/arm/mach-omap1/board-ams-delta.c +++ b/arch/arm/mach-omap1/board-ams-delta.c @@ -444,16 +444,28 @@ static struct omap1_cam_platform_data ams_delta_camera_platform_data = { .lclk_khz_max = 1334, /* results in 5fps CIF, 10fps QCIF */ }; +static struct platform_device ams_delta_audio_device = { + .name = "ams-delta-audio", + .id = -1, +}; + +static struct platform_device cx20442_codec_device = { + .name = "cx20442-codec", + .id = -1, +}; + static struct platform_device *ams_delta_devices[] __initdata = { &latch1_gpio_device, &latch2_gpio_device, &ams_delta_kp_device, &ams_delta_camera_device, + &ams_delta_audio_device, }; static struct platform_device *late_devices[] __initdata = { &ams_delta_nand_device, &ams_delta_lcd_device, + &cx20442_codec_device, }; static void __init ams_delta_init(void) diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c index 0cc54dd553e3..d3fec92c54cb 100644 --- a/arch/arm/mach-omap1/devices.c +++ b/arch/arm/mach-omap1/devices.c @@ -231,7 +231,7 @@ void __init omap1_init_mmc(struct omap_mmc_platform_data **mmc_data, omap_mmc_add("mmci-omap", i, base, size, irq, rx_req, tx_req, mmc_data[i]); - }; + } } #endif @@ -357,6 +357,33 @@ static inline void omap_init_uwire(void) {} #endif +#define OMAP1_RNG_BASE 0xfffe5000 + +static struct resource omap1_rng_resources[] = { + { + .start = OMAP1_RNG_BASE, + .end = OMAP1_RNG_BASE + 0x4f, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device omap1_rng_device = { + .name = "omap_rng", + .id = -1, + .num_resources = ARRAY_SIZE(omap1_rng_resources), + .resource = omap1_rng_resources, +}; + +static void omap1_init_rng(void) +{ + if (!cpu_is_omap16xx()) + return; + + (void) platform_device_register(&omap1_rng_device); +} + +/*-------------------------------------------------------------------------*/ + /* * This gets called after board-specific INIT_MACHINE, and initializes most * on-chip peripherals accessible on this board (except for few like USB): @@ -395,6 +422,7 @@ static int __init omap1_init_devices(void) omap_init_spi100k(); omap_init_sti(); omap_init_uwire(); + omap1_init_rng(); return 0; } diff --git a/arch/arm/mach-omap1/timer.c b/arch/arm/mach-omap1/timer.c index aa81593db1af..cdeb9d3ef640 100644 --- a/arch/arm/mach-omap1/timer.c +++ b/arch/arm/mach-omap1/timer.c @@ -141,7 +141,7 @@ static int __init omap1_dm_timer_init(void) pdata->set_timer_src = omap1_dm_timer_set_src; pdata->timer_capability = OMAP_TIMER_ALWON | - OMAP_TIMER_NEEDS_RESET; + OMAP_TIMER_NEEDS_RESET | OMAP_TIMER_HAS_DSP_IRQ; ret = platform_device_add_data(pdev, pdata, sizeof(*pdata)); if (ret) { diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index a6219eaf1f68..d669e227e00c 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -6,19 +6,18 @@ config ARCH_OMAP2PLUS_TYPICAL bool "Typical OMAP configuration" default y select AEABI - select REGULATOR - select PM_RUNTIME - select VFP - select NEON if ARCH_OMAP3 || ARCH_OMAP4 || SOC_OMAP5 - select SERIAL_OMAP - select SERIAL_OMAP_CONSOLE + select HIGHMEM select I2C select I2C_OMAP select MENELAUS if ARCH_OMAP2 + select NEON if ARCH_OMAP3 || ARCH_OMAP4 || SOC_OMAP5 + select PM_RUNTIME + select REGULATOR + select SERIAL_OMAP + select SERIAL_OMAP_CONSOLE select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4 select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4 - select HIGHMEM - select PINCTRL + select VFP help Compile a kernel suitable for booting most boards @@ -40,44 +39,44 @@ config ARCH_OMAP3 bool "TI OMAP3" depends on ARCH_OMAP2PLUS default y - select CPU_V7 - select USB_ARCH_HAS_EHCI if USB_SUPPORT select ARCH_HAS_OPP - select PM_RUNTIME if CPU_IDLE - select PM_OPP if PM select ARM_CPU_SUSPEND if PM + select CPU_V7 select MULTI_IRQ_HANDLER - select SOC_HAS_OMAP2_SDRC select OMAP_INTERCONNECT + select PM_OPP if PM + select PM_RUNTIME if CPU_IDLE + select SOC_HAS_OMAP2_SDRC + select USB_ARCH_HAS_EHCI if USB_SUPPORT config ARCH_OMAP4 bool "TI OMAP4" default y depends on ARCH_OMAP2PLUS + select ARCH_HAS_OPP + select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP + select ARM_CPU_SUSPEND if PM + select ARM_ERRATA_720789 + select ARM_GIC select CACHE_L2X0 select CPU_V7 - select ARM_GIC select HAVE_SMP select LOCAL_TIMERS if SMP + select OMAP_INTERCONNECT select PL310_ERRATA_588369 select PL310_ERRATA_727915 - select ARM_ERRATA_720789 - select ARCH_HAS_OPP - select PM_RUNTIME if CPU_IDLE select PM_OPP if PM + select PM_RUNTIME if CPU_IDLE select USB_ARCH_HAS_EHCI if USB_SUPPORT - select ARM_CPU_SUSPEND if PM - select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP - select OMAP_INTERCONNECT config SOC_OMAP5 bool "TI OMAP5" - select CPU_V7 + select ARM_ARCH_TIMER + select ARM_CPU_SUSPEND if PM select ARM_GIC + select CPU_V7 select HAVE_SMP - select ARM_CPU_SUSPEND if PM select SOC_HAS_REALTIME_COUNTER - select ARM_ARCH_TIMER comment "OMAP Core Type" depends on ARCH_OMAP2 @@ -109,8 +108,8 @@ config SOC_TI81XX config SOC_AM33XX bool "AM33XX support" default y - select CPU_V7 select ARM_CPU_SUSPEND if PM + select CPU_V7 select MULTI_IRQ_HANDLER config OMAP_PACKAGE_ZAF @@ -157,8 +156,8 @@ config MACH_OMAP_H4 bool "OMAP 2420 H4 board" depends on SOC_OMAP2420 default y - select OMAP_PACKAGE_ZAF select OMAP_DEBUG_DEVICES + select OMAP_PACKAGE_ZAF config MACH_OMAP_APOLLON bool "OMAP 2420 Apollon board" @@ -193,8 +192,8 @@ config MACH_OMAP_LDP config MACH_OMAP3530_LV_SOM bool "OMAP3 Logic 3530 LV SOM board" depends on ARCH_OMAP3 - select OMAP_PACKAGE_CBB default y + select OMAP_PACKAGE_CBB help Support for the LogicPD OMAP3530 SOM Development kit for full description please see the products webpage at @@ -203,8 +202,8 @@ config MACH_OMAP3530_LV_SOM config MACH_OMAP3_TORPEDO bool "OMAP3 Logic 35x Torpedo board" depends on ARCH_OMAP3 - select OMAP_PACKAGE_CBB default y + select OMAP_PACKAGE_CBB help Support for the LogicPD OMAP35x Torpedo Development kit for full description please see the products webpage at @@ -265,17 +264,17 @@ config MACH_NOKIA_N8X0 bool "Nokia N800/N810" depends on SOC_OMAP2420 default y - select OMAP_PACKAGE_ZAC select MACH_NOKIA_N800 select MACH_NOKIA_N810 select MACH_NOKIA_N810_WIMAX + select OMAP_PACKAGE_ZAC config MACH_NOKIA_RM680 bool "Nokia RM-680/696 board" depends on ARCH_OMAP3 default y - select OMAP_PACKAGE_CBB select MACH_NOKIA_RM696 + select OMAP_PACKAGE_CBB config MACH_NOKIA_RX51 bool "Nokia RX-51 board" @@ -288,20 +287,20 @@ config MACH_OMAP_ZOOM2 depends on ARCH_OMAP3 default y select OMAP_PACKAGE_CBB + select REGULATOR_FIXED_VOLTAGE if REGULATOR select SERIAL_8250 - select SERIAL_CORE_CONSOLE select SERIAL_8250_CONSOLE - select REGULATOR_FIXED_VOLTAGE if REGULATOR + select SERIAL_CORE_CONSOLE config MACH_OMAP_ZOOM3 bool "OMAP3630 Zoom3 board" depends on ARCH_OMAP3 default y select OMAP_PACKAGE_CBP + select REGULATOR_FIXED_VOLTAGE if REGULATOR select SERIAL_8250 - select SERIAL_CORE_CONSOLE select SERIAL_8250_CONSOLE - select REGULATOR_FIXED_VOLTAGE if REGULATOR + select SERIAL_CORE_CONSOLE config MACH_CM_T35 bool "CompuLab CM-T35/CM-T3730 modules" @@ -329,8 +328,8 @@ config MACH_IGEP0030 bool "IGEP OMAP3 module" depends on ARCH_OMAP3 default y - select OMAP_PACKAGE_CBB select MACH_IGEP0020 + select OMAP_PACKAGE_CBB config MACH_SBC3530 bool "OMAP3 SBC STALKER board" diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 7d6abda3b74e..fe40d9e488c9 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -179,6 +179,7 @@ obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o # EMU peripherals obj-$(CONFIG_OMAP3_EMU) += emu.o +obj-$(CONFIG_HW_PERF_EVENTS) += pmu.o obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o mailbox_mach-objs := mailbox.o diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index a88809a59ea9..3669c120c7e8 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -607,29 +607,6 @@ static void __init omap_sfh7741prox_init(void) __func__, OMAP4_SFH7741_ENABLE_GPIO, error); } -static struct gpio sdp4430_hdmi_gpios[] = { - { HDMI_GPIO_CT_CP_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ct_cp_hpd" }, - { HDMI_GPIO_LS_OE, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ls_oe" }, - { HDMI_GPIO_HPD, GPIOF_DIR_IN, "hdmi_gpio_hpd" }, -}; - -static int sdp4430_panel_enable_hdmi(struct omap_dss_device *dssdev) -{ - int status; - - status = gpio_request_array(sdp4430_hdmi_gpios, - ARRAY_SIZE(sdp4430_hdmi_gpios)); - if (status) - pr_err("%s: Cannot request HDMI GPIOs\n", __func__); - - return status; -} - -static void sdp4430_panel_disable_hdmi(struct omap_dss_device *dssdev) -{ - gpio_free_array(sdp4430_hdmi_gpios, ARRAY_SIZE(sdp4430_hdmi_gpios)); -} - static struct nokia_dsi_panel_data dsi1_panel = { .name = "taal", .reset_gpio = 102, @@ -650,29 +627,6 @@ static struct omap_dss_device sdp4430_lcd_device = { .phy.dsi = { .module = 0, }, - - .clocks = { - .dispc = { - .channel = { - /* Logic Clock = 172.8 MHz */ - .lck_div = 1, - /* Pixel Clock = 34.56 MHz */ - .pck_div = 5, - .lcd_clk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, - }, - .dispc_fclk_src = OMAP_DSS_CLK_SRC_FCK, - }, - - .dsi = { - .regn = 16, /* Fint = 2.4 MHz */ - .regm = 180, /* DDR Clock = 216 MHz */ - .regm_dispc = 5, /* PLL1_CLK1 = 172.8 MHz */ - .regm_dsi = 5, /* PLL1_CLK2 = 172.8 MHz */ - - .lp_clk_div = 10, /* LP Clock = 8.64 MHz */ - .dsi_fclk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, - }, - }, .channel = OMAP_DSS_CHANNEL_LCD, }; @@ -697,33 +651,12 @@ static struct omap_dss_device sdp4430_lcd2_device = { .module = 1, }, - - .clocks = { - .dispc = { - .channel = { - /* Logic Clock = 172.8 MHz */ - .lck_div = 1, - /* Pixel Clock = 34.56 MHz */ - .pck_div = 5, - .lcd_clk_src = OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, - }, - .dispc_fclk_src = OMAP_DSS_CLK_SRC_FCK, - }, - - .dsi = { - .regn = 16, /* Fint = 2.4 MHz */ - .regm = 180, /* DDR Clock = 216 MHz */ - .regm_dispc = 5, /* PLL1_CLK1 = 172.8 MHz */ - .regm_dsi = 5, /* PLL1_CLK2 = 172.8 MHz */ - - .lp_clk_div = 10, /* LP Clock = 8.64 MHz */ - .dsi_fclk_src = OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, - }, - }, .channel = OMAP_DSS_CHANNEL_LCD2, }; static struct omap_dss_hdmi_data sdp4430_hdmi_data = { + .ct_cp_hpd_gpio = HDMI_GPIO_CT_CP_HPD, + .ls_oe_gpio = HDMI_GPIO_LS_OE, .hpd_gpio = HDMI_GPIO_HPD, }; @@ -731,8 +664,6 @@ static struct omap_dss_device sdp4430_hdmi_device = { .name = "hdmi", .driver_name = "hdmi_panel", .type = OMAP_DISPLAY_TYPE_HDMI, - .platform_enable = sdp4430_panel_enable_hdmi, - .platform_disable = sdp4430_panel_disable_hdmi, .channel = OMAP_DSS_CHANNEL_DIGIT, .data = &sdp4430_hdmi_data, }; @@ -830,6 +761,32 @@ static struct omap_board_mux board_mux[] __initdata = { /* NIRQ2 for twl6040 */ OMAP4_MUX(SYS_NIRQ2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE), + /* GPIO_127 for twl6040 */ + OMAP4_MUX(HDQ_SIO, OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT), + /* McPDM */ + OMAP4_MUX(ABE_PDM_UL_DATA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), + OMAP4_MUX(ABE_PDM_DL_DATA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), + OMAP4_MUX(ABE_PDM_FRAME, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), + OMAP4_MUX(ABE_PDM_LB_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), + OMAP4_MUX(ABE_CLKS, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), + /* DMIC */ + OMAP4_MUX(ABE_DMIC_CLK1, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP4_MUX(ABE_DMIC_DIN1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + OMAP4_MUX(ABE_DMIC_DIN2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + OMAP4_MUX(ABE_DMIC_DIN3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + /* McBSP1 */ + OMAP4_MUX(ABE_MCBSP1_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + OMAP4_MUX(ABE_MCBSP1_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), + OMAP4_MUX(ABE_MCBSP1_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT | + OMAP_PULL_ENA), + OMAP4_MUX(ABE_MCBSP1_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + /* McBSP2 */ + OMAP4_MUX(ABE_MCBSP2_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + OMAP4_MUX(ABE_MCBSP2_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), + OMAP4_MUX(ABE_MCBSP2_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT | + OMAP_PULL_ENA), + OMAP4_MUX(ABE_MCBSP2_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + { .reg_offset = OMAP_MUX_TERMINATOR }, }; diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index 0d99c9110d01..e16289755f2e 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c @@ -263,6 +263,16 @@ static __init void am3517_evm_musb_init(void) usb_musb_init(&musb_board_data); } +static __init void am3517_evm_mcbsp1_init(void) +{ + u32 devconf0; + + /* McBSP1 CLKR/FSR signal to be connected to CLKX/FSX pin */ + devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); + devconf0 |= OMAP2_MCBSP1_CLKR_MASK | OMAP2_MCBSP1_FSR_MASK; + omap_ctrl_writel(devconf0, OMAP2_CONTROL_DEVCONF0); +} + static const struct usbhs_omap_board_data usbhs_bdata __initconst = { .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, #if defined(CONFIG_PANEL_SHARP_LQ043T1DG01) || \ @@ -366,6 +376,9 @@ static void __init am3517_evm_init(void) /* MUSB */ am3517_evm_musb_init(); + /* McBSP1 */ + am3517_evm_mcbsp1_init(); + /* MMC init function */ omap_hsmmc_init(mmc); } diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c index 3e2d76f05af4..cea3abace815 100644 --- a/arch/arm/mach-omap2/board-apollon.c +++ b/arch/arm/mach-omap2/board-apollon.c @@ -202,7 +202,7 @@ static inline void __init apollon_init_smc91x(void) return; } - clk_enable(gpmc_fck); + clk_prepare_enable(gpmc_fck); rate = clk_get_rate(gpmc_fck); eth_cs = APOLLON_ETH_CS; @@ -246,7 +246,7 @@ static inline void __init apollon_init_smc91x(void) gpmc_cs_free(APOLLON_ETH_CS); } out: - clk_disable(gpmc_fck); + clk_disable_unprepare(gpmc_fck); clk_put(gpmc_fck); } diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index 8ffd612c5e07..376d26eb601c 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -723,6 +723,7 @@ static void __init cm_t3x_common_init(void) cm_t35_init_ethernet(); cm_t35_init_led(); cm_t35_init_display(); + omap_twl4030_audio_init("cm-t3x"); usb_musb_init(NULL); cm_t35_init_usbh(); diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index 7bb8056d4388..1fd161e934c7 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -623,6 +623,7 @@ static void __init devkit8000_init(void) usbhs_init(&usbhs_bdata); omap_nand_flash_init(NAND_BUSWIDTH_16, devkit8000_nand_partitions, ARRAY_SIZE(devkit8000_nand_partitions)); + omap_twl4030_audio_init("omap3beagle"); /* Ensure SDRC pins are mux'd for self-refresh */ omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c index 0cabe61cd507..e642acf9cad0 100644 --- a/arch/arm/mach-omap2/board-flash.c +++ b/arch/arm/mach-omap2/board-flash.c @@ -218,7 +218,7 @@ void __init board_flash_init(struct flash_partitions partition_info[], if (onenandcs > GPMC_CS_NUM) onenandcs = cs; break; - }; + } cs++; } diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index f6c48dd764fe..8d04bf851af4 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c @@ -265,9 +265,9 @@ static inline void __init h4_init_debug(void) return; } - clk_enable(gpmc_fck); + clk_prepare_enable(gpmc_fck); rate = clk_get_rate(gpmc_fck); - clk_disable(gpmc_fck); + clk_disable_unprepare(gpmc_fck); clk_put(gpmc_fck); if (is_gpmc_muxed()) @@ -311,7 +311,7 @@ static inline void __init h4_init_debug(void) gpmc_cs_free(eth_cs); out: - clk_disable(gpmc_fck); + clk_disable_unprepare(gpmc_fck); clk_put(gpmc_fck); } diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index fb8bd837dd13..48d5e41dfbfa 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -625,6 +625,7 @@ static void __init igep_init(void) igep_flash_init(); igep_leds_init(); + omap_twl4030_audio_init("igep2"); /* * WLAN-BT combo module from MuRata which has a Marvell WLAN diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 68ff8d51973c..d41ab98890ff 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -24,6 +24,7 @@ #include <linux/input.h> #include <linux/gpio_keys.h> #include <linux/opp.h> +#include <linux/cpu.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> @@ -444,27 +445,31 @@ static struct omap_board_mux board_mux[] __initdata = { }; #endif -static void __init beagle_opp_init(void) +static int __init beagle_opp_init(void) { int r = 0; - /* Initialize the omap3 opp table */ - if (omap3_opp_init()) { + if (!machine_is_omap3_beagle()) + return 0; + + /* Initialize the omap3 opp table if not already created. */ + r = omap3_opp_init(); + if (IS_ERR_VALUE(r) && (r != -EEXIST)) { pr_err("%s: opp default init failed\n", __func__); - return; + return r; } /* Custom OPP enabled for all xM versions */ if (cpu_is_omap3630()) { struct device *mpu_dev, *iva_dev; - mpu_dev = omap_device_get_by_hwmod_name("mpu"); + mpu_dev = get_cpu_device(0); iva_dev = omap_device_get_by_hwmod_name("iva"); - if (!mpu_dev || !iva_dev) { + if (IS_ERR(mpu_dev) || IS_ERR(iva_dev)) { pr_err("%s: Aiee.. no mpu/dsp devices? %p %p\n", __func__, mpu_dev, iva_dev); - return; + return -ENODEV; } /* Enable MPU 1GHz and lower opps */ r = opp_enable(mpu_dev, 800000000); @@ -484,8 +489,9 @@ static void __init beagle_opp_init(void) opp_disable(iva_dev, 660000000); } } - return; + return 0; } +device_initcall(beagle_opp_init); static void __init omap3_beagle_init(void) { @@ -514,6 +520,7 @@ static void __init omap3_beagle_init(void) usbhs_init(&usbhs_bdata); omap_nand_flash_init(NAND_BUSWIDTH_16, omap3beagle_nand_partitions, ARRAY_SIZE(omap3beagle_nand_partitions)); + omap_twl4030_audio_init("omap3beagle"); /* Ensure msecure is mux'd to be able to set the RTC. */ omap_mux_init_signal("sys_drm_msecure", OMAP_PIN_OFF_OUTPUT_HIGH); @@ -521,8 +528,6 @@ static void __init omap3_beagle_init(void) /* Ensure SDRC pins are mux'd for self-refresh */ omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); - - beagle_opp_init(); } MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board") diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index c64e565bdef5..b9b776b6c954 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -88,11 +88,10 @@ enum { static u8 omap3_evm_version; -u8 get_omap3_evm_rev(void) +static u8 get_omap3_evm_rev(void) { return omap3_evm_version; } -EXPORT_SYMBOL(get_omap3_evm_rev); static void __init omap3_evm_get_revision(void) { @@ -739,6 +738,7 @@ static void __init omap3_evm_init(void) omap3evm_init_smsc911x(); omap3_evm_display_init(); omap3_evm_wl12xx_init(); + omap_twl4030_audio_init("omap3evm"); } MACHINE_START(OMAP3EVM, "OMAP3 EVM") diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index c7f3d026e6d4..731235eb319e 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c @@ -48,11 +48,6 @@ #include <video/omap-panel-tfp410.h> #include <linux/platform_data/spi-omap2-mcspi.h> -#include <linux/input/matrix_keypad.h> -#include <linux/spi/spi.h> -#include <linux/interrupt.h> -#include <linux/smsc911x.h> -#include <linux/i2c/at24.h> #include "sdram-micron-mt46h32m32lf-6.h" #include "mux.h" diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index e0dd70b9d917..bfcd397e233c 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -171,7 +171,7 @@ static void __init omap4_ehci_init(void) return; } clk_set_rate(phy_ref_clk, 19200000); - clk_enable(phy_ref_clk); + clk_prepare_enable(phy_ref_clk); /* disable the power to the usb hub prior to init and reset phy+hub */ ret = gpio_request_array(panda_ehci_gpios, @@ -247,8 +247,7 @@ static struct platform_device omap_vwlan_device = { }; static struct wl12xx_platform_data omap_panda_wlan_data __initdata = { - /* PANDA ref clock is 38.4 MHz */ - .board_ref_clock = 2, + .board_ref_clock = WL12XX_REFCLOCK_38, /* 38.4 MHz */ }; static struct twl6040_codec_data twl6040_codec = { @@ -388,6 +387,21 @@ static struct omap_board_mux board_mux[] __initdata = { /* NIRQ2 for twl6040 */ OMAP4_MUX(SYS_NIRQ2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE), + /* GPIO_127 for twl6040 */ + OMAP4_MUX(HDQ_SIO, OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT), + /* McPDM */ + OMAP4_MUX(ABE_PDM_UL_DATA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), + OMAP4_MUX(ABE_PDM_DL_DATA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), + OMAP4_MUX(ABE_PDM_FRAME, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), + OMAP4_MUX(ABE_PDM_LB_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), + OMAP4_MUX(ABE_CLKS, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), + /* McBSP1 */ + OMAP4_MUX(ABE_MCBSP1_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + OMAP4_MUX(ABE_MCBSP1_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), + OMAP4_MUX(ABE_MCBSP1_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT | + OMAP_PULL_ENA), + OMAP4_MUX(ABE_MCBSP1_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + { .reg_offset = OMAP_MUX_TERMINATOR }, }; @@ -414,30 +428,9 @@ static struct omap_dss_device omap4_panda_dvi_device = { .channel = OMAP_DSS_CHANNEL_LCD2, }; -static struct gpio panda_hdmi_gpios[] = { - { HDMI_GPIO_CT_CP_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ct_cp_hpd" }, - { HDMI_GPIO_LS_OE, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ls_oe" }, - { HDMI_GPIO_HPD, GPIOF_DIR_IN, "hdmi_gpio_hpd" }, -}; - -static int omap4_panda_panel_enable_hdmi(struct omap_dss_device *dssdev) -{ - int status; - - status = gpio_request_array(panda_hdmi_gpios, - ARRAY_SIZE(panda_hdmi_gpios)); - if (status) - pr_err("Cannot request HDMI GPIOs\n"); - - return status; -} - -static void omap4_panda_panel_disable_hdmi(struct omap_dss_device *dssdev) -{ - gpio_free_array(panda_hdmi_gpios, ARRAY_SIZE(panda_hdmi_gpios)); -} - static struct omap_dss_hdmi_data omap4_panda_hdmi_data = { + .ct_cp_hpd_gpio = HDMI_GPIO_CT_CP_HPD, + .ls_oe_gpio = HDMI_GPIO_LS_OE, .hpd_gpio = HDMI_GPIO_HPD, }; @@ -445,8 +438,6 @@ static struct omap_dss_device omap4_panda_hdmi_device = { .name = "hdmi", .driver_name = "hdmi_panel", .type = OMAP_DISPLAY_TYPE_HDMI, - .platform_enable = omap4_panda_panel_enable_hdmi, - .platform_disable = omap4_panda_panel_disable_hdmi, .channel = OMAP_DSS_CHANNEL_DIGIT, .data = &omap4_panda_hdmi_data, }; diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index 2e7f24030fc9..b700685762b5 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c @@ -504,6 +504,7 @@ static void __init overo_init(void) overo_display_init(); overo_init_led(); overo_init_keys(); + omap_twl4030_audio_init("overo"); /* Ensure SDRC pins are mux'd for self-refresh */ omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index 3945c5017085..020e03c95bfe 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -33,6 +33,7 @@ #include "common.h" #include <plat/dma.h> #include <plat/gpmc.h> +#include <plat/omap-pm.h> #include "gpmc-smc91x.h" #include "board-rx51.h" @@ -46,6 +47,10 @@ #include <../drivers/staging/iio/light/tsl2563.h> #include <linux/lis3lv02d.h> +#if defined(CONFIG_IR_RX51) || defined(CONFIG_IR_RX51_MODULE) +#include <media/ir-rx51.h> +#endif + #include "mux.h" #include "hsmmc.h" #include "common-board-devices.h" @@ -743,7 +748,7 @@ static struct radio_si4713_platform_data rx51_si4713_data __initdata_or_module = .subdev_board_info = &rx51_si4713_board_info, }; -static struct platform_device rx51_si4713_dev = { +static struct platform_device rx51_si4713_dev __initdata_or_module = { .name = "radio-si4713", .id = -1, .dev = { @@ -1217,6 +1222,30 @@ static void __init rx51_init_tsc2005(void) gpio_to_irq(RX51_TSC2005_IRQ_GPIO); } +#if defined(CONFIG_IR_RX51) || defined(CONFIG_IR_RX51_MODULE) +static struct lirc_rx51_platform_data rx51_lirc_data = { + .set_max_mpu_wakeup_lat = omap_pm_set_max_mpu_wakeup_lat, + .pwm_timer = 9, /* Use GPT 9 for CIR */ +}; + +static struct platform_device rx51_lirc_device = { + .name = "lirc_rx51", + .id = -1, + .dev = { + .platform_data = &rx51_lirc_data, + }, +}; + +static void __init rx51_init_lirc(void) +{ + platform_device_register(&rx51_lirc_device); +} +#else +static void __init rx51_init_lirc(void) +{ +} +#endif + void __init rx51_peripherals_init(void) { rx51_i2c_init(); @@ -1227,6 +1256,7 @@ void __init rx51_peripherals_init(void) rx51_init_wl1251(); rx51_init_tsc2005(); rx51_init_si4713(); + rx51_init_lirc(); spi_register_board_info(rx51_peripherals_spi_board_info, ARRAY_SIZE(rx51_peripherals_spi_board_info)); diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c index 6bcc107b9fc3..c166fe1fdff9 100644 --- a/arch/arm/mach-omap2/board-zoom-peripherals.c +++ b/arch/arm/mach-omap2/board-zoom-peripherals.c @@ -35,6 +35,7 @@ #include "common-board-devices.h" #define OMAP_ZOOM_WLAN_PMENA_GPIO (101) +#define ZOOM2_HEADSET_EXTMUTE_GPIO (153) #define OMAP_ZOOM_WLAN_IRQ_GPIO (162) #define LCD_PANEL_ENABLE_GPIO (7 + OMAP_MAX_GPIO_LINES) @@ -194,8 +195,7 @@ static struct platform_device omap_vwlan_device = { }; static struct wl12xx_platform_data omap_zoom_wlan_data __initdata = { - /* ZOOM ref clock is 26 MHz */ - .board_ref_clock = 1, + .board_ref_clock = WL12XX_REFCLOCK_26, /* 26 MHz */ }; static struct omap2_hsmmc_info mmc[] = { @@ -245,12 +245,6 @@ static int zoom_twl_gpio_setup(struct device *dev, return ret; } -/* EXTMUTE callback function */ -static void zoom2_set_hs_extmute(int mute) -{ - gpio_set_value(ZOOM2_HEADSET_EXTMUTE_GPIO, mute); -} - static struct twl4030_gpio_platform_data zoom_gpio_data = { .setup = zoom_twl_gpio_setup, }; @@ -277,7 +271,7 @@ static int __init omap_i2c_init(void) codec_data->ramp_delay_value = 3; /* 161 ms */ codec_data->hs_extmute = 1; - codec_data->set_hs_extmute = zoom2_set_hs_extmute; + codec_data->hs_extmute_gpio = ZOOM2_HEADSET_EXTMUTE_GPIO; } omap_pmic_init(1, 2400, "twl5030", 7 + OMAP_INTC_START, &zoom_twldata); omap_register_i2c_bus(2, 400, NULL, 0); diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c index b19a1f7234ae..c2d15212d64d 100644 --- a/arch/arm/mach-omap2/clkt2xxx_apll.c +++ b/arch/arm/mach-omap2/clkt2xxx_apll.c @@ -59,7 +59,7 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask) omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); omap2_cm_wait_idlest(cm_idlest_pll, status_mask, - OMAP24XX_CM_IDLEST_VAL, clk->name); + OMAP24XX_CM_IDLEST_VAL, __clk_get_name(clk)); /* * REVISIT: Should we return an error code if omap2_wait_clock_ready() diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c index cabcfdba5246..3524f0e7b6d5 100644 --- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c +++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c @@ -68,14 +68,15 @@ unsigned long omap2_table_mpu_recalc(struct clk *clk) long omap2_round_to_table_rate(struct clk *clk, unsigned long rate) { const struct prcm_config *ptr; - long highest_rate; + long highest_rate, sys_clk_rate; highest_rate = -EINVAL; + sys_clk_rate = __clk_get_rate(sclk); for (ptr = rate_table; ptr->mpu_speed; ptr++) { if (!(ptr->flags & cpu_mask)) continue; - if (ptr->xtal_speed != sclk->rate) + if (ptr->xtal_speed != sys_clk_rate) continue; highest_rate = ptr->mpu_speed; @@ -94,12 +95,15 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate) const struct prcm_config *prcm; unsigned long found_speed = 0; unsigned long flags; + long sys_clk_rate; + + sys_clk_rate = __clk_get_rate(sclk); for (prcm = rate_table; prcm->mpu_speed; prcm++) { if (!(prcm->flags & cpu_mask)) continue; - if (prcm->xtal_speed != sclk->rate) + if (prcm->xtal_speed != sys_clk_rate) continue; if (prcm->mpu_speed <= rate) { diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c index 298887b5bf66..7c6da2f731dc 100644 --- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c +++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c @@ -56,6 +56,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) struct omap_sdrc_params *sdrc_cs0; struct omap_sdrc_params *sdrc_cs1; int ret; + unsigned long clkrate; if (!clk || !rate) return -EINVAL; @@ -64,11 +65,12 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) if (validrate != rate) return -EINVAL; - sdrcrate = sdrc_ick_p->rate; - if (rate > clk->rate) - sdrcrate <<= ((rate / clk->rate) >> 1); + sdrcrate = __clk_get_rate(sdrc_ick_p); + clkrate = __clk_get_rate(clk); + if (rate > clkrate) + sdrcrate <<= ((rate / clkrate) >> 1); else - sdrcrate >>= ((clk->rate / rate) >> 1); + sdrcrate >>= ((clkrate / rate) >> 1); ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1); if (ret) @@ -82,7 +84,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) /* * XXX This only needs to be done when the CPU frequency changes */ - _mpurate = arm_fck_p->rate / CYCLES_PER_MHZ; + _mpurate = __clk_get_rate(arm_fck_p) / CYCLES_PER_MHZ; c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT; c += 1; /* for safety */ c *= SDRC_MPURATE_LOOPS; @@ -90,8 +92,8 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) if (c == 0) c = 1; - pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate, - validrate); + pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", + clkrate, validrate); pr_debug("clock: SDRC CS0 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n", sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, sdrc_cs0->actim_ctrlb, sdrc_cs0->mr); @@ -102,14 +104,14 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) if (sdrc_cs1) omap3_configure_core_dpll( - new_div, unlock_dll, c, rate > clk->rate, + new_div, unlock_dll, c, rate > clkrate, sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, sdrc_cs0->actim_ctrlb, sdrc_cs0->mr, sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla, sdrc_cs1->actim_ctrlb, sdrc_cs1->mr); else omap3_configure_core_dpll( - new_div, unlock_dll, c, rate > clk->rate, + new_div, unlock_dll, c, rate > clkrate, sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, sdrc_cs0->actim_ctrlb, sdrc_cs0->mr, 0, 0, 0, 0); diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c index 19a980956d44..3ff22114d702 100644 --- a/arch/arm/mach-omap2/clkt_clksel.c +++ b/arch/arm/mach-omap2/clkt_clksel.c @@ -72,7 +72,7 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk, if (!clks->parent) { /* This indicates a data problem */ WARN(1, "clock: %s: could not find parent clock %s in clksel array\n", - clk->name, src_clk->name); + __clk_get_name(clk), __clk_get_name(src_clk)); return NULL; } @@ -127,7 +127,8 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk, if (max_div == 0) { /* This indicates an error in the clksel data */ WARN(1, "clock: %s: could not find divisor for parent %s\n", - clk->name, src_clk->parent->name); + __clk_get_name(clk), + __clk_get_name(__clk_get_parent(src_clk))); return 0; } @@ -176,8 +177,10 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val) { const struct clksel *clks; const struct clksel_rate *clkr; + struct clk *parent; - clks = _get_clksel_by_parent(clk, clk->parent); + parent = __clk_get_parent(clk); + clks = _get_clksel_by_parent(clk, parent); if (!clks) return 0; @@ -191,8 +194,8 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val) if (!clkr->div) { /* This indicates a data error */ - WARN(1, "clock: %s: could not find fieldval %d parent %s\n", - clk->name, field_val, clk->parent->name); + WARN(1, "clock: %s: could not find fieldval %d for parent %s\n", + __clk_get_name(clk), field_val, __clk_get_name(parent)); return 0; } @@ -213,11 +216,13 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div) { const struct clksel *clks; const struct clksel_rate *clkr; + struct clk *parent; /* should never happen */ WARN_ON(div == 0); - clks = _get_clksel_by_parent(clk, clk->parent); + parent = __clk_get_parent(clk); + clks = _get_clksel_by_parent(clk, parent); if (!clks) return ~0; @@ -230,8 +235,8 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div) } if (!clkr->div) { - pr_err("clock: %s: could not find divisor %d parent %s\n", - clk->name, div, clk->parent->name); + pr_err("clock: %s: could not find divisor %d for parent %s\n", + __clk_get_name(clk), div, __clk_get_name(parent)); return ~0; } @@ -281,16 +286,23 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, const struct clksel *clks; const struct clksel_rate *clkr; u32 last_div = 0; + struct clk *parent; + unsigned long parent_rate; + const char *clk_name; + + parent = __clk_get_parent(clk); + parent_rate = __clk_get_rate(parent); + clk_name = __clk_get_name(clk); if (!clk->clksel || !clk->clksel_mask) return ~0; pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n", - clk->name, target_rate); + clk_name, target_rate); *new_div = 1; - clks = _get_clksel_by_parent(clk, clk->parent); + clks = _get_clksel_by_parent(clk, parent); if (!clks) return ~0; @@ -300,29 +312,29 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, /* Sanity check */ if (clkr->div <= last_div) - pr_err("clock: %s: clksel_rate table not sorted", - clk->name); + pr_err("clock: %s: clksel_rate table not sorted\n", + clk_name); last_div = clkr->div; - test_rate = clk->parent->rate / clkr->div; + test_rate = parent_rate / clkr->div; if (test_rate <= target_rate) break; /* found it */ } if (!clkr->div) { - pr_err("clock: %s: could not find divisor for target rate %ld parent %s\n", - clk->name, target_rate, clk->parent->name); + pr_err("clock: %s: could not find divisor for target rate %ld for parent %s\n", + clk_name, target_rate, __clk_get_name(parent)); return ~0; } *new_div = clkr->div; pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div, - (clk->parent->rate / clkr->div)); + (parent_rate / clkr->div)); - return clk->parent->rate / clkr->div; + return parent_rate / clkr->div; } /* @@ -344,10 +356,15 @@ void omap2_init_clksel_parent(struct clk *clk) const struct clksel *clks; const struct clksel_rate *clkr; u32 r, found = 0; + struct clk *parent; + const char *clk_name; if (!clk->clksel || !clk->clksel_mask) return; + parent = __clk_get_parent(clk); + clk_name = __clk_get_name(clk); + r = __raw_readl(clk->clksel_reg) & clk->clksel_mask; r >>= __ffs(clk->clksel_mask); @@ -357,13 +374,15 @@ void omap2_init_clksel_parent(struct clk *clk) continue; if (clkr->val == r) { - if (clk->parent != clks->parent) { + if (parent != clks->parent) { pr_debug("clock: %s: inited parent to %s (was %s)\n", - clk->name, clks->parent->name, - ((clk->parent) ? - clk->parent->name : "NULL")); + clk_name, + __clk_get_name(clks->parent), + ((parent) ? + __clk_get_name(parent) : + "NULL")); clk_reparent(clk, clks->parent); - }; + } found = 1; } } @@ -371,7 +390,7 @@ void omap2_init_clksel_parent(struct clk *clk) /* This indicates a data error */ WARN(!found, "clock: %s: init parent: could not find regval %0x\n", - clk->name, r); + clk_name, r); return; } @@ -389,15 +408,17 @@ unsigned long omap2_clksel_recalc(struct clk *clk) { unsigned long rate; u32 div = 0; + struct clk *parent; div = _read_divisor(clk); if (div == 0) - return clk->rate; + return __clk_get_rate(clk); - rate = clk->parent->rate / div; + parent = __clk_get_parent(clk); + rate = __clk_get_rate(parent) / div; - pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n", clk->name, - rate, div); + pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n", + __clk_get_name(clk), rate, div); return rate; } @@ -452,9 +473,10 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) _write_clksel_reg(clk, field_val); - clk->rate = clk->parent->rate / new_div; + clk->rate = __clk_get_rate(__clk_get_parent(clk)) / new_div; - pr_debug("clock: %s: set rate to %ld\n", clk->name, clk->rate); + pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(clk), + __clk_get_rate(clk)); return 0; } @@ -496,13 +518,15 @@ int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent) clk_reparent(clk, new_parent); /* CLKSEL clocks follow their parents' rates, divided by a divisor */ - clk->rate = new_parent->rate; + clk->rate = __clk_get_rate(new_parent); if (parent_div > 0) - clk->rate /= parent_div; + __clk_get_rate(clk) /= parent_div; pr_debug("clock: %s: set parent to %s (new rate %ld)\n", - clk->name, clk->parent->name, clk->rate); + __clk_get_name(clk), + __clk_get_name(__clk_get_parent(clk)), + __clk_get_rate(clk)); return 0; } diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c index 83b658bf385a..80411142f482 100644 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ b/arch/arm/mach-omap2/clkt_dpll.c @@ -87,7 +87,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n) dd = clk->dpll_data; /* DPLL divider must result in a valid jitter correction val */ - fint = clk->parent->rate / n; + fint = __clk_get_rate(__clk_get_parent(clk)) / n; if (cpu_is_omap24xx()) { /* Should not be called for OMAP2, so warn if it is called */ @@ -252,16 +252,16 @@ u32 omap2_get_dpll_rate(struct clk *clk) if (cpu_is_omap24xx()) { if (v == OMAP2XXX_EN_DPLL_LPBYPASS || v == OMAP2XXX_EN_DPLL_FRBYPASS) - return dd->clk_bypass->rate; + return __clk_get_rate(dd->clk_bypass); } else if (cpu_is_omap34xx()) { if (v == OMAP3XXX_EN_DPLL_LPBYPASS || v == OMAP3XXX_EN_DPLL_FRBYPASS) - return dd->clk_bypass->rate; + return __clk_get_rate(dd->clk_bypass); } else if (soc_is_am33xx() || cpu_is_omap44xx()) { if (v == OMAP4XXX_EN_DPLL_LPBYPASS || v == OMAP4XXX_EN_DPLL_FRBYPASS || v == OMAP4XXX_EN_DPLL_MNBYPASS) - return dd->clk_bypass->rate; + return __clk_get_rate(dd->clk_bypass); } v = __raw_readl(dd->mult_div1_reg); @@ -270,7 +270,7 @@ u32 omap2_get_dpll_rate(struct clk *clk) dpll_div = v & dd->div1_mask; dpll_div >>= __ffs(dd->div1_mask); - dpll_clk = (long long)dd->clk_ref->rate * dpll_mult; + dpll_clk = (long long) __clk_get_rate(dd->clk_ref) * dpll_mult; do_div(dpll_clk, dpll_div + 1); return dpll_clk; @@ -296,16 +296,20 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) unsigned long scaled_rt_rp; unsigned long new_rate = 0; struct dpll_data *dd; + unsigned long ref_rate; + const char *clk_name; if (!clk || !clk->dpll_data) return ~0; dd = clk->dpll_data; + ref_rate = __clk_get_rate(dd->clk_ref); + clk_name = __clk_get_name(clk); pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n", - clk->name, target_rate); + clk_name, target_rate); - scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR); + scaled_rt_rp = target_rate / (ref_rate / DPLL_SCALE_FACTOR); scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR; dd->last_rounded_rate = 0; @@ -332,14 +336,14 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) break; r = _dpll_test_mult(&m, n, &new_rate, target_rate, - dd->clk_ref->rate); + ref_rate); /* m can't be set low enough for this n - try with a larger n */ if (r == DPLL_MULT_UNDERFLOW) continue; pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n", - clk->name, m, n, new_rate); + clk_name, m, n, new_rate); if (target_rate == new_rate) { dd->last_rounded_m = m; @@ -350,8 +354,8 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) } if (target_rate != new_rate) { - pr_debug("clock: %s: cannot round to rate %ld\n", clk->name, - target_rate); + pr_debug("clock: %s: cannot round to rate %ld\n", + clk_name, target_rate); return ~0; } diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index e97f98ffe8b2..961ac8f7e13d 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -78,7 +78,7 @@ static void _omap2_module_wait_ready(struct clk *clk) clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val); omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), idlest_val, - clk->name); + __clk_get_name(clk)); } /* Public functions */ @@ -94,18 +94,21 @@ static void _omap2_module_wait_ready(struct clk *clk) void omap2_init_clk_clkdm(struct clk *clk) { struct clockdomain *clkdm; + const char *clk_name; if (!clk->clkdm_name) return; + clk_name = __clk_get_name(clk); + clkdm = clkdm_lookup(clk->clkdm_name); if (clkdm) { pr_debug("clock: associated clk %s to clkdm %s\n", - clk->name, clk->clkdm_name); + clk_name, clk->clkdm_name); clk->clkdm = clkdm; } else { pr_debug("clock: could not associate clk %s to clkdm %s\n", - clk->name, clk->clkdm_name); + clk_name, clk->clkdm_name); } } diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index 12c178dbc9f5..c3cde1a2b6de 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c @@ -1804,6 +1804,7 @@ static struct omap_clk omap2420_clks[] = { CLK(NULL, "gfx_ick", &gfx_ick, CK_242X), /* DSS domain clocks */ CLK("omapdss_dss", "ick", &dss_ick, CK_242X), + CLK(NULL, "dss_ick", &dss_ick, CK_242X), CLK(NULL, "dss1_fck", &dss1_fck, CK_242X), CLK(NULL, "dss2_fck", &dss2_fck, CK_242X), CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_242X), @@ -1843,12 +1844,16 @@ static struct omap_clk omap2420_clks[] = { CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X), CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X), CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X), + CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_242X), CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_242X), CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X), + CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_242X), CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_242X), CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X), + CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_242X), CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_242X), CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X), + CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_242X), CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_242X), CLK(NULL, "uart1_ick", &uart1_ick, CK_242X), CLK(NULL, "uart1_fck", &uart1_fck, CK_242X), @@ -1859,12 +1864,15 @@ static struct omap_clk omap2420_clks[] = { CLK(NULL, "gpios_ick", &gpios_ick, CK_242X), CLK(NULL, "gpios_fck", &gpios_fck, CK_242X), CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X), + CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_242X), CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_242X), CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X), CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X), CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X), CLK("omap24xxcam", "fck", &cam_fck, CK_242X), + CLK(NULL, "cam_fck", &cam_fck, CK_242X), CLK("omap24xxcam", "ick", &cam_ick, CK_242X), + CLK(NULL, "cam_ick", &cam_ick, CK_242X), CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_242X), CLK(NULL, "wdt4_ick", &wdt4_ick, CK_242X), CLK(NULL, "wdt4_fck", &wdt4_fck, CK_242X), @@ -1873,16 +1881,22 @@ static struct omap_clk omap2420_clks[] = { CLK(NULL, "mspro_ick", &mspro_ick, CK_242X), CLK(NULL, "mspro_fck", &mspro_fck, CK_242X), CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X), + CLK(NULL, "mmc_ick", &mmc_ick, CK_242X), CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X), + CLK(NULL, "mmc_fck", &mmc_fck, CK_242X), CLK(NULL, "fac_ick", &fac_ick, CK_242X), CLK(NULL, "fac_fck", &fac_fck, CK_242X), CLK(NULL, "eac_ick", &eac_ick, CK_242X), CLK(NULL, "eac_fck", &eac_fck, CK_242X), CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X), + CLK(NULL, "hdq_ick", &hdq_ick, CK_242X), CLK("omap_hdq.0", "fck", &hdq_fck, CK_242X), + CLK(NULL, "hdq_fck", &hdq_fck, CK_242X), CLK("omap_i2c.1", "ick", &i2c1_ick, CK_242X), + CLK(NULL, "i2c1_ick", &i2c1_ick, CK_242X), CLK(NULL, "i2c1_fck", &i2c1_fck, CK_242X), CLK("omap_i2c.2", "ick", &i2c2_ick, CK_242X), + CLK(NULL, "i2c2_ick", &i2c2_ick, CK_242X), CLK(NULL, "i2c2_fck", &i2c2_fck, CK_242X), CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X), CLK(NULL, "sdma_fck", &sdma_fck, CK_242X), @@ -1892,14 +1906,18 @@ static struct omap_clk omap2420_clks[] = { CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X), CLK(NULL, "des_ick", &des_ick, CK_242X), CLK("omap-sham", "ick", &sha_ick, CK_242X), + CLK(NULL, "sha_ick", &sha_ick, CK_242X), CLK("omap_rng", "ick", &rng_ick, CK_242X), + CLK(NULL, "rng_ick", &rng_ick, CK_242X), CLK("omap-aes", "ick", &aes_ick, CK_242X), + CLK(NULL, "aes_ick", &aes_ick, CK_242X), CLK(NULL, "pka_ick", &pka_ick, CK_242X), CLK(NULL, "usb_fck", &usb_fck, CK_242X), CLK("musb-hdrc", "fck", &osc_ck, CK_242X), - CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_243X), - CLK(NULL, "timer_sys_ck", &sys_ck, CK_243X), - CLK(NULL, "timer_ext_ck", &alt_ck, CK_243X), + CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_242X), + CLK(NULL, "timer_sys_ck", &sys_ck, CK_242X), + CLK(NULL, "timer_ext_ck", &alt_ck, CK_242X), + CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_242X), }; /* diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c index 7ea91398217a..22404fe435e7 100644 --- a/arch/arm/mach-omap2/clock2430_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c @@ -1888,6 +1888,7 @@ static struct omap_clk omap2430_clks[] = { CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), /* DSS domain clocks */ CLK("omapdss_dss", "ick", &dss_ick, CK_243X), + CLK(NULL, "dss_ick", &dss_ick, CK_243X), CLK(NULL, "dss1_fck", &dss1_fck, CK_243X), CLK(NULL, "dss2_fck", &dss2_fck, CK_243X), CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X), @@ -1927,20 +1928,28 @@ static struct omap_clk omap2430_clks[] = { CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X), CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X), CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X), + CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_243X), CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_243X), CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X), + CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_243X), CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_243X), CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X), + CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_243X), CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_243X), CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X), + CLK(NULL, "mcbsp4_ick", &mcbsp4_ick, CK_243X), CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_243X), CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X), + CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_243X), CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_243X), CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X), + CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_243X), CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_243X), CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X), + CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_243X), CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_243X), CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X), + CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_243X), CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_243X), CLK(NULL, "uart1_ick", &uart1_ick, CK_243X), CLK(NULL, "uart1_fck", &uart1_fck, CK_243X), @@ -1951,13 +1960,16 @@ static struct omap_clk omap2430_clks[] = { CLK(NULL, "gpios_ick", &gpios_ick, CK_243X), CLK(NULL, "gpios_fck", &gpios_fck, CK_243X), CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X), + CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_243X), CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_243X), CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X), CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X), CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X), CLK(NULL, "icr_ick", &icr_ick, CK_243X), CLK("omap24xxcam", "fck", &cam_fck, CK_243X), + CLK(NULL, "cam_fck", &cam_fck, CK_243X), CLK("omap24xxcam", "ick", &cam_ick, CK_243X), + CLK(NULL, "cam_ick", &cam_ick, CK_243X), CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X), CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X), CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X), @@ -1966,10 +1978,14 @@ static struct omap_clk omap2430_clks[] = { CLK(NULL, "fac_ick", &fac_ick, CK_243X), CLK(NULL, "fac_fck", &fac_fck, CK_243X), CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X), + CLK(NULL, "hdq_ick", &hdq_ick, CK_243X), CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X), + CLK(NULL, "hdq_fck", &hdq_fck, CK_243X), CLK("omap_i2c.1", "ick", &i2c1_ick, CK_243X), + CLK(NULL, "i2c1_ick", &i2c1_ick, CK_243X), CLK(NULL, "i2chs1_fck", &i2chs1_fck, CK_243X), CLK("omap_i2c.2", "ick", &i2c2_ick, CK_243X), + CLK(NULL, "i2c2_ick", &i2c2_ick, CK_243X), CLK(NULL, "i2chs2_fck", &i2chs2_fck, CK_243X), CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X), CLK(NULL, "sdma_fck", &sdma_fck, CK_243X), @@ -1978,22 +1994,29 @@ static struct omap_clk omap2430_clks[] = { CLK(NULL, "des_ick", &des_ick, CK_243X), CLK("omap-sham", "ick", &sha_ick, CK_243X), CLK("omap_rng", "ick", &rng_ick, CK_243X), + CLK(NULL, "rng_ick", &rng_ick, CK_243X), CLK("omap-aes", "ick", &aes_ick, CK_243X), CLK(NULL, "pka_ick", &pka_ick, CK_243X), CLK(NULL, "usb_fck", &usb_fck, CK_243X), CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X), + CLK(NULL, "usbhs_ick", &usbhs_ick, CK_243X), CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X), + CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_243X), CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_243X), CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X), + CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_243X), CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_243X), CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X), CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X), CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X), CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X), + CLK(NULL, "mmchsdb1_fck", &mmchsdb1_fck, CK_243X), CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X), + CLK(NULL, "mmchsdb2_fck", &mmchsdb2_fck, CK_243X), CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_243X), CLK(NULL, "timer_sys_ck", &sys_ck, CK_243X), CLK(NULL, "timer_ext_ck", &alt_ck, CK_243X), + CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_243X), }; /* diff --git a/arch/arm/mach-omap2/clock33xx_data.c b/arch/arm/mach-omap2/clock33xx_data.c index 2026311a4ff6..1a45d6bd2539 100644 --- a/arch/arm/mach-omap2/clock33xx_data.c +++ b/arch/arm/mach-omap2/clock33xx_data.c @@ -1013,6 +1013,7 @@ static struct omap_clk am33xx_clks[] = { CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_AM33XX), CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_AM33XX), CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_AM33XX), + CLK("cpu0", NULL, &dpll_mpu_ck, CK_AM33XX), CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_AM33XX), CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck, CK_AM33XX), CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck, CK_AM33XX), @@ -1034,6 +1035,8 @@ static struct omap_clk am33xx_clks[] = { CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk, CK_AM33XX), CLK("davinci-mcasp.0", NULL, &mcasp0_fck, CK_AM33XX), CLK("davinci-mcasp.1", NULL, &mcasp1_fck, CK_AM33XX), + CLK(NULL, "mcasp0_fck", &mcasp0_fck, CK_AM33XX), + CLK(NULL, "mcasp1_fck", &mcasp1_fck, CK_AM33XX), CLK("NULL", "mmc2_fck", &mmc2_fck, CK_AM33XX), CLK(NULL, "mmu_fck", &mmu_fck, CK_AM33XX), CLK(NULL, "smartreflex0_fck", &smartreflex0_fck, CK_AM33XX), @@ -1070,6 +1073,8 @@ static struct omap_clk am33xx_clks[] = { CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck, CK_AM33XX), CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck, CK_AM33XX), CLK(NULL, "clkout2_ck", &clkout2_ck, CK_AM33XX), + CLK(NULL, "timer_32k_ck", &clkdiv32k_ick, CK_AM33XX), + CLK(NULL, "timer_sys_ck", &sys_clkin_ck, CK_AM33XX), }; int __init am33xx_clk_init(void) diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c index 15cdc6471737..83bb01427d40 100644 --- a/arch/arm/mach-omap2/clock3xxx.c +++ b/arch/arm/mach-omap2/clock3xxx.c @@ -63,15 +63,15 @@ void __init omap3_clk_lock_dpll5(void) dpll5_clk = clk_get(NULL, "dpll5_ck"); clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST); - clk_enable(dpll5_clk); + clk_prepare_enable(dpll5_clk); /* Program dpll5_m2_clk divider for no division */ dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck"); - clk_enable(dpll5_m2_clk); + clk_prepare_enable(dpll5_m2_clk); clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST); - clk_disable(dpll5_m2_clk); - clk_disable(dpll5_clk); + clk_disable_unprepare(dpll5_m2_clk); + clk_disable_unprepare(dpll5_clk); return; } diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 700317a1bd16..1f42c9d5ecf3 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -3215,7 +3215,6 @@ static struct clk dummy_apb_pclk = { * clkdev */ -/* XXX At some point we should rename this file to clock3xxx_data.c */ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "apb_pclk", &dummy_apb_pclk, CK_3XXX), CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX), @@ -3243,11 +3242,13 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX), CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_3XXX), CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX), + CLK(NULL, "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX), CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX), CLK(NULL, "dpll4_ck", &dpll4_ck, CK_3XXX), CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_3XXX), CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX), CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX), + CLK(NULL, "omap_96m_alwon_fck_3630", &omap_96m_alwon_fck_3630, CK_36XX), CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_3XXX), CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_3XXX), CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_3XXX), @@ -3263,6 +3264,7 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX), CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX), CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX), + CLK(NULL, "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX), CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX), CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), @@ -3272,6 +3274,7 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "dpll1_fck", &dpll1_fck, CK_3XXX), CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX), CLK(NULL, "arm_fck", &arm_fck, CK_3XXX), + CLK(NULL, "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX), CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX), CLK(NULL, "dpll2_fck", &dpll2_fck, CK_34XX | CK_36XX), CLK(NULL, "iva2_ck", &iva2_ck, CK_34XX | CK_36XX), @@ -3295,6 +3298,7 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK("usbhs_omap", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK("usbhs_tll", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX), CLK(NULL, "mmchs3_fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_3XXX), @@ -3315,6 +3319,7 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1), CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX), CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX), + CLK(NULL, "hdq_fck", &hdq_fck, CK_3XXX), CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1), CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2PLUS | CK_36XX), CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1), @@ -3322,6 +3327,8 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX), CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1, CK_3430ES1), CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX), + CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es1, CK_3430ES1), + CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX), CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX), CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX), CLK(NULL, "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX), @@ -3329,28 +3336,42 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX), CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK("usbhs_omap", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK("usbhs_tll", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK("omap_hsmmc.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK(NULL, "mmchs3_ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX), CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX), CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX), CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX), CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_3XXX), CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_3XXX), + CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_3XXX), + CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_3XXX), CLK(NULL, "mspro_ick", &mspro_ick, CK_34XX | CK_36XX), CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX), + CLK(NULL, "hdq_ick", &hdq_ick, CK_3XXX), CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX), CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX), CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_3XXX), CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_3XXX), + CLK(NULL, "mcspi4_ick", &mcspi4_ick, CK_3XXX), + CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_3XXX), + CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_3XXX), + CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_3XXX), CLK("omap_i2c.3", "ick", &i2c3_ick, CK_3XXX), CLK("omap_i2c.2", "ick", &i2c2_ick, CK_3XXX), CLK("omap_i2c.1", "ick", &i2c1_ick, CK_3XXX), + CLK(NULL, "i2c3_ick", &i2c3_ick, CK_3XXX), + CLK(NULL, "i2c2_ick", &i2c2_ick, CK_3XXX), + CLK(NULL, "i2c1_ick", &i2c1_ick, CK_3XXX), CLK(NULL, "uart2_ick", &uart2_ick, CK_3XXX), CLK(NULL, "uart1_ick", &uart1_ick, CK_3XXX), CLK(NULL, "gpt11_ick", &gpt11_ick, CK_3XXX), CLK(NULL, "gpt10_ick", &gpt10_ick, CK_3XXX), CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX), CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX), + CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_3XXX), + CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_3XXX), CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1), CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX), CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX), @@ -3369,7 +3390,9 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_3XXX), CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_3XXX), CLK("omapdss_dss", "ick", &dss_ick_3430es1, CK_3430ES1), + CLK(NULL, "dss_ick", &dss_ick_3430es1, CK_3430ES1), CLK("omapdss_dss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK(NULL, "dss_ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX), CLK(NULL, "cam_ick", &cam_ick, CK_34XX | CK_36XX), CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_34XX | CK_36XX), @@ -3385,6 +3408,8 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "usb_host_hs_utmi_p2_clk", &dummy_ck, CK_3XXX), CLK("usbhs_omap", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX), CLK("usbhs_omap", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX), + CLK("usbhs_tll", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX), + CLK("usbhs_tll", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX), CLK(NULL, "init_60m_fclk", &dummy_ck, CK_3XXX), CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2PLUS | CK_36XX), CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX), @@ -3394,6 +3419,7 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_34XX | CK_36XX), CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2PLUS | CK_36XX), CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX), + CLK(NULL, "wdt2_ick", &wdt2_ick, CK_3XXX), CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX), CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX), CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX), @@ -3439,9 +3465,13 @@ static struct omap_clk omap3xxx_clks[] = { CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_3XXX), CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_3XXX), CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_3XXX), + CLK(NULL, "mcbsp4_ick", &mcbsp2_ick, CK_3XXX), + CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_3XXX), + CLK(NULL, "mcbsp2_ick", &mcbsp4_ick, CK_3XXX), CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_3XXX), CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_3XXX), CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_3XXX), + CLK(NULL, "emu_src_ck", &emu_src_ck, CK_3XXX), CLK("etb", "emu_src_ck", &emu_src_ck, CK_3XXX), CLK(NULL, "pclk_fck", &pclk_fck, CK_3XXX), CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_3XXX), @@ -3457,8 +3487,12 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX), CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX), CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX), + CLK(NULL, "emac_ick", &emac_ick, CK_AM35XX), + CLK(NULL, "emac_fck", &emac_fck, CK_AM35XX), CLK("davinci_emac.0", NULL, &emac_ick, CK_AM35XX), CLK("davinci_mdio.0", NULL, &emac_fck, CK_AM35XX), + CLK(NULL, "vpfe_ick", &emac_ick, CK_AM35XX), + CLK(NULL, "vpfe_fck", &emac_fck, CK_AM35XX), CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX), CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX), CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx, CK_AM35XX), @@ -3467,6 +3501,7 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX), CLK(NULL, "timer_32k_ck", &omap_32k_fck, CK_3XXX), CLK(NULL, "timer_sys_ck", &sys_ck, CK_3XXX), + CLK(NULL, "cpufreq_ck", &dpll1_ck, CK_3XXX), }; diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 500682c051c1..6efc30c961a5 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -3156,6 +3156,7 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X), CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X), CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X), + CLK(NULL, "dss_fck", &dss_fck, CK_443X), CLK("omapdss_dss", "ick", &dss_fck, CK_443X), CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X), CLK(NULL, "emif1_fck", &emif1_fck, CK_443X), @@ -3212,6 +3213,7 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X), CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X), CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X), + CLK(NULL, "rng_ick", &rng_ick, CK_443X), CLK("omap_rng", "ick", &rng_ick, CK_443X), CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X), CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X), @@ -3243,6 +3245,7 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "uart3_fck", &uart3_fck, CK_443X), CLK(NULL, "uart4_fck", &uart4_fck, CK_443X), CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck, CK_443X), + CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X), CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X), CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X), CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X), @@ -3253,15 +3256,19 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X), CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X), CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X), + CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X), CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck, CK_443X), CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X), CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X), + CLK(NULL, "usb_otg_hs_ick", &usb_otg_hs_ick, CK_443X), CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X), CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X), CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X), CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X), CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X), + CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X), CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick, CK_443X), + CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick, CK_443X), CLK(NULL, "usim_ck", &usim_ck, CK_443X), CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), CLK(NULL, "usim_fck", &usim_fck, CK_443X), @@ -3287,7 +3294,7 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck, CK_443X), CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X), CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X), - CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X), + CLK("omap-gpmc", "fck", &dummy_ck, CK_443X), CLK("omap_i2c.1", "ick", &dummy_ck, CK_443X), CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X), CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X), @@ -3312,8 +3319,10 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "uart4_ick", &dummy_ck, CK_443X), CLK("usbhs_omap", "usbhost_ick", &dummy_ck, CK_443X), CLK("usbhs_omap", "usbtll_fck", &dummy_ck, CK_443X), + CLK("usbhs_tll", "usbtll_fck", &dummy_ck, CK_443X), CLK("omap_wdt", "ick", &dummy_ck, CK_443X), CLK(NULL, "timer_32k_ck", &sys_32k_ck, CK_443X), + /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */ CLK("omap_timer.1", "timer_sys_ck", &sys_clkin_ck, CK_443X), CLK("omap_timer.2", "timer_sys_ck", &sys_clkin_ck, CK_443X), CLK("omap_timer.3", "timer_sys_ck", &sys_clkin_ck, CK_443X), @@ -3325,6 +3334,18 @@ static struct omap_clk omap44xx_clks[] = { CLK("omap_timer.6", "timer_sys_ck", &syc_clk_div_ck, CK_443X), CLK("omap_timer.7", "timer_sys_ck", &syc_clk_div_ck, CK_443X), CLK("omap_timer.8", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK("4a318000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("48032000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("48034000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("48036000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("4803e000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("48086000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("48088000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("49038000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK("4903a000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK("4903c000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK("4903e000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK(NULL, "cpufreq_ck", &dpll_mpu_ck, CK_443X), }; int __init omap4xxx_clk_init(void) diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index a1555627ad97..512e79a842cb 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -899,6 +899,23 @@ bool clkdm_in_hwsup(struct clockdomain *clkdm) return ret; } +/** + * clkdm_missing_idle_reporting - can @clkdm enter autoidle even if in use? + * @clkdm: struct clockdomain * + * + * Returns true if clockdomain @clkdm has the + * CLKDM_MISSING_IDLE_REPORTING flag set, or false if not or @clkdm is + * null. More information is available in the documentation for the + * CLKDM_MISSING_IDLE_REPORTING macro. + */ +bool clkdm_missing_idle_reporting(struct clockdomain *clkdm) +{ + if (!clkdm) + return false; + + return (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING) ? true : false; +} + /* Clockdomain-to-clock/hwmod framework interface code */ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm) @@ -908,15 +925,18 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm) if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_enable) return -EINVAL; + spin_lock_irqsave(&clkdm->lock, flags); + /* * For arch's with no autodeps, clkcm_clk_enable * should be called for every clock instance or hwmod that is * enabled, so the clkdm can be force woken up. */ - if ((atomic_inc_return(&clkdm->usecount) > 1) && autodeps) + if ((atomic_inc_return(&clkdm->usecount) > 1) && autodeps) { + spin_unlock_irqrestore(&clkdm->lock, flags); return 0; + } - spin_lock_irqsave(&clkdm->lock, flags); arch_clkdm->clkdm_clk_enable(clkdm); pwrdm_state_switch(clkdm->pwrdm.ptr); spin_unlock_irqrestore(&clkdm->lock, flags); @@ -933,15 +953,19 @@ static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm) if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_disable) return -EINVAL; + spin_lock_irqsave(&clkdm->lock, flags); + if (atomic_read(&clkdm->usecount) == 0) { + spin_unlock_irqrestore(&clkdm->lock, flags); WARN_ON(1); /* underflow */ return -ERANGE; } - if (atomic_dec_return(&clkdm->usecount) > 0) + if (atomic_dec_return(&clkdm->usecount) > 0) { + spin_unlock_irqrestore(&clkdm->lock, flags); return 0; + } - spin_lock_irqsave(&clkdm->lock, flags); arch_clkdm->clkdm_clk_disable(clkdm); pwrdm_state_switch(clkdm->pwrdm.ptr); spin_unlock_irqrestore(&clkdm->lock, flags); diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h index 5601dc13785e..629576be7444 100644 --- a/arch/arm/mach-omap2/clockdomain.h +++ b/arch/arm/mach-omap2/clockdomain.h @@ -1,9 +1,7 @@ /* - * arch/arm/plat-omap/include/mach/clockdomain.h - * * OMAP2/3 clockdomain framework functions * - * Copyright (C) 2008 Texas Instruments, Inc. + * Copyright (C) 2008, 2012 Texas Instruments, Inc. * Copyright (C) 2008-2011 Nokia Corporation * * Paul Walmsley @@ -34,6 +32,20 @@ * CLKDM_ACTIVE_WITH_MPU: The PRCM guarantees that this clockdomain is * active whenever the MPU is active. True for interconnects and * the WKUP clockdomains. + * CLKDM_MISSING_IDLE_REPORTING: The idle status of the IP blocks and + * clocks inside this clockdomain are not taken into account by + * the PRCM when determining whether the clockdomain is idle. + * Without this flag, if the clockdomain is set to + * hardware-supervised idle mode, the PRCM may transition the + * enclosing powerdomain to a low power state, even when devices + * inside the clockdomain and powerdomain are in use. (An example + * of such a clockdomain is the EMU clockdomain on OMAP3/4.) If + * this flag is set, and the clockdomain does not support the + * force-sleep mode, then the HW_AUTO mode will be used to put the + * clockdomain to sleep. Similarly, if the clockdomain supports + * the force-wakeup mode, then it will be used whenever a clock or + * IP block inside the clockdomain is active, rather than the + * HW_AUTO mode. */ #define CLKDM_CAN_FORCE_SLEEP (1 << 0) #define CLKDM_CAN_FORCE_WAKEUP (1 << 1) @@ -41,6 +53,7 @@ #define CLKDM_CAN_DISABLE_AUTO (1 << 3) #define CLKDM_NO_AUTODEPS (1 << 4) #define CLKDM_ACTIVE_WITH_MPU (1 << 5) +#define CLKDM_MISSING_IDLE_REPORTING (1 << 6) #define CLKDM_CAN_HWSUP (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO) #define CLKDM_CAN_SWSUP (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP) @@ -187,6 +200,7 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm); void clkdm_allow_idle(struct clockdomain *clkdm); void clkdm_deny_idle(struct clockdomain *clkdm); bool clkdm_in_hwsup(struct clockdomain *clkdm); +bool clkdm_missing_idle_reporting(struct clockdomain *clkdm); int clkdm_wakeup(struct clockdomain *clkdm); int clkdm_sleep(struct clockdomain *clkdm); diff --git a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c index f99e65cfb862..70294f54e35a 100644 --- a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c +++ b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c @@ -162,6 +162,19 @@ static void _disable_hwsup(struct clockdomain *clkdm) clkdm->clktrctrl_mask); } +static int omap3_clkdm_sleep(struct clockdomain *clkdm) +{ + omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); + return 0; +} + +static int omap3_clkdm_wakeup(struct clockdomain *clkdm) +{ + omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); + return 0; +} static int omap2_clkdm_clk_enable(struct clockdomain *clkdm) { @@ -209,20 +222,6 @@ static int omap2_clkdm_clk_disable(struct clockdomain *clkdm) return 0; } -static int omap3_clkdm_sleep(struct clockdomain *clkdm) -{ - omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs, - clkdm->clktrctrl_mask); - return 0; -} - -static int omap3_clkdm_wakeup(struct clockdomain *clkdm) -{ - omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs, - clkdm->clktrctrl_mask); - return 0; -} - static void omap3_clkdm_allow_idle(struct clockdomain *clkdm) { if (atomic_read(&clkdm->usecount) > 0) @@ -248,6 +247,17 @@ static int omap3xxx_clkdm_clk_enable(struct clockdomain *clkdm) if (!clkdm->clktrctrl_mask) return 0; + /* + * The CLKDM_MISSING_IDLE_REPORTING flag documentation has + * more details on the unpleasant problem this is working + * around + */ + if ((clkdm->flags & CLKDM_MISSING_IDLE_REPORTING) && + (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)) { + omap3_clkdm_wakeup(clkdm); + return 0; + } + hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs, clkdm->clktrctrl_mask); @@ -271,6 +281,17 @@ static int omap3xxx_clkdm_clk_disable(struct clockdomain *clkdm) if (!clkdm->clktrctrl_mask) return 0; + /* + * The CLKDM_MISSING_IDLE_REPORTING flag documentation has + * more details on the unpleasant problem this is working + * around + */ + if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING && + !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) { + _enable_hwsup(clkdm); + return 0; + } + hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs, clkdm->clktrctrl_mask); diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c index 762f2cc542ce..6fc6155625bc 100644 --- a/arch/arm/mach-omap2/clockdomain44xx.c +++ b/arch/arm/mach-omap2/clockdomain44xx.c @@ -113,6 +113,17 @@ static int omap4_clkdm_clk_disable(struct clockdomain *clkdm) if (!clkdm->prcm_partition) return 0; + /* + * The CLKDM_MISSING_IDLE_REPORTING flag documentation has + * more details on the unpleasant problem this is working + * around + */ + if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING && + !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) { + omap4_clkdm_allow_idle(clkdm); + return 0; + } + hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition, clkdm->cm_inst, clkdm->clkdm_offs); diff --git a/arch/arm/mach-omap2/clockdomains3xxx_data.c b/arch/arm/mach-omap2/clockdomains3xxx_data.c index 56089c49142a..933a35cd124a 100644 --- a/arch/arm/mach-omap2/clockdomains3xxx_data.c +++ b/arch/arm/mach-omap2/clockdomains3xxx_data.c @@ -387,14 +387,11 @@ static struct clockdomain per_am35x_clkdm = { .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK, }; -/* - * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is - * switched of even if sdti is in use - */ static struct clockdomain emu_clkdm = { .name = "emu_clkdm", .pwrdm = { .name = "emu_pwrdm" }, - .flags = /* CLKDM_CAN_ENABLE_AUTO | */CLKDM_CAN_SWSUP, + .flags = (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_SWSUP | + CLKDM_MISSING_IDLE_REPORTING), .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK, }; diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c index 63d60a773d3b..b56d06b48782 100644 --- a/arch/arm/mach-omap2/clockdomains44xx_data.c +++ b/arch/arm/mach-omap2/clockdomains44xx_data.c @@ -390,7 +390,8 @@ static struct clockdomain emu_sys_44xx_clkdm = { .prcm_partition = OMAP4430_PRM_PARTITION, .cm_inst = OMAP4430_PRM_EMU_CM_INST, .clkdm_offs = OMAP4430_PRM_EMU_CM_EMU_CDOFFS, - .flags = CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_FORCE_WAKEUP, + .flags = (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_FORCE_WAKEUP | + CLKDM_MISSING_IDLE_REPORTING), }; static struct clockdomain l3_dma_44xx_clkdm = { diff --git a/arch/arm/mach-omap2/cm-regbits-33xx.h b/arch/arm/mach-omap2/cm-regbits-33xx.h index 532027ee3d8d..adf7bb79b18f 100644 --- a/arch/arm/mach-omap2/cm-regbits-33xx.h +++ b/arch/arm/mach-omap2/cm-regbits-33xx.h @@ -25,263 +25,328 @@ * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER */ #define AM33XX_AUTO_DPLL_MODE_SHIFT 0 +#define AM33XX_AUTO_DPLL_MODE_WIDTH 3 #define AM33XX_AUTO_DPLL_MODE_MASK (0x7 << 0) /* Used by CM_WKUP_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT 14 +#define AM33XX_CLKACTIVITY_ADC_FCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_ADC_FCLK_MASK (1 << 16) /* Used by CM_PER_L4LS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT 11 +#define AM33XX_CLKACTIVITY_CAN_CLK_WIDTH 1 #define AM33XX_CLKACTIVITY_CAN_CLK_MASK (1 << 11) /* Used by CM_PER_CLK_24MHZ_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT 4 +#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK (1 << 4) /* Used by CM_PER_CPSW_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT 4 +#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK (1 << 4) /* Used by CM_PER_L4HS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT 4 +#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK (1 << 4) /* Used by CM_PER_L4HS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT 5 +#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK (1 << 5) /* Used by CM_PER_L4HS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT 6 +#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK (1 << 6) /* Used by CM_PER_L3_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT 6 +#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK (1 << 6) /* Used by CM_CEFUSE_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9 +#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH 1 #define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9) /* Used by CM_L3_AON_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT 2 +#define AM33XX_CLKACTIVITY_DBGSYSCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK (1 << 2) /* Used by CM_L3_AON_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT 4 +#define AM33XX_CLKACTIVITY_DEBUG_CLKA_WIDTH 1 #define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK (1 << 4) /* Used by CM_PER_L3_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT 2 +#define AM33XX_CLKACTIVITY_EMIF_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK (1 << 2) /* Used by CM_GFX_L3_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT 9 +#define AM33XX_CLKACTIVITY_GFX_FCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_GFX_FCLK_MASK (1 << 9) /* Used by CM_GFX_L3_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT 8 +#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK (1 << 8) /* Used by CM_WKUP_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT 8 +#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK (1 << 8) /* Used by CM_PER_L4LS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT 19 +#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK (1 << 19) /* Used by CM_PER_L4LS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT 20 +#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK (1 << 20) /* Used by CM_PER_L4LS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT 21 +#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK (1 << 21) /* Used by CM_PER_L4LS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT 22 +#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK (1 << 22) /* Used by CM_PER_L4LS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT 26 +#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK (1 << 26) /* Used by CM_PER_L4LS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT 18 +#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK (1 << 18) /* Used by CM_WKUP_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT 11 +#define AM33XX_CLKACTIVITY_I2C0_GFCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK (1 << 11) /* Used by CM_PER_L4LS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT 24 +#define AM33XX_CLKACTIVITY_I2C_FCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_I2C_FCLK_MASK (1 << 24) /* Used by CM_PER_PRUSS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT 5 +#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK (1 << 5) /* Used by CM_PER_PRUSS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT 4 +#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK (1 << 4) /* Used by CM_PER_PRUSS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT 6 +#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK (1 << 6) /* Used by CM_PER_L3S_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT 3 +#define AM33XX_CLKACTIVITY_L3S_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_L3S_GCLK_MASK (1 << 3) /* Used by CM_L3_AON_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT 3 +#define AM33XX_CLKACTIVITY_L3_AON_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK (1 << 3) /* Used by CM_PER_L3_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT 4 +#define AM33XX_CLKACTIVITY_L3_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_L3_GCLK_MASK (1 << 4) /* Used by CM_PER_L4FW_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT 8 +#define AM33XX_CLKACTIVITY_L4FW_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK (1 << 8) /* Used by CM_PER_L4HS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT 3 +#define AM33XX_CLKACTIVITY_L4HS_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK (1 << 3) /* Used by CM_PER_L4LS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT 8 +#define AM33XX_CLKACTIVITY_L4LS_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK (1 << 8) /* Used by CM_GFX_L4LS_GFX_CLKSTCTRL__1 */ #define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT 8 +#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK (1 << 8) /* Used by CM_CEFUSE_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8 +#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_WIDTH 1 #define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8) /* Used by CM_RTC_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT 8 +#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK (1 << 8) /* Used by CM_L4_WKUP_AON_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT 2 +#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK (1 << 2) /* Used by CM_WKUP_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT 2 +#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK (1 << 2) /* Used by CM_PER_L4LS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT 17 +#define AM33XX_CLKACTIVITY_LCDC_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_LCDC_GCLK_MASK (1 << 17) /* Used by CM_PER_LCDC_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT 4 +#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK (1 << 4) /* Used by CM_PER_LCDC_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT 5 +#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK (1 << 5) /* Used by CM_PER_L3_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT 7 +#define AM33XX_CLKACTIVITY_MCASP_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_MCASP_GCLK_MASK (1 << 7) /* Used by CM_PER_L3_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT 3 +#define AM33XX_CLKACTIVITY_MMC_FCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_MMC_FCLK_MASK (1 << 3) /* Used by CM_MPU_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_MPU_CLK_SHIFT 2 +#define AM33XX_CLKACTIVITY_MPU_CLK_WIDTH 1 #define AM33XX_CLKACTIVITY_MPU_CLK_MASK (1 << 2) /* Used by CM_PER_OCPWP_L3_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT 4 +#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK (1 << 4) /* Used by CM_PER_OCPWP_L3_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT 5 +#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK (1 << 5) /* Used by CM_RTC_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT 9 +#define AM33XX_CLKACTIVITY_RTC_32KCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_RTC_32KCLK_MASK (1 << 9) /* Used by CM_PER_L4LS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT 25 +#define AM33XX_CLKACTIVITY_SPI_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_SPI_GCLK_MASK (1 << 25) /* Used by CM_WKUP_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT 3 +#define AM33XX_CLKACTIVITY_SR_SYSCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_SR_SYSCLK_MASK (1 << 3) /* Used by CM_WKUP_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT 10 +#define AM33XX_CLKACTIVITY_TIMER0_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK (1 << 10) /* Used by CM_WKUP_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT 13 +#define AM33XX_CLKACTIVITY_TIMER1_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK (1 << 13) /* Used by CM_PER_L4LS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT 14 +#define AM33XX_CLKACTIVITY_TIMER2_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK (1 << 14) /* Used by CM_PER_L4LS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT 15 +#define AM33XX_CLKACTIVITY_TIMER3_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK (1 << 15) /* Used by CM_PER_L4LS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT 16 +#define AM33XX_CLKACTIVITY_TIMER4_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK (1 << 16) /* Used by CM_PER_L4LS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT 27 +#define AM33XX_CLKACTIVITY_TIMER5_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK (1 << 27) /* Used by CM_PER_L4LS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT 28 +#define AM33XX_CLKACTIVITY_TIMER6_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK (1 << 28) /* Used by CM_PER_L4LS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT 13 +#define AM33XX_CLKACTIVITY_TIMER7_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK (1 << 13) /* Used by CM_WKUP_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT 12 +#define AM33XX_CLKACTIVITY_UART0_GFCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_UART0_GFCLK_MASK (1 << 12) /* Used by CM_PER_L4LS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT 10 +#define AM33XX_CLKACTIVITY_UART_GFCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_UART_GFCLK_MASK (1 << 10) /* Used by CM_WKUP_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT 9 +#define AM33XX_CLKACTIVITY_WDT0_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_WDT0_GCLK_MASK (1 << 9) /* Used by CM_WKUP_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT 4 +#define AM33XX_CLKACTIVITY_WDT1_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_WDT1_GCLK_MASK (1 << 4) /* Used by CLKSEL_GFX_FCLK */ #define AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT 0 +#define AM33XX_CLKDIV_SEL_GFX_FCLK_WIDTH 1 #define AM33XX_CLKDIV_SEL_GFX_FCLK_MASK (1 << 0) /* Used by CM_CLKOUT_CTRL */ #define AM33XX_CLKOUT2DIV_SHIFT 3 -#define AM33XX_CLKOUT2DIV_MASK (0x05 << 3) +#define AM33XX_CLKOUT2DIV_WIDTH 3 +#define AM33XX_CLKOUT2DIV_MASK (0x7 << 3) /* Used by CM_CLKOUT_CTRL */ #define AM33XX_CLKOUT2EN_SHIFT 7 +#define AM33XX_CLKOUT2EN_WIDTH 1 #define AM33XX_CLKOUT2EN_MASK (1 << 7) /* Used by CM_CLKOUT_CTRL */ #define AM33XX_CLKOUT2SOURCE_SHIFT 0 -#define AM33XX_CLKOUT2SOURCE_MASK (0x02 << 0) +#define AM33XX_CLKOUT2SOURCE_WIDTH 3 +#define AM33XX_CLKOUT2SOURCE_MASK (0x7 << 0) /* * Used by CLKSEL_GPIO0_DBCLK, CLKSEL_LCDC_PIXEL_CLK, CLKSEL_TIMER2_CLK, @@ -289,6 +354,7 @@ * CLKSEL_TIMER7_CLK */ #define AM33XX_CLKSEL_SHIFT 0 +#define AM33XX_CLKSEL_WIDTH 1 #define AM33XX_CLKSEL_MASK (0x01 << 0) /* @@ -296,17 +362,21 @@ * CM_CPTS_RFT_CLKSEL */ #define AM33XX_CLKSEL_0_0_SHIFT 0 +#define AM33XX_CLKSEL_0_0_WIDTH 1 #define AM33XX_CLKSEL_0_0_MASK (1 << 0) #define AM33XX_CLKSEL_0_1_SHIFT 0 +#define AM33XX_CLKSEL_0_1_WIDTH 2 #define AM33XX_CLKSEL_0_1_MASK (3 << 0) /* Renamed from CLKSEL Used by CLKSEL_TIMER1MS_CLK */ #define AM33XX_CLKSEL_0_2_SHIFT 0 +#define AM33XX_CLKSEL_0_2_WIDTH 3 #define AM33XX_CLKSEL_0_2_MASK (7 << 0) /* Used by CLKSEL_GFX_FCLK */ #define AM33XX_CLKSEL_GFX_FCLK_SHIFT 1 +#define AM33XX_CLKSEL_GFX_FCLK_WIDTH 1 #define AM33XX_CLKSEL_GFX_FCLK_MASK (1 << 1) /* @@ -318,6 +388,7 @@ * CM_GFX_L3_CLKSTCTRL, CM_GFX_L4LS_GFX_CLKSTCTRL__1, CM_CEFUSE_CLKSTCTRL */ #define AM33XX_CLKTRCTRL_SHIFT 0 +#define AM33XX_CLKTRCTRL_WIDTH 2 #define AM33XX_CLKTRCTRL_MASK (0x3 << 0) /* @@ -326,34 +397,42 @@ * CM_SSC_DELTAMSTEP_DPLL_PER */ #define AM33XX_DELTAMSTEP_SHIFT 0 -#define AM33XX_DELTAMSTEP_MASK (0x19 << 0) +#define AM33XX_DELTAMSTEP_WIDTH 20 +#define AM33XX_DELTAMSTEP_MASK (0xfffff << 0) /* Used by CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, CM_CLKSEL_DPLL_MPU */ #define AM33XX_DPLL_BYP_CLKSEL_SHIFT 23 +#define AM33XX_DPLL_BYP_CLKSEL_WIDTH 1 #define AM33XX_DPLL_BYP_CLKSEL_MASK (1 << 23) /* Used by CM_CLKDCOLDO_DPLL_PER */ #define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8 +#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH 1 #define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8) /* Used by CM_CLKDCOLDO_DPLL_PER */ #define AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT 12 +#define AM33XX_DPLL_CLKDCOLDO_PWDN_WIDTH 1 #define AM33XX_DPLL_CLKDCOLDO_PWDN_MASK (1 << 12) /* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */ #define AM33XX_DPLL_CLKOUT_DIV_SHIFT 0 +#define AM33XX_DPLL_CLKOUT_DIV_WIDTH 5 #define AM33XX_DPLL_CLKOUT_DIV_MASK (0x1f << 0) /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_PER */ #define AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT 0 -#define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK (0x06 << 0) +#define AM33XX_DPLL_CLKOUT_DIV_0_6_WIDTH 7 +#define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0) /* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */ #define AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT 5 +#define AM33XX_DPLL_CLKOUT_DIVCHACK_WIDTH 1 #define AM33XX_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5) /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_PER */ #define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT 7 +#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_WIDTH 1 #define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK (1 << 7) /* @@ -361,6 +440,7 @@ * CM_DIV_M2_DPLL_PER */ #define AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT 8 +#define AM33XX_DPLL_CLKOUT_GATE_CTRL_WIDTH 1 #define AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) /* @@ -368,19 +448,22 @@ * CM_CLKSEL_DPLL_MPU */ #define AM33XX_DPLL_DIV_SHIFT 0 +#define AM33XX_DPLL_DIV_WIDTH 7 #define AM33XX_DPLL_DIV_MASK (0x7f << 0) #define AM33XX_DPLL_PER_DIV_MASK (0xff << 0) /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PERIPH */ #define AM33XX_DPLL_DIV_0_7_SHIFT 0 -#define AM33XX_DPLL_DIV_0_7_MASK (0x07 << 0) +#define AM33XX_DPLL_DIV_0_7_WIDTH 8 +#define AM33XX_DPLL_DIV_0_7_MASK (0xff << 0) /* * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, * CM_CLKMODE_DPLL_MPU */ #define AM33XX_DPLL_DRIFTGUARD_EN_SHIFT 8 +#define AM33XX_DPLL_DRIFTGUARD_EN_WIDTH 1 #define AM33XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8) /* @@ -388,6 +471,7 @@ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER */ #define AM33XX_DPLL_EN_SHIFT 0 +#define AM33XX_DPLL_EN_WIDTH 3 #define AM33XX_DPLL_EN_MASK (0x7 << 0) /* @@ -395,6 +479,7 @@ * CM_CLKMODE_DPLL_MPU */ #define AM33XX_DPLL_LPMODE_EN_SHIFT 10 +#define AM33XX_DPLL_LPMODE_EN_WIDTH 1 #define AM33XX_DPLL_LPMODE_EN_MASK (1 << 10) /* @@ -402,10 +487,12 @@ * CM_CLKSEL_DPLL_MPU */ #define AM33XX_DPLL_MULT_SHIFT 8 +#define AM33XX_DPLL_MULT_WIDTH 11 #define AM33XX_DPLL_MULT_MASK (0x7ff << 8) /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PERIPH */ #define AM33XX_DPLL_MULT_PERIPH_SHIFT 8 +#define AM33XX_DPLL_MULT_PERIPH_WIDTH 12 #define AM33XX_DPLL_MULT_PERIPH_MASK (0xfff << 8) /* @@ -413,17 +500,20 @@ * CM_CLKMODE_DPLL_MPU */ #define AM33XX_DPLL_REGM4XEN_SHIFT 11 +#define AM33XX_DPLL_REGM4XEN_WIDTH 1 #define AM33XX_DPLL_REGM4XEN_MASK (1 << 11) /* Used by CM_CLKSEL_DPLL_PERIPH */ #define AM33XX_DPLL_SD_DIV_SHIFT 24 -#define AM33XX_DPLL_SD_DIV_MASK (24, 31) +#define AM33XX_DPLL_SD_DIV_WIDTH 8 +#define AM33XX_DPLL_SD_DIV_MASK (0xff << 24) /* * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER */ #define AM33XX_DPLL_SSC_ACK_SHIFT 13 +#define AM33XX_DPLL_SSC_ACK_WIDTH 1 #define AM33XX_DPLL_SSC_ACK_MASK (1 << 13) /* @@ -431,6 +521,7 @@ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER */ #define AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT 14 +#define AM33XX_DPLL_SSC_DOWNSPREAD_WIDTH 1 #define AM33XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) /* @@ -438,54 +529,67 @@ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER */ #define AM33XX_DPLL_SSC_EN_SHIFT 12 +#define AM33XX_DPLL_SSC_EN_WIDTH 1 #define AM33XX_DPLL_SSC_EN_MASK (1 << 12) /* Used by CM_DIV_M4_DPLL_CORE */ #define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 +#define AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH 5 #define AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0) /* Used by CM_DIV_M4_DPLL_CORE */ #define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5 +#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH 1 #define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5) /* Used by CM_DIV_M4_DPLL_CORE */ #define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8 +#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH 1 #define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8) /* Used by CM_DIV_M4_DPLL_CORE */ #define AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12 +#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_WIDTH 1 #define AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12) /* Used by CM_DIV_M5_DPLL_CORE */ #define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 +#define AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH 5 #define AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0) /* Used by CM_DIV_M5_DPLL_CORE */ #define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5 +#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_WIDTH 1 #define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5) /* Used by CM_DIV_M5_DPLL_CORE */ #define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8 +#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_WIDTH 1 #define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8) /* Used by CM_DIV_M5_DPLL_CORE */ #define AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12 +#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_WIDTH 1 #define AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12) /* Used by CM_DIV_M6_DPLL_CORE */ #define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 -#define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK (0x04 << 0) +#define AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH 5 +#define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0) /* Used by CM_DIV_M6_DPLL_CORE */ #define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5 +#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_WIDTH 1 #define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5) /* Used by CM_DIV_M6_DPLL_CORE */ #define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8 +#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_WIDTH 1 #define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8) /* Used by CM_DIV_M6_DPLL_CORE */ #define AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12 +#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_WIDTH 1 #define AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12) /* @@ -522,11 +626,12 @@ * CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL */ #define AM33XX_IDLEST_SHIFT 16 +#define AM33XX_IDLEST_WIDTH 2 #define AM33XX_IDLEST_MASK (0x3 << 16) -#define AM33XX_IDLEST_VAL 0x3 /* Used by CM_MAC_CLKSEL */ #define AM33XX_MII_CLK_SEL_SHIFT 2 +#define AM33XX_MII_CLK_SEL_WIDTH 1 #define AM33XX_MII_CLK_SEL_MASK (1 << 2) /* @@ -535,7 +640,8 @@ * CM_SSC_MODFREQDIV_DPLL_PER */ #define AM33XX_MODFREQDIV_EXPONENT_SHIFT 8 -#define AM33XX_MODFREQDIV_EXPONENT_MASK (0x10 << 8) +#define AM33XX_MODFREQDIV_EXPONENT_WIDTH 3 +#define AM33XX_MODFREQDIV_EXPONENT_MASK (0x7 << 8) /* * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR, @@ -543,7 +649,8 @@ * CM_SSC_MODFREQDIV_DPLL_PER */ #define AM33XX_MODFREQDIV_MANTISSA_SHIFT 0 -#define AM33XX_MODFREQDIV_MANTISSA_MASK (0x06 << 0) +#define AM33XX_MODFREQDIV_MANTISSA_WIDTH 7 +#define AM33XX_MODFREQDIV_MANTISSA_MASK (0x7f << 0) /* * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL, @@ -580,42 +687,52 @@ * CM_CEFUSE_CEFUSE_CLKCTRL */ #define AM33XX_MODULEMODE_SHIFT 0 +#define AM33XX_MODULEMODE_WIDTH 2 #define AM33XX_MODULEMODE_MASK (0x3 << 0) /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ #define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT 30 +#define AM33XX_OPTCLK_DEBUG_CLKA_WIDTH 1 #define AM33XX_OPTCLK_DEBUG_CLKA_MASK (1 << 30) /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ #define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT 19 +#define AM33XX_OPTFCLKEN_DBGSYSCLK_WIDTH 1 #define AM33XX_OPTFCLKEN_DBGSYSCLK_MASK (1 << 19) /* Used by CM_WKUP_GPIO0_CLKCTRL */ #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT 18 +#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_WIDTH 1 #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK (1 << 18) /* Used by CM_PER_GPIO1_CLKCTRL */ #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT 18 +#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_WIDTH 1 #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK (1 << 18) /* Used by CM_PER_GPIO2_CLKCTRL */ #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT 18 +#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_WIDTH 1 #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK (1 << 18) /* Used by CM_PER_GPIO3_CLKCTRL */ #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT 18 +#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_WIDTH 1 #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK (1 << 18) /* Used by CM_PER_GPIO4_CLKCTRL */ #define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT 18 +#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_WIDTH 1 #define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK (1 << 18) /* Used by CM_PER_GPIO5_CLKCTRL */ #define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT 18 +#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_WIDTH 1 #define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK (1 << 18) /* Used by CM_PER_GPIO6_CLKCTRL */ #define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT 18 +#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_WIDTH 1 #define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK (1 << 18) /* @@ -627,25 +744,30 @@ * CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL */ #define AM33XX_STBYST_SHIFT 18 +#define AM33XX_STBYST_WIDTH 1 #define AM33XX_STBYST_MASK (1 << 18) /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ #define AM33XX_STM_PMD_CLKDIVSEL_SHIFT 27 -#define AM33XX_STM_PMD_CLKDIVSEL_MASK (0x29 << 27) +#define AM33XX_STM_PMD_CLKDIVSEL_WIDTH 3 +#define AM33XX_STM_PMD_CLKDIVSEL_MASK (0x7 << 27) /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ #define AM33XX_STM_PMD_CLKSEL_SHIFT 22 -#define AM33XX_STM_PMD_CLKSEL_MASK (0x23 << 22) +#define AM33XX_STM_PMD_CLKSEL_WIDTH 2 +#define AM33XX_STM_PMD_CLKSEL_MASK (0x3 << 22) /* * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP, * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER */ #define AM33XX_ST_DPLL_CLK_SHIFT 0 +#define AM33XX_ST_DPLL_CLK_WIDTH 1 #define AM33XX_ST_DPLL_CLK_MASK (1 << 0) /* Used by CM_CLKDCOLDO_DPLL_PER */ #define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT 8 +#define AM33XX_ST_DPLL_CLKDCOLDO_WIDTH 1 #define AM33XX_ST_DPLL_CLKDCOLDO_MASK (1 << 8) /* @@ -653,18 +775,22 @@ * CM_DIV_M2_DPLL_PER */ #define AM33XX_ST_DPLL_CLKOUT_SHIFT 9 +#define AM33XX_ST_DPLL_CLKOUT_WIDTH 1 #define AM33XX_ST_DPLL_CLKOUT_MASK (1 << 9) /* Used by CM_DIV_M4_DPLL_CORE */ #define AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT 9 +#define AM33XX_ST_HSDIVIDER_CLKOUT1_WIDTH 1 #define AM33XX_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9) /* Used by CM_DIV_M5_DPLL_CORE */ #define AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT 9 +#define AM33XX_ST_HSDIVIDER_CLKOUT2_WIDTH 1 #define AM33XX_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9) /* Used by CM_DIV_M6_DPLL_CORE */ #define AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT 9 +#define AM33XX_ST_HSDIVIDER_CLKOUT3_WIDTH 1 #define AM33XX_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9) /* @@ -672,16 +798,20 @@ * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER */ #define AM33XX_ST_MN_BYPASS_SHIFT 8 +#define AM33XX_ST_MN_BYPASS_WIDTH 1 #define AM33XX_ST_MN_BYPASS_MASK (1 << 8) /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ #define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT 24 -#define AM33XX_TRC_PMD_CLKDIVSEL_MASK (0x26 << 24) +#define AM33XX_TRC_PMD_CLKDIVSEL_WIDTH 3 +#define AM33XX_TRC_PMD_CLKDIVSEL_MASK (0x7 << 24) /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ #define AM33XX_TRC_PMD_CLKSEL_SHIFT 20 -#define AM33XX_TRC_PMD_CLKSEL_MASK (0x21 << 20) +#define AM33XX_TRC_PMD_CLKSEL_WIDTH 2 +#define AM33XX_TRC_PMD_CLKSEL_MASK (0x3 << 20) /* Used by CONTROL_SEC_CLK_CTRL */ +#define AM33XX_TIMER0_CLKSEL_WIDTH 2 #define AM33XX_TIMER0_CLKSEL_MASK (0x3 << 4) #endif diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index 975f6bda0e0b..59598ffd8783 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h @@ -218,6 +218,8 @@ #define OMAP3430_ST_MAILBOXES_MASK (1 << 7) #define OMAP3430_ST_OMAPCTRL_SHIFT 6 #define OMAP3430_ST_OMAPCTRL_MASK (1 << 6) +#define OMAP3430_ST_SAD2D_SHIFT 3 +#define OMAP3430_ST_SAD2D_MASK (1 << 3) #define OMAP3430_ST_SDMA_SHIFT 2 #define OMAP3430_ST_SDMA_MASK (1 << 2) #define OMAP3430_ST_SDRC_SHIFT 1 diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h index 65597a745638..4c6c2f7de65b 100644 --- a/arch/arm/mach-omap2/cm-regbits-44xx.h +++ b/arch/arm/mach-omap2/cm-regbits-44xx.h @@ -1,7 +1,7 @@ /* * OMAP44xx Clock Management register bits * - * Copyright (C) 2009-2010 Texas Instruments, Inc. + * Copyright (C) 2009-2012 Texas Instruments, Inc. * Copyright (C) 2009-2010 Nokia Corporation * * Paul Walmsley (paul@pwsan.com) @@ -24,6 +24,7 @@ /* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ #define OMAP4430_ABE_DYNDEP_SHIFT 3 +#define OMAP4430_ABE_DYNDEP_WIDTH 0x1 #define OMAP4430_ABE_DYNDEP_MASK (1 << 3) /* @@ -31,14 +32,17 @@ * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_ABE_STATDEP_SHIFT 3 +#define OMAP4430_ABE_STATDEP_WIDTH 0x1 #define OMAP4430_ABE_STATDEP_MASK (1 << 3) /* Used by CM_L4CFG_DYNAMICDEP */ #define OMAP4430_ALWONCORE_DYNDEP_SHIFT 16 +#define OMAP4430_ALWONCORE_DYNDEP_WIDTH 0x1 #define OMAP4430_ALWONCORE_DYNDEP_MASK (1 << 16) /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_ALWONCORE_STATDEP_SHIFT 16 +#define OMAP4430_ALWONCORE_STATDEP_WIDTH 0x1 #define OMAP4430_ALWONCORE_STATDEP_MASK (1 << 16) /* @@ -47,294 +51,367 @@ * CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB */ #define OMAP4430_AUTO_DPLL_MODE_SHIFT 0 +#define OMAP4430_AUTO_DPLL_MODE_WIDTH 0x3 #define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0) /* Used by CM_L4CFG_DYNAMICDEP */ #define OMAP4430_CEFUSE_DYNDEP_SHIFT 17 +#define OMAP4430_CEFUSE_DYNDEP_WIDTH 0x1 #define OMAP4430_CEFUSE_DYNDEP_MASK (1 << 17) /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_CEFUSE_STATDEP_SHIFT 17 +#define OMAP4430_CEFUSE_STATDEP_WIDTH 0x1 #define OMAP4430_CEFUSE_STATDEP_MASK (1 << 17) /* Used by CM1_ABE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT 13 +#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK (1 << 13) /* Used by CM1_ABE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT 12 +#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK (1 << 12) /* Used by CM_WKUP_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT 9 +#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK (1 << 9) /* Used by CM1_ABE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT 11 +#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK (1 << 11) /* Used by CM1_ABE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8) /* Used by CM_MEMIF_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT 11 +#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK (1 << 11) /* Used by CM_MEMIF_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT 12 +#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK (1 << 12) /* Used by CM_MEMIF_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT 13 +#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK (1 << 13) /* Used by CM_CAM_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT 9 +#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK (1 << 9) /* Used by CM_ALWON_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_SHIFT 12 +#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_MASK (1 << 12) /* Used by CM_EMU_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT 9 +#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK (1 << 9) /* Used by CM_L4CFG_CLKSTCTRL */ #define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_SHIFT 9 +#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_WIDTH 0x1 #define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_MASK (1 << 9) /* Used by CM_CEFUSE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9 +#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9) /* Used by CM_MEMIF_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT 9 +#define OMAP4430_CLKACTIVITY_DLL_CLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_DLL_CLK_MASK (1 << 9) /* Used by CM_L4PER_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT 9 +#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK (1 << 9) /* Used by CM_L4PER_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT 10 +#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK (1 << 10) /* Used by CM_L4PER_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT 11 +#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK (1 << 11) /* Used by CM_L4PER_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT 12 +#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK (1 << 12) /* Used by CM_L4PER_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT 13 +#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK (1 << 13) /* Used by CM_L4PER_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT 14 +#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK (1 << 14) /* Used by CM_DSS_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT 10 +#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK (1 << 10) /* Used by CM_DSS_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT 9 +#define OMAP4430_CLKACTIVITY_DSS_FCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK (1 << 9) /* Used by CM_DUCATI_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK (1 << 8) /* Used by CM_EMU_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK (1 << 8) /* Used by CM_CAM_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT 10 +#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK (1 << 10) /* Used by CM_L4PER_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT 15 +#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK (1 << 15) /* Used by CM1_ABE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT 10 +#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK (1 << 10) /* Used by CM_DSS_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT 11 +#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK (1 << 11) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20 +#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26 +#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21 +#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27 +#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT 13 +#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK (1 << 13) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT 12 +#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK (1 << 12) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT 28 +#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK (1 << 28) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT 29 +#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK (1 << 29) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT 11 +#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK (1 << 11) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT 16 +#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK (1 << 16) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT 17 +#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK (1 << 17) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT 18 +#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK (1 << 18) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT 19 +#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK (1 << 19) /* Used by CM_CAM_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_ISS_GCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK (1 << 8) /* Used by CM_IVAHD_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK (1 << 8) /* Used by CM_D2D_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT 10 +#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK (1 << 10) /* Used by CM_L3_1_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_L3_1_GICLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK (1 << 8) /* Used by CM_L3_2_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_L3_2_GICLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK (1 << 8) /* Used by CM_D2D_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK (1 << 8) /* Used by CM_SDMA_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK (1 << 8) /* Used by CM_DSS_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK (1 << 8) /* Used by CM_MEMIF_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK (1 << 8) /* Used by CM_GFX_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK (1 << 8) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK (1 << 8) /* Used by CM_L3INSTR_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK (1 << 8) /* Used by CM_L4SEC_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK (1 << 8) /* Used by CM_ALWON_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK (1 << 8) /* Used by CM_CEFUSE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8) /* Used by CM_L4CFG_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK (1 << 8) /* Used by CM_D2D_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT 9 +#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK (1 << 9) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT 9 +#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK (1 << 9) /* Used by CM_L4PER_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK (1 << 8) /* Used by CM_L4SEC_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT 9 +#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK (1 << 9) /* Used by CM_WKUP_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT 12 +#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK (1 << 12) /* Used by CM_MPU_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK (1 << 8) /* Used by CM1_ABE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT 9 +#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK (1 << 9) /* Used by CM_L4PER_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT 16 +#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK (1 << 16) /* Used by CM_L4PER_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17 +#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17) /* Used by CM_L4PER_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18 +#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18) /* Used by CM_L4PER_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19 +#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19) /* Used by CM_L4PER_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT 25 +#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK (1 << 25) /* Used by CM_L4PER_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT 20 +#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK (1 << 20) /* Used by CM_L4PER_CLKSTCTRL */ @@ -343,94 +420,114 @@ /* Used by CM_L4PER_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT 22 +#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK (1 << 22) /* Used by CM_L4PER_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT 24 +#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK (1 << 24) /* Used by CM_MEMIF_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT 10 +#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK (1 << 10) /* Used by CM_GFX_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT 9 +#define OMAP4430_CLKACTIVITY_SGX_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK (1 << 9) /* Used by CM_ALWON_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT 11 +#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK (1 << 11) /* Used by CM_ALWON_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT 10 +#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK (1 << 10) /* Used by CM_ALWON_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT 9 +#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK (1 << 9) /* Used by CM_WKUP_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_SYS_CLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_SYS_CLK_MASK (1 << 8) /* Used by CM_TESLA_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK (1 << 8) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22 +#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23 +#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24 +#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT 10 +#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK (1 << 10) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14 +#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15 +#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15) /* Used by CM_WKUP_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT 10 +#define OMAP4430_CLKACTIVITY_USIM_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK (1 << 10) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30 +#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25 +#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25) /* Used by CM_WKUP_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT 11 +#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK (1 << 11) /* Used by CM_WKUP_CLKSTCTRL */ #define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_SHIFT 13 +#define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_WIDTH 0x1 #define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_MASK (1 << 13) /* * Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, * CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, - * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MMC6_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL, + * CM_L3INIT_MMC2_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL, * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL, * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL, - * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, - * CM_WKUP_TIMER1_CLKCTRL + * CM_L4PER_DMTIMER9_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL */ #define OMAP4430_CLKSEL_SHIFT 24 +#define OMAP4430_CLKSEL_WIDTH 0x1 #define OMAP4430_CLKSEL_MASK (1 << 24) /* @@ -438,50 +535,62 @@ * CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ, CM_L4_WKUP_CLKSEL */ #define OMAP4430_CLKSEL_0_0_SHIFT 0 +#define OMAP4430_CLKSEL_0_0_WIDTH 0x1 #define OMAP4430_CLKSEL_0_0_MASK (1 << 0) /* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */ #define OMAP4430_CLKSEL_0_1_SHIFT 0 +#define OMAP4430_CLKSEL_0_1_WIDTH 0x2 #define OMAP4430_CLKSEL_0_1_MASK (0x3 << 0) /* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */ #define OMAP4430_CLKSEL_24_25_SHIFT 24 +#define OMAP4430_CLKSEL_24_25_WIDTH 0x2 #define OMAP4430_CLKSEL_24_25_MASK (0x3 << 24) /* Used by CM_L3INIT_USB_OTG_CLKCTRL */ #define OMAP4430_CLKSEL_60M_SHIFT 24 +#define OMAP4430_CLKSEL_60M_WIDTH 0x1 #define OMAP4430_CLKSEL_60M_MASK (1 << 24) /* Used by CM_MPU_MPU_CLKCTRL */ #define OMAP4460_CLKSEL_ABE_DIV_MODE_SHIFT 25 +#define OMAP4460_CLKSEL_ABE_DIV_MODE_WIDTH 0x1 #define OMAP4460_CLKSEL_ABE_DIV_MODE_MASK (1 << 25) /* Used by CM1_ABE_AESS_CLKCTRL */ #define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24 +#define OMAP4430_CLKSEL_AESS_FCLK_WIDTH 0x1 #define OMAP4430_CLKSEL_AESS_FCLK_MASK (1 << 24) /* Used by CM_CLKSEL_CORE */ #define OMAP4430_CLKSEL_CORE_SHIFT 0 +#define OMAP4430_CLKSEL_CORE_WIDTH 0x1 #define OMAP4430_CLKSEL_CORE_MASK (1 << 0) /* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */ #define OMAP4430_CLKSEL_CORE_1_1_SHIFT 1 +#define OMAP4430_CLKSEL_CORE_1_1_WIDTH 0x1 #define OMAP4430_CLKSEL_CORE_1_1_MASK (1 << 1) /* Used by CM_WKUP_USIM_CLKCTRL */ #define OMAP4430_CLKSEL_DIV_SHIFT 24 +#define OMAP4430_CLKSEL_DIV_WIDTH 0x1 #define OMAP4430_CLKSEL_DIV_MASK (1 << 24) /* Used by CM_MPU_MPU_CLKCTRL */ #define OMAP4460_CLKSEL_EMIF_DIV_MODE_SHIFT 24 +#define OMAP4460_CLKSEL_EMIF_DIV_MODE_WIDTH 0x1 #define OMAP4460_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24) /* Used by CM_CAM_FDIF_CLKCTRL */ #define OMAP4430_CLKSEL_FCLK_SHIFT 24 +#define OMAP4430_CLKSEL_FCLK_WIDTH 0x2 #define OMAP4430_CLKSEL_FCLK_MASK (0x3 << 24) /* Used by CM_L4PER_MCBSP4_CLKCTRL */ #define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT 25 +#define OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH 0x1 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK (1 << 25) /* @@ -490,34 +599,42 @@ * CM1_ABE_MCBSP3_CLKCTRL */ #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT 26 +#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_WIDTH 0x2 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK (0x3 << 26) /* Used by CM_CLKSEL_CORE */ #define OMAP4430_CLKSEL_L3_SHIFT 4 +#define OMAP4430_CLKSEL_L3_WIDTH 0x1 #define OMAP4430_CLKSEL_L3_MASK (1 << 4) /* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */ #define OMAP4430_CLKSEL_L3_SHADOW_SHIFT 2 +#define OMAP4430_CLKSEL_L3_SHADOW_WIDTH 0x1 #define OMAP4430_CLKSEL_L3_SHADOW_MASK (1 << 2) /* Used by CM_CLKSEL_CORE */ #define OMAP4430_CLKSEL_L4_SHIFT 8 +#define OMAP4430_CLKSEL_L4_WIDTH 0x1 #define OMAP4430_CLKSEL_L4_MASK (1 << 8) /* Used by CM_CLKSEL_ABE */ #define OMAP4430_CLKSEL_OPP_SHIFT 0 +#define OMAP4430_CLKSEL_OPP_WIDTH 0x2 #define OMAP4430_CLKSEL_OPP_MASK (0x3 << 0) /* Used by CM_EMU_DEBUGSS_CLKCTRL */ #define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT 27 +#define OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH 0x3 #define OMAP4430_CLKSEL_PMD_STM_CLK_MASK (0x7 << 27) /* Used by CM_EMU_DEBUGSS_CLKCTRL */ #define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT 24 +#define OMAP4430_CLKSEL_PMD_TRACE_CLK_WIDTH 0x3 #define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK (0x7 << 24) /* Used by CM_GFX_GFX_CLKCTRL */ #define OMAP4430_CLKSEL_SGX_FCLK_SHIFT 24 +#define OMAP4430_CLKSEL_SGX_FCLK_WIDTH 0x1 #define OMAP4430_CLKSEL_SGX_FCLK_MASK (1 << 24) /* @@ -525,18 +642,22 @@ * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL */ #define OMAP4430_CLKSEL_SOURCE_SHIFT 24 +#define OMAP4430_CLKSEL_SOURCE_WIDTH 0x2 #define OMAP4430_CLKSEL_SOURCE_MASK (0x3 << 24) /* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */ #define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT 24 +#define OMAP4430_CLKSEL_SOURCE_24_24_WIDTH 0x1 #define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24) /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ #define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24 +#define OMAP4430_CLKSEL_UTMI_P1_WIDTH 0x1 #define OMAP4430_CLKSEL_UTMI_P1_MASK (1 << 24) /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ #define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25 +#define OMAP4430_CLKSEL_UTMI_P2_WIDTH 0x1 #define OMAP4430_CLKSEL_UTMI_P2_MASK (1 << 25) /* @@ -549,30 +670,37 @@ * CM_TESLA_CLKSTCTRL, CM_WKUP_CLKSTCTRL */ #define OMAP4430_CLKTRCTRL_SHIFT 0 +#define OMAP4430_CLKTRCTRL_WIDTH 0x2 #define OMAP4430_CLKTRCTRL_MASK (0x3 << 0) /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ #define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT 0 +#define OMAP4430_CORE_DPLL_EMU_DIV_WIDTH 0x7 #define OMAP4430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0) /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ #define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT 8 +#define OMAP4430_CORE_DPLL_EMU_MULT_WIDTH 0xb #define OMAP4430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8) /* Used by REVISION_CM1, REVISION_CM2 */ #define OMAP4430_CUSTOM_SHIFT 6 +#define OMAP4430_CUSTOM_WIDTH 0x2 #define OMAP4430_CUSTOM_MASK (0x3 << 6) /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ #define OMAP4430_D2D_DYNDEP_SHIFT 18 +#define OMAP4430_D2D_DYNDEP_WIDTH 0x1 #define OMAP4430_D2D_DYNDEP_MASK (1 << 18) /* Used by CM_MPU_STATICDEP */ #define OMAP4430_D2D_STATDEP_SHIFT 18 +#define OMAP4430_D2D_STATDEP_WIDTH 0x1 #define OMAP4430_D2D_STATDEP_MASK (1 << 18) /* Used by CM_CLKSEL_DPLL_MPU */ #define OMAP4460_DCC_COUNT_MAX_SHIFT 24 +#define OMAP4460_DCC_COUNT_MAX_WIDTH 0x8 #define OMAP4460_DCC_COUNT_MAX_MASK (0xff << 24) /* Used by CM_CLKSEL_DPLL_MPU */ @@ -586,22 +714,27 @@ * CM_SSC_DELTAMSTEP_DPLL_UNIPRO, CM_SSC_DELTAMSTEP_DPLL_USB */ #define OMAP4430_DELTAMSTEP_SHIFT 0 +#define OMAP4430_DELTAMSTEP_WIDTH 0x14 #define OMAP4430_DELTAMSTEP_MASK (0xfffff << 0) /* Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_USB */ #define OMAP4460_DELTAMSTEP_0_20_SHIFT 0 +#define OMAP4460_DELTAMSTEP_0_20_WIDTH 0x15 #define OMAP4460_DELTAMSTEP_0_20_MASK (0x1fffff << 0) /* Used by CM_DLL_CTRL */ #define OMAP4430_DLL_OVERRIDE_SHIFT 0 +#define OMAP4430_DLL_OVERRIDE_WIDTH 0x1 #define OMAP4430_DLL_OVERRIDE_MASK (1 << 0) /* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */ #define OMAP4430_DLL_OVERRIDE_2_2_SHIFT 2 +#define OMAP4430_DLL_OVERRIDE_2_2_WIDTH 0x1 #define OMAP4430_DLL_OVERRIDE_2_2_MASK (1 << 2) /* Used by CM_SHADOW_FREQ_CONFIG1 */ #define OMAP4430_DLL_RESET_SHIFT 3 +#define OMAP4430_DLL_RESET_WIDTH 0x1 #define OMAP4430_DLL_RESET_MASK (1 << 3) /* @@ -610,30 +743,37 @@ * CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB */ #define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23 +#define OMAP4430_DPLL_BYP_CLKSEL_WIDTH 0x1 #define OMAP4430_DPLL_BYP_CLKSEL_MASK (1 << 23) /* Used by CM_CLKDCOLDO_DPLL_USB */ #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8 +#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH 0x1 #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8) /* Used by CM_CLKSEL_DPLL_CORE */ #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20 +#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_WIDTH 0x1 #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20) /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */ #define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT 0 +#define OMAP4430_DPLL_CLKOUTHIF_DIV_WIDTH 0x5 #define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0) /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */ #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT 5 +#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_WIDTH 0x1 #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK (1 << 5) /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */ #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8 +#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_WIDTH 0x1 #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK (1 << 8) /* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */ #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT 10 +#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_WIDTH 0x1 #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10) /* @@ -641,10 +781,12 @@ * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */ #define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0 +#define OMAP4430_DPLL_CLKOUT_DIV_WIDTH 0x5 #define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0) /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */ #define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT 0 +#define OMAP4430_DPLL_CLKOUT_DIV_0_6_WIDTH 0x7 #define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0) /* @@ -652,10 +794,12 @@ * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */ #define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT 5 +#define OMAP4430_DPLL_CLKOUT_DIVCHACK_WIDTH 0x1 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5) /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */ #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT 7 +#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_WIDTH 0x1 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK (1 << 7) /* @@ -663,18 +807,22 @@ * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB */ #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT 8 +#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_WIDTH 0x1 #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) /* Used by CM_SHADOW_FREQ_CONFIG1 */ #define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT 8 +#define OMAP4430_DPLL_CORE_DPLL_EN_WIDTH 0x3 #define OMAP4430_DPLL_CORE_DPLL_EN_MASK (0x7 << 8) /* Used by CM_SHADOW_FREQ_CONFIG1 */ #define OMAP4430_DPLL_CORE_M2_DIV_SHIFT 11 +#define OMAP4430_DPLL_CORE_M2_DIV_WIDTH 0x5 #define OMAP4430_DPLL_CORE_M2_DIV_MASK (0x1f << 11) /* Used by CM_SHADOW_FREQ_CONFIG2 */ #define OMAP4430_DPLL_CORE_M5_DIV_SHIFT 3 +#define OMAP4430_DPLL_CORE_M5_DIV_WIDTH 0x5 #define OMAP4430_DPLL_CORE_M5_DIV_MASK (0x1f << 3) /* @@ -683,10 +831,12 @@ * CM_CLKSEL_DPLL_UNIPRO */ #define OMAP4430_DPLL_DIV_SHIFT 0 +#define OMAP4430_DPLL_DIV_WIDTH 0x7 #define OMAP4430_DPLL_DIV_MASK (0x7f << 0) /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */ #define OMAP4430_DPLL_DIV_0_7_SHIFT 0 +#define OMAP4430_DPLL_DIV_0_7_WIDTH 0x8 #define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0) /* @@ -694,10 +844,12 @@ * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER */ #define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT 8 +#define OMAP4430_DPLL_DRIFTGUARD_EN_WIDTH 0x1 #define OMAP4430_DPLL_DRIFTGUARD_EN_MASK (1 << 8) /* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */ #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT 3 +#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_WIDTH 0x1 #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK (1 << 3) /* @@ -706,6 +858,7 @@ * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB */ #define OMAP4430_DPLL_EN_SHIFT 0 +#define OMAP4430_DPLL_EN_WIDTH 0x3 #define OMAP4430_DPLL_EN_MASK (0x7 << 0) /* @@ -714,6 +867,7 @@ * CM_CLKMODE_DPLL_UNIPRO */ #define OMAP4430_DPLL_LPMODE_EN_SHIFT 10 +#define OMAP4430_DPLL_LPMODE_EN_WIDTH 0x1 #define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10) /* @@ -722,10 +876,12 @@ * CM_CLKSEL_DPLL_UNIPRO */ #define OMAP4430_DPLL_MULT_SHIFT 8 +#define OMAP4430_DPLL_MULT_WIDTH 0xb #define OMAP4430_DPLL_MULT_MASK (0x7ff << 8) /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */ #define OMAP4430_DPLL_MULT_USB_SHIFT 8 +#define OMAP4430_DPLL_MULT_USB_WIDTH 0xc #define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8) /* @@ -734,10 +890,12 @@ * CM_CLKMODE_DPLL_UNIPRO */ #define OMAP4430_DPLL_REGM4XEN_SHIFT 11 +#define OMAP4430_DPLL_REGM4XEN_WIDTH 0x1 #define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11) /* Used by CM_CLKSEL_DPLL_USB */ #define OMAP4430_DPLL_SD_DIV_SHIFT 24 +#define OMAP4430_DPLL_SD_DIV_WIDTH 0x8 #define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24) /* @@ -746,6 +904,7 @@ * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB */ #define OMAP4430_DPLL_SSC_ACK_SHIFT 13 +#define OMAP4430_DPLL_SSC_ACK_WIDTH 0x1 #define OMAP4430_DPLL_SSC_ACK_MASK (1 << 13) /* @@ -754,6 +913,7 @@ * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB */ #define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT 14 +#define OMAP4430_DPLL_SSC_DOWNSPREAD_WIDTH 0x1 #define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) /* @@ -762,42 +922,52 @@ * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB */ #define OMAP4430_DPLL_SSC_EN_SHIFT 12 +#define OMAP4430_DPLL_SSC_EN_WIDTH 0x1 #define OMAP4430_DPLL_SSC_EN_MASK (1 << 12) /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ #define OMAP4430_DSS_DYNDEP_SHIFT 8 +#define OMAP4430_DSS_DYNDEP_WIDTH 0x1 #define OMAP4430_DSS_DYNDEP_MASK (1 << 8) /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP */ #define OMAP4430_DSS_STATDEP_SHIFT 8 +#define OMAP4430_DSS_STATDEP_WIDTH 0x1 #define OMAP4430_DSS_STATDEP_MASK (1 << 8) /* Used by CM_L3_2_DYNAMICDEP */ #define OMAP4430_DUCATI_DYNDEP_SHIFT 0 +#define OMAP4430_DUCATI_DYNDEP_WIDTH 0x1 #define OMAP4430_DUCATI_DYNDEP_MASK (1 << 0) /* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP */ #define OMAP4430_DUCATI_STATDEP_SHIFT 0 +#define OMAP4430_DUCATI_STATDEP_WIDTH 0x1 #define OMAP4430_DUCATI_STATDEP_MASK (1 << 0) /* Used by CM_SHADOW_FREQ_CONFIG1 */ #define OMAP4430_FREQ_UPDATE_SHIFT 0 +#define OMAP4430_FREQ_UPDATE_WIDTH 0x1 #define OMAP4430_FREQ_UPDATE_MASK (1 << 0) /* Used by REVISION_CM1, REVISION_CM2 */ #define OMAP4430_FUNC_SHIFT 16 +#define OMAP4430_FUNC_WIDTH 0xc #define OMAP4430_FUNC_MASK (0xfff << 16) /* Used by CM_L3_2_DYNAMICDEP */ #define OMAP4430_GFX_DYNDEP_SHIFT 10 +#define OMAP4430_GFX_DYNDEP_WIDTH 0x1 #define OMAP4430_GFX_DYNDEP_MASK (1 << 10) /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ #define OMAP4430_GFX_STATDEP_SHIFT 10 +#define OMAP4430_GFX_STATDEP_WIDTH 0x1 #define OMAP4430_GFX_STATDEP_MASK (1 << 10) /* Used by CM_SHADOW_FREQ_CONFIG2 */ #define OMAP4430_GPMC_FREQ_UPDATE_SHIFT 0 +#define OMAP4430_GPMC_FREQ_UPDATE_WIDTH 0x1 #define OMAP4430_GPMC_FREQ_UPDATE_MASK (1 << 0) /* @@ -805,6 +975,7 @@ * CM_DIV_M4_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 +#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_WIDTH 0x5 #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0) /* @@ -812,6 +983,7 @@ * CM_DIV_M4_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5 +#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH 0x1 #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5) /* @@ -819,6 +991,7 @@ * CM_DIV_M4_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8 +#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH 0x1 #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8) /* @@ -826,6 +999,7 @@ * CM_DIV_M4_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12 +#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_WIDTH 0x1 #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12) /* @@ -833,6 +1007,7 @@ * CM_DIV_M5_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 +#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_WIDTH 0x5 #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0) /* @@ -840,6 +1015,7 @@ * CM_DIV_M5_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5 +#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_WIDTH 0x1 #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5) /* @@ -847,6 +1023,7 @@ * CM_DIV_M5_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8 +#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_WIDTH 0x1 #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8) /* @@ -854,38 +1031,47 @@ * CM_DIV_M5_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12 +#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_WIDTH 0x1 #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12) /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 +#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_WIDTH 0x5 #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0) /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5 +#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_WIDTH 0x1 #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5) /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8 +#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_WIDTH 0x1 #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8) /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12 +#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_WIDTH 0x1 #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12) /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT 0 +#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_WIDTH 0x5 #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0) /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT 5 +#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_WIDTH 0x1 #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK (1 << 5) /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT 8 +#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_WIDTH 0x1 #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK (1 << 8) /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT 12 +#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_WIDTH 0x1 #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK (1 << 12) /* @@ -893,53 +1079,48 @@ * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, - * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL, - * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, - * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, - * CM_CM1_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL, - * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, - * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, + * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, + * CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, CM_CAM_FDIF_CLKCTRL, + * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, CM_CM1_PROFILING_CLKCTRL, + * CM_CM2_PROFILING_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, + * CM_D2D_SAD2D_FW_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, - * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, - * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, - * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, - * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, - * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL, - * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL, - * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL, - * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL, - * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL, - * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL, - * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL, + * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, + * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, + * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL, + * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, + * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, + * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, + * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, + * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL, * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL, * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, - * CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, - * CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, - * CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, - * CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, - * CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, - * CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL, - * CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL, - * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, - * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, - * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, + * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, + * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, + * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, + * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, + * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, + * CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, + * CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, + * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL, * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, - * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL, - * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, + * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL, - * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, - * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, - * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL + * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, + * CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, + * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL */ #define OMAP4430_IDLEST_SHIFT 16 +#define OMAP4430_IDLEST_WIDTH 0x2 #define OMAP4430_IDLEST_MASK (0x3 << 16) /* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ #define OMAP4430_ISS_DYNDEP_SHIFT 9 +#define OMAP4430_ISS_DYNDEP_WIDTH 0x1 #define OMAP4430_ISS_DYNDEP_MASK (1 << 9) /* @@ -947,10 +1128,12 @@ * CM_TESLA_STATICDEP */ #define OMAP4430_ISS_STATDEP_SHIFT 9 +#define OMAP4430_ISS_STATDEP_WIDTH 0x1 #define OMAP4430_ISS_STATDEP_MASK (1 << 9) /* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ #define OMAP4430_IVAHD_DYNDEP_SHIFT 2 +#define OMAP4430_IVAHD_DYNDEP_WIDTH 0x1 #define OMAP4430_IVAHD_DYNDEP_MASK (1 << 2) /* @@ -959,10 +1142,12 @@ * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_IVAHD_STATDEP_SHIFT 2 +#define OMAP4430_IVAHD_STATDEP_WIDTH 0x1 #define OMAP4430_IVAHD_STATDEP_MASK (1 << 2) /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ #define OMAP4430_L3INIT_DYNDEP_SHIFT 7 +#define OMAP4430_L3INIT_DYNDEP_WIDTH 0x1 #define OMAP4430_L3INIT_DYNDEP_MASK (1 << 7) /* @@ -970,6 +1155,7 @@ * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_L3INIT_STATDEP_SHIFT 7 +#define OMAP4430_L3INIT_STATDEP_WIDTH 0x1 #define OMAP4430_L3INIT_STATDEP_MASK (1 << 7) /* @@ -977,6 +1163,7 @@ * CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ #define OMAP4430_L3_1_DYNDEP_SHIFT 5 +#define OMAP4430_L3_1_DYNDEP_WIDTH 0x1 #define OMAP4430_L3_1_DYNDEP_MASK (1 << 5) /* @@ -986,6 +1173,7 @@ * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_L3_1_STATDEP_SHIFT 5 +#define OMAP4430_L3_1_STATDEP_WIDTH 0x1 #define OMAP4430_L3_1_STATDEP_MASK (1 << 5) /* @@ -995,6 +1183,7 @@ * CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP */ #define OMAP4430_L3_2_DYNDEP_SHIFT 6 +#define OMAP4430_L3_2_DYNDEP_WIDTH 0x1 #define OMAP4430_L3_2_DYNDEP_MASK (1 << 6) /* @@ -1004,10 +1193,12 @@ * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_L3_2_STATDEP_SHIFT 6 +#define OMAP4430_L3_2_STATDEP_WIDTH 0x1 #define OMAP4430_L3_2_STATDEP_MASK (1 << 6) /* Used by CM_L3_1_DYNAMICDEP */ #define OMAP4430_L4CFG_DYNDEP_SHIFT 12 +#define OMAP4430_L4CFG_DYNDEP_WIDTH 0x1 #define OMAP4430_L4CFG_DYNDEP_MASK (1 << 12) /* @@ -1015,10 +1206,12 @@ * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_L4CFG_STATDEP_SHIFT 12 +#define OMAP4430_L4CFG_STATDEP_WIDTH 0x1 #define OMAP4430_L4CFG_STATDEP_MASK (1 << 12) /* Used by CM_L3_2_DYNAMICDEP */ #define OMAP4430_L4PER_DYNDEP_SHIFT 13 +#define OMAP4430_L4PER_DYNDEP_WIDTH 0x1 #define OMAP4430_L4PER_DYNDEP_MASK (1 << 13) /* @@ -1026,10 +1219,12 @@ * CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_L4PER_STATDEP_SHIFT 13 +#define OMAP4430_L4PER_STATDEP_WIDTH 0x1 #define OMAP4430_L4PER_STATDEP_MASK (1 << 13) /* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ #define OMAP4430_L4SEC_DYNDEP_SHIFT 14 +#define OMAP4430_L4SEC_DYNDEP_WIDTH 0x1 #define OMAP4430_L4SEC_DYNDEP_MASK (1 << 14) /* @@ -1037,10 +1232,12 @@ * CM_SDMA_STATICDEP */ #define OMAP4430_L4SEC_STATDEP_SHIFT 14 +#define OMAP4430_L4SEC_STATDEP_WIDTH 0x1 #define OMAP4430_L4SEC_STATDEP_MASK (1 << 14) /* Used by CM_L4CFG_DYNAMICDEP */ #define OMAP4430_L4WKUP_DYNDEP_SHIFT 15 +#define OMAP4430_L4WKUP_DYNDEP_WIDTH 0x1 #define OMAP4430_L4WKUP_DYNDEP_MASK (1 << 15) /* @@ -1048,6 +1245,7 @@ * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_L4WKUP_STATDEP_SHIFT 15 +#define OMAP4430_L4WKUP_STATDEP_WIDTH 0x1 #define OMAP4430_L4WKUP_STATDEP_MASK (1 << 15) /* @@ -1055,6 +1253,7 @@ * CM_MPU_DYNAMICDEP */ #define OMAP4430_MEMIF_DYNDEP_SHIFT 4 +#define OMAP4430_MEMIF_DYNDEP_WIDTH 0x1 #define OMAP4430_MEMIF_DYNDEP_MASK (1 << 4) /* @@ -1064,6 +1263,7 @@ * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_MEMIF_STATDEP_SHIFT 4 +#define OMAP4430_MEMIF_STATDEP_WIDTH 0x1 #define OMAP4430_MEMIF_STATDEP_MASK (1 << 4) /* @@ -1073,6 +1273,7 @@ * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB */ #define OMAP4430_MODFREQDIV_EXPONENT_SHIFT 8 +#define OMAP4430_MODFREQDIV_EXPONENT_WIDTH 0x3 #define OMAP4430_MODFREQDIV_EXPONENT_MASK (0x7 << 8) /* @@ -1082,6 +1283,7 @@ * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB */ #define OMAP4430_MODFREQDIV_MANTISSA_SHIFT 0 +#define OMAP4430_MODFREQDIV_MANTISSA_WIDTH 0x7 #define OMAP4430_MODFREQDIV_MANTISSA_MASK (0x7f << 0) /* @@ -1089,69 +1291,68 @@ * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, - * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL, - * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, - * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, - * CM_CM1_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL, - * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, - * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, + * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, + * CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, CM_CAM_FDIF_CLKCTRL, + * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, CM_CM1_PROFILING_CLKCTRL, + * CM_CM2_PROFILING_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, + * CM_D2D_SAD2D_FW_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, - * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, - * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, - * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, - * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, - * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL, - * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL, - * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL, - * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL, - * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL, - * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL, - * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL, + * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, + * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, + * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL, + * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, + * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, + * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, + * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, + * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL, * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL, * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, - * CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, - * CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, - * CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, - * CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, - * CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, - * CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL, - * CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL, - * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, - * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, - * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, + * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, + * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, + * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, + * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, + * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, + * CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, + * CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, + * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL, * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, - * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL, - * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, + * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL, - * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, - * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, - * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL + * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, + * CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, + * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL */ #define OMAP4430_MODULEMODE_SHIFT 0 +#define OMAP4430_MODULEMODE_WIDTH 0x2 #define OMAP4430_MODULEMODE_MASK (0x3 << 0) /* Used by CM_L4CFG_DYNAMICDEP */ #define OMAP4460_MPU_DYNDEP_SHIFT 19 +#define OMAP4460_MPU_DYNDEP_WIDTH 0x1 #define OMAP4460_MPU_DYNDEP_MASK (1 << 19) /* Used by CM_DSS_DSS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9 +#define OMAP4430_OPTFCLKEN_48MHZ_CLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9) /* Used by CM_WKUP_BANDGAP_CLKCTRL */ #define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT 8 +#define OMAP4430_OPTFCLKEN_BGAP_32K_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_BGAP_32K_MASK (1 << 8) /* Used by CM_ALWON_USBPHY_CLKCTRL */ #define OMAP4430_OPTFCLKEN_CLK32K_SHIFT 8 +#define OMAP4430_OPTFCLKEN_CLK32K_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_CLK32K_MASK (1 << 8) /* Used by CM_CAM_ISS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT 8 +#define OMAP4430_OPTFCLKEN_CTRLCLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_CTRLCLK_MASK (1 << 8) /* @@ -1160,126 +1361,157 @@ * CM_WKUP_GPIO1_CLKCTRL */ #define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8 +#define OMAP4430_OPTFCLKEN_DBCLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_DBCLK_MASK (1 << 8) /* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */ #define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT 8 +#define OMAP4430_OPTFCLKEN_DLL_CLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_DLL_CLK_MASK (1 << 8) /* Used by CM_DSS_DSS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT 8 +#define OMAP4430_OPTFCLKEN_DSSCLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_DSSCLK_MASK (1 << 8) /* Used by CM_WKUP_USIM_CLKCTRL */ #define OMAP4430_OPTFCLKEN_FCLK_SHIFT 8 +#define OMAP4430_OPTFCLKEN_FCLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_FCLK_MASK (1 << 8) /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_FCLK0_SHIFT 8 +#define OMAP4430_OPTFCLKEN_FCLK0_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_FCLK0_MASK (1 << 8) /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_FCLK1_SHIFT 9 +#define OMAP4430_OPTFCLKEN_FCLK1_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_FCLK1_MASK (1 << 9) /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10 +#define OMAP4430_OPTFCLKEN_FCLK2_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_FCLK2_MASK (1 << 10) /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ #define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15 +#define OMAP4430_OPTFCLKEN_FUNC48MCLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK (1 << 15) /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 +#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13) /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 +#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14) /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 +#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11) /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 +#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12) /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT 8 +#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK (1 << 8) /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT 9 +#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK (1 << 9) /* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */ #define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT 8 +#define OMAP4430_OPTFCLKEN_PHY_48M_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_PHY_48M_MASK (1 << 8) /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT 10 +#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK (1 << 10) /* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT 11 +#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK (1 << 11) /* Used by CM_DSS_DSS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10 +#define OMAP4430_OPTFCLKEN_SYS_CLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_SYS_CLK_MASK (1 << 10) /* Used by CM_WKUP_BANDGAP_CLKCTRL */ #define OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT 8 +#define OMAP4460_OPTFCLKEN_TS_FCLK_WIDTH 0x1 #define OMAP4460_OPTFCLKEN_TS_FCLK_MASK (1 << 8) /* Used by CM_DSS_DSS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11 +#define OMAP4430_OPTFCLKEN_TV_CLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_TV_CLK_MASK (1 << 11) /* Used by CM_L3INIT_UNIPRO1_CLKCTRL */ #define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT 8 +#define OMAP4430_OPTFCLKEN_TXPHYCLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK (1 << 8) /* Used by CM_L3INIT_USB_TLL_CLKCTRL */ #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 +#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8) /* Used by CM_L3INIT_USB_TLL_CLKCTRL */ #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 +#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9) /* Used by CM_L3INIT_USB_TLL_CLKCTRL */ #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 +#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10) /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 +#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8) /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 +#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9) /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 +#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10) /* Used by CM_L3INIT_USB_OTG_CLKCTRL */ #define OMAP4430_OPTFCLKEN_XCLK_SHIFT 8 +#define OMAP4430_OPTFCLKEN_XCLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_XCLK_MASK (1 << 8) /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ #define OMAP4430_OVERRIDE_ENABLE_SHIFT 19 +#define OMAP4430_OVERRIDE_ENABLE_WIDTH 0x1 #define OMAP4430_OVERRIDE_ENABLE_MASK (1 << 19) /* Used by CM_CLKSEL_ABE */ #define OMAP4430_PAD_CLKS_GATE_SHIFT 8 +#define OMAP4430_PAD_CLKS_GATE_WIDTH 0x1 #define OMAP4430_PAD_CLKS_GATE_MASK (1 << 8) /* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */ #define OMAP4430_PERF_CURRENT_SHIFT 0 +#define OMAP4430_PERF_CURRENT_WIDTH 0x8 #define OMAP4430_PERF_CURRENT_MASK (0xff << 0) /* @@ -1288,74 +1520,85 @@ * CM_IVA_DVFS_PERF_TESLA */ #define OMAP4430_PERF_REQ_SHIFT 0 +#define OMAP4430_PERF_REQ_WIDTH 0x8 #define OMAP4430_PERF_REQ_MASK (0xff << 0) /* Used by CM_RESTORE_ST */ #define OMAP4430_PHASE1_COMPLETED_SHIFT 0 +#define OMAP4430_PHASE1_COMPLETED_WIDTH 0x1 #define OMAP4430_PHASE1_COMPLETED_MASK (1 << 0) /* Used by CM_RESTORE_ST */ #define OMAP4430_PHASE2A_COMPLETED_SHIFT 1 +#define OMAP4430_PHASE2A_COMPLETED_WIDTH 0x1 #define OMAP4430_PHASE2A_COMPLETED_MASK (1 << 1) /* Used by CM_RESTORE_ST */ #define OMAP4430_PHASE2B_COMPLETED_SHIFT 2 +#define OMAP4430_PHASE2B_COMPLETED_WIDTH 0x1 #define OMAP4430_PHASE2B_COMPLETED_MASK (1 << 2) /* Used by CM_EMU_DEBUGSS_CLKCTRL */ #define OMAP4430_PMD_STM_MUX_CTRL_SHIFT 20 +#define OMAP4430_PMD_STM_MUX_CTRL_WIDTH 0x2 #define OMAP4430_PMD_STM_MUX_CTRL_MASK (0x3 << 20) /* Used by CM_EMU_DEBUGSS_CLKCTRL */ #define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22 +#define OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH 0x2 #define OMAP4430_PMD_TRACE_MUX_CTRL_MASK (0x3 << 22) /* Used by CM_DYN_DEP_PRESCAL */ #define OMAP4430_PRESCAL_SHIFT 0 +#define OMAP4430_PRESCAL_WIDTH 0x6 #define OMAP4430_PRESCAL_MASK (0x3f << 0) /* Used by REVISION_CM1, REVISION_CM2 */ #define OMAP4430_R_RTL_SHIFT 11 +#define OMAP4430_R_RTL_WIDTH 0x5 #define OMAP4430_R_RTL_MASK (0x1f << 11) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL */ #define OMAP4430_SAR_MODE_SHIFT 4 +#define OMAP4430_SAR_MODE_WIDTH 0x1 #define OMAP4430_SAR_MODE_MASK (1 << 4) /* Used by CM_SCALE_FCLK */ #define OMAP4430_SCALE_FCLK_SHIFT 0 +#define OMAP4430_SCALE_FCLK_WIDTH 0x1 #define OMAP4430_SCALE_FCLK_MASK (1 << 0) /* Used by REVISION_CM1, REVISION_CM2 */ #define OMAP4430_SCHEME_SHIFT 30 +#define OMAP4430_SCHEME_WIDTH 0x2 #define OMAP4430_SCHEME_MASK (0x3 << 30) /* Used by CM_L4CFG_DYNAMICDEP */ #define OMAP4430_SDMA_DYNDEP_SHIFT 11 +#define OMAP4430_SDMA_DYNDEP_WIDTH 0x1 #define OMAP4430_SDMA_DYNDEP_MASK (1 << 11) /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ #define OMAP4430_SDMA_STATDEP_SHIFT 11 +#define OMAP4430_SDMA_STATDEP_WIDTH 0x1 #define OMAP4430_SDMA_STATDEP_MASK (1 << 11) /* Used by CM_CLKSEL_ABE */ #define OMAP4430_SLIMBUS_CLK_GATE_SHIFT 10 +#define OMAP4430_SLIMBUS_CLK_GATE_WIDTH 0x1 #define OMAP4430_SLIMBUS_CLK_GATE_MASK (1 << 10) /* * Used by CM1_ABE_AESS_CLKCTRL, CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, - * CM_D2D_SAD2D_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, - * CM_DUCATI_DUCATI_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, - * CM_IVAHD_IVAHD_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, + * CM_D2D_SAD2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, + * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, - * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, - * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL, - * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, - * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, - * CM_TESLA_TESLA_CLKCTRL + * CM_L3INIT_USB_OTG_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL, + * CM_SDMA_SDMA_CLKCTRL, CM_TESLA_TESLA_CLKCTRL */ #define OMAP4430_STBYST_SHIFT 18 +#define OMAP4430_STBYST_WIDTH 0x1 #define OMAP4430_STBYST_MASK (1 << 18) /* @@ -1364,10 +1607,12 @@ * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB */ #define OMAP4430_ST_DPLL_CLK_SHIFT 0 +#define OMAP4430_ST_DPLL_CLK_WIDTH 0x1 #define OMAP4430_ST_DPLL_CLK_MASK (1 << 0) /* Used by CM_CLKDCOLDO_DPLL_USB */ #define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT 9 +#define OMAP4430_ST_DPLL_CLKDCOLDO_WIDTH 0x1 #define OMAP4430_ST_DPLL_CLKDCOLDO_MASK (1 << 9) /* @@ -1375,14 +1620,17 @@ * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB */ #define OMAP4430_ST_DPLL_CLKOUT_SHIFT 9 +#define OMAP4430_ST_DPLL_CLKOUT_WIDTH 0x1 #define OMAP4430_ST_DPLL_CLKOUT_MASK (1 << 9) /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */ #define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT 9 +#define OMAP4430_ST_DPLL_CLKOUTHIF_WIDTH 0x1 #define OMAP4430_ST_DPLL_CLKOUTHIF_MASK (1 << 9) /* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */ #define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT 11 +#define OMAP4430_ST_DPLL_CLKOUTX2_WIDTH 0x1 #define OMAP4430_ST_DPLL_CLKOUTX2_MASK (1 << 11) /* @@ -1390,6 +1638,7 @@ * CM_DIV_M4_DPLL_PER */ #define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT 9 +#define OMAP4430_ST_HSDIVIDER_CLKOUT1_WIDTH 0x1 #define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9) /* @@ -1397,14 +1646,17 @@ * CM_DIV_M5_DPLL_PER */ #define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT 9 +#define OMAP4430_ST_HSDIVIDER_CLKOUT2_WIDTH 0x1 #define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9) /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ #define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT 9 +#define OMAP4430_ST_HSDIVIDER_CLKOUT3_WIDTH 0x1 #define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9) /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ #define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT 9 +#define OMAP4430_ST_HSDIVIDER_CLKOUT4_WIDTH 0x1 #define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK (1 << 9) /* @@ -1413,18 +1665,22 @@ * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB */ #define OMAP4430_ST_MN_BYPASS_SHIFT 8 +#define OMAP4430_ST_MN_BYPASS_WIDTH 0x1 #define OMAP4430_ST_MN_BYPASS_MASK (1 << 8) /* Used by CM_SYS_CLKSEL */ #define OMAP4430_SYS_CLKSEL_SHIFT 0 +#define OMAP4430_SYS_CLKSEL_WIDTH 0x3 #define OMAP4430_SYS_CLKSEL_MASK (0x7 << 0) /* Used by CM_L4CFG_DYNAMICDEP */ #define OMAP4430_TESLA_DYNDEP_SHIFT 1 +#define OMAP4430_TESLA_DYNDEP_WIDTH 0x1 #define OMAP4430_TESLA_DYNDEP_MASK (1 << 1) /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ #define OMAP4430_TESLA_STATDEP_SHIFT 1 +#define OMAP4430_TESLA_STATDEP_WIDTH 0x1 #define OMAP4430_TESLA_STATDEP_MASK (1 << 1) /* @@ -1433,13 +1689,16 @@ * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ #define OMAP4430_WINDOWSIZE_SHIFT 24 +#define OMAP4430_WINDOWSIZE_WIDTH 0x4 #define OMAP4430_WINDOWSIZE_MASK (0xf << 24) /* Used by REVISION_CM1, REVISION_CM2 */ #define OMAP4430_X_MAJOR_SHIFT 8 +#define OMAP4430_X_MAJOR_WIDTH 0x3 #define OMAP4430_X_MAJOR_MASK (0x7 << 8) /* Used by REVISION_CM1, REVISION_CM2 */ #define OMAP4430_Y_MINOR_SHIFT 0 +#define OMAP4430_Y_MINOR_WIDTH 0x6 #define OMAP4430_Y_MINOR_MASK (0x3f << 0) #endif diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm2xxx_3xxx.c index a911e76b4ecf..7f07ab02a5b3 100644 --- a/arch/arm/mach-omap2/cm2xxx_3xxx.c +++ b/arch/arm/mach-omap2/cm2xxx_3xxx.c @@ -35,7 +35,7 @@ #define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP 0x3 static const u8 cm_idlest_offs[] = { - CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3 + CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3, OMAP24XX_CM_IDLEST4 }; u32 omap2_cm_read_mod_reg(s16 module, u16 idx) diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h index 088bbad73db5..57b2f3c2fbf3 100644 --- a/arch/arm/mach-omap2/cm2xxx_3xxx.h +++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h @@ -71,6 +71,7 @@ #define OMAP24XX_CM_FCLKEN2 0x0004 #define OMAP24XX_CM_ICLKEN4 0x001c #define OMAP24XX_CM_AUTOIDLE4 0x003c +#define OMAP24XX_CM_IDLEST4 0x002c #define OMAP2430_CM_IDLEST3 0x0028 diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h index 123186ac7d2e..a89e8256fd0e 100644 --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h @@ -354,6 +354,7 @@ /* AM33XX CONTROL_STATUS bitfields (partial) */ #define AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT 22 +#define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH 0x2 #define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK (0x3 << 22) /* CONTROL OMAP STATUS register to identify OMAP3 features */ diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index d092d2a89ee0..cba60e05e32e 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -341,7 +341,7 @@ static void __init omap_init_dmic(void) oh = omap_hwmod_lookup("dmic"); if (!oh) { - printk(KERN_ERR "Could not look up mcpdm hw_mod\n"); + pr_err("Could not look up dmic hw_mod\n"); return; } @@ -433,35 +433,24 @@ static void omap_init_mcspi(void) static inline void omap_init_mcspi(void) {} #endif -static struct resource omap2_pmu_resource = { - .start = 3 + OMAP_INTC_START, - .flags = IORESOURCE_IRQ, -}; - -static struct resource omap3_pmu_resource = { - .start = 3 + OMAP_INTC_START, - .flags = IORESOURCE_IRQ, -}; - -static struct platform_device omap_pmu_device = { - .name = "arm-pmu", - .id = -1, - .num_resources = 1, -}; - -static void omap_init_pmu(void) +/** + * omap_init_rng - bind the RNG hwmod to the RNG omap_device + * + * Bind the RNG hwmod to the RNG omap_device. No return value. + */ +static void omap_init_rng(void) { - if (cpu_is_omap24xx()) - omap_pmu_device.resource = &omap2_pmu_resource; - else if (cpu_is_omap34xx()) - omap_pmu_device.resource = &omap3_pmu_resource; - else + struct omap_hwmod *oh; + struct platform_device *pdev; + + oh = omap_hwmod_lookup("rng"); + if (!oh) return; - platform_device_register(&omap_pmu_device); + pdev = omap_device_build("omap_rng", -1, oh, NULL, 0, NULL, 0, 0); + WARN(IS_ERR(pdev), "Can't build omap_device for omap_rng\n"); } - #if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE) #ifdef CONFIG_ARCH_OMAP2 @@ -646,8 +635,8 @@ static int __init omap2_init_devices(void) omap_init_mcpdm(); omap_init_mcspi(); } - omap_init_pmu(); omap_init_sti(); + omap_init_rng(); omap_init_sham(); omap_init_aes(); omap_init_vout(); diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c index af1ed7d24a1f..1011995f150a 100644 --- a/arch/arm/mach-omap2/display.c +++ b/arch/arm/mach-omap2/display.c @@ -76,14 +76,14 @@ struct omap_dss_hwmod_data { const int id; }; -static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initdata = { +static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initconst = { { "dss_core", "omapdss_dss", -1 }, { "dss_dispc", "omapdss_dispc", -1 }, { "dss_rfbi", "omapdss_rfbi", -1 }, { "dss_venc", "omapdss_venc", -1 }, }; -static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initdata = { +static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initconst = { { "dss_core", "omapdss_dss", -1 }, { "dss_dispc", "omapdss_dispc", -1 }, { "dss_rfbi", "omapdss_rfbi", -1 }, @@ -91,11 +91,10 @@ static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initdata = { { "dss_dsi1", "omapdss_dsi", 0 }, }; -static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initdata = { +static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = { { "dss_core", "omapdss_dss", -1 }, { "dss_dispc", "omapdss_dispc", -1 }, { "dss_rfbi", "omapdss_rfbi", -1 }, - { "dss_venc", "omapdss_venc", -1 }, { "dss_dsi1", "omapdss_dsi", 0 }, { "dss_dsi2", "omapdss_dsi", 1 }, { "dss_hdmi", "omapdss_hdmi", -1 }, @@ -221,7 +220,7 @@ static struct platform_device *create_dss_pdev(const char *pdev_name, ohs[0] = oh; od = omap_device_alloc(pdev, ohs, 1, NULL, 0); - if (!od) { + if (IS_ERR(od)) { pr_err("Could not alloc omap_device for %s\n", pdev_name); r = -ENOMEM; goto err; @@ -488,7 +487,7 @@ int omap_dss_reset(struct omap_hwmod *oh) for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) if (oc->_clk) - clk_enable(oc->_clk); + clk_prepare_enable(oc->_clk); dispc_disable_outputs(); @@ -515,7 +514,7 @@ int omap_dss_reset(struct omap_hwmod *oh) for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) if (oc->_clk) - clk_disable(oc->_clk); + clk_disable_unprepare(oc->_clk); r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0; diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index 27d79deb4ba2..814e1808e158 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c @@ -63,8 +63,10 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state) const struct dpll_data *dd; int i = 0; int ret = -EINVAL; + const char *clk_name; dd = clk->dpll_data; + clk_name = __clk_get_name(clk); state <<= __ffs(dd->idlest_mask); @@ -76,10 +78,10 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state) if (i == MAX_DPLL_WAIT_TRIES) { printk(KERN_ERR "clock: %s failed transition to '%s'\n", - clk->name, (state) ? "locked" : "bypassed"); + clk_name, (state) ? "locked" : "bypassed"); } else { pr_debug("clock: %s transition to '%s' in %d loops\n", - clk->name, (state) ? "locked" : "bypassed", i); + clk_name, (state) ? "locked" : "bypassed", i); ret = 0; } @@ -93,7 +95,7 @@ static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n) unsigned long fint; u16 f = 0; - fint = clk->dpll_data->clk_ref->rate / n; + fint = __clk_get_rate(clk->dpll_data->clk_ref) / n; pr_debug("clock: fint is %lu\n", fint); @@ -140,7 +142,7 @@ static int _omap3_noncore_dpll_lock(struct clk *clk) u8 state = 1; int r = 0; - pr_debug("clock: locking DPLL %s\n", clk->name); + pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk)); dd = clk->dpll_data; state <<= __ffs(dd->idlest_mask); @@ -187,7 +189,7 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk) return -EINVAL; pr_debug("clock: configuring DPLL %s for low-power bypass\n", - clk->name); + __clk_get_name(clk)); ai = omap3_dpll_autoidle_read(clk); @@ -217,7 +219,7 @@ static int _omap3_noncore_dpll_stop(struct clk *clk) if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP))) return -EINVAL; - pr_debug("clock: stopping DPLL %s\n", clk->name); + pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk)); ai = omap3_dpll_autoidle_read(clk); @@ -245,7 +247,7 @@ static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n) { unsigned long fint, clkinp; /* watch out for overflow */ - clkinp = clk->parent->rate; + clkinp = __clk_get_rate(__clk_get_parent(clk)); fint = (clkinp / n) * m; if (fint < 1000000000) @@ -271,7 +273,7 @@ static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n) unsigned long clkinp, sd; /* watch out for overflow */ int mod1, mod2; - clkinp = clk->parent->rate; + clkinp = __clk_get_rate(__clk_get_parent(clk)); /* * target sigma-delta to near 250MHz @@ -380,16 +382,19 @@ int omap3_noncore_dpll_enable(struct clk *clk) { int r; struct dpll_data *dd; + struct clk *parent; dd = clk->dpll_data; if (!dd) return -EINVAL; - if (clk->rate == dd->clk_bypass->rate) { - WARN_ON(clk->parent != dd->clk_bypass); + parent = __clk_get_parent(clk); + + if (__clk_get_rate(clk) == __clk_get_rate(dd->clk_bypass)) { + WARN_ON(parent != dd->clk_bypass); r = _omap3_noncore_dpll_bypass(clk); } else { - WARN_ON(clk->parent != dd->clk_ref); + WARN_ON(parent != dd->clk_ref); r = _omap3_noncore_dpll_lock(clk); } /* @@ -432,7 +437,7 @@ void omap3_noncore_dpll_disable(struct clk *clk) int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) { struct clk *new_parent = NULL; - unsigned long hw_rate; + unsigned long hw_rate, bypass_rate; u16 freqsel = 0; struct dpll_data *dd; int ret; @@ -456,7 +461,8 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) omap2_clk_enable(dd->clk_bypass); omap2_clk_enable(dd->clk_ref); - if (dd->clk_bypass->rate == rate && + bypass_rate = __clk_get_rate(dd->clk_bypass); + if (bypass_rate == rate && (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) { pr_debug("clock: %s: set rate: entering bypass.\n", clk->name); @@ -479,7 +485,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) } pr_debug("clock: %s: set rate: locking rate to %lu.\n", - clk->name, rate); + __clk_get_name(clk), rate); ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m, dd->last_rounded_n, freqsel); @@ -557,7 +563,7 @@ void omap3_dpll_allow_idle(struct clk *clk) if (!dd->autoidle_reg) { pr_debug("clock: DPLL %s: autoidle not supported\n", - clk->name); + __clk_get_name(clk)); return; } @@ -591,7 +597,7 @@ void omap3_dpll_deny_idle(struct clk *clk) if (!dd->autoidle_reg) { pr_debug("clock: DPLL %s: autoidle not supported\n", - clk->name); + __clk_get_name(clk)); return; } @@ -617,11 +623,12 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk) unsigned long rate; u32 v; struct clk *pclk; + unsigned long parent_rate; /* Walk up the parents of clk, looking for a DPLL */ - pclk = clk->parent; + pclk = __clk_get_parent(clk); while (pclk && !pclk->dpll_data) - pclk = pclk->parent; + pclk = __clk_get_parent(pclk); /* clk does not have a DPLL as a parent? error in the clock data */ if (!pclk) { @@ -633,12 +640,13 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk) WARN_ON(!dd->enable_mask); + parent_rate = __clk_get_rate(__clk_get_parent(clk)); v = __raw_readl(dd->control_reg) & dd->enable_mask; v >>= __ffs(dd->enable_mask); if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE)) - rate = clk->parent->rate; + rate = parent_rate; else - rate = clk->parent->rate * 2; + rate = parent_rate * 2; return rate; } diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 72428bd45efc..92b5718fa722 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -24,6 +24,7 @@ #include <linux/io.h> #include <linux/module.h> #include <linux/interrupt.h> +#include <linux/platform_device.h> #include <asm/mach-types.h> #include <plat/gpmc.h> @@ -31,10 +32,13 @@ #include <plat/cpu.h> #include <plat/gpmc.h> #include <plat/sdrc.h> +#include <plat/omap_device.h> #include "soc.h" #include "common.h" +#define DEVICE_NAME "omap-gpmc" + /* GPMC register offsets */ #define GPMC_REVISION 0x00 #define GPMC_SYSCONFIG 0x10 @@ -83,6 +87,12 @@ #define ENABLE_PREFETCH (0x1 << 7) #define DMA_MPU_MODE 2 +#define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf) +#define GPMC_REVISION_MINOR(l) (l & 0xf) + +#define GPMC_HAS_WR_ACCESS 0x1 +#define GPMC_HAS_WR_DATA_MUX_BUS 0x2 + /* XXX: Only NAND irq has been considered,currently these are the only ones used */ #define GPMC_NR_IRQ 2 @@ -128,7 +138,10 @@ static struct resource gpmc_cs_mem[GPMC_CS_NUM]; static DEFINE_SPINLOCK(gpmc_mem_lock); static unsigned int gpmc_cs_map; /* flag for cs which are initialized */ static int gpmc_ecc_used = -EINVAL; /* cs using ecc engine */ - +static struct device *gpmc_dev; +static int gpmc_irq; +static resource_size_t phys_base, mem_size; +static unsigned gpmc_capability; static void __iomem *gpmc_base; static struct clk *gpmc_l3_clk; @@ -318,10 +331,10 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t) GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access); - if (cpu_is_omap34xx()) { + if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus); + if (gpmc_capability & GPMC_HAS_WR_ACCESS) GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access); - } /* caller is expected to have initialized CONFIG1 to cover * at least sync vs async @@ -431,6 +444,20 @@ static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size) return r; } +static int gpmc_cs_delete_mem(int cs) +{ + struct resource *res = &gpmc_cs_mem[cs]; + int r; + + spin_lock(&gpmc_mem_lock); + r = release_resource(&gpmc_cs_mem[cs]); + res->start = 0; + res->end = 0; + spin_unlock(&gpmc_mem_lock); + + return r; +} + int gpmc_cs_request(int cs, unsigned long size, unsigned long *base) { struct resource *res = &gpmc_cs_mem[cs]; @@ -767,7 +794,7 @@ static void gpmc_irq_noop(struct irq_data *data) { } static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; } -static int gpmc_setup_irq(int gpmc_irq) +static int gpmc_setup_irq(void) { int i; u32 regval; @@ -811,9 +838,39 @@ static int gpmc_setup_irq(int gpmc_irq) return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL); } -static void __init gpmc_mem_init(void) +static __devexit int gpmc_free_irq(void) +{ + int i; + + if (gpmc_irq) + free_irq(gpmc_irq, NULL); + + for (i = 0; i < GPMC_NR_IRQ; i++) { + irq_set_handler(gpmc_client_irq[i].irq, NULL); + irq_set_chip(gpmc_client_irq[i].irq, &no_irq_chip); + irq_modify_status(gpmc_client_irq[i].irq, 0, 0); + } + + irq_free_descs(gpmc_irq_start, GPMC_NR_IRQ); + + return 0; +} + +static void __devexit gpmc_mem_exit(void) { int cs; + + for (cs = 0; cs < GPMC_CS_NUM; cs++) { + if (!gpmc_cs_mem_enabled(cs)) + continue; + gpmc_cs_delete_mem(cs); + } + +} + +static int __devinit gpmc_mem_init(void) +{ + int cs, rc; unsigned long boot_rom_space = 0; /* never allocate the first page, to facilitate bug detection; @@ -833,70 +890,123 @@ static void __init gpmc_mem_init(void) if (!gpmc_cs_mem_enabled(cs)) continue; gpmc_cs_get_memconf(cs, &base, &size); - if (gpmc_cs_insert_mem(cs, base, size) < 0) - BUG(); + rc = gpmc_cs_insert_mem(cs, base, size); + if (IS_ERR_VALUE(rc)) { + while (--cs >= 0) + if (gpmc_cs_mem_enabled(cs)) + gpmc_cs_delete_mem(cs); + return rc; + } } + + return 0; } -static int __init gpmc_init(void) +static __devinit int gpmc_probe(struct platform_device *pdev) { + int rc; u32 l; - int ret = -EINVAL; - int gpmc_irq; - char *ck = NULL; - - if (cpu_is_omap24xx()) { - ck = "core_l3_ck"; - if (cpu_is_omap2420()) - l = OMAP2420_GPMC_BASE; - else - l = OMAP34XX_GPMC_BASE; - gpmc_irq = 20 + OMAP_INTC_START; - } else if (cpu_is_omap34xx()) { - ck = "gpmc_fck"; - l = OMAP34XX_GPMC_BASE; - gpmc_irq = 20 + OMAP_INTC_START; - } else if (cpu_is_omap44xx() || soc_is_omap54xx()) { - /* Base address and irq number are same for OMAP4/5 */ - ck = "gpmc_ck"; - l = OMAP44XX_GPMC_BASE; - gpmc_irq = 20 + OMAP44XX_IRQ_GIC_START; + struct resource *res; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) + return -ENOENT; + + phys_base = res->start; + mem_size = resource_size(res); + + gpmc_base = devm_request_and_ioremap(&pdev->dev, res); + if (!gpmc_base) { + dev_err(&pdev->dev, "error: request memory / ioremap\n"); + return -EADDRNOTAVAIL; } - if (WARN_ON(!ck)) - return ret; + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (res == NULL) + dev_warn(&pdev->dev, "Failed to get resource: irq\n"); + else + gpmc_irq = res->start; - gpmc_l3_clk = clk_get(NULL, ck); + gpmc_l3_clk = clk_get(&pdev->dev, "fck"); if (IS_ERR(gpmc_l3_clk)) { - printk(KERN_ERR "Could not get GPMC clock %s\n", ck); - BUG(); + dev_err(&pdev->dev, "error: clk_get\n"); + gpmc_irq = 0; + return PTR_ERR(gpmc_l3_clk); } - gpmc_base = ioremap(l, SZ_4K); - if (!gpmc_base) { + clk_prepare_enable(gpmc_l3_clk); + + gpmc_dev = &pdev->dev; + + l = gpmc_read_reg(GPMC_REVISION); + if (GPMC_REVISION_MAJOR(l) > 0x4) + gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS; + dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l), + GPMC_REVISION_MINOR(l)); + + rc = gpmc_mem_init(); + if (IS_ERR_VALUE(rc)) { + clk_disable_unprepare(gpmc_l3_clk); clk_put(gpmc_l3_clk); - printk(KERN_ERR "Could not get GPMC register memory\n"); - BUG(); + dev_err(gpmc_dev, "failed to reserve memory\n"); + return rc; } - clk_enable(gpmc_l3_clk); + if (IS_ERR_VALUE(gpmc_setup_irq())) + dev_warn(gpmc_dev, "gpmc_setup_irq failed\n"); - l = gpmc_read_reg(GPMC_REVISION); - printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); - /* Set smart idle mode and automatic L3 clock gating */ - l = gpmc_read_reg(GPMC_SYSCONFIG); - l &= 0x03 << 3; - l |= (0x02 << 3) | (1 << 0); - gpmc_write_reg(GPMC_SYSCONFIG, l); - gpmc_mem_init(); - - ret = gpmc_setup_irq(gpmc_irq); - if (ret) - pr_err("gpmc: irq-%d could not claim: err %d\n", - gpmc_irq, ret); - return ret; + return 0; +} + +static __devexit int gpmc_remove(struct platform_device *pdev) +{ + gpmc_free_irq(); + gpmc_mem_exit(); + gpmc_dev = NULL; + return 0; } + +static struct platform_driver gpmc_driver = { + .probe = gpmc_probe, + .remove = __devexit_p(gpmc_remove), + .driver = { + .name = DEVICE_NAME, + .owner = THIS_MODULE, + }, +}; + +static __init int gpmc_init(void) +{ + return platform_driver_register(&gpmc_driver); +} + +static __exit void gpmc_exit(void) +{ + platform_driver_unregister(&gpmc_driver); + +} + postcore_initcall(gpmc_init); +module_exit(gpmc_exit); + +static int __init omap_gpmc_init(void) +{ + struct omap_hwmod *oh; + struct platform_device *pdev; + char *oh_name = "gpmc"; + + oh = omap_hwmod_lookup(oh_name); + if (!oh) { + pr_err("Could not look up %s\n", oh_name); + return -ENODEV; + } + + pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0, NULL, 0, 0); + WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name); + + return IS_ERR(pdev) ? PTR_ERR(pdev) : 0; +} +postcore_initcall(omap_gpmc_init); static irqreturn_t gpmc_handle_irq(int irq, void *dev) { diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c index 03ebf47cfa9a..4d3a6324155f 100644 --- a/arch/arm/mach-omap2/hsmmc.c +++ b/arch/arm/mach-omap2/hsmmc.c @@ -523,7 +523,7 @@ static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo, dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id); od = omap_device_alloc(pdev, ohs, 1, NULL, 0); - if (!od) { + if (IS_ERR(od)) { pr_err("Could not allocate od for %s\n", name); goto put_pdev; } diff --git a/arch/arm/mach-omap2/include/mach/board-zoom.h b/arch/arm/mach-omap2/include/mach/board-zoom.h index 775fdc3b000b..2e9486940ead 100644 --- a/arch/arm/mach-omap2/include/mach/board-zoom.h +++ b/arch/arm/mach-omap2/include/mach/board-zoom.h @@ -8,5 +8,3 @@ extern int __init zoom_debugboard_init(void); extern void __init zoom_peripherals_init(void); extern void __init zoom_display_init(void); - -#define ZOOM2_HEADSET_EXTMUTE_GPIO 153 diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index 7d47407d6d46..37f8f948047b 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -15,6 +15,7 @@ #include <linux/clk.h> #include <linux/err.h> #include <linux/io.h> +#include <linux/of.h> #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/platform_data/asoc-ti-mcbsp.h> @@ -23,8 +24,6 @@ #include <plat/omap_device.h> #include <linux/pm_runtime.h> -#include "control.h" - /* * FIXME: Find a mechanism to enable/disable runtime the McBSP ICLK autoidle. * Sidetone needs non-gated ICLK and sidetone autoidle is broken. @@ -32,112 +31,6 @@ #include "cm2xxx_3xxx.h" #include "cm-regbits-34xx.h" -/* McBSP1 internal signal muxing function for OMAP2/3 */ -static int omap2_mcbsp1_mux_rx_clk(struct device *dev, const char *signal, - const char *src) -{ - u32 v; - - v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); - - if (!strcmp(signal, "clkr")) { - if (!strcmp(src, "clkr")) - v &= ~OMAP2_MCBSP1_CLKR_MASK; - else if (!strcmp(src, "clkx")) - v |= OMAP2_MCBSP1_CLKR_MASK; - else - return -EINVAL; - } else if (!strcmp(signal, "fsr")) { - if (!strcmp(src, "fsr")) - v &= ~OMAP2_MCBSP1_FSR_MASK; - else if (!strcmp(src, "fsx")) - v |= OMAP2_MCBSP1_FSR_MASK; - else - return -EINVAL; - } else { - return -EINVAL; - } - - omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); - - return 0; -} - -/* McBSP4 internal signal muxing function for OMAP4 */ -#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX (1 << 31) -#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX (1 << 30) -static int omap4_mcbsp4_mux_rx_clk(struct device *dev, const char *signal, - const char *src) -{ - u32 v; - - /* - * In CONTROL_MCBSPLP register only bit 30 (CLKR mux), and bit 31 (FSR - * mux) is used */ - v = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP); - - if (!strcmp(signal, "clkr")) { - if (!strcmp(src, "clkr")) - v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX; - else if (!strcmp(src, "clkx")) - v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX; - else - return -EINVAL; - } else if (!strcmp(signal, "fsr")) { - if (!strcmp(src, "fsr")) - v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX; - else if (!strcmp(src, "fsx")) - v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX; - else - return -EINVAL; - } else { - return -EINVAL; - } - - omap4_ctrl_pad_writel(v, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP); - - return 0; -} - -/* McBSP CLKS source switching function */ -static int omap2_mcbsp_set_clk_src(struct device *dev, struct clk *clk, - const char *src) -{ - struct clk *fck_src; - char *fck_src_name; - int r; - - if (!strcmp(src, "clks_ext")) - fck_src_name = "pad_fck"; - else if (!strcmp(src, "clks_fclk")) - fck_src_name = "prcm_fck"; - else - return -EINVAL; - - fck_src = clk_get(dev, fck_src_name); - if (IS_ERR_OR_NULL(fck_src)) { - pr_err("omap-mcbsp: %s: could not clk_get() %s\n", "clks", - fck_src_name); - return -EINVAL; - } - - pm_runtime_put_sync(dev); - - r = clk_set_parent(clk, fck_src); - if (IS_ERR_VALUE(r)) { - pr_err("omap-mcbsp: %s: could not clk_set_parent() to %s\n", - "clks", fck_src_name); - clk_put(fck_src); - return -EINVAL; - } - - pm_runtime_get_sync(dev); - - clk_put(fck_src); - - return 0; -} - static int omap3_enable_st_clock(unsigned int id, bool enable) { unsigned int w; @@ -179,17 +72,11 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused) pdata->reg_size = 4; pdata->has_ccr = true; } - pdata->set_clk_src = omap2_mcbsp_set_clk_src; - - /* On OMAP2/3 the McBSP1 port has 6 pin configuration */ - if (id == 1 && oh->class->rev < MCBSP_CONFIG_TYPE4) - pdata->mux_signal = omap2_mcbsp1_mux_rx_clk; - /* On OMAP4 the McBSP4 port has 6 pin configuration */ - if (id == 4 && oh->class->rev == MCBSP_CONFIG_TYPE4) - pdata->mux_signal = omap4_mcbsp4_mux_rx_clk; - - if (oh->class->rev == MCBSP_CONFIG_TYPE3) { + if (oh->class->rev == MCBSP_CONFIG_TYPE2) { + /* The FIFO has 128 locations */ + pdata->buffer_size = 0x80; + } else if (oh->class->rev == MCBSP_CONFIG_TYPE3) { if (id == 2) /* The FIFO has 1024 + 256 locations */ pdata->buffer_size = 0x500; @@ -225,7 +112,8 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused) static int __init omap2_mcbsp_init(void) { - omap_hwmod_for_each_by_class("mcbsp", omap_init_mcbsp, NULL); + if (!of_have_populated_dt()) + omap_hwmod_for_each_by_class("mcbsp", omap_init_mcbsp, NULL); return 0; } diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index 9fe6829f4c16..701e17cba468 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c @@ -486,7 +486,7 @@ void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state) default: /* Nothing to be done */ break; - }; + } if (val >= 0) { omap_mux_write(pad->partition, val, diff --git a/arch/arm/mach-omap2/mux34xx.c b/arch/arm/mach-omap2/mux34xx.c index 17f80e4ab162..c47140bbbec4 100644 --- a/arch/arm/mach-omap2/mux34xx.c +++ b/arch/arm/mach-omap2/mux34xx.c @@ -614,16 +614,16 @@ static struct omap_mux __initdata omap3_muxmodes[] = { "sys_off_mode", NULL, NULL, NULL, "gpio_9", NULL, NULL, "safe_mode"), _OMAP3_MUXENTRY(UART1_CTS, 150, - "uart1_cts", NULL, NULL, NULL, + "uart1_cts", "ssi1_rdy_tx", NULL, NULL, "gpio_150", "hsusb3_tll_clk", NULL, "safe_mode"), _OMAP3_MUXENTRY(UART1_RTS, 149, - "uart1_rts", NULL, NULL, NULL, + "uart1_rts", "ssi1_flag_tx", NULL, NULL, "gpio_149", NULL, NULL, "safe_mode"), _OMAP3_MUXENTRY(UART1_RX, 151, - "uart1_rx", NULL, "mcbsp1_clkr", "mcspi4_clk", + "uart1_rx", "ss1_wake_tx", "mcbsp1_clkr", "mcspi4_clk", "gpio_151", NULL, NULL, "safe_mode"), _OMAP3_MUXENTRY(UART1_TX, 148, - "uart1_tx", NULL, NULL, NULL, + "uart1_tx", "ssi1_dat_tx", NULL, NULL, "gpio_148", NULL, NULL, "safe_mode"), _OMAP3_MUXENTRY(UART2_CTS, 144, "uart2_cts", "mcbsp3_dx", "gpt9_pwm_evt", NULL, diff --git a/arch/arm/mach-omap2/omap-secure.c b/arch/arm/mach-omap2/omap-secure.c index a004cb9acf52..e089e4d1ae38 100644 --- a/arch/arm/mach-omap2/omap-secure.c +++ b/arch/arm/mach-omap2/omap-secure.c @@ -61,8 +61,8 @@ int __init omap_secure_ram_reserve_memblock(void) { u32 size = OMAP_SECURE_RAM_STORAGE; - size = ALIGN(size, SZ_1M); - omap_secure_memblock_base = arm_memblock_steal(size, SZ_1M); + size = ALIGN(size, SECTION_SIZE); + omap_secure_memblock_base = arm_memblock_steal(size, SECTION_SIZE); return 0; } diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 00c006686b0d..b969ab1d258b 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -679,16 +679,25 @@ static int _init_main_clk(struct omap_hwmod *oh) if (!oh->main_clk) return 0; - oh->_clk = omap_clk_get_by_name(oh->main_clk); - if (!oh->_clk) { + oh->_clk = clk_get(NULL, oh->main_clk); + if (IS_ERR(oh->_clk)) { pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n", oh->name, oh->main_clk); return -EINVAL; } + /* + * HACK: This needs a re-visit once clk_prepare() is implemented + * to do something meaningful. Today its just a no-op. + * If clk_prepare() is used at some point to do things like + * voltage scaling etc, then this would have to be moved to + * some point where subsystems like i2c and pmic become + * available. + */ + clk_prepare(oh->_clk); if (!oh->_clk->clkdm) - pr_warning("omap_hwmod: %s: missing clockdomain for %s.\n", - oh->main_clk, oh->_clk->name); + pr_debug("omap_hwmod: %s: missing clockdomain for %s.\n", + oh->name, oh->main_clk); return ret; } @@ -715,13 +724,22 @@ static int _init_interface_clks(struct omap_hwmod *oh) if (!os->clk) continue; - c = omap_clk_get_by_name(os->clk); - if (!c) { + c = clk_get(NULL, os->clk); + if (IS_ERR(c)) { pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n", oh->name, os->clk); ret = -EINVAL; } os->_clk = c; + /* + * HACK: This needs a re-visit once clk_prepare() is implemented + * to do something meaningful. Today its just a no-op. + * If clk_prepare() is used at some point to do things like + * voltage scaling etc, then this would have to be moved to + * some point where subsystems like i2c and pmic become + * available. + */ + clk_prepare(os->_clk); } return ret; @@ -742,13 +760,22 @@ static int _init_opt_clks(struct omap_hwmod *oh) int ret = 0; for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) { - c = omap_clk_get_by_name(oc->clk); - if (!c) { + c = clk_get(NULL, oc->clk); + if (IS_ERR(c)) { pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n", oh->name, oc->clk); ret = -EINVAL; } oc->_clk = c; + /* + * HACK: This needs a re-visit once clk_prepare() is implemented + * to do something meaningful. Today its just a no-op. + * If clk_prepare() is used at some point to do things like + * voltage scaling etc, then this would have to be moved to + * some point where subsystems like i2c and pmic become + * available. + */ + clk_prepare(oc->_clk); } return ret; @@ -827,7 +854,7 @@ static void _enable_optional_clocks(struct omap_hwmod *oh) for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) if (oc->_clk) { pr_debug("omap_hwmod: enable %s:%s\n", oc->role, - oc->_clk->name); + __clk_get_name(oc->_clk)); clk_enable(oc->_clk); } } @@ -842,7 +869,7 @@ static void _disable_optional_clocks(struct omap_hwmod *oh) for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) if (oc->_clk) { pr_debug("omap_hwmod: disable %s:%s\n", oc->role, - oc->_clk->name); + __clk_get_name(oc->_clk)); clk_disable(oc->_clk); } } @@ -900,10 +927,10 @@ static void _am33xx_enable_module(struct omap_hwmod *oh) */ static int _omap4_wait_target_disable(struct omap_hwmod *oh) { - if (!oh || !oh->clkdm) + if (!oh) return -EINVAL; - if (oh->_int_flags & _HWMOD_NO_MPU_PORT) + if (oh->_int_flags & _HWMOD_NO_MPU_PORT || !oh->clkdm) return 0; if (oh->flags & HWMOD_NO_IDLEST) @@ -1427,8 +1454,10 @@ static struct omap_hwmod *_lookup(const char *name) */ static int _init_clkdm(struct omap_hwmod *oh) { - if (!oh->clkdm_name) + if (!oh->clkdm_name) { + pr_debug("omap_hwmod: %s: missing clockdomain\n", oh->name); return 0; + } oh->clkdm = clkdm_lookup(oh->clkdm_name); if (!oh->clkdm) { @@ -1556,6 +1585,7 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name) { struct omap_hwmod_rst_info ohri; int ret = -EINVAL; + int hwsup = 0; if (!oh) return -EINVAL; @@ -1567,10 +1597,46 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name) if (IS_ERR_VALUE(ret)) return ret; + if (oh->clkdm) { + /* + * A clockdomain must be in SW_SUP otherwise reset + * might not be completed. The clockdomain can be set + * in HW_AUTO only when the module become ready. + */ + hwsup = clkdm_in_hwsup(oh->clkdm); + ret = clkdm_hwmod_enable(oh->clkdm, oh); + if (ret) { + WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n", + oh->name, oh->clkdm->name, ret); + return ret; + } + } + + _enable_clocks(oh); + if (soc_ops.enable_module) + soc_ops.enable_module(oh); + ret = soc_ops.deassert_hardreset(oh, &ohri); + + if (soc_ops.disable_module) + soc_ops.disable_module(oh); + _disable_clocks(oh); + if (ret == -EBUSY) pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name); + if (!ret) { + /* + * Set the clockdomain to HW_AUTO, assuming that the + * previous state was HW_AUTO. + */ + if (oh->clkdm && hwsup) + clkdm_allow_idle(oh->clkdm); + } else { + if (oh->clkdm) + clkdm_hwmod_disable(oh->clkdm, oh); + } + return ret; } @@ -1605,30 +1671,56 @@ static int _read_hardreset(struct omap_hwmod *oh, const char *name) } /** - * _are_any_hardreset_lines_asserted - return true if part of @oh is hard-reset + * _are_all_hardreset_lines_asserted - return true if the @oh is hard-reset * @oh: struct omap_hwmod * * - * If any hardreset line associated with @oh is asserted, then return true. - * Otherwise, if @oh has no hardreset lines associated with it, or if - * no hardreset lines associated with @oh are asserted, then return false. + * If all hardreset lines associated with @oh are asserted, then return true. + * Otherwise, if part of @oh is out hardreset or if no hardreset lines + * associated with @oh are asserted, then return false. * This function is used to avoid executing some parts of the IP block - * enable/disable sequence if a hardreset line is set. + * enable/disable sequence if its hardreset line is set. */ -static bool _are_any_hardreset_lines_asserted(struct omap_hwmod *oh) +static bool _are_all_hardreset_lines_asserted(struct omap_hwmod *oh) { - int i; + int i, rst_cnt = 0; if (oh->rst_lines_cnt == 0) return false; for (i = 0; i < oh->rst_lines_cnt; i++) if (_read_hardreset(oh, oh->rst_lines[i].name) > 0) - return true; + rst_cnt++; + + if (oh->rst_lines_cnt == rst_cnt) + return true; return false; } /** + * _are_any_hardreset_lines_asserted - return true if any part of @oh is + * hard-reset + * @oh: struct omap_hwmod * + * + * If any hardreset lines associated with @oh are asserted, then + * return true. Otherwise, if no hardreset lines associated with @oh + * are asserted, or if @oh has no hardreset lines, then return false. + * This function is used to avoid executing some parts of the IP block + * enable/disable sequence if any hardreset line is set. + */ +static bool _are_any_hardreset_lines_asserted(struct omap_hwmod *oh) +{ + int rst_cnt = 0; + int i; + + for (i = 0; i < oh->rst_lines_cnt && rst_cnt == 0; i++) + if (_read_hardreset(oh, oh->rst_lines[i].name) > 0) + rst_cnt++; + + return (rst_cnt) ? true : false; +} + +/** * _omap4_disable_module - enable CLKCTRL modulemode on OMAP4 * @oh: struct omap_hwmod * * @@ -1642,6 +1734,13 @@ static int _omap4_disable_module(struct omap_hwmod *oh) if (!oh->clkdm || !oh->prcm.omap4.modulemode) return -EINVAL; + /* + * Since integration code might still be doing something, only + * disable if all lines are under hardreset. + */ + if (_are_any_hardreset_lines_asserted(oh)) + return 0; + pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__); omap4_cminst_module_disable(oh->clkdm->prcm_partition, @@ -1649,9 +1748,6 @@ static int _omap4_disable_module(struct omap_hwmod *oh) oh->clkdm->clkdm_offs, oh->prcm.omap4.clkctrl_offs); - if (_are_any_hardreset_lines_asserted(oh)) - return 0; - v = _omap4_wait_target_disable(oh); if (v) pr_warn("omap_hwmod: %s: _wait_target_disable failed\n", @@ -1676,12 +1772,12 @@ static int _am33xx_disable_module(struct omap_hwmod *oh) pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__); - am33xx_cm_module_disable(oh->clkdm->cm_inst, oh->clkdm->clkdm_offs, - oh->prcm.omap4.clkctrl_offs); - if (_are_any_hardreset_lines_asserted(oh)) return 0; + am33xx_cm_module_disable(oh->clkdm->cm_inst, oh->clkdm->clkdm_offs, + oh->prcm.omap4.clkctrl_offs); + v = _am33xx_wait_target_disable(oh); if (v) pr_warn("omap_hwmod: %s: _wait_target_disable failed\n", @@ -1907,7 +2003,7 @@ static int _enable(struct omap_hwmod *oh) } /* - * If an IP block contains HW reset lines and any of them are + * If an IP block contains HW reset lines and all of them are * asserted, we let integration code associated with that * block handle the enable. We've received very little * information on what those driver authors need, and until @@ -1915,7 +2011,7 @@ static int _enable(struct omap_hwmod *oh) * posted to the public lists, this is probably the best we * can do. */ - if (_are_any_hardreset_lines_asserted(oh)) + if (_are_all_hardreset_lines_asserted(oh)) return 0; /* Mux pins for device runtime if populated */ @@ -1934,7 +2030,8 @@ static int _enable(struct omap_hwmod *oh) * completely the module. The clockdomain can be set * in HW_AUTO only when the module become ready. */ - hwsup = clkdm_in_hwsup(oh->clkdm); + hwsup = clkdm_in_hwsup(oh->clkdm) && + !clkdm_missing_idle_reporting(oh->clkdm); r = clkdm_hwmod_enable(oh->clkdm, oh); if (r) { WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n", @@ -1996,7 +2093,7 @@ static int _idle(struct omap_hwmod *oh) return -EINVAL; } - if (_are_any_hardreset_lines_asserted(oh)) + if (_are_all_hardreset_lines_asserted(oh)) return 0; if (oh->class->sysc) @@ -2084,7 +2181,7 @@ static int _shutdown(struct omap_hwmod *oh) return -EINVAL; } - if (_are_any_hardreset_lines_asserted(oh)) + if (_are_all_hardreset_lines_asserted(oh)) return 0; pr_debug("omap_hwmod: %s: disabling\n", oh->name); @@ -2608,10 +2705,10 @@ static int _omap2_wait_target_ready(struct omap_hwmod *oh) */ static int _omap4_wait_target_ready(struct omap_hwmod *oh) { - if (!oh || !oh->clkdm) + if (!oh) return -EINVAL; - if (oh->flags & HWMOD_NO_IDLEST) + if (oh->flags & HWMOD_NO_IDLEST || !oh->clkdm) return 0; if (!_find_mpu_rt_port(oh)) diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index 10575a1bc1f1..b5db6007c523 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -536,6 +536,15 @@ static struct omap_hwmod_addr_space omap2420_counter_32k_addrs[] = { { } }; +static struct omap_hwmod_addr_space omap2420_gpmc_addrs[] = { + { + .pa_start = 0x6800a000, + .pa_end = 0x6800afff, + .flags = ADDR_TYPE_RT + }, + { } +}; + static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = { .master = &omap2xxx_l4_wkup_hwmod, .slave = &omap2xxx_counter_32k_hwmod, @@ -544,6 +553,14 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +static struct omap_hwmod_ocp_if omap2420_l3__gpmc = { + .master = &omap2xxx_l3_main_hwmod, + .slave = &omap2xxx_gpmc_hwmod, + .clk = "core_l3_ck", + .addr = omap2420_gpmc_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = { &omap2xxx_l3_main__l4_core, &omap2xxx_mpu__l3_main, @@ -585,8 +602,10 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = { &omap2420_l4_core__mcbsp1, &omap2420_l4_core__mcbsp2, &omap2420_l4_core__msdi1, + &omap2xxx_l4_core__rng, &omap2420_l4_core__hdq1w, &omap2420_l4_wkup__counter_32k, + &omap2420_l3__gpmc, NULL, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 60de70feeae5..c455e41b0237 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -888,6 +888,15 @@ static struct omap_hwmod_addr_space omap2430_counter_32k_addrs[] = { { } }; +static struct omap_hwmod_addr_space omap2430_gpmc_addrs[] = { + { + .pa_start = 0x6e000000, + .pa_end = 0x6e000fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = { .master = &omap2xxx_l4_wkup_hwmod, .slave = &omap2xxx_counter_32k_hwmod, @@ -896,6 +905,14 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +static struct omap_hwmod_ocp_if omap2430_l3__gpmc = { + .master = &omap2xxx_l3_main_hwmod, + .slave = &omap2xxx_gpmc_hwmod, + .clk = "core_l3_ck", + .addr = omap2430_gpmc_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = { &omap2xxx_l3_main__l4_core, &omap2xxx_mpu__l3_main, @@ -945,7 +962,9 @@ static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = { &omap2430_l4_core__mcbsp4, &omap2430_l4_core__mcbsp5, &omap2430_l4_core__hdq1w, + &omap2xxx_l4_core__rng, &omap2430_l4_wkup__counter_32k, + &omap2430_l3__gpmc, NULL, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c index f853a0b1d5ca..1a1287d62648 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c @@ -129,6 +129,15 @@ struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[] = { { } }; +static struct omap_hwmod_addr_space omap2_rng_addr_space[] = { + { + .pa_start = 0x480a0000, + .pa_end = 0x480a004f, + .flags = ADDR_TYPE_RT + }, + { } +}; + /* * Common interconnect data */ @@ -372,3 +381,11 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l4_core -> rng */ +struct omap_hwmod_ocp_if omap2xxx_l4_core__rng = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_rng_hwmod, + .clk = "rng_ick", + .addr = omap2_rng_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c index feeb401cf87e..bd9220ed5ab9 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c @@ -173,6 +173,26 @@ struct omap_hwmod_class omap2xxx_mcspi_class = { }; /* + * 'gpmc' class + * general purpose memory controller + */ + +static struct omap_hwmod_class_sysconfig omap2xxx_gpmc_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2xxx_gpmc_hwmod_class = { + .name = "gpmc", + .sysc = &omap2xxx_gpmc_sysc, +}; + +/* * IP blocks */ @@ -198,8 +218,14 @@ struct omap_hwmod omap2xxx_l4_wkup_hwmod = { }; /* MPU */ +static struct omap_hwmod_irq_info omap2xxx_mpu_irqs[] = { + { .name = "pmu", .irq = 3 + OMAP_INTC_START }, + { .irq = -1 } +}; + struct omap_hwmod omap2xxx_mpu_hwmod = { .name = "mpu", + .mpu_irqs = omap2xxx_mpu_irqs, .class = &mpu_hwmod_class, .main_clk = "mpu_ck", }; @@ -220,6 +246,11 @@ static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { .timer_capability = OMAP_TIMER_HAS_PWM, }; +/* timers with DSP interrupt dev attribute */ +static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = { + .timer_capability = OMAP_TIMER_HAS_DSP_IRQ, +}; + /* timer1 */ struct omap_hwmod omap2xxx_timer1_hwmod = { @@ -308,6 +339,7 @@ struct omap_hwmod omap2xxx_timer5_hwmod = { .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, }, }, + .dev_attr = &capability_dsp_dev_attr, .class = &omap2xxx_timer_hwmod_class, }; @@ -326,6 +358,7 @@ struct omap_hwmod omap2xxx_timer6_hwmod = { .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, }, }, + .dev_attr = &capability_dsp_dev_attr, .class = &omap2xxx_timer_hwmod_class, }; @@ -344,6 +377,7 @@ struct omap_hwmod omap2xxx_timer7_hwmod = { .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, }, }, + .dev_attr = &capability_dsp_dev_attr, .class = &omap2xxx_timer_hwmod_class, }; @@ -362,6 +396,7 @@ struct omap_hwmod omap2xxx_timer8_hwmod = { .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, }, }, + .dev_attr = &capability_dsp_dev_attr, .class = &omap2xxx_timer_hwmod_class, }; @@ -724,7 +759,6 @@ struct omap_hwmod omap2xxx_mcspi2_hwmod = { .dev_attr = &omap_mcspi2_dev_attr, }; - static struct omap_hwmod_class omap2xxx_counter_hwmod_class = { .name = "counter", }; @@ -743,3 +777,77 @@ struct omap_hwmod omap2xxx_counter_32k_hwmod = { }, .class = &omap2xxx_counter_hwmod_class, }; + +/* gpmc */ +static struct omap_hwmod_irq_info omap2xxx_gpmc_irqs[] = { + { .irq = 20 }, + { .irq = -1 } +}; + +struct omap_hwmod omap2xxx_gpmc_hwmod = { + .name = "gpmc", + .class = &omap2xxx_gpmc_hwmod_class, + .mpu_irqs = omap2xxx_gpmc_irqs, + .main_clk = "gpmc_fck", + /* + * XXX HWMOD_INIT_NO_RESET should not be needed for this IP + * block. It is not being added due to any known bugs with + * resetting the GPMC IP block, but rather because any timings + * set by the bootloader are not being correctly programmed by + * the kernel from the board file or DT data. + * HWMOD_INIT_NO_RESET should be removed ASAP. + */ + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET | + HWMOD_NO_IDLEST), + .prcm = { + .omap2 = { + .prcm_reg_id = 3, + .module_bit = OMAP24XX_EN_GPMC_MASK, + .module_offs = CORE_MOD, + }, + }, +}; + +/* RNG */ + +static struct omap_hwmod_class_sysconfig omap2_rng_sysc = { + .rev_offs = 0x3c, + .sysc_offs = 0x40, + .syss_offs = 0x44, + .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | + SYSS_HAS_RESET_STATUS), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2_rng_hwmod_class = { + .name = "rng", + .sysc = &omap2_rng_sysc, +}; + +static struct omap_hwmod_irq_info omap2_rng_mpu_irqs[] = { + { .irq = 52 }, + { .irq = -1 } +}; + +struct omap_hwmod omap2xxx_rng_hwmod = { + .name = "rng", + .mpu_irqs = omap2_rng_mpu_irqs, + .main_clk = "l4_ck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 4, + .module_bit = OMAP24XX_EN_RNG_SHIFT, + .idlest_reg_id = 4, + .idlest_idle_bit = OMAP24XX_ST_RNG_SHIFT, + }, + }, + /* + * XXX The first read from the SYSSTATUS register of the RNG + * after the SYSCONFIG SOFTRESET bit is set triggers an + * imprecise external abort. It's unclear why this happens. + * Until this is analyzed, skip the IP block reset. + */ + .flags = HWMOD_INIT_NO_RESET, + .class = &omap2_rng_hwmod_class, +}; diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 94b38af17055..f67b7ee07dd4 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -27,6 +27,7 @@ #include <linux/platform_data/asoc-ti-mcbsp.h> #include <linux/platform_data/spi-omap2-mcspi.h> #include <plat/dmtimer.h> +#include <plat/iommu.h> #include "am35xx.h" @@ -92,8 +93,14 @@ static struct omap_hwmod omap3xxx_l4_sec_hwmod = { }; /* MPU */ +static struct omap_hwmod_irq_info omap3xxx_mpu_irqs[] = { + { .name = "pmu", .irq = 3 + OMAP_INTC_START }, + { .irq = -1 } +}; + static struct omap_hwmod omap3xxx_mpu_hwmod = { .name = "mpu", + .mpu_irqs = omap3xxx_mpu_irqs, .class = &mpu_hwmod_class, .main_clk = "arm_fck", }; @@ -123,6 +130,24 @@ static struct omap_hwmod omap3xxx_iva_hwmod = { }, }; +/* + * 'debugss' class + * debug and emulation sub system + */ + +static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = { + .name = "debugss", +}; + +/* debugss */ +static struct omap_hwmod omap3xxx_debugss_hwmod = { + .name = "debugss", + .class = &omap3xxx_debugss_hwmod_class, + .clkdm_name = "emu_clkdm", + .main_clk = "emu_src_ck", + .flags = HWMOD_NO_IDLEST, +}; + /* timer class */ static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = { .rev_offs = 0x0000, @@ -170,6 +195,16 @@ static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { .timer_capability = OMAP_TIMER_HAS_PWM, }; +/* timers with DSP interrupt dev attribute */ +static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = { + .timer_capability = OMAP_TIMER_HAS_DSP_IRQ, +}; + +/* pwm timers with DSP interrupt dev attribute */ +static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = { + .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM, +}; + /* timer1 */ static struct omap_hwmod omap3xxx_timer1_hwmod = { .name = "timer1", @@ -253,6 +288,7 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = { .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT, }, }, + .dev_attr = &capability_dsp_dev_attr, .class = &omap3xxx_timer_hwmod_class, }; @@ -270,6 +306,7 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = { .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT, }, }, + .dev_attr = &capability_dsp_dev_attr, .class = &omap3xxx_timer_hwmod_class, }; @@ -287,6 +324,7 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = { .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT, }, }, + .dev_attr = &capability_dsp_dev_attr, .class = &omap3xxx_timer_hwmod_class, }; @@ -304,7 +342,7 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = { .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT, }, }, - .dev_attr = &capability_pwm_dev_attr, + .dev_attr = &capability_dsp_pwm_dev_attr, .class = &omap3xxx_timer_hwmod_class, }; @@ -2033,6 +2071,33 @@ static struct omap_hwmod omap3xxx_hdq1w_hwmod = { .class = &omap2_hdq1w_class, }; +/* SAD2D */ +static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = { + { .name = "rst_modem_pwron_sw", .rst_shift = 0 }, + { .name = "rst_modem_sw", .rst_shift = 1 }, +}; + +static struct omap_hwmod_class omap3xxx_sad2d_class = { + .name = "sad2d", +}; + +static struct omap_hwmod omap3xxx_sad2d_hwmod = { + .name = "sad2d", + .rst_lines = omap3xxx_sad2d_resets, + .rst_lines_cnt = ARRAY_SIZE(omap3xxx_sad2d_resets), + .main_clk = "sad2d_ick", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_SAD2D_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT, + }, + }, + .class = &omap3xxx_sad2d_class, +}; + /* * '32K sync counter' class * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock @@ -2068,6 +2133,49 @@ static struct omap_hwmod omap3xxx_counter_32k_hwmod = { }; /* + * 'gpmc' class + * general purpose memory controller + */ + +static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = { + .name = "gpmc", + .sysc = &omap3xxx_gpmc_sysc, +}; + +static struct omap_hwmod_irq_info omap3xxx_gpmc_irqs[] = { + { .irq = 20 }, + { .irq = -1 } +}; + +static struct omap_hwmod omap3xxx_gpmc_hwmod = { + .name = "gpmc", + .class = &omap3xxx_gpmc_hwmod_class, + .clkdm_name = "core_l3_clkdm", + .mpu_irqs = omap3xxx_gpmc_irqs, + .main_clk = "gpmc_fck", + /* + * XXX HWMOD_INIT_NO_RESET should not be needed for this IP + * block. It is not being added due to any known bugs with + * resetting the GPMC IP block, but rather because any timings + * set by the bootloader are not being correctly programmed by + * the kernel from the board file or DT data. + * HWMOD_INIT_NO_RESET should be removed ASAP. + */ + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET | + HWMOD_NO_IDLEST), +}; + +/* * interfaces */ @@ -2102,6 +2210,23 @@ static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { .user = OCP_USER_MPU, }; +static struct omap_hwmod_addr_space omap3xxx_l4_emu_addrs[] = { + { + .pa_start = 0x54000000, + .pa_end = 0x547fffff, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +/* l3 -> debugss */ +static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = { + .master = &omap3xxx_l3_main_hwmod, + .slave = &omap3xxx_debugss_hwmod, + .addr = omap3xxx_l4_emu_addrs, + .user = OCP_USER_MPU, +}; + /* DSS -> l3 */ static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = { .master = &omap3430es1_dss_core_hwmod, @@ -2137,6 +2262,14 @@ static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = { .user = OCP_USER_MPU, }; +/* l3_core -> sad2d interface */ +static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = { + .master = &omap3xxx_sad2d_hwmod, + .slave = &omap3xxx_l3_main_hwmod, + .clk = "core_l3_ick", + .user = OCP_USER_MPU, +}; + /* L4_CORE -> L4_WKUP interface */ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { .master = &omap3xxx_l4_core_hwmod, @@ -2823,6 +2956,122 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* + * 'mmu' class + * The memory management unit performs virtual to physical address translation + * for its requestors. + */ + +static struct omap_hwmod_class_sysconfig mmu_sysc = { + .rev_offs = 0x000, + .sysc_offs = 0x010, + .syss_offs = 0x014, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = { + .name = "mmu", + .sysc = &mmu_sysc, +}; + +/* mmu isp */ + +static struct omap_mmu_dev_attr mmu_isp_dev_attr = { + .da_start = 0x0, + .da_end = 0xfffff000, + .nr_tlb_entries = 8, +}; + +static struct omap_hwmod omap3xxx_mmu_isp_hwmod; +static struct omap_hwmod_irq_info omap3xxx_mmu_isp_irqs[] = { + { .irq = 24 }, + { .irq = -1 } +}; + +static struct omap_hwmod_addr_space omap3xxx_mmu_isp_addrs[] = { + { + .pa_start = 0x480bd400, + .pa_end = 0x480bd47f, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +/* l4_core -> mmu isp */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_mmu_isp_hwmod, + .addr = omap3xxx_mmu_isp_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod omap3xxx_mmu_isp_hwmod = { + .name = "mmu_isp", + .class = &omap3xxx_mmu_hwmod_class, + .mpu_irqs = omap3xxx_mmu_isp_irqs, + .main_clk = "cam_ick", + .dev_attr = &mmu_isp_dev_attr, + .flags = HWMOD_NO_IDLEST, +}; + +#ifdef CONFIG_OMAP_IOMMU_IVA2 + +/* mmu iva */ + +static struct omap_mmu_dev_attr mmu_iva_dev_attr = { + .da_start = 0x11000000, + .da_end = 0xfffff000, + .nr_tlb_entries = 32, +}; + +static struct omap_hwmod omap3xxx_mmu_iva_hwmod; +static struct omap_hwmod_irq_info omap3xxx_mmu_iva_irqs[] = { + { .irq = 28 }, + { .irq = -1 } +}; + +static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = { + { .name = "mmu", .rst_shift = 1, .st_shift = 9 }, +}; + +static struct omap_hwmod_addr_space omap3xxx_mmu_iva_addrs[] = { + { + .pa_start = 0x5d000000, + .pa_end = 0x5d00007f, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +/* l3_main -> iva mmu */ +static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = { + .master = &omap3xxx_l3_main_hwmod, + .slave = &omap3xxx_mmu_iva_hwmod, + .addr = omap3xxx_mmu_iva_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod omap3xxx_mmu_iva_hwmod = { + .name = "mmu_iva", + .class = &omap3xxx_mmu_hwmod_class, + .mpu_irqs = omap3xxx_mmu_iva_irqs, + .rst_lines = omap3xxx_mmu_iva_resets, + .rst_lines_cnt = ARRAY_SIZE(omap3xxx_mmu_iva_resets), + .main_clk = "iva2_ck", + .prcm = { + .omap2 = { + .module_offs = OMAP3430_IVA2_MOD, + }, + }, + .dev_attr = &mmu_iva_dev_attr, + .flags = HWMOD_NO_IDLEST, +}; + +#endif + /* l4_per -> gpio4 */ static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = { { @@ -3168,6 +3417,15 @@ static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = { { } }; +static struct omap_hwmod_addr_space omap3xxx_gpmc_addrs[] = { + { + .pa_start = 0x6e000000, + .pa_end = 0x6e000fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = { .master = &omap3xxx_l4_wkup_hwmod, .slave = &omap3xxx_counter_32k_hwmod, @@ -3277,10 +3535,19 @@ static struct omap_hwmod_ocp_if am35xx_l4_core__emac = { .user = OCP_USER_MPU, }; +static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = { + .master = &omap3xxx_l3_main_hwmod, + .slave = &omap3xxx_gpmc_hwmod, + .clk = "core_l3_ick", + .addr = omap3xxx_gpmc_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { &omap3xxx_l3_main__l4_core, &omap3xxx_l3_main__l4_per, &omap3xxx_mpu__l3_main, + &omap3xxx_l3_main__l4_debugss, &omap3xxx_l4_core__l4_wkup, &omap3xxx_l4_core__mmc3, &omap3_l4_core__uart1, @@ -3322,6 +3589,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { &omap34xx_l4_core__mcspi3, &omap34xx_l4_core__mcspi4, &omap3xxx_l4_wkup__counter_32k, + &omap3xxx_l3_main__gpmc, NULL, }; @@ -3371,6 +3639,11 @@ static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = { &omap34xx_l4_core__sr2, &omap3xxx_l4_core__mailbox, &omap3xxx_l4_core__hdq1w, + &omap3xxx_sad2d__l3, + &omap3xxx_l4_core__mmu_isp, +#ifdef CONFIG_OMAP_IOMMU_IVA2 + &omap3xxx_l3_main__mmu_iva, +#endif NULL }; @@ -3391,6 +3664,11 @@ static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = { &omap3xxx_l4_core__es3plus_mmc1, &omap3xxx_l4_core__es3plus_mmc2, &omap3xxx_l4_core__hdq1w, + &omap3xxx_sad2d__l3, + &omap3xxx_l4_core__mmu_isp, +#ifdef CONFIG_OMAP_IOMMU_IVA2 + &omap3xxx_l3_main__mmu_iva, +#endif NULL }; @@ -3405,6 +3683,7 @@ static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = { &omap3xxx_l4_core__usb_tll_hs, &omap3xxx_l4_core__es3plus_mmc1, &omap3xxx_l4_core__es3plus_mmc2, + &omap3xxx_l4_core__hdq1w, &am35xx_mdio__l3, &am35xx_l4_core__mdio, &am35xx_emac__l3, @@ -3459,7 +3738,7 @@ int __init omap3xxx_hwmod_init(void) } else { WARN(1, "OMAP3 hwmod family init: unknown chip type\n"); return -EINVAL; - }; + } r = omap_hwmod_register_links(h); if (r < 0) @@ -3476,7 +3755,7 @@ int __init omap3xxx_hwmod_init(void) rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) { h = omap3430es2plus_hwmod_ocp_ifs; - }; + } if (h) { r = omap_hwmod_register_links(h); @@ -3491,7 +3770,7 @@ int __init omap3xxx_hwmod_init(void) } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) { h = omap3430_es3plus_hwmod_ocp_ifs; - }; + } if (h) r = omap_hwmod_register_links(h); diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index c7dcb606cd0c..652d0285bd6d 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -30,6 +30,7 @@ #include <plat/mmc.h> #include <plat/dmtimer.h> #include <plat/common.h> +#include <plat/iommu.h> #include "omap_hwmod_common_data.h" #include "cm1_44xx.h" @@ -202,6 +203,9 @@ static struct omap_hwmod omap44xx_l4_abe_hwmod = { .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET, + .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK, + .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, }, }, }; @@ -258,6 +262,11 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = { .name = "mpu_private", .class = &omap44xx_mpu_bus_hwmod_class, .clkdm_name = "mpuss_clkdm", + .prcm = { + .omap4 = { + .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, + }, + }, }; /* @@ -342,6 +351,7 @@ static struct omap_hwmod omap44xx_aess_hwmod = { .omap4 = { .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET, + .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK, .modulemode = MODULEMODE_SWCTRL, }, }, @@ -446,6 +456,11 @@ static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = { .class = &omap44xx_ctrl_module_hwmod_class, .clkdm_name = "l4_cfg_clkdm", .mpu_irqs = omap44xx_ctrl_module_core_irqs, + .prcm = { + .omap4 = { + .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, + }, + }, }; /* ctrl_module_pad_core */ @@ -453,6 +468,11 @@ static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = { .name = "ctrl_module_pad_core", .class = &omap44xx_ctrl_module_hwmod_class, .clkdm_name = "l4_cfg_clkdm", + .prcm = { + .omap4 = { + .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, + }, + }, }; /* ctrl_module_wkup */ @@ -460,6 +480,11 @@ static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = { .name = "ctrl_module_wkup", .class = &omap44xx_ctrl_module_hwmod_class, .clkdm_name = "l4_wkup_clkdm", + .prcm = { + .omap4 = { + .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, + }, + }, }; /* ctrl_module_pad_wkup */ @@ -467,6 +492,11 @@ static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = { .name = "ctrl_module_pad_wkup", .class = &omap44xx_ctrl_module_hwmod_class, .clkdm_name = "l4_wkup_clkdm", + .prcm = { + .omap4 = { + .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, + }, + }, }; /* @@ -611,7 +641,6 @@ static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = { static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = { { .name = "dsp", .rst_shift = 0 }, - { .name = "mmu_cache", .rst_shift = 1 }, }; static struct omap_hwmod omap44xx_dsp_hwmod = { @@ -1323,6 +1352,14 @@ static struct omap_hwmod omap44xx_gpmc_hwmod = { .name = "gpmc", .class = &omap44xx_gpmc_hwmod_class, .clkdm_name = "l3_2_clkdm", + /* + * XXX HWMOD_INIT_NO_RESET should not be needed for this IP + * block. It is not being added due to any known bugs with + * resetting the GPMC IP block, but rather because any timings + * set by the bootloader are not being correctly programmed by + * the kernel from the board file or DT data. + * HWMOD_INIT_NO_RESET should be removed ASAP. + */ .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, .mpu_irqs = omap44xx_gpmc_irqs, .sdma_reqs = omap44xx_gpmc_sdma_reqs, @@ -1631,7 +1668,6 @@ static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = { static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = { { .name = "cpu0", .rst_shift = 0 }, { .name = "cpu1", .rst_shift = 1 }, - { .name = "mmu_cache", .rst_shift = 2 }, }; static struct omap_hwmod omap44xx_ipu_hwmod = { @@ -2438,6 +2474,137 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = { }; /* + * 'mmu' class + * The memory management unit performs virtual to physical address translation + * for its requestors. + */ + +static struct omap_hwmod_class_sysconfig mmu_sysc = { + .rev_offs = 0x000, + .sysc_offs = 0x010, + .syss_offs = 0x014, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap44xx_mmu_hwmod_class = { + .name = "mmu", + .sysc = &mmu_sysc, +}; + +/* mmu ipu */ + +static struct omap_mmu_dev_attr mmu_ipu_dev_attr = { + .da_start = 0x0, + .da_end = 0xfffff000, + .nr_tlb_entries = 32, +}; + +static struct omap_hwmod omap44xx_mmu_ipu_hwmod; +static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs[] = { + { .irq = 100 + OMAP44XX_IRQ_GIC_START, }, + { .irq = -1 } +}; + +static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = { + { .name = "mmu_cache", .rst_shift = 2 }, +}; + +static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = { + { + .pa_start = 0x55082000, + .pa_end = 0x550820ff, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +/* l3_main_2 -> mmu_ipu */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_mmu_ipu_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_mmu_ipu_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod omap44xx_mmu_ipu_hwmod = { + .name = "mmu_ipu", + .class = &omap44xx_mmu_hwmod_class, + .clkdm_name = "ducati_clkdm", + .mpu_irqs = omap44xx_mmu_ipu_irqs, + .rst_lines = omap44xx_mmu_ipu_resets, + .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_ipu_resets), + .main_clk = "ducati_clk_mux_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET, + .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, + .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, + .dev_attr = &mmu_ipu_dev_attr, +}; + +/* mmu dsp */ + +static struct omap_mmu_dev_attr mmu_dsp_dev_attr = { + .da_start = 0x0, + .da_end = 0xfffff000, + .nr_tlb_entries = 32, +}; + +static struct omap_hwmod omap44xx_mmu_dsp_hwmod; +static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs[] = { + { .irq = 28 + OMAP44XX_IRQ_GIC_START }, + { .irq = -1 } +}; + +static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = { + { .name = "mmu_cache", .rst_shift = 1 }, +}; + +static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = { + { + .pa_start = 0x4a066000, + .pa_end = 0x4a0660ff, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +/* l4_cfg -> dsp */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_mmu_dsp_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mmu_dsp_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod omap44xx_mmu_dsp_hwmod = { + .name = "mmu_dsp", + .class = &omap44xx_mmu_hwmod_class, + .clkdm_name = "tesla_clkdm", + .mpu_irqs = omap44xx_mmu_dsp_irqs, + .rst_lines = omap44xx_mmu_dsp_resets, + .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_dsp_resets), + .main_clk = "dpll_iva_m4x2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET, + .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, + .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, + .dev_attr = &mmu_dsp_dev_attr, +}; + +/* * 'mpu' class * mpu sub-system */ @@ -2448,6 +2615,8 @@ static struct omap_hwmod_class omap44xx_mpu_hwmod_class = { /* mpu */ static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = { + { .name = "pmu0", .irq = 54 + OMAP44XX_IRQ_GIC_START }, + { .name = "pmu1", .irq = 55 + OMAP44XX_IRQ_GIC_START }, { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START }, { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START }, { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START }, @@ -2497,19 +2666,27 @@ static struct omap_hwmod omap44xx_ocmc_ram_hwmod = { * protocol */ +static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = { .name = "ocp2scp", + .sysc = &omap44xx_ocp2scp_sysc, }; /* ocp2scp_usb_phy */ -static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = { - { .role = "phy_48m", .clk = "ocp2scp_usb_phy_phy_48m" }, -}; - static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = { .name = "ocp2scp_usb_phy", .class = &omap44xx_ocp2scp_hwmod_class, .clkdm_name = "l3_init_clkdm", + .main_clk = "ocp2scp_usb_phy_phy_48m", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET, @@ -2517,8 +2694,6 @@ static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = { .modulemode = MODULEMODE_HWCTRL, }, }, - .opt_clks = ocp2scp_usb_phy_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks), }; /* @@ -2536,18 +2711,36 @@ static struct omap_hwmod omap44xx_prcm_mpu_hwmod = { .name = "prcm_mpu", .class = &omap44xx_prcm_hwmod_class, .clkdm_name = "l4_wkup_clkdm", + .flags = HWMOD_NO_IDLEST, + .prcm = { + .omap4 = { + .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, + }, + }, }; /* cm_core_aon */ static struct omap_hwmod omap44xx_cm_core_aon_hwmod = { .name = "cm_core_aon", .class = &omap44xx_prcm_hwmod_class, + .flags = HWMOD_NO_IDLEST, + .prcm = { + .omap4 = { + .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, + }, + }, }; /* cm_core */ static struct omap_hwmod omap44xx_cm_core_hwmod = { .name = "cm_core", .class = &omap44xx_prcm_hwmod_class, + .flags = HWMOD_NO_IDLEST, + .prcm = { + .omap4 = { + .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, + }, + }, }; /* prm */ @@ -2583,6 +2776,11 @@ static struct omap_hwmod omap44xx_scrm_hwmod = { .name = "scrm", .class = &omap44xx_scrm_hwmod_class, .clkdm_name = "l4_wkup_clkdm", + .prcm = { + .omap4 = { + .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, + }, + }, }; /* @@ -2901,6 +3099,16 @@ static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { .timer_capability = OMAP_TIMER_HAS_PWM, }; +/* timers with DSP interrupt dev attribute */ +static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = { + .timer_capability = OMAP_TIMER_HAS_DSP_IRQ, +}; + +/* pwm timers with DSP interrupt dev attribute */ +static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = { + .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM, +}; + /* timer1 */ static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = { { .irq = 37 + OMAP44XX_IRQ_GIC_START }, @@ -3005,6 +3213,7 @@ static struct omap_hwmod omap44xx_timer5_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, + .dev_attr = &capability_dsp_dev_attr, }; /* timer6 */ @@ -3027,6 +3236,7 @@ static struct omap_hwmod omap44xx_timer6_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, + .dev_attr = &capability_dsp_dev_attr, }; /* timer7 */ @@ -3048,6 +3258,7 @@ static struct omap_hwmod omap44xx_timer7_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, + .dev_attr = &capability_dsp_dev_attr, }; /* timer8 */ @@ -3069,7 +3280,7 @@ static struct omap_hwmod omap44xx_timer8_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &capability_pwm_dev_attr, + .dev_attr = &capability_dsp_pwm_dev_attr, }; /* timer9 */ @@ -5058,6 +5269,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = { static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = { { + .name = "mpu", .pa_start = 0x40132000, .pa_end = 0x4013207f, .flags = ADDR_TYPE_RT @@ -5076,6 +5288,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = { static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = { { + .name = "dma", .pa_start = 0x49032000, .pa_end = 0x4903207f, .flags = ADDR_TYPE_RT @@ -5262,11 +5475,21 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs[] = { + { + .pa_start = 0x4a0ad000, + .pa_end = 0x4a0ad01f, + .flags = ADDR_TYPE_RT + }, + { } +}; + /* l4_cfg -> ocp2scp_usb_phy */ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = { .master = &omap44xx_l4_cfg_hwmod, .slave = &omap44xx_ocp2scp_usb_phy_hwmod, .clk = "l4_div_ck", + .addr = omap44xx_ocp2scp_usb_phy_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -5886,7 +6109,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = { static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = { { .pa_start = 0x4a0ab000, - .pa_end = 0x4a0ab003, + .pa_end = 0x4a0ab7ff, .flags = ADDR_TYPE_RT }, { @@ -6097,6 +6320,8 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l4_per__mmc3, &omap44xx_l4_per__mmc4, &omap44xx_l4_per__mmc5, + &omap44xx_l3_main_2__mmu_ipu, + &omap44xx_l4_cfg__mmu_dsp, &omap44xx_l3_main_2__ocmc_ram, &omap44xx_l4_cfg__ocp2scp_usb_phy, &omap44xx_mpu_private__prcm_mpu, diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h index dddb677fed68..2bc8f1705d4a 100644 --- a/arch/arm/mach-omap2/omap_hwmod_common_data.h +++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h @@ -2,9 +2,8 @@ * omap_hwmod_common_data.h - OMAP hwmod common macros and declarations * * Copyright (C) 2010-2011 Nokia Corporation + * Copyright (C) 2010-2012 Texas Instruments, Inc. * Paul Walmsley - * - * Copyright (C) 2010-2011 Texas Instruments, Inc. * Benoît Cousson * * This program is free software; you can redistribute it and/or modify @@ -77,6 +76,8 @@ extern struct omap_hwmod omap2xxx_gpio4_hwmod; extern struct omap_hwmod omap2xxx_mcspi1_hwmod; extern struct omap_hwmod omap2xxx_mcspi2_hwmod; extern struct omap_hwmod omap2xxx_counter_32k_hwmod; +extern struct omap_hwmod omap2xxx_gpmc_hwmod; +extern struct omap_hwmod omap2xxx_rng_hwmod; /* Common interface data across OMAP2xxx */ extern struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core; @@ -103,6 +104,7 @@ extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss; extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc; extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi; extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc; +extern struct omap_hwmod_ocp_if omap2xxx_l4_core__rng; /* Common IP block data */ extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[]; diff --git a/arch/arm/mach-omap2/opp.c b/arch/arm/mach-omap2/opp.c index 45ad7f74f356..58e16aef40bb 100644 --- a/arch/arm/mach-omap2/opp.c +++ b/arch/arm/mach-omap2/opp.c @@ -18,6 +18,7 @@ */ #include <linux/module.h> #include <linux/opp.h> +#include <linux/cpu.h> #include <plat/omap_device.h> @@ -62,13 +63,23 @@ int __init omap_init_opp_table(struct omap_opp_def *opp_def, __func__, i); return -EINVAL; } - oh = omap_hwmod_lookup(opp_def->hwmod_name); - if (!oh || !oh->od) { - pr_debug("%s: no hwmod or odev for %s, [%d] cannot add OPPs.\n", - __func__, opp_def->hwmod_name, i); - continue; + + if (!strncmp(opp_def->hwmod_name, "mpu", 3)) { + /* + * All current OMAPs share voltage rail and + * clock source, so CPU0 is used to represent + * the MPU-SS. + */ + dev = get_cpu_device(0); + } else { + oh = omap_hwmod_lookup(opp_def->hwmod_name); + if (!oh || !oh->od) { + pr_debug("%s: no hwmod or odev for %s, [%d] cannot add OPPs.\n", + __func__, opp_def->hwmod_name, i); + continue; + } + dev = &oh->od->pdev->dev; } - dev = &oh->od->pdev->dev; r = opp_add(dev, opp_def->freq, opp_def->u_volt); if (r) { diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c index 3e1345fc0713..46092cd806fa 100644 --- a/arch/arm/mach-omap2/pm-debug.c +++ b/arch/arm/mach-omap2/pm-debug.c @@ -168,7 +168,7 @@ static int pm_dbg_open(struct inode *inode, struct file *file) default: return single_open(file, pm_dbg_show_timers, &inode->i_private); - }; + } } static const struct file_operations debug_fops = { diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index 939bd6f70b51..ea61c32957bd 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -16,6 +16,7 @@ #include <linux/opp.h> #include <linux/export.h> #include <linux/suspend.h> +#include <linux/cpu.h> #include <asm/system_misc.h> @@ -80,7 +81,8 @@ static void __init omap2_init_processor_devices(void) int __init omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused) { - if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) + if ((clkdm->flags & CLKDM_CAN_ENABLE_AUTO) && + !(clkdm->flags & CLKDM_MISSING_IDLE_REPORTING)) clkdm_allow_idle(clkdm); else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && atomic_read(&clkdm->usecount) == 0) @@ -168,7 +170,15 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name, goto exit; } - dev = omap_device_get_by_hwmod_name(oh_name); + if (!strncmp(oh_name, "mpu", 3)) + /* + * All current OMAPs share voltage rail and clock + * source, so CPU0 is used to represent the MPU-SS. + */ + dev = get_cpu_device(0); + else + dev = omap_device_get_by_hwmod_name(oh_name); + if (IS_ERR(dev)) { pr_err("%s: Unable to get dev pointer for hwmod %s\n", __func__, oh_name); @@ -176,7 +186,7 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name, } voltdm = voltdm_lookup(vdd_name); - if (IS_ERR(voltdm)) { + if (!voltdm) { pr_err("%s: unable to get vdd pointer for vdd_%s\n", __func__, vdd_name); goto exit; @@ -188,7 +198,7 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name, goto exit; } - freq = clk->rate; + freq = clk_get_rate(clk); clk_put(clk); rcu_read_lock(); diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index 686137d164da..67d66131cfa7 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h @@ -91,6 +91,7 @@ extern void omap3_save_scratchpad_contents(void); #define PM_RTA_ERRATUM_i608 (1 << 0) #define PM_SDRC_WAKEUP_ERRATUM_i583 (1 << 1) +#define PM_PER_MEMORIES_ERRATUM_i582 (1 << 2) #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) extern u16 pm34xx_errata; diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index ba670db1fd37..3a904de4313e 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -652,14 +652,17 @@ static void __init pm_errata_configure(void) /* Enable the l2 cache toggling in sleep logic */ enable_omap3630_toggle_l2_on_restore(); if (omap_rev() < OMAP3630_REV_ES1_2) - pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583; + pm34xx_errata |= (PM_SDRC_WAKEUP_ERRATUM_i583 | + PM_PER_MEMORIES_ERRATUM_i582); + } else if (cpu_is_omap34xx()) { + pm34xx_errata |= PM_PER_MEMORIES_ERRATUM_i582; } } int __init omap3_pm_init(void) { struct power_state *pwrst, *tmp; - struct clockdomain *neon_clkdm, *mpu_clkdm; + struct clockdomain *neon_clkdm, *mpu_clkdm, *per_clkdm, *wkup_clkdm; int ret; if (!omap3_has_io_chain_ctrl()) @@ -711,6 +714,8 @@ int __init omap3_pm_init(void) neon_clkdm = clkdm_lookup("neon_clkdm"); mpu_clkdm = clkdm_lookup("mpu_clkdm"); + per_clkdm = clkdm_lookup("per_clkdm"); + wkup_clkdm = clkdm_lookup("wkup_clkdm"); #ifdef CONFIG_SUSPEND omap_pm_suspend = omap3_pm_suspend; @@ -727,6 +732,27 @@ int __init omap3_pm_init(void) if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608)) omap3630_ctrl_disable_rta(); + /* + * The UART3/4 FIFO and the sidetone memory in McBSP2/3 are + * not correctly reset when the PER powerdomain comes back + * from OFF or OSWR when the CORE powerdomain is kept active. + * See OMAP36xx Erratum i582 "PER Domain reset issue after + * Domain-OFF/OSWR Wakeup". This wakeup dependency is not a + * complete workaround. The kernel must also prevent the PER + * powerdomain from going to OSWR/OFF while the CORE + * powerdomain is not going to OSWR/OFF. And if PER last + * power state was off while CORE last power state was ON, the + * UART3/4 and McBSP2/3 SIDETONE devices need to run a + * self-test using their loopback tests; if that fails, those + * devices are unusable until the PER/CORE can complete a transition + * from ON to OSWR/OFF and then back to ON. + * + * XXX Technically this workaround is only needed if off-mode + * or OSWR is enabled. + */ + if (IS_PM34XX_ERRATUM(PM_PER_MEMORIES_ERRATUM_i582)) + clkdm_add_wkdep(per_clkdm, wkup_clkdm); + clkdm_add_wkdep(neon_clkdm, mpu_clkdm); if (omap_type() != OMAP2_DEVICE_TYPE_GP) { omap3_secure_ram_storage = diff --git a/arch/arm/mach-omap2/pmu.c b/arch/arm/mach-omap2/pmu.c new file mode 100644 index 000000000000..2a791766283d --- /dev/null +++ b/arch/arm/mach-omap2/pmu.c @@ -0,0 +1,95 @@ +/* + * OMAP2 ARM Performance Monitoring Unit (PMU) Support + * + * Copyright (C) 2012 Texas Instruments, Inc. + * + * Contacts: + * Jon Hunter <jon-hunter@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#include <linux/pm_runtime.h> + +#include <asm/pmu.h> + +#include <plat/omap_hwmod.h> +#include <plat/omap_device.h> + +static char *omap2_pmu_oh_names[] = {"mpu"}; +static char *omap3_pmu_oh_names[] = {"mpu", "debugss"}; +static char *omap4430_pmu_oh_names[] = {"l3_main_3", "l3_instr", "debugss"}; +static struct platform_device *omap_pmu_dev; + +/** + * omap2_init_pmu - creates and registers PMU platform device + * @oh_num: Number of OMAP HWMODs required to create PMU device + * @oh_names: Array of OMAP HWMODS names required to create PMU device + * + * Uses OMAP HWMOD framework to create and register an ARM PMU device + * from a list of HWMOD names passed. Currently supports OMAP2, OMAP3 + * and OMAP4 devices. + */ +static int __init omap2_init_pmu(unsigned oh_num, char *oh_names[]) +{ + int i; + struct omap_hwmod *oh[3]; + char *dev_name = "arm-pmu"; + + if ((!oh_num) || (oh_num > 3)) + return -EINVAL; + + for (i = 0; i < oh_num; i++) { + oh[i] = omap_hwmod_lookup(oh_names[i]); + if (!oh[i]) { + pr_err("Could not look up %s hwmod\n", oh_names[i]); + return -ENODEV; + } + } + + omap_pmu_dev = omap_device_build_ss(dev_name, -1, oh, oh_num, NULL, 0, + NULL, 0, 0); + WARN(IS_ERR(omap_pmu_dev), "Can't build omap_device for %s.\n", + dev_name); + + if (IS_ERR(omap_pmu_dev)) + return PTR_ERR(omap_pmu_dev); + + pm_runtime_enable(&omap_pmu_dev->dev); + + return 0; +} + +static int __init omap_init_pmu(void) +{ + unsigned oh_num; + char **oh_names; + + /* + * To create an ARM-PMU device the following HWMODs + * are required for the various OMAP2+ devices. + * + * OMAP24xx: mpu + * OMAP3xxx: mpu, debugss + * OMAP4430: l3_main_3, l3_instr, debugss + * OMAP4460/70: mpu, debugss + */ + if (cpu_is_omap443x()) { + oh_num = ARRAY_SIZE(omap4430_pmu_oh_names); + oh_names = omap4430_pmu_oh_names; + /* XXX Remove the next two lines when CTI driver available */ + pr_info("ARM PMU: not yet supported on OMAP4430 due to missing CTI driver\n"); + return 0; + } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) { + oh_num = ARRAY_SIZE(omap3_pmu_oh_names); + oh_names = omap3_pmu_oh_names; + } else { + oh_num = ARRAY_SIZE(omap2_pmu_oh_names); + oh_names = omap2_pmu_oh_names; + } + + return omap2_init_pmu(oh_num, oh_names); +} +subsys_initcall(omap_init_pmu); diff --git a/arch/arm/mach-omap2/powerdomain44xx.c b/arch/arm/mach-omap2/powerdomain44xx.c index aeac6f35ca10..aceb4f464c9b 100644 --- a/arch/arm/mach-omap2/powerdomain44xx.c +++ b/arch/arm/mach-omap2/powerdomain44xx.c @@ -1,7 +1,7 @@ /* * OMAP4 powerdomain control * - * Copyright (C) 2009-2010 Texas Instruments, Inc. + * Copyright (C) 2009-2010, 2012 Texas Instruments, Inc. * Copyright (C) 2007-2009 Nokia Corporation * * Derived from mach-omap2/powerdomain.c written by Paul Walmsley @@ -151,6 +151,34 @@ static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm) return v; } +/** + * omap4_pwrdm_read_prev_logic_pwrst - read the previous logic powerstate + * @pwrdm: struct powerdomain * to read the state for + * + * Reads the previous logic powerstate for a powerdomain. This + * function must determine the previous logic powerstate by first + * checking the previous powerstate for the domain. If that was OFF, + * then logic has been lost. If previous state was RETENTION, the + * function reads the setting for the next retention logic state to + * see the actual value. In every other case, the logic is + * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET + * depending whether the logic was retained or not. + */ +static int omap4_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm) +{ + int state; + + state = omap4_pwrdm_read_prev_pwrst(pwrdm); + + if (state == PWRDM_POWER_OFF) + return PWRDM_POWER_OFF; + + if (state != PWRDM_POWER_RET) + return PWRDM_POWER_RET; + + return omap4_pwrdm_read_logic_retst(pwrdm); +} + static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) { u32 m, v; @@ -179,6 +207,35 @@ static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) return v; } +/** + * omap4_pwrdm_read_prev_mem_pwrst - reads the previous memory powerstate + * @pwrdm: struct powerdomain * to read mem powerstate for + * @bank: memory bank index + * + * Reads the previous memory powerstate for a powerdomain. This + * function must determine the previous memory powerstate by first + * checking the previous powerstate for the domain. If that was OFF, + * then logic has been lost. If previous state was RETENTION, the + * function reads the setting for the next memory retention state to + * see the actual value. In every other case, the logic is + * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET + * depending whether logic was retained or not. + */ +static int omap4_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank) +{ + int state; + + state = omap4_pwrdm_read_prev_pwrst(pwrdm); + + if (state == PWRDM_POWER_OFF) + return PWRDM_POWER_OFF; + + if (state != PWRDM_POWER_RET) + return PWRDM_POWER_RET; + + return omap4_pwrdm_read_mem_retst(pwrdm, bank); +} + static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm) { u32 c = 0; @@ -217,9 +274,11 @@ struct pwrdm_ops omap4_pwrdm_operations = { .pwrdm_clear_all_prev_pwrst = omap4_pwrdm_clear_all_prev_pwrst, .pwrdm_set_logic_retst = omap4_pwrdm_set_logic_retst, .pwrdm_read_logic_pwrst = omap4_pwrdm_read_logic_pwrst, + .pwrdm_read_prev_logic_pwrst = omap4_pwrdm_read_prev_logic_pwrst, .pwrdm_read_logic_retst = omap4_pwrdm_read_logic_retst, .pwrdm_read_mem_pwrst = omap4_pwrdm_read_mem_pwrst, .pwrdm_read_mem_retst = omap4_pwrdm_read_mem_retst, + .pwrdm_read_prev_mem_pwrst = omap4_pwrdm_read_prev_mem_pwrst, .pwrdm_set_mem_onst = omap4_pwrdm_set_mem_onst, .pwrdm_set_mem_retst = omap4_pwrdm_set_mem_retst, .pwrdm_wait_transition = omap4_pwrdm_wait_transition, diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index e5f0503a68b0..72df97482cc0 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h @@ -109,6 +109,8 @@ #define OMAP2430_EN_MDM_INTC_MASK (1 << 11) #define OMAP2430_EN_USBHS_SHIFT 6 #define OMAP2430_EN_USBHS_MASK (1 << 6) +#define OMAP24XX_EN_GPMC_SHIFT 1 +#define OMAP24XX_EN_GPMC_MASK (1 << 1) /* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */ #define OMAP2420_ST_MMC_SHIFT 26 diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 0405c8190803..a507cd6cf4f1 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -329,6 +329,11 @@ void __init omap_serial_init_port(struct omap_board_data *bdata, oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt); + if (console_uart_id == bdata->id) { + omap_device_enable(pdev); + pm_runtime_set_active(&pdev->dev); + } + oh->dev_attr = uart; if (((cpu_is_omap34xx() || cpu_is_omap44xx()) && bdata->pads) diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c index cbeae56b56a9..f8217a5a4a26 100644 --- a/arch/arm/mach-omap2/sr_device.c +++ b/arch/arm/mach-omap2/sr_device.c @@ -122,7 +122,7 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user) sr_data->senp_mod = 0x1; sr_data->voltdm = voltdm_lookup(sr_dev_attr->sensor_voltdm_name); - if (IS_ERR(sr_data->voltdm)) { + if (!sr_data->voltdm) { pr_err("%s: Unable to get voltage domain pointer for VDD %s\n", __func__, sr_dev_attr->sensor_voltdm_name); goto exit; diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 8847d6eb2313..69e46631a7cd 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -378,7 +378,7 @@ static void __init realtime_counter_init(void) return; } sys_clk = clk_get(NULL, "sys_clkin_ck"); - if (!sys_clk) { + if (IS_ERR(sys_clk)) { pr_err("%s: failed to get system clock handle\n", __func__); iounmap(base); return; @@ -467,7 +467,7 @@ OMAP_SYS_TIMER(3_am33xx) #ifdef CONFIG_ARCH_OMAP4 #ifdef CONFIG_LOCAL_TIMERS static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, - OMAP44XX_LOCAL_TWD_BASE, 29 + OMAP_INTC_START); + OMAP44XX_LOCAL_TWD_BASE, 29); #endif static void __init omap4_timer_init(void) diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c index 45f77413c21d..635e109f5ad3 100644 --- a/arch/arm/mach-omap2/twl-common.c +++ b/arch/arm/mach-omap2/twl-common.c @@ -158,7 +158,7 @@ static struct regulator_init_data omap3_vpll2_idata = { }; static struct regulator_consumer_supply omap3_vdd1_supply[] = { - REGULATOR_SUPPLY("vcc", "mpu.0"), + REGULATOR_SUPPLY("vcc", "cpu0"), }; static struct regulator_consumer_supply omap3_vdd2_supply[] = { @@ -239,6 +239,10 @@ void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data, static struct twl4030_usb_data omap4_usb_pdata = { }; +static struct regulator_consumer_supply omap4_vdda_hdmi_dac_supplies[] = { + REGULATOR_SUPPLY("vdda_hdmi_dac", "omapdss_hdmi"), +}; + static struct regulator_init_data omap4_vdac_idata = { .constraints = { .min_uV = 1800000, @@ -248,6 +252,8 @@ static struct regulator_init_data omap4_vdac_idata = { .valid_ops_mask = REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, }, + .num_consumer_supplies = ARRAY_SIZE(omap4_vdda_hdmi_dac_supplies), + .consumer_supplies = omap4_vdda_hdmi_dac_supplies, .supply_regulator = "V2V1", }; @@ -519,3 +525,30 @@ void __init omap4_pmic_get_config(struct twl4030_platform_data *pmic_data, pmic_data->v2v1 = &omap4_v2v1_idata; } #endif /* CONFIG_ARCH_OMAP4 */ + +#if defined(CONFIG_SND_OMAP_SOC_OMAP_TWL4030) || \ + defined(CONFIG_SND_OMAP_SOC_OMAP_TWL4030_MODULE) +#include <linux/platform_data/omap-twl4030.h> + +static struct omap_tw4030_pdata omap_twl4030_audio_data; + +static struct platform_device audio_device = { + .name = "omap-twl4030", + .id = -1, + .dev = { + .platform_data = &omap_twl4030_audio_data, + }, +}; + +void __init omap_twl4030_audio_init(char *card_name) +{ + omap_twl4030_audio_data.card_name = card_name; + platform_device_register(&audio_device); +} + +#else /* SOC_OMAP_TWL4030 */ +void __init omap_twl4030_audio_init(char *card_name) +{ + return; +} +#endif /* SOC_OMAP_TWL4030 */ diff --git a/arch/arm/mach-omap2/twl-common.h b/arch/arm/mach-omap2/twl-common.h index 2256efe90cf1..dcfbad5ac471 100644 --- a/arch/arm/mach-omap2/twl-common.h +++ b/arch/arm/mach-omap2/twl-common.h @@ -60,4 +60,6 @@ void omap3_pmic_get_config(struct twl4030_platform_data *pmic_data, void omap4_pmic_get_config(struct twl4030_platform_data *pmic_data, u32 pdata_flags, u32 regulators_flags); +void omap_twl4030_audio_init(char *card_name); + #endif /* __OMAP_PMIC_COMMON__ */ diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c index ac95daaa4702..3c434498e12e 100644 --- a/arch/arm/mach-omap2/usb-host.c +++ b/arch/arm/mach-omap2/usb-host.c @@ -33,10 +33,12 @@ #ifdef CONFIG_MFD_OMAP_USB_HOST #define OMAP_USBHS_DEVICE "usbhs_omap" +#define OMAP_USBTLL_DEVICE "usbhs_tll" #define USBHS_UHH_HWMODNAME "usb_host_hs" #define USBHS_TLL_HWMODNAME "usb_tll_hs" static struct usbhs_omap_platform_data usbhs_data; +static struct usbtll_omap_platform_data usbtll_data; static struct ehci_hcd_omap_platform_data ehci_data; static struct ohci_hcd_omap_platform_data ohci_data; @@ -485,13 +487,14 @@ void __init setup_4430ohci_io_mux(const enum usbhs_omap_port_mode *port_mode) void __init usbhs_init(const struct usbhs_omap_board_data *pdata) { - struct omap_hwmod *oh[2]; + struct omap_hwmod *uhh_hwm, *tll_hwm; struct platform_device *pdev; int bus_id = -1; int i; for (i = 0; i < OMAP3_HS_USB_PORTS; i++) { usbhs_data.port_mode[i] = pdata->port_mode[i]; + usbtll_data.port_mode[i] = pdata->port_mode[i]; ohci_data.port_mode[i] = pdata->port_mode[i]; ehci_data.port_mode[i] = pdata->port_mode[i]; ehci_data.reset_gpio_port[i] = pdata->reset_gpio_port[i]; @@ -510,25 +513,35 @@ void __init usbhs_init(const struct usbhs_omap_board_data *pdata) setup_4430ohci_io_mux(pdata->port_mode); } - oh[0] = omap_hwmod_lookup(USBHS_UHH_HWMODNAME); - if (!oh[0]) { + uhh_hwm = omap_hwmod_lookup(USBHS_UHH_HWMODNAME); + if (!uhh_hwm) { pr_err("Could not look up %s\n", USBHS_UHH_HWMODNAME); return; } - oh[1] = omap_hwmod_lookup(USBHS_TLL_HWMODNAME); - if (!oh[1]) { + tll_hwm = omap_hwmod_lookup(USBHS_TLL_HWMODNAME); + if (!tll_hwm) { pr_err("Could not look up %s\n", USBHS_TLL_HWMODNAME); return; } - pdev = omap_device_build_ss(OMAP_USBHS_DEVICE, bus_id, oh, 2, - (void *)&usbhs_data, sizeof(usbhs_data), + pdev = omap_device_build(OMAP_USBTLL_DEVICE, bus_id, tll_hwm, + &usbtll_data, sizeof(usbtll_data), omap_uhhtll_latency, ARRAY_SIZE(omap_uhhtll_latency), false); if (IS_ERR(pdev)) { - pr_err("Could not build hwmod devices %s,%s\n", - USBHS_UHH_HWMODNAME, USBHS_TLL_HWMODNAME); + pr_err("Could not build hwmod device %s\n", + USBHS_TLL_HWMODNAME); + return; + } + + pdev = omap_device_build(OMAP_USBHS_DEVICE, bus_id, uhh_hwm, + &usbhs_data, sizeof(usbhs_data), + omap_uhhtll_latency, + ARRAY_SIZE(omap_uhhtll_latency), false); + if (IS_ERR(pdev)) { + pr_err("Could not build hwmod devices %s\n", + USBHS_UHH_HWMODNAME); return; } } diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c index eaac83d1df6f..b5efc0fd31cb 100644 --- a/arch/arm/mach-orion5x/addr-map.c +++ b/arch/arm/mach-orion5x/addr-map.c @@ -113,7 +113,8 @@ void __init orion5x_setup_cpu_mbus_bridge(void) /* * Setup MBUS dram target info. */ - orion_setup_cpu_mbus_target(&addr_map_cfg, ORION5X_DDR_WINDOW_CPU_BASE); + orion_setup_cpu_mbus_target(&addr_map_cfg, + (void __iomem *) ORION5X_DDR_WINDOW_CPU_BASE); } void __init orion5x_setup_dev_boot_win(u32 base, u32 size) diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 073c7d799068..b3eb3da01160 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -42,12 +42,12 @@ ****************************************************************************/ static struct map_desc orion5x_io_desc[] __initdata = { { - .virtual = ORION5X_REGS_VIRT_BASE, + .virtual = (unsigned long) ORION5X_REGS_VIRT_BASE, .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE), .length = ORION5X_REGS_SIZE, .type = MT_DEVICE, }, { - .virtual = ORION5X_PCIE_WA_VIRT_BASE, + .virtual = (unsigned long) ORION5X_PCIE_WA_VIRT_BASE, .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE), .length = ORION5X_PCIE_WA_SIZE, .type = MT_DEVICE, diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c index 0e19db69f5c4..e533588880ff 100644 --- a/arch/arm/mach-orion5x/dns323-setup.c +++ b/arch/arm/mach-orion5x/dns323-setup.c @@ -701,7 +701,7 @@ static void __init dns323_init(void) * Note: AFAIK, rev B1 needs the same treatement but I'll let * somebody else test it. */ - writel(0x5, ORION5X_SATA_VIRT_BASE | 0x2c); + writel(0x5, ORION5X_SATA_VIRT_BASE + 0x2c); break; } } diff --git a/arch/arm/mach-orion5x/include/mach/bridge-regs.h b/arch/arm/mach-orion5x/include/mach/bridge-regs.h index 11a3c1e9801f..461fd69a10ae 100644 --- a/arch/arm/mach-orion5x/include/mach/bridge-regs.h +++ b/arch/arm/mach-orion5x/include/mach/bridge-regs.h @@ -13,27 +13,27 @@ #include <mach/orion5x.h> -#define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE | 0x100) +#define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE + 0x100) -#define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE | 0x104) +#define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104) -#define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x108) +#define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108) #define WDT_RESET_OUT_EN 0x0002 -#define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE | 0x10c) +#define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c) -#define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x110) +#define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x110) -#define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE | 0x11C) +#define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C) #define WDT_INT_REQ 0x0008 #define BRIDGE_INT_TIMER1_CLR (~0x0004) -#define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x200) +#define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200) -#define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x204) +#define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x204) -#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE | 0x300) -#define TIMER_PHYS_BASE (ORION5X_BRIDGE_PHYS_BASE | 0x300) +#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE + 0x300) +#define TIMER_PHYS_BASE (ORION5X_BRIDGE_PHYS_BASE + 0x300) #endif diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h index 1b60131b7f60..d265f5484a8e 100644 --- a/arch/arm/mach-orion5x/include/mach/orion5x.h +++ b/arch/arm/mach-orion5x/include/mach/orion5x.h @@ -37,7 +37,7 @@ * fd000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only) ****************************************************************************/ #define ORION5X_REGS_PHYS_BASE 0xf1000000 -#define ORION5X_REGS_VIRT_BASE 0xfe000000 +#define ORION5X_REGS_VIRT_BASE IOMEM(0xfe000000) #define ORION5X_REGS_SIZE SZ_1M #define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000 @@ -53,7 +53,7 @@ /* Relevant only for Orion-1/Orion-NAS */ #define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000 -#define ORION5X_PCIE_WA_VIRT_BASE 0xfd000000 +#define ORION5X_PCIE_WA_VIRT_BASE IOMEM(0xfd000000) #define ORION5X_PCIE_WA_SIZE SZ_16M #define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000 @@ -66,42 +66,42 @@ * Orion Registers Map ******************************************************************************/ -#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x00000) -#define ORION5X_DDR_WINDOW_CPU_BASE (ORION5X_DDR_VIRT_BASE | 0x1500) -#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000) -#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000) -#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE | (x)) +#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x00000) +#define ORION5X_DDR_WINDOW_CPU_BASE (ORION5X_DDR_VIRT_BASE + 0x1500) +#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x10000) +#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x10000) +#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE + (x)) #define GPIO_VIRT_BASE ORION5X_DEV_BUS_REG(0x0100) -#define SPI_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x0600) -#define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x1000) -#define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2000) -#define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2000) -#define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2100) -#define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2100) +#define SPI_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x0600) +#define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x1000) +#define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x2000) +#define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE + 0x2000) +#define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x2100) +#define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE + 0x2100) -#define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x20000) -#define ORION5X_BRIDGE_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x20000) +#define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x20000) +#define ORION5X_BRIDGE_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x20000) -#define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x30000) +#define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x30000) -#define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x40000) +#define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x40000) -#define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x50000) -#define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x50000) +#define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x50000) +#define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x50000) -#define ORION5X_XOR_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x60900) -#define ORION5X_XOR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x60900) +#define ORION5X_XOR_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x60900) +#define ORION5X_XOR_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x60900) -#define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x70000) -#define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x70000) +#define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x70000) +#define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x70000) -#define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x80000) -#define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x80000) +#define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x80000) +#define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x80000) -#define ORION5X_CRYPTO_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x90000) +#define ORION5X_CRYPTO_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x90000) -#define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0xa0000) -#define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0xa0000) +#define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0xa0000) +#define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0xa0000) /******************************************************************************* * Device Bus Registers diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c index e152641cdb0e..30a192b9c517 100644 --- a/arch/arm/mach-orion5x/irq.c +++ b/arch/arm/mach-orion5x/irq.c @@ -12,6 +12,7 @@ #include <linux/gpio.h> #include <linux/kernel.h> #include <linux/irq.h> +#include <linux/io.h> #include <mach/bridge-regs.h> #include <plat/orion-gpio.h> #include <plat/irq.h> @@ -25,11 +26,11 @@ static int __initdata gpio0_irqs[4] = { void __init orion5x_init_irq(void) { - orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK); + orion_irq_init(0, MAIN_IRQ_MASK); /* * Initialize gpiolib for GPIOs 0-31. */ - orion_gpio_init(NULL, 0, 32, (void __iomem *)GPIO_VIRT_BASE, 0, + orion_gpio_init(NULL, 0, 32, GPIO_VIRT_BASE, 0, IRQ_ORION5X_GPIO_START, gpio0_irqs); } diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c index 6921d49b988d..cd50e328db2a 100644 --- a/arch/arm/mach-orion5x/pci.c +++ b/arch/arm/mach-orion5x/pci.c @@ -38,7 +38,7 @@ /***************************************************************************** * PCIe controller ****************************************************************************/ -#define PCIE_BASE ((void __iomem *)ORION5X_PCIE_VIRT_BASE) +#define PCIE_BASE (ORION5X_PCIE_VIRT_BASE) void __init orion5x_pcie_id(u32 *dev, u32 *rev) { @@ -111,7 +111,7 @@ static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn, return PCIBIOS_DEVICE_NOT_FOUND; } - ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE, + ret = orion_pcie_rd_conf_wa(ORION5X_PCIE_WA_VIRT_BASE, bus, devfn, where, size, val); return ret; @@ -188,7 +188,7 @@ static int __init pcie_setup(struct pci_sys_data *sys) /***************************************************************************** * PCI controller ****************************************************************************/ -#define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE | (x)) +#define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE + (x)) #define PCI_MODE ORION5X_PCI_REG(0xd00) #define PCI_CMD ORION5X_PCI_REG(0xc00) #define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14) diff --git a/arch/arm/mach-prima2/Kconfig b/arch/arm/mach-prima2/Kconfig index 41fc85327673..558ccfb8d458 100644 --- a/arch/arm/mach-prima2/Kconfig +++ b/arch/arm/mach-prima2/Kconfig @@ -6,8 +6,8 @@ config ARCH_PRIMA2 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform" default y select CPU_V7 - select ZONE_DMA select SIRF_IRQ + select ZONE_DMA help Support for CSR SiRFSoC ARM Cortex A9 Platform diff --git a/arch/arm/mach-prima2/include/mach/gpio.h b/arch/arm/mach-prima2/include/mach/gpio.h deleted file mode 100644 index 1904bb03876e..000000000000 --- a/arch/arm/mach-prima2/include/mach/gpio.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef __MACH_GPIO_H -#define __MACH_GPIO_H - -/* Pull up/down values */ -enum sirfsoc_gpio_pull { - SIRFSOC_GPIO_PULL_NONE, - SIRFSOC_GPIO_PULL_UP, - SIRFSOC_GPIO_PULL_DOWN, -}; - -void sirfsoc_gpio_set_pull(unsigned gpio, unsigned mode); - -#endif diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index 8e6288de69b9..11aa7399dc09 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -27,10 +27,10 @@ comment "Intel/Marvell Dev Platforms (sorted by hardware release time)" config MACH_PXA3XX_DT bool "Support PXA3xx platforms from device tree" - select PXA3xx select CPU_PXA300 - select POWER_SUPPLY select HAVE_PWM + select POWER_SUPPLY + select PXA3xx select USE_OF help Include support for Marvell PXA3xx based platforms using @@ -44,13 +44,13 @@ config ARCH_LUBBOCK config MACH_MAINSTONE bool "Intel HCDDBBVA0 Development Platform (aka Mainstone)" - select PXA27x select HAVE_PWM + select PXA27x config MACH_ZYLONITE bool - select PXA3xx select HAVE_PWM + select PXA3xx config MACH_ZYLONITE300 bool "PXA3xx Development Platform (aka Zylonite) PXA300/310" @@ -65,19 +65,19 @@ config MACH_ZYLONITE320 config MACH_LITTLETON bool "PXA3xx Form Factor Platform (aka Littleton)" - select PXA3xx select CPU_PXA300 select CPU_PXA310 + select PXA3xx config MACH_TAVOREVB bool "PXA930 Evaluation Board (aka TavorEVB)" - select PXA3xx select CPU_PXA930 + select PXA3xx config MACH_SAAR bool "PXA930 Handheld Platform (aka SAAR)" - select PXA3xx select CPU_PXA930 + select PXA3xx comment "Third Party Dev Platforms (sorted by vendor name)" @@ -87,29 +87,29 @@ config ARCH_PXA_IDP config ARCH_VIPER bool "Arcom/Eurotech VIPER SBC" - select PXA25x - select ISA - select I2C_GPIO + select ARCOM_PCMCIA select HAVE_PWM + select I2C_GPIO + select ISA + select PXA25x select PXA_HAVE_ISA_IRQS - select ARCOM_PCMCIA config MACH_ARCOM_ZEUS bool "Arcom/Eurotech ZEUS SBC" - select PXA27x + select ARCOM_PCMCIA select ISA + select PXA27x select PXA_HAVE_ISA_IRQS - select ARCOM_PCMCIA config MACH_BALLOON3 bool "Balloon 3 board" - select PXA27x select IWMMXT + select PXA27x config MACH_CSB726 bool "Enable Cogent CSB726 System On a Module" - select PXA27x select IWMMXT + select PXA27x help Say Y here if you intend to run this kernel on a Cogent CSB726 System On Module. @@ -121,11 +121,11 @@ config CSB726_CSB701 config MACH_ARMCORE bool "CompuLab CM-X255/CM-X270 modules" select ARCH_HAS_DMA_SET_COHERENT_MASK if PCI - select PXA27x select IWMMXT - select PXA25x select MIGHT_HAVE_PCI select NEED_MACH_IO_H if PCI + select PXA25x + select PXA27x config MACH_EM_X270 bool "CompuLab EM-x270 platform" @@ -137,10 +137,10 @@ config MACH_EXEDA config MACH_CM_X300 bool "CompuLab CM-X300 modules" - select PXA3xx select CPU_PXA300 select CPU_PXA310 select HAVE_PWM + select PXA3xx config MACH_CAPC7117 bool "Embedian CAPC-7117 evaluation kit based on the MXM-8x10 CoM" @@ -168,22 +168,22 @@ endchoice config MACH_INTELMOTE2 bool "Intel Mote 2 Platform" - select PXA27x select IWMMXT + select PXA27x config MACH_STARGATE2 bool "Intel Stargate 2 Platform" - select PXA27x select IWMMXT + select PXA27x config MACH_XCEP bool "Iskratel Electronics XCEP" - select PXA25x select MTD - select MTD_PHYSMAP - select MTD_CFI_INTELEXT select MTD_CFI + select MTD_CFI_INTELEXT select MTD_CHAR + select MTD_PHYSMAP + select PXA25x select SMC91X help PXA255 based Single Board Computer with SMC 91C111 ethernet chip and 64 MB of flash. @@ -195,14 +195,14 @@ config TRIZEPS_PXA config MACH_TRIZEPS4 bool "Keith und Koep Trizeps4 DIMM-Module" depends on TRIZEPS_PXA - select TRIZEPS_PCMCIA select PXA27x + select TRIZEPS_PCMCIA config MACH_TRIZEPS4WL bool "Keith und Koep Trizeps4-WL DIMM-Module" depends on TRIZEPS_PXA - select TRIZEPS_PCMCIA select PXA27x + select TRIZEPS_PCMCIA choice prompt "Select base board for Trizeps module" @@ -231,18 +231,18 @@ config TRIZEPS_PCMCIA config MACH_LOGICPD_PXA270 bool "LogicPD PXA270 Card Engine Development Platform" - select PXA27x select HAVE_PWM + select PXA27x config MACH_PCM027 bool "Phytec phyCORE-PXA270 CPU module (PCM-027)" - select PXA27x select IWMMXT + select PXA27x config MACH_PCM990_BASEBOARD bool "PHYTEC PCM-990 development board" - select HAVE_PWM depends on MACH_PCM027 + select HAVE_PWM choice prompt "display on pcm990" @@ -266,19 +266,19 @@ config MACH_COLIBRI config MACH_COLIBRI_PXA270_INCOME bool "Income s.r.o. PXA270 SBC" depends on MACH_COLIBRI - select PXA27x select HAVE_PWM + select PXA27x config MACH_COLIBRI300 bool "Toradex Colibri PXA300/310" - select PXA3xx select CPU_PXA300 select CPU_PXA310 + select PXA3xx config MACH_COLIBRI320 bool "Toradex Colibri PXA320" - select PXA3xx select CPU_PXA320 + select PXA3xx config MACH_COLIBRI_EVALBOARD bool "Toradex Colibri Evaluation Carrier Board support" @@ -286,8 +286,8 @@ config MACH_COLIBRI_EVALBOARD config MACH_VPAC270 bool "Voipac PXA270" - select PXA27x select HAVE_PATA_PLATFORM + select PXA27x help PXA270 based Single Board Computer. @@ -295,9 +295,9 @@ comment "End-user Products (sorted by vendor name)" config MACH_H4700 bool "HP iPAQ hx4700" - select PXA27x - select IWMMXT select HAVE_PWM + select IWMMXT + select PXA27x config MACH_H5000 bool "HP iPAQ h5000" @@ -309,16 +309,16 @@ config MACH_HIMALAYA config MACH_MAGICIAN bool "Enable HTC Magician Support" - select PXA27x - select IWMMXT select HAVE_PWM + select IWMMXT + select PXA27x config MACH_MIOA701 bool "Mitac Mio A701 Support" - select PXA27x - select IWMMXT - select HAVE_PWM select GPIO_SYSFS + select HAVE_PWM + select IWMMXT + select PXA27x help Say Y here if you intend to run this kernel on a MIO A701. Currently there is only basic support @@ -326,9 +326,9 @@ config MACH_MIOA701 config PXA_EZX bool "Motorola EZX Platform" - select PXA27x - select IWMMXT select HAVE_PWM + select IWMMXT + select PXA27x config MACH_EZX_A780 bool "Motorola EZX A780" @@ -393,9 +393,9 @@ config MACH_PALMT5 bool "Palm Tungsten|T5" default y depends on ARCH_PXA_PALM - select PXA27x select IWMMXT select MACH_PALM27X + select PXA27x help Say Y here if you intend to run this kernel on a Palm Tungsten|T5 handheld computer. @@ -404,9 +404,9 @@ config MACH_PALMTX bool "Palm T|X" default y depends on ARCH_PXA_PALM - select PXA27x select IWMMXT select MACH_PALM27X + select PXA27x help Say Y here if you intend to run this kernel on a Palm T|X handheld computer. @@ -415,9 +415,9 @@ config MACH_PALMZ72 bool "Palm Zire 72" default y depends on ARCH_PXA_PALM - select PXA27x select IWMMXT select MACH_PALM27X + select PXA27x help Say Y here if you intend to run this kernel on Palm Zire 72 handheld computer. @@ -426,9 +426,9 @@ config MACH_PALMLD bool "Palm LifeDrive" default y depends on ARCH_PXA_PALM - select PXA27x select IWMMXT select MACH_PALM27X + select PXA27x help Say Y here if you intend to run this kernel on a Palm LifeDrive handheld computer. @@ -441,10 +441,10 @@ config MACH_CENTRO bool "Palm Centro 685 (GSM)" default y depends on ARCH_PXA_PALM - select MACH_PALM27X - select PXA27x select IWMMXT + select MACH_PALM27X select PALM_TREO + select PXA27x help Say Y here if you intend to run this kernel on Palm Centro 685 (GSM) smartphone. @@ -453,37 +453,37 @@ config MACH_TREO680 bool "Palm Treo 680" default y depends on ARCH_PXA_PALM - select MACH_PALM27X - select PXA27x select IWMMXT + select MACH_PALM27X select PALM_TREO + select PXA27x help Say Y here if you intend to run this kernel on Palm Treo 680 smartphone. config MACH_RAUMFELD_RC bool "Raumfeld Controller" - select PXA3xx select CPU_PXA300 - select POWER_SUPPLY select HAVE_PWM + select POWER_SUPPLY + select PXA3xx config MACH_RAUMFELD_CONNECTOR bool "Raumfeld Connector" + select CPU_PXA300 select POWER_SUPPLY select PXA3xx - select CPU_PXA300 config MACH_RAUMFELD_SPEAKER bool "Raumfeld Speaker" + select CPU_PXA300 select POWER_SUPPLY select PXA3xx - select CPU_PXA300 config PXA_SHARPSL bool "SHARP Zaurus SL-5600, SL-C7xx and SL-Cxx00 Models" - select SHARP_SCOOP select SHARP_PARAM + select SHARP_SCOOP help Say Y here if you intend to run this kernel on a Sharp Zaurus SL-5600 (Poodle), SL-C700 (Corgi), @@ -526,11 +526,11 @@ config MACH_HUSKY config MACH_AKITA bool "Enable Sharp SL-1000 (Akita) Support" depends on PXA_SHARPSL - select PXA27x - select PXA_SHARP_Cxx00 - select MACH_SPITZ select I2C select I2C_PXA + select MACH_SPITZ + select PXA27x + select PXA_SHARP_Cxx00 config MACH_SPITZ bool "Enable Sharp Zaurus SL-3000 (Spitz) Support" @@ -575,8 +575,8 @@ config MACH_ICONTROL config ARCH_PXA_ESERIES bool "PXA based Toshiba e-series PDAs" - select PXA25x select FB_W100 + select PXA25x config MACH_E330 bool "Toshiba e330" @@ -628,8 +628,8 @@ config MACH_E800 config MACH_ZIPIT2 bool "Zipit Z2 Handheld" - select PXA27x select HAVE_PWM + select PXA27x endif endmenu @@ -720,9 +720,9 @@ config SHARPSL_PM config SHARPSL_PM_MAX1111 bool select HWMON + select SENSORS_MAX1111 select SPI select SPI_MASTER - select SENSORS_MAX1111 config PXA_HAVE_ISA_IRQS bool diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c index fc3afc7cd366..a103c8ffea9f 100644 --- a/arch/arm/mach-pxa/cm-x2xx.c +++ b/arch/arm/mach-pxa/cm-x2xx.c @@ -22,6 +22,7 @@ #include <asm/mach/map.h> #include <mach/pxa25x.h> +#undef GPIO24_SSP1_SFRM #include <mach/pxa27x.h> #include <mach/audio.h> #include <linux/platform_data/video-pxafb.h> diff --git a/arch/arm/mach-pxa/palmte2.c b/arch/arm/mach-pxa/palmte2.c index 997e6da9a9c4..32e0d7998355 100644 --- a/arch/arm/mach-pxa/palmte2.c +++ b/arch/arm/mach-pxa/palmte2.c @@ -105,6 +105,7 @@ static struct pxamci_platform_data palmte2_mci_platform_data = { .gpio_power = GPIO_NR_PALMTE2_SD_POWER, }; +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) /****************************************************************************** * GPIO keys ******************************************************************************/ @@ -132,6 +133,7 @@ static struct platform_device palmte2_pxa_keys = { .platform_data = &palmte2_pxa_keys_data, }, }; +#endif /****************************************************************************** * Backlight diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c index 5a406f794798..ec55c575ed19 100644 --- a/arch/arm/mach-pxa/sharpsl_pm.c +++ b/arch/arm/mach-pxa/sharpsl_pm.c @@ -55,7 +55,6 @@ #ifdef CONFIG_PM static int sharpsl_off_charge_battery(void); static int sharpsl_check_battery_voltage(void); -static int sharpsl_fatal_check(void); #endif static int sharpsl_check_battery_temp(void); static int sharpsl_ac_check(void); @@ -686,53 +685,6 @@ static int corgi_pxa_pm_enter(suspend_state_t state) return 0; } -/* - * Check for fatal battery errors - * Fatal returns -1 - */ -static int sharpsl_fatal_check(void) -{ - int buff[5], temp, i, acin; - - dev_dbg(sharpsl_pm.dev, "sharpsl_fatal_check entered\n"); - - /* Check AC-Adapter */ - acin = sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN); - - if (acin && (sharpsl_pm.charge_mode == CHRG_ON)) { - sharpsl_pm.machinfo->charge(0); - udelay(100); - sharpsl_pm.machinfo->discharge(1); /* enable discharge */ - mdelay(SHARPSL_WAIT_DISCHARGE_ON); - } - - if (sharpsl_pm.machinfo->discharge1) - sharpsl_pm.machinfo->discharge1(1); - - /* Check battery : check inserting battery ? */ - for (i = 0; i < 5; i++) { - buff[i] = sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT); - mdelay(SHARPSL_CHECK_BATTERY_WAIT_TIME_VOLT); - } - - if (sharpsl_pm.machinfo->discharge1) - sharpsl_pm.machinfo->discharge1(0); - - if (acin && (sharpsl_pm.charge_mode == CHRG_ON)) { - udelay(100); - sharpsl_pm.machinfo->charge(1); - sharpsl_pm.machinfo->discharge(0); - } - - temp = get_select_val(buff); - dev_dbg(sharpsl_pm.dev, "sharpsl_fatal_check: acin: %d, discharge voltage: %d, no discharge: %ld\n", acin, temp, sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT)); - - if ((acin && (temp < sharpsl_pm.machinfo->fatal_acin_volt)) || - (!acin && (temp < sharpsl_pm.machinfo->fatal_noacin_volt))) - return -1; - return 0; -} - static int sharpsl_off_charge_error(void) { dev_err(sharpsl_pm.dev, "Offline Charger: Error occurred.\n"); diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c index 392412ce4dac..c773e4dded64 100644 --- a/arch/arm/mach-pxa/viper.c +++ b/arch/arm/mach-pxa/viper.c @@ -768,8 +768,7 @@ static unsigned long viper_tpm; static int __init viper_tpm_setup(char *str) { - strict_strtoul(str, 10, &viper_tpm); - return 1; + return strict_strtoul(str, 10, &viper_tpm) >= 0; } __setup("tpm=", viper_tpm_setup); diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig index c593be428b8f..14c1d47e1abf 100644 --- a/arch/arm/mach-realview/Kconfig +++ b/arch/arm/mach-realview/Kconfig @@ -21,8 +21,8 @@ config REALVIEW_EB_A9MP config REALVIEW_EB_ARM11MP bool "Support ARM11MPCore Tile" depends on MACH_REALVIEW_EB - select CPU_V6K select ARCH_HAS_BARRIERS if SMP + select CPU_V6K select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 help @@ -40,12 +40,12 @@ config REALVIEW_EB_ARM11MP_REVB config MACH_REALVIEW_PB11MP bool "Support RealView(R) Platform Baseboard for ARM11MPCore" - select CPU_V6K + select ARCH_HAS_BARRIERS if SMP select ARM_GIC + select CPU_V6K select HAVE_PATA_PLATFORM select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 - select ARCH_HAS_BARRIERS if SMP help Include support for the ARM(R) RealView(R) Platform Baseboard for the ARM11MPCore. This platform has an on-board ARM11MPCore and has @@ -54,8 +54,8 @@ config MACH_REALVIEW_PB11MP # ARMv6 CPU without K extensions, but does have the new exclusive ops config MACH_REALVIEW_PB1176 bool "Support RealView(R) Platform Baseboard for ARM1176JZF-S" - select CPU_V6 select ARM_GIC + select CPU_V6 select HAVE_TCM select MIGHT_HAVE_CACHE_L2X0 help @@ -73,8 +73,8 @@ config REALVIEW_PB1176_SECURE_FLASH config MACH_REALVIEW_PBA8 bool "Support RealView(R) Platform Baseboard for Cortex(tm)-A8 platform" - select CPU_V7 select ARM_GIC + select CPU_V7 select HAVE_PATA_PLATFORM help Include support for the ARM(R) RealView Platform Baseboard for @@ -83,11 +83,11 @@ config MACH_REALVIEW_PBA8 config MACH_REALVIEW_PBX bool "Support RealView(R) Platform Baseboard Explore" + select ARCH_SPARSEMEM_ENABLE if CPU_V7 && !REALVIEW_HIGH_PHYS_OFFSET select ARM_GIC select HAVE_PATA_PLATFORM select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 - select ARCH_SPARSEMEM_ENABLE if CPU_V7 && !REALVIEW_HIGH_PHYS_OFFSET select ZONE_DMA if SPARSEMEM help Include support for the ARM(R) RealView(R) Platform Baseboard diff --git a/arch/arm/mach-rpc/ecard.c b/arch/arm/mach-rpc/ecard.c index b91bc87b3dcf..fcb1d59f7aec 100644 --- a/arch/arm/mach-rpc/ecard.c +++ b/arch/arm/mach-rpc/ecard.c @@ -960,7 +960,9 @@ static int __init ecard_probe(int slot, unsigned irq, card_type_t type) *ecp = ec; slot_to_expcard[slot] = ec; - device_register(&ec->dev); + rc = device_register(&ec->dev); + if (rc) + goto nodev; return 0; diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig index c5256f4e90bb..495f6928cbaa 100644 --- a/arch/arm/mach-s3c2412/Kconfig +++ b/arch/arm/mach-s3c2412/Kconfig @@ -7,7 +7,7 @@ config S3C2412_CPUFREQ bool depends on CPU_FREQ_S3C24XX && CPU_S3C2412 - select S3C2412_IOTIMING default y + select S3C2412_IOTIMING help CPU Frequency scaling support for S3C2412 and S3C2413 SoC CPUs. diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig index ece7a10fe3c6..a4d7fd27bec5 100644 --- a/arch/arm/mach-s3c2440/Kconfig +++ b/arch/arm/mach-s3c2440/Kconfig @@ -5,8 +5,8 @@ config S3C2440_CPUFREQ bool "S3C2440/S3C2442 CPU Frequency scaling support" depends on CPU_FREQ_S3C24XX && (CPU_S3C2440 || CPU_S3C2442) - select S3C2410_CPUFREQ_UTILS default y + select S3C2410_CPUFREQ_UTILS help CPU Frequency scaling support for S3C2440 and S3C2442 SoC CPUs. diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig index d56b0f7f2b20..2b6cb5f29c2d 100644 --- a/arch/arm/mach-s3c24xx/Kconfig +++ b/arch/arm/mach-s3c24xx/Kconfig @@ -17,10 +17,10 @@ config CPU_S3C2410 bool "SAMSUNG S3C2410" default y select CPU_ARM920T - select S3C2410_CLOCK select CPU_LLSERIAL_S3C2410 - select S3C2410_PM if PM + select S3C2410_CLOCK select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX + select S3C2410_PM if PM help Support for S3C2410 and S3C2410A family from the S3C24XX line of Samsung Mobile CPUs. @@ -30,8 +30,8 @@ config CPU_S3C2412 depends on ARCH_S3C24XX select CPU_ARM926T select CPU_LLSERIAL_S3C2440 - select S3C2412_PM if PM select S3C2412_DMA if S3C24XX_DMA + select S3C2412_PM if PM help Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line @@ -40,10 +40,10 @@ config CPU_S3C2416 depends on ARCH_S3C24XX select CPU_ARM926T select CPU_LLSERIAL_S3C2440 - select SAMSUNG_CLKSRC + select S3C2416_PM if PM select S3C2443_COMMON select S3C2443_DMA if S3C24XX_DMA - select S3C2416_PM if PM + select SAMSUNG_CLKSRC help Support for the S3C2416 SoC from the S3C24XX line @@ -75,9 +75,9 @@ config CPU_S3C2443 depends on ARCH_S3C24XX select CPU_ARM920T select CPU_LLSERIAL_S3C2440 - select SAMSUNG_CLKSRC select S3C2443_COMMON select S3C2443_DMA if S3C24XX_DMA + select SAMSUNG_CLKSRC help Support for the S3C2443 SoC from the S3C24XX line @@ -156,16 +156,16 @@ config MACH_AML_M5900 config ARCH_BAST bool "Simtec Electronics BAST (EB2410ITX)" + select ISA + select MACH_BAST_IDE select S3C2410_IOTIMING if S3C2410_CPUFREQ - select S3C24XX_SIMTEC_PM if PM + select S3C24XX_DCLK select S3C24XX_SIMTEC_NOR + select S3C24XX_SIMTEC_PM if PM select S3C24XX_SIMTEC_USB - select MACH_BAST_IDE - select S3C24XX_DCLK - select ISA select S3C_DEV_HWMON - select S3C_DEV_USB_HOST select S3C_DEV_NAND + select S3C_DEV_USB_HOST help Say Y here if you are using the Simtec Electronics EB2410ITX development board (also known as BAST) @@ -181,9 +181,9 @@ config BAST_PC104_IRQ config ARCH_H1940 bool "IPAQ H1940" select PM_H1940 if PM - select S3C_DEV_USB_HOST - select S3C_DEV_NAND select S3C24XX_SETUP_TS + select S3C_DEV_NAND + select S3C_DEV_USB_HOST help Say Y here if you are using the HP IPAQ H1940 @@ -203,23 +203,23 @@ config PM_H1940 config MACH_N30 bool "Acer N30 family" select MACH_N35 - select S3C_DEV_USB_HOST select S3C_DEV_NAND + select S3C_DEV_USB_HOST help Say Y here if you want suppt for the Acer N30, Acer N35, Navman PiN570, Yakumo AlphaX or Airis NC05 PDAs. config MACH_OTOM bool "NexVision OTOM Board" - select S3C_DEV_USB_HOST select S3C_DEV_NAND + select S3C_DEV_USB_HOST help Say Y here if you are using the Nex Vision OTOM board config MACH_QT2410 bool "QT2410" - select S3C_DEV_USB_HOST select S3C_DEV_NAND + select S3C_DEV_USB_HOST help Say Y here if you are using the Armzone QT2410 @@ -239,12 +239,12 @@ config MACH_TCT_HAMMER config MACH_VR1000 bool "Thorcom VR1000" - select S3C24XX_SIMTEC_PM if PM + select MACH_BAST_IDE select S3C24XX_DCLK select S3C24XX_SIMTEC_NOR - select MACH_BAST_IDE - select S3C_DEV_USB_HOST + select S3C24XX_SIMTEC_PM if PM select S3C24XX_SIMTEC_USB + select S3C_DEV_USB_HOST help Say Y here if you are using the Thorcom VR1000 board. @@ -285,8 +285,8 @@ comment "S3C2412 Boards" config MACH_JIVE bool "Logitech Jive" - select S3C_DEV_USB_HOST select S3C_DEV_NAND + select S3C_DEV_USB_HOST help Say Y here if you are using the Logitech Jive. @@ -314,15 +314,15 @@ config MACH_SMDK2413 bool "SMDK2413" select MACH_S3C2413 select S3C24XX_SMDK - select S3C_DEV_USB_HOST select S3C_DEV_NAND + select S3C_DEV_USB_HOST help Say Y here if you are using an SMDK2413 config MACH_VSTMS bool "VMSTMS" - select S3C_DEV_USB_HOST select S3C_DEV_NAND + select S3C_DEV_USB_HOST help Say Y here if you are using an VSTMS board @@ -351,13 +351,13 @@ comment "S3C2416 Boards" config MACH_SMDK2416 bool "SMDK2416" + select S3C2416_SETUP_SDHCI select S3C24XX_SMDK select S3C_DEV_FB select S3C_DEV_HSMMC select S3C_DEV_HSMMC1 select S3C_DEV_NAND select S3C_DEV_USB_HOST - select S3C2416_SETUP_SDHCI help Say Y here if you are using an SMDK2416 @@ -379,11 +379,11 @@ comment "S3C2440 Boards" config MACH_ANUBIS bool "Simtec Electronics ANUBIS" - select S3C24XX_DCLK - select S3C24XX_SIMTEC_PM if PM select HAVE_PATA_PLATFORM - select S3C24XX_GPIO_EXTRA64 select S3C2440_XTAL_12000000 + select S3C24XX_DCLK + select S3C24XX_GPIO_EXTRA64 + select S3C24XX_SIMTEC_PM if PM select S3C_DEV_USB_HOST help Say Y here if you are using the Simtec Electronics ANUBIS @@ -391,18 +391,18 @@ config MACH_ANUBIS config MACH_AT2440EVB bool "Avantech AT2440EVB development board" - select S3C_DEV_USB_HOST select S3C_DEV_NAND + select S3C_DEV_USB_HOST help Say Y here if you are using the AT2440EVB development board config MACH_MINI2440 bool "MINI2440 development board" select EEPROM_AT24 - select NEW_LEDS select LEDS_CLASS select LEDS_TRIGGER select LEDS_TRIGGER_BACKLIGHT + select NEW_LEDS select S3C_DEV_NAND select S3C_DEV_USB_HOST help @@ -412,20 +412,20 @@ config MACH_MINI2440 config MACH_NEXCODER_2440 bool "NexVision NEXCODER 2440 Light Board" select S3C2440_XTAL_12000000 - select S3C_DEV_USB_HOST select S3C_DEV_NAND + select S3C_DEV_USB_HOST help Say Y here if you are using the Nex Vision NEXCODER 2440 Light Board config MACH_OSIRIS bool "Simtec IM2440D20 (OSIRIS) module" + select S3C2410_IOTIMING if S3C2440_CPUFREQ + select S3C2440_XTAL_12000000 select S3C24XX_DCLK - select S3C24XX_SIMTEC_PM if PM select S3C24XX_GPIO_EXTRA128 - select S3C2440_XTAL_12000000 - select S3C2410_IOTIMING if S3C2440_CPUFREQ - select S3C_DEV_USB_HOST + select S3C24XX_SIMTEC_PM if PM select S3C_DEV_NAND + select S3C_DEV_USB_HOST help Say Y here if you are using the Simtec IM2440D20 module, also known as the Osiris. @@ -445,8 +445,8 @@ config MACH_OSIRIS_DVS config MACH_RX3715 bool "HP iPAQ rx3715" - select S3C2440_XTAL_16934400 select PM_H1940 if PM + select S3C2440_XTAL_16934400 select S3C_DEV_NAND help Say Y here if you are using the HP iPAQ rx3715. @@ -455,8 +455,8 @@ config ARCH_S3C2440 bool "SMDK2440" select S3C2440_XTAL_16934400 select S3C24XX_SMDK - select S3C_DEV_USB_HOST select S3C_DEV_NAND + select S3C_DEV_USB_HOST help Say Y here if you are using the SMDK2440. @@ -478,11 +478,11 @@ comment "S3C2442 Boards" config MACH_NEO1973_GTA02 bool "Openmoko GTA02 / Freerunner phone" + select I2C + select MACH_NEO1973 select MFD_PCF50633 select PCF50633_GPIO - select I2C select POWER_SUPPLY - select MACH_NEO1973 select S3C24XX_PWM select S3C_DEV_USB_HOST help @@ -490,13 +490,13 @@ config MACH_NEO1973_GTA02 config MACH_RX1950 bool "HP iPAQ rx1950" - select S3C24XX_DCLK - select PM_H1940 if PM select I2C - select S3C24XX_PWM - select S3C_DEV_NAND + select PM_H1940 if PM select S3C2410_IOTIMING if S3C2440_CPUFREQ select S3C2440_XTAL_16934400 + select S3C24XX_DCLK + select S3C24XX_PWM + select S3C_DEV_NAND help Say Y here if you're using HP iPAQ rx1950 diff --git a/arch/arm/mach-s3c24xx/clock-s3c2440.c b/arch/arm/mach-s3c24xx/clock-s3c2440.c index 749220f91a70..4407b1730539 100644 --- a/arch/arm/mach-s3c24xx/clock-s3c2440.c +++ b/arch/arm/mach-s3c24xx/clock-s3c2440.c @@ -163,7 +163,7 @@ static struct clk_lookup s3c2440_clk_lookup[] = { CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n), }; -static int s3c2440_clk_add(struct device *dev, struct subsys_interface *sif) +static int __init_refok s3c2440_clk_add(struct device *dev, struct subsys_interface *sif) { struct clk *clock_upll; struct clk *clock_h; diff --git a/arch/arm/mach-s3c24xx/irq-s3c2416.c b/arch/arm/mach-s3c24xx/irq-s3c2416.c index 23ec97370f32..ff141b0af26b 100644 --- a/arch/arm/mach-s3c24xx/irq-s3c2416.c +++ b/arch/arm/mach-s3c24xx/irq-s3c2416.c @@ -232,7 +232,7 @@ struct irq_chip s3c2416_irq_second = { /* IRQ initialisation code */ -static int __init s3c2416_add_sub(unsigned int base, +static int s3c2416_add_sub(unsigned int base, void (*demux)(unsigned int, struct irq_desc *), struct irq_chip *chip, @@ -251,7 +251,7 @@ static int __init s3c2416_add_sub(unsigned int base, return 0; } -static void __init s3c2416_irq_add_second(void) +static void s3c2416_irq_add_second(void) { unsigned long pend; unsigned long last; @@ -287,7 +287,7 @@ static void __init s3c2416_irq_add_second(void) } } -static int __init s3c2416_irq_add(struct device *dev, +static int s3c2416_irq_add(struct device *dev, struct subsys_interface *sif) { printk(KERN_INFO "S3C2416: IRQ Support\n"); diff --git a/arch/arm/mach-s3c24xx/irq-s3c2443.c b/arch/arm/mach-s3c24xx/irq-s3c2443.c index ac2829f56d12..5e69109c0928 100644 --- a/arch/arm/mach-s3c24xx/irq-s3c2443.c +++ b/arch/arm/mach-s3c24xx/irq-s3c2443.c @@ -222,7 +222,7 @@ static struct irq_chip s3c2443_irq_cam = { /* IRQ initialisation code */ -static int __init s3c2443_add_sub(unsigned int base, +static int s3c2443_add_sub(unsigned int base, void (*demux)(unsigned int, struct irq_desc *), struct irq_chip *chip, @@ -241,7 +241,7 @@ static int __init s3c2443_add_sub(unsigned int base, return 0; } -static int __init s3c2443_irq_add(struct device *dev, +static int s3c2443_irq_add(struct device *dev, struct subsys_interface *sif) { printk("S3C2443: IRQ Support\n"); diff --git a/arch/arm/mach-s3c24xx/mach-smdk2416.c b/arch/arm/mach-s3c24xx/mach-smdk2416.c index db2787aa1e5e..f30d7fccbfee 100644 --- a/arch/arm/mach-s3c24xx/mach-smdk2416.c +++ b/arch/arm/mach-s3c24xx/mach-smdk2416.c @@ -29,6 +29,7 @@ #include <asm/mach/map.h> #include <asm/mach/irq.h> +#include <video/samsung_fimd.h> #include <mach/hardware.h> #include <asm/irq.h> #include <asm/mach-types.h> @@ -52,7 +53,6 @@ #include <linux/platform_data/usb-s3c2410_udc.h> #include <linux/platform_data/s3c-hsudc.h> -#include <plat/regs-fb-v4.h> #include <plat/fb.h> #include <plat/common-smdk.h> diff --git a/arch/arm/mach-s3c24xx/s3c2416.c b/arch/arm/mach-s3c24xx/s3c2416.c index ed5a95ece9eb..77ee0b732237 100644 --- a/arch/arm/mach-s3c24xx/s3c2416.c +++ b/arch/arm/mach-s3c24xx/s3c2416.c @@ -61,6 +61,7 @@ #include <plat/nand-core.h> #include <plat/adc-core.h> #include <plat/rtc-core.h> +#include <plat/spi-core.h> static struct map_desc s3c2416_iodesc[] __initdata = { IODESC_ENT(WATCHDOG), @@ -132,6 +133,7 @@ void __init s3c2416_map_io(void) /* initialize device information early */ s3c2416_default_sdhci0(); s3c2416_default_sdhci1(); + s3c64xx_spi_setname("s3c2443-spi"); iotable_init(s3c2416_iodesc, ARRAY_SIZE(s3c2416_iodesc)); } diff --git a/arch/arm/mach-s3c24xx/s3c2443.c b/arch/arm/mach-s3c24xx/s3c2443.c index ab648ad8fa50..165b6a6b3daa 100644 --- a/arch/arm/mach-s3c24xx/s3c2443.c +++ b/arch/arm/mach-s3c24xx/s3c2443.c @@ -43,6 +43,7 @@ #include <plat/nand-core.h> #include <plat/adc-core.h> #include <plat/rtc-core.h> +#include <plat/spi-core.h> static struct map_desc s3c2443_iodesc[] __initdata = { IODESC_ENT(WATCHDOG), @@ -100,6 +101,9 @@ void __init s3c2443_map_io(void) s3c24xx_gpiocfg_default.set_pull = s3c2443_gpio_setpull; s3c24xx_gpiocfg_default.get_pull = s3c2443_gpio_getpull; + /* initialize device information early */ + s3c64xx_spi_setname("s3c2443-spi"); + iotable_init(s3c2443_iodesc, ARRAY_SIZE(s3c2443_iodesc)); } diff --git a/arch/arm/mach-s3c24xx/simtec-usb.c b/arch/arm/mach-s3c24xx/simtec-usb.c index 17f8356177c1..ddf7a3c743ac 100644 --- a/arch/arm/mach-s3c24xx/simtec-usb.c +++ b/arch/arm/mach-s3c24xx/simtec-usb.c @@ -104,7 +104,7 @@ static struct s3c2410_hcd_info usb_simtec_info __initdata = { }; -int usb_simtec_init(void) +int __init usb_simtec_init(void) { int ret; diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig index 06ca1cd4cae2..63e7ae3ee9e6 100644 --- a/arch/arm/mach-s3c64xx/Kconfig +++ b/arch/arm/mach-s3c64xx/Kconfig @@ -7,9 +7,9 @@ config PLAT_S3C64XX bool depends on ARCH_S3C64XX - select SAMSUNG_WAKEMASK - select PM_GENERIC_DOMAINS default y + select PM_GENERIC_DOMAINS + select SAMSUNG_WAKEMASK help Base platform code for any Samsung S3C64XX device @@ -31,8 +31,8 @@ config S3C64XX_DMA select S3C_DMA config S3C64XX_SETUP_SDHCI - select S3C64XX_SETUP_SDHCI_GPIO bool + select S3C64XX_SETUP_SDHCI_GPIO help Internal configuration for default SDHCI setup for S3C6400 and S3C6410 SoCs. @@ -93,9 +93,9 @@ config S3C64XX_SETUP_USB_PHY config MACH_SMDK6400 bool "SMDK6400" select CPU_S3C6400 + select S3C64XX_SETUP_SDHCI select S3C_DEV_HSMMC select S3C_DEV_NAND - select S3C64XX_SETUP_SDHCI help Machine support for the Samsung SMDK6400 @@ -104,21 +104,21 @@ config MACH_SMDK6400 config MACH_ANW6410 bool "A&W6410" select CPU_S3C6410 - select S3C_DEV_FB select S3C64XX_SETUP_FB_24BPP + select S3C_DEV_FB help Machine support for the A&W6410 config MACH_MINI6410 bool "MINI6410" select CPU_S3C6410 + select S3C64XX_SETUP_FB_24BPP + select S3C64XX_SETUP_SDHCI + select S3C_DEV_FB select S3C_DEV_HSMMC select S3C_DEV_HSMMC1 - select S3C64XX_SETUP_SDHCI - select S3C_DEV_USB_HOST select S3C_DEV_NAND - select S3C_DEV_FB - select S3C64XX_SETUP_FB_24BPP + select S3C_DEV_USB_HOST select SAMSUNG_DEV_ADC select SAMSUNG_DEV_TS help @@ -127,42 +127,42 @@ config MACH_MINI6410 config MACH_REAL6410 bool "REAL6410" select CPU_S3C6410 - select S3C_DEV_HSMMC - select S3C_DEV_HSMMC1 + select S3C64XX_SETUP_FB_24BPP select S3C64XX_SETUP_SDHCI select S3C_DEV_FB - select S3C64XX_SETUP_FB_24BPP + select S3C_DEV_HSMMC + select S3C_DEV_HSMMC1 select S3C_DEV_NAND + select S3C_DEV_USB_HOST select SAMSUNG_DEV_ADC select SAMSUNG_DEV_TS - select S3C_DEV_USB_HOST help Machine support for the CoreWind REAL6410 config MACH_SMDK6410 bool "SMDK6410" select CPU_S3C6410 - select SAMSUNG_DEV_ADC + select HAVE_S3C2410_WATCHDOG if WATCHDOG + select S3C64XX_SETUP_FB_24BPP + select S3C64XX_SETUP_I2C1 + select S3C64XX_SETUP_IDE + select S3C64XX_SETUP_KEYPAD + select S3C64XX_SETUP_SDHCI + select S3C64XX_SETUP_USB_PHY + select S3C_DEV_FB select S3C_DEV_HSMMC select S3C_DEV_HSMMC1 select S3C_DEV_I2C1 - select SAMSUNG_DEV_IDE - select S3C_DEV_FB select S3C_DEV_RTC - select SAMSUNG_DEV_TS select S3C_DEV_USB_HOST select S3C_DEV_USB_HSOTG select S3C_DEV_WDT + select SAMSUNG_DEV_ADC select SAMSUNG_DEV_BACKLIGHT + select SAMSUNG_DEV_IDE select SAMSUNG_DEV_KEYPAD select SAMSUNG_DEV_PWM - select HAVE_S3C2410_WATCHDOG if WATCHDOG - select S3C64XX_SETUP_SDHCI - select S3C64XX_SETUP_I2C1 - select S3C64XX_SETUP_IDE - select S3C64XX_SETUP_FB_24BPP - select S3C64XX_SETUP_KEYPAD - select S3C64XX_SETUP_USB_PHY + select SAMSUNG_DEV_TS help Machine support for the Samsung SMDK6410 @@ -198,13 +198,13 @@ endchoice config SMDK6410_WM1190_EV1 bool "Support Wolfson Microelectronics 1190-EV1 PMIC card" depends on MACH_SMDK6410 - select REGULATOR - select REGULATOR_WM8350 - select SAMSUNG_GPIO_EXTRA64 - select MFD_WM8350_I2C select MFD_WM8350_CONFIG_MODE_0 select MFD_WM8350_CONFIG_MODE_3 + select MFD_WM8350_I2C select MFD_WM8352_CONFIG_MODE_0 + select REGULATOR + select REGULATOR_WM8350 + select SAMSUNG_GPIO_EXTRA64 help The Wolfson Microelectronics 1190-EV1 is a WM835x based PMIC and audio daughtercard for the Samsung SMDK6410 reference @@ -216,11 +216,11 @@ config SMDK6410_WM1190_EV1 config SMDK6410_WM1192_EV1 bool "Support Wolfson Microelectronics 1192-EV1 PMIC card" depends on MACH_SMDK6410 + select MFD_WM831X + select MFD_WM831X_I2C select REGULATOR select REGULATOR_WM831X select SAMSUNG_GPIO_EXTRA64 - select MFD_WM831X - select MFD_WM831X_I2C help The Wolfson Microelectronics 1192-EV1 is a WM831x based PMIC daughtercard for the Samsung SMDK6410 reference platform. @@ -232,19 +232,19 @@ config SMDK6410_WM1192_EV1 config MACH_NCP bool "NCP" select CPU_S3C6410 - select S3C_DEV_I2C1 - select S3C_DEV_HSMMC1 select S3C64XX_SETUP_I2C1 + select S3C_DEV_HSMMC1 + select S3C_DEV_I2C1 help Machine support for the Samsung NCP config MACH_HMT bool "Airgoo HMT" select CPU_S3C6410 + select S3C64XX_SETUP_FB_24BPP select S3C_DEV_FB select S3C_DEV_NAND select S3C_DEV_USB_HOST - select S3C64XX_SETUP_FB_24BPP select SAMSUNG_DEV_PWM help Machine support for the Airgoo HMT @@ -252,17 +252,17 @@ config MACH_HMT config MACH_SMARTQ bool select CPU_S3C6410 + select S3C64XX_SETUP_FB_24BPP + select S3C64XX_SETUP_SDHCI + select S3C64XX_SETUP_USB_PHY + select S3C_DEV_FB select S3C_DEV_HSMMC select S3C_DEV_HSMMC1 select S3C_DEV_HSMMC2 - select S3C_DEV_FB select S3C_DEV_HWMON select S3C_DEV_RTC - select S3C_DEV_USB_HSOTG select S3C_DEV_USB_HOST - select S3C64XX_SETUP_SDHCI - select S3C64XX_SETUP_FB_24BPP - select S3C64XX_SETUP_USB_PHY + select S3C_DEV_USB_HSOTG select SAMSUNG_DEV_ADC select SAMSUNG_DEV_PWM select SAMSUNG_DEV_TS @@ -284,26 +284,26 @@ config MACH_SMARTQ7 config MACH_WLF_CRAGG_6410 bool "Wolfson Cragganmore 6410" select CPU_S3C6410 - select S3C64XX_SETUP_SDHCI + select I2C + select LEDS_GPIO_REGISTER + select S3C64XX_DEV_SPI0 + select S3C64XX_SETUP_FB_24BPP select S3C64XX_SETUP_I2C1 select S3C64XX_SETUP_IDE - select S3C64XX_SETUP_FB_24BPP select S3C64XX_SETUP_KEYPAD + select S3C64XX_SETUP_SDHCI select S3C64XX_SETUP_SPI select S3C64XX_SETUP_USB_PHY - select SAMSUNG_DEV_ADC - select SAMSUNG_DEV_KEYPAD - select S3C_DEV_USB_HOST - select S3C_DEV_USB_HSOTG select S3C_DEV_HSMMC select S3C_DEV_HSMMC1 select S3C_DEV_HSMMC2 select S3C_DEV_I2C1 - select S3C_DEV_WDT select S3C_DEV_RTC - select S3C64XX_DEV_SPI0 + select S3C_DEV_USB_HOST + select S3C_DEV_USB_HSOTG + select S3C_DEV_WDT + select SAMSUNG_DEV_ADC + select SAMSUNG_DEV_KEYPAD select SAMSUNG_GPIO_EXTRA128 - select I2C - select LEDS_GPIO_REGISTER help Machine support for the Wolfson Cragganmore S3C6410 variant. diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c index 15c58dfc4584..99e82ac81b69 100644 --- a/arch/arm/mach-s3c64xx/mach-anw6410.c +++ b/arch/arm/mach-s3c64xx/mach-anw6410.c @@ -29,6 +29,7 @@ #include <linux/dm9000.h> #include <video/platform_lcd.h> +#include <video/samsung_fimd.h> #include <asm/hardware/vic.h> #include <asm/mach/arch.h> @@ -44,7 +45,6 @@ #include <plat/regs-serial.h> #include <linux/platform_data/i2c-s3c2410.h> #include <plat/fb.h> -#include <plat/regs-fb-v4.h> #include <plat/clock.h> #include <plat/devs.h> diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c index 8b4d46706645..13b7eaa45fd0 100644 --- a/arch/arm/mach-s3c64xx/mach-crag6410.c +++ b/arch/arm/mach-s3c64xx/mach-crag6410.c @@ -46,6 +46,7 @@ #include <asm/mach/arch.h> #include <asm/mach-types.h> +#include <video/samsung_fimd.h> #include <mach/hardware.h> #include <mach/map.h> @@ -57,7 +58,6 @@ #include <mach/regs-gpio-memport.h> #include <plat/regs-serial.h> -#include <plat/regs-fb-v4.h> #include <plat/fb.h> #include <plat/sdhci.h> #include <plat/gpio-cfg.h> diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c index 02222b32b7d3..2b144893ddc4 100644 --- a/arch/arm/mach-s3c64xx/mach-hmt.c +++ b/arch/arm/mach-s3c64xx/mach-hmt.c @@ -26,6 +26,7 @@ #include <asm/mach/map.h> #include <asm/mach/irq.h> +#include <video/samsung_fimd.h> #include <mach/hardware.h> #include <mach/map.h> @@ -41,7 +42,6 @@ #include <plat/clock.h> #include <plat/devs.h> #include <plat/cpu.h> -#include <plat/regs-fb-v4.h> #include "common.h" diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c index 09311cc40115..07c349cca333 100644 --- a/arch/arm/mach-s3c64xx/mach-mini6410.c +++ b/arch/arm/mach-s3c64xx/mach-mini6410.c @@ -41,9 +41,9 @@ #include <linux/platform_data/mtd-nand-s3c2410.h> #include <plat/regs-serial.h> #include <linux/platform_data/touchscreen-s3c2410.h> -#include <plat/regs-fb-v4.h> #include <video/platform_lcd.h> +#include <video/samsung_fimd.h> #include "common.h" diff --git a/arch/arm/mach-s3c64xx/mach-ncp.c b/arch/arm/mach-s3c64xx/mach-ncp.c index 46ee88d16815..e5f9a79b535d 100644 --- a/arch/arm/mach-s3c64xx/mach-ncp.c +++ b/arch/arm/mach-s3c64xx/mach-ncp.c @@ -24,6 +24,7 @@ #include <linux/delay.h> #include <video/platform_lcd.h> +#include <video/samsung_fimd.h> #include <asm/hardware/vic.h> #include <asm/mach/arch.h> @@ -43,7 +44,6 @@ #include <plat/clock.h> #include <plat/devs.h> #include <plat/cpu.h> -#include <plat/regs-fb-v4.h> #include "common.h" diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c index 6daca203e72b..7476f7c722ab 100644 --- a/arch/arm/mach-s3c64xx/mach-real6410.c +++ b/arch/arm/mach-s3c64xx/mach-real6410.c @@ -42,9 +42,9 @@ #include <linux/platform_data/mtd-nand-s3c2410.h> #include <plat/regs-serial.h> #include <linux/platform_data/touchscreen-s3c2410.h> -#include <plat/regs-fb-v4.h> #include <video/platform_lcd.h> +#include <video/samsung_fimd.h> #include "common.h" diff --git a/arch/arm/mach-s3c64xx/mach-smartq5.c b/arch/arm/mach-s3c64xx/mach-smartq5.c index d6266d8b43c9..96d6da2b6b5f 100644 --- a/arch/arm/mach-s3c64xx/mach-smartq5.c +++ b/arch/arm/mach-s3c64xx/mach-smartq5.c @@ -21,6 +21,7 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> +#include <video/samsung_fimd.h> #include <mach/map.h> #include <mach/regs-gpio.h> @@ -28,7 +29,6 @@ #include <plat/devs.h> #include <plat/fb.h> #include <plat/gpio-cfg.h> -#include <plat/regs-fb-v4.h> #include "common.h" #include "mach-smartq.h" diff --git a/arch/arm/mach-s3c64xx/mach-smartq7.c b/arch/arm/mach-s3c64xx/mach-smartq7.c index 0957d2a980e1..7d1167bdc921 100644 --- a/arch/arm/mach-s3c64xx/mach-smartq7.c +++ b/arch/arm/mach-s3c64xx/mach-smartq7.c @@ -21,6 +21,7 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> +#include <video/samsung_fimd.h> #include <mach/map.h> #include <mach/regs-gpio.h> @@ -28,7 +29,6 @@ #include <plat/devs.h> #include <plat/fb.h> #include <plat/gpio-cfg.h> -#include <plat/regs-fb-v4.h> #include "common.h" #include "mach-smartq.h" diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c index 2547a8846472..da1a771a29e9 100644 --- a/arch/arm/mach-s3c64xx/mach-smdk6410.c +++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c @@ -43,6 +43,7 @@ #endif #include <video/platform_lcd.h> +#include <video/samsung_fimd.h> #include <asm/hardware/vic.h> #include <asm/mach/arch.h> @@ -72,7 +73,6 @@ #include <linux/platform_data/touchscreen-s3c2410.h> #include <plat/keypad.h> #include <plat/backlight.h> -#include <plat/regs-fb-v4.h> #include "common.h" diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig index c87f6108eeb1..e8742cb7ddd9 100644 --- a/arch/arm/mach-s5p64x0/Kconfig +++ b/arch/arm/mach-s5p64x0/Kconfig @@ -9,18 +9,18 @@ if ARCH_S5P64X0 config CPU_S5P6440 bool - select SAMSUNG_DMADEV select S5P_HRT select S5P_SLEEP if PM + select SAMSUNG_DMADEV select SAMSUNG_WAKEMASK if PM help Enable S5P6440 CPU support config CPU_S5P6450 bool - select SAMSUNG_DMADEV select S5P_HRT select S5P_SLEEP if PM + select SAMSUNG_DMADEV select SAMSUNG_WAKEMASK if PM help Enable S5P6450 CPU support @@ -52,19 +52,19 @@ config MACH_SMDK6440 bool "SMDK6440" select CPU_S5P6440 select S3C_DEV_FB - select S3C_DEV_I2C1 - select S3C_DEV_RTC - select S3C_DEV_WDT select S3C_DEV_HSMMC select S3C_DEV_HSMMC1 select S3C_DEV_HSMMC2 + select S3C_DEV_I2C1 + select S3C_DEV_RTC + select S3C_DEV_WDT + select S5P64X0_SETUP_FB_24BPP + select S5P64X0_SETUP_I2C1 + select S5P64X0_SETUP_SDHCI_GPIO select SAMSUNG_DEV_ADC select SAMSUNG_DEV_BACKLIGHT select SAMSUNG_DEV_PWM select SAMSUNG_DEV_TS - select S5P64X0_SETUP_FB_24BPP - select S5P64X0_SETUP_I2C1 - select S5P64X0_SETUP_SDHCI_GPIO help Machine support for the Samsung SMDK6440 @@ -72,19 +72,19 @@ config MACH_SMDK6450 bool "SMDK6450" select CPU_S5P6450 select S3C_DEV_FB - select S3C_DEV_I2C1 - select S3C_DEV_RTC - select S3C_DEV_WDT select S3C_DEV_HSMMC select S3C_DEV_HSMMC1 select S3C_DEV_HSMMC2 + select S3C_DEV_I2C1 + select S3C_DEV_RTC + select S3C_DEV_WDT + select S5P64X0_SETUP_FB_24BPP + select S5P64X0_SETUP_I2C1 + select S5P64X0_SETUP_SDHCI_GPIO select SAMSUNG_DEV_ADC select SAMSUNG_DEV_BACKLIGHT select SAMSUNG_DEV_PWM select SAMSUNG_DEV_TS - select S5P64X0_SETUP_FB_24BPP - select S5P64X0_SETUP_I2C1 - select S5P64X0_SETUP_SDHCI_GPIO help Machine support for the Samsung SMDK6450 diff --git a/arch/arm/mach-s5p64x0/common.c b/arch/arm/mach-s5p64x0/common.c index 6e6a0a9d6778..111e404a81fd 100644 --- a/arch/arm/mach-s5p64x0/common.c +++ b/arch/arm/mach-s5p64x0/common.c @@ -44,6 +44,7 @@ #include <plat/sdhci.h> #include <plat/adc-core.h> #include <plat/fb-core.h> +#include <plat/spi-core.h> #include <plat/gpio-cfg.h> #include <plat/regs-irqtype.h> #include <plat/regs-serial.h> @@ -179,6 +180,7 @@ void __init s5p6440_map_io(void) /* initialize any device information early */ s3c_adc_setname("s3c64xx-adc"); s3c_fb_setname("s5p64x0-fb"); + s3c64xx_spi_setname("s5p64x0-spi"); s5p64x0_default_sdhci0(); s5p64x0_default_sdhci1(); @@ -193,6 +195,7 @@ void __init s5p6450_map_io(void) /* initialize any device information early */ s3c_adc_setname("s3c64xx-adc"); s3c_fb_setname("s5p64x0-fb"); + s3c64xx_spi_setname("s5p64x0-spi"); s5p64x0_default_sdhci0(); s5p64x0_default_sdhci1(); diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c index dea78a848244..96ea1fe0ec94 100644 --- a/arch/arm/mach-s5p64x0/mach-smdk6440.c +++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c @@ -27,6 +27,7 @@ #include <linux/mmc/host.h> #include <video/platform_lcd.h> +#include <video/samsung_fimd.h> #include <asm/hardware/vic.h> #include <asm/mach/arch.h> @@ -52,7 +53,6 @@ #include <plat/s5p-time.h> #include <plat/backlight.h> #include <plat/fb.h> -#include <plat/regs-fb.h> #include <plat/sdhci.h> #include "common.h" diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c index 6f14fc729b8f..12748b6eaa7b 100644 --- a/arch/arm/mach-s5p64x0/mach-smdk6450.c +++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c @@ -27,6 +27,7 @@ #include <linux/mmc/host.h> #include <video/platform_lcd.h> +#include <video/samsung_fimd.h> #include <asm/hardware/vic.h> #include <asm/mach/arch.h> @@ -52,7 +53,6 @@ #include <plat/s5p-time.h> #include <plat/backlight.h> #include <plat/fb.h> -#include <plat/regs-fb.h> #include <plat/sdhci.h> #include "common.h" diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig index 75a26eaf2633..15170be97a74 100644 --- a/arch/arm/mach-s5pc100/Kconfig +++ b/arch/arm/mach-s5pc100/Kconfig @@ -60,12 +60,6 @@ config MACH_SMDKC100 select S3C_DEV_I2C1 select S3C_DEV_RTC select S3C_DEV_WDT - select SAMSUNG_DEV_ADC - select SAMSUNG_DEV_BACKLIGHT - select SAMSUNG_DEV_IDE - select SAMSUNG_DEV_KEYPAD - select SAMSUNG_DEV_PWM - select SAMSUNG_DEV_TS select S5PC100_SETUP_FB_24BPP select S5PC100_SETUP_I2C1 select S5PC100_SETUP_IDE @@ -74,6 +68,12 @@ config MACH_SMDKC100 select S5P_DEV_FIMC0 select S5P_DEV_FIMC1 select S5P_DEV_FIMC2 + select SAMSUNG_DEV_ADC + select SAMSUNG_DEV_BACKLIGHT + select SAMSUNG_DEV_IDE + select SAMSUNG_DEV_KEYPAD + select SAMSUNG_DEV_PWM + select SAMSUNG_DEV_TS help Machine support for the Samsung SMDKC100 diff --git a/arch/arm/mach-s5pc100/common.c b/arch/arm/mach-s5pc100/common.c index 621908658861..cc6e561c9958 100644 --- a/arch/arm/mach-s5pc100/common.c +++ b/arch/arm/mach-s5pc100/common.c @@ -45,6 +45,7 @@ #include <plat/fb-core.h> #include <plat/iic-core.h> #include <plat/onenand-core.h> +#include <plat/spi-core.h> #include <plat/regs-serial.h> #include <plat/watchdog-reset.h> @@ -165,6 +166,8 @@ void __init s5pc100_map_io(void) s3c_onenand_setname("s5pc100-onenand"); s3c_fb_setname("s5pc100-fb"); s3c_cfcon_setname("s5pc100-pata"); + + s3c64xx_spi_setname("s5pc100-spi"); } void __init s5pc100_init_clocks(int xtal) diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c index 5d2c0934928b..dba7384a87bd 100644 --- a/arch/arm/mach-s5pc100/mach-smdkc100.c +++ b/arch/arm/mach-s5pc100/mach-smdkc100.c @@ -33,6 +33,7 @@ #include <mach/regs-gpio.h> #include <video/platform_lcd.h> +#include <video/samsung_fimd.h> #include <asm/irq.h> #include <asm/mach-types.h> @@ -51,7 +52,6 @@ #include <linux/platform_data/touchscreen-s3c2410.h> #include <linux/platform_data/asoc-s3c.h> #include <plat/backlight.h> -#include <plat/regs-fb-v4.h> #include "common.h" diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig index 77185c38188b..92ad72f0ef98 100644 --- a/arch/arm/mach-s5pv210/Kconfig +++ b/arch/arm/mach-s5pv210/Kconfig @@ -11,11 +11,11 @@ if ARCH_S5PV210 config CPU_S5PV210 bool - select SAMSUNG_DMADEV select S5P_EXT_INT select S5P_HRT select S5P_PM if PM select S5P_SLEEP if PM + select SAMSUNG_DMADEV help Enable S5PV210 CPU support @@ -76,44 +76,44 @@ config MACH_AQUILA bool "Aquila" select CPU_S5PV210 select S3C_DEV_FB - select S5P_DEV_FIMC0 - select S5P_DEV_FIMC1 - select S5P_DEV_FIMC2 select S3C_DEV_HSMMC select S3C_DEV_HSMMC1 select S3C_DEV_HSMMC2 - select S5P_DEV_ONENAND select S5PV210_SETUP_FB_24BPP select S5PV210_SETUP_SDHCI select S5PV210_SETUP_USB_PHY + select S5P_DEV_FIMC0 + select S5P_DEV_FIMC1 + select S5P_DEV_FIMC2 + select S5P_DEV_ONENAND help Machine support for the Samsung Aquila target based on S5PC110 SoC config MACH_GONI bool "GONI" select CPU_S5PV210 - select S5P_GPIO_INT select S3C_DEV_FB - select S5P_DEV_FIMC0 - select S5P_DEV_FIMC1 - select S5P_DEV_FIMC2 select S3C_DEV_HSMMC select S3C_DEV_HSMMC1 select S3C_DEV_HSMMC2 select S3C_DEV_I2C1 select S3C_DEV_I2C2 - select S5P_DEV_MFC select S3C_DEV_USB_HSOTG - select S5P_DEV_ONENAND - select SAMSUNG_DEV_KEYPAD - select S5P_DEV_TV select S5PV210_SETUP_FB_24BPP + select S5PV210_SETUP_FIMC select S5PV210_SETUP_I2C1 select S5PV210_SETUP_I2C2 select S5PV210_SETUP_KEYPAD select S5PV210_SETUP_SDHCI - select S5PV210_SETUP_FIMC select S5PV210_SETUP_USB_PHY + select S5P_DEV_FIMC0 + select S5P_DEV_FIMC1 + select S5P_DEV_FIMC2 + select S5P_DEV_MFC + select S5P_DEV_ONENAND + select S5P_DEV_TV + select S5P_GPIO_INT + select SAMSUNG_DEV_KEYPAD help Machine support for Samsung GONI board S5PC110(MCP) is one of package option of S5PV210 @@ -125,14 +125,14 @@ config MACH_SMDKC110 select S3C_DEV_I2C2 select S3C_DEV_RTC select S3C_DEV_WDT + select S5PV210_SETUP_I2C1 + select S5PV210_SETUP_I2C2 + select S5PV210_SETUP_IDE select S5P_DEV_FIMC0 select S5P_DEV_FIMC1 select S5P_DEV_FIMC2 select S5P_DEV_MFC select SAMSUNG_DEV_IDE - select S5PV210_SETUP_I2C1 - select S5PV210_SETUP_I2C2 - select S5PV210_SETUP_IDE help Machine support for Samsung SMDKC110 S5PC110(MCP) is one of package option of S5PV210 @@ -154,6 +154,13 @@ config MACH_SMDKV210 select S3C_DEV_RTC select S3C_DEV_USB_HSOTG select S3C_DEV_WDT + select S5PV210_SETUP_FB_24BPP + select S5PV210_SETUP_I2C1 + select S5PV210_SETUP_I2C2 + select S5PV210_SETUP_IDE + select S5PV210_SETUP_KEYPAD + select S5PV210_SETUP_SDHCI + select S5PV210_SETUP_USB_PHY select S5P_DEV_FIMC0 select S5P_DEV_FIMC1 select S5P_DEV_FIMC2 @@ -165,20 +172,13 @@ config MACH_SMDKV210 select SAMSUNG_DEV_KEYPAD select SAMSUNG_DEV_PWM select SAMSUNG_DEV_TS - select S5PV210_SETUP_FB_24BPP - select S5PV210_SETUP_I2C1 - select S5PV210_SETUP_I2C2 - select S5PV210_SETUP_IDE - select S5PV210_SETUP_KEYPAD - select S5PV210_SETUP_SDHCI - select S5PV210_SETUP_USB_PHY help Machine support for Samsung SMDKV210 config MACH_TORBRECK bool "Torbreck" - select CPU_S5PV210 select ARCH_SPARSEMEM_ENABLE + select CPU_S5PV210 select S3C_DEV_HSMMC select S3C_DEV_HSMMC1 select S3C_DEV_HSMMC2 diff --git a/arch/arm/mach-s5pv210/common.c b/arch/arm/mach-s5pv210/common.c index 4c9e9027df9a..a0c50efe8145 100644 --- a/arch/arm/mach-s5pv210/common.c +++ b/arch/arm/mach-s5pv210/common.c @@ -43,6 +43,7 @@ #include <plat/iic-core.h> #include <plat/keypad-core.h> #include <plat/tv-core.h> +#include <plat/spi-core.h> #include <plat/regs-serial.h> #include "common.h" @@ -196,6 +197,8 @@ void __init s5pv210_map_io(void) /* setup TV devices */ s5p_hdmi_setname("s5pv210-hdmi"); + + s3c64xx_spi_setname("s5pv210-spi"); } void __init s5pv210_init_clocks(int xtal) diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c index 78028df86c5d..ee9fa5c2ef2c 100644 --- a/arch/arm/mach-s5pv210/mach-aquila.c +++ b/arch/arm/mach-s5pv210/mach-aquila.c @@ -28,6 +28,7 @@ #include <asm/setup.h> #include <asm/mach-types.h> +#include <video/samsung_fimd.h> #include <mach/map.h> #include <mach/regs-clock.h> @@ -39,7 +40,6 @@ #include <plat/fimc-core.h> #include <plat/sdhci.h> #include <plat/s5p-time.h> -#include <plat/regs-fb-v4.h> #include "common.h" diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c index 00f1e47d490a..55e1dba4ffde 100644 --- a/arch/arm/mach-s5pv210/mach-goni.c +++ b/arch/arm/mach-s5pv210/mach-goni.c @@ -35,6 +35,7 @@ #include <asm/setup.h> #include <asm/mach-types.h> +#include <video/samsung_fimd.h> #include <mach/map.h> #include <mach/regs-clock.h> @@ -49,7 +50,6 @@ #include <plat/clock.h> #include <plat/s5p-time.h> #include <plat/mfc.h> -#include <plat/regs-fb-v4.h> #include <plat/camport.h> #include <media/v4l2-mediabus.h> diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c index 7d6fab420508..4cdb5bb7bbcf 100644 --- a/arch/arm/mach-s5pv210/mach-smdkv210.c +++ b/arch/arm/mach-s5pv210/mach-smdkv210.c @@ -28,6 +28,7 @@ #include <asm/mach-types.h> #include <video/platform_lcd.h> +#include <video/samsung_fimd.h> #include <mach/map.h> #include <mach/regs-clock.h> @@ -46,7 +47,6 @@ #include <plat/fb.h> #include <plat/s5p-time.h> #include <plat/backlight.h> -#include <plat/regs-fb-v4.h> #include <plat/mfc.h> #include <plat/clock.h> diff --git a/arch/arm/mach-sa1100/Kconfig b/arch/arm/mach-sa1100/Kconfig index 42625e4d949a..ca14dbdcfb22 100644 --- a/arch/arm/mach-sa1100/Kconfig +++ b/arch/arm/mach-sa1100/Kconfig @@ -49,15 +49,15 @@ config SA1100_COLLIE bool "Sharp Zaurus SL5500" # FIXME: select CPU_FREQ_SA11x0 select SHARP_LOCOMO - select SHARP_SCOOP select SHARP_PARAM + select SHARP_SCOOP help Say Y here to support the Sharp Zaurus SL5500 PDAs. config SA1100_H3100 bool "Compaq iPAQ H3100" - select HTC_EGPIO select CPU_FREQ_SA1110 + select HTC_EGPIO help Say Y here if you intend to run this kernel on the Compaq iPAQ H3100 handheld computer. Information about this machine and the @@ -67,8 +67,8 @@ config SA1100_H3100 config SA1100_H3600 bool "Compaq iPAQ H3600/H3700" - select HTC_EGPIO select CPU_FREQ_SA1110 + select HTC_EGPIO help Say Y here if you intend to run this kernel on the Compaq iPAQ H3600 handheld computer. Information about this machine and the @@ -78,16 +78,16 @@ config SA1100_H3600 config SA1100_BADGE4 bool "HP Labs BadgePAD 4" - select SA1111 select CPU_FREQ_SA1100 + select SA1111 help Say Y here if you want to build a kernel for the HP Laboratories BadgePAD 4. config SA1100_JORNADA720 bool "HP Jornada 720" - select SA1111 # FIXME: select CPU_FREQ_SA11x0 + select SA1111 help Say Y here if you want to build a kernel for the HP Jornada 720 handheld computer. See @@ -95,8 +95,8 @@ config SA1100_JORNADA720 config SA1100_JORNADA720_SSP bool "HP Jornada 720 Extended SSP driver" - select SA1100_SSP depends on SA1100_JORNADA720 + select SA1100_SSP help Say Y here if you have a HP Jornada 7xx handheld computer and you want to access devices connected to the MCU. Those include the diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c index e1ccda6128eb..6a7ad3c2a3fc 100644 --- a/arch/arm/mach-sa1100/assabet.c +++ b/arch/arm/mach-sa1100/assabet.c @@ -388,7 +388,7 @@ static void __init map_sa1100_gpio_regs( void ) */ static void __init get_assabet_scr(void) { - unsigned long scr, i; + unsigned long uninitialized_var(scr), i; GPDR |= 0x3fc; /* Configure GPIO 9:2 as outputs */ GPSR = 0x3fc; /* Write 0xFF to GPIO 9:2 */ diff --git a/arch/arm/mach-sa1100/include/mach/SA-1111.h b/arch/arm/mach-sa1100/include/mach/SA-1111.h deleted file mode 100644 index c38f60915cb6..000000000000 --- a/arch/arm/mach-sa1100/include/mach/SA-1111.h +++ /dev/null @@ -1,5 +0,0 @@ -/* - * Moved to new location - */ -#warning using old SA-1111.h - update to <asm/hardware/sa1111.h> -#include <asm/hardware/sa1111.h> diff --git a/arch/arm/mach-sa1100/include/mach/lart.h b/arch/arm/mach-sa1100/include/mach/lart.h deleted file mode 100644 index 8a5482d908db..000000000000 --- a/arch/arm/mach-sa1100/include/mach/lart.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef _INCLUDE_LART_H -#define _INCLUDE_LART_H - -#define LART_GPIO_ETH0 GPIO_GPIO0 -#define LART_IRQ_ETH0 IRQ_GPIO0 - -#define LART_GPIO_IDE GPIO_GPIO1 -#define LART_IRQ_IDE IRQ_GPIO1 - -#define LART_GPIO_UCB1200 GPIO_GPIO18 -#define LART_IRQ_UCB1200 IRQ_GPIO18 - -#endif diff --git a/arch/arm/mach-shark/pci.c b/arch/arm/mach-shark/pci.c index b8b4ab323a3e..6d91a914c1dd 100644 --- a/arch/arm/mach-shark/pci.c +++ b/arch/arm/mach-shark/pci.c @@ -41,7 +41,7 @@ static struct hw_pci shark_pci __initdata = { static int __init shark_pci_init(void) { if (!machine_is_shark()) - return; + return -ENODEV; pcibios_min_io = 0x6000; pcibios_min_mem = 0x50000000; diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 4cacc2d22fbe..8ae100cc655c 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -4,49 +4,49 @@ comment "SH-Mobile System Type" config ARCH_SH7367 bool "SH-Mobile G3 (SH7367)" + select ARCH_WANT_OPTIONAL_GPIOLIB select CPU_V6 select SH_CLK_CPG - select ARCH_WANT_OPTIONAL_GPIOLIB config ARCH_SH7377 bool "SH-Mobile G4 (SH7377)" + select ARCH_WANT_OPTIONAL_GPIOLIB select CPU_V7 select SH_CLK_CPG - select ARCH_WANT_OPTIONAL_GPIOLIB config ARCH_SH7372 bool "SH-Mobile AP4 (SH7372)" - select CPU_V7 - select SH_CLK_CPG select ARCH_WANT_OPTIONAL_GPIOLIB select ARM_CPU_SUSPEND if PM || CPU_IDLE + select CPU_V7 + select SH_CLK_CPG config ARCH_SH73A0 bool "SH-Mobile AG5 (R8A73A00)" - select CPU_V7 - select SH_CLK_CPG select ARCH_WANT_OPTIONAL_GPIOLIB select ARM_GIC + select CPU_V7 select I2C + select SH_CLK_CPG config ARCH_R8A7740 bool "R-Mobile A1 (R8A77400)" + select ARCH_WANT_OPTIONAL_GPIOLIB select CPU_V7 select SH_CLK_CPG - select ARCH_WANT_OPTIONAL_GPIOLIB config ARCH_R8A7779 bool "R-Car H1 (R8A77790)" + select ARCH_WANT_OPTIONAL_GPIOLIB + select ARM_GIC select CPU_V7 select SH_CLK_CPG - select ARM_GIC - select ARCH_WANT_OPTIONAL_GPIOLIB config ARCH_EMEV2 bool "Emma Mobile EV2" - select CPU_V7 - select ARM_GIC select ARCH_WANT_OPTIONAL_GPIOLIB + select ARM_GIC + select CPU_V7 comment "SH-Mobile Board Type" @@ -65,9 +65,9 @@ config MACH_AP4EVB bool "AP4EVB board" depends on ARCH_SH7372 select ARCH_REQUIRE_GPIOLIB + select REGULATOR_FIXED_VOLTAGE if REGULATOR select SH_LCD_MIPI_DSI select SND_SOC_AK4642 if SND_SIMPLE_CARD - select REGULATOR_FIXED_VOLTAGE if REGULATOR choice prompt "AP4EVB LCD panel selection" @@ -84,37 +84,37 @@ endchoice config MACH_AG5EVM bool "AG5EVM board" + depends on ARCH_SH73A0 select ARCH_REQUIRE_GPIOLIB - select SH_LCD_MIPI_DSI select REGULATOR_FIXED_VOLTAGE if REGULATOR - depends on ARCH_SH73A0 + select SH_LCD_MIPI_DSI config MACH_MACKEREL bool "mackerel board" depends on ARCH_SH7372 select ARCH_REQUIRE_GPIOLIB - select SND_SOC_AK4642 if SND_SIMPLE_CARD select REGULATOR_FIXED_VOLTAGE if REGULATOR + select SND_SOC_AK4642 if SND_SIMPLE_CARD config MACH_KOTA2 bool "KOTA2 board" + depends on ARCH_SH73A0 select ARCH_REQUIRE_GPIOLIB select REGULATOR_FIXED_VOLTAGE if REGULATOR - depends on ARCH_SH73A0 config MACH_BONITO bool "bonito board" + depends on ARCH_R8A7740 select ARCH_REQUIRE_GPIOLIB select REGULATOR_FIXED_VOLTAGE if REGULATOR - depends on ARCH_R8A7740 config MACH_ARMADILLO800EVA bool "Armadillo-800 EVA board" depends on ARCH_R8A7740 select ARCH_REQUIRE_GPIOLIB - select USE_OF select REGULATOR_FIXED_VOLTAGE if REGULATOR select SND_SOC_WM8978 if SND_SIMPLE_CARD + select USE_OF config MACH_MARZEN bool "MARZEN board" @@ -125,16 +125,16 @@ config MACH_MARZEN config MACH_KZM9D bool "KZM9D board" depends on ARCH_EMEV2 - select USE_OF select REGULATOR_FIXED_VOLTAGE if REGULATOR + select USE_OF config MACH_KZM9G bool "KZM-A9-GT board" depends on ARCH_SH73A0 select ARCH_REQUIRE_GPIOLIB - select USE_OF - select SND_SOC_AK4642 if SND_SIMPLE_CARD select REGULATOR_FIXED_VOLTAGE if REGULATOR + select SND_SOC_AK4642 if SND_SIMPLE_CARD + select USE_OF comment "SH-Mobile System Configuration" diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c index 2912eab3b967..3cc8b1c21da9 100644 --- a/arch/arm/mach-shmobile/board-armadillo800eva.c +++ b/arch/arm/mach-shmobile/board-armadillo800eva.c @@ -1196,7 +1196,7 @@ static void __init eva_init(void) #ifdef CONFIG_CACHE_L2X0 /* Early BRESP enable, Shared attribute override enable, 32K*8way */ - l2x0_init(__io(0xf0002000), 0x40440000, 0x82000fff); + l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff); #endif i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices)); diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c index 3cafb6ab5e9a..37b2a3133b3b 100644 --- a/arch/arm/mach-shmobile/clock-r8a7779.c +++ b/arch/arm/mach-shmobile/clock-r8a7779.c @@ -24,17 +24,17 @@ #include <linux/clkdev.h> #include <mach/common.h> -#define FRQMR 0xffc80014 -#define MSTPCR0 0xffc80030 -#define MSTPCR1 0xffc80034 -#define MSTPCR3 0xffc8003c -#define MSTPSR1 0xffc80044 -#define MSTPSR4 0xffc80048 -#define MSTPSR6 0xffc8004c -#define MSTPCR4 0xffc80050 -#define MSTPCR5 0xffc80054 -#define MSTPCR6 0xffc80058 -#define MSTPCR7 0xffc80040 +#define FRQMR IOMEM(0xffc80014) +#define MSTPCR0 IOMEM(0xffc80030) +#define MSTPCR1 IOMEM(0xffc80034) +#define MSTPCR3 IOMEM(0xffc8003c) +#define MSTPSR1 IOMEM(0xffc80044) +#define MSTPSR4 IOMEM(0xffc80048) +#define MSTPSR6 IOMEM(0xffc8004c) +#define MSTPCR4 IOMEM(0xffc80050) +#define MSTPCR5 IOMEM(0xffc80054) +#define MSTPCR6 IOMEM(0xffc80058) +#define MSTPCR7 IOMEM(0xffc80040) /* ioremap() through clock mapping mandatory to avoid * collision with ARM coherent DMA virtual memory range. diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index ed77ab8c9143..d47e215aca87 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -100,7 +100,7 @@ static inline int shmobile_cpu_is_dead(unsigned int cpu) { return 1; } extern void shmobile_smp_init_cpus(unsigned int ncores); -static inline void shmobile_init_late(void) +static inline void __init shmobile_init_late(void) { shmobile_suspend_init(); shmobile_cpuidle_init(); diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index 2917668f0091..ebbffc25f24f 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c @@ -247,7 +247,7 @@ void __init r8a7779_add_standard_devices(void) { #ifdef CONFIG_CACHE_L2X0 /* Early BRESP enable, Shared attribute override enable, 64K*16way */ - l2x0_init((void __iomem __force *)(0xf0100000), 0x40470000, 0x82000fff); + l2x0_init(IOMEM(0xf0100000), 0x40470000, 0x82000fff); #endif r8a7779_pm_init(); diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c index f978c5d0e1ae..f67456286280 100644 --- a/arch/arm/mach-shmobile/smp-emev2.c +++ b/arch/arm/mach-shmobile/smp-emev2.c @@ -100,7 +100,7 @@ static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct * /* Tell ROM loader about our vector (in headsmp.S) */ emev2_set_boot_vector(__pa(shmobile_secondary_vector)); - gic_raise_softirq(cpumask_of(cpu), 1); + gic_raise_softirq(cpumask_of(cpu), 0); return 0; } diff --git a/arch/arm/mach-spear13xx/include/mach/spear1310_misc_regs.h b/arch/arm/mach-spear13xx/include/mach/spear1310_misc_regs.h deleted file mode 100644 index e69de29bb2d1..000000000000 --- a/arch/arm/mach-spear13xx/include/mach/spear1310_misc_regs.h +++ /dev/null diff --git a/arch/arm/mach-spear13xx/include/mach/spear1340_misc_regs.h b/arch/arm/mach-spear13xx/include/mach/spear1340_misc_regs.h deleted file mode 100644 index e69de29bb2d1..000000000000 --- a/arch/arm/mach-spear13xx/include/mach/spear1340_misc_regs.h +++ /dev/null diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c index e10648801b2e..5633d698f1e1 100644 --- a/arch/arm/mach-spear13xx/spear13xx.c +++ b/arch/arm/mach-spear13xx/spear13xx.c @@ -78,6 +78,9 @@ struct dw_dma_platform_data dmac_plat_data = { .nr_channels = 8, .chan_allocation_order = CHAN_ALLOCATION_DESCENDING, .chan_priority = CHAN_PRIORITY_DESCENDING, + .block_size = 4095U, + .nr_masters = 2, + .data_width = { 3, 3, 0, 0 }, }; void __init spear13xx_l2x0_init(void) diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 5f3c03b61f8e..9ff6f6ea3617 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -4,42 +4,42 @@ comment "NVIDIA Tegra options" config ARCH_TEGRA_2x_SOC bool "Enable support for Tegra20 family" - select CPU_V7 - select ARM_GIC select ARCH_REQUIRE_GPIOLIB - select PINCTRL - select PINCTRL_TEGRA20 - select USB_ARCH_HAS_EHCI if USB_SUPPORT - select USB_ULPI if USB - select USB_ULPI_VIEWPORT if USB_SUPPORT select ARM_ERRATA_720789 select ARM_ERRATA_742230 select ARM_ERRATA_751472 select ARM_ERRATA_754327 - select ARM_ERRATA_764369 + select ARM_ERRATA_764369 if SMP + select ARM_GIC + select CPU_FREQ_TABLE if CPU_FREQ + select CPU_V7 + select PINCTRL + select PINCTRL_TEGRA20 select PL310_ERRATA_727915 if CACHE_L2X0 select PL310_ERRATA_769419 if CACHE_L2X0 - select CPU_FREQ_TABLE if CPU_FREQ + select USB_ARCH_HAS_EHCI if USB_SUPPORT + select USB_ULPI if USB + select USB_ULPI_VIEWPORT if USB_SUPPORT help Support for NVIDIA Tegra AP20 and T20 processors, based on the ARM CortexA9MP CPU and the ARM PL310 L2 cache controller config ARCH_TEGRA_3x_SOC bool "Enable support for Tegra30 family" - select CPU_V7 - select ARM_GIC select ARCH_REQUIRE_GPIOLIB + select ARM_ERRATA_743622 + select ARM_ERRATA_751472 + select ARM_ERRATA_754322 + select ARM_ERRATA_764369 if SMP + select ARM_GIC + select CPU_FREQ_TABLE if CPU_FREQ + select CPU_V7 select PINCTRL select PINCTRL_TEGRA30 + select PL310_ERRATA_769419 if CACHE_L2X0 select USB_ARCH_HAS_EHCI if USB_SUPPORT select USB_ULPI if USB select USB_ULPI_VIEWPORT if USB_SUPPORT - select ARM_ERRATA_743622 - select ARM_ERRATA_751472 - select ARM_ERRATA_754322 - select ARM_ERRATA_764369 - select PL310_ERRATA_769419 if CACHE_L2X0 - select CPU_FREQ_TABLE if CPU_FREQ help Support for NVIDIA Tegra T30 processor family, based on the ARM CortexA9MP CPU and the ARM PL310 L2 cache controller @@ -57,8 +57,6 @@ config TEGRA_AHB which controls AHB bus master arbitration and some perfomance parameters(priority, prefech size). -comment "Tegra board type" - choice prompt "Default low-level debug console UART" default TEGRA_DEBUG_UART_NONE diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c index 57e235f4ac74..aa5325cd1c42 100644 --- a/arch/arm/mach-tegra/board-dt-tegra20.c +++ b/arch/arm/mach-tegra/board-dt-tegra20.c @@ -182,7 +182,7 @@ DT_MACHINE_START(TEGRA_DT, "nVidia Tegra20 (Flattened Device Tree)") .init_early = tegra20_init_early, .init_irq = tegra_dt_init_irq, .handle_irq = gic_handle_irq, - .timer = &tegra_timer, + .timer = &tegra_sys_timer, .init_machine = tegra_dt_init, .init_late = tegra_dt_init_late, .restart = tegra_assert_system_reset, diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c index e4a676d4ddf7..5e92a81f9a2e 100644 --- a/arch/arm/mach-tegra/board-dt-tegra30.c +++ b/arch/arm/mach-tegra/board-dt-tegra30.c @@ -89,7 +89,7 @@ DT_MACHINE_START(TEGRA30_DT, "NVIDIA Tegra30 (Flattened Device Tree)") .init_early = tegra30_init_early, .init_irq = tegra_dt_init_irq, .handle_irq = gic_handle_irq, - .timer = &tegra_timer, + .timer = &tegra_sys_timer, .init_machine = tegra30_dt_init, .init_late = tegra_init_late, .restart = tegra_assert_system_reset, diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h index f88e5143c767..91fbe733a21e 100644 --- a/arch/arm/mach-tegra/board.h +++ b/arch/arm/mach-tegra/board.h @@ -55,5 +55,5 @@ static inline int harmony_pcie_init(void) { return 0; } void __init tegra_paz00_wifikill_init(void); -extern struct sys_timer tegra_timer; +extern struct sys_timer tegra_sys_timer; #endif diff --git a/arch/arm/mach-tegra/include/mach/smmu.h b/arch/arm/mach-tegra/include/mach/smmu.h deleted file mode 100644 index dad403a9cf00..000000000000 --- a/arch/arm/mach-tegra/include/mach/smmu.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * IOMMU API for SMMU in Tegra30 - * - * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#ifndef MACH_SMMU_H -#define MACH_SMMU_H - -enum smmu_hwgrp { - HWGRP_AFI, - HWGRP_AVPC, - HWGRP_DC, - HWGRP_DCB, - HWGRP_EPP, - HWGRP_G2, - HWGRP_HC, - HWGRP_HDA, - HWGRP_ISP, - HWGRP_MPE, - HWGRP_NV, - HWGRP_NV2, - HWGRP_PPCS, - HWGRP_SATA, - HWGRP_VDE, - HWGRP_VI, - - HWGRP_COUNT, - - HWGRP_END = ~0, -}; - -#define HWG_AFI (1 << HWGRP_AFI) -#define HWG_AVPC (1 << HWGRP_AVPC) -#define HWG_DC (1 << HWGRP_DC) -#define HWG_DCB (1 << HWGRP_DCB) -#define HWG_EPP (1 << HWGRP_EPP) -#define HWG_G2 (1 << HWGRP_G2) -#define HWG_HC (1 << HWGRP_HC) -#define HWG_HDA (1 << HWGRP_HDA) -#define HWG_ISP (1 << HWGRP_ISP) -#define HWG_MPE (1 << HWGRP_MPE) -#define HWG_NV (1 << HWGRP_NV) -#define HWG_NV2 (1 << HWGRP_NV2) -#define HWG_PPCS (1 << HWGRP_PPCS) -#define HWG_SATA (1 << HWGRP_SATA) -#define HWG_VDE (1 << HWGRP_VDE) -#define HWG_VI (1 << HWGRP_VI) - -#endif /* MACH_SMMU_H */ diff --git a/arch/arm/mach-tegra/include/mach/tegra_wm8903_pdata.h b/arch/arm/mach-tegra/include/mach/tegra_wm8903_pdata.h deleted file mode 100644 index 9d293344a7ff..000000000000 --- a/arch/arm/mach-tegra/include/mach/tegra_wm8903_pdata.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * arch/arm/mach-tegra/include/mach/tegra_wm8903_pdata.h - * - * Copyright 2011 NVIDIA, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -struct tegra_wm8903_platform_data { - int gpio_spkr_en; - int gpio_hp_det; - int gpio_hp_mute; - int gpio_int_mic_en; - int gpio_ext_mic_en; -}; diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c index cc9b5fd8c3d3..8d398a33adf7 100644 --- a/arch/arm/mach-tegra/tegra20_clocks_data.c +++ b/arch/arm/mach-tegra/tegra20_clocks_data.c @@ -953,6 +953,7 @@ PERIPH_CLK(pcie_xclk, NULL, "pcie_xclk", 74, 0, 26000000, mux_clk_m, static struct clk *tegra_list_clks[] = { &tegra_apbdma, &tegra_rtc, + &tegra_timer, &tegra_i2s1, &tegra_i2s2, &tegra_spdif_out, diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c index 5cd502c27163..e9de5dfd94ec 100644 --- a/arch/arm/mach-tegra/tegra30_clocks.c +++ b/arch/arm/mach-tegra/tegra30_clocks.c @@ -1199,7 +1199,7 @@ static long tegra30_pll_round_rate(struct clk_hw *hw, unsigned long rate, { struct clk_tegra *c = to_clk_tegra(hw); unsigned long input_rate = *prate; - unsigned long output_rate = *prate; + u64 output_rate = *prate; const struct clk_pll_freq_table *sel; struct clk_pll_freq_table cfg; int mul; diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c b/arch/arm/mach-tegra/tegra30_clocks_data.c index d92cb556ae35..3d2e5532a9ea 100644 --- a/arch/arm/mach-tegra/tegra30_clocks_data.c +++ b/arch/arm/mach-tegra/tegra30_clocks_data.c @@ -1143,6 +1143,7 @@ struct clk *tegra_list_clks[] = { &tegra_apbdma, &tegra_rtc, &tegra_kbc, + &tegra_timer, &tegra_kfuse, &tegra_fuse, &tegra_fuse_burn, diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c index eccdce983043..d3b8c8e7368f 100644 --- a/arch/arm/mach-tegra/timer.c +++ b/arch/arm/mach-tegra/timer.c @@ -245,7 +245,7 @@ static void __init tegra_init_timer(void) register_persistent_clock(NULL, tegra_read_persistent_clock); } -struct sys_timer tegra_timer = { +struct sys_timer tegra_sys_timer = { .init = tegra_init_timer, }; diff --git a/arch/arm/mach-u300/Kconfig b/arch/arm/mach-u300/Kconfig index f7e12ede008c..1f597647d431 100644 --- a/arch/arm/mach-u300/Kconfig +++ b/arch/arm/mach-u300/Kconfig @@ -7,8 +7,8 @@ comment "ST-Ericsson Mobile Platform Products" config MACH_U300 bool "U300" select PINCTRL - select PINCTRL_U300 select PINCTRL_COH901 + select PINCTRL_U300 comment "ST-Ericsson U300/U335 Feature Selections" diff --git a/arch/arm/mach-u300/i2c.c b/arch/arm/mach-u300/i2c.c index 0d4620ed853c..96800aa1316d 100644 --- a/arch/arm/mach-u300/i2c.c +++ b/arch/arm/mach-u300/i2c.c @@ -9,7 +9,7 @@ */ #include <linux/kernel.h> #include <linux/i2c.h> -#include <linux/mfd/abx500.h> +#include <linux/mfd/ab3100.h> #include <linux/regulator/machine.h> #include <linux/amba/bus.h> #include <mach/irqs.h> diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig index c77c86c47369..e8c3f0d70ca6 100644 --- a/arch/arm/mach-ux500/Kconfig +++ b/arch/arm/mach-ux500/Kconfig @@ -3,33 +3,33 @@ if ARCH_U8500 config UX500_SOC_COMMON bool default y - select ARM_GIC - select HAS_MTU - select PL310_ERRATA_753970 select ARM_ERRATA_754322 - select ARM_ERRATA_764369 + select ARM_ERRATA_764369 if SMP + select ARM_GIC select CACHE_L2X0 + select COMMON_CLK + select HAS_MTU select PINCTRL select PINCTRL_NOMADIK - select COMMON_CLK + select PL310_ERRATA_753970 if CACHE_PL310 config UX500_SOC_DB8500 bool + select CPU_FREQ_TABLE if CPU_FREQ select MFD_DB8500_PRCMU + select PINCTRL_DB8500 select REGULATOR select REGULATOR_DB8500_PRCMU - select CPU_FREQ_TABLE if CPU_FREQ - select PINCTRL_DB8500 menu "Ux500 target platform (boards)" config MACH_MOP500 bool "U8500 Development platform, MOP500 versions" - select UX500_SOC_DB8500 select I2C select I2C_NOMADIK - select SOC_BUS select REGULATOR_FIXED_VOLTAGE + select SOC_BUS + select UX500_SOC_DB8500 help Include support for the MOP500 development platform. diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c index 2236cbd03cd7..1f3fbc2bb776 100644 --- a/arch/arm/mach-ux500/cpu.c +++ b/arch/arm/mach-ux500/cpu.c @@ -16,6 +16,7 @@ #include <linux/stat.h> #include <linux/of.h> #include <linux/of_irq.h> +#include <linux/irq.h> #include <linux/platform_data/clk-ux500.h> #include <asm/hardware/gic.h> diff --git a/arch/arm/mach-versatile/Kconfig b/arch/arm/mach-versatile/Kconfig index c1f38f6625b2..63d8e9f81b99 100644 --- a/arch/arm/mach-versatile/Kconfig +++ b/arch/arm/mach-versatile/Kconfig @@ -3,9 +3,9 @@ menu "Versatile platform type" config ARCH_VERSATILE_PB bool "Support Versatile Platform Baseboard for ARM926EJ-S" + default y select CPU_ARM926T select MIGHT_HAVE_PCI - default y help Include support for the ARM(R) Versatile Platform Baseboard for the ARM926EJ-S. @@ -19,8 +19,8 @@ config MACH_VERSATILE_AB config MACH_VERSATILE_DT bool "Support Versatile platform from device tree" - select USE_OF select CPU_ARM926T + select USE_OF help Include support for the ARM(R) Versatile/PB platform, using the device tree for discovery diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c index 5f6b7d543e55..560e0df728f8 100644 --- a/arch/arm/mach-vexpress/v2m.c +++ b/arch/arm/mach-vexpress/v2m.c @@ -659,6 +659,7 @@ static void __init v2m_dt_init(void) const static char *v2m_dt_match[] __initconst = { "arm,vexpress", + "xen,xenvm", NULL, }; diff --git a/arch/arm/mach-vt8500/include/mach/uncompress.h b/arch/arm/mach-vt8500/include/mach/uncompress.h index bb9e2d23fee3..e6e81fdaf109 100644 --- a/arch/arm/mach-vt8500/include/mach/uncompress.h +++ b/arch/arm/mach-vt8500/include/mach/uncompress.h @@ -15,15 +15,15 @@ * */ -#define UART0_PHYS 0xd8200000 -#include <asm/io.h> +#define UART0_PHYS 0xd8200000 +#define UART0_ADDR(x) *(volatile unsigned char *)(UART0_PHYS + x) static void putc(const char c) { - while (readb(UART0_PHYS + 0x1c) & 0x2) + while (UART0_ADDR(0x1c) & 0x2) /* Tx busy, wait and poll */; - writeb(c, UART0_PHYS); + UART0_ADDR(0) = c; } static void flush(void) diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c index 587ea950d08b..8d3871f110a5 100644 --- a/arch/arm/mach-vt8500/vt8500.c +++ b/arch/arm/mach-vt8500/vt8500.c @@ -77,8 +77,11 @@ static void vt8500_power_off(void) void __init vt8500_init(void) { - struct device_node *np, *fb; + struct device_node *np; +#if defined(CONFIG_FB_VT8500) || defined(CONFIG_FB_WM8505) + struct device_node *fb; void __iomem *gpio_base; +#endif #ifdef CONFIG_FB_VT8500 fb = of_find_compatible_node(NULL, NULL, "via,vt8500-fb"); diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 101b9681c08c..94186b6c685f 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -10,8 +10,8 @@ config CPU_ARM7TDMI depends on !MMU select CPU_32v4T select CPU_ABRT_LV4T - select CPU_PABRT_LEGACY select CPU_CACHE_V4 + select CPU_PABRT_LEGACY help A 32-bit RISC microprocessor based on the ARM7 processor core which has no memory control unit and cache. @@ -24,11 +24,11 @@ config CPU_ARM720T bool "Support ARM720T processor" if ARCH_INTEGRATOR select CPU_32v4T select CPU_ABRT_LV4T - select CPU_PABRT_LEGACY select CPU_CACHE_V4 select CPU_CACHE_VIVT - select CPU_CP15_MMU select CPU_COPY_V4WT if MMU + select CPU_CP15_MMU + select CPU_PABRT_LEGACY select CPU_TLB_V4WT if MMU help A 32-bit RISC processor with 8kByte Cache, Write Buffer and @@ -43,9 +43,9 @@ config CPU_ARM740T depends on !MMU select CPU_32v4T select CPU_ABRT_LV4T - select CPU_PABRT_LEGACY select CPU_CACHE_V3 # although the core is v4t select CPU_CP15_MPU + select CPU_PABRT_LEGACY help A 32-bit RISC processor with 8KB cache or 4KB variants, write buffer and MPU(Protection Unit) built around @@ -60,8 +60,8 @@ config CPU_ARM9TDMI depends on !MMU select CPU_32v4T select CPU_ABRT_NOMMU - select CPU_PABRT_LEGACY select CPU_CACHE_V4 + select CPU_PABRT_LEGACY help A 32-bit RISC microprocessor based on the ARM9 processor core which has no memory control unit and cache. @@ -74,11 +74,11 @@ config CPU_ARM920T bool "Support ARM920T processor" if ARCH_INTEGRATOR select CPU_32v4T select CPU_ABRT_EV4T - select CPU_PABRT_LEGACY select CPU_CACHE_V4WT select CPU_CACHE_VIVT - select CPU_CP15_MMU select CPU_COPY_V4WB if MMU + select CPU_CP15_MMU + select CPU_PABRT_LEGACY select CPU_TLB_V4WBI if MMU help The ARM920T is licensed to be produced by numerous vendors, @@ -92,11 +92,11 @@ config CPU_ARM922T bool "Support ARM922T processor" if ARCH_INTEGRATOR select CPU_32v4T select CPU_ABRT_EV4T - select CPU_PABRT_LEGACY select CPU_CACHE_V4WT select CPU_CACHE_VIVT - select CPU_CP15_MMU select CPU_COPY_V4WB if MMU + select CPU_CP15_MMU + select CPU_PABRT_LEGACY select CPU_TLB_V4WBI if MMU help The ARM922T is a version of the ARM920T, but with smaller @@ -111,11 +111,11 @@ config CPU_ARM925T bool "Support ARM925T processor" if ARCH_OMAP1 select CPU_32v4T select CPU_ABRT_EV4T - select CPU_PABRT_LEGACY select CPU_CACHE_V4WT select CPU_CACHE_VIVT - select CPU_CP15_MMU select CPU_COPY_V4WB if MMU + select CPU_CP15_MMU + select CPU_PABRT_LEGACY select CPU_TLB_V4WBI if MMU help The ARM925T is a mix between the ARM920T and ARM926T, but with @@ -130,10 +130,10 @@ config CPU_ARM926T bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB select CPU_32v5 select CPU_ABRT_EV5TJ - select CPU_PABRT_LEGACY select CPU_CACHE_VIVT - select CPU_CP15_MMU select CPU_COPY_V4WB if MMU + select CPU_CP15_MMU + select CPU_PABRT_LEGACY select CPU_TLB_V4WBI if MMU help This is a variant of the ARM920. It has slightly different @@ -148,11 +148,11 @@ config CPU_FA526 bool select CPU_32v4 select CPU_ABRT_EV4 - select CPU_PABRT_LEGACY - select CPU_CACHE_VIVT - select CPU_CP15_MMU select CPU_CACHE_FA + select CPU_CACHE_VIVT select CPU_COPY_FA if MMU + select CPU_CP15_MMU + select CPU_PABRT_LEGACY select CPU_TLB_FA if MMU help The FA526 is a version of the ARMv4 compatible processor with @@ -167,9 +167,9 @@ config CPU_ARM940T depends on !MMU select CPU_32v4T select CPU_ABRT_NOMMU - select CPU_PABRT_LEGACY select CPU_CACHE_VIVT select CPU_CP15_MPU + select CPU_PABRT_LEGACY help ARM940T is a member of the ARM9TDMI family of general- purpose microprocessors with MPU and separate 4KB @@ -185,9 +185,9 @@ config CPU_ARM946E depends on !MMU select CPU_32v5 select CPU_ABRT_NOMMU - select CPU_PABRT_LEGACY select CPU_CACHE_VIVT select CPU_CP15_MPU + select CPU_PABRT_LEGACY help ARM946E-S is a member of the ARM9E-S family of high- performance, 32-bit system-on-chip processor solutions. @@ -201,11 +201,11 @@ config CPU_ARM1020 bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR select CPU_32v5 select CPU_ABRT_EV4T - select CPU_PABRT_LEGACY select CPU_CACHE_V4WT select CPU_CACHE_VIVT - select CPU_CP15_MMU select CPU_COPY_V4WB if MMU + select CPU_CP15_MMU + select CPU_PABRT_LEGACY select CPU_TLB_V4WBI if MMU help The ARM1020 is the 32K cached version of the ARM10 processor, @@ -217,25 +217,25 @@ config CPU_ARM1020 # ARM1020E - needs validating config CPU_ARM1020E bool "Support ARM1020E processor" if ARCH_INTEGRATOR + depends on n select CPU_32v5 select CPU_ABRT_EV4T - select CPU_PABRT_LEGACY select CPU_CACHE_V4WT select CPU_CACHE_VIVT - select CPU_CP15_MMU select CPU_COPY_V4WB if MMU + select CPU_CP15_MMU + select CPU_PABRT_LEGACY select CPU_TLB_V4WBI if MMU - depends on n # ARM1022E config CPU_ARM1022 bool "Support ARM1022E processor" if ARCH_INTEGRATOR select CPU_32v5 select CPU_ABRT_EV4T - select CPU_PABRT_LEGACY select CPU_CACHE_VIVT - select CPU_CP15_MMU select CPU_COPY_V4WB if MMU # can probably do better + select CPU_CP15_MMU + select CPU_PABRT_LEGACY select CPU_TLB_V4WBI if MMU help The ARM1022E is an implementation of the ARMv5TE architecture @@ -250,10 +250,10 @@ config CPU_ARM1026 bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR select CPU_32v5 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10 - select CPU_PABRT_LEGACY select CPU_CACHE_VIVT - select CPU_CP15_MMU select CPU_COPY_V4WB if MMU # can probably do better + select CPU_CP15_MMU + select CPU_PABRT_LEGACY select CPU_TLB_V4WBI if MMU help The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture @@ -268,11 +268,11 @@ config CPU_SA110 select CPU_32v3 if ARCH_RPC select CPU_32v4 if !ARCH_RPC select CPU_ABRT_EV4 - select CPU_PABRT_LEGACY select CPU_CACHE_V4WB select CPU_CACHE_VIVT - select CPU_CP15_MMU select CPU_COPY_V4WB if MMU + select CPU_CP15_MMU + select CPU_PABRT_LEGACY select CPU_TLB_V4WB if MMU help The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and @@ -288,10 +288,10 @@ config CPU_SA1100 bool select CPU_32v4 select CPU_ABRT_EV4 - select CPU_PABRT_LEGACY select CPU_CACHE_V4WB select CPU_CACHE_VIVT select CPU_CP15_MMU + select CPU_PABRT_LEGACY select CPU_TLB_V4WB if MMU # XScale @@ -299,9 +299,9 @@ config CPU_XSCALE bool select CPU_32v5 select CPU_ABRT_EV5T - select CPU_PABRT_LEGACY select CPU_CACHE_VIVT select CPU_CP15_MMU + select CPU_PABRT_LEGACY select CPU_TLB_V4WBI if MMU # XScale Core Version 3 @@ -309,9 +309,9 @@ config CPU_XSC3 bool select CPU_32v5 select CPU_ABRT_EV5T - select CPU_PABRT_LEGACY select CPU_CACHE_VIVT select CPU_CP15_MMU + select CPU_PABRT_LEGACY select CPU_TLB_V4WBI if MMU select IO_36 @@ -320,21 +320,21 @@ config CPU_MOHAWK bool select CPU_32v5 select CPU_ABRT_EV5T - select CPU_PABRT_LEGACY select CPU_CACHE_VIVT + select CPU_COPY_V4WB if MMU select CPU_CP15_MMU + select CPU_PABRT_LEGACY select CPU_TLB_V4WBI if MMU - select CPU_COPY_V4WB if MMU # Feroceon config CPU_FEROCEON bool select CPU_32v5 select CPU_ABRT_EV5T - select CPU_PABRT_LEGACY select CPU_CACHE_VIVT - select CPU_CP15_MMU select CPU_COPY_FEROCEON if MMU + select CPU_CP15_MMU + select CPU_PABRT_LEGACY select CPU_TLB_FEROCEON if MMU config CPU_FEROCEON_OLD_ID @@ -349,20 +349,20 @@ config CPU_FEROCEON_OLD_ID # Marvell PJ4 config CPU_PJ4 bool - select CPU_V7 select ARM_THUMBEE + select CPU_V7 # ARMv6 config CPU_V6 bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX select CPU_32v6 select CPU_ABRT_EV6 - select CPU_PABRT_V6 select CPU_CACHE_V6 select CPU_CACHE_VIPT + select CPU_COPY_V6 if MMU select CPU_CP15_MMU select CPU_HAS_ASID if MMU - select CPU_COPY_V6 if MMU + select CPU_PABRT_V6 select CPU_TLB_V6 if MMU # ARMv6k @@ -371,12 +371,12 @@ config CPU_V6K select CPU_32v6 select CPU_32v6K select CPU_ABRT_EV6 - select CPU_PABRT_V6 select CPU_CACHE_V6 select CPU_CACHE_VIPT + select CPU_COPY_V6 if MMU select CPU_CP15_MMU select CPU_HAS_ASID if MMU - select CPU_COPY_V6 if MMU + select CPU_PABRT_V6 select CPU_TLB_V6 if MMU # ARMv7 @@ -385,44 +385,44 @@ config CPU_V7 select CPU_32v6K select CPU_32v7 select CPU_ABRT_EV7 - select CPU_PABRT_V7 select CPU_CACHE_V7 select CPU_CACHE_VIPT + select CPU_COPY_V6 if MMU select CPU_CP15_MMU select CPU_HAS_ASID if MMU - select CPU_COPY_V6 if MMU + select CPU_PABRT_V7 select CPU_TLB_V7 if MMU # Figure out what processor architecture version we should be using. # This defines the compiler instruction set which depends on the machine type. config CPU_32v3 bool - select TLS_REG_EMUL if SMP || !MMU - select NEEDS_SYSCALL_FOR_CMPXCHG if SMP select CPU_USE_DOMAINS if MMU + select NEEDS_SYSCALL_FOR_CMPXCHG if SMP + select TLS_REG_EMUL if SMP || !MMU config CPU_32v4 bool - select TLS_REG_EMUL if SMP || !MMU - select NEEDS_SYSCALL_FOR_CMPXCHG if SMP select CPU_USE_DOMAINS if MMU + select NEEDS_SYSCALL_FOR_CMPXCHG if SMP + select TLS_REG_EMUL if SMP || !MMU config CPU_32v4T bool - select TLS_REG_EMUL if SMP || !MMU - select NEEDS_SYSCALL_FOR_CMPXCHG if SMP select CPU_USE_DOMAINS if MMU + select NEEDS_SYSCALL_FOR_CMPXCHG if SMP + select TLS_REG_EMUL if SMP || !MMU config CPU_32v5 bool - select TLS_REG_EMUL if SMP || !MMU - select NEEDS_SYSCALL_FOR_CMPXCHG if SMP select CPU_USE_DOMAINS if MMU + select NEEDS_SYSCALL_FOR_CMPXCHG if SMP + select TLS_REG_EMUL if SMP || !MMU config CPU_32v6 bool - select TLS_REG_EMUL if !CPU_32v6K && !MMU select CPU_USE_DOMAINS if CPU_V6 && MMU + select TLS_REG_EMUL if !CPU_32v6K && !MMU config CPU_32v6K bool @@ -624,11 +624,28 @@ config ARM_THUMBEE Say Y here if you have a CPU with the ThumbEE extension and code to make use of it. Say N for code that can run on CPUs without ThumbEE. +config ARM_VIRT_EXT + bool "Native support for the ARM Virtualization Extensions" + depends on MMU && CPU_V7 + help + Enable the kernel to make use of the ARM Virtualization + Extensions to install hypervisors without run-time firmware + assistance. + + A compliant bootloader is required in order to make maximum + use of this feature. Refer to Documentation/arm/Booting for + details. + + It is safe to enable this option even if the kernel may not be + booted in HYP mode, may not have support for the + virtualization extensions, or may be booted with a + non-compliant bootloader. + config SWP_EMULATE bool "Emulate SWP/SWPB instructions" depends on !CPU_USE_DOMAINS && CPU_V7 - select HAVE_PROC_CPU if PROC_FS default y if SMP + select HAVE_PROC_CPU if PROC_FS help ARMv6 architecture deprecates use of the SWP/SWPB instructions. ARMv7 multiprocessing extensions introduce the ability to disable diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c index 9107231aacc5..023f443784ec 100644 --- a/arch/arm/mm/alignment.c +++ b/arch/arm/mm/alignment.c @@ -699,7 +699,6 @@ do_alignment_t32_to_handler(unsigned long *pinstr, struct pt_regs *regs, unsigned long instr = *pinstr; u16 tinst1 = (instr >> 16) & 0xffff; u16 tinst2 = instr & 0xffff; - poffset->un = 0; switch (tinst1 & 0xffe0) { /* A6.3.5 Load/Store multiple */ @@ -854,10 +853,13 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs) break; case 0x08000000: /* ldm or stm, or thumb-2 32bit instruction */ - if (thumb2_32b) + if (thumb2_32b) { + offset.un = 0; handler = do_alignment_t32_to_handler(&instr, regs, &offset); - else + } else { + offset.un = 0; handler = do_alignment_ldmstm; + } break; default: diff --git a/arch/arm/mm/cache-fa.S b/arch/arm/mm/cache-fa.S index 072016371093..e505befe51b5 100644 --- a/arch/arm/mm/cache-fa.S +++ b/arch/arm/mm/cache-fa.S @@ -240,6 +240,9 @@ ENTRY(fa_dma_unmap_area) mov pc, lr ENDPROC(fa_dma_unmap_area) + .globl fa_flush_kern_cache_louis + .equ fa_flush_kern_cache_louis, fa_flush_kern_cache_all + __INITDATA @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 577baf7d0a8d..8a97e6443c62 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -368,14 +368,18 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) /* l2x0 controller is disabled */ writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL); - l2x0_saved_regs.aux_ctrl = aux; - l2x0_inv_all(); /* enable L2X0 */ writel_relaxed(1, l2x0_base + L2X0_CTRL); } + /* Re-read it in case some bits are reserved. */ + aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); + + /* Save the value for resuming. */ + l2x0_saved_regs.aux_ctrl = aux; + outer_cache.inv_range = l2x0_inv_range; outer_cache.clean_range = l2x0_clean_range; outer_cache.flush_range = l2x0_flush_range; diff --git a/arch/arm/mm/cache-v3.S b/arch/arm/mm/cache-v3.S index 52e35f32eefb..8a3fadece8d3 100644 --- a/arch/arm/mm/cache-v3.S +++ b/arch/arm/mm/cache-v3.S @@ -128,6 +128,9 @@ ENTRY(v3_dma_map_area) ENDPROC(v3_dma_unmap_area) ENDPROC(v3_dma_map_area) + .globl v3_flush_kern_cache_louis + .equ v3_flush_kern_cache_louis, v3_flush_kern_cache_all + __INITDATA @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) diff --git a/arch/arm/mm/cache-v4.S b/arch/arm/mm/cache-v4.S index 022135d2b7e4..43e5d77be677 100644 --- a/arch/arm/mm/cache-v4.S +++ b/arch/arm/mm/cache-v4.S @@ -140,6 +140,9 @@ ENTRY(v4_dma_map_area) ENDPROC(v4_dma_unmap_area) ENDPROC(v4_dma_map_area) + .globl v4_flush_kern_cache_louis + .equ v4_flush_kern_cache_louis, v4_flush_kern_cache_all + __INITDATA @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) diff --git a/arch/arm/mm/cache-v4wb.S b/arch/arm/mm/cache-v4wb.S index 8f1eeae340c8..cd4945321407 100644 --- a/arch/arm/mm/cache-v4wb.S +++ b/arch/arm/mm/cache-v4wb.S @@ -251,6 +251,9 @@ ENTRY(v4wb_dma_unmap_area) mov pc, lr ENDPROC(v4wb_dma_unmap_area) + .globl v4wb_flush_kern_cache_louis + .equ v4wb_flush_kern_cache_louis, v4wb_flush_kern_cache_all + __INITDATA @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) diff --git a/arch/arm/mm/cache-v4wt.S b/arch/arm/mm/cache-v4wt.S index b34a5f908a82..11e5e5838bc5 100644 --- a/arch/arm/mm/cache-v4wt.S +++ b/arch/arm/mm/cache-v4wt.S @@ -196,6 +196,9 @@ ENTRY(v4wt_dma_map_area) ENDPROC(v4wt_dma_unmap_area) ENDPROC(v4wt_dma_map_area) + .globl v4wt_flush_kern_cache_louis + .equ v4wt_flush_kern_cache_louis, v4wt_flush_kern_cache_all + __INITDATA @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S index 4b10760c56d6..d8fd4d4bd3d4 100644 --- a/arch/arm/mm/cache-v6.S +++ b/arch/arm/mm/cache-v6.S @@ -326,6 +326,9 @@ ENTRY(v6_dma_unmap_area) mov pc, lr ENDPROC(v6_dma_unmap_area) + .globl v6_flush_kern_cache_louis + .equ v6_flush_kern_cache_louis, v6_flush_kern_cache_all + __INITDATA @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 39e3fb3db801..cd956647c21a 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -33,6 +33,24 @@ ENTRY(v7_flush_icache_all) mov pc, lr ENDPROC(v7_flush_icache_all) + /* + * v7_flush_dcache_louis() + * + * Flush the D-cache up to the Level of Unification Inner Shareable + * + * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode) + */ + +ENTRY(v7_flush_dcache_louis) + dmb @ ensure ordering with previous memory accesses + mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr + ands r3, r0, #0xe00000 @ extract LoUIS from clidr + mov r3, r3, lsr #20 @ r3 = LoUIS * 2 + moveq pc, lr @ return if level == 0 + mov r10, #0 @ r10 (starting level) = 0 + b flush_levels @ start flushing cache levels +ENDPROC(v7_flush_dcache_louis) + /* * v7_flush_dcache_all() * @@ -49,7 +67,7 @@ ENTRY(v7_flush_dcache_all) mov r3, r3, lsr #23 @ left align loc bit field beq finished @ if loc is 0, then no need to clean mov r10, #0 @ start clean at cache level 0 -loop1: +flush_levels: add r2, r10, r10, lsr #1 @ work out 3x current cache level mov r1, r0, lsr r2 @ extract cache type bits from clidr and r1, r1, #7 @ mask of the bits for current cache only @@ -71,9 +89,9 @@ loop1: clz r5, r4 @ find bit position of way size increment ldr r7, =0x7fff ands r7, r7, r1, lsr #13 @ extract max number of the index size -loop2: +loop1: mov r9, r4 @ create working copy of max way size -loop3: +loop2: ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11 THUMB( lsl r6, r9, r5 ) THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11 @@ -82,13 +100,13 @@ loop3: THUMB( orr r11, r11, r6 ) @ factor index number into r11 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way subs r9, r9, #1 @ decrement the way - bge loop3 - subs r7, r7, #1 @ decrement the index bge loop2 + subs r7, r7, #1 @ decrement the index + bge loop1 skip: add r10, r10, #2 @ increment cache number cmp r3, r10 - bgt loop1 + bgt flush_levels finished: mov r10, #0 @ swith back to cache level 0 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr @@ -120,6 +138,24 @@ ENTRY(v7_flush_kern_cache_all) mov pc, lr ENDPROC(v7_flush_kern_cache_all) + /* + * v7_flush_kern_cache_louis(void) + * + * Flush the data cache up to Level of Unification Inner Shareable. + * Invalidate the I-cache to the point of unification. + */ +ENTRY(v7_flush_kern_cache_louis) + ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} ) + THUMB( stmfd sp!, {r4-r7, r9-r11, lr} ) + bl v7_flush_dcache_louis + mov r0, #0 + ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable + ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate + ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} ) + THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} ) + mov pc, lr +ENDPROC(v7_flush_kern_cache_louis) + /* * v7_flush_cache_all() * @@ -211,6 +247,9 @@ ENTRY(v7_coherent_user_range) * isn't mapped, fail with -EFAULT. */ 9001: +#ifdef CONFIG_ARM_ERRATA_775420 + dsb +#endif mov r0, #-EFAULT mov pc, lr UNWIND(.fnend ) diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index 477a2d23ddf1..58bc3e4d3bd0 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -610,7 +610,7 @@ static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp, pgprot_t prot, bool is_coherent, const void *caller) { u64 mask = get_coherent_dma_mask(dev); - struct page *page; + struct page *page = NULL; void *addr; #ifdef CONFIG_DMA_API_DEBUG diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c index 7599e2625c7d..2a5907b5c8d2 100644 --- a/arch/arm/mm/fault-armv.c +++ b/arch/arm/mm/fault-armv.c @@ -134,7 +134,6 @@ make_coherent(struct address_space *mapping, struct vm_area_struct *vma, { struct mm_struct *mm = vma->vm_mm; struct vm_area_struct *mpnt; - struct prio_tree_iter iter; unsigned long offset; pgoff_t pgoff; int aliases = 0; @@ -147,7 +146,7 @@ make_coherent(struct address_space *mapping, struct vm_area_struct *vma, * cache coherency. */ flush_dcache_mmap_lock(mapping); - vma_prio_tree_foreach(mpnt, &iter, &mapping->i_mmap, pgoff, pgoff) { + vma_interval_tree_foreach(mpnt, &mapping->i_mmap, pgoff, pgoff) { /* * If this VMA is not in our MM, we can ignore it. * Note that we intentionally mask out the VMA diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c index c3bd83450227..5dbf13f954f6 100644 --- a/arch/arm/mm/fault.c +++ b/arch/arm/mm/fault.c @@ -336,6 +336,7 @@ retry: /* Clear FAULT_FLAG_ALLOW_RETRY to avoid any risk * of starvation. */ flags &= ~FAULT_FLAG_ALLOW_RETRY; + flags |= FAULT_FLAG_TRIED; goto retry; } } diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c index 40ca11ed6e5f..1c8f7f564175 100644 --- a/arch/arm/mm/flush.c +++ b/arch/arm/mm/flush.c @@ -196,7 +196,6 @@ static void __flush_dcache_aliases(struct address_space *mapping, struct page *p { struct mm_struct *mm = current->active_mm; struct vm_area_struct *mpnt; - struct prio_tree_iter iter; pgoff_t pgoff; /* @@ -208,7 +207,7 @@ static void __flush_dcache_aliases(struct address_space *mapping, struct page *p pgoff = page->index << (PAGE_CACHE_SHIFT - PAGE_SHIFT); flush_dcache_mmap_lock(mapping); - vma_prio_tree_foreach(mpnt, &iter, &mapping->i_mmap, pgoff, pgoff) { + vma_interval_tree_foreach(mpnt, &mapping->i_mmap, pgoff, pgoff) { unsigned long offset; /* diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index 9aec41fa80ae..ad722f1208a5 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c @@ -324,7 +324,7 @@ phys_addr_t __init arm_memblock_steal(phys_addr_t size, phys_addr_t align) BUG_ON(!arm_memblock_steal_permitted); - phys = memblock_alloc(size, align); + phys = memblock_alloc_base(size, align, MEMBLOCK_ALLOC_ANYWHERE); memblock_free(phys, size); memblock_remove(phys, size); diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c index 9d869f93a3da..5dcc2fd46c46 100644 --- a/arch/arm/mm/ioremap.c +++ b/arch/arm/mm/ioremap.c @@ -248,6 +248,7 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn, if (!area) return NULL; addr = (unsigned long)area->addr; + area->phys_addr = __pfn_to_phys(pfn); #if !defined(CONFIG_SMP) && !defined(CONFIG_ARM_LPAE) if (DOMAIN_IO == 0 && diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S index 0650bb87c1e3..2bb61e703d6c 100644 --- a/arch/arm/mm/proc-arm1020.S +++ b/arch/arm/mm/proc-arm1020.S @@ -368,6 +368,9 @@ ENTRY(arm1020_dma_unmap_area) mov pc, lr ENDPROC(arm1020_dma_unmap_area) + .globl arm1020_flush_kern_cache_louis + .equ arm1020_flush_kern_cache_louis, arm1020_flush_kern_cache_all + @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) define_cache_functions arm1020 diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S index 4188478325a6..8f96aa40f510 100644 --- a/arch/arm/mm/proc-arm1020e.S +++ b/arch/arm/mm/proc-arm1020e.S @@ -354,6 +354,9 @@ ENTRY(arm1020e_dma_unmap_area) mov pc, lr ENDPROC(arm1020e_dma_unmap_area) + .globl arm1020e_flush_kern_cache_louis + .equ arm1020e_flush_kern_cache_louis, arm1020e_flush_kern_cache_all + @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) define_cache_functions arm1020e diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S index 33c68824bff0..8ebe4a469a22 100644 --- a/arch/arm/mm/proc-arm1022.S +++ b/arch/arm/mm/proc-arm1022.S @@ -343,6 +343,9 @@ ENTRY(arm1022_dma_unmap_area) mov pc, lr ENDPROC(arm1022_dma_unmap_area) + .globl arm1022_flush_kern_cache_louis + .equ arm1022_flush_kern_cache_louis, arm1022_flush_kern_cache_all + @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) define_cache_functions arm1022 diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S index fbc1d5fc24dc..093fc7e520c3 100644 --- a/arch/arm/mm/proc-arm1026.S +++ b/arch/arm/mm/proc-arm1026.S @@ -337,6 +337,9 @@ ENTRY(arm1026_dma_unmap_area) mov pc, lr ENDPROC(arm1026_dma_unmap_area) + .globl arm1026_flush_kern_cache_louis + .equ arm1026_flush_kern_cache_louis, arm1026_flush_kern_cache_all + @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) define_cache_functions arm1026 diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S index 1a8c138eb897..2c3b9421ab5e 100644 --- a/arch/arm/mm/proc-arm920.S +++ b/arch/arm/mm/proc-arm920.S @@ -319,6 +319,9 @@ ENTRY(arm920_dma_unmap_area) mov pc, lr ENDPROC(arm920_dma_unmap_area) + .globl arm920_flush_kern_cache_louis + .equ arm920_flush_kern_cache_louis, arm920_flush_kern_cache_all + @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) define_cache_functions arm920 #endif diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S index 4c44d7e1c3ca..4464c49d7449 100644 --- a/arch/arm/mm/proc-arm922.S +++ b/arch/arm/mm/proc-arm922.S @@ -321,6 +321,9 @@ ENTRY(arm922_dma_unmap_area) mov pc, lr ENDPROC(arm922_dma_unmap_area) + .globl arm922_flush_kern_cache_louis + .equ arm922_flush_kern_cache_louis, arm922_flush_kern_cache_all + @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) define_cache_functions arm922 #endif diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S index ec5b1180994f..281eb9b9c1d6 100644 --- a/arch/arm/mm/proc-arm925.S +++ b/arch/arm/mm/proc-arm925.S @@ -376,6 +376,9 @@ ENTRY(arm925_dma_unmap_area) mov pc, lr ENDPROC(arm925_dma_unmap_area) + .globl arm925_flush_kern_cache_louis + .equ arm925_flush_kern_cache_louis, arm925_flush_kern_cache_all + @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) define_cache_functions arm925 diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S index c31e62c606c0..f1803f7e2972 100644 --- a/arch/arm/mm/proc-arm926.S +++ b/arch/arm/mm/proc-arm926.S @@ -339,6 +339,9 @@ ENTRY(arm926_dma_unmap_area) mov pc, lr ENDPROC(arm926_dma_unmap_area) + .globl arm926_flush_kern_cache_louis + .equ arm926_flush_kern_cache_louis, arm926_flush_kern_cache_all + @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) define_cache_functions arm926 diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S index a613a7dd7146..8da189d4a402 100644 --- a/arch/arm/mm/proc-arm940.S +++ b/arch/arm/mm/proc-arm940.S @@ -267,6 +267,9 @@ ENTRY(arm940_dma_unmap_area) mov pc, lr ENDPROC(arm940_dma_unmap_area) + .globl arm940_flush_kern_cache_louis + .equ arm940_flush_kern_cache_louis, arm940_flush_kern_cache_all + @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) define_cache_functions arm940 diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S index 9f4f2999fdd0..f666cf34075a 100644 --- a/arch/arm/mm/proc-arm946.S +++ b/arch/arm/mm/proc-arm946.S @@ -310,6 +310,9 @@ ENTRY(arm946_dma_unmap_area) mov pc, lr ENDPROC(arm946_dma_unmap_area) + .globl arm946_flush_kern_cache_louis + .equ arm946_flush_kern_cache_louis, arm946_flush_kern_cache_all + @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) define_cache_functions arm946 diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S index 23a8e4c7f2bd..4106b09e0c29 100644 --- a/arch/arm/mm/proc-feroceon.S +++ b/arch/arm/mm/proc-feroceon.S @@ -415,6 +415,9 @@ ENTRY(feroceon_dma_unmap_area) mov pc, lr ENDPROC(feroceon_dma_unmap_area) + .globl feroceon_flush_kern_cache_louis + .equ feroceon_flush_kern_cache_louis, feroceon_flush_kern_cache_all + @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) define_cache_functions feroceon @@ -431,6 +434,7 @@ ENDPROC(feroceon_dma_unmap_area) range_alias flush_icache_all range_alias flush_user_cache_all range_alias flush_kern_cache_all + range_alias flush_kern_cache_louis range_alias flush_user_cache_range range_alias coherent_kern_range range_alias coherent_user_range diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S index 2d8ff3ad86d3..b29a2265af01 100644 --- a/arch/arm/mm/proc-macros.S +++ b/arch/arm/mm/proc-macros.S @@ -299,6 +299,7 @@ ENTRY(\name\()_processor_functions) ENTRY(\name\()_cache_fns) .long \name\()_flush_icache_all .long \name\()_flush_kern_cache_all + .long \name\()_flush_kern_cache_louis .long \name\()_flush_user_cache_all .long \name\()_flush_user_cache_range .long \name\()_coherent_kern_range diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S index fbb2124a547d..82f9cdc751d6 100644 --- a/arch/arm/mm/proc-mohawk.S +++ b/arch/arm/mm/proc-mohawk.S @@ -303,6 +303,9 @@ ENTRY(mohawk_dma_unmap_area) mov pc, lr ENDPROC(mohawk_dma_unmap_area) + .globl mohawk_flush_kern_cache_louis + .equ mohawk_flush_kern_cache_louis, mohawk_flush_kern_cache_all + @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) define_cache_functions mohawk diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index c2e2b66f72b5..846d279f3176 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -172,7 +172,7 @@ __v7_ca15mp_setup: __v7_setup: adr r12, __v7_setup_stack @ the local stack stmia r12, {r0-r5, r7, r9, r11, lr} - bl v7_flush_dcache_all + bl v7_flush_dcache_louis ldmia r12, {r0-r5, r7, r9, r11, lr} mrc p15, 0, r0, c0, c0, 0 @ read main ID register diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S index b0d57869da2d..eb93d6487f35 100644 --- a/arch/arm/mm/proc-xsc3.S +++ b/arch/arm/mm/proc-xsc3.S @@ -337,6 +337,9 @@ ENTRY(xsc3_dma_unmap_area) mov pc, lr ENDPROC(xsc3_dma_unmap_area) + .globl xsc3_flush_kern_cache_louis + .equ xsc3_flush_kern_cache_louis, xsc3_flush_kern_cache_all + @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) define_cache_functions xsc3 diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S index 4ffebaa595ee..25510361aa18 100644 --- a/arch/arm/mm/proc-xscale.S +++ b/arch/arm/mm/proc-xscale.S @@ -410,6 +410,9 @@ ENTRY(xscale_dma_unmap_area) mov pc, lr ENDPROC(xscale_dma_unmap_area) + .globl xscale_flush_kern_cache_louis + .equ xscale_flush_kern_cache_louis, xscale_flush_kern_cache_all + @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) define_cache_functions xscale @@ -439,6 +442,7 @@ ENDPROC(xscale_dma_unmap_area) a0_alias flush_icache_all a0_alias flush_user_cache_all a0_alias flush_kern_cache_all + a0_alias flush_kern_cache_louis a0_alias flush_user_cache_range a0_alias coherent_kern_range a0_alias coherent_user_range diff --git a/arch/arm/mm/vmregion.h b/arch/arm/mm/vmregion.h index bf312c354a21..0f5a5f2a2c7b 100644 --- a/arch/arm/mm/vmregion.h +++ b/arch/arm/mm/vmregion.h @@ -17,7 +17,6 @@ struct arm_vmregion { struct list_head vm_list; unsigned long vm_start; unsigned long vm_end; - void *priv; int vm_active; const void *caller; }; diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index baf9064c0844..88e1e2e7a20d 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig @@ -10,16 +10,16 @@ choice config ARCH_IMX_V4_V5 bool "i.MX1, i.MX21, i.MX25, i.MX27" - select AUTO_ZRELADDR if !ZBOOT_ROM select ARM_PATCH_PHYS_VIRT + select AUTO_ZRELADDR if !ZBOOT_ROM help This enables support for systems based on the Freescale i.MX ARMv4 and ARMv5 SoCs config ARCH_IMX_V6_V7 bool "i.MX3, i.MX5, i.MX6" - select AUTO_ZRELADDR if !ZBOOT_ROM select ARM_PATCH_PHYS_VIRT + select AUTO_ZRELADDR if !ZBOOT_ROM select MIGHT_HAVE_CACHE_L2X0 help This enables support for systems based on the Freescale i.MX3, i.MX5 diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig index cb3e3eef55c0..a35d9841f494 100644 --- a/arch/arm/plat-mxc/devices/Kconfig +++ b/arch/arm/plat-mxc/devices/Kconfig @@ -3,8 +3,8 @@ config IMX_HAVE_PLATFORM_FEC default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX50 || SOC_IMX51 || SOC_IMX53 config IMX_HAVE_PLATFORM_FLEXCAN - select HAVE_CAN_FLEXCAN if CAN bool + select HAVE_CAN_FLEXCAN if CAN config IMX_HAVE_PLATFORM_FSL_USB2_UDC bool @@ -15,7 +15,11 @@ config IMX_HAVE_PLATFORM_GPIO_KEYS config IMX_HAVE_PLATFORM_IMX21_HCD bool - + +config IMX_HAVE_PLATFORM_IMX27_CODA + bool + default y if SOC_IMX27 + config IMX_HAVE_PLATFORM_IMX2_WDT bool diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile index c11ac8472beb..76f3195475d0 100644 --- a/arch/arm/plat-mxc/devices/Makefile +++ b/arch/arm/plat-mxc/devices/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC) += platform-fsl-usb2-udc.o obj-$(CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS) += platform-gpio_keys.o obj-y += platform-gpio-mxc.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX21_HCD) += platform-imx21-hcd.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX27_CODA) += platform-imx27-coda.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMXDI_RTC) += platform-imxdi_rtc.o obj-y += platform-imx-dma.o diff --git a/arch/arm/plat-mxc/devices/platform-imx27-coda.c b/arch/arm/plat-mxc/devices/platform-imx27-coda.c new file mode 100644 index 000000000000..8b12aacdf396 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx27-coda.c @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2012 Vista Silicon + * Javier Martin <javier.martin@vista-silicon.com> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ + +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#ifdef CONFIG_SOC_IMX27 +const struct imx_imx27_coda_data imx27_coda_data __initconst = { + .iobase = MX27_VPU_BASE_ADDR, + .iosize = SZ_512, + .irq = MX27_INT_VPU, +}; +#endif + +struct platform_device *__init imx_add_imx27_coda( + const struct imx_imx27_coda_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + return imx_add_platform_device_dmamask("coda-imx27", 0, res, 2, NULL, + 0, DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/devices/platform-mxc-mmc.c b/arch/arm/plat-mxc/devices/platform-mxc-mmc.c index 540d3a7d92df..e7b920b58675 100644 --- a/arch/arm/plat-mxc/devices/platform-mxc-mmc.c +++ b/arch/arm/plat-mxc/devices/platform-mxc-mmc.c @@ -55,7 +55,7 @@ struct platform_device *__init imx_add_mxc_mmc( struct resource res[] = { { .start = data->iobase, - .end = data->iobase + SZ_4K - 1, + .end = data->iobase + data->iosize - 1, .flags = IORESOURCE_MEM, }, { .start = data->irq, diff --git a/arch/arm/plat-mxc/devices/platform-mxc_nand.c b/arch/arm/plat-mxc/devices/platform-mxc_nand.c index 1568f39fba8b..95b75cc70515 100644 --- a/arch/arm/plat-mxc/devices/platform-mxc_nand.c +++ b/arch/arm/plat-mxc/devices/platform-mxc_nand.c @@ -63,10 +63,6 @@ struct platform_device *__init imx_add_mxc_nand( /* AXI has to come first, that's how the mxc_nand driver expect it */ struct resource res[] = { { - .start = data->axibase, - .end = data->axibase + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, { .start = data->iobase, .end = data->iobase + data->iosize - 1, .flags = IORESOURCE_MEM, @@ -74,10 +70,13 @@ struct platform_device *__init imx_add_mxc_nand( .start = data->irq, .end = data->irq, .flags = IORESOURCE_IRQ, + }, { + .start = data->axibase, + .end = data->axibase + SZ_16K - 1, + .flags = IORESOURCE_MEM, }, }; return imx_add_platform_device("mxc_nand", data->id, - res + !data->axibase, - ARRAY_SIZE(res) - !data->axibase, + res, ARRAY_SIZE(res) - !data->axibase, pdata, sizeof(*pdata)); } diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index 9e3e3d8ae8c2..eaf79d220c9a 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -83,6 +83,14 @@ struct platform_device *__init imx_add_imx21_hcd( const struct imx_imx21_hcd_data *data, const struct mx21_usbh_platform_data *pdata); +struct imx_imx27_coda_data { + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; +struct platform_device *__init imx_add_imx27_coda( + const struct imx_imx27_coda_data *data); + struct imx_imx2_wdt_data { int id; resource_size_t iobase; diff --git a/arch/arm/plat-nomadik/Kconfig b/arch/arm/plat-nomadik/Kconfig index 4c48c8b60b54..19f55cae5d73 100644 --- a/arch/arm/plat-nomadik/Kconfig +++ b/arch/arm/plat-nomadik/Kconfig @@ -5,8 +5,8 @@ config PLAT_NOMADIK bool depends on ARCH_NOMADIK || ARCH_U8500 - select CLKSRC_MMIO default y + select CLKSRC_MMIO help Common platform code for Nomadik and other ST-Ericsson platforms. diff --git a/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h b/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h index 826de74bfdd1..c08a54d9d889 100644 --- a/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h +++ b/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h @@ -45,6 +45,12 @@ #define NMK_GPIO_ALT_B 2 #define NMK_GPIO_ALT_C (NMK_GPIO_ALT_A | NMK_GPIO_ALT_B) +#define NMK_GPIO_ALT_CX_SHIFT 2 +#define NMK_GPIO_ALT_C1 ((1<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C) +#define NMK_GPIO_ALT_C2 ((2<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C) +#define NMK_GPIO_ALT_C3 ((3<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C) +#define NMK_GPIO_ALT_C4 ((4<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C) + /* Pull up/down values */ enum nmk_gpio_pull { NMK_GPIO_PULL_NONE, diff --git a/arch/arm/plat-nomadik/include/plat/pincfg.h b/arch/arm/plat-nomadik/include/plat/pincfg.h index 9c949c7c98a7..3b8ec60af351 100644 --- a/arch/arm/plat-nomadik/include/plat/pincfg.h +++ b/arch/arm/plat-nomadik/include/plat/pincfg.h @@ -25,6 +25,8 @@ * bit 19..20 - SLPM direction * bit 21..22 - SLPM Value (if output) * bit 23..25 - PDIS value (if input) + * bit 26 - Gpio mode + * bit 27 - Sleep mode * * to facilitate the definition, the following macros are provided * diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index ca83a7659aef..82fcb206b5b2 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig @@ -14,10 +14,10 @@ config ARCH_OMAP1 select CLKDEV_LOOKUP select CLKSRC_MMIO select GENERIC_IRQ_CHIP - select IRQ_DOMAIN select HAVE_IDE - select NEED_MACH_MEMORY_H + select IRQ_DOMAIN select NEED_MACH_IO_H if PCCARD + select NEED_MACH_MEMORY_H help "Systems based on omap7xx, omap15xx or omap16xx" @@ -25,10 +25,11 @@ config ARCH_OMAP2PLUS bool "TI OMAP2/3/4" select CLKDEV_LOOKUP select GENERIC_IRQ_CHIP - select SPARSE_IRQ select OMAP_DM_TIMER - select USE_OF + select PINCTRL select PROC_DEVICETREE if PROC_FS + select SPARSE_IRQ + select USE_OF help "Systems based on OMAP2, OMAP3, OMAP4 or OMAP5" @@ -44,10 +45,12 @@ config OMAP_DEBUG_DEVICES config OMAP_DEBUG_LEDS def_bool y if NEW_LEDS depends on OMAP_DEBUG_DEVICES + select LEDS_CLASS config POWER_AVS_OMAP bool "AVS(Adaptive Voltage Scaling) support for OMAP IP versions 1&2" depends on POWER_AVS && (ARCH_OMAP3 || ARCH_OMAP4) && PM + select POWER_SUPPLY help Say Y to enable AVS(Adaptive Voltage Scaling) support on OMAP containing the version 1 or diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c index 706b7e29397f..9d7ac20ef8f9 100644 --- a/arch/arm/plat-omap/clock.c +++ b/arch/arm/plat-omap/clock.c @@ -312,33 +312,6 @@ void clk_enable_init_clocks(void) } } -/** - * omap_clk_get_by_name - locate OMAP struct clk by its name - * @name: name of the struct clk to locate - * - * Locate an OMAP struct clk by its name. Assumes that struct clk - * names are unique. Returns NULL if not found or a pointer to the - * struct clk if found. - */ -struct clk *omap_clk_get_by_name(const char *name) -{ - struct clk *c; - struct clk *ret = NULL; - - mutex_lock(&clocks_mutex); - - list_for_each_entry(c, &clocks, node) { - if (!strcmp(c->name, name)) { - ret = c; - break; - } - } - - mutex_unlock(&clocks_mutex); - - return ret; -} - int omap_clk_enable_autoidle_all(void) { struct clk *c; diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c index 2e826f1faf7b..87ba8dd0d791 100644 --- a/arch/arm/plat-omap/counter_32k.c +++ b/arch/arm/plat-omap/counter_32k.c @@ -52,22 +52,29 @@ static u32 notrace omap_32k_read_sched_clock(void) * nsecs and adds to a monotonically increasing timespec. */ static struct timespec persistent_ts; -static cycles_t cycles, last_cycles; +static cycles_t cycles; static unsigned int persistent_mult, persistent_shift; +static DEFINE_SPINLOCK(read_persistent_clock_lock); + static void omap_read_persistent_clock(struct timespec *ts) { unsigned long long nsecs; - cycles_t delta; - struct timespec *tsp = &persistent_ts; + cycles_t last_cycles; + unsigned long flags; + + spin_lock_irqsave(&read_persistent_clock_lock, flags); last_cycles = cycles; cycles = sync32k_cnt_reg ? __raw_readl(sync32k_cnt_reg) : 0; - delta = cycles - last_cycles; - nsecs = clocksource_cyc2ns(delta, persistent_mult, persistent_shift); + nsecs = clocksource_cyc2ns(cycles - last_cycles, + persistent_mult, persistent_shift); + + timespec_add_ns(&persistent_ts, nsecs); + + *ts = persistent_ts; - timespec_add_ns(tsp, nsecs); - *ts = *tsp; + spin_unlock_irqrestore(&read_persistent_clock_lock, flags); } /** diff --git a/arch/arm/plat-omap/debug-devices.c b/arch/arm/plat-omap/debug-devices.c index c7a4c0902b38..5a4678edd65a 100644 --- a/arch/arm/plat-omap/debug-devices.c +++ b/arch/arm/plat-omap/debug-devices.c @@ -16,6 +16,7 @@ #include <linux/smc91x.h> #include <mach/hardware.h> +#include "../mach-omap2/debug-devices.h" /* Many OMAP development platforms reuse the same "debug board"; these * platforms include H2, H3, H4, and Perseus2. diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c index 6013831a043e..a5683a84c6ee 100644 --- a/arch/arm/plat-omap/i2c.c +++ b/arch/arm/plat-omap/i2c.c @@ -26,14 +26,12 @@ #include <linux/kernel.h> #include <linux/platform_device.h> #include <linux/i2c.h> -#include <linux/i2c-omap.h> #include <linux/slab.h> #include <linux/err.h> #include <linux/clk.h> #include <mach/irqs.h> #include <plat/i2c.h> -#include <plat/omap-pm.h> #include <plat/omap_device.h> #define OMAP_I2C_SIZE 0x3f @@ -129,16 +127,6 @@ static inline int omap1_i2c_add_bus(int bus_id) #ifdef CONFIG_ARCH_OMAP2PLUS -/* - * XXX This function is a temporary compatibility wrapper - only - * needed until the I2C driver can be converted to call - * omap_pm_set_max_dev_wakeup_lat() and handle a return code. - */ -static void omap_pm_set_max_mpu_wakeup_lat_compat(struct device *dev, long t) -{ - omap_pm_set_max_mpu_wakeup_lat(dev, t); -} - static inline int omap2_i2c_add_bus(int bus_id) { int l; @@ -170,15 +158,6 @@ static inline int omap2_i2c_add_bus(int bus_id) dev_attr = (struct omap_i2c_dev_attr *)oh->dev_attr; pdata->flags = dev_attr->flags; - /* - * When waiting for completion of a i2c transfer, we need to - * set a wake up latency constraint for the MPU. This is to - * ensure quick enough wakeup from idle, when transfer - * completes. - * Only omap3 has support for constraints - */ - if (cpu_is_omap34xx()) - pdata->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat; pdev = omap_device_build(name, bus_id, oh, pdata, sizeof(struct omap_i2c_bus_platform_data), NULL, 0, 0); diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h index 656b9862279e..e2e2d045e428 100644 --- a/arch/arm/plat-omap/include/plat/clock.h +++ b/arch/arm/plat-omap/include/plat/clock.h @@ -19,6 +19,11 @@ struct module; struct clk; struct clockdomain; +/* Temporary, needed during the common clock framework conversion */ +#define __clk_get_name(clk) (clk->name) +#define __clk_get_parent(clk) (clk->parent) +#define __clk_get_rate(clk) (clk->rate) + /** * struct clkops - some clock function pointers * @enable: fn ptr that enables the current clock in hardware diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index 19e7fa577bd0..85868e98c11c 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -60,6 +60,7 @@ #define OMAP_TIMER_ALWON 0x40000000 #define OMAP_TIMER_HAS_PWM 0x20000000 #define OMAP_TIMER_NEEDS_RESET 0x10000000 +#define OMAP_TIMER_HAS_DSP_IRQ 0x08000000 struct omap_timer_capability_dev_attr { u32 timer_capability; diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h index 88be3e628b33..68b5f0362f35 100644 --- a/arch/arm/plat-omap/include/plat/iommu.h +++ b/arch/arm/plat-omap/include/plat/iommu.h @@ -103,6 +103,19 @@ struct iommu_functions { ssize_t (*dump_ctx)(struct omap_iommu *obj, char *buf, ssize_t len); }; +/** + * struct omap_mmu_dev_attr - OMAP mmu device attributes for omap_hwmod + * @da_start: device address where the va space starts. + * @da_end: device address where the va space ends. + * @nr_tlb_entries: number of entries supported by the translation + * look-aside buffer (TLB). + */ +struct omap_mmu_dev_attr { + u32 da_start; + u32 da_end; + int nr_tlb_entries; +}; + struct iommu_platform_data { const char *name; const char *clk_name; @@ -126,6 +139,7 @@ struct omap_iommu_arch_data { struct omap_iommu *iommu_dev; }; +#ifdef CONFIG_IOMMU_API /** * dev_to_omap_iommu() - retrieves an omap iommu object from a user device * @dev: iommu client device @@ -136,6 +150,7 @@ static inline struct omap_iommu *dev_to_omap_iommu(struct device *dev) return arch_data->iommu_dev; } +#endif /* IOMMU errors */ #define OMAP_IOMMU_ERR_TLB_MISS (1 << 0) diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h index f4a4cd014795..1957a8516e93 100644 --- a/arch/arm/plat-omap/include/plat/omap-serial.h +++ b/arch/arm/plat-omap/include/plat/omap-serial.h @@ -40,10 +40,10 @@ #define OMAP_UART_WER_MOD_WKUP 0X7F /* Enable XON/XOFF flow control on output */ -#define OMAP_UART_SW_TX 0x8 +#define OMAP_UART_SW_TX 0x04 /* Enable XON/XOFF flow control on input */ -#define OMAP_UART_SW_RX 0x2 +#define OMAP_UART_SW_RX 0x04 #define OMAP_UART_SYSC_RESET 0X07 #define OMAP_UART_TCR_TRIG 0X0F diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h index e7259c0d33ec..106f50665804 100644 --- a/arch/arm/plat-omap/include/plat/omap_device.h +++ b/arch/arm/plat-omap/include/plat/omap_device.h @@ -120,6 +120,10 @@ int omap_device_get_context_loss_count(struct platform_device *pdev); /* Other */ +int omap_device_assert_hardreset(struct platform_device *pdev, + const char *name); +int omap_device_deassert_hardreset(struct platform_device *pdev, + const char *name); int omap_device_idle_hwmods(struct omap_device *od); int omap_device_enable_hwmods(struct omap_device *od); diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index 05330735f23f..b3349f7b1a2c 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -2,7 +2,7 @@ * omap_hwmod macros, structures * * Copyright (C) 2009-2011 Nokia Corporation - * Copyright (C) 2011 Texas Instruments, Inc. + * Copyright (C) 2012 Texas Instruments, Inc. * Paul Walmsley * * Created in collaboration with (alphabetical order): Benoît Cousson, @@ -384,21 +384,38 @@ struct omap_hwmod_omap2_prcm { u8 idlest_stdby_bit; }; +/* + * Possible values for struct omap_hwmod_omap4_prcm.flags + * + * HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT: Some IP blocks don't have a PRCM + * module-level context loss register associated with them; this + * flag bit should be set in those cases + */ +#define HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT (1 << 0) /** * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data * @clkctrl_reg: PRCM address of the clock control register * @rstctrl_reg: address of the XXX_RSTCTRL register located in the PRM + * @lostcontext_mask: bitmask for selecting bits from RM_*_CONTEXT register * @rstst_reg: (AM33XX only) address of the XXX_RSTST register in the PRM * @submodule_wkdep_bit: bit shift of the WKDEP range + * @flags: PRCM register capabilities for this IP block + * + * If @lostcontext_mask is not defined, context loss check code uses + * whole register without masking. @lostcontext_mask should only be + * defined in cases where @context_offs register is shared by two or + * more hwmods. */ struct omap_hwmod_omap4_prcm { u16 clkctrl_offs; u16 rstctrl_offs; u16 rstst_offs; u16 context_offs; + u32 lostcontext_mask; u8 submodule_wkdep_bit; u8 modulemode; + u8 flags; }; @@ -591,9 +608,7 @@ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), int __init omap_hwmod_setup_one(const char *name); int omap_hwmod_enable(struct omap_hwmod *oh); -int _omap_hwmod_enable(struct omap_hwmod *oh); int omap_hwmod_idle(struct omap_hwmod *oh); -int _omap_hwmod_idle(struct omap_hwmod *oh); int omap_hwmod_shutdown(struct omap_hwmod *oh); int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name); @@ -627,11 +642,6 @@ int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh, int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh); -int omap_hwmod_set_clockact_both(struct omap_hwmod *oh); -int omap_hwmod_set_clockact_main(struct omap_hwmod *oh); -int omap_hwmod_set_clockact_iclk(struct omap_hwmod *oh); -int omap_hwmod_set_clockact_none(struct omap_hwmod *oh); - int omap_hwmod_enable_wakeup(struct omap_hwmod *oh); int omap_hwmod_disable_wakeup(struct omap_hwmod *oh); diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h index bd20588c356b..87ee140fefaa 100644 --- a/arch/arm/plat-omap/include/plat/usb.h +++ b/arch/arm/plat-omap/include/plat/usb.h @@ -4,6 +4,7 @@ #define __ASM_ARCH_OMAP_USB_H #include <linux/io.h> +#include <linux/platform_device.h> #include <linux/usb/musb.h> #define OMAP3_HS_USB_PORTS 3 @@ -63,6 +64,10 @@ struct usbhs_omap_platform_data { struct ehci_hcd_omap_platform_data *ehci_data; struct ohci_hcd_omap_platform_data *ohci_data; }; + +struct usbtll_omap_platform_data { + enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS]; +}; /*-------------------------------------------------------------------------*/ struct omap_musb_board_data { @@ -81,6 +86,8 @@ enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI}; extern void usb_musb_init(struct omap_musb_board_data *board_data); extern void usbhs_init(const struct usbhs_omap_board_data *pdata); +extern int omap_tll_enable(void); +extern int omap_tll_disable(void); extern int omap4430_phy_power(struct device *dev, int ID, int on); extern int omap4430_phy_set_clk(struct device *dev, int on); diff --git a/arch/arm/plat-omap/omap-pm-noop.c b/arch/arm/plat-omap/omap-pm-noop.c index 9f6413324df9..9722f418ae1f 100644 --- a/arch/arm/plat-omap/omap-pm-noop.c +++ b/arch/arm/plat-omap/omap-pm-noop.c @@ -38,7 +38,7 @@ int omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t) if (!dev || t < -1) { WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__); return -EINVAL; - }; + } if (t == -1) pr_debug("OMAP PM: remove max MPU wakeup latency constraint: dev %s\n", @@ -67,7 +67,7 @@ int omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r) agent_id != OCP_TARGET_AGENT)) { WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__); return -EINVAL; - }; + } if (r == 0) pr_debug("OMAP PM: remove min bus tput constraint: dev %s for agent_id %d\n", @@ -93,7 +93,7 @@ int omap_pm_set_max_dev_wakeup_lat(struct device *req_dev, struct device *dev, if (!req_dev || !dev || t < -1) { WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__); return -EINVAL; - }; + } if (t == -1) pr_debug("OMAP PM: remove max device latency constraint: dev %s\n", @@ -123,7 +123,7 @@ int omap_pm_set_max_sdma_lat(struct device *dev, long t) if (!dev || t < -1) { WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__); return -EINVAL; - }; + } if (t == -1) pr_debug("OMAP PM: remove max DMA latency constraint: dev %s\n", diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c index d5f617c542d3..7a7d1f2a65e9 100644 --- a/arch/arm/plat-omap/omap_device.c +++ b/arch/arm/plat-omap/omap_device.c @@ -261,10 +261,10 @@ static void _add_clkdev(struct omap_device *od, const char *clk_alias, return; } - r = omap_clk_get_by_name(clk_name); + r = clk_get(NULL, clk_name); if (IS_ERR(r)) { dev_err(&od->pdev->dev, - "omap_clk_get_by_name for %s failed\n", clk_name); + "clk_get for %s failed\n", clk_name); return; } @@ -725,7 +725,7 @@ struct platform_device __init *omap_device_build_ss(const char *pdev_name, int p dev_set_name(&pdev->dev, "%s", pdev->name); od = omap_device_alloc(pdev, ohs, oh_cnt, pm_lats, pm_lats_cnt); - if (!od) + if (IS_ERR(od)) goto odbs_exit1; ret = platform_device_add_data(pdev, pdata, pdata_len); @@ -983,6 +983,61 @@ int omap_device_shutdown(struct platform_device *pdev) } /** + * omap_device_assert_hardreset - set a device's hardreset line + * @pdev: struct platform_device * to reset + * @name: const char * name of the reset line + * + * Set the hardreset line identified by @name on the IP blocks + * associated with the hwmods backing the platform_device @pdev. All + * of the hwmods associated with @pdev must have the same hardreset + * line linked to them for this to work. Passes along the return value + * of omap_hwmod_assert_hardreset() in the event of any failure, or + * returns 0 upon success. + */ +int omap_device_assert_hardreset(struct platform_device *pdev, const char *name) +{ + struct omap_device *od = to_omap_device(pdev); + int ret = 0; + int i; + + for (i = 0; i < od->hwmods_cnt; i++) { + ret = omap_hwmod_assert_hardreset(od->hwmods[i], name); + if (ret) + break; + } + + return ret; +} + +/** + * omap_device_deassert_hardreset - release a device's hardreset line + * @pdev: struct platform_device * to reset + * @name: const char * name of the reset line + * + * Release the hardreset line identified by @name on the IP blocks + * associated with the hwmods backing the platform_device @pdev. All + * of the hwmods associated with @pdev must have the same hardreset + * line linked to them for this to work. Passes along the return + * value of omap_hwmod_deassert_hardreset() in the event of any + * failure, or returns 0 upon success. + */ +int omap_device_deassert_hardreset(struct platform_device *pdev, + const char *name) +{ + struct omap_device *od = to_omap_device(pdev); + int ret = 0; + int i; + + for (i = 0; i < od->hwmods_cnt; i++) { + ret = omap_hwmod_deassert_hardreset(od->hwmods[i], name); + if (ret) + break; + } + + return ret; +} + +/** * omap_device_align_pm_lat - activate/deactivate device to match wakeup lat lim * @od: struct omap_device * * diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile index c20ce0f5ce33..a82cecb84948 100644 --- a/arch/arm/plat-orion/Makefile +++ b/arch/arm/plat-orion/Makefile @@ -1,10 +1,10 @@ # # Makefile for the linux kernel. # +ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include -obj-y := irq.o pcie.o time.o common.o mpp.o addr-map.o -obj-m := -obj-n := -obj- := +obj-y += addr-map.o -obj-$(CONFIG_GENERIC_GPIO) += gpio.o +orion-gpio-$(CONFIG_GENERIC_GPIO) += gpio.o +obj-$(CONFIG_PLAT_ORION_LEGACY) += irq.o pcie.o time.o common.o mpp.o +obj-$(CONFIG_PLAT_ORION_LEGACY) += $(orion-gpio-y) diff --git a/arch/arm/plat-orion/addr-map.c b/arch/arm/plat-orion/addr-map.c index 367ca89ac403..a7b8060c293a 100644 --- a/arch/arm/plat-orion/addr-map.c +++ b/arch/arm/plat-orion/addr-map.c @@ -48,7 +48,7 @@ EXPORT_SYMBOL_GPL(mv_mbus_dram_info); static void __init __iomem * orion_win_cfg_base(const struct orion_addr_map_cfg *cfg, int win) { - return (void __iomem *)(cfg->bridge_virt_base + (win << 4)); + return cfg->bridge_virt_base + (win << 4); } /* @@ -143,19 +143,16 @@ void __init orion_config_wins(struct orion_addr_map_cfg * cfg, * Setup MBUS dram target info. */ void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg, - const u32 ddr_window_cpu_base) + const void __iomem *ddr_window_cpu_base) { - void __iomem *addr; int i; int cs; orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; - addr = (void __iomem *)ddr_window_cpu_base; - for (i = 0, cs = 0; i < 4; i++) { - u32 base = readl(addr + DDR_BASE_CS_OFF(i)); - u32 size = readl(addr + DDR_SIZE_CS_OFF(i)); + u32 base = readl(ddr_window_cpu_base + DDR_BASE_CS_OFF(i)); + u32 size = readl(ddr_window_cpu_base + DDR_SIZE_CS_OFF(i)); /* * Chip select enabled? diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c index 87f53caef655..b8a688cad4c2 100644 --- a/arch/arm/plat-orion/common.c +++ b/arch/arm/plat-orion/common.c @@ -86,13 +86,13 @@ static void __init uart_complete( struct platform_device *orion_uart, struct plat_serial8250_port *data, struct resource *resources, - unsigned int membase, + void __iomem *membase, resource_size_t mapbase, unsigned int irq, struct clk *clk) { data->mapbase = mapbase; - data->membase = (void __iomem *)membase; + data->membase = membase; data->irq = irq; data->uartclk = uart_get_clk_rate(clk); orion_uart->dev.platform_data = data; @@ -120,7 +120,7 @@ static struct platform_device orion_uart0 = { .id = PLAT8250_DEV_PLATFORM, }; -void __init orion_uart0_init(unsigned int membase, +void __init orion_uart0_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, struct clk *clk) @@ -148,7 +148,7 @@ static struct platform_device orion_uart1 = { .id = PLAT8250_DEV_PLATFORM1, }; -void __init orion_uart1_init(unsigned int membase, +void __init orion_uart1_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, struct clk *clk) @@ -176,7 +176,7 @@ static struct platform_device orion_uart2 = { .id = PLAT8250_DEV_PLATFORM2, }; -void __init orion_uart2_init(unsigned int membase, +void __init orion_uart2_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, struct clk *clk) @@ -204,7 +204,7 @@ static struct platform_device orion_uart3 = { .id = 3, }; -void __init orion_uart3_init(unsigned int membase, +void __init orion_uart3_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, struct clk *clk) diff --git a/arch/arm/plat-orion/include/plat/addr-map.h b/arch/arm/plat-orion/include/plat/addr-map.h index fd556f77562c..ec63e4a627d0 100644 --- a/arch/arm/plat-orion/include/plat/addr-map.h +++ b/arch/arm/plat-orion/include/plat/addr-map.h @@ -16,7 +16,7 @@ extern struct mbus_dram_target_info orion_mbus_dram_info; struct orion_addr_map_cfg { const int num_wins; /* Total number of windows */ const int remappable_wins; - const u32 bridge_virt_base; + void __iomem *bridge_virt_base; /* If NULL, the default cpu_win_can_remap will be used, using the value in remappable_wins */ @@ -49,5 +49,5 @@ void __init orion_setup_cpu_win(const struct orion_addr_map_cfg *cfg, const u8 attr, const int remap); void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg, - const u32 ddr_window_cpu_base); + const void __iomem *ddr_window_cpu_base); #endif diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h index ae2377ef63e5..6bbc3fe5f58e 100644 --- a/arch/arm/plat-orion/include/plat/common.h +++ b/arch/arm/plat-orion/include/plat/common.h @@ -13,22 +13,22 @@ struct dsa_platform_data; -void __init orion_uart0_init(unsigned int membase, +void __init orion_uart0_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, struct clk *clk); -void __init orion_uart1_init(unsigned int membase, +void __init orion_uart1_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, struct clk *clk); -void __init orion_uart2_init(unsigned int membase, +void __init orion_uart2_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, struct clk *clk); -void __init orion_uart3_init(unsigned int membase, +void __init orion_uart3_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, struct clk *clk); diff --git a/arch/arm/plat-orion/include/plat/mpp.h b/arch/arm/plat-orion/include/plat/mpp.h index 723adce99f41..254552fee889 100644 --- a/arch/arm/plat-orion/include/plat/mpp.h +++ b/arch/arm/plat-orion/include/plat/mpp.h @@ -29,6 +29,6 @@ #define MPP_OUTPUT_MASK GENERIC_MPP(0, 0x0, 0, 1) void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask, - unsigned int mpp_max, unsigned int dev_bus); + unsigned int mpp_max, void __iomem *dev_bus); #endif diff --git a/arch/arm/plat-orion/include/plat/time.h b/arch/arm/plat-orion/include/plat/time.h index 4d5f1f6e18df..07527e417c62 100644 --- a/arch/arm/plat-orion/include/plat/time.h +++ b/arch/arm/plat-orion/include/plat/time.h @@ -11,9 +11,9 @@ #ifndef __PLAT_TIME_H #define __PLAT_TIME_H -void orion_time_set_base(u32 timer_base); +void orion_time_set_base(void __iomem *timer_base); -void orion_time_init(u32 bridge_base, u32 bridge_timer1_clr_mask, +void orion_time_init(void __iomem *bridge_base, u32 bridge_timer1_clr_mask, unsigned int irq, unsigned int tclk); diff --git a/arch/arm/plat-orion/mpp.c b/arch/arm/plat-orion/mpp.c index 7740bb31d662..e686fe76a96b 100644 --- a/arch/arm/plat-orion/mpp.c +++ b/arch/arm/plat-orion/mpp.c @@ -18,15 +18,15 @@ #include <plat/mpp.h> /* Address of the ith MPP control register */ -static __init unsigned long mpp_ctrl_addr(unsigned int i, - unsigned long dev_bus) +static __init void __iomem *mpp_ctrl_addr(unsigned int i, + void __iomem *dev_bus) { return dev_bus + (i) * 4; } void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask, - unsigned int mpp_max, unsigned int dev_bus) + unsigned int mpp_max, void __iomem *dev_bus) { unsigned int mpp_nr_regs = (1 + mpp_max/8); u32 mpp_ctrl[mpp_nr_regs]; diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c index 1ed8d1397fcf..0f4fa863dd55 100644 --- a/arch/arm/plat-orion/time.c +++ b/arch/arm/plat-orion/time.c @@ -180,13 +180,13 @@ static struct irqaction orion_timer_irq = { }; void __init -orion_time_set_base(u32 _timer_base) +orion_time_set_base(void __iomem *_timer_base) { - timer_base = (void __iomem *)_timer_base; + timer_base = _timer_base; } void __init -orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask, +orion_time_init(void __iomem *_bridge_base, u32 _bridge_timer1_clr_mask, unsigned int irq, unsigned int tclk) { u32 u; @@ -194,7 +194,7 @@ orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask, /* * Set SoC-specific data. */ - bridge_base = (void __iomem *)_bridge_base; + bridge_base = _bridge_base; bridge_timer1_clr_mask = _bridge_timer1_clr_mask; ticks_per_jiffy = (tclk + HZ/2) / HZ; diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig index 21bf6adb9198..eef3b6a2f8a8 100644 --- a/arch/arm/plat-s3c24xx/Kconfig +++ b/arch/arm/plat-s3c24xx/Kconfig @@ -6,8 +6,8 @@ config PLAT_S3C24XX bool depends on ARCH_S3C24XX default y - select NO_IOPORT select ARCH_REQUIRE_GPIOLIB + select NO_IOPORT select S3C_DEV_NAND help Base platform code for any Samsung S3C24XX device diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index 9c3b90c3538e..59401e1cc530 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -7,9 +7,9 @@ config PLAT_SAMSUNG bool depends on PLAT_S3C24XX || ARCH_S3C64XX || PLAT_S5P - select NO_IOPORT - select GENERIC_IRQ_CHIP default y + select GENERIC_IRQ_CHIP + select NO_IOPORT help Base platform code for all Samsung SoC based systems @@ -17,16 +17,16 @@ config PLAT_S5P bool depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS) default y - select ARM_VIC if !ARCH_EXYNOS + select ARCH_REQUIRE_GPIOLIB select ARM_GIC if ARCH_EXYNOS + select ARM_VIC if !ARCH_EXYNOS select GIC_NON_BANKED if ARCH_EXYNOS4 select NO_IOPORT - select ARCH_REQUIRE_GPIOLIB + select PLAT_SAMSUNG select S3C_GPIO_TRACK select S5P_GPIO_DRVSTR - select SAMSUNG_GPIOLIB_4BIT - select PLAT_SAMSUNG select SAMSUNG_CLKSRC + select SAMSUNG_GPIOLIB_4BIT select SAMSUNG_IRQ_VIC_TIMER help Base platform code for Samsung's S5P series SoC. @@ -423,10 +423,10 @@ config S3C_DMA config SAMSUNG_DMADEV bool + select ARM_AMBA select DMADEVICES select PL330_DMA if (ARCH_EXYNOS5 || ARCH_EXYNOS4 || CPU_S5PV210 || CPU_S5PC100 || \ CPU_S5P6450 || CPU_S5P6440) - select ARM_AMBA help Use DMA device engine for PL330 DMAC. diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c index c38d75489240..d088afa034e8 100644 --- a/arch/arm/plat-samsung/dma-ops.c +++ b/arch/arm/plat-samsung/dma-ops.c @@ -91,7 +91,8 @@ static int samsung_dmadev_prepare(unsigned ch, break; case DMA_CYCLIC: desc = dmaengine_prep_dma_cyclic(chan, param->buf, - param->len, param->period, param->direction); + param->len, param->period, param->direction, + DMA_PREP_INTERRUPT | DMA_CTRL_ACK); break; default: dev_err(&chan->dev->device, "unsupported format\n"); diff --git a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h deleted file mode 100644 index 4c3647f80057..000000000000 --- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h +++ /dev/null @@ -1,159 +0,0 @@ -/* arch/arm/plat-samsung/include/plat/regs-fb-v4.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C64XX - new-style framebuffer register definitions - * - * This is the register set for the new style framebuffer interface - * found from the S3C2443 onwards and specifically the S3C64XX series - * S3C6400 and S3C6410. - * - * The file contains the cpu specific items which change between whichever - * architecture is selected. See <plat/regs-fb.h> for the core definitions - * that are the same. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/* include the core definitions here, in case we really do need to - * override them at a later date. -*/ - -#include <plat/regs-fb.h> - -#define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */ -#define VIDCON1_FSTATUS_EVEN (1 << 15) - -/* Video timing controls */ -#define VIDTCON0 (0x10) -#define VIDTCON1 (0x14) -#define VIDTCON2 (0x18) - -/* Window position controls */ - -#define WINCON(_win) (0x20 + ((_win) * 4)) - -/* OSD1 and OSD4 do not have register D */ - -#define VIDOSD_BASE (0x40) - -#define VIDINTCON0 (0x130) - -/* WINCONx */ - -#define WINCONx_CSCWIDTH_MASK (0x3 << 26) -#define WINCONx_CSCWIDTH_SHIFT (26) -#define WINCONx_CSCWIDTH_WIDE (0x0 << 26) -#define WINCONx_CSCWIDTH_NARROW (0x3 << 26) - -#define WINCONx_ENLOCAL (1 << 22) -#define WINCONx_BUFSTATUS (1 << 21) -#define WINCONx_BUFSEL (1 << 20) -#define WINCONx_BUFAUTOEN (1 << 19) -#define WINCONx_YCbCr (1 << 13) - -#define WINCON1_LOCALSEL_CAMIF (1 << 23) - -#define WINCON2_LOCALSEL_CAMIF (1 << 23) -#define WINCON2_BLD_PIX (1 << 6) - -#define WINCON2_ALPHA_SEL (1 << 1) -#define WINCON2_BPPMODE_MASK (0xf << 2) -#define WINCON2_BPPMODE_SHIFT (2) -#define WINCON2_BPPMODE_1BPP (0x0 << 2) -#define WINCON2_BPPMODE_2BPP (0x1 << 2) -#define WINCON2_BPPMODE_4BPP (0x2 << 2) -#define WINCON2_BPPMODE_8BPP_1232 (0x4 << 2) -#define WINCON2_BPPMODE_16BPP_565 (0x5 << 2) -#define WINCON2_BPPMODE_16BPP_A1555 (0x6 << 2) -#define WINCON2_BPPMODE_16BPP_I1555 (0x7 << 2) -#define WINCON2_BPPMODE_18BPP_666 (0x8 << 2) -#define WINCON2_BPPMODE_18BPP_A1665 (0x9 << 2) -#define WINCON2_BPPMODE_19BPP_A1666 (0xa << 2) -#define WINCON2_BPPMODE_24BPP_888 (0xb << 2) -#define WINCON2_BPPMODE_24BPP_A1887 (0xc << 2) -#define WINCON2_BPPMODE_25BPP_A1888 (0xd << 2) -#define WINCON2_BPPMODE_28BPP_A4888 (0xd << 2) - -#define WINCON3_BLD_PIX (1 << 6) - -#define WINCON3_ALPHA_SEL (1 << 1) -#define WINCON3_BPPMODE_MASK (0xf << 2) -#define WINCON3_BPPMODE_SHIFT (2) -#define WINCON3_BPPMODE_1BPP (0x0 << 2) -#define WINCON3_BPPMODE_2BPP (0x1 << 2) -#define WINCON3_BPPMODE_4BPP (0x2 << 2) -#define WINCON3_BPPMODE_16BPP_565 (0x5 << 2) -#define WINCON3_BPPMODE_16BPP_A1555 (0x6 << 2) -#define WINCON3_BPPMODE_16BPP_I1555 (0x7 << 2) -#define WINCON3_BPPMODE_18BPP_666 (0x8 << 2) -#define WINCON3_BPPMODE_18BPP_A1665 (0x9 << 2) -#define WINCON3_BPPMODE_19BPP_A1666 (0xa << 2) -#define WINCON3_BPPMODE_24BPP_888 (0xb << 2) -#define WINCON3_BPPMODE_24BPP_A1887 (0xc << 2) -#define WINCON3_BPPMODE_25BPP_A1888 (0xd << 2) -#define WINCON3_BPPMODE_28BPP_A4888 (0xd << 2) - -#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5) -#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5) -#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5) - -#define DITHMODE (0x170) -#define WINxMAP(_win) (0x180 + ((_win) * 4)) - - -#define DITHMODE_R_POS_MASK (0x3 << 5) -#define DITHMODE_R_POS_SHIFT (5) -#define DITHMODE_R_POS_8BIT (0x0 << 5) -#define DITHMODE_R_POS_6BIT (0x1 << 5) -#define DITHMODE_R_POS_5BIT (0x2 << 5) - -#define DITHMODE_G_POS_MASK (0x3 << 3) -#define DITHMODE_G_POS_SHIFT (3) -#define DITHMODE_G_POS_8BIT (0x0 << 3) -#define DITHMODE_G_POS_6BIT (0x1 << 3) -#define DITHMODE_G_POS_5BIT (0x2 << 3) - -#define DITHMODE_B_POS_MASK (0x3 << 1) -#define DITHMODE_B_POS_SHIFT (1) -#define DITHMODE_B_POS_8BIT (0x0 << 1) -#define DITHMODE_B_POS_6BIT (0x1 << 1) -#define DITHMODE_B_POS_5BIT (0x2 << 1) - -#define DITHMODE_DITH_EN (1 << 0) - -#define WPALCON (0x1A0) - -/* Palette control */ -/* Note for S5PC100: you can still use those macros on WPALCON (aka WPALCON_L), - * but make sure that WPALCON_H W2PAL-W4PAL entries are zeroed out */ -#define WPALCON_W4PAL_16BPP_A555 (1 << 8) -#define WPALCON_W3PAL_16BPP_A555 (1 << 7) -#define WPALCON_W2PAL_16BPP_A555 (1 << 6) - - -/* Notes on per-window bpp settings - * - * Value Win0 Win1 Win2 Win3 Win 4 - * 0000 1(P) 1(P) 1(P) 1(P) 1(P) - * 0001 2(P) 2(P) 2(P) 2(P) 2(P) - * 0010 4(P) 4(P) 4(P) 4(P) -none- - * 0011 8(P) 8(P) -none- -none- -none- - * 0100 -none- 8(A232) 8(A232) -none- -none- - * 0101 16(565) 16(565) 16(565) 16(565) 16(565) - * 0110 -none- 16(A555) 16(A555) 16(A555) 16(A555) - * 0111 16(I555) 16(I565) 16(I555) 16(I555) 16(I555) - * 1000 18(666) 18(666) 18(666) 18(666) 18(666) - * 1001 -none- 18(A665) 18(A665) 18(A665) 16(A665) - * 1010 -none- 19(A666) 19(A666) 19(A666) 19(A666) - * 1011 24(888) 24(888) 24(888) 24(888) 24(888) - * 1100 -none- 24(A887) 24(A887) 24(A887) 24(A887) - * 1101 -none- 25(A888) 25(A888) 25(A888) 25(A888) - * 1110 -none- -none- -none- -none- -none- - * 1111 -none- -none- -none- -none- -none- -*/ diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h b/arch/arm/plat-samsung/include/plat/regs-fb.h deleted file mode 100644 index 9a78012d6f43..000000000000 --- a/arch/arm/plat-samsung/include/plat/regs-fb.h +++ /dev/null @@ -1,403 +0,0 @@ -/* arch/arm/plat-samsung/include/plat/regs-fb.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C Platform - new-style framebuffer register definitions - * - * This is the register set for the new style framebuffer interface - * found from the S3C2443 onwards into the S3C2416, S3C2450 and the - * S3C64XX series such as the S3C6400 and S3C6410. - * - * The file does not contain the cpu specific items which are based on - * whichever architecture is selected, it only contains the core of the - * register set. See <mach/regs-fb.h> to get the specifics. - * - * Note, we changed to using regs-fb.h as it avoids any clashes with - * the original regs-lcd.h so out of the way of regs-lcd.h as well as - * indicating the newer block is much more than just an LCD interface. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/* Please do not include this file directly, use <mach/regs-fb.h> to - * ensure all the localised SoC support is included as necessary. -*/ - -/* VIDCON0 */ - -#define VIDCON0 (0x00) -#define VIDCON0_INTERLACE (1 << 29) -#define VIDCON0_VIDOUT_MASK (0x3 << 26) -#define VIDCON0_VIDOUT_SHIFT (26) -#define VIDCON0_VIDOUT_RGB (0x0 << 26) -#define VIDCON0_VIDOUT_TV (0x1 << 26) -#define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26) -#define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26) - -#define VIDCON0_L1_DATA_MASK (0x7 << 23) -#define VIDCON0_L1_DATA_SHIFT (23) -#define VIDCON0_L1_DATA_16BPP (0x0 << 23) -#define VIDCON0_L1_DATA_18BPP16 (0x1 << 23) -#define VIDCON0_L1_DATA_18BPP9 (0x2 << 23) -#define VIDCON0_L1_DATA_24BPP (0x3 << 23) -#define VIDCON0_L1_DATA_18BPP (0x4 << 23) -#define VIDCON0_L1_DATA_16BPP8 (0x5 << 23) - -#define VIDCON0_L0_DATA_MASK (0x7 << 20) -#define VIDCON0_L0_DATA_SHIFT (20) -#define VIDCON0_L0_DATA_16BPP (0x0 << 20) -#define VIDCON0_L0_DATA_18BPP16 (0x1 << 20) -#define VIDCON0_L0_DATA_18BPP9 (0x2 << 20) -#define VIDCON0_L0_DATA_24BPP (0x3 << 20) -#define VIDCON0_L0_DATA_18BPP (0x4 << 20) -#define VIDCON0_L0_DATA_16BPP8 (0x5 << 20) - -#define VIDCON0_PNRMODE_MASK (0x3 << 17) -#define VIDCON0_PNRMODE_SHIFT (17) -#define VIDCON0_PNRMODE_RGB (0x0 << 17) -#define VIDCON0_PNRMODE_BGR (0x1 << 17) -#define VIDCON0_PNRMODE_SERIAL_RGB (0x2 << 17) -#define VIDCON0_PNRMODE_SERIAL_BGR (0x3 << 17) - -#define VIDCON0_CLKVALUP (1 << 16) -#define VIDCON0_CLKVAL_F_MASK (0xff << 6) -#define VIDCON0_CLKVAL_F_SHIFT (6) -#define VIDCON0_CLKVAL_F_LIMIT (0xff) -#define VIDCON0_CLKVAL_F(_x) ((_x) << 6) -#define VIDCON0_VLCKFREE (1 << 5) -#define VIDCON0_CLKDIR (1 << 4) - -#define VIDCON0_CLKSEL_MASK (0x3 << 2) -#define VIDCON0_CLKSEL_SHIFT (2) -#define VIDCON0_CLKSEL_HCLK (0x0 << 2) -#define VIDCON0_CLKSEL_LCD (0x1 << 2) -#define VIDCON0_CLKSEL_27M (0x3 << 2) - -#define VIDCON0_ENVID (1 << 1) -#define VIDCON0_ENVID_F (1 << 0) - -#define VIDCON1 (0x04) -#define VIDCON1_LINECNT_MASK (0x7ff << 16) -#define VIDCON1_LINECNT_SHIFT (16) -#define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff) -#define VIDCON1_VSTATUS_MASK (0x3 << 13) -#define VIDCON1_VSTATUS_SHIFT (13) -#define VIDCON1_VSTATUS_VSYNC (0x0 << 13) -#define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13) -#define VIDCON1_VSTATUS_ACTIVE (0x2 << 13) -#define VIDCON1_VSTATUS_FRONTPORCH (0x0 << 13) -#define VIDCON1_VCLK_MASK (0x3 << 9) -#define VIDCON1_VCLK_HOLD (0x0 << 9) -#define VIDCON1_VCLK_RUN (0x1 << 9) - -#define VIDCON1_INV_VCLK (1 << 7) -#define VIDCON1_INV_HSYNC (1 << 6) -#define VIDCON1_INV_VSYNC (1 << 5) -#define VIDCON1_INV_VDEN (1 << 4) - -/* VIDCON2 */ - -#define VIDCON2 (0x08) -#define VIDCON2_EN601 (1 << 23) -#define VIDCON2_TVFMTSEL_SW (1 << 14) - -#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12) -#define VIDCON2_TVFMTSEL1_SHIFT (12) -#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12) -#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12) -#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12) - -#define VIDCON2_ORGYCbCr (1 << 8) -#define VIDCON2_YUVORDCrCb (1 << 7) - -/* PRTCON (S3C6410, S5PC100) - * Might not be present in the S3C6410 documentation, - * but tests prove it's there almost for sure; shouldn't hurt in any case. - */ -#define PRTCON (0x0c) -#define PRTCON_PROTECT (1 << 11) - -/* VIDTCON0 */ - -#define VIDTCON0_VBPDE_MASK (0xff << 24) -#define VIDTCON0_VBPDE_SHIFT (24) -#define VIDTCON0_VBPDE_LIMIT (0xff) -#define VIDTCON0_VBPDE(_x) ((_x) << 24) - -#define VIDTCON0_VBPD_MASK (0xff << 16) -#define VIDTCON0_VBPD_SHIFT (16) -#define VIDTCON0_VBPD_LIMIT (0xff) -#define VIDTCON0_VBPD(_x) ((_x) << 16) - -#define VIDTCON0_VFPD_MASK (0xff << 8) -#define VIDTCON0_VFPD_SHIFT (8) -#define VIDTCON0_VFPD_LIMIT (0xff) -#define VIDTCON0_VFPD(_x) ((_x) << 8) - -#define VIDTCON0_VSPW_MASK (0xff << 0) -#define VIDTCON0_VSPW_SHIFT (0) -#define VIDTCON0_VSPW_LIMIT (0xff) -#define VIDTCON0_VSPW(_x) ((_x) << 0) - -/* VIDTCON1 */ - -#define VIDTCON1_VFPDE_MASK (0xff << 24) -#define VIDTCON1_VFPDE_SHIFT (24) -#define VIDTCON1_VFPDE_LIMIT (0xff) -#define VIDTCON1_VFPDE(_x) ((_x) << 24) - -#define VIDTCON1_HBPD_MASK (0xff << 16) -#define VIDTCON1_HBPD_SHIFT (16) -#define VIDTCON1_HBPD_LIMIT (0xff) -#define VIDTCON1_HBPD(_x) ((_x) << 16) - -#define VIDTCON1_HFPD_MASK (0xff << 8) -#define VIDTCON1_HFPD_SHIFT (8) -#define VIDTCON1_HFPD_LIMIT (0xff) -#define VIDTCON1_HFPD(_x) ((_x) << 8) - -#define VIDTCON1_HSPW_MASK (0xff << 0) -#define VIDTCON1_HSPW_SHIFT (0) -#define VIDTCON1_HSPW_LIMIT (0xff) -#define VIDTCON1_HSPW(_x) ((_x) << 0) - -#define VIDTCON2 (0x18) -#define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23) -#define VIDTCON2_LINEVAL_MASK (0x7ff << 11) -#define VIDTCON2_LINEVAL_SHIFT (11) -#define VIDTCON2_LINEVAL_LIMIT (0x7ff) -#define VIDTCON2_LINEVAL(_x) (((_x) & 0x7ff) << 11) - -#define VIDTCON2_HOZVAL_E(_x) ((((_x) & 0x800) >> 11) << 22) -#define VIDTCON2_HOZVAL_MASK (0x7ff << 0) -#define VIDTCON2_HOZVAL_SHIFT (0) -#define VIDTCON2_HOZVAL_LIMIT (0x7ff) -#define VIDTCON2_HOZVAL(_x) (((_x) & 0x7ff) << 0) - -/* WINCONx */ - - -#define WINCONx_BITSWP (1 << 18) -#define WINCONx_BYTSWP (1 << 17) -#define WINCONx_HAWSWP (1 << 16) -#define WINCONx_WSWP (1 << 15) -#define WINCONx_BURSTLEN_MASK (0x3 << 9) -#define WINCONx_BURSTLEN_SHIFT (9) -#define WINCONx_BURSTLEN_16WORD (0x0 << 9) -#define WINCONx_BURSTLEN_8WORD (0x1 << 9) -#define WINCONx_BURSTLEN_4WORD (0x2 << 9) - -#define WINCONx_ENWIN (1 << 0) -#define WINCON0_BPPMODE_MASK (0xf << 2) -#define WINCON0_BPPMODE_SHIFT (2) -#define WINCON0_BPPMODE_1BPP (0x0 << 2) -#define WINCON0_BPPMODE_2BPP (0x1 << 2) -#define WINCON0_BPPMODE_4BPP (0x2 << 2) -#define WINCON0_BPPMODE_8BPP_PALETTE (0x3 << 2) -#define WINCON0_BPPMODE_16BPP_565 (0x5 << 2) -#define WINCON0_BPPMODE_16BPP_1555 (0x7 << 2) -#define WINCON0_BPPMODE_18BPP_666 (0x8 << 2) -#define WINCON0_BPPMODE_24BPP_888 (0xb << 2) - -#define WINCON1_BLD_PIX (1 << 6) - -#define WINCON1_ALPHA_SEL (1 << 1) -#define WINCON1_BPPMODE_MASK (0xf << 2) -#define WINCON1_BPPMODE_SHIFT (2) -#define WINCON1_BPPMODE_1BPP (0x0 << 2) -#define WINCON1_BPPMODE_2BPP (0x1 << 2) -#define WINCON1_BPPMODE_4BPP (0x2 << 2) -#define WINCON1_BPPMODE_8BPP_PALETTE (0x3 << 2) -#define WINCON1_BPPMODE_8BPP_1232 (0x4 << 2) -#define WINCON1_BPPMODE_16BPP_565 (0x5 << 2) -#define WINCON1_BPPMODE_16BPP_A1555 (0x6 << 2) -#define WINCON1_BPPMODE_16BPP_I1555 (0x7 << 2) -#define WINCON1_BPPMODE_18BPP_666 (0x8 << 2) -#define WINCON1_BPPMODE_18BPP_A1665 (0x9 << 2) -#define WINCON1_BPPMODE_19BPP_A1666 (0xa << 2) -#define WINCON1_BPPMODE_24BPP_888 (0xb << 2) -#define WINCON1_BPPMODE_24BPP_A1887 (0xc << 2) -#define WINCON1_BPPMODE_25BPP_A1888 (0xd << 2) -#define WINCON1_BPPMODE_28BPP_A4888 (0xd << 2) - -/* S5PV210 */ -#define SHADOWCON (0x34) -#define SHADOWCON_WINx_PROTECT(_win) (1 << (10 + (_win))) -/* DMA channels (all windows) */ -#define SHADOWCON_CHx_ENABLE(_win) (1 << (_win)) -/* Local input channels (windows 0-2) */ -#define SHADOWCON_CHx_LOCAL_ENABLE(_win) (1 << (5 + (_win))) - -#define VIDOSDxA_TOPLEFT_X_E(_x) ((((_x) & 0x800) >> 11) << 23) -#define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11) -#define VIDOSDxA_TOPLEFT_X_SHIFT (11) -#define VIDOSDxA_TOPLEFT_X_LIMIT (0x7ff) -#define VIDOSDxA_TOPLEFT_X(_x) (((_x) & 0x7ff) << 11) - -#define VIDOSDxA_TOPLEFT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22) -#define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0) -#define VIDOSDxA_TOPLEFT_Y_SHIFT (0) -#define VIDOSDxA_TOPLEFT_Y_LIMIT (0x7ff) -#define VIDOSDxA_TOPLEFT_Y(_x) (((_x) & 0x7ff) << 0) - -#define VIDOSDxB_BOTRIGHT_X_E(_x) ((((_x) & 0x800) >> 11) << 23) -#define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11) -#define VIDOSDxB_BOTRIGHT_X_SHIFT (11) -#define VIDOSDxB_BOTRIGHT_X_LIMIT (0x7ff) -#define VIDOSDxB_BOTRIGHT_X(_x) (((_x) & 0x7ff) << 11) - -#define VIDOSDxB_BOTRIGHT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22) -#define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0) -#define VIDOSDxB_BOTRIGHT_Y_SHIFT (0) -#define VIDOSDxB_BOTRIGHT_Y_LIMIT (0x7ff) -#define VIDOSDxB_BOTRIGHT_Y(_x) (((_x) & 0x7ff) << 0) - -/* For VIDOSD[1..4]C */ -#define VIDISD14C_ALPHA0_R(_x) ((_x) << 20) -#define VIDISD14C_ALPHA0_G_MASK (0xf << 16) -#define VIDISD14C_ALPHA0_G_SHIFT (16) -#define VIDISD14C_ALPHA0_G_LIMIT (0xf) -#define VIDISD14C_ALPHA0_G(_x) ((_x) << 16) -#define VIDISD14C_ALPHA0_B_MASK (0xf << 12) -#define VIDISD14C_ALPHA0_B_SHIFT (12) -#define VIDISD14C_ALPHA0_B_LIMIT (0xf) -#define VIDISD14C_ALPHA0_B(_x) ((_x) << 12) -#define VIDISD14C_ALPHA1_R_MASK (0xf << 8) -#define VIDISD14C_ALPHA1_R_SHIFT (8) -#define VIDISD14C_ALPHA1_R_LIMIT (0xf) -#define VIDISD14C_ALPHA1_R(_x) ((_x) << 8) -#define VIDISD14C_ALPHA1_G_MASK (0xf << 4) -#define VIDISD14C_ALPHA1_G_SHIFT (4) -#define VIDISD14C_ALPHA1_G_LIMIT (0xf) -#define VIDISD14C_ALPHA1_G(_x) ((_x) << 4) -#define VIDISD14C_ALPHA1_B_MASK (0xf << 0) -#define VIDISD14C_ALPHA1_B_SHIFT (0) -#define VIDISD14C_ALPHA1_B_LIMIT (0xf) -#define VIDISD14C_ALPHA1_B(_x) ((_x) << 0) - -/* Video buffer addresses */ -#define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8)) -#define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8)) -#define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8)) -#define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8)) -#define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4)) - -#define VIDW_BUF_SIZE_OFFSET_E(_x) ((((_x) & 0x2000) >> 13) << 27) -#define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13) -#define VIDW_BUF_SIZE_OFFSET_SHIFT (13) -#define VIDW_BUF_SIZE_OFFSET_LIMIT (0x1fff) -#define VIDW_BUF_SIZE_OFFSET(_x) (((_x) & 0x1fff) << 13) - -#define VIDW_BUF_SIZE_PAGEWIDTH_E(_x) ((((_x) & 0x2000) >> 13) << 26) -#define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff << 0) -#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT (0) -#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT (0x1fff) -#define VIDW_BUF_SIZE_PAGEWIDTH(_x) (((_x) & 0x1fff) << 0) - -/* Interrupt controls and status */ - -#define VIDINTCON0_FIFOINTERVAL_MASK (0x3f << 20) -#define VIDINTCON0_FIFOINTERVAL_SHIFT (20) -#define VIDINTCON0_FIFOINTERVAL_LIMIT (0x3f) -#define VIDINTCON0_FIFOINTERVAL(_x) ((_x) << 20) - -#define VIDINTCON0_INT_SYSMAINCON (1 << 19) -#define VIDINTCON0_INT_SYSSUBCON (1 << 18) -#define VIDINTCON0_INT_I80IFDONE (1 << 17) - -#define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15) -#define VIDINTCON0_FRAMESEL0_SHIFT (15) -#define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15) -#define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15) -#define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15) -#define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15) - -#define VIDINTCON0_FRAMESEL1 (1 << 13) -#define VIDINTCON0_FRAMESEL1_MASK (0x3 << 13) -#define VIDINTCON0_FRAMESEL1_NONE (0x0 << 13) -#define VIDINTCON0_FRAMESEL1_BACKPORCH (0x1 << 13) -#define VIDINTCON0_FRAMESEL1_VSYNC (0x2 << 13) -#define VIDINTCON0_FRAMESEL1_FRONTPORCH (0x3 << 13) - -#define VIDINTCON0_INT_FRAME (1 << 12) -#define VIDINTCON0_FIFIOSEL_MASK (0x7f << 5) -#define VIDINTCON0_FIFIOSEL_SHIFT (5) -#define VIDINTCON0_FIFIOSEL_WINDOW0 (0x1 << 5) -#define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5) - -#define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 2) -#define VIDINTCON0_FIFOLEVEL_SHIFT (2) -#define VIDINTCON0_FIFOLEVEL_TO25PC (0x0 << 2) -#define VIDINTCON0_FIFOLEVEL_TO50PC (0x1 << 2) -#define VIDINTCON0_FIFOLEVEL_TO75PC (0x2 << 2) -#define VIDINTCON0_FIFOLEVEL_EMPTY (0x3 << 2) -#define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 2) - -#define VIDINTCON0_INT_FIFO_MASK (0x3 << 0) -#define VIDINTCON0_INT_FIFO_SHIFT (0) -#define VIDINTCON0_INT_ENABLE (1 << 0) - -#define VIDINTCON1 (0x134) -#define VIDINTCON1_INT_I180 (1 << 2) -#define VIDINTCON1_INT_FRAME (1 << 1) -#define VIDINTCON1_INT_FIFO (1 << 0) - -/* Window colour-key control registers */ -#define WKEYCON (0x140) /* 6410,V210 */ - -#define WKEYCON0 (0x00) -#define WKEYCON1 (0x04) - -#define WxKEYCON0_KEYBL_EN (1 << 26) -#define WxKEYCON0_KEYEN_F (1 << 25) -#define WxKEYCON0_DIRCON (1 << 24) -#define WxKEYCON0_COMPKEY_MASK (0xffffff << 0) -#define WxKEYCON0_COMPKEY_SHIFT (0) -#define WxKEYCON0_COMPKEY_LIMIT (0xffffff) -#define WxKEYCON0_COMPKEY(_x) ((_x) << 0) -#define WxKEYCON1_COLVAL_MASK (0xffffff << 0) -#define WxKEYCON1_COLVAL_SHIFT (0) -#define WxKEYCON1_COLVAL_LIMIT (0xffffff) -#define WxKEYCON1_COLVAL(_x) ((_x) << 0) - - -/* Window blanking (MAP) */ - -#define WINxMAP_MAP (1 << 24) -#define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0) -#define WINxMAP_MAP_COLOUR_SHIFT (0) -#define WINxMAP_MAP_COLOUR_LIMIT (0xffffff) -#define WINxMAP_MAP_COLOUR(_x) ((_x) << 0) - -#define WPALCON_PAL_UPDATE (1 << 9) -#define WPALCON_W1PAL_MASK (0x7 << 3) -#define WPALCON_W1PAL_SHIFT (3) -#define WPALCON_W1PAL_25BPP_A888 (0x0 << 3) -#define WPALCON_W1PAL_24BPP (0x1 << 3) -#define WPALCON_W1PAL_19BPP_A666 (0x2 << 3) -#define WPALCON_W1PAL_18BPP_A665 (0x3 << 3) -#define WPALCON_W1PAL_18BPP (0x4 << 3) -#define WPALCON_W1PAL_16BPP_A555 (0x5 << 3) -#define WPALCON_W1PAL_16BPP_565 (0x6 << 3) - -#define WPALCON_W0PAL_MASK (0x7 << 0) -#define WPALCON_W0PAL_SHIFT (0) -#define WPALCON_W0PAL_25BPP_A888 (0x0 << 0) -#define WPALCON_W0PAL_24BPP (0x1 << 0) -#define WPALCON_W0PAL_19BPP_A666 (0x2 << 0) -#define WPALCON_W0PAL_18BPP_A665 (0x3 << 0) -#define WPALCON_W0PAL_18BPP (0x4 << 0) -#define WPALCON_W0PAL_16BPP_A555 (0x5 << 0) -#define WPALCON_W0PAL_16BPP_565 (0x6 << 0) - -/* Blending equation control */ -#define BLENDCON (0x260) -#define BLENDCON_NEW_MASK (1 << 0) -#define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0) -#define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0) - diff --git a/arch/arm/plat-samsung/include/plat/spi-core.h b/arch/arm/plat-samsung/include/plat/spi-core.h new file mode 100644 index 000000000000..0b9428ab3fc3 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/spi-core.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2012 Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __PLAT_S3C_SPI_CORE_H +#define __PLAT_S3C_SPI_CORE_H + +/* These functions are only for use with the core support code, such as + * the cpu specific initialisation code + */ + +/* re-define device name depending on support. */ +static inline void s3c64xx_spi_setname(char *name) +{ +#ifdef CONFIG_S3C64XX_DEV_SPI0 + s3c64xx_device_spi0.name = name; +#endif +#ifdef CONFIG_S3C64XX_DEV_SPI1 + s3c64xx_device_spi1.name = name; +#endif +#ifdef CONFIG_S3C64XX_DEV_SPI2 + s3c64xx_device_spi2.name = name; +#endif +} + +#endif /* __PLAT_S3C_SPI_CORE_H */ diff --git a/arch/arm/plat-samsung/setup-mipiphy.c b/arch/arm/plat-samsung/setup-mipiphy.c index 683c466c0e6a..147459327601 100644 --- a/arch/arm/plat-samsung/setup-mipiphy.c +++ b/arch/arm/plat-samsung/setup-mipiphy.c @@ -14,24 +14,18 @@ #include <linux/spinlock.h> #include <mach/regs-clock.h> -static int __s5p_mipi_phy_control(struct platform_device *pdev, - bool on, u32 reset) +static int __s5p_mipi_phy_control(int id, bool on, u32 reset) { static DEFINE_SPINLOCK(lock); void __iomem *addr; unsigned long flags; - int pid; u32 cfg; - if (!pdev) + id = max(0, id); + if (id > 1) return -EINVAL; - pid = (pdev->id == -1) ? 0 : pdev->id; - - if (pid != 0 && pid != 1) - return -EINVAL; - - addr = S5P_MIPI_DPHY_CONTROL(pid); + addr = S5P_MIPI_DPHY_CONTROL(id); spin_lock_irqsave(&lock, flags); @@ -52,12 +46,12 @@ static int __s5p_mipi_phy_control(struct platform_device *pdev, return 0; } -int s5p_csis_phy_enable(struct platform_device *pdev, bool on) +int s5p_csis_phy_enable(int id, bool on) { - return __s5p_mipi_phy_control(pdev, on, S5P_MIPI_DPHY_SRESETN); + return __s5p_mipi_phy_control(id, on, S5P_MIPI_DPHY_SRESETN); } int s5p_dsim_phy_enable(struct platform_device *pdev, bool on) { - return __s5p_mipi_phy_control(pdev, on, S5P_MIPI_DPHY_MRESETN); + return __s5p_mipi_phy_control(pdev->id, on, S5P_MIPI_DPHY_MRESETN); } diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig index 4404f82d5979..f8db7b2deb36 100644 --- a/arch/arm/plat-spear/Kconfig +++ b/arch/arm/plat-spear/Kconfig @@ -12,10 +12,10 @@ config ARCH_SPEAR13XX bool "ST SPEAr13xx with Device Tree" select ARM_GIC select CPU_V7 - select USE_OF select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 select PINCTRL + select USE_OF help Supports for ARM's SPEAR13XX family @@ -23,8 +23,8 @@ config ARCH_SPEAR3XX bool "ST SPEAr3xx with Device Tree" select ARM_VIC select CPU_ARM926T - select USE_OF select PINCTRL + select USE_OF help Supports for ARM's SPEAR3XX family diff --git a/arch/arm/plat-versatile/fpga-irq.c b/arch/arm/plat-versatile/fpga-irq.c index 6e70d03824a1..091ae1030045 100644 --- a/arch/arm/plat-versatile/fpga-irq.c +++ b/arch/arm/plat-versatile/fpga-irq.c @@ -5,6 +5,8 @@ #include <linux/io.h> #include <linux/irqdomain.h> #include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> #include <asm/exception.h> #include <asm/mach/irq.h> @@ -14,11 +16,17 @@ #define IRQ_RAW_STATUS 0x04 #define IRQ_ENABLE_SET 0x08 #define IRQ_ENABLE_CLEAR 0x0c +#define INT_SOFT_SET 0x10 +#define INT_SOFT_CLEAR 0x14 +#define FIQ_STATUS 0x20 +#define FIQ_RAW_STATUS 0x24 +#define FIQ_ENABLE 0x28 +#define FIQ_ENABLE_SET 0x28 +#define FIQ_ENABLE_CLEAR 0x2C /** * struct fpga_irq_data - irq data container for the FPGA IRQ controller * @base: memory offset in virtual memory - * @irq_start: first IRQ number handled by this instance * @chip: chip container for this instance * @domain: IRQ domain for this instance * @valid: mask for valid IRQs on this controller @@ -26,7 +34,6 @@ */ struct fpga_irq_data { void __iomem *base; - unsigned int irq_start; struct irq_chip chip; u32 valid; struct irq_domain *domain; @@ -125,34 +132,79 @@ static struct irq_domain_ops fpga_irqdomain_ops = { .xlate = irq_domain_xlate_onetwocell, }; -void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start, - int parent_irq, u32 valid, struct device_node *node) -{ +static __init struct fpga_irq_data * +fpga_irq_prep_struct(void __iomem *base, const char *name, u32 valid) { struct fpga_irq_data *f; if (fpga_irq_id >= ARRAY_SIZE(fpga_irq_devices)) { printk(KERN_ERR "%s: too few FPGA IRQ controllers, increase CONFIG_PLAT_VERSATILE_FPGA_IRQ_NR\n", __func__); - return; + return NULL; } - f = &fpga_irq_devices[fpga_irq_id]; f->base = base; - f->irq_start = irq_start; f->chip.name = name; f->chip.irq_ack = fpga_irq_mask; f->chip.irq_mask = fpga_irq_mask; f->chip.irq_unmask = fpga_irq_unmask; f->valid = valid; + fpga_irq_id++; + + return f; +} + +void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start, + int parent_irq, u32 valid, struct device_node *node) +{ + struct fpga_irq_data *f; + + f = fpga_irq_prep_struct(base, name, valid); + if (!f) + return; if (parent_irq != -1) { irq_set_handler_data(parent_irq, f); irq_set_chained_handler(parent_irq, fpga_irq_handle); } - f->domain = irq_domain_add_legacy(node, fls(valid), f->irq_start, 0, + f->domain = irq_domain_add_legacy(node, fls(valid), irq_start, 0, &fpga_irqdomain_ops, f); pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs\n", fpga_irq_id, name, base, f->used_irqs); +} - fpga_irq_id++; +#ifdef CONFIG_OF +int __init fpga_irq_of_init(struct device_node *node, + struct device_node *parent) +{ + struct fpga_irq_data *f; + void __iomem *base; + u32 clear_mask; + u32 valid_mask; + + if (WARN_ON(!node)) + return -ENODEV; + + base = of_iomap(node, 0); + WARN(!base, "unable to map fpga irq registers\n"); + + if (of_property_read_u32(node, "clear-mask", &clear_mask)) + clear_mask = 0; + + if (of_property_read_u32(node, "valid-mask", &valid_mask)) + valid_mask = 0; + + f = fpga_irq_prep_struct(base, node->name, valid_mask); + if (!f) + return -ENOMEM; + + writel(clear_mask, base + IRQ_ENABLE_CLEAR); + writel(clear_mask, base + FIQ_ENABLE_CLEAR); + + f->domain = irq_domain_add_linear(node, fls(valid_mask), &fpga_irqdomain_ops, f); + f->used_irqs = hweight32(valid_mask); + + pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs\n", + fpga_irq_id, node->name, base, f->used_irqs); + return 0; } +#endif diff --git a/arch/arm/plat-versatile/include/plat/fpga-irq.h b/arch/arm/plat-versatile/include/plat/fpga-irq.h index 91bcfb67551d..1fac9651d3ca 100644 --- a/arch/arm/plat-versatile/include/plat/fpga-irq.h +++ b/arch/arm/plat-versatile/include/plat/fpga-irq.h @@ -7,5 +7,7 @@ struct pt_regs; void fpga_handle_irq(struct pt_regs *regs); void fpga_irq_init(void __iomem *, const char *, int, int, u32, struct device_node *node); +int fpga_irq_of_init(struct device_node *node, + struct device_node *parent); #endif diff --git a/arch/arm/tools/Makefile b/arch/arm/tools/Makefile index 635cb1865e4d..cd60a81163e9 100644 --- a/arch/arm/tools/Makefile +++ b/arch/arm/tools/Makefile @@ -5,6 +5,6 @@ # include/generated/mach-types.h: $(src)/gen-mach-types $(src)/mach-types - @echo ' Generating $@' + $(kecho) ' Generating $@' @mkdir -p $(dir $@) $(Q)$(AWK) -f $^ > $@ || { rm -f $@; /bin/false; } diff --git a/arch/arm/xen/Makefile b/arch/arm/xen/Makefile new file mode 100644 index 000000000000..43841033afd3 --- /dev/null +++ b/arch/arm/xen/Makefile @@ -0,0 +1 @@ +obj-y := enlighten.o hypercall.o grant-table.o diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c new file mode 100644 index 000000000000..59bcb96ac369 --- /dev/null +++ b/arch/arm/xen/enlighten.c @@ -0,0 +1,168 @@ +#include <xen/xen.h> +#include <xen/events.h> +#include <xen/grant_table.h> +#include <xen/hvm.h> +#include <xen/interface/xen.h> +#include <xen/interface/memory.h> +#include <xen/interface/hvm/params.h> +#include <xen/features.h> +#include <xen/platform_pci.h> +#include <xen/xenbus.h> +#include <asm/xen/hypervisor.h> +#include <asm/xen/hypercall.h> +#include <linux/interrupt.h> +#include <linux/irqreturn.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_irq.h> +#include <linux/of_address.h> + +struct start_info _xen_start_info; +struct start_info *xen_start_info = &_xen_start_info; +EXPORT_SYMBOL_GPL(xen_start_info); + +enum xen_domain_type xen_domain_type = XEN_NATIVE; +EXPORT_SYMBOL_GPL(xen_domain_type); + +struct shared_info xen_dummy_shared_info; +struct shared_info *HYPERVISOR_shared_info = (void *)&xen_dummy_shared_info; + +DEFINE_PER_CPU(struct vcpu_info *, xen_vcpu); + +/* TODO: to be removed */ +__read_mostly int xen_have_vector_callback; +EXPORT_SYMBOL_GPL(xen_have_vector_callback); + +int xen_platform_pci_unplug = XEN_UNPLUG_ALL; +EXPORT_SYMBOL_GPL(xen_platform_pci_unplug); + +static __read_mostly int xen_events_irq = -1; + +int xen_remap_domain_mfn_range(struct vm_area_struct *vma, + unsigned long addr, + unsigned long mfn, int nr, + pgprot_t prot, unsigned domid) +{ + return -ENOSYS; +} +EXPORT_SYMBOL_GPL(xen_remap_domain_mfn_range); + +/* + * see Documentation/devicetree/bindings/arm/xen.txt for the + * documentation of the Xen Device Tree format. + */ +#define GRANT_TABLE_PHYSADDR 0 +static int __init xen_guest_init(void) +{ + struct xen_add_to_physmap xatp; + static struct shared_info *shared_info_page = 0; + struct device_node *node; + int len; + const char *s = NULL; + const char *version = NULL; + const char *xen_prefix = "xen,xen-"; + struct resource res; + + node = of_find_compatible_node(NULL, NULL, "xen,xen"); + if (!node) { + pr_debug("No Xen support\n"); + return 0; + } + s = of_get_property(node, "compatible", &len); + if (strlen(xen_prefix) + 3 < len && + !strncmp(xen_prefix, s, strlen(xen_prefix))) + version = s + strlen(xen_prefix); + if (version == NULL) { + pr_debug("Xen version not found\n"); + return 0; + } + if (of_address_to_resource(node, GRANT_TABLE_PHYSADDR, &res)) + return 0; + xen_hvm_resume_frames = res.start >> PAGE_SHIFT; + xen_events_irq = irq_of_parse_and_map(node, 0); + pr_info("Xen %s support found, events_irq=%d gnttab_frame_pfn=%lx\n", + version, xen_events_irq, xen_hvm_resume_frames); + xen_domain_type = XEN_HVM_DOMAIN; + + xen_setup_features(); + if (xen_feature(XENFEAT_dom0)) + xen_start_info->flags |= SIF_INITDOMAIN|SIF_PRIVILEGED; + else + xen_start_info->flags &= ~(SIF_INITDOMAIN|SIF_PRIVILEGED); + + if (!shared_info_page) + shared_info_page = (struct shared_info *) + get_zeroed_page(GFP_KERNEL); + if (!shared_info_page) { + pr_err("not enough memory\n"); + return -ENOMEM; + } + xatp.domid = DOMID_SELF; + xatp.idx = 0; + xatp.space = XENMAPSPACE_shared_info; + xatp.gpfn = __pa(shared_info_page) >> PAGE_SHIFT; + if (HYPERVISOR_memory_op(XENMEM_add_to_physmap, &xatp)) + BUG(); + + HYPERVISOR_shared_info = (struct shared_info *)shared_info_page; + + /* xen_vcpu is a pointer to the vcpu_info struct in the shared_info + * page, we use it in the event channel upcall and in some pvclock + * related functions. We don't need the vcpu_info placement + * optimizations because we don't use any pv_mmu or pv_irq op on + * HVM. + * The shared info contains exactly 1 CPU (the boot CPU). The guest + * is required to use VCPUOP_register_vcpu_info to place vcpu info + * for secondary CPUs as they are brought up. */ + per_cpu(xen_vcpu, 0) = &HYPERVISOR_shared_info->vcpu_info[0]; + + gnttab_init(); + if (!xen_initial_domain()) + xenbus_probe(NULL); + + return 0; +} +core_initcall(xen_guest_init); + +static irqreturn_t xen_arm_callback(int irq, void *arg) +{ + xen_hvm_evtchn_do_upcall(); + return IRQ_HANDLED; +} + +static int __init xen_init_events(void) +{ + if (!xen_domain() || xen_events_irq < 0) + return -ENODEV; + + xen_init_IRQ(); + + if (request_percpu_irq(xen_events_irq, xen_arm_callback, + "events", xen_vcpu)) { + pr_err("Error requesting IRQ %d\n", xen_events_irq); + return -EINVAL; + } + + enable_percpu_irq(xen_events_irq, 0); + + return 0; +} +postcore_initcall(xen_init_events); + +/* XXX: only until balloon is properly working */ +int alloc_xenballooned_pages(int nr_pages, struct page **pages, bool highmem) +{ + *pages = alloc_pages(highmem ? GFP_HIGHUSER : GFP_KERNEL, + get_order(nr_pages)); + if (*pages == NULL) + return -ENOMEM; + return 0; +} +EXPORT_SYMBOL_GPL(alloc_xenballooned_pages); + +void free_xenballooned_pages(int nr_pages, struct page **pages) +{ + kfree(*pages); + *pages = NULL; +} +EXPORT_SYMBOL_GPL(free_xenballooned_pages); diff --git a/arch/arm/xen/grant-table.c b/arch/arm/xen/grant-table.c new file mode 100644 index 000000000000..859a9bb002d5 --- /dev/null +++ b/arch/arm/xen/grant-table.c @@ -0,0 +1,53 @@ +/****************************************************************************** + * grant_table.c + * ARM specific part + * + * Granting foreign access to our memory reservation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation; or, when distributed + * separately from the Linux kernel or incorporated into other + * software packages, subject to the following license: + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this source file (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, modify, + * merge, publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#include <xen/interface/xen.h> +#include <xen/page.h> +#include <xen/grant_table.h> + +int arch_gnttab_map_shared(xen_pfn_t *frames, unsigned long nr_gframes, + unsigned long max_nr_gframes, + void **__shared) +{ + return -ENOSYS; +} + +void arch_gnttab_unmap(void *shared, unsigned long nr_gframes) +{ + return; +} + +int arch_gnttab_map_status(uint64_t *frames, unsigned long nr_gframes, + unsigned long max_nr_gframes, + grant_status_t **__shared) +{ + return -ENOSYS; +} diff --git a/arch/arm/xen/hypercall.S b/arch/arm/xen/hypercall.S new file mode 100644 index 000000000000..074f5ed101b9 --- /dev/null +++ b/arch/arm/xen/hypercall.S @@ -0,0 +1,106 @@ +/****************************************************************************** + * hypercall.S + * + * Xen hypercall wrappers + * + * Stefano Stabellini <stefano.stabellini@eu.citrix.com>, Citrix, 2012 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation; or, when distributed + * separately from the Linux kernel or incorporated into other + * software packages, subject to the following license: + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this source file (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, modify, + * merge, publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +/* + * The Xen hypercall calling convention is very similar to the ARM + * procedure calling convention: the first paramter is passed in r0, the + * second in r1, the third in r2 and the fourth in r3. Considering that + * Xen hypercalls have 5 arguments at most, the fifth paramter is passed + * in r4, differently from the procedure calling convention of using the + * stack for that case. + * + * The hypercall number is passed in r12. + * + * The return value is in r0. + * + * The hvc ISS is required to be 0xEA1, that is the Xen specific ARM + * hypercall tag. + */ + +#include <linux/linkage.h> +#include <asm/assembler.h> +#include <xen/interface/xen.h> + + +/* HVC 0xEA1 */ +#ifdef CONFIG_THUMB2_KERNEL +#define xen_hvc .word 0xf7e08ea1 +#else +#define xen_hvc .word 0xe140ea71 +#endif + +#define HYPERCALL_SIMPLE(hypercall) \ +ENTRY(HYPERVISOR_##hypercall) \ + mov r12, #__HYPERVISOR_##hypercall; \ + xen_hvc; \ + mov pc, lr; \ +ENDPROC(HYPERVISOR_##hypercall) + +#define HYPERCALL0 HYPERCALL_SIMPLE +#define HYPERCALL1 HYPERCALL_SIMPLE +#define HYPERCALL2 HYPERCALL_SIMPLE +#define HYPERCALL3 HYPERCALL_SIMPLE +#define HYPERCALL4 HYPERCALL_SIMPLE + +#define HYPERCALL5(hypercall) \ +ENTRY(HYPERVISOR_##hypercall) \ + stmdb sp!, {r4} \ + ldr r4, [sp, #4] \ + mov r12, #__HYPERVISOR_##hypercall; \ + xen_hvc \ + ldm sp!, {r4} \ + mov pc, lr \ +ENDPROC(HYPERVISOR_##hypercall) + + .text + +HYPERCALL2(xen_version); +HYPERCALL3(console_io); +HYPERCALL3(grant_table_op); +HYPERCALL2(sched_op); +HYPERCALL2(event_channel_op); +HYPERCALL2(hvm_op); +HYPERCALL2(memory_op); +HYPERCALL2(physdev_op); + +ENTRY(privcmd_call) + stmdb sp!, {r4} + mov r12, r0 + mov r0, r1 + mov r1, r2 + mov r2, r3 + ldr r3, [sp, #8] + ldr r4, [sp, #4] + xen_hvc + ldm sp!, {r4} + mov pc, lr +ENDPROC(privcmd_call); |