diff options
Diffstat (limited to 'arch/arm')
284 files changed, 18541 insertions, 4740 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3849887157e7..bf7273f3dc64 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -573,6 +573,7 @@ config ARCH_TEGRA select HAVE_CLK select COMMON_CLKDEV select ARCH_HAS_BARRIERS if CACHE_L2X0 + select ARCH_HAS_CPUFREQ help This enables support for NVIDIA Tegra based systems (Tegra APX, Tegra 6xx and Tegra 2 series). @@ -831,7 +832,7 @@ config ARCH_OMAP select GENERIC_CLOCKEVENTS select ARCH_HAS_HOLES_MEMORYMODEL help - Support for TI's OMAP platform (OMAP1 and OMAP2). + Support for TI's OMAP platform (OMAP1/2/3/4). config PLAT_SPEAR bool "ST SPEAr" @@ -1222,7 +1223,7 @@ config SMP See also <file:Documentation/i386/IO-APIC.txt>, <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at - <http://www.linuxdoc.org/docs.html#howto>. + <http://tldp.org/HOWTO/SMP-HOWTO.html>. If you don't know what to do here, say N. diff --git a/arch/arm/common/icst.c b/arch/arm/common/icst.c index 9a7f09cff300..2dc6da70ae59 100644 --- a/arch/arm/common/icst.c +++ b/arch/arm/common/icst.c @@ -8,7 +8,7 @@ * published by the Free Software Foundation. * * Support functions for calculating clocks/divisors for the ICST307 - * clock generators. See http://www.icst.com/ for more information + * clock generators. See http://www.idt.com/ for more information * on these devices. * * This is an almost identical implementation to the ICST525 clock generator. diff --git a/arch/arm/common/scoop.c b/arch/arm/common/scoop.c index 9012004321dd..c11af1e4bad3 100644 --- a/arch/arm/common/scoop.c +++ b/arch/arm/common/scoop.c @@ -44,12 +44,12 @@ void reset_scoop(struct device *dev) { struct scoop_dev *sdev = dev_get_drvdata(dev); - iowrite16(0x0100, sdev->base + SCOOP_MCR); // 00 - iowrite16(0x0000, sdev->base + SCOOP_CDR); // 04 - iowrite16(0x0000, sdev->base + SCOOP_CCR); // 10 - iowrite16(0x0000, sdev->base + SCOOP_IMR); // 18 - iowrite16(0x00FF, sdev->base + SCOOP_IRM); // 14 - iowrite16(0x0000, sdev->base + SCOOP_ISR); // 1C + iowrite16(0x0100, sdev->base + SCOOP_MCR); /* 00 */ + iowrite16(0x0000, sdev->base + SCOOP_CDR); /* 04 */ + iowrite16(0x0000, sdev->base + SCOOP_CCR); /* 10 */ + iowrite16(0x0000, sdev->base + SCOOP_IMR); /* 18 */ + iowrite16(0x00FF, sdev->base + SCOOP_IRM); /* 14 */ + iowrite16(0x0000, sdev->base + SCOOP_ISR); /* 1C */ iowrite16(0x0000, sdev->base + SCOOP_IRM); } diff --git a/arch/arm/common/uengine.c b/arch/arm/common/uengine.c index b520e56216a9..bef408f3d76c 100644 --- a/arch/arm/common/uengine.c +++ b/arch/arm/common/uengine.c @@ -312,16 +312,16 @@ static void generate_ucode(u8 *ucode, u32 *gpr_a, u32 *gpr_b) b1 = (gpr_a[i] >> 8) & 0xff; b0 = gpr_a[i] & 0xff; - // immed[@ai, (b1 << 8) | b0] - // 11110000 0000VVVV VVVV11VV VVVVVV00 1IIIIIII + /* immed[@ai, (b1 << 8) | b0] */ + /* 11110000 0000VVVV VVVV11VV VVVVVV00 1IIIIIII */ ucode[offset++] = 0xf0; ucode[offset++] = (b1 >> 4); ucode[offset++] = (b1 << 4) | 0x0c | (b0 >> 6); ucode[offset++] = (b0 << 2); ucode[offset++] = 0x80 | i; - // immed_w1[@ai, (b3 << 8) | b2] - // 11110100 0100VVVV VVVV11VV VVVVVV00 1IIIIIII + /* immed_w1[@ai, (b3 << 8) | b2] */ + /* 11110100 0100VVVV VVVV11VV VVVVVV00 1IIIIIII */ ucode[offset++] = 0xf4; ucode[offset++] = 0x40 | (b3 >> 4); ucode[offset++] = (b3 << 4) | 0x0c | (b2 >> 6); @@ -340,16 +340,16 @@ static void generate_ucode(u8 *ucode, u32 *gpr_a, u32 *gpr_b) b1 = (gpr_b[i] >> 8) & 0xff; b0 = gpr_b[i] & 0xff; - // immed[@bi, (b1 << 8) | b0] - // 11110000 0000VVVV VVVV001I IIIIII11 VVVVVVVV + /* immed[@bi, (b1 << 8) | b0] */ + /* 11110000 0000VVVV VVVV001I IIIIII11 VVVVVVVV */ ucode[offset++] = 0xf0; ucode[offset++] = (b1 >> 4); ucode[offset++] = (b1 << 4) | 0x02 | (i >> 6); ucode[offset++] = (i << 2) | 0x03; ucode[offset++] = b0; - // immed_w1[@bi, (b3 << 8) | b2] - // 11110100 0100VVVV VVVV001I IIIIII11 VVVVVVVV + /* immed_w1[@bi, (b3 << 8) | b2] */ + /* 11110100 0100VVVV VVVV001I IIIIII11 VVVVVVVV */ ucode[offset++] = 0xf4; ucode[offset++] = 0x40 | (b3 >> 4); ucode[offset++] = (b3 << 4) | 0x02 | (i >> 6); @@ -357,7 +357,7 @@ static void generate_ucode(u8 *ucode, u32 *gpr_a, u32 *gpr_b) ucode[offset++] = b2; } - // ctx_arb[kill] + /* ctx_arb[kill] */ ucode[offset++] = 0xe0; ucode[offset++] = 0x00; ucode[offset++] = 0x01; diff --git a/arch/arm/configs/da8xx_omapl_defconfig b/arch/arm/configs/da8xx_omapl_defconfig index ba6670556f78..cdc40c4b8c48 100644 --- a/arch/arm/configs/da8xx_omapl_defconfig +++ b/arch/arm/configs/da8xx_omapl_defconfig @@ -17,6 +17,8 @@ CONFIG_MODVERSIONS=y CONFIG_ARCH_DAVINCI=y CONFIG_ARCH_DAVINCI_DA830=y CONFIG_ARCH_DAVINCI_DA850=y +CONFIG_MACH_MITYOMAPL138=y +CONFIG_MACH_OMAPL138_HAWKBOARD=y CONFIG_DAVINCI_RESET_CLOCKS=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y @@ -79,6 +81,7 @@ CONFIG_I2C_DAVINCI=y # CONFIG_HWMON is not set CONFIG_WATCHDOG=y CONFIG_REGULATOR=y +CONFIG_REGULATOR_DUMMY=y CONFIG_REGULATOR_TPS6507X=y CONFIG_FB=y CONFIG_FB_DA8XX=y diff --git a/arch/arm/configs/n8x0_defconfig b/arch/arm/configs/n8x0_defconfig deleted file mode 100644 index 56aebb69411d..000000000000 --- a/arch/arm/configs/n8x0_defconfig +++ /dev/null @@ -1,94 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_LBDAF is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -CONFIG_ARCH_OMAP=y -CONFIG_ARCH_OMAP2=y -CONFIG_OMAP_RESET_CLOCKS=y -# CONFIG_OMAP_MUX is not set -# CONFIG_OMAP_MCBSP is not set -CONFIG_OMAP_MBOX_FWK=y -CONFIG_OMAP_32K_TIMER=y -CONFIG_ARCH_OMAP2420=y -CONFIG_MACH_NOKIA_N8X0=y -CONFIG_AEABI=y -CONFIG_LEDS=y -CONFIG_ZBOOT_ROM_TEXT=0x10C08000 -CONFIG_ZBOOT_ROM_BSS=0x10200000 -CONFIG_CMDLINE="root=/dev/mmcblk0p2 console=ttyS2,115200n8 debug earlyprintk rootwait" -CONFIG_FPE_NWFPE=y -CONFIG_VFP=y -CONFIG_PM=y -CONFIG_PM_RUNTIME=y -CONFIG_NET=y -CONFIG_UNIX=y -CONFIG_INET=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_ONENAND=y -CONFIG_MTD_ONENAND_OMAP2=y -CONFIG_MTD_ONENAND_OTP=y -CONFIG_BLK_DEV_RAM=y -# CONFIG_MISC_DEVICES is not set -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -# CONFIG_I2C_COMPAT is not set -# CONFIG_I2C_HELPER_AUTO is not set -CONFIG_I2C_OMAP=y -CONFIG_SPI=y -CONFIG_SPI_OMAP24XX=y -# CONFIG_HWMON is not set -CONFIG_MENELAUS=y -CONFIG_REGULATOR=y -# CONFIG_VGA_CONSOLE is not set -# CONFIG_HID_SUPPORT is not set -CONFIG_USB=y -CONFIG_USB_DEBUG=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_DEVICEFS=y -CONFIG_USB_SUSPEND=y -# CONFIG_USB_OTG_WHITELIST is not set -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_OTG=y -CONFIG_USB_GADGET_MUSB_HDRC=y -# CONFIG_MUSB_PIO_ONLY is not set -CONFIG_USB_MUSB_DEBUG=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_DEBUG=y -CONFIG_USB_GADGET_DEBUG_FILES=y -CONFIG_USB_ETH=m -CONFIG_USB_ETH_EEM=y -CONFIG_MMC=y -CONFIG_MMC_OMAP=y -CONFIG_EXT3_FS=y -CONFIG_INOTIFY=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_SUMMARY=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_LZO=y -CONFIG_PRINTK_TIME=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y -CONFIG_CRC_CCITT=y diff --git a/arch/arm/configs/omap3_defconfig b/arch/arm/configs/omap2plus_defconfig index 5db9a6be2054..ccedde1371c3 100644 --- a/arch/arm/configs/omap3_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -53,18 +53,18 @@ CONFIG_MACH_SBC3530=y CONFIG_MACH_OMAP_3630SDP=y CONFIG_MACH_OMAP_4430SDP=y CONFIG_ARM_THUMBEE=y +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_ERRATA_411920=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y +CONFIG_SMP=y +# CONFIG_LOCAL_TIMERS is not set CONFIG_AEABI=y CONFIG_LEDS=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="root=/dev/mmcblk0p2 rootwait console=ttyS2,115200" +CONFIG_CMDLINE="root=/dev/mmcblk0p2 rootwait console=ttyO2,115200" CONFIG_KEXEC=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_STAT_DETAILS=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y CONFIG_FPE_NWFPE=y CONFIG_VFP=y CONFIG_NEON=y @@ -87,23 +87,23 @@ CONFIG_IP_PNP_RARP=y # CONFIG_INET_LRO is not set # CONFIG_IPV6 is not set CONFIG_NETFILTER=y -CONFIG_BT=y -CONFIG_BT_L2CAP=y -CONFIG_BT_SCO=y +CONFIG_BT=m +CONFIG_BT_L2CAP=m +CONFIG_BT_SCO=m CONFIG_BT_RFCOMM=y CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=y +CONFIG_BT_BNEP=m CONFIG_BT_BNEP_MC_FILTER=y CONFIG_BT_BNEP_PROTO_FILTER=y -CONFIG_BT_HIDP=y -CONFIG_BT_HCIUART=y +CONFIG_BT_HIDP=m +CONFIG_BT_HCIUART=m CONFIG_BT_HCIUART_H4=y CONFIG_BT_HCIUART_BCSP=y CONFIG_BT_HCIUART_LL=y -CONFIG_BT_HCIBCM203X=y -CONFIG_BT_HCIBPA10X=y -CONFIG_CFG80211=y -CONFIG_MAC80211=y +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBPA10X=m +CONFIG_CFG80211=m +CONFIG_MAC80211=m CONFIG_MAC80211_RC_PID=y CONFIG_MAC80211_RC_DEFAULT_PID=y CONFIG_MAC80211_LEDS=y @@ -137,9 +137,11 @@ CONFIG_SMSC_PHY=y CONFIG_NET_ETHERNET=y CONFIG_SMC91X=y CONFIG_SMSC911X=y -CONFIG_LIBERTAS=y -CONFIG_LIBERTAS_USB=y -CONFIG_LIBERTAS_SDIO=y +CONFIG_KS8851=y +CONFIG_KS8851_MLL=y +CONFIG_LIBERTAS=m +CONFIG_LIBERTAS_USB=m +CONFIG_LIBERTAS_SDIO=m CONFIG_LIBERTAS_DEBUG=y CONFIG_USB_USBNET=y CONFIG_USB_ALI_M5632=y @@ -201,8 +203,8 @@ CONFIG_FONTS=y CONFIG_FONT_8x8=y CONFIG_FONT_8x16=y CONFIG_LOGO=y -CONFIG_SOUND=y -CONFIG_SND=y +CONFIG_SOUND=m +CONFIG_SND=m CONFIG_SND_MIXER_OSS=y CONFIG_SND_PCM_OSS=y CONFIG_SND_VERBOSE_PRINTK=y @@ -218,9 +220,9 @@ CONFIG_USB_DEVICEFS=y CONFIG_USB_SUSPEND=y # CONFIG_USB_OTG_WHITELIST is not set CONFIG_USB_MON=y -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_OTG=y -CONFIG_USB_GADGET_MUSB_HDRC=y +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_MUSB_OTG is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set CONFIG_USB_MUSB_DEBUG=y CONFIG_USB_WDM=y CONFIG_USB_STORAGE=y @@ -276,12 +278,11 @@ CONFIG_DEBUG_KERNEL=y CONFIG_SCHEDSTATS=y CONFIG_TIMER_STATS=y CONFIG_PROVE_LOCKING=y -CONFIG_LOCK_STAT=y +# CONFIG_LOCK_STAT is not set CONFIG_DEBUG_SPINLOCK_SLEEP=y # CONFIG_DEBUG_BUGVERBOSE is not set CONFIG_DEBUG_INFO=y # CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_DEBUG_LL=y CONFIG_SECURITY=y CONFIG_CRYPTO_MICHAEL_MIC=y # CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/arm/configs/omap_4430sdp_defconfig b/arch/arm/configs/omap_4430sdp_defconfig deleted file mode 100644 index 14c1e18c648f..000000000000 --- a/arch/arm/configs/omap_4430sdp_defconfig +++ /dev/null @@ -1,125 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y -# CONFIG_SYSCTL_SYSCALL is not set -# CONFIG_ELF_CORE is not set -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ARCH_OMAP=y -CONFIG_ARCH_OMAP4=y -# CONFIG_ARCH_OMAP2PLUS_TYPICAL is not set -# CONFIG_ARCH_OMAP2 is not set -# CONFIG_ARCH_OMAP3 is not set -# CONFIG_OMAP_MUX is not set -CONFIG_OMAP_32K_TIMER=y -CONFIG_OMAP_DM_TIMER=y -CONFIG_MACH_OMAP_4430SDP=y -# CONFIG_ARM_THUMB is not set -CONFIG_PL310_ERRATA_588369=y -CONFIG_SMP=y -CONFIG_NR_CPUS=2 -# CONFIG_LOCAL_TIMERS is not set -CONFIG_PREEMPT=y -CONFIG_AEABI=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="root=/dev/ram0 rw mem=128M console=ttyS2,115200n8 initrd=0x81600000,20M ramdisk_size=20480" -CONFIG_VFP=y -CONFIG_NEON=y -CONFIG_BINFMT_MISC=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_FW_LOADER is not set -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=16384 -# CONFIG_MISC_DEVICES is not set -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_KS8851=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_SERIAL_8250_RSA=y -# CONFIG_LEGACY_PTYS is not set -CONFIG_HW_RANDOM=y -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_OMAP=y -CONFIG_SPI=y -CONFIG_SPI_OMAP24XX=y -# CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_OMAP_WATCHDOG=y -CONFIG_TWL4030_CORE=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_TWL4030=y -# CONFIG_VGA_CONSOLE is not set -# CONFIG_HID_SUPPORT is not set -# CONFIG_USB_SUPPORT is not set -CONFIG_MMC=y -CONFIG_MMC_OMAP_HS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_TWL4030=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -# CONFIG_EXT3_FS_XATTR is not set -CONFIG_INOTIFY=y -CONFIG_QUOTA=y -CONFIG_QFMT_V2=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=y -CONFIG_ROOT_NFS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -# CONFIG_ENABLE_WARN_DEPRECATED is not set -# CONFIG_ENABLE_MUST_CHECK is not set -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_KERNEL=y -# CONFIG_DETECT_SOFTLOCKUP is not set -CONFIG_DETECT_HUNG_TASK=y -# CONFIG_SCHED_DEBUG is not set -# CONFIG_DEBUG_PREEMPT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_FTRACE is not set -# CONFIG_ARM_UNWIND is not set -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_PCBC=m -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRC_CCITT=y -CONFIG_CRC_T10DIF=y -CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/omap_generic_2420_defconfig b/arch/arm/configs/omap_generic_2420_defconfig deleted file mode 100644 index ac08e51180dd..000000000000 --- a/arch/arm/configs/omap_generic_2420_defconfig +++ /dev/null @@ -1,37 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ARCH_OMAP=y -CONFIG_ARCH_OMAP2=y -# CONFIG_OMAP_MUX is not set -CONFIG_MACH_OMAP_GENERIC=y -CONFIG_ARCH_OMAP2420=y -CONFIG_LEDS=y -CONFIG_ZBOOT_ROM_TEXT=0x10C08000 -CONFIG_ZBOOT_ROM_BSS=0x10200000 -CONFIG_FPE_NWFPE=y -CONFIG_BLK_DEV_RAM=y -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -# CONFIG_LEGACY_PTYS is not set -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_NOWAYOUT=y -CONFIG_VIDEO_OUTPUT_CONTROL=m -# CONFIG_VGA_CONSOLE is not set -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_INOTIFY=y -CONFIG_ROMFS_FS=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y -CONFIG_DEBUG_LL=y -CONFIG_CRC_CCITT=y diff --git a/arch/arm/configs/pcontrol_g20_defconfig b/arch/arm/configs/pcontrol_g20_defconfig new file mode 100644 index 000000000000..b42ee62c4d77 --- /dev/null +++ b/arch/arm/configs/pcontrol_g20_defconfig @@ -0,0 +1,175 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_CROSS_COMPILE="/opt/arm-2010q1/bin/arm-none-linux-gnueabi-" +# CONFIG_LOCALVERSION_AUTO is not set +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_TREE_PREEMPT_RCU=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_NAMESPACES=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EMBEDDED=y +# CONFIG_SYSCTL_SYSCALL is not set +# CONFIG_KALLSYMS is not set +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_SLAB=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +CONFIG_DEFAULT_DEADLINE=y +CONFIG_ARCH_AT91=y +CONFIG_ARCH_AT91SAM9G20=y +CONFIG_MACH_PCONTROL_G20=y +CONFIG_AT91_PROGRAMMABLE_CLOCKS=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_PREEMPT=y +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyS0,115200 mem=128M mtdparts=atmel_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) root=/dev/mmcblk0p1 rootwait rw" +CONFIG_VFP=y +CONFIG_BINFMT_MISC=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_IPV6 is not set +CONFIG_VLAN_8021Q=y +# CONFIG_WIRELESS is not set +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_FW_LOADER is not set +CONFIG_MTD=y +CONFIG_MTD_PARTITIONS=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_COMPLEX_MAPPINGS=y +CONFIG_MTD_PHRAM=m +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_ATMEL=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_ATMEL_TCLIB=y +CONFIG_EEPROM_AT24=m +CONFIG_SCSI=m +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=m +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_NETDEVICES=y +CONFIG_MACVLAN=m +CONFIG_TUN=m +CONFIG_SMSC_PHY=m +CONFIG_BROADCOM_PHY=m +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +CONFIG_MACB=y +CONFIG_SMSC911X=m +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_WLAN is not set +CONFIG_PPP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_MPPE=m +CONFIG_INPUT_POLLDEV=y +CONFIG_INPUT_SPARSEKMAP=y +# CONFIG_INPUT_MOUSEDEV is not set +CONFIG_INPUT_EVDEV=m +CONFIG_INPUT_EVBUG=m +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_GPIO=m +CONFIG_KEYBOARD_MATRIX=m +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_UINPUT=m +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m +# CONFIG_SERIO is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_ATMEL=y +CONFIG_SERIAL_ATMEL_CONSOLE=y +CONFIG_SERIAL_MAX3100=m +# CONFIG_LEGACY_PTYS is not set +# CONFIG_HW_RANDOM is not set +CONFIG_R3964=m +CONFIG_I2C=m +CONFIG_I2C_CHARDEV=m +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_GPIO=m +CONFIG_SPI=y +CONFIG_SPI_ATMEL=m +CONFIG_SPI_SPIDEV=m +CONFIG_GPIO_SYSFS=y +CONFIG_W1=m +CONFIG_W1_MASTER_GPIO=m +CONFIG_W1_SLAVE_DS2431=m +# CONFIG_HWMON is not set +CONFIG_WATCHDOG=y +CONFIG_AT91SAM9X_WATCHDOG=y +# CONFIG_MFD_SUPPORT is not set +# CONFIG_HID_SUPPORT is not set +CONFIG_USB=y +# CONFIG_USB_DEVICE_CLASS is not set +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_STORAGE=m +CONFIG_USB_LIBUSUAL=y +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_GADGET=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_FILE_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_USB_G_HID=m +CONFIG_MMC=y +CONFIG_MMC_UNSAFE_RESUME=y +CONFIG_MMC_ATMELMCI=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_AT91SAM9=y +CONFIG_AUXDISPLAY=y +CONFIG_UIO=y +CONFIG_UIO_PDRV=y +CONFIG_STAGING=y +# CONFIG_STAGING_EXCLUDE_BUILD is not set +CONFIG_IIO=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_NFS_V4=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=y +CONFIG_NLS_UTF8=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ANSI_CPRNG=y +# CONFIG_CRYPTO_HW is not set +CONFIG_CRC_CCITT=y diff --git a/arch/arm/include/asm/hardware/icst.h b/arch/arm/include/asm/hardware/icst.h index 10382a3dcec9..794220b087d2 100644 --- a/arch/arm/include/asm/hardware/icst.h +++ b/arch/arm/include/asm/hardware/icst.h @@ -8,7 +8,7 @@ * published by the Free Software Foundation. * * Support functions for calculating clocks/divisors for the ICST - * clock generators. See http://www.icst.com/ for more information + * clock generators. See http://www.idt.com/ for more information * on these devices. */ #ifndef ASMARM_HARDWARE_ICST_H diff --git a/arch/arm/include/asm/highmem.h b/arch/arm/include/asm/highmem.h index 5aff58126602..1fc684e70ab6 100644 --- a/arch/arm/include/asm/highmem.h +++ b/arch/arm/include/asm/highmem.h @@ -35,9 +35,9 @@ extern void kunmap_high_l1_vipt(struct page *page, pte_t saved_pte); #ifdef CONFIG_HIGHMEM extern void *kmap(struct page *page); extern void kunmap(struct page *page); -extern void *kmap_atomic(struct page *page, enum km_type type); -extern void kunmap_atomic_notypecheck(void *kvaddr, enum km_type type); -extern void *kmap_atomic_pfn(unsigned long pfn, enum km_type type); +extern void *__kmap_atomic(struct page *page); +extern void __kunmap_atomic(void *kvaddr); +extern void *kmap_atomic_pfn(unsigned long pfn); extern struct page *kmap_atomic_to_page(const void *ptr); #endif diff --git a/arch/arm/include/asm/ioctls.h b/arch/arm/include/asm/ioctls.h index 0b30894b5482..9c9629816128 100644 --- a/arch/arm/include/asm/ioctls.h +++ b/arch/arm/include/asm/ioctls.h @@ -1,89 +1,8 @@ #ifndef __ASM_ARM_IOCTLS_H #define __ASM_ARM_IOCTLS_H -#include <asm/ioctl.h> - -/* 0x54 is just a magic number to make these relatively unique ('T') */ - -#define TCGETS 0x5401 -#define TCSETS 0x5402 -#define TCSETSW 0x5403 -#define TCSETSF 0x5404 -#define TCGETA 0x5405 -#define TCSETA 0x5406 -#define TCSETAW 0x5407 -#define TCSETAF 0x5408 -#define TCSBRK 0x5409 -#define TCXONC 0x540A -#define TCFLSH 0x540B -#define TIOCEXCL 0x540C -#define TIOCNXCL 0x540D -#define TIOCSCTTY 0x540E -#define TIOCGPGRP 0x540F -#define TIOCSPGRP 0x5410 -#define TIOCOUTQ 0x5411 -#define TIOCSTI 0x5412 -#define TIOCGWINSZ 0x5413 -#define TIOCSWINSZ 0x5414 -#define TIOCMGET 0x5415 -#define TIOCMBIS 0x5416 -#define TIOCMBIC 0x5417 -#define TIOCMSET 0x5418 -#define TIOCGSOFTCAR 0x5419 -#define TIOCSSOFTCAR 0x541A -#define FIONREAD 0x541B -#define TIOCINQ FIONREAD -#define TIOCLINUX 0x541C -#define TIOCCONS 0x541D -#define TIOCGSERIAL 0x541E -#define TIOCSSERIAL 0x541F -#define TIOCPKT 0x5420 -#define FIONBIO 0x5421 -#define TIOCNOTTY 0x5422 -#define TIOCSETD 0x5423 -#define TIOCGETD 0x5424 -#define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */ -#define TIOCSBRK 0x5427 /* BSD compatibility */ -#define TIOCCBRK 0x5428 /* BSD compatibility */ -#define TIOCGSID 0x5429 /* Return the session ID of FD */ -#define TCGETS2 _IOR('T',0x2A, struct termios2) -#define TCSETS2 _IOW('T',0x2B, struct termios2) -#define TCSETSW2 _IOW('T',0x2C, struct termios2) -#define TCSETSF2 _IOW('T',0x2D, struct termios2) -#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ -#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ -#define TIOCSIG _IOW('T',0x36, int) /* Generate signal on Pty slave */ - -#define TIOCGRS485 0x542E -#define TIOCSRS485 0x542F - -#define FIONCLEX 0x5450 /* these numbers need to be adjusted. */ -#define FIOCLEX 0x5451 -#define FIOASYNC 0x5452 -#define TIOCSERCONFIG 0x5453 -#define TIOCSERGWILD 0x5454 -#define TIOCSERSWILD 0x5455 -#define TIOCGLCKTRMIOS 0x5456 -#define TIOCSLCKTRMIOS 0x5457 -#define TIOCSERGSTRUCT 0x5458 /* For debugging only */ -#define TIOCSERGETLSR 0x5459 /* Get line status register */ -#define TIOCSERGETMULTI 0x545A /* Get multiport config */ -#define TIOCSERSETMULTI 0x545B /* Set multiport config */ - -#define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */ -#define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */ #define FIOQSIZE 0x545E -/* Used for packet mode */ -#define TIOCPKT_DATA 0 -#define TIOCPKT_FLUSHREAD 1 -#define TIOCPKT_FLUSHWRITE 2 -#define TIOCPKT_STOP 4 -#define TIOCPKT_START 8 -#define TIOCPKT_NOSTOP 16 -#define TIOCPKT_DOSTOP 32 -#define TIOCPKT_IOCTL 64 - -#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */ +#include <asm-generic/ioctls.h> #endif diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h index a9672e8406a3..b155414192da 100644 --- a/arch/arm/include/asm/pgtable.h +++ b/arch/arm/include/asm/pgtable.h @@ -263,17 +263,15 @@ extern struct page *empty_zero_page; #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) #define pte_offset_kernel(dir,addr) (pmd_page_vaddr(*(dir)) + __pte_index(addr)) -#define pte_offset_map(dir,addr) (__pte_map(dir, KM_PTE0) + __pte_index(addr)) -#define pte_offset_map_nested(dir,addr) (__pte_map(dir, KM_PTE1) + __pte_index(addr)) -#define pte_unmap(pte) __pte_unmap(pte, KM_PTE0) -#define pte_unmap_nested(pte) __pte_unmap(pte, KM_PTE1) +#define pte_offset_map(dir,addr) (__pte_map(dir) + __pte_index(addr)) +#define pte_unmap(pte) __pte_unmap(pte) #ifndef CONFIG_HIGHPTE -#define __pte_map(dir,km) pmd_page_vaddr(*(dir)) -#define __pte_unmap(pte,km) do { } while (0) +#define __pte_map(dir) pmd_page_vaddr(*(dir)) +#define __pte_unmap(pte) do { } while (0) #else -#define __pte_map(dir,km) ((pte_t *)kmap_atomic(pmd_page(*(dir)), km) + PTRS_PER_PTE) -#define __pte_unmap(pte,km) kunmap_atomic((pte - PTRS_PER_PTE), km) +#define __pte_map(dir) ((pte_t *)kmap_atomic(pmd_page(*(dir))) + PTRS_PER_PTE) +#define __pte_unmap(pte) kunmap_atomic((pte - PTRS_PER_PTE)) #endif #define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext) diff --git a/arch/arm/kernel/etm.c b/arch/arm/kernel/etm.c index a48d51257988..11db62806a1a 100644 --- a/arch/arm/kernel/etm.c +++ b/arch/arm/kernel/etm.c @@ -329,6 +329,7 @@ static const struct file_operations etb_fops = { .read = etb_read, .open = etb_open, .release = etb_release, + .llseek = no_llseek, }; static struct miscdevice etb_miscdev = { diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c index e0cb6370ed14..3e97483abcf0 100644 --- a/arch/arm/kernel/ptrace.c +++ b/arch/arm/kernel/ptrace.c @@ -1075,13 +1075,15 @@ out: } #endif -long arch_ptrace(struct task_struct *child, long request, long addr, long data) +long arch_ptrace(struct task_struct *child, long request, + unsigned long addr, unsigned long data) { int ret; + unsigned long __user *datap = (unsigned long __user *) data; switch (request) { case PTRACE_PEEKUSR: - ret = ptrace_read_user(child, addr, (unsigned long __user *)data); + ret = ptrace_read_user(child, addr, datap); break; case PTRACE_POKEUSR: @@ -1089,34 +1091,34 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) break; case PTRACE_GETREGS: - ret = ptrace_getregs(child, (void __user *)data); + ret = ptrace_getregs(child, datap); break; case PTRACE_SETREGS: - ret = ptrace_setregs(child, (void __user *)data); + ret = ptrace_setregs(child, datap); break; case PTRACE_GETFPREGS: - ret = ptrace_getfpregs(child, (void __user *)data); + ret = ptrace_getfpregs(child, datap); break; case PTRACE_SETFPREGS: - ret = ptrace_setfpregs(child, (void __user *)data); + ret = ptrace_setfpregs(child, datap); break; #ifdef CONFIG_IWMMXT case PTRACE_GETWMMXREGS: - ret = ptrace_getwmmxregs(child, (void __user *)data); + ret = ptrace_getwmmxregs(child, datap); break; case PTRACE_SETWMMXREGS: - ret = ptrace_setwmmxregs(child, (void __user *)data); + ret = ptrace_setwmmxregs(child, datap); break; #endif case PTRACE_GET_THREAD_AREA: ret = put_user(task_thread_info(child)->tp_value, - (unsigned long __user *) data); + datap); break; case PTRACE_SET_SYSCALL: @@ -1126,21 +1128,21 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) #ifdef CONFIG_CRUNCH case PTRACE_GETCRUNCHREGS: - ret = ptrace_getcrunchregs(child, (void __user *)data); + ret = ptrace_getcrunchregs(child, datap); break; case PTRACE_SETCRUNCHREGS: - ret = ptrace_setcrunchregs(child, (void __user *)data); + ret = ptrace_setcrunchregs(child, datap); break; #endif #ifdef CONFIG_VFP case PTRACE_GETVFPREGS: - ret = ptrace_getvfpregs(child, (void __user *)data); + ret = ptrace_getvfpregs(child, datap); break; case PTRACE_SETVFPREGS: - ret = ptrace_setvfpregs(child, (void __user *)data); + ret = ptrace_setvfpregs(child, datap); break; #endif diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 851e8139ef9d..c015b684b4fe 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -109,7 +109,7 @@ config MACH_ONEARM bool "Ajeco 1ARM Single Board Computer" help Select this if you are using Ajeco's 1ARM Single Board Computer. - <http://www.ajeco.fi/products.htm> + <http://www.ajeco.fi/> config ARCH_AT91RM9200DK bool "Atmel AT91RM9200-DK Development board" @@ -141,7 +141,7 @@ config MACH_CARMEVA bool "Conitec ARM&EVA" help Select this if you are using Conitec's AT91RM9200-MCU-Module. - <http://www.conitec.net/english/linuxboard.htm> + <http://www.conitec.net/english/linuxboard.php> config MACH_ATEB9200 bool "Embest ATEB9200" @@ -153,7 +153,7 @@ config MACH_KB9200 bool "KwikByte KB920x" help Select this if you are using KwikByte's KB920x board. - <http://kwikbyte.com/KB9202_description_new.htm> + <http://www.kwikbyte.com/KB9202.html> config MACH_PICOTUX2XX bool "picotux 200" @@ -375,6 +375,12 @@ config MACH_STAMP9G20 evaluation board. <http://www.taskit.de/en/> +config MACH_PCONTROL_G20 + bool "PControl G20 CPU module" + help + Select this if you are using taskit's Stamp9G20 CPU module on this + carrier board, beeing the decentralized unit of a building automation + system; featuring nvram, eth-switch, iso-rs485, display, io endif if (ARCH_AT91SAM9260 || ARCH_AT91SAM9G20) diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 412b3a471a4b..821eb842795f 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -11,12 +11,12 @@ obj-$(CONFIG_AT91_PMC_UNIT) += clock.o # CPU-specific support obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o -obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o +obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o at91sam9_alt_reset.o +obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o at91sam9_alt_reset.o +obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o at91sam9_alt_reset.o +obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o at91sam9_alt_reset.o +obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o at91sam9_alt_reset.o +obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o at91sam9_alt_reset.o obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o obj-$(CONFIG_ARCH_AT572D940HF) += at572d940hf.o at91sam926x_time.o at572d940hf_devices.o sam9_smc.o @@ -65,6 +65,7 @@ obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o obj-$(CONFIG_MACH_CPU9G20) += board-cpu9krea.o obj-$(CONFIG_MACH_STAMP9G20) += board-stamp9g20.o obj-$(CONFIG_MACH_PORTUXG20) += board-stamp9g20.o +obj-$(CONFIG_MACH_PCONTROL_G20) += board-pcontrol-g20.o # AT91SAM9260/AT91SAM9G20 board-specific support obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c index 0894f1077be7..195208b30024 100644 --- a/arch/arm/mach-at91/at91sam9260.c +++ b/arch/arm/mach-at91/at91sam9260.c @@ -279,11 +279,6 @@ static struct at91_gpio_bank at91sam9260_gpio[] = { } }; -static void at91sam9260_reset(void) -{ - at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); -} - static void at91sam9260_poweroff(void) { at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); @@ -327,7 +322,7 @@ void __init at91sam9260_initialize(unsigned long main_clock) else iotable_init(at91sam9260_sram_desc, ARRAY_SIZE(at91sam9260_sram_desc)); - at91_arch_reset = at91sam9260_reset; + at91_arch_reset = at91sam9_alt_reset; pm_power_off = at91sam9260_poweroff; at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1) | (1 << AT91SAM9260_ID_IRQ2); diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c index 4ecf37996c77..fcad88668504 100644 --- a/arch/arm/mach-at91/at91sam9261.c +++ b/arch/arm/mach-at91/at91sam9261.c @@ -257,11 +257,6 @@ static struct at91_gpio_bank at91sam9261_gpio[] = { } }; -static void at91sam9261_reset(void) -{ - at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); -} - static void at91sam9261_poweroff(void) { at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); @@ -283,7 +278,7 @@ void __init at91sam9261_initialize(unsigned long main_clock) iotable_init(at91sam9261_sram_desc, ARRAY_SIZE(at91sam9261_sram_desc)); - at91_arch_reset = at91sam9261_reset; + at91_arch_reset = at91sam9_alt_reset; pm_power_off = at91sam9261_poweroff; at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1) | (1 << AT91SAM9261_ID_IRQ2); diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c index 942792d630d8..249f900954d8 100644 --- a/arch/arm/mach-at91/at91sam9263.c +++ b/arch/arm/mach-at91/at91sam9263.c @@ -269,11 +269,6 @@ static struct at91_gpio_bank at91sam9263_gpio[] = { } }; -static void at91sam9263_reset(void) -{ - at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); -} - static void at91sam9263_poweroff(void) { at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); @@ -289,7 +284,7 @@ void __init at91sam9263_initialize(unsigned long main_clock) /* Map peripherals */ iotable_init(at91sam9263_io_desc, ARRAY_SIZE(at91sam9263_io_desc)); - at91_arch_reset = at91sam9263_reset; + at91_arch_reset = at91sam9_alt_reset; pm_power_off = at91sam9263_poweroff; at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1); diff --git a/arch/arm/mach-at91/at91sam9_alt_reset.S b/arch/arm/mach-at91/at91sam9_alt_reset.S new file mode 100644 index 000000000000..e0256deb91fb --- /dev/null +++ b/arch/arm/mach-at91/at91sam9_alt_reset.S @@ -0,0 +1,48 @@ +/* + * reset AT91SAM9G20 as per errata + * + * (C) BitBox Ltd 2010 + * + * unless the SDRAM is cleanly shutdown before we hit the + * reset register it can be left driving the data bus and + * killing the chance of a subsequent boot from NAND + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/linkage.h> +#include <asm/system.h> +#include <mach/hardware.h> +#include <mach/at91sam9_sdramc.h> +#include <mach/at91_rstc.h> + + .arm + + .globl at91sam9_alt_reset + +at91sam9_alt_reset: mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #CR_I + mcr p15, 0, r0, c1, c0, 0 @ enable I-cache + + ldr r0, .at91_va_base_sdramc @ preload constants + ldr r1, .at91_va_base_rstc_cr + + mov r2, #1 + mov r3, #AT91_SDRAMC_LPCB_POWER_DOWN + ldr r4, =AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST + + .balign 32 @ align to cache line + + str r2, [r0, #AT91_SDRAMC_TR] @ disable SDRAM access + str r3, [r0, #AT91_SDRAMC_LPR] @ power down SDRAM + str r4, [r1] @ reset processor + + b . + +.at91_va_base_sdramc: + .word AT91_VA_BASE_SYS + AT91_SDRAMC0 +.at91_va_base_rstc_cr: + .word AT91_VA_BASE_SYS + AT91_RSTC_CR diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c index 1276babf84d5..1e8f275c17f6 100644 --- a/arch/arm/mach-at91/at91sam9g45_devices.c +++ b/arch/arm/mach-at91/at91sam9g45_devices.c @@ -15,6 +15,7 @@ #include <linux/dma-mapping.h> #include <linux/platform_device.h> #include <linux/i2c-gpio.h> +#include <linux/atmel-mci.h> #include <linux/fb.h> #include <video/atmel_lcdc.h> @@ -25,6 +26,7 @@ #include <mach/at91sam9g45_matrix.h> #include <mach/at91sam9_smc.h> #include <mach/at_hdmac.h> +#include <mach/atmel-mci.h> #include "generic.h" @@ -350,6 +352,169 @@ void __init at91_add_device_eth(struct at91_eth_data *data) {} /* -------------------------------------------------------------------- + * MMC / SD + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE) +static u64 mmc_dmamask = DMA_BIT_MASK(32); +static struct mci_platform_data mmc0_data, mmc1_data; + +static struct resource mmc0_resources[] = { + [0] = { + .start = AT91SAM9G45_BASE_MCI0, + .end = AT91SAM9G45_BASE_MCI0 + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91SAM9G45_ID_MCI0, + .end = AT91SAM9G45_ID_MCI0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device at91sam9g45_mmc0_device = { + .name = "atmel_mci", + .id = 0, + .dev = { + .dma_mask = &mmc_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &mmc0_data, + }, + .resource = mmc0_resources, + .num_resources = ARRAY_SIZE(mmc0_resources), +}; + +static struct resource mmc1_resources[] = { + [0] = { + .start = AT91SAM9G45_BASE_MCI1, + .end = AT91SAM9G45_BASE_MCI1 + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91SAM9G45_ID_MCI1, + .end = AT91SAM9G45_ID_MCI1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device at91sam9g45_mmc1_device = { + .name = "atmel_mci", + .id = 1, + .dev = { + .dma_mask = &mmc_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &mmc1_data, + }, + .resource = mmc1_resources, + .num_resources = ARRAY_SIZE(mmc1_resources), +}; + +/* Consider only one slot : slot 0 */ +void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) +{ + + if (!data) + return; + + /* Must have at least one usable slot */ + if (!data->slot[0].bus_width) + return; + +#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE) + { + struct at_dma_slave *atslave; + struct mci_dma_data *alt_atslave; + + alt_atslave = kzalloc(sizeof(struct mci_dma_data), GFP_KERNEL); + atslave = &alt_atslave->sdata; + + /* DMA slave channel configuration */ + atslave->dma_dev = &at_hdmac_device.dev; + atslave->reg_width = AT_DMA_SLAVE_WIDTH_32BIT; + atslave->cfg = ATC_FIFOCFG_HALFFIFO + | ATC_SRC_H2SEL_HW | ATC_DST_H2SEL_HW; + atslave->ctrla = ATC_SCSIZE_16 | ATC_DCSIZE_16; + if (mmc_id == 0) /* MCI0 */ + atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI0) + | ATC_DST_PER(AT_DMA_ID_MCI0); + + else /* MCI1 */ + atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI1) + | ATC_DST_PER(AT_DMA_ID_MCI1); + + data->dma_slave = alt_atslave; + } +#endif + + + /* input/irq */ + if (data->slot[0].detect_pin) { + at91_set_gpio_input(data->slot[0].detect_pin, 1); + at91_set_deglitch(data->slot[0].detect_pin, 1); + } + if (data->slot[0].wp_pin) + at91_set_gpio_input(data->slot[0].wp_pin, 1); + + if (mmc_id == 0) { /* MCI0 */ + + /* CLK */ + at91_set_A_periph(AT91_PIN_PA0, 0); + + /* CMD */ + at91_set_A_periph(AT91_PIN_PA1, 1); + + /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */ + at91_set_A_periph(AT91_PIN_PA2, 1); + if (data->slot[0].bus_width == 4) { + at91_set_A_periph(AT91_PIN_PA3, 1); + at91_set_A_periph(AT91_PIN_PA4, 1); + at91_set_A_periph(AT91_PIN_PA5, 1); + if (data->slot[0].bus_width == 8) { + at91_set_A_periph(AT91_PIN_PA6, 1); + at91_set_A_periph(AT91_PIN_PA7, 1); + at91_set_A_periph(AT91_PIN_PA8, 1); + at91_set_A_periph(AT91_PIN_PA9, 1); + } + } + + mmc0_data = *data; + at91_clock_associate("mci0_clk", &at91sam9g45_mmc0_device.dev, "mci_clk"); + platform_device_register(&at91sam9g45_mmc0_device); + + } else { /* MCI1 */ + + /* CLK */ + at91_set_A_periph(AT91_PIN_PA31, 0); + + /* CMD */ + at91_set_A_periph(AT91_PIN_PA22, 1); + + /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */ + at91_set_A_periph(AT91_PIN_PA23, 1); + if (data->slot[0].bus_width == 4) { + at91_set_A_periph(AT91_PIN_PA24, 1); + at91_set_A_periph(AT91_PIN_PA25, 1); + at91_set_A_periph(AT91_PIN_PA26, 1); + if (data->slot[0].bus_width == 8) { + at91_set_A_periph(AT91_PIN_PA27, 1); + at91_set_A_periph(AT91_PIN_PA28, 1); + at91_set_A_periph(AT91_PIN_PA29, 1); + at91_set_A_periph(AT91_PIN_PA30, 1); + } + } + + mmc1_data = *data; + at91_clock_associate("mci1_clk", &at91sam9g45_mmc1_device.dev, "mci_clk"); + platform_device_register(&at91sam9g45_mmc1_device); + + } +} +#else +void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {} +#endif + + +/* -------------------------------------------------------------------- * NAND / SmartMedia * -------------------------------------------------------------------- */ diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c index 211c5c14a1e6..6a9d24e5ed8e 100644 --- a/arch/arm/mach-at91/at91sam9rl.c +++ b/arch/arm/mach-at91/at91sam9rl.c @@ -242,11 +242,6 @@ static struct at91_gpio_bank at91sam9rl_gpio[] = { } }; -static void at91sam9rl_reset(void) -{ - at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); -} - static void at91sam9rl_poweroff(void) { at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); @@ -281,7 +276,7 @@ void __init at91sam9rl_initialize(unsigned long main_clock) /* Map SRAM */ iotable_init(at91sam9rl_sram_desc, ARRAY_SIZE(at91sam9rl_sram_desc)); - at91_arch_reset = at91sam9rl_reset; + at91_arch_reset = at91sam9_alt_reset; pm_power_off = at91sam9rl_poweroff; at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0); diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c new file mode 100644 index 000000000000..bba5a560e02b --- /dev/null +++ b/arch/arm/mach-at91/board-pcontrol-g20.c @@ -0,0 +1,322 @@ +/* + * Copyright (C) 2010 Christian Glindkamp <christian.glindkamp@taskit.de> + * taskit GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +/* + * copied and adjusted from board-stamp9g20.c + * by Peter Gsellmann <pgsellmann@portner-elektronik.at> + */ + +#include <linux/mm.h> +#include <linux/platform_device.h> +#include <linux/gpio.h> +#include <linux/w1-gpio.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +#include <mach/board.h> +#include <mach/at91sam9_smc.h> + +#include "sam9_smc.h" +#include "generic.h" + + +static void __init pcontrol_g20_map_io(void) +{ + /* Initialize processor: 18.432 MHz crystal */ + at91sam9260_initialize(18432000); + + /* DGBU on ttyS0. (Rx, Tx) only TTL -> JTAG connector X7 17,19 ) */ + at91_register_uart(0, 0, 0); + + /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) piggyback A2 */ + at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS + | ATMEL_UART_RTS); + + /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) isolated RS485 X5 */ + at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS + | ATMEL_UART_RTS); + + /* USART2 on ttyS3. (Rx, Tx) 9bit-Bus Multidrop-mode X4 */ + at91_register_uart(AT91SAM9260_ID_US4, 3, 0); + + /* set serial console to ttyS0 (ie, DBGU) */ + at91_set_serial_console(0); +} + + +static void __init init_irq(void) +{ + at91sam9260_init_interrupts(NULL); +} + + +/* + * NAND flash 512MiB 1,8V 8-bit, sector size 128 KiB + */ +static struct atmel_nand_data __initdata nand_data = { + .ale = 21, + .cle = 22, + .rdy_pin = AT91_PIN_PC13, + .enable_pin = AT91_PIN_PC14, +}; + +/* + * Bus timings; unit = 7.57ns + */ +static struct sam9_smc_config __initdata nand_smc_config = { + .ncs_read_setup = 0, + .nrd_setup = 2, + .ncs_write_setup = 0, + .nwe_setup = 2, + + .ncs_read_pulse = 4, + .nrd_pulse = 4, + .ncs_write_pulse = 4, + .nwe_pulse = 4, + + .read_cycle = 7, + .write_cycle = 7, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE + | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8, + .tdf_cycles = 3, +}; + +static struct sam9_smc_config __initdata pcontrol_smc_config[2] = { { + .ncs_read_setup = 16, + .nrd_setup = 18, + .ncs_write_setup = 16, + .nwe_setup = 18, + + .ncs_read_pulse = 63, + .nrd_pulse = 55, + .ncs_write_pulse = 63, + .nwe_pulse = 55, + + .read_cycle = 127, + .write_cycle = 127, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE + | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_SELECT + | AT91_SMC_DBW_8 | AT91_SMC_PS_4 + | AT91_SMC_TDFMODE, + .tdf_cycles = 3, +}, { + .ncs_read_setup = 0, + .nrd_setup = 0, + .ncs_write_setup = 0, + .nwe_setup = 1, + + .ncs_read_pulse = 8, + .nrd_pulse = 8, + .ncs_write_pulse = 5, + .nwe_pulse = 4, + + .read_cycle = 8, + .write_cycle = 7, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE + | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_SELECT + | AT91_SMC_DBW_16 | AT91_SMC_PS_8 + | AT91_SMC_TDFMODE, + .tdf_cycles = 1, +} }; + +static void __init add_device_nand(void) +{ + /* configure chip-select 3 (NAND) */ + sam9_smc_configure(3, &nand_smc_config); + at91_add_device_nand(&nand_data); +} + + +static void __init add_device_pcontrol(void) +{ + /* configure chip-select 4 (IO compatible to 8051 X4 ) */ + sam9_smc_configure(4, &pcontrol_smc_config[0]); + /* configure chip-select 7 (FerroRAM 256KiBx16bit MR2A16A D4 ) */ + sam9_smc_configure(7, &pcontrol_smc_config[1]); +} + + +/* + * MCI (SD/MMC) + * det_pin, wp_pin and vcc_pin are not connected + */ +#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE) +static struct mci_platform_data __initdata mmc_data = { + .slot[0] = { + .bus_width = 4, + }, +}; +#else +static struct at91_mmc_data __initdata mmc_data = { + .wire4 = 1, +}; +#endif + + +/* + * USB Host port + */ +static struct at91_usbh_data __initdata usbh_data = { + .ports = 2, +}; + + +/* + * USB Device port + */ +static struct at91_udc_data __initdata pcontrol_g20_udc_data = { + .vbus_pin = AT91_PIN_PA22, /* Detect +5V bus voltage */ + .pullup_pin = AT91_PIN_PA4, /* K-state, active low */ +}; + + +/* + * MACB Ethernet device + */ +static struct at91_eth_data __initdata macb_data = { + .phy_irq_pin = AT91_PIN_PA28, + .is_rmii = 1, +}; + + +/* + * I2C devices: eeprom and phy/switch + */ +static struct i2c_board_info __initdata pcontrol_g20_i2c_devices[] = { +{ /* D7 address width=2, 8KiB */ + I2C_BOARD_INFO("24c64", 0x50) +}, { /* D8 address width=1, 1 byte has 32 bits! */ + I2C_BOARD_INFO("lan9303", 0x0a) +}, }; + + +/* + * LEDs + */ +static struct gpio_led pcontrol_g20_leds[] = { + { + .name = "LED1", /* red H5 */ + .gpio = AT91_PIN_PB18, + .active_low = 1, + .default_trigger = "none", /* supervisor */ + }, { + .name = "LED2", /* yellow H7 */ + .gpio = AT91_PIN_PB19, + .active_low = 1, + .default_trigger = "mmc0", /* SD-card activity */ + }, { + .name = "LED3", /* green H2 */ + .gpio = AT91_PIN_PB20, + .active_low = 1, + .default_trigger = "heartbeat", /* blinky */ + }, { + .name = "LED4", /* red H3 */ + .gpio = AT91_PIN_PC6, + .active_low = 1, + .default_trigger = "none", /* connection lost */ + }, { + .name = "LED5", /* yellow H6 */ + .gpio = AT91_PIN_PC7, + .active_low = 1, + .default_trigger = "none", /* unsent data */ + }, { + .name = "LED6", /* green H1 */ + .gpio = AT91_PIN_PC9, + .active_low = 1, + .default_trigger = "none", /* snafu */ + } +}; + + +/* + * SPI devices + */ +static struct spi_board_info pcontrol_g20_spi_devices[] = { + { + .modalias = "spidev", /* HMI port X4 */ + .chip_select = 1, + .max_speed_hz = 50 * 1000 * 1000, + .bus_num = 0, + }, { + .modalias = "spidev", /* piggyback A2 */ + .chip_select = 0, + .max_speed_hz = 50 * 1000 * 1000, + .bus_num = 1, + }, +}; + + +/* + * Dallas 1-Wire DS2431 + */ +static struct w1_gpio_platform_data w1_gpio_pdata = { + .pin = AT91_PIN_PA29, + .is_open_drain = 1, +}; + +static struct platform_device w1_device = { + .name = "w1-gpio", + .id = -1, + .dev.platform_data = &w1_gpio_pdata, +}; + +static void add_wire1(void) +{ + at91_set_GPIO_periph(w1_gpio_pdata.pin, 1); + at91_set_multi_drive(w1_gpio_pdata.pin, 1); + platform_device_register(&w1_device); +} + + +static void __init pcontrol_g20_board_init(void) +{ + at91_add_device_serial(); + add_device_nand(); +#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE) + at91_add_device_mci(0, &mmc_data); +#else + at91_add_device_mmc(0, &mmc_data); +#endif + at91_add_device_usbh(&usbh_data); + at91_add_device_eth(&macb_data); + at91_add_device_i2c(pcontrol_g20_i2c_devices, + ARRAY_SIZE(pcontrol_g20_i2c_devices)); + add_wire1(); + add_device_pcontrol(); + at91_add_device_spi(pcontrol_g20_spi_devices, + ARRAY_SIZE(pcontrol_g20_spi_devices)); + at91_add_device_udc(&pcontrol_g20_udc_data); + at91_gpio_leds(pcontrol_g20_leds, + ARRAY_SIZE(pcontrol_g20_leds)); + /* piggyback A2 */ + at91_set_gpio_output(AT91_PIN_PB31, 1); +} + + +MACHINE_START(PCONTROL_G20, "PControl G20") + /* Maintainer: pgsellmann@portner-elektronik.at */ + .boot_params = AT91_SDRAM_BASE + 0x100, + .timer = &at91sam926x_timer, + .map_io = pcontrol_g20_map_io, + .init_irq = init_irq, + .init_machine = pcontrol_g20_board_init, +MACHINE_END diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c index 7913984f6de9..86ff4b52db32 100644 --- a/arch/arm/mach-at91/board-sam9m10g45ek.c +++ b/arch/arm/mach-at91/board-sam9m10g45ek.c @@ -24,7 +24,9 @@ #include <linux/input.h> #include <linux/leds.h> #include <linux/clk.h> +#include <linux/atmel-mci.h> +#include <mach/hardware.h> #include <video/atmel_lcdc.h> #include <asm/setup.h> @@ -98,6 +100,25 @@ static struct spi_board_info ek_spi_devices[] = { /* + * MCI (SD/MMC) + */ +static struct mci_platform_data __initdata mci0_data = { + .slot[0] = { + .bus_width = 4, + .detect_pin = AT91_PIN_PD10, + }, +}; + +static struct mci_platform_data __initdata mci1_data = { + .slot[0] = { + .bus_width = 4, + .detect_pin = AT91_PIN_PD11, + .wp_pin = AT91_PIN_PD29, + }, +}; + + +/* * MACB Ethernet device */ static struct at91_eth_data __initdata ek_macb_data = { @@ -380,6 +401,9 @@ static void __init ek_board_init(void) at91_add_device_usba(&ek_usba_udc_data); /* SPI */ at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices)); + /* MMC */ + at91_add_device_mci(0, &mci0_data); + at91_add_device_mci(1, &mci1_data); /* Ethernet */ at91_add_device_eth(&ek_macb_data); /* NAND */ diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h index 65c3dc5ba0d0..0c66deb2db39 100644 --- a/arch/arm/mach-at91/generic.h +++ b/arch/arm/mach-at91/generic.h @@ -46,6 +46,9 @@ extern void __init at91_clock_associate(const char *id, struct device *dev, cons extern void at91_irq_suspend(void); extern void at91_irq_resume(void); +/* reset */ +extern void at91sam9_alt_reset(void); + /* GPIO */ #define AT91RM9200_PQFP 3 /* AT91RM9200 PQFP package has 3 banks */ #define AT91RM9200_BGA 4 /* AT91RM9200 BGA package has 4 banks */ diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 615668986480..dafbacc25eb1 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -258,16 +258,23 @@ static int at91_pm_enter(suspend_state_t state) * NOTE: the Wait-for-Interrupt instruction needs to be * in icache so no SDRAM accesses are needed until the * wakeup IRQ occurs and self-refresh is terminated. + * For ARM 926 based chips, this requirement is weaker + * as at91sam9 can access a RAM in self-refresh mode. */ - asm("b 1f; .align 5; 1:"); - asm("mcr p15, 0, r0, c7, c10, 4"); /* drain write buffer */ + asm volatile ( "mov r0, #0\n\t" + "b 1f\n\t" + ".align 5\n\t" + "1: mcr p15, 0, r0, c7, c10, 4\n\t" + : /* no output */ + : /* no input */ + : "r0"); saved_lpr = sdram_selfrefresh_enable(); - asm("mcr p15, 0, r0, c7, c0, 4"); /* wait for interrupt */ + wait_for_interrupt_enable(); sdram_selfrefresh_disable(saved_lpr); break; case PM_SUSPEND_ON: - asm("mcr p15, 0, r0, c7, c0, 4"); /* wait for interrupt */ + cpu_do_idle(); break; default: diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h index 8c87d0c1b8f8..ce9a20699111 100644 --- a/arch/arm/mach-at91/pm.h +++ b/arch/arm/mach-at91/pm.h @@ -21,6 +21,8 @@ static inline u32 sdram_selfrefresh_enable(void) } #define sdram_selfrefresh_disable(saved_lpr) at91_sys_write(AT91_SDRAMC_LPR, saved_lpr) +#define wait_for_interrupt_enable() asm volatile ("mcr p15, 0, %0, c7, c0, 4" \ + : : "r" (0)) #elif defined(CONFIG_ARCH_AT91CAP9) #include <mach/at91cap9_ddrsdr.h> @@ -38,6 +40,7 @@ static inline u32 sdram_selfrefresh_enable(void) } #define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr) +#define wait_for_interrupt_enable() cpu_do_idle() #elif defined(CONFIG_ARCH_AT91SAM9G45) #include <mach/at91sam9_ddrsdr.h> @@ -74,6 +77,7 @@ static inline u32 sdram_selfrefresh_enable(void) at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); \ at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); \ } while (0) +#define wait_for_interrupt_enable() cpu_do_idle() #else #include <mach/at91sam9_sdramc.h> @@ -98,5 +102,6 @@ static inline u32 sdram_selfrefresh_enable(void) } #define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr) +#define wait_for_interrupt_enable() cpu_do_idle() #endif diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S index b6b00a1f6125..f7922a436172 100644 --- a/arch/arm/mach-at91/pm_slowclock.S +++ b/arch/arm/mach-at91/pm_slowclock.S @@ -124,6 +124,7 @@ ENTRY(at91_slow_clock) ldr r5, .at91_va_base_ramc1 /* Drain write buffer */ + mov r0, #0 mcr p15, 0, r0, c7, c10, 4 #ifdef CONFIG_ARCH_AT91RM9200 diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 71f90f864748..b77b860b36d7 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -20,23 +20,23 @@ config ARCH_DAVINCI_DM644x select ARCH_DAVINCI_DMx config ARCH_DAVINCI_DM355 - bool "DaVinci 355 based system" + bool "DaVinci 355 based system" select AINTC select ARCH_DAVINCI_DMx config ARCH_DAVINCI_DM646x - bool "DaVinci 646x based system" + bool "DaVinci 646x based system" select AINTC select ARCH_DAVINCI_DMx config ARCH_DAVINCI_DA830 - bool "DA830/OMAP-L137 based system" + bool "DA830/OMAP-L137/AM17x based system" select CP_INTC select ARCH_DAVINCI_DA8XX select CPU_DCACHE_WRITETHROUGH # needed on silicon revs 1.0, 1.1 config ARCH_DAVINCI_DA850 - bool "DA850/OMAP-L138 based system" + bool "DA850/OMAP-L138/AM18x based system" select CP_INTC select ARCH_DAVINCI_DA8XX select ARCH_HAS_CPUFREQ @@ -115,21 +115,21 @@ config MACH_DAVINCI_DM365_EVM for development is a DM365 EVM config MACH_DAVINCI_DA830_EVM - bool "TI DA830/OMAP-L137 Reference Platform" + bool "TI DA830/OMAP-L137/AM17x Reference Platform" default ARCH_DAVINCI_DA830 depends on ARCH_DAVINCI_DA830 select GPIO_PCF857X help - Say Y here to select the TI DA830/OMAP-L137 Evaluation Module. + Say Y here to select the TI DA830/OMAP-L137/AM17x Evaluation Module. choice - prompt "Select DA830/OMAP-L137 UI board peripheral" + prompt "Select DA830/OMAP-L137/AM17x UI board peripheral" depends on MACH_DAVINCI_DA830_EVM help - The presence of UI card on the DA830/OMAP-L137 EVM is detected - automatically based on successful probe of the I2C based GPIO - expander on that board. This option selected in this menu has - an effect only in case of a successful UI card detection. + The presence of UI card on the DA830/OMAP-L137/AM17x EVM is + detected automatically based on successful probe of the I2C + based GPIO expander on that board. This option selected in this + menu has an effect only in case of a successful UI card detection. config DA830_UI_LCD bool "LCD" @@ -140,23 +140,23 @@ config DA830_UI_LCD config DA830_UI_NAND bool "NAND flash" help - Say Y here to use the NAND flash. Do not forget to setup + Say Y here to use the NAND flash. Do not forget to setup the switch correctly. endchoice config MACH_DAVINCI_DA850_EVM - bool "TI DA850/OMAP-L138 Reference Platform" + bool "TI DA850/OMAP-L138/AM18x Reference Platform" default ARCH_DAVINCI_DA850 depends on ARCH_DAVINCI_DA850 select GPIO_PCA953X help - Say Y here to select the TI DA850/OMAP-L138 Evaluation Module. + Say Y here to select the TI DA850/OMAP-L138/AM18x Evaluation Module. choice prompt "Select peripherals connected to expander on UI board" depends on MACH_DAVINCI_DA850_EVM help - The presence of User Interface (UI) card on the DA850/OMAP-L138 + The presence of User Interface (UI) card on the DA850/OMAP-L138/AM18x EVM is detected automatically based on successful probe of the I2C based GPIO expander on that card. This option selected in this menu has an effect only in case of a successful UI card detection. @@ -165,13 +165,13 @@ config DA850_UI_NONE bool "No peripheral is enabled" help Say Y if you do not want to enable any of the peripherals connected - to TCA6416 expander on DA850/OMAP-L138 EVM UI card + to TCA6416 expander on DA850/OMAP-L138/AM18x EVM UI card config DA850_UI_RMII bool "RMII Ethernet PHY" help - Say Y if you want to use the RMII PHY on the DA850/OMAP-L138 EVM. - This PHY is found on the UI daughter card that is supplied with + Say Y if you want to use the RMII PHY on the DA850/OMAP-L138/AM18x + EVM. This PHY is found on the UI daughter card that is supplied with the EVM. NOTE: Please take care while choosing this option, MII PHY will not be functional if RMII mode is selected. @@ -185,6 +185,22 @@ config MACH_TNETV107X help Say Y here to select the TI TNETV107X Evaluation Module. +config MACH_MITYOMAPL138 + bool "Critical Link MityDSP-L138/MityARM-1808 SoM" + depends on ARCH_DAVINCI_DA850 + help + Say Y here to select the Critical Link MityDSP-L138/MityARM-1808 + System on Module. Information on this SoM may be found at + http://www.mitydsp.com + +config MACH_OMAPL138_HAWKBOARD + bool "TI AM1808 / OMAPL-138 Hawkboard platform" + depends on ARCH_DAVINCI_DA850 + help + Say Y here to select the TI AM1808 / OMAPL-138 Hawkboard platform . + Information of this board may be found at + http://www.hawkboard.org/ + config DAVINCI_MUX bool "DAVINCI multiplexing support" depends on ARCH_DAVINCI @@ -195,20 +211,20 @@ config DAVINCI_MUX say Y. config DAVINCI_MUX_DEBUG - bool "Multiplexing debug output" - depends on DAVINCI_MUX - help - Makes the multiplexing functions print out a lot of debug info. - This is useful if you want to find out the correct values of the - multiplexing registers. + bool "Multiplexing debug output" + depends on DAVINCI_MUX + help + Makes the multiplexing functions print out a lot of debug info. + This is useful if you want to find out the correct values of the + multiplexing registers. config DAVINCI_MUX_WARNINGS - bool "Warn about pins the bootloader didn't set up" - depends on DAVINCI_MUX - help - Choose Y here to warn whenever driver initialization logic needs - to change the pin multiplexing setup. When there are no warnings - printed, it's safe to deselect DAVINCI_MUX for your product. + bool "Warn about pins the bootloader didn't set up" + depends on DAVINCI_MUX + help + Choose Y here to warn whenever driver initialization logic needs + to change the pin multiplexing setup. When there are no warnings + printed, it's safe to deselect DAVINCI_MUX for your product. config DAVINCI_RESET_CLOCKS bool "Reset unused clocks during boot" diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index eab4c0fd667a..0b87a1ca2bb3 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -5,7 +5,7 @@ # Common objects obj-y := time.o clock.o serial.o io.o psc.o \ - gpio.o dma.o usb.o common.o sram.o + gpio.o dma.o usb.o common.o sram.o aemif.o obj-$(CONFIG_DAVINCI_MUX) += mux.o @@ -33,6 +33,8 @@ obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += board-da830-evm.o obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o obj-$(CONFIG_MACH_TNETV107X) += board-tnetv107x-evm.o +obj-$(CONFIG_MACH_MITYOMAPL138) += board-mityomapl138.o +obj-$(CONFIG_MACH_OMAPL138_HAWKBOARD) += board-omapl138-hawk.o # Power Management obj-$(CONFIG_CPU_FREQ) += cpufreq.o diff --git a/arch/arm/mach-davinci/aemif.c b/arch/arm/mach-davinci/aemif.c new file mode 100644 index 000000000000..9c3f500fc12f --- /dev/null +++ b/arch/arm/mach-davinci/aemif.c @@ -0,0 +1,133 @@ +/* + * AEMIF support for DaVinci SoCs + * + * Copyright (C) 2010 Texas Instruments Incorporated. http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/io.h> +#include <linux/err.h> +#include <linux/clk.h> +#include <linux/module.h> +#include <linux/time.h> + +#include <mach/aemif.h> + +/* Timing value configuration */ + +#define TA(x) ((x) << 2) +#define RHOLD(x) ((x) << 4) +#define RSTROBE(x) ((x) << 7) +#define RSETUP(x) ((x) << 13) +#define WHOLD(x) ((x) << 17) +#define WSTROBE(x) ((x) << 20) +#define WSETUP(x) ((x) << 26) + +#define TA_MAX 0x3 +#define RHOLD_MAX 0x7 +#define RSTROBE_MAX 0x3f +#define RSETUP_MAX 0xf +#define WHOLD_MAX 0x7 +#define WSTROBE_MAX 0x3f +#define WSETUP_MAX 0xf + +#define TIMING_MASK (TA(TA_MAX) | \ + RHOLD(RHOLD_MAX) | \ + RSTROBE(RSTROBE_MAX) | \ + RSETUP(RSETUP_MAX) | \ + WHOLD(WHOLD_MAX) | \ + WSTROBE(WSTROBE_MAX) | \ + WSETUP(WSETUP_MAX)) + +/* + * aemif_calc_rate - calculate timing data. + * @wanted: The cycle time needed in nanoseconds. + * @clk: The input clock rate in kHz. + * @max: The maximum divider value that can be programmed. + * + * On success, returns the calculated timing value minus 1 for easy + * programming into AEMIF timing registers, else negative errno. + */ +static int aemif_calc_rate(int wanted, unsigned long clk, int max) +{ + int result; + + result = DIV_ROUND_UP((wanted * clk), NSEC_PER_MSEC) - 1; + + pr_debug("%s: result %d from %ld, %d\n", __func__, result, clk, wanted); + + /* It is generally OK to have a more relaxed timing than requested... */ + if (result < 0) + result = 0; + + /* ... But configuring tighter timings is not an option. */ + else if (result > max) + result = -EINVAL; + + return result; +} + +/** + * davinci_aemif_setup_timing - setup timing values for a given AEMIF interface + * @t: timing values to be progammed + * @base: The virtual base address of the AEMIF interface + * @cs: chip-select to program the timing values for + * + * This function programs the given timing values (in real clock) into the + * AEMIF registers taking the AEMIF clock into account. + * + * This function does not use any locking while programming the AEMIF + * because it is expected that there is only one user of a given + * chip-select. + * + * Returns 0 on success, else negative errno. + */ +int davinci_aemif_setup_timing(struct davinci_aemif_timing *t, + void __iomem *base, unsigned cs) +{ + unsigned set, val; + unsigned ta, rhold, rstrobe, rsetup, whold, wstrobe, wsetup; + unsigned offset = A1CR_OFFSET + cs * 4; + struct clk *aemif_clk; + unsigned long clkrate; + + if (!t) + return 0; /* Nothing to do */ + + aemif_clk = clk_get(NULL, "aemif"); + if (IS_ERR(aemif_clk)) + return PTR_ERR(aemif_clk); + + clkrate = clk_get_rate(aemif_clk); + + clkrate /= 1000; /* turn clock into kHz for ease of use */ + + ta = aemif_calc_rate(t->ta, clkrate, TA_MAX); + rhold = aemif_calc_rate(t->rhold, clkrate, RHOLD_MAX); + rstrobe = aemif_calc_rate(t->rstrobe, clkrate, RSTROBE_MAX); + rsetup = aemif_calc_rate(t->rsetup, clkrate, RSETUP_MAX); + whold = aemif_calc_rate(t->whold, clkrate, WHOLD_MAX); + wstrobe = aemif_calc_rate(t->wstrobe, clkrate, WSTROBE_MAX); + wsetup = aemif_calc_rate(t->wsetup, clkrate, WSETUP_MAX); + + if (ta < 0 || rhold < 0 || rstrobe < 0 || rsetup < 0 || + whold < 0 || wstrobe < 0 || wsetup < 0) { + pr_err("%s: cannot get suitable timings\n", __func__); + return -EINVAL; + } + + set = TA(ta) | RHOLD(rhold) | RSTROBE(rstrobe) | RSETUP(rsetup) | + WHOLD(whold) | WSTROBE(wstrobe) | WSETUP(wsetup); + + val = __raw_readl(base + offset); + val &= ~TIMING_MASK; + val |= set; + __raw_writel(val, base + offset); + + return 0; +} +EXPORT_SYMBOL(davinci_aemif_setup_timing); diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c index 7f3cdbfc0fbb..b52a3a1abd94 100644 --- a/arch/arm/mach-davinci/board-da830-evm.c +++ b/arch/arm/mach-davinci/board-da830-evm.c @@ -29,10 +29,9 @@ #include <mach/nand.h> #include <mach/da8xx.h> #include <mach/usb.h> +#include <mach/aemif.h> -#define DA830_EVM_PHY_MASK 0x0 -#define DA830_EVM_MDIO_FREQUENCY 2200000 /* PHY bus frequency */ - +#define DA830_EVM_PHY_ID "" /* * USB1 VBUS is controlled by GPIO1[15], over-current is reported on GPIO2[4]. */ @@ -360,6 +359,16 @@ static struct nand_bbt_descr da830_evm_nand_bbt_mirror_descr = { .pattern = da830_evm_nand_mirror_pattern }; +static struct davinci_aemif_timing da830_evm_nandflash_timing = { + .wsetup = 24, + .wstrobe = 21, + .whold = 14, + .rsetup = 19, + .rstrobe = 50, + .rhold = 0, + .ta = 20, +}; + static struct davinci_nand_pdata da830_evm_nand_pdata = { .parts = da830_evm_nand_partitions, .nr_parts = ARRAY_SIZE(da830_evm_nand_partitions), @@ -368,6 +377,7 @@ static struct davinci_nand_pdata da830_evm_nand_pdata = { .options = NAND_USE_FLASH_BBT, .bbt_td = &da830_evm_nand_bbt_main_descr, .bbt_md = &da830_evm_nand_bbt_mirror_descr, + .timing = &da830_evm_nandflash_timing, }; static struct resource da830_evm_nand_resources[] = { @@ -546,9 +556,8 @@ static __init void da830_evm_init(void) da830_evm_usb_init(); - soc_info->emac_pdata->phy_mask = DA830_EVM_PHY_MASK; - soc_info->emac_pdata->mdio_max_freq = DA830_EVM_MDIO_FREQUENCY; soc_info->emac_pdata->rmii_en = 1; + soc_info->emac_pdata->phy_id = DA830_EVM_PHY_ID; ret = davinci_cfg_reg_list(da830_cpgmac_pins); if (ret) @@ -586,6 +595,9 @@ static __init void da830_evm_init(void) #ifdef CONFIG_SERIAL_8250_CONSOLE static int __init da830_evm_console_init(void) { + if (!machine_is_davinci_da830_evm()) + return 0; + return add_preferred_console("ttyS", 2, "115200"); } console_initcall(da830_evm_console_init); @@ -596,7 +608,7 @@ static void __init da830_evm_map_io(void) da830_init(); } -MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137 EVM") +MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137/AM17x EVM") .boot_params = (DA8XX_DDR_BASE + 0x100), .map_io = da830_evm_map_io, .init_irq = cp_intc_init, diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index b26f5cbfce3e..c6e11c682e4c 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -26,7 +26,6 @@ #include <linux/mtd/physmap.h> #include <linux/regulator/machine.h> #include <linux/regulator/tps6507x.h> -#include <linux/mfd/tps6507x.h> #include <linux/input/tps6507x-ts.h> #include <asm/mach-types.h> @@ -36,10 +35,9 @@ #include <mach/da8xx.h> #include <mach/nand.h> #include <mach/mux.h> +#include <mach/aemif.h> -#define DA850_EVM_PHY_MASK 0x1 -#define DA850_EVM_MDIO_FREQUENCY 2200000 /* PHY bus frequency */ - +#define DA850_EVM_PHY_ID "0:00" #define DA850_LCD_PWR_PIN GPIO_TO_PIN(2, 8) #define DA850_LCD_BL_PIN GPIO_TO_PIN(2, 15) @@ -110,7 +108,7 @@ static struct platform_device da850_pm_device = { * to boot, using TI's tools to install the secondary boot loader * (UBL) and U-Boot. */ -struct mtd_partition da850_evm_nandflash_partition[] = { +static struct mtd_partition da850_evm_nandflash_partition[] = { { .name = "u-boot env", .offset = 0, @@ -143,12 +141,23 @@ struct mtd_partition da850_evm_nandflash_partition[] = { }, }; +static struct davinci_aemif_timing da850_evm_nandflash_timing = { + .wsetup = 24, + .wstrobe = 21, + .whold = 14, + .rsetup = 19, + .rstrobe = 50, + .rhold = 0, + .ta = 20, +}; + static struct davinci_nand_pdata da850_evm_nandflash_data = { .parts = da850_evm_nandflash_partition, .nr_parts = ARRAY_SIZE(da850_evm_nandflash_partition), .ecc_mode = NAND_ECC_HW, .ecc_bits = 4, .options = NAND_USE_FLASH_BBT, + .timing = &da850_evm_nandflash_timing, }; static struct resource da850_evm_nandflash_resource[] = { @@ -196,6 +205,30 @@ static void __init da850_evm_init_nor(void) iounmap(aemif_addr); } +static const short da850_evm_nand_pins[] = { + DA850_EMA_D_0, DA850_EMA_D_1, DA850_EMA_D_2, DA850_EMA_D_3, + DA850_EMA_D_4, DA850_EMA_D_5, DA850_EMA_D_6, DA850_EMA_D_7, + DA850_EMA_A_1, DA850_EMA_A_2, DA850_NEMA_CS_3, DA850_NEMA_CS_4, + DA850_NEMA_WE, DA850_NEMA_OE, + -1 +}; + +static const short da850_evm_nor_pins[] = { + DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2, + DA850_NEMA_WE, DA850_NEMA_OE, DA850_EMA_D_0, DA850_EMA_D_1, + DA850_EMA_D_2, DA850_EMA_D_3, DA850_EMA_D_4, DA850_EMA_D_5, + DA850_EMA_D_6, DA850_EMA_D_7, DA850_EMA_D_8, DA850_EMA_D_9, + DA850_EMA_D_10, DA850_EMA_D_11, DA850_EMA_D_12, DA850_EMA_D_13, + DA850_EMA_D_14, DA850_EMA_D_15, DA850_EMA_A_0, DA850_EMA_A_1, + DA850_EMA_A_2, DA850_EMA_A_3, DA850_EMA_A_4, DA850_EMA_A_5, + DA850_EMA_A_6, DA850_EMA_A_7, DA850_EMA_A_8, DA850_EMA_A_9, + DA850_EMA_A_10, DA850_EMA_A_11, DA850_EMA_A_12, DA850_EMA_A_13, + DA850_EMA_A_14, DA850_EMA_A_15, DA850_EMA_A_16, DA850_EMA_A_17, + DA850_EMA_A_18, DA850_EMA_A_19, DA850_EMA_A_20, DA850_EMA_A_21, + DA850_EMA_A_22, DA850_EMA_A_23, + -1 +}; + static u32 ui_card_detected; #if defined(CONFIG_MMC_DAVINCI) || \ @@ -205,17 +238,17 @@ static u32 ui_card_detected; #define HAS_MMC 0 #endif -static __init void da850_evm_setup_nor_nand(void) +static inline void da850_evm_setup_nor_nand(void) { int ret = 0; if (ui_card_detected & !HAS_MMC) { - ret = davinci_cfg_reg_list(da850_nand_pins); + ret = davinci_cfg_reg_list(da850_evm_nand_pins); if (ret) pr_warning("da850_evm_init: nand mux setup failed: " "%d\n", ret); - ret = davinci_cfg_reg_list(da850_nor_pins); + ret = davinci_cfg_reg_list(da850_evm_nor_pins); if (ret) pr_warning("da850_evm_init: nor mux setup failed: %d\n", ret); @@ -406,7 +439,7 @@ static int da850_lcd_hw_init(void) /* TPS65070 voltage regulator support */ /* 3.3V */ -struct regulator_consumer_supply tps65070_dcdc1_consumers[] = { +static struct regulator_consumer_supply tps65070_dcdc1_consumers[] = { { .supply = "usb0_vdda33", }, @@ -416,7 +449,7 @@ struct regulator_consumer_supply tps65070_dcdc1_consumers[] = { }; /* 3.3V or 1.8V */ -struct regulator_consumer_supply tps65070_dcdc2_consumers[] = { +static struct regulator_consumer_supply tps65070_dcdc2_consumers[] = { { .supply = "dvdd3318_a", }, @@ -429,14 +462,14 @@ struct regulator_consumer_supply tps65070_dcdc2_consumers[] = { }; /* 1.2V */ -struct regulator_consumer_supply tps65070_dcdc3_consumers[] = { +static struct regulator_consumer_supply tps65070_dcdc3_consumers[] = { { .supply = "cvdd", }, }; /* 1.8V LDO */ -struct regulator_consumer_supply tps65070_ldo1_consumers[] = { +static struct regulator_consumer_supply tps65070_ldo1_consumers[] = { { .supply = "sata_vddr", }, @@ -452,7 +485,7 @@ struct regulator_consumer_supply tps65070_ldo1_consumers[] = { }; /* 1.2V LDO */ -struct regulator_consumer_supply tps65070_ldo2_consumers[] = { +static struct regulator_consumer_supply tps65070_ldo2_consumers[] = { { .supply = "sata_vdd", }, @@ -475,7 +508,7 @@ static struct tps6507x_reg_platform_data tps6507x_platform_data = { .defdcdc_default = true, }; -struct regulator_init_data tps65070_regulator_data[] = { +static struct regulator_init_data tps65070_regulator_data[] = { /* dcdc1 */ { .constraints = { @@ -576,6 +609,23 @@ static const short da850_evm_lcdc_pins[] = { -1 }; +static const short da850_evm_mii_pins[] = { + DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3, + DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER, + DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3, + DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK, + DA850_MDIO_D, + -1 +}; + +static const short da850_evm_rmii_pins[] = { + DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN, + DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1, + DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK, + DA850_MDIO_D, + -1 +}; + static int __init da850_evm_config_emac(void) { void __iomem *cfg_chip3_base; @@ -593,12 +643,12 @@ static int __init da850_evm_config_emac(void) if (rmii_en) { val |= BIT(8); - ret = davinci_cfg_reg_list(da850_rmii_pins); + ret = davinci_cfg_reg_list(da850_evm_rmii_pins); pr_info("EMAC: RMII PHY configured, MII PHY will not be" " functional\n"); } else { val &= ~BIT(8); - ret = davinci_cfg_reg_list(da850_cpgmac_pins); + ret = davinci_cfg_reg_list(da850_evm_mii_pins); pr_info("EMAC: MII PHY configured, RMII PHY will not be" " functional\n"); } @@ -625,8 +675,7 @@ static int __init da850_evm_config_emac(void) /* Enable/Disable MII MDIO clock */ gpio_direction_output(DA850_MII_MDIO_CLKEN_PIN, rmii_en); - soc_info->emac_pdata->phy_mask = DA850_EVM_PHY_MASK; - soc_info->emac_pdata->mdio_max_freq = DA850_EVM_MDIO_FREQUENCY; + soc_info->emac_pdata->phy_id = DA850_EVM_PHY_ID; ret = da8xx_register_emac(); if (ret) @@ -787,7 +836,7 @@ static __init void da850_evm_init(void) if (ret) pr_warning("da850_evm_init: rtc setup failed: %d\n", ret); - ret = da850_register_cpufreq(); + ret = da850_register_cpufreq("pll0_sysclk3"); if (ret) pr_warning("da850_evm_init: cpufreq registration failed: %d\n", ret); @@ -806,6 +855,9 @@ static __init void da850_evm_init(void) #ifdef CONFIG_SERIAL_8250_CONSOLE static int __init da850_evm_console_init(void) { + if (!machine_is_davinci_da850_evm()) + return 0; + return add_preferred_console("ttyS", 2, "115200"); } console_initcall(da850_evm_console_init); @@ -816,7 +868,7 @@ static void __init da850_evm_map_io(void) da850_init(); } -MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138 EVM") +MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138/AM18x EVM") .boot_params = (DA8XX_DDR_BASE + 0x100), .map_io = da850_evm_map_io, .init_irq = cp_intc_init, diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c index 944a0cbaf5cb..c67f684ee3e5 100644 --- a/arch/arm/mach-davinci/board-dm365-evm.c +++ b/arch/arm/mach-davinci/board-dm365-evm.c @@ -54,9 +54,7 @@ static inline int have_tvp7002(void) return 0; } -#define DM365_EVM_PHY_MASK (0x2) -#define DM365_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ - +#define DM365_EVM_PHY_ID "0:01" /* * A MAX-II CPLD is used for various board control functions. */ @@ -175,7 +173,9 @@ static struct at24_platform_data eeprom_info = { .context = (void *)0x7f00, }; -static struct snd_platform_data dm365_evm_snd_data; +static struct snd_platform_data dm365_evm_snd_data = { + .asp_chan_q = EVENTQ_3, +}; static struct i2c_board_info i2c_info[] = { { @@ -533,8 +533,7 @@ fail: /* ... and ENET ... */ dm365evm_emac_configure(); - soc_info->emac_pdata->phy_mask = DM365_EVM_PHY_MASK; - soc_info->emac_pdata->mdio_max_freq = DM365_EVM_MDIO_FREQUENCY; + soc_info->emac_pdata->phy_id = DM365_EVM_PHY_ID; resets &= ~BIT(3); /* ... and AIC33 */ diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c index d59fba15ba8d..0ca90b834586 100644 --- a/arch/arm/mach-davinci/board-dm644x-evm.c +++ b/arch/arm/mach-davinci/board-dm644x-evm.c @@ -37,10 +37,9 @@ #include <mach/nand.h> #include <mach/mmc.h> #include <mach/usb.h> +#include <mach/aemif.h> -#define DM644X_EVM_PHY_MASK (0x2) -#define DM644X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ - +#define DM644X_EVM_PHY_ID "0:01" #define LXT971_PHY_ID (0x001378e2) #define LXT971_PHY_MASK (0xfffffff0) @@ -137,11 +136,22 @@ static struct mtd_partition davinci_evm_nandflash_partition[] = { */ }; +static struct davinci_aemif_timing davinci_evm_nandflash_timing = { + .wsetup = 20, + .wstrobe = 40, + .whold = 20, + .rsetup = 10, + .rstrobe = 40, + .rhold = 10, + .ta = 40, +}; + static struct davinci_nand_pdata davinci_evm_nandflash_data = { .parts = davinci_evm_nandflash_partition, .nr_parts = ARRAY_SIZE(davinci_evm_nandflash_partition), .ecc_mode = NAND_ECC_HW, .options = NAND_USE_FLASH_BBT, + .timing = &davinci_evm_nandflash_timing, }; static struct resource davinci_evm_nandflash_resource[] = { @@ -695,9 +705,7 @@ static __init void davinci_evm_init(void) davinci_serial_init(&uart_config); dm644x_init_asp(&dm644x_evm_snd_data); - soc_info->emac_pdata->phy_mask = DM644X_EVM_PHY_MASK; - soc_info->emac_pdata->mdio_max_freq = DM644X_EVM_MDIO_FREQUENCY; - + soc_info->emac_pdata->phy_id = DM644X_EVM_PHY_ID; /* Register the fixup for PHY on DaVinci */ phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK, davinci_phy_fixup); diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c index 6890488fb92b..f6ac9ba74878 100644 --- a/arch/arm/mach-davinci/board-dm646x-evm.c +++ b/arch/arm/mach-davinci/board-dm646x-evm.c @@ -42,6 +42,7 @@ #include <mach/nand.h> #include <mach/clock.h> #include <mach/cdce949.h> +#include <mach/aemif.h> #include "clock.h" @@ -71,6 +72,16 @@ static struct mtd_partition davinci_nand_partitions[] = { } }; +static struct davinci_aemif_timing dm6467tevm_nandflash_timing = { + .wsetup = 29, + .wstrobe = 24, + .whold = 14, + .rsetup = 19, + .rstrobe = 33, + .rhold = 0, + .ta = 29, +}; + static struct davinci_nand_pdata davinci_nand_data = { .mask_cle = 0x80000, .mask_ale = 0x40000, @@ -718,9 +729,7 @@ static struct davinci_uart_config uart_config __initdata = { .enabled_uarts = (1 << 0), }; -#define DM646X_EVM_PHY_MASK (0x2) -#define DM646X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ - +#define DM646X_EVM_PHY_ID "0:01" /* * The following EDMA channels/slots are not being used by drivers (for * example: Timer, GPIO, UART events etc) on dm646x, hence they are being @@ -763,6 +772,9 @@ static __init void evm_init(void) dm646x_init_mcasp0(&dm646x_evm_snd_data[0]); dm646x_init_mcasp1(&dm646x_evm_snd_data[1]); + if (machine_is_davinci_dm6467tevm()) + davinci_nand_data.timing = &dm6467tevm_nandflash_timing; + platform_device_register(&davinci_nand_device); dm646x_init_edma(dm646x_edma_rsv); @@ -770,8 +782,7 @@ static __init void evm_init(void) if (HAS_ATA) davinci_init_ide(); - soc_info->emac_pdata->phy_mask = DM646X_EVM_PHY_MASK; - soc_info->emac_pdata->mdio_max_freq = DM646X_EVM_MDIO_FREQUENCY; + soc_info->emac_pdata->phy_id = DM646X_EVM_PHY_ID; } #define DM646X_EVM_REF_FREQ 27000000 diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c new file mode 100644 index 000000000000..0bb5f0ce4fdc --- /dev/null +++ b/arch/arm/mach-davinci/board-mityomapl138.c @@ -0,0 +1,422 @@ +/* + * Critical Link MityOMAP-L138 SoM + * + * Copyright (C) 2010 Critical Link LLC - http://www.criticallink.com + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of + * any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/console.h> +#include <linux/platform_device.h> +#include <linux/mtd/partitions.h> +#include <linux/regulator/machine.h> +#include <linux/i2c.h> +#include <linux/i2c/at24.h> +#include <linux/etherdevice.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <mach/common.h> +#include <mach/cp_intc.h> +#include <mach/da8xx.h> +#include <mach/nand.h> +#include <mach/mux.h> + +#define MITYOMAPL138_PHY_ID "0:03" + +#define FACTORY_CONFIG_MAGIC 0x012C0138 +#define FACTORY_CONFIG_VERSION 0x00010001 + +/* Data Held in On-Board I2C device */ +struct factory_config { + u32 magic; + u32 version; + u8 mac[6]; + u32 fpga_type; + u32 spare; + u32 serialnumber; + char partnum[32]; +}; + +static struct factory_config factory_config; + +static void read_factory_config(struct memory_accessor *a, void *context) +{ + int ret; + struct davinci_soc_info *soc_info = &davinci_soc_info; + + ret = a->read(a, (char *)&factory_config, 0, sizeof(factory_config)); + if (ret != sizeof(struct factory_config)) { + pr_warning("MityOMAPL138: Read Factory Config Failed: %d\n", + ret); + return; + } + + if (factory_config.magic != FACTORY_CONFIG_MAGIC) { + pr_warning("MityOMAPL138: Factory Config Magic Wrong (%X)\n", + factory_config.magic); + return; + } + + if (factory_config.version != FACTORY_CONFIG_VERSION) { + pr_warning("MityOMAPL138: Factory Config Version Wrong (%X)\n", + factory_config.version); + return; + } + + pr_info("MityOMAPL138: Found MAC = %pM\n", factory_config.mac); + pr_info("MityOMAPL138: Part Number = %s\n", factory_config.partnum); + if (is_valid_ether_addr(factory_config.mac)) + memcpy(soc_info->emac_pdata->mac_addr, + factory_config.mac, ETH_ALEN); + else + pr_warning("MityOMAPL138: Invalid MAC found " + "in factory config block\n"); +} + +static struct at24_platform_data mityomapl138_fd_chip = { + .byte_len = 256, + .page_size = 8, + .flags = AT24_FLAG_READONLY | AT24_FLAG_IRUGO, + .setup = read_factory_config, + .context = NULL, +}; + +static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = { + .bus_freq = 100, /* kHz */ + .bus_delay = 0, /* usec */ +}; + +/* TPS65023 voltage regulator support */ +/* 1.2V Core */ +static struct regulator_consumer_supply tps65023_dcdc1_consumers[] = { + { + .supply = "cvdd", + }, +}; + +/* 1.8V */ +static struct regulator_consumer_supply tps65023_dcdc2_consumers[] = { + { + .supply = "usb0_vdda18", + }, + { + .supply = "usb1_vdda18", + }, + { + .supply = "ddr_dvdd18", + }, + { + .supply = "sata_vddr", + }, +}; + +/* 1.2V */ +static struct regulator_consumer_supply tps65023_dcdc3_consumers[] = { + { + .supply = "sata_vdd", + }, + { + .supply = "usb_cvdd", + }, + { + .supply = "pll0_vdda", + }, + { + .supply = "pll1_vdda", + }, +}; + +/* 1.8V Aux LDO, not used */ +static struct regulator_consumer_supply tps65023_ldo1_consumers[] = { + { + .supply = "1.8v_aux", + }, +}; + +/* FPGA VCC Aux (2.5 or 3.3) LDO */ +static struct regulator_consumer_supply tps65023_ldo2_consumers[] = { + { + .supply = "vccaux", + }, +}; + +static struct regulator_init_data tps65023_regulator_data[] = { + /* dcdc1 */ + { + .constraints = { + .min_uV = 1150000, + .max_uV = 1350000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers), + .consumer_supplies = tps65023_dcdc1_consumers, + }, + /* dcdc2 */ + { + .constraints = { + .min_uV = 1800000, + .max_uV = 1800000, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers), + .consumer_supplies = tps65023_dcdc2_consumers, + }, + /* dcdc3 */ + { + .constraints = { + .min_uV = 1200000, + .max_uV = 1200000, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers), + .consumer_supplies = tps65023_dcdc3_consumers, + }, + /* ldo1 */ + { + .constraints = { + .min_uV = 1800000, + .max_uV = 1800000, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers), + .consumer_supplies = tps65023_ldo1_consumers, + }, + /* ldo2 */ + { + .constraints = { + .min_uV = 2500000, + .max_uV = 3300000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers), + .consumer_supplies = tps65023_ldo2_consumers, + }, +}; + +static struct i2c_board_info __initdata mityomap_tps65023_info[] = { + { + I2C_BOARD_INFO("tps65023", 0x48), + .platform_data = &tps65023_regulator_data[0], + }, + { + I2C_BOARD_INFO("24c02", 0x50), + .platform_data = &mityomapl138_fd_chip, + }, +}; + +static int __init pmic_tps65023_init(void) +{ + return i2c_register_board_info(1, mityomap_tps65023_info, + ARRAY_SIZE(mityomap_tps65023_info)); +} + +/* + * MityDSP-L138 includes a 256 MByte large-page NAND flash + * (128K blocks). + */ +static struct mtd_partition mityomapl138_nandflash_partition[] = { + { + .name = "rootfs", + .offset = 0, + .size = SZ_128M, + .mask_flags = 0, /* MTD_WRITEABLE, */ + }, + { + .name = "homefs", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + }, +}; + +static struct davinci_nand_pdata mityomapl138_nandflash_data = { + .parts = mityomapl138_nandflash_partition, + .nr_parts = ARRAY_SIZE(mityomapl138_nandflash_partition), + .ecc_mode = NAND_ECC_HW, + .options = NAND_USE_FLASH_BBT | NAND_BUSWIDTH_16, + .ecc_bits = 1, /* 4 bit mode is not supported with 16 bit NAND */ +}; + +static struct resource mityomapl138_nandflash_resource[] = { + { + .start = DA8XX_AEMIF_CS3_BASE, + .end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = DA8XX_AEMIF_CTL_BASE, + .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device mityomapl138_nandflash_device = { + .name = "davinci_nand", + .id = 0, + .dev = { + .platform_data = &mityomapl138_nandflash_data, + }, + .num_resources = ARRAY_SIZE(mityomapl138_nandflash_resource), + .resource = mityomapl138_nandflash_resource, +}; + +static struct platform_device *mityomapl138_devices[] __initdata = { + &mityomapl138_nandflash_device, +}; + +static void __init mityomapl138_setup_nand(void) +{ + platform_add_devices(mityomapl138_devices, + ARRAY_SIZE(mityomapl138_devices)); +} + +static struct davinci_uart_config mityomapl138_uart_config __initdata = { + .enabled_uarts = 0x7, +}; + +static const short mityomap_mii_pins[] = { + DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3, + DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER, + DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3, + DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK, + DA850_MDIO_D, + -1 +}; + +static const short mityomap_rmii_pins[] = { + DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN, + DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1, + DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK, + DA850_MDIO_D, + -1 +}; + +static void __init mityomapl138_config_emac(void) +{ + void __iomem *cfg_chip3_base; + int ret; + u32 val; + struct davinci_soc_info *soc_info = &davinci_soc_info; + + soc_info->emac_pdata->rmii_en = 0; /* hardcoded for now */ + + cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG); + val = __raw_readl(cfg_chip3_base); + + if (soc_info->emac_pdata->rmii_en) { + val |= BIT(8); + ret = davinci_cfg_reg_list(mityomap_rmii_pins); + pr_info("RMII PHY configured\n"); + } else { + val &= ~BIT(8); + ret = davinci_cfg_reg_list(mityomap_mii_pins); + pr_info("MII PHY configured\n"); + } + + if (ret) { + pr_warning("mii/rmii mux setup failed: %d\n", ret); + return; + } + + /* configure the CFGCHIP3 register for RMII or MII */ + __raw_writel(val, cfg_chip3_base); + + soc_info->emac_pdata->phy_id = MITYOMAPL138_PHY_ID; + + ret = da8xx_register_emac(); + if (ret) + pr_warning("emac registration failed: %d\n", ret); +} + +static struct davinci_pm_config da850_pm_pdata = { + .sleepcount = 128, +}; + +static struct platform_device da850_pm_device = { + .name = "pm-davinci", + .dev = { + .platform_data = &da850_pm_pdata, + }, + .id = -1, +}; + +static void __init mityomapl138_init(void) +{ + int ret; + + /* for now, no special EDMA channels are reserved */ + ret = da850_register_edma(NULL); + if (ret) + pr_warning("edma registration failed: %d\n", ret); + + ret = da8xx_register_watchdog(); + if (ret) + pr_warning("watchdog registration failed: %d\n", ret); + + davinci_serial_init(&mityomapl138_uart_config); + + ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata); + if (ret) + pr_warning("i2c0 registration failed: %d\n", ret); + + ret = pmic_tps65023_init(); + if (ret) + pr_warning("TPS65023 PMIC init failed: %d\n", ret); + + mityomapl138_setup_nand(); + + mityomapl138_config_emac(); + + ret = da8xx_register_rtc(); + if (ret) + pr_warning("rtc setup failed: %d\n", ret); + + ret = da850_register_cpufreq("pll0_sysclk3"); + if (ret) + pr_warning("cpufreq registration failed: %d\n", ret); + + ret = da8xx_register_cpuidle(); + if (ret) + pr_warning("cpuidle registration failed: %d\n", ret); + + ret = da850_register_pm(&da850_pm_device); + if (ret) + pr_warning("da850_evm_init: suspend registration failed: %d\n", + ret); +} + +#ifdef CONFIG_SERIAL_8250_CONSOLE +static int __init mityomapl138_console_init(void) +{ + if (!machine_is_mityomapl138()) + return 0; + + return add_preferred_console("ttyS", 1, "115200"); +} +console_initcall(mityomapl138_console_init); +#endif + +static void __init mityomapl138_map_io(void) +{ + da850_init(); +} + +MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808") + .boot_params = (DA8XX_DDR_BASE + 0x100), + .map_io = mityomapl138_map_io, + .init_irq = cp_intc_init, + .timer = &davinci_timer, + .init_machine = mityomapl138_init, +MACHINE_END diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c index a4def889275c..6c389ff1020e 100644 --- a/arch/arm/mach-davinci/board-neuros-osd2.c +++ b/arch/arm/mach-davinci/board-neuros-osd2.c @@ -39,9 +39,7 @@ #include <mach/mmc.h> #include <mach/usb.h> -#define NEUROS_OSD2_PHY_MASK 0x2 -#define NEUROS_OSD2_MDIO_FREQUENCY 2200000 /* PHY bus frequency */ - +#define NEUROS_OSD2_PHY_ID "0:01" #define LXT971_PHY_ID 0x001378e2 #define LXT971_PHY_MASK 0xfffffff0 @@ -252,8 +250,7 @@ static __init void davinci_ntosd2_init(void) davinci_serial_init(&uart_config); dm644x_init_asp(&dm644x_ntosd2_snd_data); - soc_info->emac_pdata->phy_mask = NEUROS_OSD2_PHY_MASK; - soc_info->emac_pdata->mdio_max_freq = NEUROS_OSD2_MDIO_FREQUENCY; + soc_info->emac_pdata->phy_id = NEUROS_OSD2_PHY_ID; davinci_setup_usb(1000, 8); /* diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c new file mode 100644 index 000000000000..0b8dbdb79fe0 --- /dev/null +++ b/arch/arm/mach-davinci/board-omapl138-hawk.c @@ -0,0 +1,62 @@ +/* + * Hawkboard.org based on TI's OMAP-L138 Platform + * + * Initial code: Syed Mohammed Khasim + * + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of + * any kind, whether express or implied. + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/console.h> +#include <linux/gpio.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +#include <mach/cp_intc.h> +#include <mach/da8xx.h> + +static struct davinci_uart_config omapl138_hawk_uart_config __initdata = { + .enabled_uarts = 0x7, +}; + +static __init void omapl138_hawk_init(void) +{ + int ret; + + davinci_serial_init(&omapl138_hawk_uart_config); + + ret = da8xx_register_watchdog(); + if (ret) + pr_warning("omapl138_hawk_init: " + "watchdog registration failed: %d\n", + ret); +} + +#ifdef CONFIG_SERIAL_8250_CONSOLE +static int __init omapl138_hawk_console_init(void) +{ + if (!machine_is_omapl138_hawkboard()) + return 0; + + return add_preferred_console("ttyS", 2, "115200"); +} +console_initcall(omapl138_hawk_console_init); +#endif + +static void __init omapl138_hawk_map_io(void) +{ + da850_init(); +} + +MACHINE_START(OMAPL138_HAWKBOARD, "AM18x/OMAP-L138 Hawkboard") + .boot_params = (DA8XX_DDR_BASE + 0x100), + .map_io = omapl138_hawk_map_io, + .init_irq = cp_intc_init, + .timer = &davinci_timer, + .init_machine = omapl138_hawk_init, +MACHINE_END diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c index 9bdf8aafcc84..61ac96d8f00d 100644 --- a/arch/arm/mach-davinci/board-sffsdr.c +++ b/arch/arm/mach-davinci/board-sffsdr.c @@ -42,9 +42,7 @@ #include <mach/mux.h> #include <mach/usb.h> -#define SFFSDR_PHY_MASK (0x2) -#define SFFSDR_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ - +#define SFFSDR_PHY_ID "0:01" static struct mtd_partition davinci_sffsdr_nandflash_partition[] = { /* U-Boot Environment: Block 0 * UBL: Block 1 @@ -143,8 +141,7 @@ static __init void davinci_sffsdr_init(void) ARRAY_SIZE(davinci_sffsdr_devices)); sffsdr_init_i2c(); davinci_serial_init(&uart_config); - soc_info->emac_pdata->phy_mask = SFFSDR_PHY_MASK; - soc_info->emac_pdata->mdio_max_freq = SFFSDR_MDIO_FREQUENCY; + soc_info->emac_pdata->phy_id = SFFSDR_PHY_ID; davinci_setup_usb(0, 0); /* We support only peripheral mode. */ /* mux VLYNQ pins */ diff --git a/arch/arm/mach-davinci/board-tnetv107x-evm.c b/arch/arm/mach-davinci/board-tnetv107x-evm.c index b4de35b78904..a6db85460227 100644 --- a/arch/arm/mach-davinci/board-tnetv107x-evm.c +++ b/arch/arm/mach-davinci/board-tnetv107x-evm.c @@ -23,6 +23,9 @@ #include <linux/ratelimit.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> +#include <linux/input.h> +#include <linux/input/matrix_keypad.h> + #include <asm/mach/arch.h> #include <asm/mach-types.h> @@ -141,10 +144,63 @@ static struct davinci_uart_config serial_config __initconst = { .enabled_uarts = BIT(1), }; +static const uint32_t keymap[] = { + KEY(0, 0, KEY_NUMERIC_1), + KEY(0, 1, KEY_NUMERIC_2), + KEY(0, 2, KEY_NUMERIC_3), + KEY(0, 3, KEY_FN_F1), + KEY(0, 4, KEY_MENU), + + KEY(1, 0, KEY_NUMERIC_4), + KEY(1, 1, KEY_NUMERIC_5), + KEY(1, 2, KEY_NUMERIC_6), + KEY(1, 3, KEY_UP), + KEY(1, 4, KEY_FN_F2), + + KEY(2, 0, KEY_NUMERIC_7), + KEY(2, 1, KEY_NUMERIC_8), + KEY(2, 2, KEY_NUMERIC_9), + KEY(2, 3, KEY_LEFT), + KEY(2, 4, KEY_ENTER), + + KEY(3, 0, KEY_NUMERIC_STAR), + KEY(3, 1, KEY_NUMERIC_0), + KEY(3, 2, KEY_NUMERIC_POUND), + KEY(3, 3, KEY_DOWN), + KEY(3, 4, KEY_RIGHT), + + KEY(4, 0, KEY_FN_F3), + KEY(4, 1, KEY_FN_F4), + KEY(4, 2, KEY_MUTE), + KEY(4, 3, KEY_HOME), + KEY(4, 4, KEY_BACK), + + KEY(5, 0, KEY_VOLUMEDOWN), + KEY(5, 1, KEY_VOLUMEUP), + KEY(5, 2, KEY_F1), + KEY(5, 3, KEY_F2), + KEY(5, 4, KEY_F3), +}; + +static const struct matrix_keymap_data keymap_data = { + .keymap = keymap, + .keymap_size = ARRAY_SIZE(keymap), +}; + +static struct matrix_keypad_platform_data keypad_config = { + .keymap_data = &keymap_data, + .num_row_gpios = 6, + .num_col_gpios = 5, + .debounce_ms = 0, /* minimum */ + .active_low = 0, /* pull up realization */ + .no_autorepeat = 0, +}; + static struct tnetv107x_device_info evm_device_info __initconst = { .serial_config = &serial_config, .mmc_config[1] = &mmc_config, /* controller 1 */ .nand_config[0] = &nand_config, /* chip select 0 */ + .keypad_config = &keypad_config, }; static __init void tnetv107x_evm_board_init(void) diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c index 054c303caead..01ba080433db 100644 --- a/arch/arm/mach-davinci/clock.c +++ b/arch/arm/mach-davinci/clock.c @@ -236,7 +236,7 @@ static int __init clk_disable_unused(void) if (!davinci_psc_is_clk_active(ck->gpsc, ck->lpsc)) continue; - pr_info("Clocks: disable unused %s\n", ck->name); + pr_debug("Clocks: disable unused %s\n", ck->name); davinci_psc_config(psc_domain(ck), ck->gpsc, ck->lpsc, (ck->flags & PSC_SWRSTDISABLE) ? @@ -287,6 +287,79 @@ static unsigned long clk_sysclk_recalc(struct clk *clk) return rate; } +int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate) +{ + unsigned v; + struct pll_data *pll; + unsigned long input; + unsigned ratio = 0; + + /* If this is the PLL base clock, wrong function to call */ + if (clk->pll_data) + return -EINVAL; + + /* There must be a parent... */ + if (WARN_ON(!clk->parent)) + return -EINVAL; + + /* ... the parent must be a PLL... */ + if (WARN_ON(!clk->parent->pll_data)) + return -EINVAL; + + /* ... and this clock must have a divider. */ + if (WARN_ON(!clk->div_reg)) + return -EINVAL; + + pll = clk->parent->pll_data; + + input = clk->parent->rate; + + /* If pre-PLL, source clock is before the multiplier and divider(s) */ + if (clk->flags & PRE_PLL) + input = pll->input_rate; + + if (input > rate) { + /* + * Can afford to provide an output little higher than requested + * only if maximum rate supported by hardware on this sysclk + * is known. + */ + if (clk->maxrate) { + ratio = DIV_ROUND_CLOSEST(input, rate); + if (input / ratio > clk->maxrate) + ratio = 0; + } + + if (ratio == 0) + ratio = DIV_ROUND_UP(input, rate); + + ratio--; + } + + if (ratio > PLLDIV_RATIO_MASK) + return -EINVAL; + + do { + v = __raw_readl(pll->base + PLLSTAT); + } while (v & PLLSTAT_GOSTAT); + + v = __raw_readl(pll->base + clk->div_reg); + v &= ~PLLDIV_RATIO_MASK; + v |= ratio | PLLDIV_EN; + __raw_writel(v, pll->base + clk->div_reg); + + v = __raw_readl(pll->base + PLLCMD); + v |= PLLCMD_GOSET; + __raw_writel(v, pll->base + PLLCMD); + + do { + v = __raw_readl(pll->base + PLLSTAT); + } while (v & PLLSTAT_GOSTAT); + + return 0; +} +EXPORT_SYMBOL(davinci_set_sysclk_rate); + static unsigned long clk_leafclk_recalc(struct clk *clk) { if (WARN_ON(!clk->parent)) diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h index 01e36483ac3d..11099980b58b 100644 --- a/arch/arm/mach-davinci/clock.h +++ b/arch/arm/mach-davinci/clock.h @@ -70,6 +70,9 @@ #include <linux/list.h> #include <asm/clkdev.h> +#define PLLSTAT_GOSTAT BIT(0) +#define PLLCMD_GOSET BIT(0) + struct pll_data { u32 phys_base; void __iomem *base; @@ -86,6 +89,7 @@ struct clk { struct module *owner; const char *name; unsigned long rate; + unsigned long maxrate; /* H/W supported max rate */ u8 usecount; u8 lpsc; u8 gpsc; @@ -118,6 +122,7 @@ struct clk { int davinci_clk_init(struct clk_lookup *clocks); int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv, unsigned int mult, unsigned int postdiv); +int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate); extern struct platform_device davinci_wdt_device; extern void davinci_watchdog_reset(struct platform_device *); diff --git a/arch/arm/mach-davinci/cpufreq.c b/arch/arm/mach-davinci/cpufreq.c index d3fa6de1e20f..343de73161fa 100644 --- a/arch/arm/mach-davinci/cpufreq.c +++ b/arch/arm/mach-davinci/cpufreq.c @@ -34,6 +34,8 @@ struct davinci_cpufreq { struct device *dev; struct clk *armclk; + struct clk *asyncclk; + unsigned long asyncrate; }; static struct davinci_cpufreq cpufreq; @@ -104,15 +106,27 @@ static int davinci_target(struct cpufreq_policy *policy, cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); /* if moving to higher frequency, up the voltage beforehand */ - if (pdata->set_voltage && freqs.new > freqs.old) - pdata->set_voltage(idx); + if (pdata->set_voltage && freqs.new > freqs.old) { + ret = pdata->set_voltage(idx); + if (ret) + goto out; + } ret = clk_set_rate(armclk, idx); + if (ret) + goto out; + + if (cpufreq.asyncclk) { + ret = clk_set_rate(cpufreq.asyncclk, cpufreq.asyncrate); + if (ret) + goto out; + } /* if moving to lower freq, lower the voltage after lowering freq */ if (pdata->set_voltage && freqs.new < freqs.old) pdata->set_voltage(idx); +out: cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); return ret; @@ -185,6 +199,7 @@ static struct cpufreq_driver davinci_driver = { static int __init davinci_cpufreq_probe(struct platform_device *pdev) { struct davinci_cpufreq_config *pdata = pdev->dev.platform_data; + struct clk *asyncclk; if (!pdata) return -EINVAL; @@ -199,6 +214,12 @@ static int __init davinci_cpufreq_probe(struct platform_device *pdev) return PTR_ERR(cpufreq.armclk); } + asyncclk = clk_get(cpufreq.dev, "async"); + if (!IS_ERR(asyncclk)) { + cpufreq.asyncclk = asyncclk; + cpufreq.asyncrate = clk_get_rate(asyncclk); + } + return cpufreq_register_driver(&davinci_driver); } @@ -206,6 +227,9 @@ static int __exit davinci_cpufreq_remove(struct platform_device *pdev) { clk_put(cpufreq.armclk); + if (cpufreq.asyncclk) + clk_put(cpufreq.asyncclk); + return cpufreq_unregister_driver(&davinci_driver); } diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 68ed58a48252..63916b902760 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -86,6 +86,8 @@ static struct clk pll0_sysclk3 = { .parent = &pll0_clk, .flags = CLK_PLL, .div_reg = PLLDIV3, + .set_rate = davinci_set_sysclk_rate, + .maxrate = 100000000, }; static struct clk pll0_sysclk4 = { @@ -323,12 +325,19 @@ static struct clk lcdc_clk = { .gpsc = 1, }; -static struct clk mmcsd_clk = { - .name = "mmcsd", +static struct clk mmcsd0_clk = { + .name = "mmcsd0", .parent = &pll0_sysclk2, .lpsc = DA8XX_LPSC0_MMC_SD, }; +static struct clk mmcsd1_clk = { + .name = "mmcsd1", + .parent = &pll0_sysclk2, + .lpsc = DA850_LPSC1_MMC_SD1, + .gpsc = 1, +}; + static struct clk aemif_clk = { .name = "aemif", .parent = &pll0_sysclk3, @@ -375,7 +384,8 @@ static struct clk_lookup da850_clks[] = { CLK("davinci_emac.1", NULL, &emac_clk), CLK("davinci-mcasp.0", NULL, &mcasp_clk), CLK("da8xx_lcdc.0", NULL, &lcdc_clk), - CLK("davinci_mmc.0", NULL, &mmcsd_clk), + CLK("davinci_mmc.0", NULL, &mmcsd0_clk), + CLK("davinci_mmc.1", NULL, &mmcsd1_clk), CLK(NULL, "aemif", &aemif_clk), CLK(NULL, NULL, NULL), }; @@ -572,15 +582,9 @@ const short da850_cpgmac_pins[] __initdata = { DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER, DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3, DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK, - DA850_MDIO_D, - -1 -}; - -const short da850_rmii_pins[] __initdata = { - DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN, - DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1, - DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK, - DA850_MDIO_D, + DA850_MDIO_D, DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN, + DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1, DA850_RMII_RXER, + DA850_RMII_MHZ_50_CLK, -1 }; @@ -607,27 +611,19 @@ const short da850_mmcsd0_pins[] __initdata = { -1 }; -const short da850_nand_pins[] __initdata = { - DA850_EMA_D_7, DA850_EMA_D_6, DA850_EMA_D_5, DA850_EMA_D_4, - DA850_EMA_D_3, DA850_EMA_D_2, DA850_EMA_D_1, DA850_EMA_D_0, - DA850_EMA_A_1, DA850_EMA_A_2, DA850_NEMA_CS_3, DA850_NEMA_CS_4, - DA850_NEMA_WE, DA850_NEMA_OE, - -1 -}; - -const short da850_nor_pins[] __initdata = { +const short da850_emif25_pins[] __initdata = { DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2, - DA850_NEMA_WE, DA850_NEMA_OE, DA850_EMA_D_0, DA850_EMA_D_1, - DA850_EMA_D_2, DA850_EMA_D_3, DA850_EMA_D_4, DA850_EMA_D_5, - DA850_EMA_D_6, DA850_EMA_D_7, DA850_EMA_D_8, DA850_EMA_D_9, - DA850_EMA_D_10, DA850_EMA_D_11, DA850_EMA_D_12, DA850_EMA_D_13, - DA850_EMA_D_14, DA850_EMA_D_15, DA850_EMA_A_0, DA850_EMA_A_1, - DA850_EMA_A_2, DA850_EMA_A_3, DA850_EMA_A_4, DA850_EMA_A_5, - DA850_EMA_A_6, DA850_EMA_A_7, DA850_EMA_A_8, DA850_EMA_A_9, - DA850_EMA_A_10, DA850_EMA_A_11, DA850_EMA_A_12, DA850_EMA_A_13, - DA850_EMA_A_14, DA850_EMA_A_15, DA850_EMA_A_16, DA850_EMA_A_17, - DA850_EMA_A_18, DA850_EMA_A_19, DA850_EMA_A_20, DA850_EMA_A_21, - DA850_EMA_A_22, DA850_EMA_A_23, + DA850_NEMA_CS_3, DA850_NEMA_CS_4, DA850_NEMA_WE, DA850_NEMA_OE, + DA850_EMA_D_0, DA850_EMA_D_1, DA850_EMA_D_2, DA850_EMA_D_3, + DA850_EMA_D_4, DA850_EMA_D_5, DA850_EMA_D_6, DA850_EMA_D_7, + DA850_EMA_D_8, DA850_EMA_D_9, DA850_EMA_D_10, DA850_EMA_D_11, + DA850_EMA_D_12, DA850_EMA_D_13, DA850_EMA_D_14, DA850_EMA_D_15, + DA850_EMA_A_0, DA850_EMA_A_1, DA850_EMA_A_2, DA850_EMA_A_3, + DA850_EMA_A_4, DA850_EMA_A_5, DA850_EMA_A_6, DA850_EMA_A_7, + DA850_EMA_A_8, DA850_EMA_A_9, DA850_EMA_A_10, DA850_EMA_A_11, + DA850_EMA_A_12, DA850_EMA_A_13, DA850_EMA_A_14, DA850_EMA_A_15, + DA850_EMA_A_16, DA850_EMA_A_17, DA850_EMA_A_18, DA850_EMA_A_19, + DA850_EMA_A_20, DA850_EMA_A_21, DA850_EMA_A_22, DA850_EMA_A_23, -1 }; @@ -851,7 +847,7 @@ static const struct da850_opp da850_opp_300 = { .prediv = 1, .mult = 25, .postdiv = 2, - .cvdd_min = 1140000, + .cvdd_min = 1200000, .cvdd_max = 1320000, }; @@ -860,7 +856,7 @@ static const struct da850_opp da850_opp_200 = { .prediv = 1, .mult = 25, .postdiv = 3, - .cvdd_min = 1050000, + .cvdd_min = 1100000, .cvdd_max = 1160000, }; @@ -869,7 +865,7 @@ static const struct da850_opp da850_opp_96 = { .prediv = 1, .mult = 20, .postdiv = 5, - .cvdd_min = 950000, + .cvdd_min = 1000000, .cvdd_max = 1050000, }; @@ -929,10 +925,16 @@ static struct platform_device da850_cpufreq_device = { .dev = { .platform_data = &cpufreq_info, }, + .id = -1, }; -int __init da850_register_cpufreq(void) +int __init da850_register_cpufreq(char *async_clk) { + /* cpufreq driver can help keep an "async" clock constant */ + if (async_clk) + clk_add_alias("async", da850_cpufreq_device.name, + async_clk, NULL); + return platform_device_register(&da850_cpufreq_device); } @@ -983,7 +985,7 @@ static int da850_set_pll0rate(struct clk *clk, unsigned long index) return 0; } #else -int __init da850_register_cpufreq(void) +int __init da850_register_cpufreq(char *async_clk) { return 0; } diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c index 52bc7b1c6ca3..9eec63070e0c 100644 --- a/arch/arm/mach-davinci/devices-da8xx.c +++ b/arch/arm/mach-davinci/devices-da8xx.c @@ -24,6 +24,7 @@ #include "clock.h" #define DA8XX_TPCC_BASE 0x01c00000 +#define DA850_MMCSD1_BASE 0x01e1b000 #define DA850_TPCC1_BASE 0x01e30000 #define DA8XX_TPTC0_BASE 0x01c08000 #define DA8XX_TPTC1_BASE 0x01c08400 @@ -41,7 +42,6 @@ #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000 #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000 #define DA8XX_EMAC_RAM_OFFSET 0x0000 -#define DA8XX_MDIO_REG_OFFSET 0x4000 #define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K void __iomem *da8xx_syscfg0_base; @@ -351,7 +351,7 @@ int __init da8xx_register_watchdog(void) static struct resource da8xx_emac_resources[] = { { .start = DA8XX_EMAC_CPPI_PORT_BASE, - .end = DA8XX_EMAC_CPPI_PORT_BASE + 0x5000 - 1, + .end = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1, .flags = IORESOURCE_MEM, }, { @@ -380,7 +380,6 @@ struct emac_platform_data da8xx_emac_pdata = { .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET, .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET, .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET, - .mdio_reg_offset = DA8XX_MDIO_REG_OFFSET, .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE, .version = EMAC_VERSION_2, }; @@ -395,9 +394,34 @@ static struct platform_device da8xx_emac_device = { .resource = da8xx_emac_resources, }; +static struct resource da8xx_mdio_resources[] = { + { + .start = DA8XX_EMAC_MDIO_BASE, + .end = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device da8xx_mdio_device = { + .name = "davinci_mdio", + .id = 0, + .num_resources = ARRAY_SIZE(da8xx_mdio_resources), + .resource = da8xx_mdio_resources, +}; + int __init da8xx_register_emac(void) { - return platform_device_register(&da8xx_emac_device); + int ret; + + ret = platform_device_register(&da8xx_mdio_device); + if (ret < 0) + return ret; + ret = platform_device_register(&da8xx_emac_device); + if (ret < 0) + return ret; + ret = clk_add_alias(NULL, dev_name(&da8xx_mdio_device.dev), + NULL, &da8xx_emac_device.dev); + return ret; } static struct resource da830_mcasp1_resources[] = { @@ -566,6 +590,44 @@ int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config) return platform_device_register(&da8xx_mmcsd0_device); } +#ifdef CONFIG_ARCH_DAVINCI_DA850 +static struct resource da850_mmcsd1_resources[] = { + { /* registers */ + .start = DA850_MMCSD1_BASE, + .end = DA850_MMCSD1_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { /* interrupt */ + .start = IRQ_DA850_MMCSDINT0_1, + .end = IRQ_DA850_MMCSDINT0_1, + .flags = IORESOURCE_IRQ, + }, + { /* DMA RX */ + .start = EDMA_CTLR_CHAN(1, 28), + .end = EDMA_CTLR_CHAN(1, 28), + .flags = IORESOURCE_DMA, + }, + { /* DMA TX */ + .start = EDMA_CTLR_CHAN(1, 29), + .end = EDMA_CTLR_CHAN(1, 29), + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device da850_mmcsd1_device = { + .name = "davinci_mmc", + .id = 1, + .num_resources = ARRAY_SIZE(da850_mmcsd1_resources), + .resource = da850_mmcsd1_resources, +}; + +int __init da850_register_mmcsd1(struct davinci_mmc_config *config) +{ + da850_mmcsd1_device.dev.platform_data = config; + return platform_device_register(&da850_mmcsd1_device); +} +#endif + static struct resource da8xx_rtc_resources[] = { { .start = DA8XX_RTC_BASE, diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c index 2718a3a90dff..c9a86d8130d1 100644 --- a/arch/arm/mach-davinci/devices-tnetv107x.c +++ b/arch/arm/mach-davinci/devices-tnetv107x.c @@ -31,8 +31,10 @@ #define TNETV107X_TPTC0_BASE 0x01c10000 #define TNETV107X_TPTC1_BASE 0x01c10400 #define TNETV107X_WDOG_BASE 0x08086700 +#define TNETV107X_TSC_BASE 0x08088500 #define TNETV107X_SDIO0_BASE 0x08088700 #define TNETV107X_SDIO1_BASE 0x08088800 +#define TNETV107X_KEYPAD_BASE 0x08088a00 #define TNETV107X_ASYNC_EMIF_CNTRL_BASE 0x08200000 #define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE 0x30000000 #define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE 0x40000000 @@ -298,12 +300,55 @@ static int __init nand_init(int chipsel, struct davinci_nand_pdata *data) return platform_device_register(pdev); } +static struct resource keypad_resources[] = { + { + .start = TNETV107X_KEYPAD_BASE, + .end = TNETV107X_KEYPAD_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_TNETV107X_KEYPAD, + .flags = IORESOURCE_IRQ, + .name = "press", + }, + { + .start = IRQ_TNETV107X_KEYPAD_FREE, + .flags = IORESOURCE_IRQ, + .name = "release", + }, +}; + +static struct platform_device keypad_device = { + .name = "tnetv107x-keypad", + .num_resources = ARRAY_SIZE(keypad_resources), + .resource = keypad_resources, +}; + +static struct resource tsc_resources[] = { + { + .start = TNETV107X_TSC_BASE, + .end = TNETV107X_TSC_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_TNETV107X_TSC, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device tsc_device = { + .name = "tnetv107x-ts", + .num_resources = ARRAY_SIZE(tsc_resources), + .resource = tsc_resources, +}; + void __init tnetv107x_devices_init(struct tnetv107x_device_info *info) { int i; platform_device_register(&edma_device); platform_device_register(&tnetv107x_wdt_device); + platform_device_register(&tsc_device); if (info->serial_config) davinci_serial_init(info->serial_config); @@ -317,4 +362,9 @@ void __init tnetv107x_devices_init(struct tnetv107x_device_info *info) for (i = 0; i < 4; i++) if (info->nand_config[i]) nand_init(i, info->nand_config[i]); + + if (info->keypad_config) { + keypad_device.dev.platform_data = info->keypad_config; + platform_device_register(&keypad_device); + } } diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c index 8b7201e4c79c..22ebc64bc9d9 100644 --- a/arch/arm/mach-davinci/devices.c +++ b/arch/arm/mach-davinci/devices.c @@ -213,7 +213,7 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config) IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE + 0x7c); /* Configure pull down control */ - __raw_writel((__raw_readl(pupdctl1) & ~0x400), + __raw_writel((__raw_readl(pupdctl1) & ~0xfc0), pupdctl1); mmcsd1_resources[0].start = DM365_MMCSD1_BASE; @@ -295,6 +295,18 @@ static void davinci_init_wdt(void) /*-------------------------------------------------------------------------*/ +struct platform_device davinci_pcm_device = { + .name = "davinci-pcm-audio", + .id = -1, +}; + +static void davinci_init_pcm(void) +{ + platform_device_register(&davinci_pcm_device); +} + +/*-------------------------------------------------------------------------*/ + struct davinci_timer_instance davinci_timer_instance[2] = { { .base = DAVINCI_TIMER0_BASE, @@ -315,6 +327,7 @@ static int __init davinci_init_devices(void) /* please keep these calls, and their implementations above, * in alphabetical order so they're easier to sort through. */ + davinci_init_pcm(); davinci_init_wdt(); return 0; diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index 7781e35daec3..a12065e87266 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -691,7 +691,6 @@ static struct emac_platform_data dm365_emac_pdata = { .ctrl_reg_offset = DM365_EMAC_CNTRL_OFFSET, .ctrl_mod_reg_offset = DM365_EMAC_CNTRL_MOD_OFFSET, .ctrl_ram_offset = DM365_EMAC_CNTRL_RAM_OFFSET, - .mdio_reg_offset = DM365_EMAC_MDIO_OFFSET, .ctrl_ram_size = DM365_EMAC_CNTRL_RAM_SIZE, .version = EMAC_VERSION_2, }; @@ -699,7 +698,7 @@ static struct emac_platform_data dm365_emac_pdata = { static struct resource dm365_emac_resources[] = { { .start = DM365_EMAC_BASE, - .end = DM365_EMAC_BASE + 0x47ff, + .end = DM365_EMAC_BASE + SZ_16K - 1, .flags = IORESOURCE_MEM, }, { @@ -734,6 +733,21 @@ static struct platform_device dm365_emac_device = { .resource = dm365_emac_resources, }; +static struct resource dm365_mdio_resources[] = { + { + .start = DM365_EMAC_MDIO_BASE, + .end = DM365_EMAC_MDIO_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device dm365_mdio_device = { + .name = "davinci_mdio", + .id = 0, + .num_resources = ARRAY_SIZE(dm365_mdio_resources), + .resource = dm365_mdio_resources, +}; + static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = { [IRQ_VDINT0] = 2, [IRQ_VDINT1] = 6, @@ -1219,7 +1233,12 @@ static int __init dm365_init_devices(void) davinci_cfg_reg(DM365_INT_EDMA_CC); platform_device_register(&dm365_edma_device); + + platform_device_register(&dm365_mdio_device); platform_device_register(&dm365_emac_device); + clk_add_alias(NULL, dev_name(&dm365_mdio_device.dev), + NULL, &dm365_emac_device.dev); + /* Add isif clock alias */ clk_add_alias("master", dm365_isif_dev.name, "vpss_master", NULL); platform_device_register(&dm365_vpss_device); diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index 5e5b0a7831fb..0608dd776a16 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -322,7 +322,6 @@ static struct emac_platform_data dm644x_emac_pdata = { .ctrl_reg_offset = DM644X_EMAC_CNTRL_OFFSET, .ctrl_mod_reg_offset = DM644X_EMAC_CNTRL_MOD_OFFSET, .ctrl_ram_offset = DM644X_EMAC_CNTRL_RAM_OFFSET, - .mdio_reg_offset = DM644X_EMAC_MDIO_OFFSET, .ctrl_ram_size = DM644X_EMAC_CNTRL_RAM_SIZE, .version = EMAC_VERSION_1, }; @@ -330,7 +329,7 @@ static struct emac_platform_data dm644x_emac_pdata = { static struct resource dm644x_emac_resources[] = { { .start = DM644X_EMAC_BASE, - .end = DM644X_EMAC_BASE + 0x47ff, + .end = DM644X_EMAC_BASE + SZ_16K - 1, .flags = IORESOURCE_MEM, }, { @@ -350,6 +349,21 @@ static struct platform_device dm644x_emac_device = { .resource = dm644x_emac_resources, }; +static struct resource dm644x_mdio_resources[] = { + { + .start = DM644X_EMAC_MDIO_BASE, + .end = DM644X_EMAC_MDIO_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device dm644x_mdio_device = { + .name = "davinci_mdio", + .id = 0, + .num_resources = ARRAY_SIZE(dm644x_mdio_resources), + .resource = dm644x_mdio_resources, +}; + /* * Device specific mux setup * @@ -776,7 +790,12 @@ static int __init dm644x_init_devices(void) clk_add_alias("master", dm644x_ccdc_dev.name, "vpss_master", NULL); clk_add_alias("slave", dm644x_ccdc_dev.name, "vpss_slave", NULL); platform_device_register(&dm644x_edma_device); + + platform_device_register(&dm644x_mdio_device); platform_device_register(&dm644x_emac_device); + clk_add_alias(NULL, dev_name(&dm644x_mdio_device.dev), + NULL, &dm644x_emac_device.dev); + platform_device_register(&dm644x_vpss_device); platform_device_register(&dm644x_ccdc_dev); platform_device_register(&vpfe_capture_dev); diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index 26e8a9c7f50b..1e0f809644bb 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c @@ -358,7 +358,6 @@ static struct emac_platform_data dm646x_emac_pdata = { .ctrl_reg_offset = DM646X_EMAC_CNTRL_OFFSET, .ctrl_mod_reg_offset = DM646X_EMAC_CNTRL_MOD_OFFSET, .ctrl_ram_offset = DM646X_EMAC_CNTRL_RAM_OFFSET, - .mdio_reg_offset = DM646X_EMAC_MDIO_OFFSET, .ctrl_ram_size = DM646X_EMAC_CNTRL_RAM_SIZE, .version = EMAC_VERSION_2, }; @@ -366,7 +365,7 @@ static struct emac_platform_data dm646x_emac_pdata = { static struct resource dm646x_emac_resources[] = { { .start = DM646X_EMAC_BASE, - .end = DM646X_EMAC_BASE + 0x47ff, + .end = DM646X_EMAC_BASE + SZ_16K - 1, .flags = IORESOURCE_MEM, }, { @@ -401,6 +400,21 @@ static struct platform_device dm646x_emac_device = { .resource = dm646x_emac_resources, }; +static struct resource dm646x_mdio_resources[] = { + { + .start = DM646X_EMAC_MDIO_BASE, + .end = DM646X_EMAC_MDIO_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device dm646x_mdio_device = { + .name = "davinci_mdio", + .id = 0, + .num_resources = ARRAY_SIZE(dm646x_mdio_resources), + .resource = dm646x_mdio_resources, +}; + /* * Device specific mux setup * @@ -896,7 +910,11 @@ static int __init dm646x_init_devices(void) if (!cpu_is_davinci_dm646x()) return 0; + platform_device_register(&dm646x_mdio_device); platform_device_register(&dm646x_emac_device); + clk_add_alias(NULL, dev_name(&dm646x_mdio_device.dev), + NULL, &dm646x_emac_device.dev); + return 0; } postcore_initcall(dm646x_init_devices); diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c index 2ede598b77dd..6b9669869c46 100644 --- a/arch/arm/mach-davinci/dma.c +++ b/arch/arm/mach-davinci/dma.c @@ -354,10 +354,12 @@ static int irq2ctlr(int irq) static irqreturn_t dma_irq_handler(int irq, void *data) { int i; - unsigned ctlr; + int ctlr; unsigned int cnt = 0; ctlr = irq2ctlr(irq); + if (ctlr < 0) + return IRQ_NONE; dev_dbg(data, "dma_irq_handler\n"); @@ -408,10 +410,12 @@ static irqreturn_t dma_irq_handler(int irq, void *data) static irqreturn_t dma_ccerr_handler(int irq, void *data) { int i; - unsigned ctlr; + int ctlr; unsigned int cnt = 0; ctlr = irq2ctlr(irq); + if (ctlr < 0) + return IRQ_NONE; dev_dbg(data, "dma_ccerr_handler\n"); diff --git a/arch/arm/mach-davinci/include/mach/aemif.h b/arch/arm/mach-davinci/include/mach/aemif.h new file mode 100644 index 000000000000..05b293443097 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/aemif.h @@ -0,0 +1,36 @@ +/* + * TI DaVinci AEMIF support + * + * Copyright 2010 (C) Texas Instruments, Inc. http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ +#ifndef _MACH_DAVINCI_AEMIF_H +#define _MACH_DAVINCI_AEMIF_H + +#define NRCSR_OFFSET 0x00 +#define AWCCR_OFFSET 0x04 +#define A1CR_OFFSET 0x10 + +#define ACR_ASIZE_MASK 0x3 +#define ACR_EW_MASK BIT(30) +#define ACR_SS_MASK BIT(31) + +/* All timings in nanoseconds */ +struct davinci_aemif_timing { + u8 wsetup; + u8 wstrobe; + u8 whold; + + u8 rsetup; + u8 rstrobe; + u8 rhold; + + u8 ta; +}; + +int davinci_aemif_setup_timing(struct davinci_aemif_timing *t, + void __iomem *base, unsigned cs); +#endif diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index 3c07059f526e..4247b3f53b33 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -76,9 +76,10 @@ int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata); int da8xx_register_emac(void); int da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata); int da8xx_register_mmcsd0(struct davinci_mmc_config *config); +int da850_register_mmcsd1(struct davinci_mmc_config *config); void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata); int da8xx_register_rtc(void); -int da850_register_cpufreq(void); +int da850_register_cpufreq(char *async_clk); int da8xx_register_cpuidle(void); void __iomem * __init da8xx_get_mem_ctlr(void); int da850_register_pm(struct platform_device *pdev); @@ -121,11 +122,9 @@ extern const short da850_uart2_pins[]; extern const short da850_i2c0_pins[]; extern const short da850_i2c1_pins[]; extern const short da850_cpgmac_pins[]; -extern const short da850_rmii_pins[]; extern const short da850_mcasp_pins[]; extern const short da850_lcdcntl_pins[]; extern const short da850_mmcsd0_pins[]; -extern const short da850_nand_pins[]; -extern const short da850_nor_pins[]; +extern const short da850_emif25_pins[]; #endif /* __ASM_ARCH_DAVINCI_DA8XX_H */ diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-davinci/include/mach/dm365.h index ea5df3b49ec4..2563bf4e93a1 100644 --- a/arch/arm/mach-davinci/include/mach/dm365.h +++ b/arch/arm/mach-davinci/include/mach/dm365.h @@ -21,10 +21,10 @@ #include <media/davinci/vpfe_capture.h> #define DM365_EMAC_BASE (0x01D07000) +#define DM365_EMAC_MDIO_BASE (DM365_EMAC_BASE + 0x4000) #define DM365_EMAC_CNTRL_OFFSET (0x0000) #define DM365_EMAC_CNTRL_MOD_OFFSET (0x3000) #define DM365_EMAC_CNTRL_RAM_OFFSET (0x1000) -#define DM365_EMAC_MDIO_OFFSET (0x4000) #define DM365_EMAC_CNTRL_RAM_SIZE (0x2000) /* Base of key scan register bank */ diff --git a/arch/arm/mach-davinci/include/mach/dm644x.h b/arch/arm/mach-davinci/include/mach/dm644x.h index 6fca568a0fd2..5a1b26d4e68b 100644 --- a/arch/arm/mach-davinci/include/mach/dm644x.h +++ b/arch/arm/mach-davinci/include/mach/dm644x.h @@ -28,10 +28,10 @@ #include <media/davinci/vpfe_capture.h> #define DM644X_EMAC_BASE (0x01C80000) +#define DM644X_EMAC_MDIO_BASE (DM644X_EMAC_BASE + 0x4000) #define DM644X_EMAC_CNTRL_OFFSET (0x0000) #define DM644X_EMAC_CNTRL_MOD_OFFSET (0x1000) #define DM644X_EMAC_CNTRL_RAM_OFFSET (0x2000) -#define DM644X_EMAC_MDIO_OFFSET (0x4000) #define DM644X_EMAC_CNTRL_RAM_SIZE (0x2000) #define DM644X_ASYNC_EMIF_CONTROL_BASE 0x01E00000 diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h index 0a27ee9a70e1..7a27f3f13913 100644 --- a/arch/arm/mach-davinci/include/mach/dm646x.h +++ b/arch/arm/mach-davinci/include/mach/dm646x.h @@ -19,10 +19,10 @@ #include <linux/davinci_emac.h> #define DM646X_EMAC_BASE (0x01C80000) +#define DM646X_EMAC_MDIO_BASE (DM646X_EMAC_BASE + 0x4000) #define DM646X_EMAC_CNTRL_OFFSET (0x0000) #define DM646X_EMAC_CNTRL_MOD_OFFSET (0x1000) #define DM646X_EMAC_CNTRL_RAM_OFFSET (0x2000) -#define DM646X_EMAC_MDIO_OFFSET (0x4000) #define DM646X_EMAC_CNTRL_RAM_SIZE (0x2000) #define DM646X_ASYNC_EMIF_CONTROL_BASE 0x20008000 diff --git a/arch/arm/mach-davinci/include/mach/nand.h b/arch/arm/mach-davinci/include/mach/nand.h index b2ad8090bd10..025151049f05 100644 --- a/arch/arm/mach-davinci/include/mach/nand.h +++ b/arch/arm/mach-davinci/include/mach/nand.h @@ -30,9 +30,6 @@ #include <linux/mtd/nand.h> -#define NRCSR_OFFSET 0x00 -#define AWCCR_OFFSET 0x04 -#define A1CR_OFFSET 0x10 #define NANDFCR_OFFSET 0x60 #define NANDFSR_OFFSET 0x64 #define NANDF1ECC_OFFSET 0x70 @@ -83,6 +80,9 @@ struct davinci_nand_pdata { /* platform_data */ /* Main and mirror bbt descriptor overrides */ struct nand_bbt_descr *bbt_td; struct nand_bbt_descr *bbt_md; + + /* Access timings */ + struct davinci_aemif_timing *timing; }; #endif /* __ARCH_ARM_DAVINCI_NAND_H */ diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h index 983da6e4554c..62b0858f68ca 100644 --- a/arch/arm/mach-davinci/include/mach/psc.h +++ b/arch/arm/mach-davinci/include/mach/psc.h @@ -172,6 +172,7 @@ #define DA8XX_LPSC1_UART2 13 #define DA8XX_LPSC1_LCDC 16 #define DA8XX_LPSC1_PWM 17 +#define DA850_LPSC1_MMC_SD1 18 #define DA8XX_LPSC1_ECAP 20 #define DA830_LPSC1_EQEP 21 #define DA850_LPSC1_TPTC2 21 diff --git a/arch/arm/mach-davinci/include/mach/tnetv107x.h b/arch/arm/mach-davinci/include/mach/tnetv107x.h index c72064733123..5a681d880dcb 100644 --- a/arch/arm/mach-davinci/include/mach/tnetv107x.h +++ b/arch/arm/mach-davinci/include/mach/tnetv107x.h @@ -33,6 +33,8 @@ #ifndef __ASSEMBLY__ #include <linux/serial_8250.h> +#include <linux/input/matrix_keypad.h> + #include <mach/mmc.h> #include <mach/nand.h> #include <mach/serial.h> @@ -41,6 +43,7 @@ struct tnetv107x_device_info { struct davinci_uart_config *serial_config; struct davinci_mmc_config *mmc_config[2]; /* 2 controllers */ struct davinci_nand_pdata *nand_config[4]; /* 4 chipsels */ + struct matrix_keypad_platform_data *keypad_config; }; extern struct platform_device tnetv107x_wdt_device; diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h index 15a6192ad6eb..47723e8d75a4 100644 --- a/arch/arm/mach-davinci/include/mach/uncompress.h +++ b/arch/arm/mach-davinci/include/mach/uncompress.h @@ -88,6 +88,8 @@ static inline void __arch_decomp_setup(unsigned long arch_id) /* DA8xx boards */ DEBUG_LL_DA8XX(davinci_da830_evm, 2); DEBUG_LL_DA8XX(davinci_da850_evm, 2); + DEBUG_LL_DA8XX(mityomapl138, 1); + DEBUG_LL_DA8XX(omapl138_hawkboard, 2); /* TNETV107x boards */ DEBUG_LL_TNETV107X(tnetv107x, 1); diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c index 864e60482c53..daeae06430b9 100644 --- a/arch/arm/mach-davinci/tnetv107x.c +++ b/arch/arm/mach-davinci/tnetv107x.c @@ -104,7 +104,7 @@ static u32 pll_ext_freq[] = { }; /* PSC control registers */ -static u32 psc_regs[] __initconst = { TNETV107X_PSC_BASE }; +static u32 psc_regs[] = { TNETV107X_PSC_BASE }; /* Host map for interrupt controller */ static u32 intc_host_map[] = { 0x01010000, 0x01010101, -1 }; @@ -581,7 +581,14 @@ static struct davinci_id ids[] = { .part_no = 0xb8a1, .manufacturer = 0x017, .cpu_id = DAVINCI_CPU_ID_TNETV107X, - .name = "tnetv107x rev1.0", + .name = "tnetv107x rev 1.0", + }, + { + .variant = 0x1, + .part_no = 0xb8a1, + .manufacturer = 0x017, + .cpu_id = DAVINCI_CPU_ID_TNETV107X, + .name = "tnetv107x rev 1.1/1.2", }, }; diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c index 4566bd1c8660..ef06c66a6f16 100644 --- a/arch/arm/mach-ep93xx/clock.c +++ b/arch/arm/mach-ep93xx/clock.c @@ -358,8 +358,7 @@ static int calc_clk_div(struct clk *clk, unsigned long rate, int i, found = 0, __div = 0, __pdiv = 0; /* Don't exceed the maximum rate */ - max_rate = max(max(clk_pll1.rate / 4, clk_pll2.rate / 4), - clk_xtali.rate / 4); + max_rate = max3(clk_pll1.rate / 4, clk_pll2.rate / 4, clk_xtali.rate / 4); rate = min(rate, max_rate); /* diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index 4cb55d3902ff..ffdf87be2958 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c @@ -776,9 +776,15 @@ static struct platform_device ep93xx_i2s_device = { .resource = ep93xx_i2s_resource, }; +static struct platform_device ep93xx_pcm_device = { + .name = "ep93xx-pcm-audio", + .id = -1, +}; + void __init ep93xx_register_i2s(void) { platform_device_register(&ep93xx_i2s_device); + platform_device_register(&ep93xx_pcm_device); } #define EP93XX_SYSCON_DEVCFG_I2S_MASK (EP93XX_SYSCON_DEVCFG_I2SONSSP | \ @@ -826,6 +832,40 @@ void ep93xx_i2s_release(void) } EXPORT_SYMBOL(ep93xx_i2s_release); +/************************************************************************* + * EP93xx AC97 audio peripheral handling + *************************************************************************/ +static struct resource ep93xx_ac97_resources[] = { + { + .start = EP93XX_AAC_PHYS_BASE, + .end = EP93XX_AAC_PHYS_BASE + 0xb0 - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_EP93XX_AACINTR, + .end = IRQ_EP93XX_AACINTR, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device ep93xx_ac97_device = { + .name = "ep93xx-ac97", + .id = -1, + .num_resources = ARRAY_SIZE(ep93xx_ac97_resources), + .resource = ep93xx_ac97_resources, +}; + +void __init ep93xx_register_ac97(void) +{ + /* + * Make sure that the AC97 pins are not used by I2S. + */ + ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2SONAC97); + + platform_device_register(&ep93xx_ac97_device); + platform_device_register(&ep93xx_pcm_device); +} + extern void ep93xx_gpio_init(void); void __init ep93xx_init_devices(void) diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h index c54b3e56ba63..9ac4d1055097 100644 --- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h +++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h @@ -105,6 +105,7 @@ #define EP93XX_GPIO_B_INT_STATUS EP93XX_GPIO_REG(0xbc) #define EP93XX_GPIO_EEDRIVE EP93XX_GPIO_REG(0xc8) +#define EP93XX_AAC_PHYS_BASE EP93XX_APB_PHYS(0x00080000) #define EP93XX_AAC_BASE EP93XX_APB_IOMEM(0x00080000) #define EP93XX_SPI_PHYS_BASE EP93XX_APB_PHYS(0x000a0000) diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h index 3330b36d79e6..50660455b1d8 100644 --- a/arch/arm/mach-ep93xx/include/mach/platform.h +++ b/arch/arm/mach-ep93xx/include/mach/platform.h @@ -61,6 +61,7 @@ void ep93xx_keypad_release_gpio(struct platform_device *pdev); void ep93xx_register_i2s(void); int ep93xx_i2s_acquire(unsigned i2s_pins, unsigned i2s_config); void ep93xx_i2s_release(void); +void ep93xx_register_ac97(void); void ep93xx_init_devices(void); extern struct sys_timer ep93xx_timer; diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c index f22ce8db7947..d96dc1c5da20 100644 --- a/arch/arm/mach-ep93xx/simone.c +++ b/arch/arm/mach-ep93xx/simone.c @@ -61,6 +61,7 @@ static void __init simone_init_machine(void) ep93xx_register_fb(&simone_fb_info); ep93xx_register_i2c(&simone_i2c_gpio_data, simone_i2c_board_info, ARRAY_SIZE(simone_i2c_board_info)); + ep93xx_register_ac97(); } MACHINE_START(SIM_ONE, "Simplemachines Sim.One Board") diff --git a/arch/arm/mach-imx/include/mach/dma-v1.h b/arch/arm/mach-imx/include/mach/dma-v1.h index 287431cc13e5..ac6fd713828a 100644 --- a/arch/arm/mach-imx/include/mach/dma-v1.h +++ b/arch/arm/mach-imx/include/mach/dma-v1.h @@ -27,6 +27,8 @@ #define imx_has_dma_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27()) +#include <mach/dma.h> + #define IMX_DMA_CHANNELS 16 #define DMA_MODE_READ 0 @@ -96,12 +98,6 @@ int imx_dma_request(int channel, const char *name); void imx_dma_free(int channel); -enum imx_dma_prio { - DMA_PRIO_HIGH = 0, - DMA_PRIO_MEDIUM = 1, - DMA_PRIO_LOW = 2 -}; - int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio); #endif /* __MACH_DMA_V1_H__ */ diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index 1c82d4290dad..51ff23b72d3a 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -903,10 +903,16 @@ static struct platform_device kirkwood_i2s_device = { }, }; +static struct platform_device kirkwood_pcm_device = { + .name = "kirkwood-pcm-audio", + .id = -1, +}; + void __init kirkwood_audio_init(void) { kirkwood_clk_ctrl |= CGC_AUDIO; platform_device_register(&kirkwood_i2s_device); + platform_device_register(&kirkwood_pcm_device); } /***************************************************************************** diff --git a/arch/arm/mach-kirkwood/netspace_v2-setup.c b/arch/arm/mach-kirkwood/netspace_v2-setup.c index 5e286441b8f4..5ea66f1f4178 100644 --- a/arch/arm/mach-kirkwood/netspace_v2-setup.c +++ b/arch/arm/mach-kirkwood/netspace_v2-setup.c @@ -30,6 +30,7 @@ #include <linux/gpio.h> #include <linux/gpio_keys.h> #include <linux/leds.h> +#include <linux/gpio-fan.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <mach/kirkwood.h> @@ -137,6 +138,46 @@ static struct platform_device netspace_v2_leds = { }; /***************************************************************************** + * GPIO fan + ****************************************************************************/ + +/* Designed for fan 40x40x16: ADDA AD0412LB-D50 6000rpm@12v */ +static struct gpio_fan_speed netspace_max_v2_fan_speed[] = { + { 0, 0 }, + { 1500, 15 }, + { 1700, 14 }, + { 1800, 13 }, + { 2100, 12 }, + { 3100, 11 }, + { 3300, 10 }, + { 4300, 9 }, + { 5500, 8 }, +}; + +static unsigned netspace_max_v2_fan_ctrl[] = { 22, 7, 33, 23 }; + +static struct gpio_fan_alarm netspace_max_v2_fan_alarm = { + .gpio = 25, + .active_low = 1, +}; + +static struct gpio_fan_platform_data netspace_max_v2_fan_data = { + .num_ctrl = ARRAY_SIZE(netspace_max_v2_fan_ctrl), + .ctrl = netspace_max_v2_fan_ctrl, + .alarm = &netspace_max_v2_fan_alarm, + .num_speed = ARRAY_SIZE(netspace_max_v2_fan_speed), + .speed = netspace_max_v2_fan_speed, +}; + +static struct platform_device netspace_max_v2_gpio_fan = { + .name = "gpio-fan", + .id = -1, + .dev = { + .platform_data = &netspace_max_v2_fan_data, + }, +}; + +/***************************************************************************** * General Setup ****************************************************************************/ @@ -205,6 +246,8 @@ static void __init netspace_v2_init(void) platform_device_register(&netspace_v2_leds); platform_device_register(&netspace_v2_gpio_leds); platform_device_register(&netspace_v2_gpio_buttons); + if (machine_is_netspace_max_v2()) + platform_device_register(&netspace_max_v2_gpio_fan); if (gpio_request(NETSPACE_V2_GPIO_POWER_OFF, "power-off") == 0 && gpio_direction_output(NETSPACE_V2_GPIO_POWER_OFF, 0) == 0) diff --git a/arch/arm/mach-msm/last_radio_log.c b/arch/arm/mach-msm/last_radio_log.c index b64ba5a98686..1e243f46a969 100644 --- a/arch/arm/mach-msm/last_radio_log.c +++ b/arch/arm/mach-msm/last_radio_log.c @@ -48,7 +48,8 @@ static ssize_t last_radio_log_read(struct file *file, char __user *buf, } static struct file_operations last_radio_log_fops = { - .read = last_radio_log_read + .read = last_radio_log_read, + .llseek = default_llseek, }; void msm_init_last_radio_log(struct module *owner) diff --git a/arch/arm/mach-msm/smd_debug.c b/arch/arm/mach-msm/smd_debug.c index 3b2dd717b788..f91c3b7bc655 100644 --- a/arch/arm/mach-msm/smd_debug.c +++ b/arch/arm/mach-msm/smd_debug.c @@ -212,6 +212,7 @@ static int debug_open(struct inode *inode, struct file *file) static const struct file_operations debug_ops = { .read = debug_read, .open = debug_open, + .llseek = default_llseek, }; static void debug_create(const char *name, mode_t mode, diff --git a/arch/arm/mach-mx3/mach-cpuimx35.c b/arch/arm/mach-mx3/mach-cpuimx35.c index 8533bf04284a..9fde873f5889 100644 --- a/arch/arm/mach-mx3/mach-cpuimx35.c +++ b/arch/arm/mach-mx3/mach-cpuimx35.c @@ -131,6 +131,7 @@ static struct mxc_usbh_platform_data __maybe_unused usbh1_pdata = { static struct fsl_usb2_platform_data otg_device_pdata = { .operating_mode = FSL_USB2_DR_DEVICE, .phy_mode = FSL_USB2_PHY_UTMI, + .workaround = FLS_USB2_WORKAROUND_ENGCM09152, }; static int otg_mode_host; diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig index 3b02d3b944af..5f6496375404 100644 --- a/arch/arm/mach-omap1/Kconfig +++ b/arch/arm/mach-omap1/Kconfig @@ -128,7 +128,7 @@ config MACH_OMAP_PALMTT help Support for the Palm Tungsten|T PDA. To boot the kernel, you'll need a PalmOS compatible bootloader (Garux); check out - http://www.hackndev.com/palm/tt/ for more information. + http://garux.sourceforge.net/ for more information. Say Y here if you have this PDA model, say N otherwise. config MACH_SX1 diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile index facfaeb1ae5c..9a304d854e33 100644 --- a/arch/arm/mach-omap1/Makefile +++ b/arch/arm/mach-omap1/Makefile @@ -12,7 +12,7 @@ obj-$(CONFIG_OMAP_MPU_TIMER) += time.o obj-$(CONFIG_OMAP_32K_TIMER) += timer32k.o # Power Management -obj-$(CONFIG_PM) += pm.o sleep.o +obj-$(CONFIG_PM) += pm.o sleep.o pm_bus.o # DSP obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c index 73c86392fcd3..1d4163b9f0b7 100644 --- a/arch/arm/mach-omap1/board-ams-delta.c +++ b/arch/arm/mach-omap1/board-ams-delta.c @@ -16,9 +16,12 @@ #include <linux/init.h> #include <linux/input.h> #include <linux/interrupt.h> +#include <linux/leds.h> #include <linux/platform_device.h> #include <linux/serial_8250.h> +#include <media/soc_camera.h> + #include <asm/serial.h> #include <mach/hardware.h> #include <asm/mach-types.h> @@ -32,6 +35,7 @@ #include <plat/usb.h> #include <plat/board.h> #include <plat/common.h> +#include <mach/camera.h> #include <mach/ams-delta-fiq.h> @@ -213,10 +217,56 @@ static struct platform_device ams_delta_led_device = { .id = -1 }; +static struct i2c_board_info ams_delta_camera_board_info[] = { + { + I2C_BOARD_INFO("ov6650", 0x60), + }, +}; + +#ifdef CONFIG_LEDS_TRIGGERS +DEFINE_LED_TRIGGER(ams_delta_camera_led_trigger); + +static int ams_delta_camera_power(struct device *dev, int power) +{ + /* + * turn on camera LED + */ + if (power) + led_trigger_event(ams_delta_camera_led_trigger, LED_FULL); + else + led_trigger_event(ams_delta_camera_led_trigger, LED_OFF); + return 0; +} +#else +#define ams_delta_camera_power NULL +#endif + +static struct soc_camera_link __initdata ams_delta_iclink = { + .bus_id = 0, /* OMAP1 SoC camera bus */ + .i2c_adapter_id = 1, + .board_info = &ams_delta_camera_board_info[0], + .module_name = "ov6650", + .power = ams_delta_camera_power, +}; + +static struct platform_device ams_delta_camera_device = { + .name = "soc-camera-pdrv", + .id = 0, + .dev = { + .platform_data = &ams_delta_iclink, + }, +}; + +static struct omap1_cam_platform_data ams_delta_camera_platform_data = { + .camexclk_khz = 12000, /* default 12MHz clock, no extra DPLL */ + .lclk_khz_max = 1334, /* results in 5fps CIF, 10fps QCIF */ +}; + static struct platform_device *ams_delta_devices[] __initdata = { &ams_delta_kp_device, &ams_delta_lcd_device, &ams_delta_led_device, + &ams_delta_camera_device, }; static void __init ams_delta_init(void) @@ -225,6 +275,20 @@ static void __init ams_delta_init(void) omap_cfg_reg(UART1_TX); omap_cfg_reg(UART1_RTS); + /* parallel camera interface */ + omap_cfg_reg(H19_1610_CAM_EXCLK); + omap_cfg_reg(J15_1610_CAM_LCLK); + omap_cfg_reg(L18_1610_CAM_VS); + omap_cfg_reg(L15_1610_CAM_HS); + omap_cfg_reg(L19_1610_CAM_D0); + omap_cfg_reg(K14_1610_CAM_D1); + omap_cfg_reg(K15_1610_CAM_D2); + omap_cfg_reg(K19_1610_CAM_D3); + omap_cfg_reg(K18_1610_CAM_D4); + omap_cfg_reg(J14_1610_CAM_D5); + omap_cfg_reg(J19_1610_CAM_D6); + omap_cfg_reg(J18_1610_CAM_D7); + iotable_init(ams_delta_io_desc, ARRAY_SIZE(ams_delta_io_desc)); omap_board_config = ams_delta_config; @@ -236,6 +300,11 @@ static void __init ams_delta_init(void) ams_delta_latch2_write(~0, 0); omap1_usb_init(&ams_delta_usb_config); + omap1_set_camera_info(&ams_delta_camera_platform_data); +#ifdef CONFIG_LEDS_TRIGGERS + led_trigger_register_simple("ams_delta_camera", + &ams_delta_camera_led_trigger); +#endif platform_add_devices(ams_delta_devices, ARRAY_SIZE(ams_delta_devices)); #ifdef CONFIG_AMS_DELTA_FIQ diff --git a/arch/arm/mach-omap1/board-h2-mmc.c b/arch/arm/mach-omap1/board-h2-mmc.c index b30c4990744d..f2fc43d8382b 100644 --- a/arch/arm/mach-omap1/board-h2-mmc.c +++ b/arch/arm/mach-omap1/board-h2-mmc.c @@ -58,8 +58,7 @@ static struct omap_mmc_platform_data mmc1_data = { .dma_mask = 0xffffffff, .slots[0] = { .set_power = mmc_set_power, - .ocr_mask = MMC_VDD_28_29 | MMC_VDD_30_31 | - MMC_VDD_32_33 | MMC_VDD_33_34, + .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, .name = "mmcblk", }, }; diff --git a/arch/arm/mach-omap1/board-h3-mmc.c b/arch/arm/mach-omap1/board-h3-mmc.c index 54b0f063e263..2098525e7cc5 100644 --- a/arch/arm/mach-omap1/board-h3-mmc.c +++ b/arch/arm/mach-omap1/board-h3-mmc.c @@ -40,8 +40,7 @@ static struct omap_mmc_platform_data mmc1_data = { .dma_mask = 0xffffffff, .slots[0] = { .set_power = mmc_set_power, - .ocr_mask = MMC_VDD_28_29 | MMC_VDD_30_31 | - MMC_VDD_32_33 | MMC_VDD_33_34, + .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, .name = "mmcblk", }, }; diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c index 86afb2952225..071af3e47789 100644 --- a/arch/arm/mach-omap1/board-htcherald.c +++ b/arch/arm/mach-omap1/board-htcherald.c @@ -30,6 +30,13 @@ #include <linux/input.h> #include <linux/io.h> #include <linux/gpio.h> +#include <linux/gpio_keys.h> +#include <linux/i2c.h> +#include <linux/i2c-gpio.h> +#include <linux/htcpld.h> +#include <linux/leds.h> +#include <linux/spi/spi.h> +#include <linux/spi/ads7846.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -39,6 +46,7 @@ #include <plat/board.h> #include <plat/keypad.h> #include <plat/usb.h> +#include <plat/mmc.h> #include <mach/irqs.h> @@ -52,13 +60,123 @@ #define OMAP_LCDC_CTRL_LCD_EN (1 << 0) #define OMAP_LCDC_STAT_DONE (1 << 0) -static struct omap_lcd_config htcherald_lcd_config __initdata = { - .ctrl_name = "internal", -}; +/* GPIO definitions for the power button and keyboard slide switch */ +#define HTCHERALD_GPIO_POWER 139 +#define HTCHERALD_GPIO_SLIDE 174 +#define HTCHERALD_GIRQ_BTNS 141 -static struct omap_board_config_kernel htcherald_config[] __initdata = { - { OMAP_TAG_LCD, &htcherald_lcd_config }, -}; +/* GPIO definitions for the touchscreen */ +#define HTCHERALD_GPIO_TS 76 + +/* HTCPLD definitions */ + +/* + * CPLD Logic + * + * Chip 3 - 0x03 + * + * Function 7 6 5 4 3 2 1 0 + * ------------------------------------ + * DPAD light x x x x x x x 1 + * SoundDev x x x x 1 x x x + * Screen white 1 x x x x x x x + * MMC power on x x x x x 1 x x + * Happy times (n) 0 x x x x 1 x x + * + * Chip 4 - 0x04 + * + * Function 7 6 5 4 3 2 1 0 + * ------------------------------------ + * Keyboard light x x x x x x x 1 + * LCD Bright (4) x x x x x 1 1 x + * LCD Bright (3) x x x x x 0 1 x + * LCD Bright (2) x x x x x 1 0 x + * LCD Bright (1) x x x x x 0 0 x + * LCD Off x x x x 0 x x x + * LCD image (fb) 1 x x x x x x x + * LCD image (white) 0 x x x x x x x + * Caps lock LED x x 1 x x x x x + * + * Chip 5 - 0x05 + * + * Function 7 6 5 4 3 2 1 0 + * ------------------------------------ + * Red (solid) x x x x x 1 x x + * Red (flash) x x x x x x 1 x + * Green (GSM flash) x x x x 1 x x x + * Green (GSM solid) x x x 1 x x x x + * Green (wifi flash) x x 1 x x x x x + * Blue (bt flash) x 1 x x x x x x + * DPAD Int Enable 1 x x x x x x 0 + * + * (Combinations of the above can be made for different colors.) + * The direction pad interrupt enable must be set each time the + * interrupt is handled. + * + * Chip 6 - 0x06 + * + * Function 7 6 5 4 3 2 1 0 + * ------------------------------------ + * Vibrator x x x x 1 x x x + * Alt LED x x x 1 x x x x + * Screen white 1 x x x x x x x + * Screen white x x 1 x x x x x + * Screen white x 0 x x x x x x + * Enable kbd dpad x x x x x x 0 x + * Happy Times 0 1 0 x x x 0 x + */ + +/* + * HTCPLD GPIO lines start 16 after OMAP_MAX_GPIO_LINES to account + * for the 16 MPUIO lines. + */ +#define HTCPLD_GPIO_START_OFFSET (OMAP_MAX_GPIO_LINES + 16) +#define HTCPLD_IRQ(chip, offset) (OMAP_IRQ_END + 8 * (chip) + (offset)) +#define HTCPLD_BASE(chip, offset) \ + (HTCPLD_GPIO_START_OFFSET + 8 * (chip) + (offset)) + +#define HTCPLD_GPIO_LED_DPAD HTCPLD_BASE(0, 0) +#define HTCPLD_GPIO_LED_KBD HTCPLD_BASE(1, 0) +#define HTCPLD_GPIO_LED_CAPS HTCPLD_BASE(1, 5) +#define HTCPLD_GPIO_LED_RED_FLASH HTCPLD_BASE(2, 1) +#define HTCPLD_GPIO_LED_RED_SOLID HTCPLD_BASE(2, 2) +#define HTCPLD_GPIO_LED_GREEN_FLASH HTCPLD_BASE(2, 3) +#define HTCPLD_GPIO_LED_GREEN_SOLID HTCPLD_BASE(2, 4) +#define HTCPLD_GPIO_LED_WIFI HTCPLD_BASE(2, 5) +#define HTCPLD_GPIO_LED_BT HTCPLD_BASE(2, 6) +#define HTCPLD_GPIO_LED_VIBRATE HTCPLD_BASE(3, 3) +#define HTCPLD_GPIO_LED_ALT HTCPLD_BASE(3, 4) + +#define HTCPLD_GPIO_RIGHT_KBD HTCPLD_BASE(6, 7) +#define HTCPLD_GPIO_UP_KBD HTCPLD_BASE(6, 6) +#define HTCPLD_GPIO_LEFT_KBD HTCPLD_BASE(6, 5) +#define HTCPLD_GPIO_DOWN_KBD HTCPLD_BASE(6, 4) + +#define HTCPLD_GPIO_RIGHT_DPAD HTCPLD_BASE(7, 7) +#define HTCPLD_GPIO_UP_DPAD HTCPLD_BASE(7, 6) +#define HTCPLD_GPIO_LEFT_DPAD HTCPLD_BASE(7, 5) +#define HTCPLD_GPIO_DOWN_DPAD HTCPLD_BASE(7, 4) +#define HTCPLD_GPIO_ENTER_DPAD HTCPLD_BASE(7, 3) + +/* + * The htcpld chip requires a gpio write to a specific line + * to re-enable interrupts after one has occurred. + */ +#define HTCPLD_GPIO_INT_RESET_HI HTCPLD_BASE(2, 7) +#define HTCPLD_GPIO_INT_RESET_LO HTCPLD_BASE(2, 0) + +/* Chip 5 */ +#define HTCPLD_IRQ_RIGHT_KBD HTCPLD_IRQ(0, 7) +#define HTCPLD_IRQ_UP_KBD HTCPLD_IRQ(0, 6) +#define HTCPLD_IRQ_LEFT_KBD HTCPLD_IRQ(0, 5) +#define HTCPLD_IRQ_DOWN_KBD HTCPLD_IRQ(0, 4) + +/* Chip 6 */ +#define HTCPLD_IRQ_RIGHT_DPAD HTCPLD_IRQ(1, 7) +#define HTCPLD_IRQ_UP_DPAD HTCPLD_IRQ(1, 6) +#define HTCPLD_IRQ_LEFT_DPAD HTCPLD_IRQ(1, 5) +#define HTCPLD_IRQ_DOWN_DPAD HTCPLD_IRQ(1, 4) +#define HTCPLD_IRQ_ENTER_DPAD HTCPLD_IRQ(1, 3) /* Keyboard definition */ @@ -140,6 +258,129 @@ static struct platform_device kp_device = { .resource = kp_resources, }; +/* GPIO buttons for keyboard slide and power button */ +static struct gpio_keys_button herald_gpio_keys_table[] = { + {BTN_0, HTCHERALD_GPIO_POWER, 1, "POWER", EV_KEY, 1, 20}, + {SW_LID, HTCHERALD_GPIO_SLIDE, 0, "SLIDE", EV_SW, 1, 20}, + + {KEY_LEFT, HTCPLD_GPIO_LEFT_KBD, 1, "LEFT", EV_KEY, 1, 20}, + {KEY_RIGHT, HTCPLD_GPIO_RIGHT_KBD, 1, "RIGHT", EV_KEY, 1, 20}, + {KEY_UP, HTCPLD_GPIO_UP_KBD, 1, "UP", EV_KEY, 1, 20}, + {KEY_DOWN, HTCPLD_GPIO_DOWN_KBD, 1, "DOWN", EV_KEY, 1, 20}, + + {KEY_LEFT, HTCPLD_GPIO_LEFT_DPAD, 1, "DLEFT", EV_KEY, 1, 20}, + {KEY_RIGHT, HTCPLD_GPIO_RIGHT_DPAD, 1, "DRIGHT", EV_KEY, 1, 20}, + {KEY_UP, HTCPLD_GPIO_UP_DPAD, 1, "DUP", EV_KEY, 1, 20}, + {KEY_DOWN, HTCPLD_GPIO_DOWN_DPAD, 1, "DDOWN", EV_KEY, 1, 20}, + {KEY_ENTER, HTCPLD_GPIO_ENTER_DPAD, 1, "DENTER", EV_KEY, 1, 20}, +}; + +static struct gpio_keys_platform_data herald_gpio_keys_data = { + .buttons = herald_gpio_keys_table, + .nbuttons = ARRAY_SIZE(herald_gpio_keys_table), + .rep = 1, +}; + +static struct platform_device herald_gpiokeys_device = { + .name = "gpio-keys", + .id = -1, + .dev = { + .platform_data = &herald_gpio_keys_data, + }, +}; + +/* LEDs for the Herald. These connect to the HTCPLD GPIO device. */ +static struct gpio_led gpio_leds[] = { + {"dpad", NULL, HTCPLD_GPIO_LED_DPAD, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, + {"kbd", NULL, HTCPLD_GPIO_LED_KBD, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, + {"vibrate", NULL, HTCPLD_GPIO_LED_VIBRATE, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, + {"green_solid", NULL, HTCPLD_GPIO_LED_GREEN_SOLID, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, + {"green_flash", NULL, HTCPLD_GPIO_LED_GREEN_FLASH, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, + {"red_solid", "mmc0", HTCPLD_GPIO_LED_RED_SOLID, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, + {"red_flash", NULL, HTCPLD_GPIO_LED_RED_FLASH, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, + {"wifi", NULL, HTCPLD_GPIO_LED_WIFI, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, + {"bt", NULL, HTCPLD_GPIO_LED_BT, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, + {"caps", NULL, HTCPLD_GPIO_LED_CAPS, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, + {"alt", NULL, HTCPLD_GPIO_LED_ALT, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, +}; + +static struct gpio_led_platform_data gpio_leds_data = { + .leds = gpio_leds, + .num_leds = ARRAY_SIZE(gpio_leds), +}; + +static struct platform_device gpio_leds_device = { + .name = "leds-gpio", + .id = 0, + .dev = { + .platform_data = &gpio_leds_data, + }, +}; + +/* HTC PLD chips */ + +static struct resource htcpld_resources[] = { + [0] = { + .start = OMAP_GPIO_IRQ(HTCHERALD_GIRQ_BTNS), + .end = OMAP_GPIO_IRQ(HTCHERALD_GIRQ_BTNS), + .flags = IORESOURCE_IRQ, + }, +}; + +struct htcpld_chip_platform_data htcpld_chips[] = { + [0] = { + .addr = 0x03, + .reset = 0x04, + .num_gpios = 8, + .gpio_out_base = HTCPLD_BASE(0, 0), + .gpio_in_base = HTCPLD_BASE(4, 0), + }, + [1] = { + .addr = 0x04, + .reset = 0x8e, + .num_gpios = 8, + .gpio_out_base = HTCPLD_BASE(1, 0), + .gpio_in_base = HTCPLD_BASE(5, 0), + }, + [2] = { + .addr = 0x05, + .reset = 0x80, + .num_gpios = 8, + .gpio_out_base = HTCPLD_BASE(2, 0), + .gpio_in_base = HTCPLD_BASE(6, 0), + .irq_base = HTCPLD_IRQ(0, 0), + .num_irqs = 8, + }, + [3] = { + .addr = 0x06, + .reset = 0x40, + .num_gpios = 8, + .gpio_out_base = HTCPLD_BASE(3, 0), + .gpio_in_base = HTCPLD_BASE(7, 0), + .irq_base = HTCPLD_IRQ(1, 0), + .num_irqs = 8, + }, +}; + +struct htcpld_core_platform_data htcpld_pfdata = { + .int_reset_gpio_hi = HTCPLD_GPIO_INT_RESET_HI, + .int_reset_gpio_lo = HTCPLD_GPIO_INT_RESET_LO, + .i2c_adapter_id = 1, + + .chip = htcpld_chips, + .num_chip = ARRAY_SIZE(htcpld_chips), +}; + +static struct platform_device htcpld_device = { + .name = "i2c-htcpld", + .id = -1, + .resource = htcpld_resources, + .num_resources = ARRAY_SIZE(htcpld_resources), + .dev = { + .platform_data = &htcpld_pfdata, + }, +}; + /* USB Device */ static struct omap_usb_config htcherald_usb_config __initdata = { .otg = 0, @@ -150,14 +391,71 @@ static struct omap_usb_config htcherald_usb_config __initdata = { }; /* LCD Device resources */ +static struct omap_lcd_config htcherald_lcd_config __initdata = { + .ctrl_name = "internal", +}; + +static struct omap_board_config_kernel htcherald_config[] __initdata = { + { OMAP_TAG_LCD, &htcherald_lcd_config }, +}; + static struct platform_device lcd_device = { .name = "lcd_htcherald", .id = -1, }; +/* MMC Card */ +#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) +static struct omap_mmc_platform_data htc_mmc1_data = { + .nr_slots = 1, + .switch_slot = NULL, + .slots[0] = { + .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, + .name = "mmcblk", + .nomux = 1, + .wires = 4, + .switch_pin = -1, + }, +}; + +static struct omap_mmc_platform_data *htc_mmc_data[1]; +#endif + + +/* Platform devices for the Herald */ static struct platform_device *devices[] __initdata = { &kp_device, &lcd_device, + &htcpld_device, + &gpio_leds_device, + &herald_gpiokeys_device, +}; + +/* + * Touchscreen + */ +static const struct ads7846_platform_data htcherald_ts_platform_data = { + .model = 7846, + .keep_vref_on = 1, + .x_plate_ohms = 496, + .gpio_pendown = HTCHERALD_GPIO_TS, + .pressure_max = 100000, + .pressure_min = 5000, + .x_min = 528, + .x_max = 3760, + .y_min = 624, + .y_max = 3760, +}; + +static struct spi_board_info __initdata htcherald_spi_board_info[] = { + { + .modalias = "ads7846", + .platform_data = &htcherald_ts_platform_data, + .irq = OMAP_GPIO_IRQ(HTCHERALD_GPIO_TS), + .max_speed_hz = 2500000, + .bus_num = 2, + .chip_select = 1, + } }; /* @@ -278,6 +576,7 @@ static void __init htcherald_init(void) { printk(KERN_INFO "HTC Herald init.\n"); + /* Do board initialization before we register all the devices */ omap_gpio_init(); omap_board_config = htcherald_config; @@ -288,6 +587,16 @@ static void __init htcherald_init(void) htcherald_usb_enable(); omap1_usb_init(&htcherald_usb_config); + + spi_register_board_info(htcherald_spi_board_info, + ARRAY_SIZE(htcherald_spi_board_info)); + + omap_register_i2c_bus(1, 100, NULL, 0); + +#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) + htc_mmc_data[0] = &htc_mmc1_data; + omap1_init_mmc(htc_mmc_data, 1); +#endif } static void __init htcherald_init_irq(void) diff --git a/arch/arm/mach-omap1/board-sx1-mmc.c b/arch/arm/mach-omap1/board-sx1-mmc.c index 5b33ae8141bc..e8ddd86e3fda 100644 --- a/arch/arm/mach-omap1/board-sx1-mmc.c +++ b/arch/arm/mach-omap1/board-sx1-mmc.c @@ -44,8 +44,7 @@ static struct omap_mmc_platform_data mmc1_data = { .nr_slots = 1, .slots[0] = { .set_power = mmc_set_power, - .ocr_mask = MMC_VDD_28_29 | MMC_VDD_30_31 | - MMC_VDD_32_33 | MMC_VDD_33_34, + .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, .name = "mmcblk", }, }; diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c index aa0725608fb1..ea0d80a89da7 100644 --- a/arch/arm/mach-omap1/devices.c +++ b/arch/arm/mach-omap1/devices.c @@ -9,6 +9,7 @@ * (at your option) any later version. */ +#include <linux/dma-mapping.h> #include <linux/module.h> #include <linux/kernel.h> #include <linux/init.h> @@ -25,6 +26,7 @@ #include <mach/gpio.h> #include <plat/mmc.h> #include <plat/omap7xx.h> +#include <plat/mcbsp.h> /*-------------------------------------------------------------------------*/ @@ -191,10 +193,76 @@ static inline void omap_init_spi100k(void) } #endif + +#define OMAP1_CAMERA_BASE 0xfffb6800 +#define OMAP1_CAMERA_IOSIZE 0x1c + +static struct resource omap1_camera_resources[] = { + [0] = { + .start = OMAP1_CAMERA_BASE, + .end = OMAP1_CAMERA_BASE + OMAP1_CAMERA_IOSIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = INT_CAMERA, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 omap1_camera_dma_mask = DMA_BIT_MASK(32); + +static struct platform_device omap1_camera_device = { + .name = "omap1-camera", + .id = 0, /* This is used to put cameras on this interface */ + .dev = { + .dma_mask = &omap1_camera_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(omap1_camera_resources), + .resource = omap1_camera_resources, +}; + +void __init omap1_camera_init(void *info) +{ + struct platform_device *dev = &omap1_camera_device; + int ret; + + dev->dev.platform_data = info; + + ret = platform_device_register(dev); + if (ret) + dev_err(&dev->dev, "unable to register device: %d\n", ret); +} + + /*-------------------------------------------------------------------------*/ static inline void omap_init_sti(void) {} +#if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE) + +static struct platform_device omap_pcm = { + .name = "omap-pcm-audio", + .id = -1, +}; + +OMAP_MCBSP_PLATFORM_DEVICE(1); +OMAP_MCBSP_PLATFORM_DEVICE(2); +OMAP_MCBSP_PLATFORM_DEVICE(3); + +static void omap_init_audio(void) +{ + platform_device_register(&omap_mcbsp1); + platform_device_register(&omap_mcbsp2); + if (!cpu_is_omap7xx()) + platform_device_register(&omap_mcbsp3); + platform_device_register(&omap_pcm); +} + +#else +static inline void omap_init_audio(void) {} +#endif + /*-------------------------------------------------------------------------*/ /* @@ -227,8 +295,36 @@ static int __init omap1_init_devices(void) omap_init_rtc(); omap_init_spi100k(); omap_init_sti(); + omap_init_audio(); return 0; } arch_initcall(omap1_init_devices); +#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE) + +static struct resource wdt_resources[] = { + { + .start = 0xfffeb000, + .end = 0xfffeb07F, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device omap_wdt_device = { + .name = "omap_wdt", + .id = -1, + .num_resources = ARRAY_SIZE(wdt_resources), + .resource = wdt_resources, +}; + +static int __init omap_init_wdt(void) +{ + if (!cpu_is_omap16xx()) + return; + + platform_device_register(&omap_wdt_device); + return 0; +} +subsys_initcall(omap_init_wdt); +#endif diff --git a/arch/arm/mach-omap1/include/mach/camera.h b/arch/arm/mach-omap1/include/mach/camera.h new file mode 100644 index 000000000000..fd54b452eb22 --- /dev/null +++ b/arch/arm/mach-omap1/include/mach/camera.h @@ -0,0 +1,11 @@ +#ifndef __ASM_ARCH_CAMERA_H_ +#define __ASM_ARCH_CAMERA_H_ + +void omap1_camera_init(void *); + +static inline void omap1_set_camera_info(struct omap1_cam_platform_data *info) +{ + omap1_camera_init(info); +} + +#endif /* __ASM_ARCH_CAMERA_H_ */ diff --git a/arch/arm/mach-omap1/pm_bus.c b/arch/arm/mach-omap1/pm_bus.c new file mode 100644 index 000000000000..8b66392be745 --- /dev/null +++ b/arch/arm/mach-omap1/pm_bus.c @@ -0,0 +1,98 @@ +/* + * Runtime PM support code for OMAP1 + * + * Author: Kevin Hilman, Deep Root Systems, LLC + * + * Copyright (C) 2010 Texas Instruments, Inc. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/io.h> +#include <linux/pm_runtime.h> +#include <linux/platform_device.h> +#include <linux/mutex.h> +#include <linux/clk.h> +#include <linux/err.h> + +#include <plat/omap_device.h> +#include <plat/omap-pm.h> + +#ifdef CONFIG_PM_RUNTIME +static int omap1_pm_runtime_suspend(struct device *dev) +{ + struct clk *iclk, *fclk; + int ret = 0; + + dev_dbg(dev, "%s\n", __func__); + + ret = pm_generic_runtime_suspend(dev); + + fclk = clk_get(dev, "fck"); + if (!IS_ERR(fclk)) { + clk_disable(fclk); + clk_put(fclk); + } + + iclk = clk_get(dev, "ick"); + if (!IS_ERR(iclk)) { + clk_disable(iclk); + clk_put(iclk); + } + + return 0; +}; + +static int omap1_pm_runtime_resume(struct device *dev) +{ + int ret = 0; + struct clk *iclk, *fclk; + + dev_dbg(dev, "%s\n", __func__); + + iclk = clk_get(dev, "ick"); + if (!IS_ERR(iclk)) { + clk_enable(iclk); + clk_put(iclk); + } + + fclk = clk_get(dev, "fck"); + if (!IS_ERR(fclk)) { + clk_enable(fclk); + clk_put(fclk); + } + + return pm_generic_runtime_resume(dev); +}; + +static int __init omap1_pm_runtime_init(void) +{ + const struct dev_pm_ops *pm; + struct dev_pm_ops *omap_pm; + + pm = platform_bus_get_pm_ops(); + if (!pm) { + pr_err("%s: unable to get dev_pm_ops from platform_bus\n", + __func__); + return -ENODEV; + } + + omap_pm = kmemdup(pm, sizeof(struct dev_pm_ops), GFP_KERNEL); + if (!omap_pm) { + pr_err("%s: unable to alloc memory for new dev_pm_ops\n", + __func__); + return -ENOMEM; + } + + omap_pm->runtime_suspend = omap1_pm_runtime_suspend; + omap_pm->runtime_resume = omap1_pm_runtime_resume; + + platform_bus_set_pm_ops(omap_pm); + + return 0; +} +core_initcall(omap1_pm_runtime_init); +#endif /* CONFIG_PM_RUNTIME */ diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index b48bacf0a7aa..ab784bfde908 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -11,9 +11,8 @@ config ARCH_OMAP2PLUS_TYPICAL select PM_RUNTIME select VFP select NEON if ARCH_OMAP3 || ARCH_OMAP4 - select SERIAL_8250 - select SERIAL_CORE_CONSOLE - select SERIAL_8250_CONSOLE + select SERIAL_OMAP + select SERIAL_OMAP_CONSOLE select I2C select I2C_OMAP select MFD @@ -35,7 +34,7 @@ config ARCH_OMAP3 default y select CPU_V7 select USB_ARCH_HAS_EHCI - select ARM_L1_CACHE_SHIFT_6 + select ARM_L1_CACHE_SHIFT_6 if !ARCH_OMAP4 config ARCH_OMAP4 bool "TI OMAP4" @@ -43,6 +42,8 @@ config ARCH_OMAP4 depends on ARCH_OMAP2PLUS select CPU_V7 select ARM_GIC + select PL310_ERRATA_588369 + select ARM_ERRATA_720789 comment "OMAP Core Type" depends on ARCH_OMAP2 @@ -99,20 +100,20 @@ config MACH_OMAP2_TUSB6010 config MACH_OMAP_H4 bool "OMAP 2420 H4 board" - depends on ARCH_OMAP2 + depends on ARCH_OMAP2420 default y select OMAP_PACKAGE_ZAF select OMAP_DEBUG_DEVICES config MACH_OMAP_APOLLON bool "OMAP 2420 Apollon board" - depends on ARCH_OMAP2 + depends on ARCH_OMAP2420 default y select OMAP_PACKAGE_ZAC config MACH_OMAP_2430SDP bool "OMAP 2430 SDP board" - depends on ARCH_OMAP2 + depends on ARCH_OMAP2430 default y select OMAP_PACKAGE_ZAC @@ -135,6 +136,26 @@ config MACH_OMAP_LDP default y select OMAP_PACKAGE_CBB +config MACH_OMAP3530_LV_SOM + bool "OMAP3 Logic 3530 LV SOM board" + depends on ARCH_OMAP3 + select OMAP_PACKAGE_CBB + default y + help + Support for the LogicPD OMAP3530 SOM Development kit + for full description please see the products webpage at + http://www.logicpd.com/products/development-kits/texas-instruments-zoom%E2%84%A2-omap35x-development-kit + +config MACH_OMAP3_TORPEDO + bool "OMAP3 Logic 35x Torpedo board" + depends on ARCH_OMAP3 + select OMAP_PACKAGE_CBB + default y + help + Support for the LogicPD OMAP35x Torpedo Development kit + for full description please see the products webpage at + http://www.logicpd.com/products/development-kits/zoom-omap35x-torpedo-development-kit + config MACH_OVERO bool "Gumstix Overo board" depends on ARCH_OMAP3 @@ -200,12 +221,18 @@ config MACH_OMAP_ZOOM2 depends on ARCH_OMAP3 default y select OMAP_PACKAGE_CBB + select SERIAL_8250 + select SERIAL_CORE_CONSOLE + select SERIAL_8250_CONSOLE config MACH_OMAP_ZOOM3 bool "OMAP3630 Zoom3 board" depends on ARCH_OMAP3 default y select OMAP_PACKAGE_CBP + select SERIAL_8250 + select SERIAL_CORE_CONSOLE + select SERIAL_8250_CONSOLE config MACH_CM_T35 bool "CompuLab CM-T35 module" @@ -214,12 +241,25 @@ config MACH_CM_T35 select OMAP_PACKAGE_CUS select OMAP_MUX +config MACH_CM_T3517 + bool "CompuLab CM-T3517 module" + depends on ARCH_OMAP3 + default y + select OMAP_PACKAGE_CBB + select OMAP_MUX + config MACH_IGEP0020 bool "IGEP v2 board" depends on ARCH_OMAP3 default y select OMAP_PACKAGE_CBB +config MACH_IGEP0030 + bool "IGEP OMAP3 module" + depends on ARCH_OMAP3 + default y + select OMAP_PACKAGE_CBB + config MACH_SBC3530 bool "OMAP3 SBC STALKER board" depends on ARCH_OMAP3 diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 88d3a1e920f5..7352412e4917 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -3,9 +3,10 @@ # # Common support -obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o +obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o \ + common.o -omap-2-3-common = irq.o sdrc.o +omap-2-3-common = irq.o sdrc.o prm2xxx_3xxx.o hwmod-common = omap_hwmod.o \ omap_hwmod_common_data.o prcm-common = prcm.o powerdomain.o @@ -15,7 +16,7 @@ clock-common = clock.o clock_common_data.o \ obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(hwmod-common) obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(hwmod-common) -obj-$(CONFIG_ARCH_OMAP4) += $(prcm-common) $(hwmod-common) +obj-$(CONFIG_ARCH_OMAP4) += $(prcm-common) prm44xx.o $(hwmod-common) obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o @@ -49,14 +50,18 @@ obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o # Power Management ifeq ($(CONFIG_PM),y) obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o -obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o -obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o -obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o +obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o pm_bus.o +obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o pm_bus.o +obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o pm_bus.o obj-$(CONFIG_PM_DEBUG) += pm-debug.o AFLAGS_sleep24xx.o :=-Wa,-march=armv6 AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a +ifeq ($(CONFIG_PM_VERBOSE),y) +CFLAGS_pm_bus.o += -DDEBUG +endif + endif # PRCM @@ -87,6 +92,7 @@ obj-$(CONFIG_ARCH_OMAP2430) += opp2430_data.o obj-$(CONFIG_ARCH_OMAP2420) += omap_hwmod_2420_data.o obj-$(CONFIG_ARCH_OMAP2430) += omap_hwmod_2430_data.o obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o +obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o # EMU peripherals obj-$(CONFIG_OMAP3_EMU) += emu.o @@ -115,6 +121,10 @@ obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o \ obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o \ board-flash.o \ hsmmc.o +obj-$(CONFIG_MACH_OMAP3530_LV_SOM) += board-omap3logic.o \ + hsmmc.o +obj-$(CONFIG_MACH_OMAP3_TORPEDO) += board-omap3logic.o \ + hsmmc.o obj-$(CONFIG_MACH_OVERO) += board-overo.o \ hsmmc.o obj-$(CONFIG_MACH_OMAP3EVM) += board-omap3evm.o \ @@ -146,8 +156,11 @@ obj-$(CONFIG_MACH_OMAP_3630SDP) += board-3630sdp.o \ hsmmc.o obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o \ hsmmc.o +obj-$(CONFIG_MACH_CM_T3517) += board-cm-t3517.o obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o \ hsmmc.o +obj-$(CONFIG_MACH_IGEP0030) += board-igep0030.o \ + hsmmc.o obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK) += board-omap3touchbook.o \ hsmmc.o obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o \ @@ -174,3 +187,6 @@ obj-y += $(nand-m) $(nand-y) smc91x-$(CONFIG_SMC91X) := gpmc-smc91x.o obj-y += $(smc91x-m) $(smc91x-y) + +smsc911x-$(CONFIG_SMSC911X) := gpmc-smsc911x.o +obj-y += $(smsc911x-m) $(smsc911x-y) diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index b857ce484510..b527f8d187ad 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c @@ -19,6 +19,7 @@ #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> #include <linux/mtd/physmap.h> +#include <linux/mmc/host.h> #include <linux/delay.h> #include <linux/i2c/twl.h> #include <linux/err.h> @@ -190,7 +191,7 @@ static int __init omap2430_i2c_init(void) static struct omap2_hsmmc_info mmc[] __initdata = { { .mmc = 1, - .wires = 4, + .caps = MMC_CAP_4_BIT_DATA, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, .ext_clock = 1, diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index a5b095cf2adc..4e3742c512b8 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -24,6 +24,7 @@ #include <linux/regulator/machine.h> #include <linux/io.h> #include <linux/gpio.h> +#include <linux/mmc/host.h> #include <mach/hardware.h> #include <asm/mach-types.h> @@ -38,15 +39,14 @@ #include <plat/gpmc.h> #include <plat/display.h> -#include <plat/control.h> #include <plat/gpmc-smc91x.h> -#include <mach/board-flash.h> - +#include "board-flash.h" #include "mux.h" #include "sdram-qimonda-hyb18m512160af-6.h" #include "hsmmc.h" #include "pm.h" +#include "control.h" #define CONFIG_DISABLE_HFCLK 1 @@ -76,7 +76,7 @@ static struct cpuidle_params omap3_cpuidle_params_table[] = { {1, 10000, 30000, 300000}, }; -static int board_keymap[] = { +static uint32_t board_keymap[] = { KEY(0, 0, KEY_LEFT), KEY(0, 1, KEY_RIGHT), KEY(0, 2, KEY_A), @@ -353,12 +353,12 @@ static struct omap2_hsmmc_info mmc[] = { /* 8 bits (default) requires S6.3 == ON, * so the SIM card isn't used; else 4 bits. */ - .wires = 8, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, .gpio_wp = 4, }, { .mmc = 2, - .wires = 8, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, .gpio_wp = 7, }, {} /* Terminator */ diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c index fd27ac0860b0..bbcf580fa097 100644 --- a/arch/arm/mach-omap2/board-3630sdp.c +++ b/arch/arm/mach-omap2/board-3630sdp.c @@ -21,8 +21,8 @@ #include <plat/usb.h> #include <mach/board-zoom.h> -#include <mach/board-flash.h> +#include "board-flash.h" #include "mux.h" #include "sdram-hynix-h8mbx00u0mer-0em.h" @@ -208,7 +208,6 @@ static struct flash_partitions sdp_flash_partitions[] = { static void __init omap_sdp_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); - omap_serial_init(); zoom_peripherals_init(); board_smc91x_init(); board_flash_init(sdp_flash_partitions, chip_sel_sdp); diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index 0b6a65f3a10a..69a4ae971e41 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -20,6 +20,7 @@ #include <linux/usb/otg.h> #include <linux/spi/spi.h> #include <linux/i2c/twl.h> +#include <linux/gpio_keys.h> #include <linux/regulator/machine.h> #include <linux/leds.h> @@ -31,15 +32,18 @@ #include <plat/board.h> #include <plat/common.h> -#include <plat/control.h> -#include <plat/timer-gp.h> #include <plat/usb.h> #include <plat/mmc.h> + #include "hsmmc.h" +#include "timer-gp.h" +#include "control.h" #define ETH_KS8851_IRQ 34 #define ETH_KS8851_POWER_ON 48 #define ETH_KS8851_QUART 138 +#define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO 184 +#define OMAP4_SFH7741_ENABLE_GPIO 188 static struct gpio_led sdp4430_gpio_leds[] = { { @@ -77,11 +81,47 @@ static struct gpio_led sdp4430_gpio_leds[] = { }; +static struct gpio_keys_button sdp4430_gpio_keys[] = { + { + .desc = "Proximity Sensor", + .type = EV_SW, + .code = SW_FRONT_PROXIMITY, + .gpio = OMAP4_SFH7741_SENSOR_OUTPUT_GPIO, + .active_low = 0, + } +}; + static struct gpio_led_platform_data sdp4430_led_data = { .leds = sdp4430_gpio_leds, .num_leds = ARRAY_SIZE(sdp4430_gpio_leds), }; +static int omap_prox_activate(struct device *dev) +{ + gpio_set_value(OMAP4_SFH7741_ENABLE_GPIO , 1); + return 0; +} + +static void omap_prox_deactivate(struct device *dev) +{ + gpio_set_value(OMAP4_SFH7741_ENABLE_GPIO , 0); +} + +static struct gpio_keys_platform_data sdp4430_gpio_keys_data = { + .buttons = sdp4430_gpio_keys, + .nbuttons = ARRAY_SIZE(sdp4430_gpio_keys), + .enable = omap_prox_activate, + .disable = omap_prox_deactivate, +}; + +static struct platform_device sdp4430_gpio_keys_device = { + .name = "gpio-keys", + .id = -1, + .dev = { + .platform_data = &sdp4430_gpio_keys_data, + }, +}; + static struct platform_device sdp4430_leds_gpio = { .name = "leds-gpio", .id = -1, @@ -161,6 +201,7 @@ static struct platform_device sdp4430_lcd_device = { static struct platform_device *sdp4430_devices[] __initdata = { &sdp4430_lcd_device, + &sdp4430_gpio_keys_device, &sdp4430_leds_gpio, }; @@ -193,15 +234,16 @@ static struct omap_musb_board_data musb_board_data = { static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, - .wires = 8, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, .gpio_wp = -EINVAL, }, { .mmc = 2, - .wires = 8, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, .nonremovable = true, + .ocr_mask = MMC_VDD_29_30, }, {} /* Terminator */ }; @@ -235,8 +277,14 @@ static int omap4_twl6030_hsmmc_late_init(struct device *dev) static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev) { - struct omap_mmc_platform_data *pdata = dev->platform_data; + struct omap_mmc_platform_data *pdata; + /* dev can be null if CONFIG_MMC_OMAP_HS is not set */ + if (!dev) { + pr_err("Failed %s\n", __func__); + return; + } + pdata = dev->platform_data; pdata->init = omap4_twl6030_hsmmc_late_init; } @@ -412,6 +460,11 @@ static struct i2c_board_info __initdata sdp4430_i2c_3_boardinfo[] = { I2C_BOARD_INFO("tmp105", 0x48), }, }; +static struct i2c_board_info __initdata sdp4430_i2c_4_boardinfo[] = { + { + I2C_BOARD_INFO("hmc5843", 0x1e), + }, +}; static int __init omap4_i2c_init(void) { /* @@ -423,14 +476,36 @@ static int __init omap4_i2c_init(void) omap_register_i2c_bus(2, 400, NULL, 0); omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo, ARRAY_SIZE(sdp4430_i2c_3_boardinfo)); - omap_register_i2c_bus(4, 400, NULL, 0); + omap_register_i2c_bus(4, 400, sdp4430_i2c_4_boardinfo, + ARRAY_SIZE(sdp4430_i2c_4_boardinfo)); return 0; } + +static void __init omap_sfh7741prox_init(void) +{ + int error; + + error = gpio_request(OMAP4_SFH7741_ENABLE_GPIO, "sfh7741"); + if (error < 0) { + pr_err("%s:failed to request GPIO %d, error %d\n", + __func__, OMAP4_SFH7741_ENABLE_GPIO, error); + return; + } + + error = gpio_direction_output(OMAP4_SFH7741_ENABLE_GPIO , 0); + if (error < 0) { + pr_err("%s: GPIO configuration failed: GPIO %d,error %d\n", + __func__, OMAP4_SFH7741_ENABLE_GPIO, error); + gpio_free(OMAP4_SFH7741_ENABLE_GPIO); + } +} + static void __init omap_4430sdp_init(void) { int status; omap4_i2c_init(); + omap_sfh7741prox_init(); platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices)); omap_serial_init(); omap4_twl6030_hsmmc_init(mmc); diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index f85c8da17e8b..07399505312b 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c @@ -18,6 +18,7 @@ #include <linux/kernel.h> #include <linux/init.h> +#include <linux/clk.h> #include <linux/platform_device.h> #include <linux/gpio.h> #include <linux/i2c/pca953x.h> @@ -32,25 +33,43 @@ #include <plat/board.h> #include <plat/common.h> -#include <plat/control.h> #include <plat/usb.h> #include <plat/display.h> #include "mux.h" +#include "control.h" -#define AM35XX_EVM_PHY_MASK (0xF) #define AM35XX_EVM_MDIO_FREQUENCY (1000000) +static struct mdio_platform_data am3517_evm_mdio_pdata = { + .bus_freq = AM35XX_EVM_MDIO_FREQUENCY, +}; + +static struct resource am3517_mdio_resources[] = { + { + .start = AM35XX_IPSS_EMAC_BASE + AM35XX_EMAC_MDIO_OFFSET, + .end = AM35XX_IPSS_EMAC_BASE + AM35XX_EMAC_MDIO_OFFSET + + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device am3517_mdio_device = { + .name = "davinci_mdio", + .id = 0, + .num_resources = ARRAY_SIZE(am3517_mdio_resources), + .resource = am3517_mdio_resources, + .dev.platform_data = &am3517_evm_mdio_pdata, +}; + static struct emac_platform_data am3517_evm_emac_pdata = { - .phy_mask = AM35XX_EVM_PHY_MASK, - .mdio_max_freq = AM35XX_EVM_MDIO_FREQUENCY, .rmii_en = 1, }; static struct resource am3517_emac_resources[] = { { .start = AM35XX_IPSS_EMAC_BASE, - .end = AM35XX_IPSS_EMAC_BASE + 0x3FFFF, + .end = AM35XX_IPSS_EMAC_BASE + 0x2FFFF, .flags = IORESOURCE_MEM, }, { @@ -106,14 +125,13 @@ static void am3517_disable_ethernet_int(void) regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); } -void am3517_evm_ethernet_init(struct emac_platform_data *pdata) +static void am3517_evm_ethernet_init(struct emac_platform_data *pdata) { unsigned int regval; pdata->ctrl_reg_offset = AM35XX_EMAC_CNTRL_OFFSET; pdata->ctrl_mod_reg_offset = AM35XX_EMAC_CNTRL_MOD_OFFSET; pdata->ctrl_ram_offset = AM35XX_EMAC_CNTRL_RAM_OFFSET; - pdata->mdio_reg_offset = AM35XX_EMAC_MDIO_OFFSET; pdata->ctrl_ram_size = AM35XX_EMAC_CNTRL_RAM_SIZE; pdata->version = EMAC_VERSION_2; pdata->hw_ram_addr = AM35XX_EMAC_HW_RAM_ADDR; @@ -121,6 +139,9 @@ void am3517_evm_ethernet_init(struct emac_platform_data *pdata) pdata->interrupt_disable = am3517_disable_ethernet_int; am3517_emac_device.dev.platform_data = pdata; platform_device_register(&am3517_emac_device); + platform_device_register(&am3517_mdio_device); + clk_add_alias(NULL, dev_name(&am3517_mdio_device.dev), + NULL, &am3517_emac_device.dev); regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); regval = regval & (~(AM35XX_CPGMACSS_SW_RST)); @@ -139,7 +160,6 @@ void am3517_evm_ethernet_init(struct emac_platform_data *pdata) static struct i2c_board_info __initdata am3517evm_i2c1_boardinfo[] = { { I2C_BOARD_INFO("s35390a", 0x30), - .type = "s35390a", }, }; @@ -347,7 +367,7 @@ static struct omap_dss_board_info am3517_evm_dss_data = { .default_device = &am3517_evm_lcd_device, }; -struct platform_device am3517_evm_dss_device = { +static struct platform_device am3517_evm_dss_device = { .name = "omapdss", .id = -1, .dev = { @@ -375,6 +395,31 @@ static void __init am3517_evm_init_irq(void) omap_gpio_init(); } +static struct omap_musb_board_data musb_board_data = { + .interface_type = MUSB_INTERFACE_ULPI, + .mode = MUSB_OTG, + .power = 500, +}; + +static __init void am3517_evm_musb_init(void) +{ + u32 devconf2; + + /* + * Set up USB clock/mode in the DEVCONF2 register. + */ + devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); + + /* USB2.0 PHY reference clock is 13 MHz */ + devconf2 &= ~(CONF2_REFFREQ | CONF2_OTGMODE | CONF2_PHY_GPIOMODE); + devconf2 |= CONF2_REFFREQ_13MHZ | CONF2_SESENDEN | CONF2_VBDTCTEN + | CONF2_DATPOL; + + omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); + + usb_musb_init(&musb_board_data); +} + static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, #if defined(CONFIG_PANEL_SHARP_LQ043T1DG01) || \ @@ -393,6 +438,8 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { #ifdef CONFIG_OMAP_MUX static struct omap_board_mux board_mux[] __initdata = { + /* USB OTG DRVVBUS offset = 0x212 */ + OMAP3_MUX(SAD2D_MCAD23, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), { .reg_offset = OMAP_MUX_TERMINATOR }, }; #else @@ -459,6 +506,9 @@ static void __init am3517_evm_init(void) ARRAY_SIZE(am3517evm_i2c1_boardinfo)); /*Ethernet*/ am3517_evm_ethernet_init(&am3517_evm_emac_pdata); + + /* MUSB */ + am3517_evm_musb_init(); } MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM") diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c index 68f07f5f441a..2c6db1aaeb29 100644 --- a/arch/arm/mach-omap2/board-apollon.c +++ b/arch/arm/mach-omap2/board-apollon.c @@ -39,9 +39,9 @@ #include <plat/board.h> #include <plat/common.h> #include <plat/gpmc.h> -#include <plat/control.h> #include "mux.h" +#include "control.h" /* LED & Switch macros */ #define LED0_GPIO13 13 diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index 934d9380c372..63f764e2af3f 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -31,6 +31,7 @@ #include <linux/i2c/at24.h> #include <linux/i2c/twl.h> #include <linux/regulator/machine.h> +#include <linux/mmc/host.h> #include <linux/spi/spi.h> #include <linux/spi/tdo24m.h> @@ -237,8 +238,6 @@ static inline void cm_t35_init_nand(void) {} defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) #include <linux/spi/ads7846.h> -#include <plat/mcspi.h> - static struct omap2_mcspi_device_config ads7846_mcspi_config = { .turbo_mode = 0, .single_channel = 1, /* 0: slave, 1: master */ @@ -558,7 +557,7 @@ static struct twl4030_usb_data cm_t35_usb_data = { .usb_mode = T2_USB_MODE_ULPI, }; -static int cm_t35_keymap[] = { +static uint32_t cm_t35_keymap[] = { KEY(0, 0, KEY_A), KEY(0, 1, KEY_B), KEY(0, 2, KEY_LEFT), KEY(1, 0, KEY_UP), KEY(1, 1, KEY_ENTER), KEY(1, 2, KEY_DOWN), KEY(2, 0, KEY_RIGHT), KEY(2, 1, KEY_C), KEY(2, 2, KEY_D), @@ -579,14 +578,14 @@ static struct twl4030_keypad_data cm_t35_kp_data = { static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, - .wires = 4, + .caps = MMC_CAP_4_BIT_DATA, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, }, { .mmc = 2, - .wires = 4, + .caps = MMC_CAP_4_BIT_DATA, .transceiver = 1, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c new file mode 100644 index 000000000000..1dd303e9a267 --- /dev/null +++ b/arch/arm/mach-omap2/board-cm-t3517.c @@ -0,0 +1,292 @@ +/* + * linux/arch/arm/mach-omap2/board-cm-t3517.c + * + * Support for the CompuLab CM-T3517 modules + * + * Copyright (C) 2010 CompuLab, Ltd. + * Author: Igor Grinberg <grinberg@compulab.co.il> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/delay.h> +#include <linux/gpio.h> +#include <linux/leds.h> +#include <linux/rtc-v3020.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/partitions.h> +#include <linux/can/platform/ti_hecc.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> + +#include <plat/board.h> +#include <plat/common.h> +#include <plat/usb.h> +#include <plat/nand.h> +#include <plat/gpmc.h> + +#include <mach/am35xx.h> + +#include "mux.h" +#include "control.h" + +#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) +static struct gpio_led cm_t3517_leds[] = { + [0] = { + .gpio = 186, + .name = "cm-t3517:green", + .default_trigger = "heartbeat", + .active_low = 0, + }, +}; + +static struct gpio_led_platform_data cm_t3517_led_pdata = { + .num_leds = ARRAY_SIZE(cm_t3517_leds), + .leds = cm_t3517_leds, +}; + +static struct platform_device cm_t3517_led_device = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &cm_t3517_led_pdata, + }, +}; + +static void __init cm_t3517_init_leds(void) +{ + platform_device_register(&cm_t3517_led_device); +} +#else +static inline void cm_t3517_init_leds(void) {} +#endif + +#if defined(CONFIG_CAN_TI_HECC) || defined(CONFIG_CAN_TI_HECC_MODULE) +static struct resource cm_t3517_hecc_resources[] = { + { + .start = AM35XX_IPSS_HECC_BASE, + .end = AM35XX_IPSS_HECC_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_35XX_HECC0_IRQ, + .end = INT_35XX_HECC0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct ti_hecc_platform_data cm_t3517_hecc_pdata = { + .scc_hecc_offset = AM35XX_HECC_SCC_HECC_OFFSET, + .scc_ram_offset = AM35XX_HECC_SCC_RAM_OFFSET, + .hecc_ram_offset = AM35XX_HECC_RAM_OFFSET, + .mbx_offset = AM35XX_HECC_MBOX_OFFSET, + .int_line = AM35XX_HECC_INT_LINE, + .version = AM35XX_HECC_VERSION, +}; + +static struct platform_device cm_t3517_hecc_device = { + .name = "ti_hecc", + .id = 1, + .num_resources = ARRAY_SIZE(cm_t3517_hecc_resources), + .resource = cm_t3517_hecc_resources, + .dev = { + .platform_data = &cm_t3517_hecc_pdata, + }, +}; + +static void cm_t3517_init_hecc(void) +{ + platform_device_register(&cm_t3517_hecc_device); +} +#else +static inline void cm_t3517_init_hecc(void) {} +#endif + +#if defined(CONFIG_RTC_DRV_V3020) || defined(CONFIG_RTC_DRV_V3020_MODULE) +#define RTC_IO_GPIO (153) +#define RTC_WR_GPIO (154) +#define RTC_RD_GPIO (160) +#define RTC_CS_GPIO (163) + +struct v3020_platform_data cm_t3517_v3020_pdata = { + .use_gpio = 1, + .gpio_cs = RTC_CS_GPIO, + .gpio_wr = RTC_WR_GPIO, + .gpio_rd = RTC_RD_GPIO, + .gpio_io = RTC_IO_GPIO, +}; + +static struct platform_device cm_t3517_rtc_device = { + .name = "v3020", + .id = -1, + .dev = { + .platform_data = &cm_t3517_v3020_pdata, + } +}; + +static void __init cm_t3517_init_rtc(void) +{ + platform_device_register(&cm_t3517_rtc_device); +} +#else +static inline void cm_t3517_init_rtc(void) {} +#endif + +#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE) +#define HSUSB1_RESET_GPIO (146) +#define HSUSB2_RESET_GPIO (147) +#define USB_HUB_RESET_GPIO (152) + +static struct ehci_hcd_omap_platform_data cm_t3517_ehci_pdata __initdata = { + .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, + .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, + .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, + + .phy_reset = true, + .reset_gpio_port[0] = HSUSB1_RESET_GPIO, + .reset_gpio_port[1] = HSUSB2_RESET_GPIO, + .reset_gpio_port[2] = -EINVAL, +}; + +static int cm_t3517_init_usbh(void) +{ + int err; + + err = gpio_request(USB_HUB_RESET_GPIO, "usb hub rst"); + if (err) { + pr_err("CM-T3517: usb hub rst gpio request failed: %d\n", err); + } else { + gpio_direction_output(USB_HUB_RESET_GPIO, 0); + udelay(10); + gpio_set_value(USB_HUB_RESET_GPIO, 1); + msleep(1); + } + + usb_ehci_init(&cm_t3517_ehci_pdata); + + return 0; +} +#else +static inline int cm_t3517_init_usbh(void) +{ + return 0; +} +#endif + +#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE) +#define NAND_BLOCK_SIZE SZ_128K + +static struct mtd_partition cm_t3517_nand_partitions[] = { + { + .name = "xloader", + .offset = 0, /* Offset = 0x00000 */ + .size = 4 * NAND_BLOCK_SIZE, + .mask_flags = MTD_WRITEABLE + }, + { + .name = "uboot", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ + .size = 15 * NAND_BLOCK_SIZE, + }, + { + .name = "uboot environment", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */ + .size = 2 * NAND_BLOCK_SIZE, + }, + { + .name = "linux", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */ + .size = 32 * NAND_BLOCK_SIZE, + }, + { + .name = "rootfs", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x680000 */ + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct omap_nand_platform_data cm_t3517_nand_data = { + .parts = cm_t3517_nand_partitions, + .nr_parts = ARRAY_SIZE(cm_t3517_nand_partitions), + .dma_channel = -1, /* disable DMA in OMAP NAND driver */ + .cs = 0, +}; + +static void __init cm_t3517_init_nand(void) +{ + if (gpmc_nand_init(&cm_t3517_nand_data) < 0) + pr_err("CM-T3517: NAND initialization failed\n"); +} +#else +static inline void cm_t3517_init_nand(void) {} +#endif + +static struct omap_board_config_kernel cm_t3517_config[] __initdata = { +}; + +static void __init cm_t3517_init_irq(void) +{ + omap_board_config = cm_t3517_config; + omap_board_config_size = ARRAY_SIZE(cm_t3517_config); + + omap2_init_common_hw(NULL, NULL); + omap_init_irq(); + omap_gpio_init(); +} + +static struct omap_board_mux board_mux[] __initdata = { + /* GPIO186 - Green LED */ + OMAP3_MUX(SYS_CLKOUT2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), + /* RTC GPIOs: IO, WR#, RD#, CS# */ + OMAP3_MUX(MCBSP4_DR, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), + OMAP3_MUX(MCBSP4_DX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), + OMAP3_MUX(MCBSP_CLKS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), + OMAP3_MUX(UART3_CTS_RCTX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), + /* HSUSB1 RESET */ + OMAP3_MUX(UART2_TX, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), + /* HSUSB2 RESET */ + OMAP3_MUX(UART2_RX, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), + /* CM-T3517 USB HUB nRESET */ + OMAP3_MUX(MCBSP4_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), + + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; + +static void __init cm_t3517_init(void) +{ + omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); + omap_serial_init(); + cm_t3517_init_leds(); + cm_t3517_init_nand(); + cm_t3517_init_rtc(); + cm_t3517_init_usbh(); + cm_t3517_init_hecc(); +} + +MACHINE_START(CM_T3517, "Compulab CM-T3517") + .boot_params = 0x80000100, + .map_io = omap3_map_io, + .reserve = omap_reserve, + .init_irq = cm_t3517_init_irq, + .init_machine = cm_t3517_init, + .timer = &omap_timer, +MACHINE_END diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index 2205c20a4cdb..067f4379c87f 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -28,6 +28,7 @@ #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> #include <linux/mtd/nand.h> +#include <linux/mmc/host.h> #include <linux/regulator/machine.h> #include <linux/i2c/twl.h> @@ -44,7 +45,6 @@ #include <plat/gpmc.h> #include <plat/nand.h> #include <plat/usb.h> -#include <plat/timer-gp.h> #include <plat/display.h> #include <plat/mcspi.h> @@ -58,6 +58,7 @@ #include "mux.h" #include "hsmmc.h" +#include "timer-gp.h" #define NAND_BLOCK_SIZE SZ_128K @@ -105,7 +106,7 @@ static struct omap_nand_platform_data devkit8000_nand_data = { static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, - .wires = 8, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, .gpio_wp = 29, }, {} /* Terminator */ @@ -198,7 +199,7 @@ static struct platform_device devkit8000_dss_device = { static struct regulator_consumer_supply devkit8000_vdda_dac_supply = REGULATOR_SUPPLY("vdda_dac", "omapdss"); -static int board_keymap[] = { +static uint32_t board_keymap[] = { KEY(0, 0, KEY_1), KEY(1, 0, KEY_2), KEY(2, 0, KEY_3), diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c index ac834aa7abf6..fd38c05bb47f 100644 --- a/arch/arm/mach-omap2/board-flash.c +++ b/arch/arm/mach-omap2/board-flash.c @@ -21,7 +21,8 @@ #include <plat/nand.h> #include <plat/onenand.h> #include <plat/tc.h> -#include <mach/board-flash.h> + +#include "board-flash.h" #define REG_FPGA_REV 0x10 #define REG_FPGA_DIP_SWITCH_INPUT2 0x60 diff --git a/arch/arm/mach-omap2/include/mach/board-flash.h b/arch/arm/mach-omap2/board-flash.h index b2242ae2bb6f..69befe00dd2f 100644 --- a/arch/arm/mach-omap2/include/mach/board-flash.h +++ b/arch/arm/mach-omap2/board-flash.h @@ -26,3 +26,5 @@ struct flash_partitions { extern void board_flash_init(struct flash_partitions [], char chip_sel[][GPMC_CS_NUM]); +extern void board_nand_init(struct mtd_partition *nand_parts, + u8 nr_parts, u8 cs); diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 69064b1c6a75..b1c2c9a11c38 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -48,10 +48,22 @@ static void __init omap_generic_init(void) static void __init omap_generic_map_io(void) { - omap2_set_globals_242x(); /* should be 242x, 243x, or 343x */ - omap242x_map_common_io(); + if (cpu_is_omap242x()) { + omap2_set_globals_242x(); + omap242x_map_common_io(); + } else if (cpu_is_omap243x()) { + omap2_set_globals_243x(); + omap243x_map_common_io(); + } else if (cpu_is_omap34xx()) { + omap2_set_globals_3xxx(); + omap34xx_map_common_io(); + } else if (cpu_is_omap44xx()) { + omap2_set_globals_443x(); + omap44xx_map_common_io(); + } } +/* XXX This machine entry name should be updated */ MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx") /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */ .boot_params = 0x80000100, diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index cc39fc866524..929993b4bf26 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c @@ -31,7 +31,6 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/control.h> #include <mach/gpio.h> #include <plat/usb.h> #include <plat/board.h> @@ -42,6 +41,7 @@ #include <plat/gpmc.h> #include "mux.h" +#include "control.h" #define H4_FLASH_CS 0 #define H4_SMC91X_CS 1 diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index b62a68ba069b..5e035a58b809 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -20,6 +20,7 @@ #include <linux/regulator/machine.h> #include <linux/i2c/twl.h> +#include <linux/mmc/host.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -38,12 +39,61 @@ #define IGEP2_SMSC911X_CS 5 #define IGEP2_SMSC911X_GPIO 176 #define IGEP2_GPIO_USBH_NRESET 24 -#define IGEP2_GPIO_LED0_GREEN 26 -#define IGEP2_GPIO_LED0_RED 27 -#define IGEP2_GPIO_LED1_RED 28 -#define IGEP2_GPIO_DVI_PUP 170 -#define IGEP2_GPIO_WIFI_NPD 94 -#define IGEP2_GPIO_WIFI_NRESET 95 +#define IGEP2_GPIO_LED0_GREEN 26 +#define IGEP2_GPIO_LED0_RED 27 +#define IGEP2_GPIO_LED1_RED 28 +#define IGEP2_GPIO_DVI_PUP 170 + +#define IGEP2_RB_GPIO_WIFI_NPD 94 +#define IGEP2_RB_GPIO_WIFI_NRESET 95 +#define IGEP2_RB_GPIO_BT_NRESET 137 +#define IGEP2_RC_GPIO_WIFI_NPD 138 +#define IGEP2_RC_GPIO_WIFI_NRESET 139 +#define IGEP2_RC_GPIO_BT_NRESET 137 + +/* + * IGEP2 Hardware Revision Table + * + * -------------------------------------------------------------------------- + * | Id. | Hw Rev. | HW0 (28) | WIFI_NPD | WIFI_NRESET | BT_NRESET | + * -------------------------------------------------------------------------- + * | 0 | B | high | gpio94 | gpio95 | - | + * | 0 | B/C (B-compatible) | high | gpio94 | gpio95 | gpio137 | + * | 1 | C | low | gpio138 | gpio139 | gpio137 | + * -------------------------------------------------------------------------- + */ + +#define IGEP2_BOARD_HWREV_B 0 +#define IGEP2_BOARD_HWREV_C 1 + +static u8 hwrev; + +static void __init igep2_get_revision(void) +{ + u8 ret; + + omap_mux_init_gpio(IGEP2_GPIO_LED1_RED, OMAP_PIN_INPUT); + + if ((gpio_request(IGEP2_GPIO_LED1_RED, "GPIO_HW0_REV") == 0) && + (gpio_direction_input(IGEP2_GPIO_LED1_RED) == 0)) { + ret = gpio_get_value(IGEP2_GPIO_LED1_RED); + if (ret == 0) { + pr_info("IGEP2: Hardware Revision C (B-NON compatible)\n"); + hwrev = IGEP2_BOARD_HWREV_C; + } else if (ret == 1) { + pr_info("IGEP2: Hardware Revision B/C (B compatible)\n"); + hwrev = IGEP2_BOARD_HWREV_B; + } else { + pr_err("IGEP2: Unknown Hardware Revision\n"); + hwrev = -1; + } + } else { + pr_warning("IGEP2: Could not obtain gpio GPIO_HW0_REV\n"); + pr_err("IGEP2: Unknown Hardware Revision\n"); + } + + gpio_free(IGEP2_GPIO_LED1_RED); +} #if defined(CONFIG_MTD_ONENAND_OMAP2) || \ defined(CONFIG_MTD_ONENAND_OMAP2_MODULE) @@ -107,7 +157,7 @@ static struct platform_device igep2_onenand_device = { }, }; -void __init igep2_flash_init(void) +static void __init igep2_flash_init(void) { u8 cs = 0; u8 onenandcs = GPMC_CS_NUM + 1; @@ -141,7 +191,7 @@ void __init igep2_flash_init(void) } #else -void __init igep2_flash_init(void) {} +static void __init igep2_flash_init(void) {} #endif #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) @@ -211,10 +261,6 @@ static struct regulator_consumer_supply igep2_vmmc1_supply = { .supply = "vmmc", }; -static struct regulator_consumer_supply igep2_vmmc2_supply = { - .supply = "vmmc", -}; - /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ static struct regulator_init_data igep2_vmmc1 = { .constraints = { @@ -230,37 +276,95 @@ static struct regulator_init_data igep2_vmmc1 = { .consumer_supplies = &igep2_vmmc1_supply, }; -/* VMMC2 for OMAP VDD_MMC2 (i/o) and MMC2 WIFI */ -static struct regulator_init_data igep2_vmmc2 = { - .constraints = { - .min_uV = 1850000, - .max_uV = 3150000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &igep2_vmmc2_supply, -}; - static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, - .wires = 4, + .caps = MMC_CAP_4_BIT_DATA, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, }, +#if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE) { .mmc = 2, - .wires = 4, + .caps = MMC_CAP_4_BIT_DATA, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, }, +#endif {} /* Terminator */ }; +#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) +#include <linux/leds.h> + +static struct gpio_led igep2_gpio_leds[] = { + [0] = { + .name = "gpio-led:red:d0", + .gpio = IGEP2_GPIO_LED0_RED, + .default_trigger = "default-off" + }, + [1] = { + .name = "gpio-led:green:d0", + .gpio = IGEP2_GPIO_LED0_GREEN, + .default_trigger = "default-off", + }, + [2] = { + .name = "gpio-led:red:d1", + .gpio = IGEP2_GPIO_LED1_RED, + .default_trigger = "default-off", + }, + [3] = { + .name = "gpio-led:green:d1", + .default_trigger = "heartbeat", + .gpio = -EINVAL, /* gets replaced */ + }, +}; + +static struct gpio_led_platform_data igep2_led_pdata = { + .leds = igep2_gpio_leds, + .num_leds = ARRAY_SIZE(igep2_gpio_leds), +}; + +static struct platform_device igep2_led_device = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &igep2_led_pdata, + }, +}; + +static void __init igep2_leds_init(void) +{ + platform_device_register(&igep2_led_device); +} + +#else +static inline void igep2_leds_init(void) +{ + if ((gpio_request(IGEP2_GPIO_LED0_RED, "gpio-led:red:d0") == 0) && + (gpio_direction_output(IGEP2_GPIO_LED0_RED, 1) == 0)) { + gpio_export(IGEP2_GPIO_LED0_RED, 0); + gpio_set_value(IGEP2_GPIO_LED0_RED, 0); + } else + pr_warning("IGEP v2: Could not obtain gpio GPIO_LED0_RED\n"); + + if ((gpio_request(IGEP2_GPIO_LED0_GREEN, "gpio-led:green:d0") == 0) && + (gpio_direction_output(IGEP2_GPIO_LED0_GREEN, 1) == 0)) { + gpio_export(IGEP2_GPIO_LED0_GREEN, 0); + gpio_set_value(IGEP2_GPIO_LED0_GREEN, 0); + } else + pr_warning("IGEP v2: Could not obtain gpio GPIO_LED0_GREEN\n"); + + if ((gpio_request(IGEP2_GPIO_LED1_RED, "gpio-led:red:d1") == 0) && + (gpio_direction_output(IGEP2_GPIO_LED1_RED, 1) == 0)) { + gpio_export(IGEP2_GPIO_LED1_RED, 0); + gpio_set_value(IGEP2_GPIO_LED1_RED, 0); + } else + pr_warning("IGEP v2: Could not obtain gpio GPIO_LED1_RED\n"); + +} +#endif + static int igep2_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio) { @@ -268,20 +372,48 @@ static int igep2_twl_gpio_setup(struct device *dev, mmc[0].gpio_cd = gpio + 0; omap2_hsmmc_init(mmc); - /* link regulators to MMC adapters ... we "know" the + /* + * link regulators to MMC adapters ... we "know" the * regulators will be set up only *after* we return. - */ + */ igep2_vmmc1_supply.dev = mmc[0].dev; - igep2_vmmc2_supply.dev = mmc[1].dev; + + /* + * REVISIT: need ehci-omap hooks for external VBUS + * power switch and overcurrent detect + */ + if ((gpio_request(gpio + 1, "GPIO_EHCI_NOC") < 0) || + (gpio_direction_input(gpio + 1) < 0)) + pr_err("IGEP2: Could not obtain gpio for EHCI NOC"); + + /* + * TWL4030_GPIO_MAX + 0 == ledA, GPIO_USBH_CPEN + * (out, active low) + */ + if ((gpio_request(gpio + TWL4030_GPIO_MAX, "GPIO_USBH_CPEN") < 0) || + (gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0) < 0)) + pr_err("IGEP2: Could not obtain gpio for USBH_CPEN"); + + /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */ +#if !defined(CONFIG_LEDS_GPIO) && !defined(CONFIG_LEDS_GPIO_MODULE) + if ((gpio_request(gpio+TWL4030_GPIO_MAX+1, "gpio-led:green:d1") == 0) + && (gpio_direction_output(gpio + TWL4030_GPIO_MAX + 1, 1) == 0)) { + gpio_export(gpio + TWL4030_GPIO_MAX + 1, 0); + gpio_set_value(gpio + TWL4030_GPIO_MAX + 1, 0); + } else + pr_warning("IGEP v2: Could not obtain gpio GPIO_LED1_GREEN\n"); +#else + igep2_gpio_leds[3].gpio = gpio + TWL4030_GPIO_MAX + 1; +#endif return 0; }; -static struct twl4030_gpio_platform_data igep2_gpio_data = { +static struct twl4030_gpio_platform_data igep2_twl4030_gpio_pdata = { .gpio_base = OMAP_MAX_GPIO_LINES, .irq_base = TWL4030_GPIO_IRQ_BASE, .irq_end = TWL4030_GPIO_IRQ_END, - .use_leds = false, + .use_leds = true, .setup = igep2_twl_gpio_setup, }; @@ -355,47 +487,6 @@ static void __init igep2_display_init(void) pr_err("IGEP v2: Could not obtain gpio GPIO_DVI_PUP\n"); } -#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) -#include <linux/leds.h> - -static struct gpio_led igep2_gpio_leds[] = { - { - .name = "led0:red", - .gpio = IGEP2_GPIO_LED0_RED, - }, - { - .name = "led0:green", - .default_trigger = "heartbeat", - .gpio = IGEP2_GPIO_LED0_GREEN, - }, - { - .name = "led1:red", - .gpio = IGEP2_GPIO_LED1_RED, - }, -}; - -static struct gpio_led_platform_data igep2_led_pdata = { - .leds = igep2_gpio_leds, - .num_leds = ARRAY_SIZE(igep2_gpio_leds), -}; - -static struct platform_device igep2_led_device = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &igep2_led_pdata, - }, -}; - -static void __init igep2_init_led(void) -{ - platform_device_register(&igep2_led_device); -} - -#else -static inline void igep2_init_led(void) {} -#endif - static struct platform_device *igep2_devices[] __initdata = { &igep2_dss_device, }; @@ -425,14 +516,13 @@ static struct twl4030_platform_data igep2_twldata = { /* platform_data for children goes here */ .usb = &igep2_usb_data, .codec = &igep2_codec_data, - .gpio = &igep2_gpio_data, + .gpio = &igep2_twl4030_gpio_pdata, .vmmc1 = &igep2_vmmc1, - .vmmc2 = &igep2_vmmc2, .vpll2 = &igep2_vpll2, }; -static struct i2c_board_info __initdata igep2_i2c_boardinfo[] = { +static struct i2c_board_info __initdata igep2_i2c1_boardinfo[] = { { I2C_BOARD_INFO("twl4030", 0x48), .flags = I2C_CLIENT_WAKE, @@ -441,14 +531,29 @@ static struct i2c_board_info __initdata igep2_i2c_boardinfo[] = { }, }; -static int __init igep2_i2c_init(void) +static struct i2c_board_info __initdata igep2_i2c3_boardinfo[] = { + { + I2C_BOARD_INFO("eeprom", 0x50), + }, +}; + +static void __init igep2_i2c_init(void) { - omap_register_i2c_bus(1, 2600, igep2_i2c_boardinfo, - ARRAY_SIZE(igep2_i2c_boardinfo)); - /* Bus 3 is attached to the DVI port where devices like the pico DLP - * projector don't work reliably with 400kHz */ - omap_register_i2c_bus(3, 100, NULL, 0); - return 0; + int ret; + + ret = omap_register_i2c_bus(1, 2600, igep2_i2c1_boardinfo, + ARRAY_SIZE(igep2_i2c1_boardinfo)); + if (ret) + pr_warning("IGEP2: Could not register I2C1 bus (%d)\n", ret); + + /* + * Bus 3 is attached to the DVI port where devices like the pico DLP + * projector don't work reliably with 400kHz + */ + ret = omap_register_i2c_bus(3, 100, igep2_i2c3_boardinfo, + ARRAY_SIZE(igep2_i2c3_boardinfo)); + if (ret) + pr_warning("IGEP2: Could not register I2C3 bus (%d)\n", ret); } static struct omap_musb_board_data musb_board_data = { @@ -476,9 +581,57 @@ static struct omap_board_mux board_mux[] __initdata = { #define board_mux NULL #endif +#if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE) + +static void __init igep2_wlan_bt_init(void) +{ + unsigned npd, wreset, btreset; + + /* GPIO's for WLAN-BT combo depends on hardware revision */ + if (hwrev == IGEP2_BOARD_HWREV_B) { + npd = IGEP2_RB_GPIO_WIFI_NPD; + wreset = IGEP2_RB_GPIO_WIFI_NRESET; + btreset = IGEP2_RB_GPIO_BT_NRESET; + } else if (hwrev == IGEP2_BOARD_HWREV_C) { + npd = IGEP2_RC_GPIO_WIFI_NPD; + wreset = IGEP2_RC_GPIO_WIFI_NRESET; + btreset = IGEP2_RC_GPIO_BT_NRESET; + } else + return; + + /* Set GPIO's for WLAN-BT combo module */ + if ((gpio_request(npd, "GPIO_WIFI_NPD") == 0) && + (gpio_direction_output(npd, 1) == 0)) { + gpio_export(npd, 0); + } else + pr_warning("IGEP2: Could not obtain gpio GPIO_WIFI_NPD\n"); + + if ((gpio_request(wreset, "GPIO_WIFI_NRESET") == 0) && + (gpio_direction_output(wreset, 1) == 0)) { + gpio_export(wreset, 0); + gpio_set_value(wreset, 0); + udelay(10); + gpio_set_value(wreset, 1); + } else + pr_warning("IGEP2: Could not obtain gpio GPIO_WIFI_NRESET\n"); + + if ((gpio_request(btreset, "GPIO_BT_NRESET") == 0) && + (gpio_direction_output(btreset, 1) == 0)) { + gpio_export(btreset, 0); + } else + pr_warning("IGEP2: Could not obtain gpio GPIO_BT_NRESET\n"); +} +#else +static inline void __init igep2_wlan_bt_init(void) { } +#endif + static void __init igep2_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); + + /* Get IGEP2 hardware revision */ + igep2_get_revision(); + /* Register I2C busses and drivers */ igep2_i2c_init(); platform_add_devices(igep2_devices, ARRAY_SIZE(igep2_devices)); omap_serial_init(); @@ -486,50 +639,16 @@ static void __init igep2_init(void) usb_ehci_init(&ehci_pdata); igep2_flash_init(); - igep2_init_led(); + igep2_leds_init(); igep2_display_init(); igep2_init_smsc911x(); - /* GPIO userspace leds */ -#if !defined(CONFIG_LEDS_GPIO) && !defined(CONFIG_LEDS_GPIO_MODULE) - if ((gpio_request(IGEP2_GPIO_LED0_RED, "led0:red") == 0) && - (gpio_direction_output(IGEP2_GPIO_LED0_RED, 1) == 0)) { - gpio_export(IGEP2_GPIO_LED0_RED, 0); - gpio_set_value(IGEP2_GPIO_LED0_RED, 0); - } else - pr_warning("IGEP v2: Could not obtain gpio GPIO_LED0_RED\n"); - - if ((gpio_request(IGEP2_GPIO_LED0_GREEN, "led0:green") == 0) && - (gpio_direction_output(IGEP2_GPIO_LED0_GREEN, 1) == 0)) { - gpio_export(IGEP2_GPIO_LED0_GREEN, 0); - gpio_set_value(IGEP2_GPIO_LED0_GREEN, 0); - } else - pr_warning("IGEP v2: Could not obtain gpio GPIO_LED0_GREEN\n"); - - if ((gpio_request(IGEP2_GPIO_LED1_RED, "led1:red") == 0) && - (gpio_direction_output(IGEP2_GPIO_LED1_RED, 1) == 0)) { - gpio_export(IGEP2_GPIO_LED1_RED, 0); - gpio_set_value(IGEP2_GPIO_LED1_RED, 0); - } else - pr_warning("IGEP v2: Could not obtain gpio GPIO_LED1_RED\n"); -#endif - - /* GPIO W-LAN + Bluetooth combo module */ - if ((gpio_request(IGEP2_GPIO_WIFI_NPD, "GPIO_WIFI_NPD") == 0) && - (gpio_direction_output(IGEP2_GPIO_WIFI_NPD, 1) == 0)) { - gpio_export(IGEP2_GPIO_WIFI_NPD, 0); -/* gpio_set_value(IGEP2_GPIO_WIFI_NPD, 0); */ - } else - pr_warning("IGEP v2: Could not obtain gpio GPIO_WIFI_NPD\n"); + /* + * WLAN-BT combo module from MuRata wich has a Marvell WLAN + * (88W8686) + CSR Bluetooth chipset. Uses SDIO interface. + */ + igep2_wlan_bt_init(); - if ((gpio_request(IGEP2_GPIO_WIFI_NRESET, "GPIO_WIFI_NRESET") == 0) && - (gpio_direction_output(IGEP2_GPIO_WIFI_NRESET, 1) == 0)) { - gpio_export(IGEP2_GPIO_WIFI_NRESET, 0); - gpio_set_value(IGEP2_GPIO_WIFI_NRESET, 0); - udelay(10); - gpio_set_value(IGEP2_GPIO_WIFI_NRESET, 1); - } else - pr_warning("IGEP v2: Could not obtain gpio GPIO_WIFI_NRESET\n"); } MACHINE_START(IGEP0020, "IGEP v2 board") diff --git a/arch/arm/mach-omap2/board-igep0030.c b/arch/arm/mach-omap2/board-igep0030.c new file mode 100644 index 000000000000..22b0b253e16b --- /dev/null +++ b/arch/arm/mach-omap2/board-igep0030.c @@ -0,0 +1,400 @@ +/* + * Copyright (C) 2010 - ISEE 2007 SL + * + * Modified from mach-omap2/board-generic.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/gpio.h> +#include <linux/interrupt.h> + +#include <linux/regulator/machine.h> +#include <linux/i2c/twl.h> +#include <linux/mmc/host.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +#include <plat/board.h> +#include <plat/common.h> +#include <plat/gpmc.h> +#include <plat/usb.h> +#include <plat/onenand.h> + +#include "mux.h" +#include "hsmmc.h" +#include "sdram-numonyx-m65kxxxxam.h" + +#define IGEP3_GPIO_LED0_GREEN 54 +#define IGEP3_GPIO_LED0_RED 53 +#define IGEP3_GPIO_LED1_RED 16 + +#define IGEP3_GPIO_WIFI_NPD 138 +#define IGEP3_GPIO_WIFI_NRESET 139 +#define IGEP3_GPIO_BT_NRESET 137 + +#define IGEP3_GPIO_USBH_NRESET 115 + + +#if defined(CONFIG_MTD_ONENAND_OMAP2) || \ + defined(CONFIG_MTD_ONENAND_OMAP2_MODULE) + +#define ONENAND_MAP 0x20000000 + +/* + * x2 Flash built-in COMBO POP MEMORY + * Since the device is equipped with two DataRAMs, and two-plane NAND + * Flash memory array, these two component enables simultaneous program + * of 4KiB. Plane1 has only even blocks such as block0, block2, block4 + * while Plane2 has only odd blocks such as block1, block3, block5. + * So MTD regards it as 4KiB page size and 256KiB block size 64*(2*2048) + */ + +static struct mtd_partition igep3_onenand_partitions[] = { + { + .name = "X-Loader", + .offset = 0, + .size = 2 * (64*(2*2048)) + }, + { + .name = "U-Boot", + .offset = MTDPART_OFS_APPEND, + .size = 6 * (64*(2*2048)), + }, + { + .name = "Environment", + .offset = MTDPART_OFS_APPEND, + .size = 2 * (64*(2*2048)), + }, + { + .name = "Kernel", + .offset = MTDPART_OFS_APPEND, + .size = 12 * (64*(2*2048)), + }, + { + .name = "File System", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct omap_onenand_platform_data igep3_onenand_pdata = { + .parts = igep3_onenand_partitions, + .nr_parts = ARRAY_SIZE(igep3_onenand_partitions), + .onenand_setup = NULL, + .dma_channel = -1, /* disable DMA in OMAP OneNAND driver */ +}; + +static struct platform_device igep3_onenand_device = { + .name = "omap2-onenand", + .id = -1, + .dev = { + .platform_data = &igep3_onenand_pdata, + }, +}; + +void __init igep3_flash_init(void) +{ + u8 cs = 0; + u8 onenandcs = GPMC_CS_NUM + 1; + + for (cs = 0; cs < GPMC_CS_NUM; cs++) { + u32 ret; + ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); + + /* Check if NAND/oneNAND is configured */ + if ((ret & 0xC00) == 0x800) + /* NAND found */ + pr_err("IGEP3: Unsupported NAND found\n"); + else { + ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); + + if ((ret & 0x3F) == (ONENAND_MAP >> 24)) + /* OneNAND found */ + onenandcs = cs; + } + } + + if (onenandcs > GPMC_CS_NUM) { + pr_err("IGEP3: Unable to find configuration in GPMC\n"); + return; + } + + igep3_onenand_pdata.cs = onenandcs; + + if (platform_device_register(&igep3_onenand_device) < 0) + pr_err("IGEP3: Unable to register OneNAND device\n"); +} + +#else +void __init igep3_flash_init(void) {} +#endif + +static struct regulator_consumer_supply igep3_vmmc1_supply = { + .supply = "vmmc", +}; + +/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ +static struct regulator_init_data igep3_vmmc1 = { + .constraints = { + .min_uV = 1850000, + .max_uV = 3150000, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &igep3_vmmc1_supply, +}; + +static struct omap2_hsmmc_info mmc[] = { + [0] = { + .mmc = 1, + .caps = MMC_CAP_4_BIT_DATA, + .gpio_cd = -EINVAL, + .gpio_wp = -EINVAL, + }, +#if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE) + [1] = { + .mmc = 2, + .caps = MMC_CAP_4_BIT_DATA, + .gpio_cd = -EINVAL, + .gpio_wp = -EINVAL, + }, +#endif + {} /* Terminator */ +}; + +#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) +#include <linux/leds.h> + +static struct gpio_led igep3_gpio_leds[] = { + [0] = { + .name = "gpio-led:red:d0", + .gpio = IGEP3_GPIO_LED0_RED, + .default_trigger = "default-off" + }, + [1] = { + .name = "gpio-led:green:d0", + .gpio = IGEP3_GPIO_LED0_GREEN, + .default_trigger = "default-off", + }, + [2] = { + .name = "gpio-led:red:d1", + .gpio = IGEP3_GPIO_LED1_RED, + .default_trigger = "default-off", + }, + [3] = { + .name = "gpio-led:green:d1", + .default_trigger = "heartbeat", + .gpio = -EINVAL, /* gets replaced */ + }, +}; + +static struct gpio_led_platform_data igep3_led_pdata = { + .leds = igep3_gpio_leds, + .num_leds = ARRAY_SIZE(igep3_gpio_leds), +}; + +static struct platform_device igep3_led_device = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &igep3_led_pdata, + }, +}; + +static void __init igep3_leds_init(void) +{ + platform_device_register(&igep3_led_device); +} + +#else +static inline void igep3_leds_init(void) +{ + if ((gpio_request(IGEP3_GPIO_LED0_RED, "gpio-led:red:d0") == 0) && + (gpio_direction_output(IGEP3_GPIO_LED0_RED, 1) == 0)) { + gpio_export(IGEP3_GPIO_LED0_RED, 0); + gpio_set_value(IGEP3_GPIO_LED0_RED, 1); + } else + pr_warning("IGEP3: Could not obtain gpio GPIO_LED0_RED\n"); + + if ((gpio_request(IGEP3_GPIO_LED0_GREEN, "gpio-led:green:d0") == 0) && + (gpio_direction_output(IGEP3_GPIO_LED0_GREEN, 1) == 0)) { + gpio_export(IGEP3_GPIO_LED0_GREEN, 0); + gpio_set_value(IGEP3_GPIO_LED0_GREEN, 1); + } else + pr_warning("IGEP3: Could not obtain gpio GPIO_LED0_GREEN\n"); + + if ((gpio_request(IGEP3_GPIO_LED1_RED, "gpio-led:red:d1") == 0) && + (gpio_direction_output(IGEP3_GPIO_LED1_RED, 1) == 0)) { + gpio_export(IGEP3_GPIO_LED1_RED, 0); + gpio_set_value(IGEP3_GPIO_LED1_RED, 1); + } else + pr_warning("IGEP3: Could not obtain gpio GPIO_LED1_RED\n"); +} +#endif + +static int igep3_twl4030_gpio_setup(struct device *dev, + unsigned gpio, unsigned ngpio) +{ + /* gpio + 0 is "mmc0_cd" (input/IRQ) */ + mmc[0].gpio_cd = gpio + 0; + omap2_hsmmc_init(mmc); + + /* + * link regulators to MMC adapters ... we "know" the + * regulators will be set up only *after* we return. + */ + igep3_vmmc1_supply.dev = mmc[0].dev; + + /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */ +#if !defined(CONFIG_LEDS_GPIO) && !defined(CONFIG_LEDS_GPIO_MODULE) + if ((gpio_request(gpio+TWL4030_GPIO_MAX+1, "gpio-led:green:d1") == 0) + && (gpio_direction_output(gpio + TWL4030_GPIO_MAX + 1, 1) == 0)) { + gpio_export(gpio + TWL4030_GPIO_MAX + 1, 0); + gpio_set_value(gpio + TWL4030_GPIO_MAX + 1, 0); + } else + pr_warning("IGEP3: Could not obtain gpio GPIO_LED1_GREEN\n"); +#else + igep3_gpio_leds[3].gpio = gpio + TWL4030_GPIO_MAX + 1; +#endif + + return 0; +}; + +static struct twl4030_gpio_platform_data igep3_twl4030_gpio_pdata = { + .gpio_base = OMAP_MAX_GPIO_LINES, + .irq_base = TWL4030_GPIO_IRQ_BASE, + .irq_end = TWL4030_GPIO_IRQ_END, + .use_leds = true, + .setup = igep3_twl4030_gpio_setup, +}; + +static struct twl4030_usb_data igep3_twl4030_usb_data = { + .usb_mode = T2_USB_MODE_ULPI, +}; + +static void __init igep3_init_irq(void) +{ + omap2_init_common_hw(m65kxxxxam_sdrc_params, m65kxxxxam_sdrc_params); + omap_init_irq(); + omap_gpio_init(); +} + +static struct twl4030_platform_data igep3_twl4030_pdata = { + .irq_base = TWL4030_IRQ_BASE, + .irq_end = TWL4030_IRQ_END, + + /* platform_data for children goes here */ + .usb = &igep3_twl4030_usb_data, + .gpio = &igep3_twl4030_gpio_pdata, + .vmmc1 = &igep3_vmmc1, +}; + +static struct i2c_board_info __initdata igep3_i2c_boardinfo[] = { + { + I2C_BOARD_INFO("twl4030", 0x48), + .flags = I2C_CLIENT_WAKE, + .irq = INT_34XX_SYS_NIRQ, + .platform_data = &igep3_twl4030_pdata, + }, +}; + +static int __init igep3_i2c_init(void) +{ + omap_register_i2c_bus(1, 2600, igep3_i2c_boardinfo, + ARRAY_SIZE(igep3_i2c_boardinfo)); + + return 0; +} + +static struct omap_musb_board_data musb_board_data = { + .interface_type = MUSB_INTERFACE_ULPI, + .mode = MUSB_OTG, + .power = 100, +}; + +#if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE) + +static void __init igep3_wifi_bt_init(void) +{ + /* Configure MUX values for W-LAN + Bluetooth GPIO's */ + omap_mux_init_gpio(IGEP3_GPIO_WIFI_NPD, OMAP_PIN_OUTPUT); + omap_mux_init_gpio(IGEP3_GPIO_WIFI_NRESET, OMAP_PIN_OUTPUT); + omap_mux_init_gpio(IGEP3_GPIO_BT_NRESET, OMAP_PIN_OUTPUT); + + /* Set GPIO's for W-LAN + Bluetooth combo module */ + if ((gpio_request(IGEP3_GPIO_WIFI_NPD, "GPIO_WIFI_NPD") == 0) && + (gpio_direction_output(IGEP3_GPIO_WIFI_NPD, 1) == 0)) { + gpio_export(IGEP3_GPIO_WIFI_NPD, 0); + } else + pr_warning("IGEP3: Could not obtain gpio GPIO_WIFI_NPD\n"); + + if ((gpio_request(IGEP3_GPIO_WIFI_NRESET, "GPIO_WIFI_NRESET") == 0) && + (gpio_direction_output(IGEP3_GPIO_WIFI_NRESET, 1) == 0)) { + gpio_export(IGEP3_GPIO_WIFI_NRESET, 0); + gpio_set_value(IGEP3_GPIO_WIFI_NRESET, 0); + udelay(10); + gpio_set_value(IGEP3_GPIO_WIFI_NRESET, 1); + } else + pr_warning("IGEP3: Could not obtain gpio GPIO_WIFI_NRESET\n"); + + if ((gpio_request(IGEP3_GPIO_BT_NRESET, "GPIO_BT_NRESET") == 0) && + (gpio_direction_output(IGEP3_GPIO_BT_NRESET, 1) == 0)) { + gpio_export(IGEP3_GPIO_BT_NRESET, 0); + } else + pr_warning("IGEP3: Could not obtain gpio GPIO_BT_NRESET\n"); +} +#else +void __init igep3_wifi_bt_init(void) {} +#endif + +#ifdef CONFIG_OMAP_MUX +static struct omap_board_mux board_mux[] __initdata = { + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; +#else +#define board_mux NULL +#endif + +static void __init igep3_init(void) +{ + omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); + + /* Register I2C busses and drivers */ + igep3_i2c_init(); + + omap_serial_init(); + usb_musb_init(&musb_board_data); + + igep3_flash_init(); + igep3_leds_init(); + + /* + * WLAN-BT combo module from MuRata wich has a Marvell WLAN + * (88W8686) + CSR Bluetooth chipset. Uses SDIO interface. + */ + igep3_wifi_bt_init(); + +} + +MACHINE_START(IGEP0030, "IGEP OMAP3 module") + .boot_params = 0x80000100, + .map_io = omap3_map_io, + .init_irq = igep3_init_irq, + .init_machine = igep3_init, + .timer = &omap_timer, +MACHINE_END diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index f28fd77bceb3..001fd9713f39 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c @@ -27,6 +27,7 @@ #include <linux/i2c/twl.h> #include <linux/io.h> #include <linux/smsc911x.h> +#include <linux/mmc/host.h> #include <mach/hardware.h> #include <asm/mach-types.h> @@ -41,11 +42,12 @@ #include <mach/board-zoom.h> #include <asm/delay.h> -#include <plat/control.h> #include <plat/usb.h> +#include "board-flash.h" #include "mux.h" #include "hsmmc.h" +#include "control.h" #define LDP_SMSC911X_CS 1 #define LDP_SMSC911X_GPIO 152 @@ -82,7 +84,7 @@ static struct platform_device ldp_smsc911x_device = { }, }; -static int board_keymap[] = { +static uint32_t board_keymap[] = { KEY(0, 0, KEY_1), KEY(1, 0, KEY_2), KEY(2, 0, KEY_3), @@ -362,7 +364,7 @@ static int __init omap_i2c_init(void) static struct omap2_hsmmc_info mmc[] __initdata = { { .mmc = 1, - .wires = 4, + .caps = MMC_CAP_4_BIT_DATA, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, }, diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c index 3f7966873507..e823c7042ab3 100644 --- a/arch/arm/mach-omap2/board-n8x0.c +++ b/arch/arm/mach-omap2/board-n8x0.c @@ -20,6 +20,7 @@ #include <linux/i2c.h> #include <linux/spi/spi.h> #include <linux/usb/musb.h> +#include <sound/tlv320aic3x.h> #include <asm/mach/arch.h> #include <asm/mach-types.h> @@ -383,15 +384,6 @@ static void n8x0_mmc_callback(void *data, u8 card_mask) omap_mmc_notify_cover_event(mmc_device, index, *openp); } -void n8x0_mmc_slot1_cover_handler(void *arg, int closed_state) -{ - if (mmc_device == NULL) - return; - - slot1_cover_open = !closed_state; - omap_mmc_notify_cover_event(mmc_device, 0, closed_state); -} - static int n8x0_mmc_late_init(struct device *dev) { int r, bit, *openp; @@ -511,7 +503,7 @@ static struct omap_mmc_platform_data mmc1_data = { static struct omap_mmc_platform_data *mmc_data[OMAP24XX_NR_MMC]; -void __init n8x0_mmc_init(void) +static void __init n8x0_mmc_init(void) { int err; @@ -560,11 +552,6 @@ void __init n8x0_mmc_init(void) void __init n8x0_mmc_init(void) { } - -void n8x0_mmc_slot1_cover_handler(void *arg, int state) -{ -} - #endif /* CONFIG_MMC_OMAP */ #ifdef CONFIG_MENELAUS @@ -614,29 +601,35 @@ static int n8x0_menelaus_late_init(struct device *dev) return 0; } -static struct i2c_board_info __initdata n8x0_i2c_board_info_1[] = { +#else +static int n8x0_menelaus_late_init(struct device *dev) +{ + return 0; +} +#endif + +static struct menelaus_platform_data n8x0_menelaus_platform_data __initdata = { + .late_init = n8x0_menelaus_late_init, +}; + +static struct i2c_board_info __initdata n8x0_i2c_board_info_1[] __initdata = { { I2C_BOARD_INFO("menelaus", 0x72), .irq = INT_24XX_SYS_NIRQ, + .platform_data = &n8x0_menelaus_platform_data, }, }; -static struct menelaus_platform_data n8x0_menelaus_platform_data = { - .late_init = n8x0_menelaus_late_init, +static struct aic3x_pdata n810_aic33_data __initdata = { + .gpio_reset = 118, }; -static void __init n8x0_menelaus_init(void) -{ - n8x0_i2c_board_info_1[0].platform_data = &n8x0_menelaus_platform_data; - omap_register_i2c_bus(1, 400, n8x0_i2c_board_info_1, - ARRAY_SIZE(n8x0_i2c_board_info_1)); -} - -#else -static inline void __init n8x0_menelaus_init(void) -{ -} -#endif +static struct i2c_board_info n810_i2c_board_info_2[] __initdata = { + { + I2C_BOARD_INFO("tlv320aic3x", 0x18), + .platform_data = &n810_aic33_data, + }, +}; static void __init n8x0_map_io(void) { @@ -653,6 +646,11 @@ static void __init n8x0_init_irq(void) #ifdef CONFIG_OMAP_MUX static struct omap_board_mux board_mux[] __initdata = { + /* I2S codec port pins for McBSP block */ + OMAP2420_MUX(EAC_AC_SCLK, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), + OMAP2420_MUX(EAC_AC_FS, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), + OMAP2420_MUX(EAC_AC_DIN, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), + OMAP2420_MUX(EAC_AC_DOUT, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT), { .reg_offset = OMAP_MUX_TERMINATOR }, }; #else @@ -665,9 +663,14 @@ static void __init n8x0_init_machine(void) /* FIXME: add n810 spi devices */ spi_register_board_info(n800_spi_board_info, ARRAY_SIZE(n800_spi_board_info)); + omap_register_i2c_bus(1, 400, n8x0_i2c_board_info_1, + ARRAY_SIZE(n8x0_i2c_board_info_1)); + omap_register_i2c_bus(2, 400, NULL, 0); + if (machine_is_nokia_n810()) + i2c_register_board_info(2, n810_i2c_board_info_2, + ARRAY_SIZE(n810_i2c_board_info_2)); omap_serial_init(); - n8x0_menelaus_init(); n8x0_onenand_init(); n8x0_mmc_init(); n8x0_usb_init(); diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 9d9f5b881ee8..14f42240ae79 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -27,6 +27,7 @@ #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> #include <linux/mtd/nand.h> +#include <linux/mmc/host.h> #include <linux/regulator/machine.h> #include <linux/i2c/twl.h> @@ -43,13 +44,100 @@ #include <plat/gpmc.h> #include <plat/nand.h> #include <plat/usb.h> -#include <plat/timer-gp.h> #include "mux.h" #include "hsmmc.h" +#include "timer-gp.h" #define NAND_BLOCK_SIZE SZ_128K +/* + * OMAP3 Beagle revision + * Run time detection of Beagle revision is done by reading GPIO. + * GPIO ID - + * AXBX = GPIO173, GPIO172, GPIO171: 1 1 1 + * C1_3 = GPIO173, GPIO172, GPIO171: 1 1 0 + * C4 = GPIO173, GPIO172, GPIO171: 1 0 1 + * XM = GPIO173, GPIO172, GPIO171: 0 0 0 + */ +enum { + OMAP3BEAGLE_BOARD_UNKN = 0, + OMAP3BEAGLE_BOARD_AXBX, + OMAP3BEAGLE_BOARD_C1_3, + OMAP3BEAGLE_BOARD_C4, + OMAP3BEAGLE_BOARD_XM, +}; + +static u8 omap3_beagle_version; + +static u8 omap3_beagle_get_rev(void) +{ + return omap3_beagle_version; +} + +static void __init omap3_beagle_init_rev(void) +{ + int ret; + u16 beagle_rev = 0; + + omap_mux_init_gpio(171, OMAP_PIN_INPUT_PULLUP); + omap_mux_init_gpio(172, OMAP_PIN_INPUT_PULLUP); + omap_mux_init_gpio(173, OMAP_PIN_INPUT_PULLUP); + + ret = gpio_request(171, "rev_id_0"); + if (ret < 0) + goto fail0; + + ret = gpio_request(172, "rev_id_1"); + if (ret < 0) + goto fail1; + + ret = gpio_request(173, "rev_id_2"); + if (ret < 0) + goto fail2; + + gpio_direction_input(171); + gpio_direction_input(172); + gpio_direction_input(173); + + beagle_rev = gpio_get_value(171) | (gpio_get_value(172) << 1) + | (gpio_get_value(173) << 2); + + switch (beagle_rev) { + case 7: + printk(KERN_INFO "OMAP3 Beagle Rev: Ax/Bx\n"); + omap3_beagle_version = OMAP3BEAGLE_BOARD_AXBX; + break; + case 6: + printk(KERN_INFO "OMAP3 Beagle Rev: C1/C2/C3\n"); + omap3_beagle_version = OMAP3BEAGLE_BOARD_C1_3; + break; + case 5: + printk(KERN_INFO "OMAP3 Beagle Rev: C4\n"); + omap3_beagle_version = OMAP3BEAGLE_BOARD_C4; + break; + case 0: + printk(KERN_INFO "OMAP3 Beagle Rev: xM\n"); + omap3_beagle_version = OMAP3BEAGLE_BOARD_XM; + break; + default: + printk(KERN_INFO "OMAP3 Beagle Rev: unknown %hd\n", beagle_rev); + omap3_beagle_version = OMAP3BEAGLE_BOARD_UNKN; + } + + return; + +fail2: + gpio_free(172); +fail1: + gpio_free(171); +fail0: + printk(KERN_ERR "Unable to get revision detection GPIO pins\n"); + omap3_beagle_version = OMAP3BEAGLE_BOARD_UNKN; + + return; +} + static struct mtd_partition omap3beagle_nand_partitions[] = { /* All the partition sizes are listed in terms of NAND block size */ { @@ -166,7 +254,7 @@ static void __init beagle_display_init(void) static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, - .wires = 8, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, .gpio_wp = 29, }, {} /* Terminator */ @@ -185,7 +273,10 @@ static struct gpio_led gpio_leds[]; static int beagle_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio) { - if (system_rev >= 0x20 && system_rev <= 0x34301000) { + if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XM) { + mmc[0].gpio_wp = -EINVAL; + } else if ((omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_C1_3) || + (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_C4)) { omap_mux_init_gpio(23, OMAP_PIN_INPUT); mmc[0].gpio_wp = 23; } else { @@ -322,13 +413,19 @@ static struct i2c_board_info __initdata beagle_i2c_boardinfo[] = { }, }; +static struct i2c_board_info __initdata beagle_i2c_eeprom[] = { + { + I2C_BOARD_INFO("eeprom", 0x50), + }, +}; + static int __init omap3_beagle_i2c_init(void) { omap_register_i2c_bus(1, 2600, beagle_i2c_boardinfo, ARRAY_SIZE(beagle_i2c_boardinfo)); /* Bus 3 is attached to the DVI port where devices like the pico DLP * projector don't work reliably with 400kHz */ - omap_register_i2c_bus(3, 100, NULL, 0); + omap_register_i2c_bus(3, 100, beagle_i2c_eeprom, ARRAY_SIZE(beagle_i2c_eeprom)); return 0; } @@ -464,6 +561,7 @@ static struct omap_musb_board_data musb_board_data = { static void __init omap3_beagle_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); + omap3_beagle_init_rev(); omap3_beagle_i2c_init(); platform_add_devices(omap3_beagle_devices, ARRAY_SIZE(omap3_beagle_devices)); diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index 8936e4fba334..b04365c6bb10 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -31,6 +31,7 @@ #include <linux/smsc911x.h> #include <linux/regulator/machine.h> +#include <linux/mmc/host.h> #include <mach/hardware.h> #include <asm/mach-types.h> @@ -370,7 +371,7 @@ static struct regulator_init_data omap3evm_vsim = { static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, - .wires = 4, + .caps = MMC_CAP_4_BIT_DATA, .gpio_cd = -EINVAL, .gpio_wp = 63, }, @@ -446,7 +447,7 @@ static struct twl4030_usb_data omap3evm_usb_data = { .usb_mode = T2_USB_MODE_ULPI, }; -static int board_keymap[] = { +static uint32_t board_keymap[] = { KEY(0, 0, KEY_LEFT), KEY(0, 1, KEY_DOWN), KEY(0, 2, KEY_ENTER), @@ -584,7 +585,7 @@ static int ads7846_get_pendown_state(void) return !gpio_get_value(OMAP3_EVM_TS_GPIO); } -struct ads7846_platform_data ads7846_config = { +static struct ads7846_platform_data ads7846_config = { .x_max = 0x0fff, .y_max = 0x0fff, .x_plate_ohms = 180, @@ -603,7 +604,7 @@ static struct omap2_mcspi_device_config ads7846_mcspi_config = { .single_channel = 1, /* 0: slave, 1: master */ }; -struct spi_board_info omap3evm_spi_board_info[] = { +static struct spi_board_info omap3evm_spi_board_info[] = { [0] = { .modalias = "ads7846", .bus_num = 1, diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c new file mode 100644 index 000000000000..5f7d2c1e7ef5 --- /dev/null +++ b/arch/arm/mach-omap2/board-omap3logic.c @@ -0,0 +1,241 @@ +/* + * linux/arch/arm/mach-omap2/board-omap3logic.c + * + * Copyright (C) 2010 Li-Pro.Net + * Stephan Linz <linz@li-pro.net> + * + * Copyright (C) 2010 Logic Product Development, Inc. + * Peter Barada <peter.barada@logicpd.com> + * + * Modified from Beagle, EVM, and RX51 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/gpio.h> + +#include <linux/regulator/machine.h> + +#include <linux/i2c/twl.h> +#include <linux/mmc/host.h> + +#include <mach/hardware.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> + +#include "mux.h" +#include "hsmmc.h" +#include "timer-gp.h" +#include "control.h" + +#include <plat/mux.h> +#include <plat/board.h> +#include <plat/common.h> +#include <plat/gpmc-smsc911x.h> +#include <plat/gpmc.h> +#include <plat/sdrc.h> + +#define OMAP3LOGIC_SMSC911X_CS 1 + +#define OMAP3530_LV_SOM_MMC_GPIO_CD 110 +#define OMAP3530_LV_SOM_MMC_GPIO_WP 126 +#define OMAP3530_LV_SOM_SMSC911X_GPIO_IRQ 152 + +#define OMAP3_TORPEDO_MMC_GPIO_CD 127 +#define OMAP3_TORPEDO_SMSC911X_GPIO_IRQ 129 + +static struct regulator_consumer_supply omap3logic_vmmc1_supply = { + .supply = "vmmc", +}; + +/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ +static struct regulator_init_data omap3logic_vmmc1 = { + .constraints = { + .name = "VMMC1", + .min_uV = 1850000, + .max_uV = 3150000, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &omap3logic_vmmc1_supply, +}; + +static struct twl4030_gpio_platform_data omap3logic_gpio_data = { + .gpio_base = OMAP_MAX_GPIO_LINES, + .irq_base = TWL4030_GPIO_IRQ_BASE, + .irq_end = TWL4030_GPIO_IRQ_END, + .use_leds = true, + .pullups = BIT(1), + .pulldowns = BIT(2) | BIT(6) | BIT(7) | BIT(8) + | BIT(13) | BIT(15) | BIT(16) | BIT(17), +}; + +static struct twl4030_platform_data omap3logic_twldata = { + .irq_base = TWL4030_IRQ_BASE, + .irq_end = TWL4030_IRQ_END, + + /* platform_data for children goes here */ + .gpio = &omap3logic_gpio_data, + .vmmc1 = &omap3logic_vmmc1, +}; + +static struct i2c_board_info __initdata omap3logic_i2c_boardinfo[] = { + { + I2C_BOARD_INFO("twl4030", 0x48), + .flags = I2C_CLIENT_WAKE, + .irq = INT_34XX_SYS_NIRQ, + .platform_data = &omap3logic_twldata, + }, +}; + +static int __init omap3logic_i2c_init(void) +{ + omap_register_i2c_bus(1, 2600, omap3logic_i2c_boardinfo, + ARRAY_SIZE(omap3logic_i2c_boardinfo)); + return 0; +} + +static struct omap2_hsmmc_info __initdata board_mmc_info[] = { + { + .name = "external", + .mmc = 1, + .caps = MMC_CAP_4_BIT_DATA, + .gpio_cd = -EINVAL, + .gpio_wp = -EINVAL, + }, + {} /* Terminator */ +}; + +static void __init board_mmc_init(void) +{ + if (machine_is_omap3530_lv_som()) { + /* OMAP3530 LV SOM board */ + board_mmc_info[0].gpio_cd = OMAP3530_LV_SOM_MMC_GPIO_CD; + board_mmc_info[0].gpio_wp = OMAP3530_LV_SOM_MMC_GPIO_WP; + omap_mux_init_signal("gpio_110", OMAP_PIN_OUTPUT); + omap_mux_init_signal("gpio_126", OMAP_PIN_OUTPUT); + } else if (machine_is_omap3_torpedo()) { + /* OMAP3 Torpedo board */ + board_mmc_info[0].gpio_cd = OMAP3_TORPEDO_MMC_GPIO_CD; + omap_mux_init_signal("gpio_127", OMAP_PIN_OUTPUT); + } else { + /* unsupported board */ + printk(KERN_ERR "%s(): unknown machine type\n", __func__); + return; + } + + omap2_hsmmc_init(board_mmc_info); + /* link regulators to MMC adapters */ + omap3logic_vmmc1_supply.dev = board_mmc_info[0].dev; +} + +static struct omap_smsc911x_platform_data __initdata board_smsc911x_data = { + .cs = OMAP3LOGIC_SMSC911X_CS, + .gpio_irq = -EINVAL, + .gpio_reset = -EINVAL, + .flags = IORESOURCE_IRQ_LOWLEVEL, +}; + +/* TODO/FIXME (comment by Peter Barada, LogicPD): + * Fix the PBIAS voltage for Torpedo MMC1 pins that + * are used for other needs (IRQs, etc). */ +static void omap3torpedo_fix_pbias_voltage(void) +{ + u16 control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE; + u32 reg; + + if (machine_is_omap3_torpedo()) + { + /* Set the bias for the pin */ + reg = omap_ctrl_readl(control_pbias_offset); + + reg &= ~OMAP343X_PBIASLITEPWRDNZ1; + omap_ctrl_writel(reg, control_pbias_offset); + + /* 100ms delay required for PBIAS configuration */ + msleep(100); + + reg |= OMAP343X_PBIASLITEVMODE1; + reg |= OMAP343X_PBIASLITEPWRDNZ1; + omap_ctrl_writel(reg | 0x300, control_pbias_offset); + } +} + +static inline void __init board_smsc911x_init(void) +{ + if (machine_is_omap3530_lv_som()) { + /* OMAP3530 LV SOM board */ + board_smsc911x_data.gpio_irq = + OMAP3530_LV_SOM_SMSC911X_GPIO_IRQ; + omap_mux_init_signal("gpio_152", OMAP_PIN_INPUT); + } else if (machine_is_omap3_torpedo()) { + /* OMAP3 Torpedo board */ + board_smsc911x_data.gpio_irq = OMAP3_TORPEDO_SMSC911X_GPIO_IRQ; + omap_mux_init_signal("gpio_129", OMAP_PIN_INPUT); + } else { + /* unsupported board */ + printk(KERN_ERR "%s(): unknown machine type\n", __func__); + return; + } + + gpmc_smsc911x_init(&board_smsc911x_data); +} + +static void __init omap3logic_init_irq(void) +{ + omap2_init_common_hw(NULL, NULL); + omap_init_irq(); + omap_gpio_init(); +} + +#ifdef CONFIG_OMAP_MUX +static struct omap_board_mux board_mux[] __initdata = { + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; +#else +#define board_mux NULL +#endif + +static void __init omap3logic_init(void) +{ + omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); + omap3torpedo_fix_pbias_voltage(); + omap3logic_i2c_init(); + omap_serial_init(); + board_mmc_init(); + board_smsc911x_init(); + + /* Ensure SDRC pins are mux'd for self-refresh */ + omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); + omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); +} + +MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board") + .boot_params = 0x80000100, + .map_io = omap3_map_io, + .init_irq = omap3logic_init_irq, + .init_machine = omap3logic_init, + .timer = &omap_timer, +MACHINE_END + +MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board") + .boot_params = 0x80000100, + .map_io = omap3_map_io, + .init_irq = omap3logic_init_irq, + .init_machine = omap3logic_init, + .timer = &omap_timer, +MACHINE_END diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index b7d6df4e3cf9..89ed1be2d62e 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c @@ -25,14 +25,16 @@ #include <linux/spi/ads7846.h> #include <linux/regulator/machine.h> #include <linux/i2c/twl.h> -#include <linux/spi/wl12xx.h> +#include <linux/wl12xx.h> #include <linux/mtd/partitions.h> #include <linux/mtd/nand.h> #include <linux/leds.h> #include <linux/input.h> #include <linux/input/matrix_keypad.h> #include <linux/gpio_keys.h> +#include <linux/mmc/host.h> #include <linux/mmc/card.h> +#include <linux/regulator/fixed.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -276,14 +278,14 @@ static void pandora_wl1251_init_card(struct mmc_card *card) static struct omap2_hsmmc_info omap3pandora_mmc[] = { { .mmc = 1, - .wires = 4, + .caps = MMC_CAP_4_BIT_DATA, .gpio_cd = -EINVAL, .gpio_wp = 126, .ext_clock = 0, }, { .mmc = 2, - .wires = 4, + .caps = MMC_CAP_4_BIT_DATA, .gpio_cd = -EINVAL, .gpio_wp = 127, .ext_clock = 1, @@ -291,7 +293,7 @@ static struct omap2_hsmmc_info omap3pandora_mmc[] = { }, { .mmc = 3, - .wires = 4, + .caps = MMC_CAP_4_BIT_DATA, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, .init_card = pandora_wl1251_init_card, @@ -344,6 +346,9 @@ static struct regulator_consumer_supply pandora_vmmc1_supply = static struct regulator_consumer_supply pandora_vmmc2_supply = REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"); +static struct regulator_consumer_supply pandora_vmmc3_supply = + REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.2"); + static struct regulator_consumer_supply pandora_vdda_dac_supply = REGULATOR_SUPPLY("vdda_dac", "omapdss"); @@ -488,6 +493,33 @@ static struct regulator_init_data pandora_vsim = { .consumer_supplies = &pandora_adac_supply, }; +/* Fixed regulator internal to Wifi module */ +static struct regulator_init_data pandora_vmmc3 = { + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &pandora_vmmc3_supply, +}; + +static struct fixed_voltage_config pandora_vwlan = { + .supply_name = "vwlan", + .microvolts = 1800000, /* 1.8V */ + .gpio = PANDORA_WIFI_NRESET_GPIO, + .startup_delay = 50000, /* 50ms */ + .enable_high = 1, + .enabled_at_boot = 0, + .init_data = &pandora_vmmc3, +}; + +static struct platform_device pandora_vwlan_device = { + .name = "reg-fixed-voltage", + .id = 1, + .dev = { + .platform_data = &pandora_vwlan, + }, +}; + static struct twl4030_usb_data omap3pandora_usb_data = { .usb_mode = T2_USB_MODE_ULPI, }; @@ -501,6 +533,8 @@ static struct twl4030_codec_data omap3pandora_codec_data = { .audio = &omap3pandora_audio_data, }; +static struct twl4030_bci_platform_data pandora_bci_data; + static struct twl4030_platform_data omap3pandora_twldata = { .irq_base = TWL4030_IRQ_BASE, .irq_end = TWL4030_IRQ_END, @@ -516,6 +550,7 @@ static struct twl4030_platform_data omap3pandora_twldata = { .vaux4 = &pandora_vaux4, .vsim = &pandora_vsim, .keypad = &pandora_kp_data, + .bci = &pandora_bci_data, }; static struct i2c_board_info __initdata omap3pandora_i2c_boardinfo[] = { @@ -644,19 +679,8 @@ static void pandora_wl1251_init(void) if (pandora_wl1251_pdata.irq < 0) goto fail_irq; - ret = gpio_request(PANDORA_WIFI_NRESET_GPIO, "wl1251 nreset"); - if (ret < 0) - goto fail_irq; - - /* start powered so that it probes with MMC subsystem */ - ret = gpio_direction_output(PANDORA_WIFI_NRESET_GPIO, 1); - if (ret < 0) - goto fail_nreset; - return; -fail_nreset: - gpio_free(PANDORA_WIFI_NRESET_GPIO); fail_irq: gpio_free(PANDORA_WIFI_IRQ_GPIO); fail: @@ -668,6 +692,7 @@ static struct platform_device *omap3pandora_devices[] __initdata = { &pandora_keys_gpio, &pandora_dss_device, &pandora_wl1251_data, + &pandora_vwlan_device, }; static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index bc5ac83bd4cf..f25272125413 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c @@ -26,6 +26,7 @@ #include <linux/regulator/machine.h> #include <linux/i2c/twl.h> +#include <linux/mmc/host.h> #include <mach/hardware.h> #include <asm/mach-types.h> @@ -38,7 +39,6 @@ #include <plat/gpmc.h> #include <plat/nand.h> #include <plat/usb.h> -#include <plat/timer-gp.h> #include <plat/display.h> #include <plat/mcspi.h> @@ -52,6 +52,7 @@ #include "sdram-micron-mt46h32m32lf-6.h" #include "mux.h" #include "hsmmc.h" +#include "timer-gp.h" #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) #define OMAP3STALKER_ETHR_START 0x2c000000 @@ -275,7 +276,7 @@ static struct regulator_init_data omap3stalker_vsim = { static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, - .wires = 4, + .caps = MMC_CAP_4_BIT_DATA, .gpio_cd = -EINVAL, .gpio_wp = 23, }, @@ -389,7 +390,7 @@ static struct twl4030_usb_data omap3stalker_usb_data = { .usb_mode = T2_USB_MODE_ULPI, }; -static int board_keymap[] = { +static uint32_t board_keymap[] = { KEY(0, 0, KEY_LEFT), KEY(0, 1, KEY_DOWN), KEY(0, 2, KEY_ENTER), @@ -564,7 +565,7 @@ static struct omap2_mcspi_device_config ads7846_mcspi_config = { .single_channel = 1, /* 0: slave, 1: master */ }; -struct spi_board_info omap3stalker_spi_board_info[] = { +static struct spi_board_info omap3stalker_spi_board_info[] = { [0] = { .modalias = "ads7846", .bus_num = 1, diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c index 0e99ce584dbf..41104bb8774c 100644 --- a/arch/arm/mach-omap2/board-omap3touchbook.c +++ b/arch/arm/mach-omap2/board-omap3touchbook.c @@ -27,6 +27,7 @@ #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> #include <linux/mtd/nand.h> +#include <linux/mmc/host.h> #include <plat/mcspi.h> #include <linux/spi/spi.h> @@ -47,10 +48,10 @@ #include <plat/gpmc.h> #include <plat/nand.h> #include <plat/usb.h> -#include <plat/timer-gp.h> #include "mux.h" #include "hsmmc.h" +#include "timer-gp.h" #include <asm/setup.h> @@ -61,7 +62,7 @@ #define TB_BL_PWM_TIMER 9 #define TB_KILL_POWER_GPIO 168 -unsigned long touchbook_revision; +static unsigned long touchbook_revision; static struct mtd_partition omap3touchbook_nand_partitions[] = { /* All the partition sizes are listed in terms of NAND block size */ @@ -108,7 +109,7 @@ static struct omap_nand_platform_data omap3touchbook_nand_data = { static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, - .wires = 8, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, .gpio_wp = 29, }, {} /* Terminator */ diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index db69bcadf4c7..702f2a63f2c1 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -20,6 +20,7 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/io.h> +#include <linux/leds.h> #include <linux/gpio.h> #include <linux/usb/otg.h> #include <linux/i2c/twl.h> @@ -33,12 +34,45 @@ #include <plat/board.h> #include <plat/common.h> -#include <plat/control.h> -#include <plat/timer-gp.h> #include <plat/usb.h> #include <plat/mmc.h> +#include "timer-gp.h" + #include "hsmmc.h" +#include "control.h" + +#define GPIO_HUB_POWER 1 +#define GPIO_HUB_NRESET 62 + +static struct gpio_led gpio_leds[] = { + { + .name = "pandaboard::status1", + .default_trigger = "heartbeat", + .gpio = 7, + }, + { + .name = "pandaboard::status2", + .default_trigger = "mmc0", + .gpio = 8, + }, +}; +static struct gpio_led_platform_data gpio_led_info = { + .leds = gpio_leds, + .num_leds = ARRAY_SIZE(gpio_leds), +}; + +static struct platform_device leds_gpio = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &gpio_led_info, + }, +}; + +static struct platform_device *panda_devices[] __initdata = { + &leds_gpio, +}; static void __init omap4_panda_init_irq(void) { @@ -47,6 +81,56 @@ static void __init omap4_panda_init_irq(void) omap_gpio_init(); } +static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { + .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, + .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN, + .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, + .phy_reset = false, + .reset_gpio_port[0] = -EINVAL, + .reset_gpio_port[1] = -EINVAL, + .reset_gpio_port[2] = -EINVAL +}; + +static void __init omap4_ehci_init(void) +{ + int ret; + + + /* disable the power to the usb hub prior to init */ + ret = gpio_request(GPIO_HUB_POWER, "hub_power"); + if (ret) { + pr_err("Cannot request GPIO %d\n", GPIO_HUB_POWER); + goto error1; + } + gpio_export(GPIO_HUB_POWER, 0); + gpio_direction_output(GPIO_HUB_POWER, 0); + gpio_set_value(GPIO_HUB_POWER, 0); + + /* reset phy+hub */ + ret = gpio_request(GPIO_HUB_NRESET, "hub_nreset"); + if (ret) { + pr_err("Cannot request GPIO %d\n", GPIO_HUB_NRESET); + goto error2; + } + gpio_export(GPIO_HUB_NRESET, 0); + gpio_direction_output(GPIO_HUB_NRESET, 0); + gpio_set_value(GPIO_HUB_NRESET, 0); + gpio_set_value(GPIO_HUB_NRESET, 1); + + usb_ehci_init(&ehci_pdata); + + /* enable power to hub */ + gpio_set_value(GPIO_HUB_POWER, 1); + return; + +error2: + gpio_free(GPIO_HUB_POWER); +error1: + pr_err("Unable to initialize EHCI power/reset\n"); + return; + +} + static struct omap_musb_board_data musb_board_data = { .interface_type = MUSB_INTERFACE_UTMI, .mode = MUSB_PERIPHERAL, @@ -56,7 +140,7 @@ static struct omap_musb_board_data musb_board_data = { static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, - .wires = 8, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, .gpio_wp = -EINVAL, }, {} /* Terminator */ @@ -67,10 +151,6 @@ static struct regulator_consumer_supply omap4_panda_vmmc_supply[] = { .supply = "vmmc", .dev_name = "mmci-omap-hs.0", }, - { - .supply = "vmmc", - .dev_name = "mmci-omap-hs.1", - }, }; static int omap4_twl6030_hsmmc_late_init(struct device *dev) @@ -89,7 +169,14 @@ static int omap4_twl6030_hsmmc_late_init(struct device *dev) static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev) { - struct omap_mmc_platform_data *pdata = dev->platform_data; + struct omap_mmc_platform_data *pdata; + + /* dev can be null if CONFIG_MMC_OMAP_HS is not set */ + if (!dev) { + pr_err("Failed omap4_twl6030_hsmmc_set_late_init\n"); + return; + } + pdata = dev->platform_data; pdata->init = omap4_twl6030_hsmmc_late_init; } @@ -156,7 +243,7 @@ static struct regulator_init_data omap4_panda_vmmc = { | REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, }, - .num_consumer_supplies = 2, + .num_consumer_supplies = 1, .consumer_supplies = omap4_panda_vmmc_supply, }; @@ -274,13 +361,13 @@ static int __init omap4_panda_i2c_init(void) } static void __init omap4_panda_init(void) { - int status; - omap4_panda_i2c_init(); + platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices)); omap_serial_init(); omap4_twl6030_hsmmc_init(mmc); /* OMAP4 Panda uses internal transceiver so register nop transceiver */ usb_nop_xceiv_register(); + omap4_ehci_init(); /* FIXME: allow multi-omap to boot until musb is updated for omap4 */ if (!cpu_is_omap44xx()) usb_musb_init(&musb_board_data); diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index 5e528ca015a1..7053bc0b46db 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c @@ -32,6 +32,7 @@ #include <linux/mtd/mtd.h> #include <linux/mtd/nand.h> #include <linux/mtd/partitions.h> +#include <linux/mmc/host.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -303,13 +304,13 @@ static void __init overo_flash_init(void) static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, - .wires = 4, + .caps = MMC_CAP_4_BIT_DATA, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, }, { .mmc = 2, - .wires = 4, + .caps = MMC_CAP_4_BIT_DATA, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, .transceiver = true, diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index 9a5eb87425fc..3fec4d62a91a 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -14,7 +14,7 @@ #include <linux/input.h> #include <linux/input/matrix_keypad.h> #include <linux/spi/spi.h> -#include <linux/spi/wl12xx.h> +#include <linux/wl12xx.h> #include <linux/i2c.h> #include <linux/i2c/twl.h> #include <linux/clk.h> @@ -23,6 +23,7 @@ #include <linux/gpio.h> #include <linux/gpio_keys.h> #include <linux/mmc/host.h> +#include <sound/tlv320aic3x.h> #include <plat/mcspi.h> #include <plat/board.h> @@ -32,6 +33,8 @@ #include <plat/onenand.h> #include <plat/gpmc-smc91x.h> +#include <mach/board-rx51.h> + #include <sound/tlv320aic3x.h> #include <sound/tpa6130a2-plat.h> @@ -104,6 +107,10 @@ static struct spi_board_info rx51_peripherals_spi_board_info[] __initdata = { }, }; +static struct platform_device rx51_charger_device = { + .name = "isp1704_charger", +}; + #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) #define RX51_GPIO_CAMERA_LENS_COVER 110 @@ -184,7 +191,7 @@ static void __init rx51_add_gpio_keys(void) } #endif /* CONFIG_KEYBOARD_GPIO || CONFIG_KEYBOARD_GPIO_MODULE */ -static int board_keymap[] = { +static uint32_t board_keymap[] = { /* * Note that KEY(x, 8, KEY_XXX) entries represent "entrire row * connected to the ground" matrix state. @@ -302,7 +309,7 @@ static struct omap2_hsmmc_info mmc[] __initdata = { { .name = "external", .mmc = 1, - .wires = 4, + .caps = MMC_CAP_4_BIT_DATA, .cover_only = true, .gpio_cd = 160, .gpio_wp = -EINVAL, @@ -311,7 +318,8 @@ static struct omap2_hsmmc_info mmc[] __initdata = { { .name = "internal", .mmc = 2, - .wires = 8, /* See also rx51_mmc2_remux */ + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, + /* See also rx51_mmc2_remux */ .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, .nonremovable = true, @@ -689,7 +697,6 @@ static struct twl4030_power_data rx51_t2scripts_data __initdata = { }; - static struct twl4030_platform_data rx51_twldata __initdata = { .irq_base = TWL4030_IRQ_BASE, .irq_end = TWL4030_IRQ_END, @@ -710,10 +717,6 @@ static struct twl4030_platform_data rx51_twldata __initdata = { .vio = &rx51_vio, }; -static struct aic3x_pdata rx51_aic3x_data __initdata = { - .gpio_reset = 60, -}; - static struct tpa6130a2_platform_data rx51_tpa6130a2_data __initdata = { .id = TPA6130A2, .power_gpio = 98, @@ -728,6 +731,17 @@ static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_1[] = { }, }; +/* Audio setup data */ +static struct aic3x_setup_data rx51_aic34_setup = { + .gpio_func[0] = AIC3X_GPIO1_FUNC_DISABLED, + .gpio_func[1] = AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT, +}; + +static struct aic3x_pdata rx51_aic3x_data = { + .setup = &rx51_aic34_setup, + .gpio_reset = 60, +}; + static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_2[] = { { I2C_BOARD_INFO("tlv320aic3x", 0x18), @@ -909,5 +923,6 @@ void __init rx51_peripherals_init(void) spi_register_board_info(rx51_peripherals_spi_board_info, ARRAY_SIZE(rx51_peripherals_spi_board_info)); omap2_hsmmc_init(mmc); + platform_device_register(&rx51_charger_device); } diff --git a/arch/arm/mach-omap2/board-rx51-sdram.c b/arch/arm/mach-omap2/board-rx51-sdram.c index f392844195d2..a43b2c5c838b 100644 --- a/arch/arm/mach-omap2/board-rx51-sdram.c +++ b/arch/arm/mach-omap2/board-rx51-sdram.c @@ -43,7 +43,7 @@ struct sdram_timings { u32 tWTR; }; -struct omap_sdrc_params rx51_sdrc_params[4]; +static struct omap_sdrc_params rx51_sdrc_params[4]; static const struct sdram_timings rx51_timings[] = { { diff --git a/arch/arm/mach-omap2/board-rx51-video.c b/arch/arm/mach-omap2/board-rx51-video.c index 5a1005ba9815..85503fed4e13 100644 --- a/arch/arm/mach-omap2/board-rx51-video.c +++ b/arch/arm/mach-omap2/board-rx51-video.c @@ -20,6 +20,8 @@ #include <plat/vram.h> #include <plat/mcspi.h> +#include <mach/board-rx51.h> + #include "mux.h" #define RX51_LCD_RESET_GPIO 90 diff --git a/arch/arm/mach-omap2/board-zoom-debugboard.c b/arch/arm/mach-omap2/board-zoom-debugboard.c index 1d7f827b0408..007ebdc6c993 100644 --- a/arch/arm/mach-omap2/board-zoom-debugboard.c +++ b/arch/arm/mach-omap2/board-zoom-debugboard.c @@ -16,6 +16,8 @@ #include <plat/gpmc.h> +#include <mach/board-zoom.h> + #define ZOOM_SMSC911X_CS 7 #define ZOOM_SMSC911X_GPIO 158 #define ZOOM_QUADUART_CS 3 diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c index 6b3984964cc5..86c9b2102952 100644 --- a/arch/arm/mach-omap2/board-zoom-peripherals.c +++ b/arch/arm/mach-omap2/board-zoom-peripherals.c @@ -16,6 +16,9 @@ #include <linux/gpio.h> #include <linux/i2c/twl.h> #include <linux/regulator/machine.h> +#include <linux/regulator/fixed.h> +#include <linux/wl12xx.h> +#include <linux/mmc/host.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -24,11 +27,16 @@ #include <plat/common.h> #include <plat/usb.h> +#include <mach/board-zoom.h> + #include "mux.h" #include "hsmmc.h" +#define OMAP_ZOOM_WLAN_PMENA_GPIO (101) +#define OMAP_ZOOM_WLAN_IRQ_GPIO (162) + /* Zoom2 has Qwerty keyboard*/ -static int board_keymap[] = { +static uint32_t board_keymap[] = { KEY(0, 0, KEY_E), KEY(0, 1, KEY_R), KEY(0, 2, KEY_T), @@ -106,6 +114,11 @@ static struct regulator_consumer_supply zoom_vmmc2_supply = { .supply = "vmmc", }; +static struct regulator_consumer_supply zoom_vmmc3_supply = { + .supply = "vmmc", + .dev_name = "mmci-omap-hs.2", +}; + /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ static struct regulator_init_data zoom_vmmc1 = { .constraints = { @@ -151,23 +164,63 @@ static struct regulator_init_data zoom_vsim = { .consumer_supplies = &zoom_vsim_supply, }; +static struct regulator_init_data zoom_vmmc3 = { + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &zoom_vmmc3_supply, +}; + +static struct fixed_voltage_config zoom_vwlan = { + .supply_name = "vwl1271", + .microvolts = 1800000, /* 1.8V */ + .gpio = OMAP_ZOOM_WLAN_PMENA_GPIO, + .startup_delay = 70000, /* 70msec */ + .enable_high = 1, + .enabled_at_boot = 0, + .init_data = &zoom_vmmc3, +}; + +static struct platform_device omap_vwlan_device = { + .name = "reg-fixed-voltage", + .id = 1, + .dev = { + .platform_data = &zoom_vwlan, + }, +}; + +struct wl12xx_platform_data omap_zoom_wlan_data __initdata = { + .irq = OMAP_GPIO_IRQ(OMAP_ZOOM_WLAN_IRQ_GPIO), + /* ZOOM ref clock is 26 MHz */ + .board_ref_clock = 1, +}; + static struct omap2_hsmmc_info mmc[] __initdata = { { .name = "external", .mmc = 1, - .wires = 4, + .caps = MMC_CAP_4_BIT_DATA, .gpio_wp = -EINVAL, .power_saving = true, }, { .name = "internal", .mmc = 2, - .wires = 8, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, .nonremovable = true, .power_saving = true, }, + { + .name = "wl1271", + .mmc = 3, + .caps = MMC_CAP_4_BIT_DATA, + .gpio_wp = -EINVAL, + .gpio_cd = -EINVAL, + .nonremovable = true, + }, {} /* Terminator */ }; @@ -188,6 +241,11 @@ static int zoom_twl_gpio_setup(struct device *dev, return 0; } +/* EXTMUTE callback function */ +void zoom2_set_hs_extmute(int mute) +{ + gpio_set_value(ZOOM2_HEADSET_EXTMUTE_GPIO, mute); +} static int zoom_batt_table[] = { /* 0 C*/ @@ -257,6 +315,11 @@ static struct i2c_board_info __initdata zoom_i2c_boardinfo[] = { static int __init omap_i2c_init(void) { + if (machine_is_omap_zoom2()) { + zoom_audio_data.ramp_delay_value = 3; /* 161 ms */ + zoom_audio_data.hs_extmute = 1; + zoom_audio_data.set_hs_extmute = zoom2_set_hs_extmute; + } omap_register_i2c_bus(1, 2400, zoom_i2c_boardinfo, ARRAY_SIZE(zoom_i2c_boardinfo)); omap_register_i2c_bus(2, 400, NULL, 0); @@ -279,7 +342,12 @@ static void enable_board_wakeup_source(void) void __init zoom_peripherals_init(void) { + if (wl12xx_set_platform_data(&omap_zoom_wlan_data)) + pr_err("error setting wl12xx data\n"); + omap_i2c_init(); + platform_device_register(&omap_vwlan_device); usb_musb_init(&musb_board_data); enable_board_wakeup_source(); + omap_serial_init(); } diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c index 24bbd0def64f..2992a9f3a585 100644 --- a/arch/arm/mach-omap2/board-zoom2.c +++ b/arch/arm/mach-omap2/board-zoom2.c @@ -14,6 +14,7 @@ #include <linux/platform_device.h> #include <linux/input.h> #include <linux/gpio.h> +#include <linux/i2c/twl.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -23,6 +24,7 @@ #include <mach/board-zoom.h> +#include "board-flash.h" #include "mux.h" #include "sdram-micron-mt46h32m32lf-6.h" @@ -34,41 +36,6 @@ static void __init omap_zoom2_init_irq(void) omap_gpio_init(); } -/* REVISIT: These audio entries can be removed once MFD code is merged */ -#if 0 - -static struct twl4030_madc_platform_data zoom2_madc_data = { - .irq_line = 1, -}; - -static struct twl4030_codec_audio_data zoom2_audio_data = { - .audio_mclk = 26000000, -}; - -static struct twl4030_codec_data zoom2_codec_data = { - .audio_mclk = 26000000, - .audio = &zoom2_audio_data, -}; - -static struct twl4030_platform_data zoom2_twldata = { - .irq_base = TWL4030_IRQ_BASE, - .irq_end = TWL4030_IRQ_END, - - /* platform_data for children goes here */ - .bci = &zoom2_bci_data, - .madc = &zoom2_madc_data, - .usb = &zoom2_usb_data, - .gpio = &zoom2_gpio_data, - .keypad = &zoom2_kp_twl4030_data, - .codec = &zoom2_codec_data, - .vmmc1 = &zoom2_vmmc1, - .vmmc2 = &zoom2_vmmc2, - .vsim = &zoom2_vsim, - -}; - -#endif - #ifdef CONFIG_OMAP_MUX static struct omap_board_mux board_mux[] __initdata = { /* WLAN IRQ - GPIO 162 */ diff --git a/arch/arm/mach-omap2/board-zoom3.c b/arch/arm/mach-omap2/board-zoom3.c index b2bb3ff971ac..5adde12c0395 100644 --- a/arch/arm/mach-omap2/board-zoom3.c +++ b/arch/arm/mach-omap2/board-zoom3.c @@ -22,6 +22,7 @@ #include <plat/board.h> #include <plat/usb.h> +#include "board-flash.h" #include "mux.h" #include "sdram-hynix-h8mbx00u0mer-0em.h" diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 605f531783a8..b5babf5440e4 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -395,7 +395,7 @@ void omap2_clk_disable_unused(struct clk *clk) if ((regval32 & (1 << clk->enable_bit)) == v) return; - printk(KERN_DEBUG "Disabling unused clock \"%s\"\n", clk->name); + pr_debug("Disabling unused clock \"%s\"\n", clk->name); if (cpu_is_omap34xx()) { omap2_clk_enable(clk); omap2_clk_disable(clk); diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index 37d65d62ed8f..21f856252ad8 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c @@ -27,6 +27,7 @@ #include "prm-regbits-24xx.h" #include "cm-regbits-24xx.h" #include "sdrc.h" +#include "control.h" #define OMAP_CM_REGADDR OMAP2420_CM_REGADDR @@ -89,6 +90,12 @@ static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ .clkdm_name = "wkup_clkdm", }; +/* Optional external clock input for McBSP CLKS */ +static struct clk mcbsp_clks = { + .name = "mcbsp_clks", + .ops = &clkops_null, +}; + /* * Analog domain root source clocks */ @@ -1135,14 +1142,34 @@ static struct clk mcbsp1_ick = { .recalc = &followparent_recalc, }; +static const struct clksel_rate common_mcbsp_96m_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel mcbsp_fck_clksel[] = { + { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates }, + { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, + { .parent = NULL } +}; + static struct clk mcbsp1_fck = { .name = "mcbsp1_fck", .ops = &clkops_omap2_dflt_wait, .parent = &func_96m_ck, + .init = &omap2_init_clksel_parent, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, - .recalc = &followparent_recalc, + .clksel_reg = OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), + .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, + .clksel = mcbsp_fck_clksel, + .recalc = &omap2_clksel_recalc, }; static struct clk mcbsp2_ick = { @@ -1159,10 +1186,14 @@ static struct clk mcbsp2_fck = { .name = "mcbsp2_fck", .ops = &clkops_omap2_dflt_wait, .parent = &func_96m_ck, + .init = &omap2_init_clksel_parent, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, - .recalc = &followparent_recalc, + .clksel_reg = OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), + .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, + .clksel = mcbsp_fck_clksel, + .recalc = &omap2_clksel_recalc, }; static struct clk mcspi1_ick = { @@ -1721,6 +1752,9 @@ static struct omap_clk omap2420_clks[] = { CLK(NULL, "osc_ck", &osc_ck, CK_242X), CLK(NULL, "sys_ck", &sys_ck, CK_242X), CLK(NULL, "alt_ck", &alt_ck, CK_242X), + CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_242X), + CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_242X), + CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_242X), /* internal analog sources */ CLK(NULL, "dpll_ck", &dpll_ck, CK_242X), CLK(NULL, "apll96_ck", &apll96_ck, CK_242X), @@ -1728,6 +1762,8 @@ static struct omap_clk omap2420_clks[] = { /* internal prcm root sources */ CLK(NULL, "func_54m_ck", &func_54m_ck, CK_242X), CLK(NULL, "core_ck", &core_ck, CK_242X), + CLK("omap-mcbsp.1", "prcm_fck", &func_96m_ck, CK_242X), + CLK("omap-mcbsp.2", "prcm_fck", &func_96m_ck, CK_242X), CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X), CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X), CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X), @@ -1838,7 +1874,7 @@ static struct omap_clk omap2420_clks[] = { CLK(NULL, "des_ick", &des_ick, CK_242X), CLK("omap-sham", "ick", &sha_ick, CK_242X), CLK("omap_rng", "ick", &rng_ick, CK_242X), - CLK(NULL, "aes_ick", &aes_ick, CK_242X), + CLK("omap-aes", "ick", &aes_ick, CK_242X), CLK(NULL, "pka_ick", &pka_ick, CK_242X), CLK(NULL, "usb_fck", &usb_fck, CK_242X), CLK("musb_hdrc", "fck", &osc_ck, CK_242X), diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c index b33118fb6a87..e32afcbdfb88 100644 --- a/arch/arm/mach-omap2/clock2430_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c @@ -27,6 +27,7 @@ #include "prm-regbits-24xx.h" #include "cm-regbits-24xx.h" #include "sdrc.h" +#include "control.h" #define OMAP_CM_REGADDR OMAP2430_CM_REGADDR @@ -89,6 +90,12 @@ static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ .clkdm_name = "wkup_clkdm", }; +/* Optional external clock input for McBSP CLKS */ +static struct clk mcbsp_clks = { + .name = "mcbsp_clks", + .ops = &clkops_null, +}; + /* * Analog domain root source clocks */ @@ -1123,14 +1130,34 @@ static struct clk mcbsp1_ick = { .recalc = &followparent_recalc, }; +static const struct clksel_rate common_mcbsp_96m_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel mcbsp_fck_clksel[] = { + { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates }, + { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, + { .parent = NULL } +}; + static struct clk mcbsp1_fck = { .name = "mcbsp1_fck", .ops = &clkops_omap2_dflt_wait, .parent = &func_96m_ck, + .init = &omap2_init_clksel_parent, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, - .recalc = &followparent_recalc, + .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), + .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, + .clksel = mcbsp_fck_clksel, + .recalc = &omap2_clksel_recalc, }; static struct clk mcbsp2_ick = { @@ -1147,10 +1174,14 @@ static struct clk mcbsp2_fck = { .name = "mcbsp2_fck", .ops = &clkops_omap2_dflt_wait, .parent = &func_96m_ck, + .init = &omap2_init_clksel_parent, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, - .recalc = &followparent_recalc, + .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), + .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, + .clksel = mcbsp_fck_clksel, + .recalc = &omap2_clksel_recalc, }; static struct clk mcbsp3_ick = { @@ -1167,10 +1198,14 @@ static struct clk mcbsp3_fck = { .name = "mcbsp3_fck", .ops = &clkops_omap2_dflt_wait, .parent = &func_96m_ck, + .init = &omap2_init_clksel_parent, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, - .recalc = &followparent_recalc, + .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), + .clksel_mask = OMAP2_MCBSP3_CLKS_MASK, + .clksel = mcbsp_fck_clksel, + .recalc = &omap2_clksel_recalc, }; static struct clk mcbsp4_ick = { @@ -1187,10 +1222,14 @@ static struct clk mcbsp4_fck = { .name = "mcbsp4_fck", .ops = &clkops_omap2_dflt_wait, .parent = &func_96m_ck, + .init = &omap2_init_clksel_parent, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, - .recalc = &followparent_recalc, + .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), + .clksel_mask = OMAP2_MCBSP4_CLKS_MASK, + .clksel = mcbsp_fck_clksel, + .recalc = &omap2_clksel_recalc, }; static struct clk mcbsp5_ick = { @@ -1207,10 +1246,14 @@ static struct clk mcbsp5_fck = { .name = "mcbsp5_fck", .ops = &clkops_omap2_dflt_wait, .parent = &func_96m_ck, + .init = &omap2_init_clksel_parent, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, - .recalc = &followparent_recalc, + .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), + .clksel_mask = OMAP2_MCBSP5_CLKS_MASK, + .clksel = mcbsp_fck_clksel, + .recalc = &omap2_clksel_recalc, }; static struct clk mcspi1_ick = { @@ -1808,6 +1851,12 @@ static struct omap_clk omap2430_clks[] = { CLK(NULL, "osc_ck", &osc_ck, CK_243X), CLK(NULL, "sys_ck", &sys_ck, CK_243X), CLK(NULL, "alt_ck", &alt_ck, CK_243X), + CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_243X), + CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_243X), + CLK("omap-mcbsp.3", "pad_fck", &mcbsp_clks, CK_243X), + CLK("omap-mcbsp.4", "pad_fck", &mcbsp_clks, CK_243X), + CLK("omap-mcbsp.5", "pad_fck", &mcbsp_clks, CK_243X), + CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_243X), /* internal analog sources */ CLK(NULL, "dpll_ck", &dpll_ck, CK_243X), CLK(NULL, "apll96_ck", &apll96_ck, CK_243X), @@ -1815,6 +1864,11 @@ static struct omap_clk omap2430_clks[] = { /* internal prcm root sources */ CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X), CLK(NULL, "core_ck", &core_ck, CK_243X), + CLK("omap-mcbsp.1", "prcm_fck", &func_96m_ck, CK_243X), + CLK("omap-mcbsp.2", "prcm_fck", &func_96m_ck, CK_243X), + CLK("omap-mcbsp.3", "prcm_fck", &func_96m_ck, CK_243X), + CLK("omap-mcbsp.4", "prcm_fck", &func_96m_ck, CK_243X), + CLK("omap-mcbsp.5", "prcm_fck", &func_96m_ck, CK_243X), CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X), CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X), CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X), @@ -1926,7 +1980,7 @@ static struct omap_clk omap2430_clks[] = { CLK(NULL, "des_ick", &des_ick, CK_243X), CLK("omap-sham", "ick", &sha_ick, CK_243X), CLK("omap_rng", "ick", &rng_ick, CK_243X), - CLK(NULL, "aes_ick", &aes_ick, CK_243X), + CLK("omap-aes", "ick", &aes_ick, CK_243X), CLK(NULL, "pka_ick", &pka_ick, CK_243X), CLK(NULL, "usb_fck", &usb_fck, CK_243X), CLK("musb_hdrc", "ick", &usbhs_ick, CK_243X), diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index dfdce2d82779..d85ecd5aebfd 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -20,7 +20,6 @@ #include <linux/clk.h> #include <linux/list.h> -#include <plat/control.h> #include <plat/clkdev_omap.h> #include "clock.h" @@ -33,6 +32,7 @@ #include "cm-regbits-34xx.h" #include "prm.h" #include "prm-regbits-34xx.h" +#include "control.h" /* * clocks @@ -2465,6 +2465,16 @@ static struct clk uart3_fck = { .recalc = &followparent_recalc, }; +static struct clk uart4_fck = { + .name = "uart4_fck", + .ops = &clkops_omap2_dflt_wait, + .parent = &per_48m_fck, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3630_EN_UART4_SHIFT, + .clkdm_name = "per_clkdm", + .recalc = &followparent_recalc, +}; + static struct clk gpt2_fck = { .name = "gpt2_fck", .ops = &clkops_omap2_dflt_wait, @@ -2715,6 +2725,16 @@ static struct clk uart3_ick = { .recalc = &followparent_recalc, }; +static struct clk uart4_ick = { + .name = "uart4_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &per_l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3630_EN_UART4_SHIFT, + .clkdm_name = "per_clkdm", + .recalc = &followparent_recalc, +}; + static struct clk gpt9_ick = { .name = "gpt9_ick", .ops = &clkops_omap2_dflt_wait, @@ -3188,6 +3208,11 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX), CLK(NULL, "sys_ck", &sys_ck, CK_3XXX), CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX), + CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_3XXX), + CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_3XXX), + CLK("omap-mcbsp.3", "pad_fck", &mcbsp_clks, CK_3XXX), + CLK("omap-mcbsp.4", "pad_fck", &mcbsp_clks, CK_3XXX), + CLK("omap-mcbsp.5", "pad_fck", &mcbsp_clks, CK_3XXX), CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX), CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX), CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX), @@ -3253,6 +3278,8 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2 | CK_AM35XX), CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2 | CK_AM35XX), CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2 | CK_AM35XX), + CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX), + CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX), CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX), CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2 | CK_AM35XX), CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_3XXX), @@ -3288,7 +3315,7 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2 | CK_AM35XX), CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2 | CK_AM35XX), CLK(NULL, "icr_ick", &icr_ick, CK_343X), - CLK(NULL, "aes2_ick", &aes2_ick, CK_343X), + CLK("omap-aes", "ick", &aes2_ick, CK_343X), CLK("omap-sham", "ick", &sha12_ick, CK_343X), CLK(NULL, "des2_ick", &des2_ick, CK_343X), CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_3XXX), @@ -3346,9 +3373,13 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX), CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX), CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX), + CLK("omap-mcbsp.2", "prcm_fck", &per_96m_fck, CK_3XXX), + CLK("omap-mcbsp.3", "prcm_fck", &per_96m_fck, CK_3XXX), + CLK("omap-mcbsp.4", "prcm_fck", &per_96m_fck, CK_3XXX), CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX), CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX), CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX), + CLK(NULL, "uart4_fck", &uart4_fck, CK_36XX), CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX), CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX), CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX), @@ -3372,6 +3403,7 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "gpio2_ick", &gpio2_ick, CK_3XXX), CLK(NULL, "wdt3_ick", &wdt3_ick, CK_3XXX), CLK(NULL, "uart3_ick", &uart3_ick, CK_3XXX), + CLK(NULL, "uart4_ick", &uart4_ick, CK_36XX), CLK(NULL, "gpt9_ick", &gpt9_ick, CK_3XXX), CLK(NULL, "gpt8_ick", &gpt8_ick, CK_3XXX), CLK(NULL, "gpt7_ick", &gpt7_ick, CK_3XXX), diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index e10db7a90cb2..1599836ba3d9 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -17,13 +17,15 @@ * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. + * + * XXX Some of the ES1 clocks have been removed/changed; once support + * is added for discriminating clocks by ES level, these should be added back + * in. */ #include <linux/kernel.h> #include <linux/list.h> #include <linux/clk.h> - -#include <plat/control.h> #include <plat/clkdev_omap.h> #include "clock.h" @@ -32,6 +34,7 @@ #include "cm-regbits-44xx.h" #include "prm.h" #include "prm-regbits-44xx.h" +#include "control.h" /* Root clocks */ @@ -175,21 +178,27 @@ static struct clk sys_clkin_ck = { .recalc = &omap2_clksel_recalc, }; +static struct clk tie_low_clock_ck = { + .name = "tie_low_clock_ck", + .rate = 0, + .ops = &clkops_null, +}; + static struct clk utmi_phy_clkout_ck = { .name = "utmi_phy_clkout_ck", - .rate = 12000000, + .rate = 60000000, .ops = &clkops_null, }; static struct clk xclk60mhsp1_ck = { .name = "xclk60mhsp1_ck", - .rate = 12000000, + .rate = 60000000, .ops = &clkops_null, }; static struct clk xclk60mhsp2_ck = { .name = "xclk60mhsp2_ck", - .rate = 12000000, + .rate = 60000000, .ops = &clkops_null, }; @@ -201,39 +210,23 @@ static struct clk xclk60motg_ck = { /* Module clocks and DPLL outputs */ -static const struct clksel_rate div2_1to2_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_4430 }, - { .div = 2, .val = 1, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; - -static const struct clksel dpll_sys_ref_clk_div[] = { - { .parent = &sys_clkin_ck, .rates = div2_1to2_rates }, +static const struct clksel abe_dpll_bypass_clk_mux_sel[] = { + { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, + { .parent = &sys_32k_ck, .rates = div_1_1_rates }, { .parent = NULL }, }; -static struct clk dpll_sys_ref_clk = { - .name = "dpll_sys_ref_clk", +static struct clk abe_dpll_bypass_clk_mux_ck = { + .name = "abe_dpll_bypass_clk_mux_ck", .parent = &sys_clkin_ck, - .clksel = dpll_sys_ref_clk_div, - .clksel_reg = OMAP4430_CM_DPLL_SYS_REF_CLKSEL, - .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static const struct clksel abe_dpll_refclk_mux_sel[] = { - { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates }, - { .parent = &sys_32k_ck, .rates = div_1_1_rates }, - { .parent = NULL }, + .recalc = &followparent_recalc, }; static struct clk abe_dpll_refclk_mux_ck = { .name = "abe_dpll_refclk_mux_ck", - .parent = &dpll_sys_ref_clk, - .clksel = abe_dpll_refclk_mux_sel, + .parent = &sys_clkin_ck, + .clksel = abe_dpll_bypass_clk_mux_sel, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_ABE_PLL_REF_CLKSEL, .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, @@ -244,7 +237,7 @@ static struct clk abe_dpll_refclk_mux_ck = { /* DPLL_ABE */ static struct dpll_data dpll_abe_dd = { .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE, - .clk_bypass = &sys_clkin_ck, + .clk_bypass = &abe_dpll_bypass_clk_mux_ck, .clk_ref = &abe_dpll_refclk_mux_ck, .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), @@ -310,6 +303,12 @@ static struct clk abe_clk = { .set_rate = &omap2_clksel_set_rate, }; +static const struct clksel_rate div2_1to2_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_4430 }, + { .div = 2, .val = 1, .flags = RATE_IN_4430 }, + { .div = 0 }, +}; + static const struct clksel aess_fclk_div[] = { { .parent = &abe_clk, .rates = div2_1to2_rates }, { .parent = NULL }, @@ -380,14 +379,14 @@ static struct clk dpll_abe_m3_ck = { }; static const struct clksel core_hsd_byp_clk_mux_sel[] = { - { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates }, + { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, { .parent = &dpll_abe_m3_ck, .rates = div_1_1_rates }, { .parent = NULL }, }; static struct clk core_hsd_byp_clk_mux_ck = { .name = "core_hsd_byp_clk_mux_ck", - .parent = &dpll_sys_ref_clk, + .parent = &sys_clkin_ck, .clksel = core_hsd_byp_clk_mux_sel, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_CORE, @@ -400,7 +399,7 @@ static struct clk core_hsd_byp_clk_mux_ck = { static struct dpll_data dpll_core_dd = { .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE, .clk_bypass = &core_hsd_byp_clk_mux_ck, - .clk_ref = &dpll_sys_ref_clk, + .clk_ref = &sys_clkin_ck, .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE, @@ -418,7 +417,7 @@ static struct dpll_data dpll_core_dd = { static struct clk dpll_core_ck = { .name = "dpll_core_ck", - .parent = &dpll_sys_ref_clk, + .parent = &sys_clkin_ck, .dpll_data = &dpll_core_dd, .init = &omap2_init_dpll_parent, .ops = &clkops_null, @@ -596,14 +595,14 @@ static struct clk dpll_core_m7_ck = { }; static const struct clksel iva_hsd_byp_clk_mux_sel[] = { - { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates }, + { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, { .parent = &div_iva_hs_clk, .rates = div_1_1_rates }, { .parent = NULL }, }; static struct clk iva_hsd_byp_clk_mux_ck = { .name = "iva_hsd_byp_clk_mux_ck", - .parent = &dpll_sys_ref_clk, + .parent = &sys_clkin_ck, .ops = &clkops_null, .recalc = &followparent_recalc, }; @@ -612,7 +611,7 @@ static struct clk iva_hsd_byp_clk_mux_ck = { static struct dpll_data dpll_iva_dd = { .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA, .clk_bypass = &iva_hsd_byp_clk_mux_ck, - .clk_ref = &dpll_sys_ref_clk, + .clk_ref = &sys_clkin_ck, .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA, @@ -630,7 +629,7 @@ static struct dpll_data dpll_iva_dd = { static struct clk dpll_iva_ck = { .name = "dpll_iva_ck", - .parent = &dpll_sys_ref_clk, + .parent = &sys_clkin_ck, .dpll_data = &dpll_iva_dd, .init = &omap2_init_dpll_parent, .ops = &clkops_omap3_noncore_dpll_ops, @@ -672,7 +671,7 @@ static struct clk dpll_iva_m5_ck = { static struct dpll_data dpll_mpu_dd = { .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU, .clk_bypass = &div_mpu_hs_clk, - .clk_ref = &dpll_sys_ref_clk, + .clk_ref = &sys_clkin_ck, .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU, @@ -690,7 +689,7 @@ static struct dpll_data dpll_mpu_dd = { static struct clk dpll_mpu_ck = { .name = "dpll_mpu_ck", - .parent = &dpll_sys_ref_clk, + .parent = &sys_clkin_ck, .dpll_data = &dpll_mpu_dd, .init = &omap2_init_dpll_parent, .ops = &clkops_omap3_noncore_dpll_ops, @@ -724,14 +723,14 @@ static struct clk per_hs_clk_div_ck = { }; static const struct clksel per_hsd_byp_clk_mux_sel[] = { - { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates }, + { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates }, { .parent = NULL }, }; static struct clk per_hsd_byp_clk_mux_ck = { .name = "per_hsd_byp_clk_mux_ck", - .parent = &dpll_sys_ref_clk, + .parent = &sys_clkin_ck, .clksel = per_hsd_byp_clk_mux_sel, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_PER, @@ -744,7 +743,7 @@ static struct clk per_hsd_byp_clk_mux_ck = { static struct dpll_data dpll_per_dd = { .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER, .clk_bypass = &per_hsd_byp_clk_mux_ck, - .clk_ref = &dpll_sys_ref_clk, + .clk_ref = &sys_clkin_ck, .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER, @@ -762,7 +761,7 @@ static struct dpll_data dpll_per_dd = { static struct clk dpll_per_ck = { .name = "dpll_per_ck", - .parent = &dpll_sys_ref_clk, + .parent = &sys_clkin_ck, .dpll_data = &dpll_per_dd, .init = &omap2_init_dpll_parent, .ops = &clkops_omap3_noncore_dpll_ops, @@ -858,8 +857,8 @@ static struct clk dpll_per_m7_ck = { /* DPLL_UNIPRO */ static struct dpll_data dpll_unipro_dd = { .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_UNIPRO, - .clk_bypass = &dpll_sys_ref_clk, - .clk_ref = &dpll_sys_ref_clk, + .clk_bypass = &sys_clkin_ck, + .clk_ref = &sys_clkin_ck, .control_reg = OMAP4430_CM_CLKMODE_DPLL_UNIPRO, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO, @@ -877,7 +876,7 @@ static struct dpll_data dpll_unipro_dd = { static struct clk dpll_unipro_ck = { .name = "dpll_unipro_ck", - .parent = &dpll_sys_ref_clk, + .parent = &sys_clkin_ck, .dpll_data = &dpll_unipro_dd, .init = &omap2_init_dpll_parent, .ops = &clkops_omap3_noncore_dpll_ops, @@ -914,7 +913,8 @@ static struct clk usb_hs_clk_div_ck = { static struct dpll_data dpll_usb_dd = { .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB, .clk_bypass = &usb_hs_clk_div_ck, - .clk_ref = &dpll_sys_ref_clk, + .flags = DPLL_J_TYPE | DPLL_NO_DCO_SEL, + .clk_ref = &sys_clkin_ck, .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB, @@ -927,13 +927,12 @@ static struct dpll_data dpll_usb_dd = { .max_multiplier = OMAP4430_MAX_DPLL_MULT, .max_divider = OMAP4430_MAX_DPLL_DIV, .min_divider = 1, - .flags = DPLL_J_TYPE | DPLL_NO_DCO_SEL }; static struct clk dpll_usb_ck = { .name = "dpll_usb_ck", - .parent = &dpll_sys_ref_clk, + .parent = &sys_clkin_ck, .dpll_data = &dpll_usb_dd, .init = &omap2_init_dpll_parent, .ops = &clkops_omap3_noncore_dpll_ops, @@ -1222,7 +1221,7 @@ static struct clk per_abe_24m_fclk = { static const struct clksel pmd_stm_clock_mux_sel[] = { { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates }, - { .parent = &dpll_per_m7_ck, .rates = div_1_2_rates }, + { .parent = &tie_low_clock_ck, .rates = div_1_2_rates }, { .parent = NULL }, }; @@ -1240,10 +1239,15 @@ static struct clk pmd_trace_clk_mux_ck = { .recalc = &followparent_recalc, }; +static const struct clksel syc_clk_div_div[] = { + { .parent = &sys_clkin_ck, .rates = div2_1to2_rates }, + { .parent = NULL }, +}; + static struct clk syc_clk_div_ck = { .name = "syc_clk_div_ck", .parent = &sys_clkin_ck, - .clksel = dpll_sys_ref_clk_div, + .clksel = syc_clk_div_div, .clksel_reg = OMAP4430_CM_ABE_DSS_SYS_CLKSEL, .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, .ops = &clkops_null, @@ -1284,13 +1288,13 @@ static struct clk aess_fck = { .recalc = &followparent_recalc, }; -static struct clk cust_efuse_fck = { - .name = "cust_efuse_fck", +static struct clk bandgap_fclk = { + .name = "bandgap_fclk", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_cefuse_clkdm", - .parent = &sys_clkin_ck, + .enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, + .clkdm_name = "l4_wkup_clkdm", + .parent = &sys_32k_ck, .recalc = &followparent_recalc, }; @@ -1344,6 +1348,56 @@ static struct clk dmic_fck = { .clkdm_name = "abe_clkdm", }; +static struct clk dsp_fck = { + .name = "dsp_fck", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .clkdm_name = "tesla_clkdm", + .parent = &dpll_iva_m4_ck, + .recalc = &followparent_recalc, +}; + +static struct clk dss_sys_clk = { + .name = "dss_sys_clk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, + .clkdm_name = "l3_dss_clkdm", + .parent = &syc_clk_div_ck, + .recalc = &followparent_recalc, +}; + +static struct clk dss_tv_clk = { + .name = "dss_tv_clk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, + .clkdm_name = "l3_dss_clkdm", + .parent = &extalt_clkin_ck, + .recalc = &followparent_recalc, +}; + +static struct clk dss_dss_clk = { + .name = "dss_dss_clk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT, + .clkdm_name = "l3_dss_clkdm", + .parent = &dpll_per_m5_ck, + .recalc = &followparent_recalc, +}; + +static struct clk dss_48mhz_clk = { + .name = "dss_48mhz_clk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT, + .clkdm_name = "l3_dss_clkdm", + .parent = &func_48mc_fclk, + .recalc = &followparent_recalc, +}; + static struct clk dss_fck = { .name = "dss_fck", .ops = &clkops_omap2_dflt, @@ -1354,18 +1408,18 @@ static struct clk dss_fck = { .recalc = &followparent_recalc, }; -static struct clk ducati_ick = { - .name = "ducati_ick", +static struct clk efuse_ctrl_cust_fck = { + .name = "efuse_ctrl_cust_fck", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "ducati_clkdm", - .parent = &ducati_clk_mux_ck, + .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_cefuse_clkdm", + .parent = &sys_clkin_ck, .recalc = &followparent_recalc, }; -static struct clk emif1_ick = { - .name = "emif1_ick", +static struct clk emif1_fck = { + .name = "emif1_fck", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, @@ -1375,8 +1429,8 @@ static struct clk emif1_ick = { .recalc = &followparent_recalc, }; -static struct clk emif2_ick = { - .name = "emif2_ick", +static struct clk emif2_fck = { + .name = "emif2_fck", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, @@ -1407,42 +1461,24 @@ static struct clk fdif_fck = { .clkdm_name = "iss_clkdm", }; -static const struct clksel per_sgx_fclk_div[] = { - { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates }, - { .parent = NULL }, -}; - -static struct clk per_sgx_fclk = { - .name = "per_sgx_fclk", - .parent = &dpll_per_m2x2_ck, - .clksel = per_sgx_fclk_div, - .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_PER_192M_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static const struct clksel sgx_clk_mux_sel[] = { - { .parent = &dpll_core_m7_ck, .rates = div_1_0_rates }, - { .parent = &per_sgx_fclk, .rates = div_1_1_rates }, - { .parent = NULL }, +static struct clk fpka_fck = { + .name = "fpka_fck", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_secure_clkdm", + .parent = &l4_div_ck, + .recalc = &followparent_recalc, }; -/* Merged sgx_clk_mux into gfx */ -static struct clk gfx_fck = { - .name = "gfx_fck", - .parent = &dpll_core_m7_ck, - .clksel = sgx_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK, +static struct clk gpio1_dbclk = { + .name = "gpio1_dbclk", .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l3_gfx_clkdm", + .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, + .clkdm_name = "l4_wkup_clkdm", + .parent = &sys_32k_ck, + .recalc = &followparent_recalc, }; static struct clk gpio1_ick = { @@ -1455,6 +1491,16 @@ static struct clk gpio1_ick = { .recalc = &followparent_recalc, }; +static struct clk gpio2_dbclk = { + .name = "gpio2_dbclk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, + .clkdm_name = "l4_per_clkdm", + .parent = &sys_32k_ck, + .recalc = &followparent_recalc, +}; + static struct clk gpio2_ick = { .name = "gpio2_ick", .ops = &clkops_omap2_dflt, @@ -1465,6 +1511,16 @@ static struct clk gpio2_ick = { .recalc = &followparent_recalc, }; +static struct clk gpio3_dbclk = { + .name = "gpio3_dbclk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, + .clkdm_name = "l4_per_clkdm", + .parent = &sys_32k_ck, + .recalc = &followparent_recalc, +}; + static struct clk gpio3_ick = { .name = "gpio3_ick", .ops = &clkops_omap2_dflt, @@ -1475,6 +1531,16 @@ static struct clk gpio3_ick = { .recalc = &followparent_recalc, }; +static struct clk gpio4_dbclk = { + .name = "gpio4_dbclk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, + .clkdm_name = "l4_per_clkdm", + .parent = &sys_32k_ck, + .recalc = &followparent_recalc, +}; + static struct clk gpio4_ick = { .name = "gpio4_ick", .ops = &clkops_omap2_dflt, @@ -1485,6 +1551,16 @@ static struct clk gpio4_ick = { .recalc = &followparent_recalc, }; +static struct clk gpio5_dbclk = { + .name = "gpio5_dbclk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, + .clkdm_name = "l4_per_clkdm", + .parent = &sys_32k_ck, + .recalc = &followparent_recalc, +}; + static struct clk gpio5_ick = { .name = "gpio5_ick", .ops = &clkops_omap2_dflt, @@ -1495,6 +1571,16 @@ static struct clk gpio5_ick = { .recalc = &followparent_recalc, }; +static struct clk gpio6_dbclk = { + .name = "gpio6_dbclk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, + .clkdm_name = "l4_per_clkdm", + .parent = &sys_32k_ck, + .recalc = &followparent_recalc, +}; + static struct clk gpio6_ick = { .name = "gpio6_ick", .ops = &clkops_omap2_dflt, @@ -1515,214 +1601,25 @@ static struct clk gpmc_ick = { .recalc = &followparent_recalc, }; -static const struct clksel dmt1_clk_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &sys_32k_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -/* - * Merged dmt1_clk_mux into gptimer1 - * gptimer1 renamed temporarily into gpt1 to match OMAP3 convention - */ -static struct clk gpt1_fck = { - .name = "gpt1_fck", - .parent = &sys_clkin_ck, - .clksel = dmt1_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_wkup_clkdm", -}; - -/* - * Merged cm2_dm10_mux into gptimer10 - * gptimer10 renamed temporarily into gpt10 to match OMAP3 convention - */ -static struct clk gpt10_fck = { - .name = "gpt10_fck", - .parent = &sys_clkin_ck, - .clksel = dmt1_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", -}; - -/* - * Merged cm2_dm11_mux into gptimer11 - * gptimer11 renamed temporarily into gpt11 to match OMAP3 convention - */ -static struct clk gpt11_fck = { - .name = "gpt11_fck", - .parent = &sys_clkin_ck, - .clksel = dmt1_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", -}; - -/* - * Merged cm2_dm2_mux into gptimer2 - * gptimer2 renamed temporarily into gpt2 to match OMAP3 convention - */ -static struct clk gpt2_fck = { - .name = "gpt2_fck", - .parent = &sys_clkin_ck, - .clksel = dmt1_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", -}; - -/* - * Merged cm2_dm3_mux into gptimer3 - * gptimer3 renamed temporarily into gpt3 to match OMAP3 convention - */ -static struct clk gpt3_fck = { - .name = "gpt3_fck", - .parent = &sys_clkin_ck, - .clksel = dmt1_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", -}; - -/* - * Merged cm2_dm4_mux into gptimer4 - * gptimer4 renamed temporarily into gpt4 to match OMAP3 convention - */ -static struct clk gpt4_fck = { - .name = "gpt4_fck", - .parent = &sys_clkin_ck, - .clksel = dmt1_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", -}; - -static const struct clksel timer5_sync_mux_sel[] = { - { .parent = &syc_clk_div_ck, .rates = div_1_0_rates }, - { .parent = &sys_32k_ck, .rates = div_1_1_rates }, +static const struct clksel sgx_clk_mux_sel[] = { + { .parent = &dpll_core_m7_ck, .rates = div_1_0_rates }, + { .parent = &dpll_per_m7_ck, .rates = div_1_1_rates }, { .parent = NULL }, }; -/* - * Merged timer5_sync_mux into gptimer5 - * gptimer5 renamed temporarily into gpt5 to match OMAP3 convention - */ -static struct clk gpt5_fck = { - .name = "gpt5_fck", - .parent = &syc_clk_div_ck, - .clksel = timer5_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", -}; - -/* - * Merged timer6_sync_mux into gptimer6 - * gptimer6 renamed temporarily into gpt6 to match OMAP3 convention - */ -static struct clk gpt6_fck = { - .name = "gpt6_fck", - .parent = &syc_clk_div_ck, - .clksel = timer5_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", -}; - -/* - * Merged timer7_sync_mux into gptimer7 - * gptimer7 renamed temporarily into gpt7 to match OMAP3 convention - */ -static struct clk gpt7_fck = { - .name = "gpt7_fck", - .parent = &syc_clk_div_ck, - .clksel = timer5_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", -}; - -/* - * Merged timer8_sync_mux into gptimer8 - * gptimer8 renamed temporarily into gpt8 to match OMAP3 convention - */ -static struct clk gpt8_fck = { - .name = "gpt8_fck", - .parent = &syc_clk_div_ck, - .clksel = timer5_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", -}; - -/* - * Merged cm2_dm9_mux into gptimer9 - * gptimer9 renamed temporarily into gpt9 to match OMAP3 convention - */ -static struct clk gpt9_fck = { - .name = "gpt9_fck", - .parent = &sys_clkin_ck, - .clksel = dmt1_clk_mux_sel, +/* Merged sgx_clk_mux into gpu */ +static struct clk gpu_fck = { + .name = "gpu_fck", + .parent = &dpll_core_m7_ck, + .clksel = sgx_clk_mux_sel, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, + .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK, .ops = &clkops_omap2_dflt, .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, + .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", + .clkdm_name = "l3_gfx_clkdm", }; static struct clk hdq1w_fck = { @@ -1735,11 +1632,16 @@ static struct clk hdq1w_fck = { .recalc = &followparent_recalc, }; +static const struct clksel hsi_fclk_div[] = { + { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates }, + { .parent = NULL }, +}; + /* Merged hsi_fclk into hsi */ -static struct clk hsi_ick = { - .name = "hsi_ick", +static struct clk hsi_fck = { + .name = "hsi_fck", .parent = &dpll_per_m2x2_ck, - .clksel = per_sgx_fclk_div, + .clksel = hsi_fclk_div, .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_24_25_MASK, .ops = &clkops_omap2_dflt, @@ -1791,6 +1693,26 @@ static struct clk i2c4_fck = { .recalc = &followparent_recalc, }; +static struct clk ipu_fck = { + .name = "ipu_fck", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .clkdm_name = "ducati_clkdm", + .parent = &ducati_clk_mux_ck, + .recalc = &followparent_recalc, +}; + +static struct clk iss_ctrlclk = { + .name = "iss_ctrlclk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT, + .clkdm_name = "iss_clkdm", + .parent = &func_96m_fclk, + .recalc = &followparent_recalc, +}; + static struct clk iss_fck = { .name = "iss_fck", .ops = &clkops_omap2_dflt, @@ -1801,8 +1723,8 @@ static struct clk iss_fck = { .recalc = &followparent_recalc, }; -static struct clk ivahd_ick = { - .name = "ivahd_ick", +static struct clk iva_fck = { + .name = "iva_fck", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, @@ -1811,8 +1733,8 @@ static struct clk ivahd_ick = { .recalc = &followparent_recalc, }; -static struct clk keyboard_fck = { - .name = "keyboard_fck", +static struct clk kbd_fck = { + .name = "kbd_fck", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, @@ -1821,8 +1743,8 @@ static struct clk keyboard_fck = { .recalc = &followparent_recalc, }; -static struct clk l3_instr_interconnect_ick = { - .name = "l3_instr_interconnect_ick", +static struct clk l3_instr_ick = { + .name = "l3_instr_ick", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, @@ -1831,8 +1753,8 @@ static struct clk l3_instr_interconnect_ick = { .recalc = &followparent_recalc, }; -static struct clk l3_interconnect_3_ick = { - .name = "l3_interconnect_3_ick", +static struct clk l3_main_3_ick = { + .name = "l3_main_3_ick", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, @@ -2005,6 +1927,16 @@ static struct clk mcbsp4_fck = { .clkdm_name = "l4_per_clkdm", }; +static struct clk mcpdm_fck = { + .name = "mcpdm_fck", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "abe_clkdm", + .parent = &pad_clks_ck, + .recalc = &followparent_recalc, +}; + static struct clk mcspi1_fck = { .name = "mcspi1_fck", .ops = &clkops_omap2_dflt, @@ -2105,33 +2037,33 @@ static struct clk mmc5_fck = { .recalc = &followparent_recalc, }; -static struct clk ocp_wp1_ick = { - .name = "ocp_wp1_ick", +static struct clk ocp2scp_usb_phy_phy_48m = { + .name = "ocp2scp_usb_phy_phy_48m", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l3_instr_clkdm", - .parent = &l3_div_ck, + .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, + .clkdm_name = "l3_init_clkdm", + .parent = &func_48m_fclk, .recalc = &followparent_recalc, }; -static struct clk pdm_fck = { - .name = "pdm_fck", +static struct clk ocp2scp_usb_phy_ick = { + .name = "ocp2scp_usb_phy_ick", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", - .parent = &pad_clks_ck, + .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .clkdm_name = "l3_init_clkdm", + .parent = &l4_div_ck, .recalc = &followparent_recalc, }; -static struct clk pkaeip29_fck = { - .name = "pkaeip29_fck", +static struct clk ocp_wp_noc_ick = { + .name = "ocp_wp_noc_ick", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_secure_clkdm", - .parent = &l4_div_ck, + .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .clkdm_name = "l3_instr_clkdm", + .parent = &l3_div_ck, .recalc = &followparent_recalc, }; @@ -2145,8 +2077,8 @@ static struct clk rng_ick = { .recalc = &followparent_recalc, }; -static struct clk sha2md51_fck = { - .name = "sha2md51_fck", +static struct clk sha2md5_fck = { + .name = "sha2md5_fck", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, @@ -2155,8 +2087,8 @@ static struct clk sha2md51_fck = { .recalc = &followparent_recalc, }; -static struct clk sl2_ick = { - .name = "sl2_ick", +static struct clk sl2if_ick = { + .name = "sl2if_ick", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, @@ -2165,6 +2097,46 @@ static struct clk sl2_ick = { .recalc = &followparent_recalc, }; +static struct clk slimbus1_fclk_1 = { + .name = "slimbus1_fclk_1", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_FCLK1_SHIFT, + .clkdm_name = "abe_clkdm", + .parent = &func_24m_clk, + .recalc = &followparent_recalc, +}; + +static struct clk slimbus1_fclk_0 = { + .name = "slimbus1_fclk_0", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_FCLK0_SHIFT, + .clkdm_name = "abe_clkdm", + .parent = &abe_24m_fclk, + .recalc = &followparent_recalc, +}; + +static struct clk slimbus1_fclk_2 = { + .name = "slimbus1_fclk_2", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_FCLK2_SHIFT, + .clkdm_name = "abe_clkdm", + .parent = &pad_clks_ck, + .recalc = &followparent_recalc, +}; + +static struct clk slimbus1_slimbus_clk = { + .name = "slimbus1_slimbus_clk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, + .clkdm_name = "abe_clkdm", + .parent = &slimbus_clk, + .recalc = &followparent_recalc, +}; + static struct clk slimbus1_fck = { .name = "slimbus1_fck", .ops = &clkops_omap2_dflt, @@ -2175,6 +2147,36 @@ static struct clk slimbus1_fck = { .recalc = &followparent_recalc, }; +static struct clk slimbus2_fclk_1 = { + .name = "slimbus2_fclk_1", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, + .clkdm_name = "l4_per_clkdm", + .parent = &per_abe_24m_fclk, + .recalc = &followparent_recalc, +}; + +static struct clk slimbus2_fclk_0 = { + .name = "slimbus2_fclk_0", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT, + .clkdm_name = "l4_per_clkdm", + .parent = &func_24mc_fclk, + .recalc = &followparent_recalc, +}; + +static struct clk slimbus2_slimbus_clk = { + .name = "slimbus2_slimbus_clk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, + .clkdm_name = "l4_per_clkdm", + .parent = &pad_slimbus_core_clks_ck, + .recalc = &followparent_recalc, +}; + static struct clk slimbus2_fck = { .name = "slimbus2_fck", .ops = &clkops_omap2_dflt, @@ -2185,8 +2187,8 @@ static struct clk slimbus2_fck = { .recalc = &followparent_recalc, }; -static struct clk sr_core_fck = { - .name = "sr_core_fck", +static struct clk smartreflex_core_fck = { + .name = "smartreflex_core_fck", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, @@ -2195,8 +2197,8 @@ static struct clk sr_core_fck = { .recalc = &followparent_recalc, }; -static struct clk sr_iva_fck = { - .name = "sr_iva_fck", +static struct clk smartreflex_iva_fck = { + .name = "smartreflex_iva_fck", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, @@ -2205,8 +2207,8 @@ static struct clk sr_iva_fck = { .recalc = &followparent_recalc, }; -static struct clk sr_mpu_fck = { - .name = "sr_mpu_fck", +static struct clk smartreflex_mpu_fck = { + .name = "smartreflex_mpu_fck", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, @@ -2215,14 +2217,175 @@ static struct clk sr_mpu_fck = { .recalc = &followparent_recalc, }; -static struct clk tesla_ick = { - .name = "tesla_ick", +/* Merged dmt1_clk_mux into timer1 */ +static struct clk timer1_fck = { + .name = "timer1_fck", + .parent = &sys_clkin_ck, + .clksel = abe_dpll_bypass_clk_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "tesla_clkdm", - .parent = &dpll_iva_m4_ck, - .recalc = &followparent_recalc, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_wkup_clkdm", +}; + +/* Merged cm2_dm10_mux into timer10 */ +static struct clk timer10_fck = { + .name = "timer10_fck", + .parent = &sys_clkin_ck, + .clksel = abe_dpll_bypass_clk_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, + .ops = &clkops_omap2_dflt, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_per_clkdm", +}; + +/* Merged cm2_dm11_mux into timer11 */ +static struct clk timer11_fck = { + .name = "timer11_fck", + .parent = &sys_clkin_ck, + .clksel = abe_dpll_bypass_clk_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, + .ops = &clkops_omap2_dflt, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_per_clkdm", +}; + +/* Merged cm2_dm2_mux into timer2 */ +static struct clk timer2_fck = { + .name = "timer2_fck", + .parent = &sys_clkin_ck, + .clksel = abe_dpll_bypass_clk_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, + .ops = &clkops_omap2_dflt, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_per_clkdm", +}; + +/* Merged cm2_dm3_mux into timer3 */ +static struct clk timer3_fck = { + .name = "timer3_fck", + .parent = &sys_clkin_ck, + .clksel = abe_dpll_bypass_clk_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, + .ops = &clkops_omap2_dflt, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_per_clkdm", +}; + +/* Merged cm2_dm4_mux into timer4 */ +static struct clk timer4_fck = { + .name = "timer4_fck", + .parent = &sys_clkin_ck, + .clksel = abe_dpll_bypass_clk_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, + .ops = &clkops_omap2_dflt, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_per_clkdm", +}; + +static const struct clksel timer5_sync_mux_sel[] = { + { .parent = &syc_clk_div_ck, .rates = div_1_0_rates }, + { .parent = &sys_32k_ck, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +/* Merged timer5_sync_mux into timer5 */ +static struct clk timer5_fck = { + .name = "timer5_fck", + .parent = &syc_clk_div_ck, + .clksel = timer5_sync_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, + .ops = &clkops_omap2_dflt, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "abe_clkdm", +}; + +/* Merged timer6_sync_mux into timer6 */ +static struct clk timer6_fck = { + .name = "timer6_fck", + .parent = &syc_clk_div_ck, + .clksel = timer5_sync_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, + .ops = &clkops_omap2_dflt, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "abe_clkdm", +}; + +/* Merged timer7_sync_mux into timer7 */ +static struct clk timer7_fck = { + .name = "timer7_fck", + .parent = &syc_clk_div_ck, + .clksel = timer5_sync_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, + .ops = &clkops_omap2_dflt, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "abe_clkdm", +}; + +/* Merged timer8_sync_mux into timer8 */ +static struct clk timer8_fck = { + .name = "timer8_fck", + .parent = &syc_clk_div_ck, + .clksel = timer5_sync_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, + .ops = &clkops_omap2_dflt, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "abe_clkdm", +}; + +/* Merged cm2_dm9_mux into timer9 */ +static struct clk timer9_fck = { + .name = "timer9_fck", + .parent = &sys_clkin_ck, + .clksel = abe_dpll_bypass_clk_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, + .ops = &clkops_omap2_dflt, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_per_clkdm", }; static struct clk uart1_fck = { @@ -2265,105 +2428,148 @@ static struct clk uart4_fck = { .recalc = &followparent_recalc, }; -static struct clk unipro1_fck = { - .name = "unipro1_fck", +static struct clk usb_host_fs_fck = { + .name = "usb_host_fs_fck", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL, + .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l3_init_clkdm", - .parent = &func_96m_fclk, + .parent = &func_48mc_fclk, .recalc = &followparent_recalc, }; -static struct clk usb_host_fck = { - .name = "usb_host_fck", +static struct clk usb_host_hs_utmi_p3_clk = { + .name = "usb_host_hs_utmi_p3_clk", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, .clkdm_name = "l3_init_clkdm", .parent = &init_60m_fclk, .recalc = &followparent_recalc, }; -static struct clk usb_host_fs_fck = { - .name = "usb_host_fs_fck", +static struct clk usb_host_hs_hsic60m_p1_clk = { + .name = "usb_host_hs_hsic60m_p1_clk", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, .clkdm_name = "l3_init_clkdm", - .parent = &func_48mc_fclk, + .parent = &init_60m_fclk, .recalc = &followparent_recalc, }; -static struct clk usb_otg_ick = { - .name = "usb_otg_ick", +static struct clk usb_host_hs_hsic60m_p2_clk = { + .name = "usb_host_hs_hsic60m_p2_clk", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, .clkdm_name = "l3_init_clkdm", - .parent = &l3_div_ck, + .parent = &init_60m_fclk, .recalc = &followparent_recalc, }; -static struct clk usb_tll_ick = { - .name = "usb_tll_ick", +static const struct clksel utmi_p1_gfclk_sel[] = { + { .parent = &init_60m_fclk, .rates = div_1_0_rates }, + { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +static struct clk utmi_p1_gfclk = { + .name = "utmi_p1_gfclk", + .parent = &init_60m_fclk, + .clksel = utmi_p1_gfclk_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk usb_host_hs_utmi_p1_clk = { + .name = "usb_host_hs_utmi_p1_clk", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT, .clkdm_name = "l3_init_clkdm", - .parent = &l4_div_ck, + .parent = &utmi_p1_gfclk, .recalc = &followparent_recalc, }; -static struct clk usbphyocp2scp_ick = { - .name = "usbphyocp2scp_ick", +static const struct clksel utmi_p2_gfclk_sel[] = { + { .parent = &init_60m_fclk, .rates = div_1_0_rates }, + { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +static struct clk utmi_p2_gfclk = { + .name = "utmi_p2_gfclk", + .parent = &init_60m_fclk, + .clksel = utmi_p2_gfclk_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk usb_host_hs_utmi_p2_clk = { + .name = "usb_host_hs_utmi_p2_clk", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT, .clkdm_name = "l3_init_clkdm", - .parent = &l4_div_ck, + .parent = &utmi_p2_gfclk, .recalc = &followparent_recalc, }; -static struct clk usim_fck = { - .name = "usim_fck", +static struct clk usb_host_hs_hsic480m_p1_clk = { + .name = "usb_host_hs_hsic480m_p1_clk", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_wkup_clkdm", - .parent = &sys_32k_ck, + .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT, + .clkdm_name = "l3_init_clkdm", + .parent = &dpll_usb_m2_ck, .recalc = &followparent_recalc, }; -static struct clk wdt2_fck = { - .name = "wdt2_fck", +static struct clk usb_host_hs_hsic480m_p2_clk = { + .name = "usb_host_hs_hsic480m_p2_clk", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_wkup_clkdm", - .parent = &sys_32k_ck, + .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT, + .clkdm_name = "l3_init_clkdm", + .parent = &dpll_usb_m2_ck, .recalc = &followparent_recalc, }; -static struct clk wdt3_fck = { - .name = "wdt3_fck", +static struct clk usb_host_hs_func48mclk = { + .name = "usb_host_hs_func48mclk", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, + .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT, + .clkdm_name = "l3_init_clkdm", + .parent = &func_48mc_fclk, + .recalc = &followparent_recalc, +}; + +static struct clk usb_host_hs_fck = { + .name = "usb_host_hs_fck", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", - .parent = &sys_32k_ck, + .clkdm_name = "l3_init_clkdm", + .parent = &init_60m_fclk, .recalc = &followparent_recalc, }; -/* Remaining optional clocks */ static const struct clksel otg_60m_gfclk_sel[] = { { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates }, { .parent = &xclk60motg_ck, .rates = div_1_1_rates }, { .parent = NULL }, }; -static struct clk otg_60m_gfclk_ck = { - .name = "otg_60m_gfclk_ck", +static struct clk otg_60m_gfclk = { + .name = "otg_60m_gfclk", .parent = &utmi_phy_clkout_ck, .clksel = otg_60m_gfclk_sel, .init = &omap2_init_clksel_parent, @@ -2373,38 +2579,74 @@ static struct clk otg_60m_gfclk_ck = { .recalc = &omap2_clksel_recalc, }; -static const struct clksel stm_clk_div_div[] = { - { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates }, - { .parent = NULL }, +static struct clk usb_otg_hs_xclk = { + .name = "usb_otg_hs_xclk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_XCLK_SHIFT, + .clkdm_name = "l3_init_clkdm", + .parent = &otg_60m_gfclk, + .recalc = &followparent_recalc, }; -static struct clk stm_clk_div_ck = { - .name = "stm_clk_div_ck", - .parent = &pmd_stm_clock_mux_ck, - .clksel = stm_clk_div_div, - .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_PMD_STM_CLK_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, +static struct clk usb_otg_hs_ick = { + .name = "usb_otg_hs_ick", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .clkdm_name = "l3_init_clkdm", + .parent = &l3_div_ck, + .recalc = &followparent_recalc, }; -static const struct clksel trace_clk_div_div[] = { - { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates }, - { .parent = NULL }, +static struct clk usb_phy_cm_clk32k = { + .name = "usb_phy_cm_clk32k", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_ALWON_USBPHY_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_CLK32K_SHIFT, + .clkdm_name = "l4_ao_clkdm", + .parent = &sys_32k_ck, + .recalc = &followparent_recalc, }; -static struct clk trace_clk_div_ck = { - .name = "trace_clk_div_ck", - .parent = &pmd_trace_clk_mux_ck, - .clksel = trace_clk_div_div, - .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, +static struct clk usb_tll_hs_usb_ch2_clk = { + .name = "usb_tll_hs_usb_ch2_clk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT, + .clkdm_name = "l3_init_clkdm", + .parent = &init_60m_fclk, + .recalc = &followparent_recalc, +}; + +static struct clk usb_tll_hs_usb_ch0_clk = { + .name = "usb_tll_hs_usb_ch0_clk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT, + .clkdm_name = "l3_init_clkdm", + .parent = &init_60m_fclk, + .recalc = &followparent_recalc, +}; + +static struct clk usb_tll_hs_usb_ch1_clk = { + .name = "usb_tll_hs_usb_ch1_clk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT, + .clkdm_name = "l3_init_clkdm", + .parent = &init_60m_fclk, + .recalc = &followparent_recalc, +}; + +static struct clk usb_tll_hs_ick = { + .name = "usb_tll_hs_ick", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .clkdm_name = "l3_init_clkdm", + .parent = &l4_div_ck, + .recalc = &followparent_recalc, }; static const struct clksel_rate div2_14to18_rates[] = { @@ -2418,8 +2660,8 @@ static const struct clksel usim_fclk_div[] = { { .parent = NULL }, }; -static struct clk usim_fclk = { - .name = "usim_fclk", +static struct clk usim_ck = { + .name = "usim_ck", .parent = &dpll_per_m4_ck, .clksel = usim_fclk_div, .clksel_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, @@ -2430,38 +2672,79 @@ static struct clk usim_fclk = { .set_rate = &omap2_clksel_set_rate, }; -static const struct clksel utmi_p1_gfclk_sel[] = { - { .parent = &init_60m_fclk, .rates = div_1_0_rates }, - { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates }, +static struct clk usim_fclk = { + .name = "usim_fclk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_FCLK_SHIFT, + .clkdm_name = "l4_wkup_clkdm", + .parent = &usim_ck, + .recalc = &followparent_recalc, +}; + +static struct clk usim_fck = { + .name = "usim_fck", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .clkdm_name = "l4_wkup_clkdm", + .parent = &sys_32k_ck, + .recalc = &followparent_recalc, +}; + +static struct clk wd_timer2_fck = { + .name = "wd_timer2_fck", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_wkup_clkdm", + .parent = &sys_32k_ck, + .recalc = &followparent_recalc, +}; + +static struct clk wd_timer3_fck = { + .name = "wd_timer3_fck", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "abe_clkdm", + .parent = &sys_32k_ck, + .recalc = &followparent_recalc, +}; + +/* Remaining optional clocks */ +static const struct clksel stm_clk_div_div[] = { + { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates }, { .parent = NULL }, }; -static struct clk utmi_p1_gfclk_ck = { - .name = "utmi_p1_gfclk_ck", - .parent = &init_60m_fclk, - .clksel = utmi_p1_gfclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK, +static struct clk stm_clk_div_ck = { + .name = "stm_clk_div_ck", + .parent = &pmd_stm_clock_mux_ck, + .clksel = stm_clk_div_div, + .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_PMD_STM_CLK_MASK, .ops = &clkops_null, .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, }; -static const struct clksel utmi_p2_gfclk_sel[] = { - { .parent = &init_60m_fclk, .rates = div_1_0_rates }, - { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates }, +static const struct clksel trace_clk_div_div[] = { + { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates }, { .parent = NULL }, }; -static struct clk utmi_p2_gfclk_ck = { - .name = "utmi_p2_gfclk_ck", - .parent = &init_60m_fclk, - .clksel = utmi_p2_gfclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK, +static struct clk trace_clk_div_ck = { + .name = "trace_clk_div_ck", + .parent = &pmd_trace_clk_mux_ck, + .clksel = trace_clk_div_div, + .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK, .ops = &clkops_null, .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, }; /* @@ -2483,11 +2766,12 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X), CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X), CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X), + CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck, CK_443X), CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X), CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X), CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X), CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X), - CLK(NULL, "dpll_sys_ref_clk", &dpll_sys_ref_clk, CK_443X), + CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X), CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X), CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X), CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X), @@ -2557,46 +2841,48 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "aes1_fck", &aes1_fck, CK_443X), CLK(NULL, "aes2_fck", &aes2_fck, CK_443X), CLK(NULL, "aess_fck", &aess_fck, CK_443X), - CLK(NULL, "cust_efuse_fck", &cust_efuse_fck, CK_443X), + CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X), CLK(NULL, "des3des_fck", &des3des_fck, CK_443X), CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), CLK(NULL, "dmic_fck", &dmic_fck, CK_443X), + CLK(NULL, "dsp_fck", &dsp_fck, CK_443X), + CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X), + CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X), + CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X), + CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X), CLK(NULL, "dss_fck", &dss_fck, CK_443X), - CLK(NULL, "ducati_ick", &ducati_ick, CK_443X), - CLK(NULL, "emif1_ick", &emif1_ick, CK_443X), - CLK(NULL, "emif2_ick", &emif2_ick, CK_443X), + CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X), + CLK(NULL, "emif1_fck", &emif1_fck, CK_443X), + CLK(NULL, "emif2_fck", &emif2_fck, CK_443X), CLK(NULL, "fdif_fck", &fdif_fck, CK_443X), - CLK(NULL, "per_sgx_fclk", &per_sgx_fclk, CK_443X), - CLK(NULL, "gfx_fck", &gfx_fck, CK_443X), + CLK(NULL, "fpka_fck", &fpka_fck, CK_443X), + CLK(NULL, "gpio1_dbck", &gpio1_dbclk, CK_443X), CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X), + CLK(NULL, "gpio2_dbck", &gpio2_dbclk, CK_443X), CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X), + CLK(NULL, "gpio3_dbck", &gpio3_dbclk, CK_443X), CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X), + CLK(NULL, "gpio4_dbck", &gpio4_dbclk, CK_443X), CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X), + CLK(NULL, "gpio5_dbck", &gpio5_dbclk, CK_443X), CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X), + CLK(NULL, "gpio6_dbck", &gpio6_dbclk, CK_443X), CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X), CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X), - CLK(NULL, "gpt1_fck", &gpt1_fck, CK_443X), - CLK(NULL, "gpt10_fck", &gpt10_fck, CK_443X), - CLK(NULL, "gpt11_fck", &gpt11_fck, CK_443X), - CLK(NULL, "gpt2_fck", &gpt2_fck, CK_443X), - CLK(NULL, "gpt3_fck", &gpt3_fck, CK_443X), - CLK(NULL, "gpt4_fck", &gpt4_fck, CK_443X), - CLK(NULL, "gpt5_fck", &gpt5_fck, CK_443X), - CLK(NULL, "gpt6_fck", &gpt6_fck, CK_443X), - CLK(NULL, "gpt7_fck", &gpt7_fck, CK_443X), - CLK(NULL, "gpt8_fck", &gpt8_fck, CK_443X), - CLK(NULL, "gpt9_fck", &gpt9_fck, CK_443X), + CLK(NULL, "gpu_fck", &gpu_fck, CK_443X), CLK("omap2_hdq.0", "fck", &hdq1w_fck, CK_443X), - CLK(NULL, "hsi_ick", &hsi_ick, CK_443X), + CLK(NULL, "hsi_fck", &hsi_fck, CK_443X), CLK("i2c_omap.1", "fck", &i2c1_fck, CK_443X), CLK("i2c_omap.2", "fck", &i2c2_fck, CK_443X), CLK("i2c_omap.3", "fck", &i2c3_fck, CK_443X), CLK("i2c_omap.4", "fck", &i2c4_fck, CK_443X), + CLK(NULL, "ipu_fck", &ipu_fck, CK_443X), + CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X), CLK(NULL, "iss_fck", &iss_fck, CK_443X), - CLK(NULL, "ivahd_ick", &ivahd_ick, CK_443X), - CLK(NULL, "keyboard_fck", &keyboard_fck, CK_443X), - CLK(NULL, "l3_instr_interconnect_ick", &l3_instr_interconnect_ick, CK_443X), - CLK(NULL, "l3_interconnect_3_ick", &l3_interconnect_3_ick, CK_443X), + CLK(NULL, "iva_fck", &iva_fck, CK_443X), + CLK(NULL, "kbd_fck", &kbd_fck, CK_443X), + CLK(NULL, "l3_instr_ick", &l3_instr_ick, CK_443X), + CLK(NULL, "l3_main_3_ick", &l3_main_3_ick, CK_443X), CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X), CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X), CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X), @@ -2607,6 +2893,7 @@ static struct omap_clk omap44xx_clks[] = { CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_443X), CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X), CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_443X), + CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X), CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_443X), CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_443X), CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_443X), @@ -2616,43 +2903,66 @@ static struct omap_clk omap44xx_clks[] = { CLK("mmci-omap-hs.2", "fck", &mmc3_fck, CK_443X), CLK("mmci-omap-hs.3", "fck", &mmc4_fck, CK_443X), CLK("mmci-omap-hs.4", "fck", &mmc5_fck, CK_443X), - CLK(NULL, "ocp_wp1_ick", &ocp_wp1_ick, CK_443X), - CLK(NULL, "pdm_fck", &pdm_fck, CK_443X), - CLK(NULL, "pkaeip29_fck", &pkaeip29_fck, CK_443X), + CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X), + CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X), + CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X), CLK("omap_rng", "ick", &rng_ick, CK_443X), - CLK(NULL, "sha2md51_fck", &sha2md51_fck, CK_443X), - CLK(NULL, "sl2_ick", &sl2_ick, CK_443X), + CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X), + CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X), + CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X), + CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X), + CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X), + CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X), CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X), + CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X), + CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X), + CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X), CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X), - CLK(NULL, "sr_core_fck", &sr_core_fck, CK_443X), - CLK(NULL, "sr_iva_fck", &sr_iva_fck, CK_443X), - CLK(NULL, "sr_mpu_fck", &sr_mpu_fck, CK_443X), - CLK(NULL, "tesla_ick", &tesla_ick, CK_443X), + CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X), + CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X), + CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X), + CLK(NULL, "gpt1_fck", &timer1_fck, CK_443X), + CLK(NULL, "gpt10_fck", &timer10_fck, CK_443X), + CLK(NULL, "gpt11_fck", &timer11_fck, CK_443X), + CLK(NULL, "gpt2_fck", &timer2_fck, CK_443X), + CLK(NULL, "gpt3_fck", &timer3_fck, CK_443X), + CLK(NULL, "gpt4_fck", &timer4_fck, CK_443X), + CLK(NULL, "gpt5_fck", &timer5_fck, CK_443X), + CLK(NULL, "gpt6_fck", &timer6_fck, CK_443X), + CLK(NULL, "gpt7_fck", &timer7_fck, CK_443X), + CLK(NULL, "gpt8_fck", &timer8_fck, CK_443X), + CLK(NULL, "gpt9_fck", &timer9_fck, CK_443X), CLK(NULL, "uart1_fck", &uart1_fck, CK_443X), CLK(NULL, "uart2_fck", &uart2_fck, CK_443X), CLK(NULL, "uart3_fck", &uart3_fck, CK_443X), CLK(NULL, "uart4_fck", &uart4_fck, CK_443X), - CLK(NULL, "unipro1_fck", &unipro1_fck, CK_443X), - CLK(NULL, "usb_host_fck", &usb_host_fck, CK_443X), CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X), - CLK("musb_hdrc", "ick", &usb_otg_ick, CK_443X), - CLK(NULL, "usb_tll_ick", &usb_tll_ick, CK_443X), - CLK(NULL, "usbphyocp2scp_ick", &usbphyocp2scp_ick, CK_443X), + CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X), + CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X), + CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X), + CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X), + CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X), + CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X), + CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X), + CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X), + CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X), + CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X), + CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X), + CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X), + CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X), + CLK("musb_hdrc", "ick", &usb_otg_hs_ick, CK_443X), + CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X), + CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X), + CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X), + CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X), + CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X), + CLK(NULL, "usim_ck", &usim_ck, CK_443X), + CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), CLK(NULL, "usim_fck", &usim_fck, CK_443X), - CLK("omap_wdt", "fck", &wdt2_fck, CK_443X), - CLK(NULL, "wdt3_fck", &wdt3_fck, CK_443X), - CLK(NULL, "otg_60m_gfclk_ck", &otg_60m_gfclk_ck, CK_443X), + CLK("omap_wdt", "fck", &wd_timer2_fck, CK_443X), + CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X), CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), - CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), - CLK(NULL, "utmi_p1_gfclk_ck", &utmi_p1_gfclk_ck, CK_443X), - CLK(NULL, "utmi_p2_gfclk_ck", &utmi_p2_gfclk_ck, CK_443X), - CLK(NULL, "gpio1_dbck", &dummy_ck, CK_443X), - CLK(NULL, "gpio2_dbck", &dummy_ck, CK_443X), - CLK(NULL, "gpio3_dbck", &dummy_ck, CK_443X), - CLK(NULL, "gpio4_dbck", &dummy_ck, CK_443X), - CLK(NULL, "gpio5_dbck", &dummy_ck, CK_443X), - CLK(NULL, "gpio6_dbck", &dummy_ck, CK_443X), CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X), CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X), CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X), @@ -2669,19 +2979,19 @@ static struct omap_clk omap44xx_clks[] = { CLK("i2c_omap.2", "ick", &dummy_ck, CK_443X), CLK("i2c_omap.3", "ick", &dummy_ck, CK_443X), CLK("i2c_omap.4", "ick", &dummy_ck, CK_443X), + CLK("mmci-omap-hs.0", "ick", &dummy_ck, CK_443X), + CLK("mmci-omap-hs.1", "ick", &dummy_ck, CK_443X), + CLK("mmci-omap-hs.2", "ick", &dummy_ck, CK_443X), + CLK("mmci-omap-hs.3", "ick", &dummy_ck, CK_443X), + CLK("mmci-omap-hs.4", "ick", &dummy_ck, CK_443X), CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X), CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X), CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X), CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X), - CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X), - CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X), - CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X), - CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X), - CLK("mmci-omap-hs.0", "ick", &dummy_ck, CK_443X), - CLK("mmci-omap-hs.1", "ick", &dummy_ck, CK_443X), - CLK("mmci-omap-hs.2", "ick", &dummy_ck, CK_443X), - CLK("mmci-omap-hs.3", "ick", &dummy_ck, CK_443X), - CLK("mmci-omap-hs.4", "ick", &dummy_ck, CK_443X), + CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X), + CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X), + CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X), + CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X), CLK(NULL, "uart1_ick", &dummy_ck, CK_443X), CLK(NULL, "uart2_ick", &dummy_ck, CK_443X), CLK(NULL, "uart3_ick", &dummy_ck, CK_443X), diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index 5d80cb897489..6fb61b1a0d46 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -258,97 +258,6 @@ static void _omap2_clkdm_set_hwsup(struct clockdomain *clkdm, int enable) } -/** - * _init_wkdep_usecount - initialize wkdep usecounts to match hardware - * @clkdm: clockdomain to initialize wkdep usecounts - * - * Initialize the wakeup dependency usecount variables for clockdomain @clkdm. - * If a wakeup dependency is present in the hardware, the usecount will be - * set to 1; otherwise, it will be set to 0. Software should clear all - * software wakeup dependencies prior to calling this function if it wishes - * to ensure that all usecounts start at 0. No return value. - */ -static void _init_wkdep_usecount(struct clockdomain *clkdm) -{ - u32 v; - struct clkdm_dep *cd; - - if (!clkdm->wkdep_srcs) - return; - - for (cd = clkdm->wkdep_srcs; cd->clkdm_name; cd++) { - if (!omap_chip_is(cd->omap_chip)) - continue; - - if (!cd->clkdm && cd->clkdm_name) - cd->clkdm = _clkdm_lookup(cd->clkdm_name); - - if (!cd->clkdm) { - WARN(!cd->clkdm, "clockdomain: %s: wkdep clkdm %s not " - "found\n", clkdm->name, cd->clkdm_name); - continue; - } - - v = prm_read_mod_bits_shift(clkdm->pwrdm.ptr->prcm_offs, - PM_WKDEP, - (1 << cd->clkdm->dep_bit)); - - if (v) - pr_debug("clockdomain: %s: wakeup dependency already " - "set to wake up when %s wakes\n", - clkdm->name, cd->clkdm->name); - - atomic_set(&cd->wkdep_usecount, (v) ? 1 : 0); - } -} - -/** - * _init_sleepdep_usecount - initialize sleepdep usecounts to match hardware - * @clkdm: clockdomain to initialize sleepdep usecounts - * - * Initialize the sleep dependency usecount variables for clockdomain @clkdm. - * If a sleep dependency is present in the hardware, the usecount will be - * set to 1; otherwise, it will be set to 0. Software should clear all - * software sleep dependencies prior to calling this function if it wishes - * to ensure that all usecounts start at 0. No return value. - */ -static void _init_sleepdep_usecount(struct clockdomain *clkdm) -{ - u32 v; - struct clkdm_dep *cd; - - if (!cpu_is_omap34xx()) - return; - - if (!clkdm->sleepdep_srcs) - return; - - for (cd = clkdm->sleepdep_srcs; cd->clkdm_name; cd++) { - if (!omap_chip_is(cd->omap_chip)) - continue; - - if (!cd->clkdm && cd->clkdm_name) - cd->clkdm = _clkdm_lookup(cd->clkdm_name); - - if (!cd->clkdm) { - WARN(!cd->clkdm, "clockdomain: %s: sleepdep clkdm %s " - "not found\n", clkdm->name, cd->clkdm_name); - continue; - } - - v = prm_read_mod_bits_shift(clkdm->pwrdm.ptr->prcm_offs, - OMAP3430_CM_SLEEPDEP, - (1 << cd->clkdm->dep_bit)); - - if (v) - pr_debug("clockdomain: %s: sleep dependency already " - "set to prevent from idling until %s " - "idles\n", clkdm->name, cd->clkdm->name); - - atomic_set(&cd->sleepdep_usecount, (v) ? 1 : 0); - } -}; - /* Public functions */ /** @@ -379,12 +288,17 @@ void clkdm_init(struct clockdomain **clkdms, _autodep_lookup(autodep); /* - * Ensure that the *dep_usecount registers reflect the current - * state of the PRCM. + * Put all clockdomains into software-supervised mode; PM code + * should later enable hardware-supervised mode as appropriate */ list_for_each_entry(clkdm, &clkdm_list, node) { - _init_wkdep_usecount(clkdm); - _init_sleepdep_usecount(clkdm); + if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) + omap2_clkdm_wakeup(clkdm); + else if (clkdm->flags & CLKDM_CAN_DISABLE_AUTO) + omap2_clkdm_deny_idle(clkdm); + + clkdm_clear_all_wkdeps(clkdm); + clkdm_clear_all_sleepdeps(clkdm); } } @@ -592,6 +506,9 @@ int clkdm_clear_all_wkdeps(struct clockdomain *clkdm) if (!omap_chip_is(cd->omap_chip)) continue; + if (!cd->clkdm && cd->clkdm_name) + cd->clkdm = _clkdm_lookup(cd->clkdm_name); + /* PRM accesses are slow, so minimize them */ mask |= 1 << cd->clkdm->dep_bit; atomic_set(&cd->wkdep_usecount, 0); @@ -752,6 +669,9 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm) if (!omap_chip_is(cd->omap_chip)) continue; + if (!cd->clkdm && cd->clkdm_name) + cd->clkdm = _clkdm_lookup(cd->clkdm_name); + /* PRM accesses are slow, so minimize them */ mask |= 1 << cd->clkdm->dep_bit; atomic_set(&cd->sleepdep_usecount, 0); diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index fe82b79d5f3b..4f959a7d881c 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h @@ -649,6 +649,8 @@ #define OMAP3430_ST_MCBSP2_MASK (1 << 0) /* CM_AUTOIDLE_PER */ +#define OMAP3630_AUTO_UART4_MASK (1 << 18) +#define OMAP3630_AUTO_UART4_SHIFT 18 #define OMAP3430_AUTO_GPIO6_MASK (1 << 17) #define OMAP3430_AUTO_GPIO6_SHIFT 17 #define OMAP3430_AUTO_GPIO5_MASK (1 << 16) diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h index ac8458e43252..0b72be433776 100644 --- a/arch/arm/mach-omap2/cm-regbits-44xx.h +++ b/arch/arm/mach-omap2/cm-regbits-44xx.h @@ -1,8 +1,8 @@ /* * OMAP44xx Clock Management register bits * - * Copyright (C) 2009 Texas Instruments, Inc. - * Copyright (C) 2009 Nokia Corporation + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * Copyright (C) 2009-2010 Nokia Corporation * * Paul Walmsley (paul@pwsan.com) * Rajendra Nayak (rnayak@ti.com) @@ -25,453 +25,459 @@ #include "cm.h" -/* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ +/* + * Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, + * CM_TESLA_DYNAMICDEP + */ #define OMAP4430_ABE_DYNDEP_SHIFT 3 -#define OMAP4430_ABE_DYNDEP_MASK BITFIELD(3, 3) +#define OMAP4430_ABE_DYNDEP_MASK (1 << 3) /* - * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, - * CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, - * CM_TESLA_STATICDEP + * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP, + * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, + * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP */ #define OMAP4430_ABE_STATDEP_SHIFT 3 -#define OMAP4430_ABE_STATDEP_MASK BITFIELD(3, 3) +#define OMAP4430_ABE_STATDEP_MASK (1 << 3) -/* Used by CM_L4CFG_DYNAMICDEP */ +/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ #define OMAP4430_ALWONCORE_DYNDEP_SHIFT 16 -#define OMAP4430_ALWONCORE_DYNDEP_MASK BITFIELD(16, 16) +#define OMAP4430_ALWONCORE_DYNDEP_MASK (1 << 16) /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_ALWONCORE_STATDEP_SHIFT 16 -#define OMAP4430_ALWONCORE_STATDEP_MASK BITFIELD(16, 16) +#define OMAP4430_ALWONCORE_STATDEP_MASK (1 << 16) /* - * Used by CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB, - * CM_AUTOIDLE_DPLL_CORE_RESTORE, CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, - * CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU + * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, + * CM_AUTOIDLE_DPLL_CORE_RESTORE, CM_AUTOIDLE_DPLL_DDRPHY, + * CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER, + * CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB */ #define OMAP4430_AUTO_DPLL_MODE_SHIFT 0 -#define OMAP4430_AUTO_DPLL_MODE_MASK BITFIELD(0, 2) +#define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0) -/* Used by CM_L4CFG_DYNAMICDEP */ +/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ #define OMAP4430_CEFUSE_DYNDEP_SHIFT 17 -#define OMAP4430_CEFUSE_DYNDEP_MASK BITFIELD(17, 17) +#define OMAP4430_CEFUSE_DYNDEP_MASK (1 << 17) /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_CEFUSE_STATDEP_SHIFT 17 -#define OMAP4430_CEFUSE_STATDEP_MASK BITFIELD(17, 17) +#define OMAP4430_CEFUSE_STATDEP_MASK (1 << 17) /* Used by CM1_ABE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT 13 -#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK BITFIELD(13, 13) +#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK (1 << 13) /* Used by CM1_ABE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT 12 -#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK BITFIELD(12, 12) +#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK (1 << 12) /* Used by CM_WKUP_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK BITFIELD(9, 9) +#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK (1 << 9) /* Used by CM1_ABE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK BITFIELD(11, 11) +#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK (1 << 11) /* Used by CM1_ABE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8) /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK BITFIELD(11, 11) +#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK (1 << 11) /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT 12 -#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK BITFIELD(12, 12) +#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK (1 << 12) /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT 13 -#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK BITFIELD(13, 13) +#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK (1 << 13) /* Used by CM_CAM_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK BITFIELD(9, 9) +#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK (1 << 9) + +/* Used by CM_ALWON_CLKSTCTRL */ +#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_SHIFT 12 +#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_MASK (1 << 12) /* Used by CM_EMU_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK BITFIELD(9, 9) +#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK (1 << 9) /* Used by CM_CEFUSE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK BITFIELD(9, 9) +#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9) /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_DLL_CLK_MASK BITFIELD(9, 9) +#define OMAP4430_CLKACTIVITY_DLL_CLK_MASK (1 << 9) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK BITFIELD(9, 9) +#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK (1 << 9) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK BITFIELD(10, 10) +#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK (1 << 10) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK BITFIELD(11, 11) +#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK (1 << 11) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT 12 -#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK BITFIELD(12, 12) +#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK (1 << 12) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT 13 -#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK BITFIELD(13, 13) +#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK (1 << 13) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT 14 -#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK BITFIELD(14, 14) +#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK (1 << 14) /* Used by CM_DSS_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK BITFIELD(10, 10) +#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK (1 << 10) /* Used by CM_DSS_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK BITFIELD(9, 9) +#define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK (1 << 9) /* Used by CM_DUCATI_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK BITFIELD(8, 8) - -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK_MASK BITFIELD(10, 10) +#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK (1 << 8) /* Used by CM_EMU_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK (1 << 8) /* Used by CM_CAM_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK BITFIELD(10, 10) +#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK (1 << 10) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT 15 -#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK BITFIELD(15, 15) +#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK (1 << 15) /* Used by CM1_ABE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK BITFIELD(10, 10) +#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK (1 << 10) /* Used by CM_DSS_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK BITFIELD(11, 11) +#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK (1 << 11) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20 -#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK BITFIELD(20, 20) +#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26 -#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK BITFIELD(26, 26) +#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21 -#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK BITFIELD(21, 21) +#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27 -#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK BITFIELD(27, 27) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_INIT_32K_GFCLK_SHIFT 31 -#define OMAP4430_CLKACTIVITY_INIT_32K_GFCLK_MASK BITFIELD(31, 31) +#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT 13 -#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK BITFIELD(13, 13) +#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK (1 << 13) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT 12 -#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK BITFIELD(12, 12) +#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK (1 << 12) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT 28 -#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK BITFIELD(28, 28) +#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK (1 << 28) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT 29 -#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK BITFIELD(29, 29) +#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK (1 << 29) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK BITFIELD(11, 11) +#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK (1 << 11) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT 16 -#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK BITFIELD(16, 16) +#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK (1 << 16) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT 17 -#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK BITFIELD(17, 17) +#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK (1 << 17) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT 18 -#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK BITFIELD(18, 18) +#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK (1 << 18) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT 19 -#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK BITFIELD(19, 19) +#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK (1 << 19) /* Used by CM_CAM_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK (1 << 8) /* Used by CM_IVAHD_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK (1 << 8) -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK_SHIFT 14 -#define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK_MASK BITFIELD(14, 14) +/* Used by CM_D2D_CLKSTCTRL */ +#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT 10 +#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK (1 << 10) /* Used by CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK (1 << 8) /* Used by CM_L3_2_CLKSTCTRL, CM_L3_2_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK (1 << 8) /* Used by CM_D2D_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK (1 << 8) /* Used by CM_SDMA_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK (1 << 8) /* Used by CM_DSS_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK (1 << 8) /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK (1 << 8) /* Used by CM_GFX_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK (1 << 8) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK (1 << 8) /* Used by CM_L3INSTR_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK (1 << 8) /* Used by CM_L4SEC_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK (1 << 8) /* Used by CM_ALWON_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK (1 << 8) /* Used by CM_CEFUSE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8) /* Used by CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK (1 << 8) /* Used by CM_D2D_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK BITFIELD(9, 9) +#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK (1 << 9) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK BITFIELD(9, 9) +#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK (1 << 9) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK (1 << 8) /* Used by CM_L4SEC_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK BITFIELD(9, 9) +#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK (1 << 9) /* Used by CM_WKUP_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT 12 -#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK BITFIELD(12, 12) +#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK (1 << 12) /* Used by CM_MPU_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK (1 << 8) /* Used by CM1_ABE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK BITFIELD(9, 9) +#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK (1 << 9) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT 16 -#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK BITFIELD(16, 16) +#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK (1 << 16) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17 -#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK BITFIELD(17, 17) +#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18 -#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK BITFIELD(18, 18) +#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19 -#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK BITFIELD(19, 19) +#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT 25 -#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK BITFIELD(25, 25) - -/* Used by CM_EMU_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_PER_DPLL_EMU_CLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_PER_DPLL_EMU_CLK_MASK BITFIELD(10, 10) +#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK (1 << 25) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT 20 -#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK BITFIELD(20, 20) +#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK (1 << 20) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT 21 -#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK BITFIELD(21, 21) +#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK (1 << 21) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT 22 -#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK BITFIELD(22, 22) +#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK (1 << 22) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT 24 -#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK BITFIELD(24, 24) +#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK (1 << 24) /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK BITFIELD(10, 10) +#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK (1 << 10) /* Used by CM_GFX_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK BITFIELD(9, 9) +#define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK (1 << 9) /* Used by CM_ALWON_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK BITFIELD(11, 11) +#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK (1 << 11) /* Used by CM_ALWON_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK BITFIELD(10, 10) +#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK (1 << 10) /* Used by CM_ALWON_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK BITFIELD(9, 9) +#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK (1 << 9) /* Used by CM_WKUP_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_SYS_CLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_SYS_CLK_MASK (1 << 8) /* Used by CM_TESLA_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK (1 << 8) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22 -#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK BITFIELD(22, 22) +#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23 -#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK BITFIELD(23, 23) +#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24 -#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK BITFIELD(24, 24) +#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24) + +/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ +#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT 10 +#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK (1 << 10) + +/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ +#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14 +#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15 -#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK BITFIELD(15, 15) +#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15) /* Used by CM_WKUP_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK BITFIELD(10, 10) +#define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK (1 << 10) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30 -#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK BITFIELD(30, 30) +#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25 -#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK BITFIELD(25, 25) +#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25) /* Used by CM_WKUP_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK BITFIELD(11, 11) +#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK (1 << 11) /* - * Used by CM_WKUP_TIMER1_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL, + * Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, + * CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, + * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MMC6_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL, * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL, * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL, * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, - * CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MMC6_CLKCTRL, - * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, - * CM1_ABE_TIMER8_CLKCTRL + * CM_WKUP_TIMER1_CLKCTRL */ #define OMAP4430_CLKSEL_SHIFT 24 -#define OMAP4430_CLKSEL_MASK BITFIELD(24, 24) +#define OMAP4430_CLKSEL_MASK (1 << 24) /* * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL, - * CM_DPLL_SYS_REF_CLKSEL, CM_L4_WKUP_CLKSEL, CM_CLKSEL_DUCATI_ISS_ROOT, - * CM_CLKSEL_USB_60MHZ + * CM_L4_WKUP_CLKSEL, CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ */ #define OMAP4430_CLKSEL_0_0_SHIFT 0 -#define OMAP4430_CLKSEL_0_0_MASK BITFIELD(0, 0) +#define OMAP4430_CLKSEL_0_0_MASK (1 << 0) /* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */ #define OMAP4430_CLKSEL_0_1_SHIFT 0 -#define OMAP4430_CLKSEL_0_1_MASK BITFIELD(0, 1) +#define OMAP4430_CLKSEL_0_1_MASK (0x3 << 0) /* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */ #define OMAP4430_CLKSEL_24_25_SHIFT 24 -#define OMAP4430_CLKSEL_24_25_MASK BITFIELD(24, 25) +#define OMAP4430_CLKSEL_24_25_MASK (0x3 << 24) /* Used by CM_L3INIT_USB_OTG_CLKCTRL */ #define OMAP4430_CLKSEL_60M_SHIFT 24 -#define OMAP4430_CLKSEL_60M_MASK BITFIELD(24, 24) +#define OMAP4430_CLKSEL_60M_MASK (1 << 24) /* Used by CM1_ABE_AESS_CLKCTRL */ #define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24 -#define OMAP4430_CLKSEL_AESS_FCLK_MASK BITFIELD(24, 24) +#define OMAP4430_CLKSEL_AESS_FCLK_MASK (1 << 24) -/* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */ +/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */ #define OMAP4430_CLKSEL_CORE_SHIFT 0 -#define OMAP4430_CLKSEL_CORE_MASK BITFIELD(0, 0) +#define OMAP4430_CLKSEL_CORE_MASK (1 << 0) -/* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */ +/* + * Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2_RESTORE, + * CM_SHADOW_FREQ_CONFIG2 + */ #define OMAP4430_CLKSEL_CORE_1_1_SHIFT 1 -#define OMAP4430_CLKSEL_CORE_1_1_MASK BITFIELD(1, 1) +#define OMAP4430_CLKSEL_CORE_1_1_MASK (1 << 1) /* Used by CM_WKUP_USIM_CLKCTRL */ #define OMAP4430_CLKSEL_DIV_SHIFT 24 -#define OMAP4430_CLKSEL_DIV_MASK BITFIELD(24, 24) +#define OMAP4430_CLKSEL_DIV_MASK (1 << 24) /* Used by CM_CAM_FDIF_CLKCTRL */ #define OMAP4430_CLKSEL_FCLK_SHIFT 24 -#define OMAP4430_CLKSEL_FCLK_MASK BITFIELD(24, 25) +#define OMAP4430_CLKSEL_FCLK_MASK (0x3 << 24) /* Used by CM_L4PER_MCBSP4_CLKCTRL */ #define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT 25 -#define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK BITFIELD(25, 25) +#define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK (1 << 25) /* * Renamed from CLKSEL_INTERNAL_SOURCE Used by CM1_ABE_DMIC_CLKCTRL, @@ -479,836 +485,869 @@ * CM1_ABE_MCBSP3_CLKCTRL */ #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT 26 -#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK BITFIELD(26, 27) +#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK (0x3 << 26) -/* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */ +/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */ #define OMAP4430_CLKSEL_L3_SHIFT 4 -#define OMAP4430_CLKSEL_L3_MASK BITFIELD(4, 4) +#define OMAP4430_CLKSEL_L3_MASK (1 << 4) -/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */ +/* + * Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2_RESTORE, + * CM_SHADOW_FREQ_CONFIG2 + */ #define OMAP4430_CLKSEL_L3_SHADOW_SHIFT 2 -#define OMAP4430_CLKSEL_L3_SHADOW_MASK BITFIELD(2, 2) +#define OMAP4430_CLKSEL_L3_SHADOW_MASK (1 << 2) -/* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */ +/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */ #define OMAP4430_CLKSEL_L4_SHIFT 8 -#define OMAP4430_CLKSEL_L4_MASK BITFIELD(8, 8) +#define OMAP4430_CLKSEL_L4_MASK (1 << 8) /* Used by CM_CLKSEL_ABE */ #define OMAP4430_CLKSEL_OPP_SHIFT 0 -#define OMAP4430_CLKSEL_OPP_MASK BITFIELD(0, 1) - -/* Used by CM_GFX_GFX_CLKCTRL */ -#define OMAP4430_CLKSEL_PER_192M_SHIFT 25 -#define OMAP4430_CLKSEL_PER_192M_MASK BITFIELD(25, 26) +#define OMAP4430_CLKSEL_OPP_MASK (0x3 << 0) /* Used by CM_EMU_DEBUGSS_CLKCTRL */ #define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT 27 -#define OMAP4430_CLKSEL_PMD_STM_CLK_MASK BITFIELD(27, 29) +#define OMAP4430_CLKSEL_PMD_STM_CLK_MASK (0x7 << 27) /* Used by CM_EMU_DEBUGSS_CLKCTRL */ #define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT 24 -#define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK BITFIELD(24, 26) +#define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK (0x7 << 24) /* Used by CM_GFX_GFX_CLKCTRL */ #define OMAP4430_CLKSEL_SGX_FCLK_SHIFT 24 -#define OMAP4430_CLKSEL_SGX_FCLK_MASK BITFIELD(24, 24) +#define OMAP4430_CLKSEL_SGX_FCLK_MASK (1 << 24) /* * Used by CM1_ABE_DMIC_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL */ #define OMAP4430_CLKSEL_SOURCE_SHIFT 24 -#define OMAP4430_CLKSEL_SOURCE_MASK BITFIELD(24, 25) +#define OMAP4430_CLKSEL_SOURCE_MASK (0x3 << 24) /* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */ #define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT 24 -#define OMAP4430_CLKSEL_SOURCE_24_24_MASK BITFIELD(24, 24) +#define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ #define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24 -#define OMAP4430_CLKSEL_UTMI_P1_MASK BITFIELD(24, 24) +#define OMAP4430_CLKSEL_UTMI_P1_MASK (1 << 24) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ #define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25 -#define OMAP4430_CLKSEL_UTMI_P2_MASK BITFIELD(25, 25) +#define OMAP4430_CLKSEL_UTMI_P2_MASK (1 << 25) /* - * Used by CM_WKUP_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_D2D_CLKSTCTRL, - * CM_DUCATI_CLKSTCTRL, CM_L3INSTR_CLKSTCTRL, CM_L3_1_CLKSTCTRL, - * CM_L3_2_CLKSTCTRL, CM_L4CFG_CLKSTCTRL, CM_MEMIF_CLKSTCTRL, - * CM_SDMA_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_L4PER_CLKSTCTRL, CM_L4SEC_CLKSTCTRL, - * CM_L3INIT_CLKSTCTRL, CM_CAM_CLKSTCTRL, CM_CEFUSE_CLKSTCTRL, - * CM_L3INIT_CLKSTCTRL_RESTORE, CM_L3_1_CLKSTCTRL_RESTORE, - * CM_L3_2_CLKSTCTRL_RESTORE, CM_L4CFG_CLKSTCTRL_RESTORE, - * CM_L4PER_CLKSTCTRL_RESTORE, CM_MEMIF_CLKSTCTRL_RESTORE, CM_ALWON_CLKSTCTRL, - * CM_IVAHD_CLKSTCTRL, CM_DSS_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_TESLA_CLKSTCTRL, - * CM1_ABE_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE + * Used by CM1_ABE_CLKSTCTRL, CM_ALWON_CLKSTCTRL, CM_CAM_CLKSTCTRL, + * CM_CEFUSE_CLKSTCTRL, CM_D2D_CLKSTCTRL, CM_DSS_CLKSTCTRL, + * CM_DUCATI_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_IVAHD_CLKSTCTRL, + * CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE, CM_L3INSTR_CLKSTCTRL, + * CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE, CM_L3_2_CLKSTCTRL, + * CM_L3_2_CLKSTCTRL_RESTORE, CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE, + * CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE, CM_L4SEC_CLKSTCTRL, + * CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE, CM_MPU_CLKSTCTRL, + * CM_MPU_CLKSTCTRL_RESTORE, CM_SDMA_CLKSTCTRL, CM_TESLA_CLKSTCTRL, + * CM_WKUP_CLKSTCTRL */ #define OMAP4430_CLKTRCTRL_SHIFT 0 -#define OMAP4430_CLKTRCTRL_MASK BITFIELD(0, 1) +#define OMAP4430_CLKTRCTRL_MASK (0x3 << 0) /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ #define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT 0 -#define OMAP4430_CORE_DPLL_EMU_DIV_MASK BITFIELD(0, 6) +#define OMAP4430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0) /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ #define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT 8 -#define OMAP4430_CORE_DPLL_EMU_MULT_MASK BITFIELD(8, 18) +#define OMAP4430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8) + +/* Used by REVISION_CM1, REVISION_CM2 */ +#define OMAP4430_CUSTOM_SHIFT 6 +#define OMAP4430_CUSTOM_MASK (0x3 << 6) -/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ +/* + * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, + * CM_L4CFG_DYNAMICDEP_RESTORE + */ #define OMAP4430_D2D_DYNDEP_SHIFT 18 -#define OMAP4430_D2D_DYNDEP_MASK BITFIELD(18, 18) +#define OMAP4430_D2D_DYNDEP_MASK (1 << 18) /* Used by CM_MPU_STATICDEP */ #define OMAP4430_D2D_STATDEP_SHIFT 18 -#define OMAP4430_D2D_STATDEP_MASK BITFIELD(18, 18) +#define OMAP4430_D2D_STATDEP_MASK (1 << 18) /* - * Used by CM_SSC_DELTAMSTEP_DPLL_PER, CM_SSC_DELTAMSTEP_DPLL_UNIPRO, - * CM_SSC_DELTAMSTEP_DPLL_USB, CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE, - * CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE, - * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA, - * CM_SSC_DELTAMSTEP_DPLL_MPU + * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE, + * CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE, CM_SSC_DELTAMSTEP_DPLL_DDRPHY, + * CM_SSC_DELTAMSTEP_DPLL_IVA, CM_SSC_DELTAMSTEP_DPLL_MPU, + * CM_SSC_DELTAMSTEP_DPLL_PER, CM_SSC_DELTAMSTEP_DPLL_UNIPRO, + * CM_SSC_DELTAMSTEP_DPLL_USB */ #define OMAP4430_DELTAMSTEP_SHIFT 0 -#define OMAP4430_DELTAMSTEP_MASK BITFIELD(0, 19) +#define OMAP4430_DELTAMSTEP_MASK (0xfffff << 0) -/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ +/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ #define OMAP4430_DLL_OVERRIDE_SHIFT 2 -#define OMAP4430_DLL_OVERRIDE_MASK BITFIELD(2, 2) +#define OMAP4430_DLL_OVERRIDE_MASK (1 << 2) /* Renamed from DLL_OVERRIDE Used by CM_DLL_CTRL */ #define OMAP4430_DLL_OVERRIDE_0_0_SHIFT 0 -#define OMAP4430_DLL_OVERRIDE_0_0_MASK BITFIELD(0, 0) +#define OMAP4430_DLL_OVERRIDE_0_0_MASK (1 << 0) -/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ +/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ #define OMAP4430_DLL_RESET_SHIFT 3 -#define OMAP4430_DLL_RESET_MASK BITFIELD(3, 3) +#define OMAP4430_DLL_RESET_MASK (1 << 3) /* - * Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB, - * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, - * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU + * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, + * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, + * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO, + * CM_CLKSEL_DPLL_USB */ #define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23 -#define OMAP4430_DPLL_BYP_CLKSEL_MASK BITFIELD(23, 23) +#define OMAP4430_DPLL_BYP_CLKSEL_MASK (1 << 23) /* Used by CM_CLKDCOLDO_DPLL_USB */ #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8 -#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK BITFIELD(8, 8) +#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8) -/* Used by CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_CORE */ +/* Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_CORE_RESTORE */ #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20 -#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK BITFIELD(20, 20) +#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20) /* - * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, - * CM_DIV_M3_DPLL_CORE + * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, + * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER */ #define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT 0 -#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK BITFIELD(0, 4) +#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0) /* - * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, - * CM_DIV_M3_DPLL_CORE + * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, + * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER */ #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT 5 -#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK BITFIELD(5, 5) +#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK (1 << 5) /* - * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, - * CM_DIV_M3_DPLL_CORE + * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, + * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER */ #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8 -#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK BITFIELD(8, 8) +#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK (1 << 8) -/* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, CM_DIV_M2_DPLL_ABE */ +/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */ #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT 10 -#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK BITFIELD(10, 10) +#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10) /* - * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, - * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, - * CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU + * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, + * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU, + * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */ #define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0 -#define OMAP4430_DPLL_CLKOUT_DIV_MASK BITFIELD(0, 4) +#define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0) /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */ #define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT 0 -#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK BITFIELD(0, 6) +#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0) /* - * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, - * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, - * CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU + * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, + * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU, + * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */ #define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT 5 -#define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK BITFIELD(5, 5) +#define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5) /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */ #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT 7 -#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK BITFIELD(7, 7) +#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK (1 << 7) /* - * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB, CM_DIV_M2_DPLL_CORE_RESTORE, - * CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, - * CM_DIV_M2_DPLL_MPU + * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, + * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU, + * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB */ #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT 8 -#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK BITFIELD(8, 8) +#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) -/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ +/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ #define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT 8 -#define OMAP4430_DPLL_CORE_DPLL_EN_MASK BITFIELD(8, 10) +#define OMAP4430_DPLL_CORE_DPLL_EN_MASK (0x7 << 8) -/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ +/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ #define OMAP4430_DPLL_CORE_M2_DIV_SHIFT 11 -#define OMAP4430_DPLL_CORE_M2_DIV_MASK BITFIELD(11, 15) +#define OMAP4430_DPLL_CORE_M2_DIV_MASK (0x1f << 11) -/* Used by CM_SHADOW_FREQ_CONFIG2 */ +/* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */ #define OMAP4430_DPLL_CORE_M5_DIV_SHIFT 3 -#define OMAP4430_DPLL_CORE_M5_DIV_MASK BITFIELD(3, 7) - -/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ -#define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL_SHIFT 1 -#define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL_MASK BITFIELD(1, 1) +#define OMAP4430_DPLL_CORE_M5_DIV_MASK (0x1f << 3) /* - * Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO, - * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, - * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU + * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, + * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, + * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO */ #define OMAP4430_DPLL_DIV_SHIFT 0 -#define OMAP4430_DPLL_DIV_MASK BITFIELD(0, 6) +#define OMAP4430_DPLL_DIV_MASK (0x7f << 0) /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */ #define OMAP4430_DPLL_DIV_0_7_SHIFT 0 -#define OMAP4430_DPLL_DIV_0_7_MASK BITFIELD(0, 7) +#define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0) /* - * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_USB, - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, - * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU + * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, + * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, + * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER */ #define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT 8 -#define OMAP4430_DPLL_DRIFTGUARD_EN_MASK BITFIELD(8, 8) +#define OMAP4430_DPLL_DRIFTGUARD_EN_MASK (1 << 8) /* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */ #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT 3 -#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK BITFIELD(3, 3) +#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK (1 << 3) /* - * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB, - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, - * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU + * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, + * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, + * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, + * CM_CLKMODE_DPLL_USB */ #define OMAP4430_DPLL_EN_SHIFT 0 -#define OMAP4430_DPLL_EN_MASK BITFIELD(0, 2) +#define OMAP4430_DPLL_EN_MASK (0x7 << 0) /* - * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, - * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU + * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, + * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, + * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO */ #define OMAP4430_DPLL_LPMODE_EN_SHIFT 10 -#define OMAP4430_DPLL_LPMODE_EN_MASK BITFIELD(10, 10) +#define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10) /* - * Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO, - * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, - * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU + * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, + * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, + * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO */ #define OMAP4430_DPLL_MULT_SHIFT 8 -#define OMAP4430_DPLL_MULT_MASK BITFIELD(8, 18) +#define OMAP4430_DPLL_MULT_MASK (0x7ff << 8) /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */ #define OMAP4430_DPLL_MULT_USB_SHIFT 8 -#define OMAP4430_DPLL_MULT_USB_MASK BITFIELD(8, 19) +#define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8) /* - * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, - * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU + * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, + * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, + * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO */ #define OMAP4430_DPLL_REGM4XEN_SHIFT 11 -#define OMAP4430_DPLL_REGM4XEN_MASK BITFIELD(11, 11) +#define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11) /* Used by CM_CLKSEL_DPLL_USB */ #define OMAP4430_DPLL_SD_DIV_SHIFT 24 -#define OMAP4430_DPLL_SD_DIV_MASK BITFIELD(24, 31) +#define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24) /* - * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB, - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, - * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU + * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, + * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, + * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, + * CM_CLKMODE_DPLL_USB */ #define OMAP4430_DPLL_SSC_ACK_SHIFT 13 -#define OMAP4430_DPLL_SSC_ACK_MASK BITFIELD(13, 13) +#define OMAP4430_DPLL_SSC_ACK_MASK (1 << 13) /* - * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB, - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, - * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU + * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, + * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, + * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, + * CM_CLKMODE_DPLL_USB */ #define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT 14 -#define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK BITFIELD(14, 14) +#define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) /* - * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB, - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, - * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU + * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, + * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, + * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, + * CM_CLKMODE_DPLL_USB */ #define OMAP4430_DPLL_SSC_EN_SHIFT 12 -#define OMAP4430_DPLL_SSC_EN_MASK BITFIELD(12, 12) +#define OMAP4430_DPLL_SSC_EN_MASK (1 << 12) -/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ +/* + * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, + * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE + */ #define OMAP4430_DSS_DYNDEP_SHIFT 8 -#define OMAP4430_DSS_DYNDEP_MASK BITFIELD(8, 8) +#define OMAP4430_DSS_DYNDEP_MASK (1 << 8) /* - * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, - * CM_MPU_STATICDEP + * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, + * CM_SDMA_STATICDEP_RESTORE */ #define OMAP4430_DSS_STATDEP_SHIFT 8 -#define OMAP4430_DSS_STATDEP_MASK BITFIELD(8, 8) +#define OMAP4430_DSS_STATDEP_MASK (1 << 8) -/* Used by CM_L3_2_DYNAMICDEP */ +/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */ #define OMAP4430_DUCATI_DYNDEP_SHIFT 0 -#define OMAP4430_DUCATI_DYNDEP_MASK BITFIELD(0, 0) +#define OMAP4430_DUCATI_DYNDEP_MASK (1 << 0) -/* Used by CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP */ +/* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE */ #define OMAP4430_DUCATI_STATDEP_SHIFT 0 -#define OMAP4430_DUCATI_STATDEP_MASK BITFIELD(0, 0) +#define OMAP4430_DUCATI_STATDEP_MASK (1 << 0) -/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ +/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ #define OMAP4430_FREQ_UPDATE_SHIFT 0 -#define OMAP4430_FREQ_UPDATE_MASK BITFIELD(0, 0) +#define OMAP4430_FREQ_UPDATE_MASK (1 << 0) + +/* Used by REVISION_CM1, REVISION_CM2 */ +#define OMAP4430_FUNC_SHIFT 16 +#define OMAP4430_FUNC_MASK (0xfff << 16) -/* Used by CM_L3_2_DYNAMICDEP */ +/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */ #define OMAP4430_GFX_DYNDEP_SHIFT 10 -#define OMAP4430_GFX_DYNDEP_MASK BITFIELD(10, 10) +#define OMAP4430_GFX_DYNDEP_MASK (1 << 10) /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ #define OMAP4430_GFX_STATDEP_SHIFT 10 -#define OMAP4430_GFX_STATDEP_MASK BITFIELD(10, 10) +#define OMAP4430_GFX_STATDEP_MASK (1 << 10) -/* Used by CM_SHADOW_FREQ_CONFIG2 */ +/* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */ #define OMAP4430_GPMC_FREQ_UPDATE_SHIFT 0 -#define OMAP4430_GPMC_FREQ_UPDATE_MASK BITFIELD(0, 0) +#define OMAP4430_GPMC_FREQ_UPDATE_MASK (1 << 0) /* - * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, - * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA + * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, + * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 -#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK BITFIELD(0, 4) +#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0) /* - * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, - * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA + * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, + * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5 -#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK BITFIELD(5, 5) +#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5) /* - * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, - * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA + * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, + * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8 -#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK BITFIELD(8, 8) +#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8) /* - * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, - * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA + * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, + * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12 -#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK BITFIELD(12, 12) +#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12) /* - * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, - * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA + * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, + * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 -#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK BITFIELD(0, 4) +#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0) /* - * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, - * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA + * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, + * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5 -#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK BITFIELD(5, 5) +#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5) /* - * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, - * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA + * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, + * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8 -#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK BITFIELD(8, 8) +#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8) /* - * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, - * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA + * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, + * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12 -#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK BITFIELD(12, 12) +#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12) /* - * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, - * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY + * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE, + * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 -#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK BITFIELD(0, 4) +#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0) /* - * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, - * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY + * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE, + * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5 -#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK BITFIELD(5, 5) +#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5) /* - * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, - * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY + * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE, + * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8 -#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK BITFIELD(8, 8) +#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8) /* - * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, - * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY + * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE, + * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12 -#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK BITFIELD(12, 12) +#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12) /* - * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, - * CM_DIV_M7_DPLL_CORE + * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE, + * CM_DIV_M7_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT 0 -#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK BITFIELD(0, 4) +#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0) /* - * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, - * CM_DIV_M7_DPLL_CORE + * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE, + * CM_DIV_M7_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT 5 -#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK BITFIELD(5, 5) +#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK (1 << 5) /* - * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, - * CM_DIV_M7_DPLL_CORE + * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE, + * CM_DIV_M7_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT 8 -#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK BITFIELD(8, 8) +#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK (1 << 8) /* - * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, - * CM_DIV_M7_DPLL_CORE + * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE, + * CM_DIV_M7_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT 12 -#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK BITFIELD(12, 12) - -/* - * Used by PRM_PRM_PROFILING_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, - * CM_WKUP_KEYBOARD_CLKCTRL, CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, - * CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, - * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, - * CM_WKUP_WDT2_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, - * CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, - * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, - * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, - * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, - * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, - * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, - * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL, - * CM_MEMIF_EMIF_H2_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL, - * CM_L4PER_ADC_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL, - * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL, - * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL, - * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL, - * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, - * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, - * CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, - * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, - * CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, - * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, - * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, - * CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, - * CM_L4PER_MSPROHG_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, - * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, - * CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, - * CM_L4SEC_DES3DES_CLKCTRL, CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, - * CM_L4SEC_SHA2MD51_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, +#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK (1 << 12) + +/* + * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, + * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, + * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, + * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, + * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL, + * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, + * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, + * CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE, + * CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE, + * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, + * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, + * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, + * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL, - * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL, - * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL, - * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, - * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, - * CM_L3INSTR_L3_3_CLKCTRL_RESTORE, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE, - * CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE, CM_L4PER_GPIO2_CLKCTRL_RESTORE, - * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE, - * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE, - * CM_ALWON_MDMINTC_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, - * CM_ALWON_SR_MPU_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, CM_IVAHD_SL2_CLKCTRL, - * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_CM2_PROFILING_CLKCTRL, - * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL, - * CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, - * CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL, - * CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, CM1_ABE_TIMER5_CLKCTRL, - * CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, - * CM1_ABE_WDT3_CLKCTRL, CM_CM1_PROFILING_CLKCTRL + * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL, + * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, + * CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL, + * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE, + * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE, + * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE, + * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL, + * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL, + * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL, + * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL, + * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL, + * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, + * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE, + * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE, + * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE, + * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE, + * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE, + * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, + * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, + * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, + * CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, + * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, + * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, + * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL, + * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, + * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, + * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, + * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL, + * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, + * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL, + * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, + * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL, + * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, + * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, + * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL */ #define OMAP4430_IDLEST_SHIFT 16 -#define OMAP4430_IDLEST_MASK BITFIELD(16, 17) +#define OMAP4430_IDLEST_MASK (0x3 << 16) -/* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ +/* + * Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, + * CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE + */ #define OMAP4430_ISS_DYNDEP_SHIFT 9 -#define OMAP4430_ISS_DYNDEP_MASK BITFIELD(9, 9) +#define OMAP4430_ISS_DYNDEP_MASK (1 << 9) /* - * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, - * CM_MPU_STATICDEP, CM_TESLA_STATICDEP + * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, + * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP */ #define OMAP4430_ISS_STATDEP_SHIFT 9 -#define OMAP4430_ISS_STATDEP_MASK BITFIELD(9, 9) +#define OMAP4430_ISS_STATDEP_MASK (1 << 9) -/* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ +/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_TESLA_DYNAMICDEP */ #define OMAP4430_IVAHD_DYNDEP_SHIFT 2 -#define OMAP4430_IVAHD_DYNDEP_MASK BITFIELD(2, 2) +#define OMAP4430_IVAHD_DYNDEP_MASK (1 << 2) /* - * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, - * CM_GFX_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP, - * CM_SDMA_STATICDEP_RESTORE, CM_DSS_STATICDEP, CM_MPU_STATICDEP, - * CM_TESLA_STATICDEP + * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, + * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, + * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, + * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP */ #define OMAP4430_IVAHD_STATDEP_SHIFT 2 -#define OMAP4430_IVAHD_STATDEP_MASK BITFIELD(2, 2) +#define OMAP4430_IVAHD_STATDEP_MASK (1 << 2) -/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ +/* + * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, + * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE + */ #define OMAP4430_L3INIT_DYNDEP_SHIFT 7 -#define OMAP4430_L3INIT_DYNDEP_MASK BITFIELD(7, 7) +#define OMAP4430_L3INIT_DYNDEP_MASK (1 << 7) /* - * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, - * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, CM_TESLA_STATICDEP + * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP, + * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, + * CM_TESLA_STATICDEP */ #define OMAP4430_L3INIT_STATDEP_SHIFT 7 -#define OMAP4430_L3INIT_STATDEP_MASK BITFIELD(7, 7) +#define OMAP4430_L3INIT_STATDEP_MASK (1 << 7) /* - * Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, - * CM_DSS_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP + * Used by CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_2_DYNAMICDEP, + * CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, + * CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ #define OMAP4430_L3_1_DYNDEP_SHIFT 5 -#define OMAP4430_L3_1_DYNDEP_MASK BITFIELD(5, 5) +#define OMAP4430_L3_1_DYNDEP_MASK (1 << 5) /* - * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, - * CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP, - * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP, - * CM_MPU_STATICDEP, CM_TESLA_STATICDEP + * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, + * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, + * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, + * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP */ #define OMAP4430_L3_1_STATDEP_SHIFT 5 -#define OMAP4430_L3_1_STATDEP_MASK BITFIELD(5, 5) +#define OMAP4430_L3_1_STATDEP_MASK (1 << 5) /* - * Used by CM_EMU_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, - * CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_SDMA_DYNAMICDEP, - * CM_GFX_DYNAMICDEP, CM_L4SEC_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, - * CM_CAM_DYNAMICDEP, CM_IVAHD_DYNAMICDEP + * Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, + * CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP, + * CM_IVAHD_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP, + * CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, + * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP */ #define OMAP4430_L3_2_DYNDEP_SHIFT 6 -#define OMAP4430_L3_2_DYNDEP_MASK BITFIELD(6, 6) +#define OMAP4430_L3_2_DYNDEP_MASK (1 << 6) /* - * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, - * CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP, - * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP, - * CM_MPU_STATICDEP, CM_TESLA_STATICDEP + * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, + * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, + * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, + * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP */ #define OMAP4430_L3_2_STATDEP_SHIFT 6 -#define OMAP4430_L3_2_STATDEP_MASK BITFIELD(6, 6) +#define OMAP4430_L3_2_STATDEP_MASK (1 << 6) -/* Used by CM_L3_1_DYNAMICDEP */ +/* Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE */ #define OMAP4430_L4CFG_DYNDEP_SHIFT 12 -#define OMAP4430_L4CFG_DYNDEP_MASK BITFIELD(12, 12) +#define OMAP4430_L4CFG_DYNDEP_MASK (1 << 12) /* - * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, - * CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, - * CM_TESLA_STATICDEP + * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP, + * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, + * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP */ #define OMAP4430_L4CFG_STATDEP_SHIFT 12 -#define OMAP4430_L4CFG_STATDEP_MASK BITFIELD(12, 12) +#define OMAP4430_L4CFG_STATDEP_MASK (1 << 12) -/* Used by CM_L3_2_DYNAMICDEP */ +/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */ #define OMAP4430_L4PER_DYNDEP_SHIFT 13 -#define OMAP4430_L4PER_DYNDEP_MASK BITFIELD(13, 13) +#define OMAP4430_L4PER_DYNDEP_MASK (1 << 13) /* - * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, - * CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, - * CM_MPU_STATICDEP, CM_TESLA_STATICDEP + * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP, + * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, + * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP */ #define OMAP4430_L4PER_STATDEP_SHIFT 13 -#define OMAP4430_L4PER_STATDEP_MASK BITFIELD(13, 13) +#define OMAP4430_L4PER_STATDEP_MASK (1 << 13) -/* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ +/* + * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, + * CM_L4PER_DYNAMICDEP_RESTORE + */ #define OMAP4430_L4SEC_DYNDEP_SHIFT 14 -#define OMAP4430_L4SEC_DYNDEP_MASK BITFIELD(14, 14) +#define OMAP4430_L4SEC_DYNDEP_MASK (1 << 14) /* - * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_L3INIT_STATICDEP, - * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP + * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, + * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE */ #define OMAP4430_L4SEC_STATDEP_SHIFT 14 -#define OMAP4430_L4SEC_STATDEP_MASK BITFIELD(14, 14) +#define OMAP4430_L4SEC_STATDEP_MASK (1 << 14) -/* Used by CM_L4CFG_DYNAMICDEP */ +/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ #define OMAP4430_L4WKUP_DYNDEP_SHIFT 15 -#define OMAP4430_L4WKUP_DYNDEP_MASK BITFIELD(15, 15) +#define OMAP4430_L4WKUP_DYNDEP_MASK (1 << 15) /* - * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_L3INIT_STATICDEP, - * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, CM_TESLA_STATICDEP + * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, + * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP */ #define OMAP4430_L4WKUP_STATDEP_SHIFT 15 -#define OMAP4430_L4WKUP_STATDEP_MASK BITFIELD(15, 15) +#define OMAP4430_L4WKUP_STATDEP_MASK (1 << 15) /* - * Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, - * CM_MPU_DYNAMICDEP + * Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_L3_1_DYNAMICDEP, + * CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, + * CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP */ #define OMAP4430_MEMIF_DYNDEP_SHIFT 4 -#define OMAP4430_MEMIF_DYNDEP_MASK BITFIELD(4, 4) +#define OMAP4430_MEMIF_DYNDEP_MASK (1 << 4) /* - * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, - * CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP, - * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP, - * CM_MPU_STATICDEP, CM_TESLA_STATICDEP + * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, + * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, + * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, + * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP */ #define OMAP4430_MEMIF_STATDEP_SHIFT 4 -#define OMAP4430_MEMIF_STATDEP_MASK BITFIELD(4, 4) +#define OMAP4430_MEMIF_STATDEP_MASK (1 << 4) /* - * Used by CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO, - * CM_SSC_MODFREQDIV_DPLL_USB, CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, - * CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, - * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA, - * CM_SSC_MODFREQDIV_DPLL_MPU + * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, + * CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY, + * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU, + * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO, + * CM_SSC_MODFREQDIV_DPLL_USB */ #define OMAP4430_MODFREQDIV_EXPONENT_SHIFT 8 -#define OMAP4430_MODFREQDIV_EXPONENT_MASK BITFIELD(8, 10) +#define OMAP4430_MODFREQDIV_EXPONENT_MASK (0x7 << 8) /* - * Used by CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO, - * CM_SSC_MODFREQDIV_DPLL_USB, CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, - * CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, - * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA, - * CM_SSC_MODFREQDIV_DPLL_MPU + * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, + * CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY, + * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU, + * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO, + * CM_SSC_MODFREQDIV_DPLL_USB */ #define OMAP4430_MODFREQDIV_MANTISSA_SHIFT 0 -#define OMAP4430_MODFREQDIV_MANTISSA_MASK BITFIELD(0, 6) - -/* - * Used by PRM_PRM_PROFILING_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, - * CM_WKUP_KEYBOARD_CLKCTRL, CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, - * CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, - * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, - * CM_WKUP_WDT2_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, - * CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, - * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, - * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, - * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, - * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, - * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, - * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL, - * CM_MEMIF_EMIF_H2_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL, - * CM_L4PER_ADC_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL, - * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL, - * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL, - * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL, - * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, - * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, - * CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, - * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, - * CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, - * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, - * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, - * CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, - * CM_L4PER_MSPROHG_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, - * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, - * CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, - * CM_L4SEC_DES3DES_CLKCTRL, CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, - * CM_L4SEC_SHA2MD51_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, +#define OMAP4430_MODFREQDIV_MANTISSA_MASK (0x7f << 0) + +/* + * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, + * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, + * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, + * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, + * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL, + * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, + * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, + * CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE, + * CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE, + * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, + * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, + * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, + * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL, - * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL, - * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL, - * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, - * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, - * CM_L3INSTR_L3_3_CLKCTRL_RESTORE, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE, - * CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE, CM_L4PER_GPIO2_CLKCTRL_RESTORE, - * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE, - * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE, - * CM_ALWON_MDMINTC_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, - * CM_ALWON_SR_MPU_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, CM_IVAHD_SL2_CLKCTRL, - * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_CM2_PROFILING_CLKCTRL, - * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL, - * CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, - * CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL, - * CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, CM1_ABE_TIMER5_CLKCTRL, - * CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, - * CM1_ABE_WDT3_CLKCTRL, CM_CM1_PROFILING_CLKCTRL + * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL, + * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, + * CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL, + * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE, + * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE, + * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE, + * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL, + * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL, + * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL, + * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL, + * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL, + * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, + * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE, + * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE, + * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE, + * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE, + * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE, + * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, + * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, + * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, + * CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, + * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, + * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, + * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL, + * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, + * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, + * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, + * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL, + * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, + * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL, + * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, + * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL, + * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, + * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, + * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL */ #define OMAP4430_MODULEMODE_SHIFT 0 -#define OMAP4430_MODULEMODE_MASK BITFIELD(0, 1) +#define OMAP4430_MODULEMODE_MASK (0x3 << 0) /* Used by CM_DSS_DSS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9 -#define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK BITFIELD(9, 9) +#define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9) /* Used by CM_WKUP_BANDGAP_CLKCTRL */ #define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT 8 -#define OMAP4430_OPTFCLKEN_BGAP_32K_MASK BITFIELD(8, 8) +#define OMAP4430_OPTFCLKEN_BGAP_32K_MASK (1 << 8) -/* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_CLK32K_SHIFT 9 -#define OMAP4430_OPTFCLKEN_CLK32K_MASK BITFIELD(9, 9) +/* Used by CM_ALWON_USBPHY_CLKCTRL */ +#define OMAP4430_OPTFCLKEN_CLK32K_SHIFT 8 +#define OMAP4430_OPTFCLKEN_CLK32K_MASK (1 << 8) /* Used by CM_CAM_ISS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_CTRLCLK_MASK BITFIELD(8, 8) +#define OMAP4430_OPTFCLKEN_CTRLCLK_MASK (1 << 8) /* - * Used by CM_WKUP_GPIO1_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL, - * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, - * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE, - * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE, - * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE + * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE, + * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE, + * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE, + * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE, + * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE, CM_WKUP_GPIO1_CLKCTRL */ #define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_DBCLK_MASK BITFIELD(8, 8) +#define OMAP4430_OPTFCLKEN_DBCLK_MASK (1 << 8) /* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */ #define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_DLL_CLK_MASK BITFIELD(8, 8) +#define OMAP4430_OPTFCLKEN_DLL_CLK_MASK (1 << 8) /* Used by CM_DSS_DSS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_DSSCLK_MASK BITFIELD(8, 8) +#define OMAP4430_OPTFCLKEN_DSSCLK_MASK (1 << 8) + +/* Used by CM_WKUP_USIM_CLKCTRL */ +#define OMAP4430_OPTFCLKEN_FCLK_SHIFT 8 +#define OMAP4430_OPTFCLKEN_FCLK_MASK (1 << 8) /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_FCLK0_SHIFT 8 -#define OMAP4430_OPTFCLKEN_FCLK0_MASK BITFIELD(8, 8) +#define OMAP4430_OPTFCLKEN_FCLK0_MASK (1 << 8) /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_FCLK1_SHIFT 9 -#define OMAP4430_OPTFCLKEN_FCLK1_MASK BITFIELD(9, 9) +#define OMAP4430_OPTFCLKEN_FCLK1_MASK (1 << 9) /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10 -#define OMAP4430_OPTFCLKEN_FCLK2_MASK BITFIELD(10, 10) +#define OMAP4430_OPTFCLKEN_FCLK2_MASK (1 << 10) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15 -#define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK BITFIELD(15, 15) +#define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK (1 << 15) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 -#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK BITFIELD(13, 13) +#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 -#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK BITFIELD(14, 14) +#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 -#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK BITFIELD(11, 11) +#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 -#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK BITFIELD(12, 12) +#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12) /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK BITFIELD(8, 8) +#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK (1 << 8) /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT 9 -#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK BITFIELD(9, 9) +#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK (1 << 9) /* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */ #define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT 8 -#define OMAP4430_OPTFCLKEN_PHY_48M_MASK BITFIELD(8, 8) +#define OMAP4430_OPTFCLKEN_PHY_48M_MASK (1 << 8) /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT 10 -#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK BITFIELD(10, 10) +#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK (1 << 10) /* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT 11 -#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK BITFIELD(11, 11) +#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK (1 << 11) /* Used by CM_DSS_DSS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10 -#define OMAP4430_OPTFCLKEN_SYS_CLK_MASK BITFIELD(10, 10) +#define OMAP4430_OPTFCLKEN_SYS_CLK_MASK (1 << 10) /* Used by CM_DSS_DSS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11 -#define OMAP4430_OPTFCLKEN_TV_CLK_MASK BITFIELD(11, 11) +#define OMAP4430_OPTFCLKEN_TV_CLK_MASK (1 << 11) /* Used by CM_L3INIT_UNIPRO1_CLKCTRL */ #define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK BITFIELD(8, 8) +#define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK (1 << 8) /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK BITFIELD(8, 8) +#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8) /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 -#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK BITFIELD(9, 9) +#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9) /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 -#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK BITFIELD(10, 10) +#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK BITFIELD(8, 8) +#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 -#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK BITFIELD(9, 9) +#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 -#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK BITFIELD(10, 10) +#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10) /* Used by CM_L3INIT_USB_OTG_CLKCTRL */ #define OMAP4430_OPTFCLKEN_XCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_XCLK_MASK BITFIELD(8, 8) +#define OMAP4430_OPTFCLKEN_XCLK_MASK (1 << 8) -/* Used by CM_EMU_OVERRIDE_DPLL_PER, CM_EMU_OVERRIDE_DPLL_CORE */ +/* Used by CM_EMU_OVERRIDE_DPLL_CORE */ #define OMAP4430_OVERRIDE_ENABLE_SHIFT 19 -#define OMAP4430_OVERRIDE_ENABLE_MASK BITFIELD(19, 19) +#define OMAP4430_OVERRIDE_ENABLE_MASK (1 << 19) /* Used by CM_CLKSEL_ABE */ #define OMAP4430_PAD_CLKS_GATE_SHIFT 8 -#define OMAP4430_PAD_CLKS_GATE_MASK BITFIELD(8, 8) +#define OMAP4430_PAD_CLKS_GATE_MASK (1 << 8) /* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */ #define OMAP4430_PERF_CURRENT_SHIFT 0 -#define OMAP4430_PERF_CURRENT_MASK BITFIELD(0, 7) +#define OMAP4430_PERF_CURRENT_MASK (0xff << 0) /* * Used by CM_CORE_DVFS_PERF1, CM_CORE_DVFS_PERF2, CM_CORE_DVFS_PERF3, @@ -1316,159 +1355,173 @@ * CM_IVA_DVFS_PERF_TESLA */ #define OMAP4430_PERF_REQ_SHIFT 0 -#define OMAP4430_PERF_REQ_MASK BITFIELD(0, 7) - -/* Used by CM_EMU_OVERRIDE_DPLL_PER */ -#define OMAP4430_PER_DPLL_EMU_DIV_SHIFT 0 -#define OMAP4430_PER_DPLL_EMU_DIV_MASK BITFIELD(0, 6) - -/* Used by CM_EMU_OVERRIDE_DPLL_PER */ -#define OMAP4430_PER_DPLL_EMU_MULT_SHIFT 8 -#define OMAP4430_PER_DPLL_EMU_MULT_MASK BITFIELD(8, 18) +#define OMAP4430_PERF_REQ_MASK (0xff << 0) /* Used by CM_RESTORE_ST */ #define OMAP4430_PHASE1_COMPLETED_SHIFT 0 -#define OMAP4430_PHASE1_COMPLETED_MASK BITFIELD(0, 0) +#define OMAP4430_PHASE1_COMPLETED_MASK (1 << 0) /* Used by CM_RESTORE_ST */ #define OMAP4430_PHASE2A_COMPLETED_SHIFT 1 -#define OMAP4430_PHASE2A_COMPLETED_MASK BITFIELD(1, 1) +#define OMAP4430_PHASE2A_COMPLETED_MASK (1 << 1) /* Used by CM_RESTORE_ST */ #define OMAP4430_PHASE2B_COMPLETED_SHIFT 2 -#define OMAP4430_PHASE2B_COMPLETED_MASK BITFIELD(2, 2) +#define OMAP4430_PHASE2B_COMPLETED_MASK (1 << 2) /* Used by CM_EMU_DEBUGSS_CLKCTRL */ #define OMAP4430_PMD_STM_MUX_CTRL_SHIFT 20 -#define OMAP4430_PMD_STM_MUX_CTRL_MASK BITFIELD(20, 21) +#define OMAP4430_PMD_STM_MUX_CTRL_MASK (0x3 << 20) /* Used by CM_EMU_DEBUGSS_CLKCTRL */ #define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22 -#define OMAP4430_PMD_TRACE_MUX_CTRL_MASK BITFIELD(22, 23) +#define OMAP4430_PMD_TRACE_MUX_CTRL_MASK (0x3 << 22) -/* Used by CM_DYN_DEP_PRESCAL */ +/* Used by CM_DYN_DEP_PRESCAL, CM_DYN_DEP_PRESCAL_RESTORE */ #define OMAP4430_PRESCAL_SHIFT 0 -#define OMAP4430_PRESCAL_MASK BITFIELD(0, 5) +#define OMAP4430_PRESCAL_MASK (0x3f << 0) -/* Used by REVISION_CM2, REVISION_CM1 */ -#define OMAP4430_REV_SHIFT 0 -#define OMAP4430_REV_MASK BITFIELD(0, 7) +/* Used by REVISION_CM1, REVISION_CM2 */ +#define OMAP4430_R_RTL_SHIFT 11 +#define OMAP4430_R_RTL_MASK (0x1f << 11) /* - * Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, - * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE + * Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, + * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ #define OMAP4430_SAR_MODE_SHIFT 4 -#define OMAP4430_SAR_MODE_MASK BITFIELD(4, 4) +#define OMAP4430_SAR_MODE_MASK (1 << 4) /* Used by CM_SCALE_FCLK */ #define OMAP4430_SCALE_FCLK_SHIFT 0 -#define OMAP4430_SCALE_FCLK_MASK BITFIELD(0, 0) +#define OMAP4430_SCALE_FCLK_MASK (1 << 0) + +/* Used by REVISION_CM1, REVISION_CM2 */ +#define OMAP4430_SCHEME_SHIFT 30 +#define OMAP4430_SCHEME_MASK (0x3 << 30) -/* Used by CM_L4CFG_DYNAMICDEP */ +/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ #define OMAP4430_SDMA_DYNDEP_SHIFT 11 -#define OMAP4430_SDMA_DYNDEP_MASK BITFIELD(11, 11) +#define OMAP4430_SDMA_DYNDEP_MASK (1 << 11) /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ #define OMAP4430_SDMA_STATDEP_SHIFT 11 -#define OMAP4430_SDMA_STATDEP_MASK BITFIELD(11, 11) +#define OMAP4430_SDMA_STATDEP_MASK (1 << 11) /* Used by CM_CLKSEL_ABE */ #define OMAP4430_SLIMBUS_CLK_GATE_SHIFT 10 -#define OMAP4430_SLIMBUS_CLK_GATE_MASK BITFIELD(10, 10) +#define OMAP4430_SLIMBUS_CLK_GATE_MASK (1 << 10) /* - * Used by CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, - * CM_DUCATI_DUCATI_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL, - * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, + * Used by CM1_ABE_AESS_CLKCTRL, CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, + * CM_D2D_SAD2D_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, + * CM_DUCATI_DUCATI_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, + * CM_IVAHD_IVAHD_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, - * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL, - * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL, - * CM_CAM_ISS_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, - * CM_IVAHD_IVAHD_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, - * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL + * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, + * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL, + * CM_L3INIT_XHPI_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL, + * CM_SDMA_SDMA_CLKCTRL, CM_TESLA_TESLA_CLKCTRL */ #define OMAP4430_STBYST_SHIFT 18 -#define OMAP4430_STBYST_MASK BITFIELD(18, 18) +#define OMAP4430_STBYST_MASK (1 << 18) /* - * Used by CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB, - * CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY, - * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU + * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY, + * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, + * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB */ #define OMAP4430_ST_DPLL_CLK_SHIFT 0 -#define OMAP4430_ST_DPLL_CLK_MASK BITFIELD(0, 0) +#define OMAP4430_ST_DPLL_CLK_MASK (1 << 0) /* Used by CM_CLKDCOLDO_DPLL_USB */ #define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT 9 -#define OMAP4430_ST_DPLL_CLKDCOLDO_MASK BITFIELD(9, 9) +#define OMAP4430_ST_DPLL_CLKDCOLDO_MASK (1 << 9) /* - * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB, CM_DIV_M2_DPLL_CORE_RESTORE, - * CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, - * CM_DIV_M2_DPLL_MPU + * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, + * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU, + * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB */ #define OMAP4430_ST_DPLL_CLKOUT_SHIFT 9 -#define OMAP4430_ST_DPLL_CLKOUT_MASK BITFIELD(9, 9) +#define OMAP4430_ST_DPLL_CLKOUT_MASK (1 << 9) /* - * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, - * CM_DIV_M3_DPLL_CORE + * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, + * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER */ #define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT 9 -#define OMAP4430_ST_DPLL_CLKOUTHIF_MASK BITFIELD(9, 9) +#define OMAP4430_ST_DPLL_CLKOUTHIF_MASK (1 << 9) -/* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, CM_DIV_M2_DPLL_ABE */ +/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */ #define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT 11 -#define OMAP4430_ST_DPLL_CLKOUTX2_MASK BITFIELD(11, 11) +#define OMAP4430_ST_DPLL_CLKOUTX2_MASK (1 << 11) /* - * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, - * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA + * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, + * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER */ #define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT 9 -#define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK BITFIELD(9, 9) +#define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9) /* - * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, - * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA + * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, + * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER */ #define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT 9 -#define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK BITFIELD(9, 9) +#define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9) /* - * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, - * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY + * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE, + * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ #define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT 9 -#define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK BITFIELD(9, 9) +#define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9) /* - * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, - * CM_DIV_M7_DPLL_CORE + * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE, + * CM_DIV_M7_DPLL_PER */ #define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT 9 -#define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK BITFIELD(9, 9) +#define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK (1 << 9) + +/* + * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY, + * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, + * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB + */ +#define OMAP4430_ST_MN_BYPASS_SHIFT 8 +#define OMAP4430_ST_MN_BYPASS_MASK (1 << 8) /* Used by CM_SYS_CLKSEL */ #define OMAP4430_SYS_CLKSEL_SHIFT 0 -#define OMAP4430_SYS_CLKSEL_MASK BITFIELD(0, 2) +#define OMAP4430_SYS_CLKSEL_MASK (0x7 << 0) -/* Used by CM_L4CFG_DYNAMICDEP */ +/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ #define OMAP4430_TESLA_DYNDEP_SHIFT 1 -#define OMAP4430_TESLA_DYNDEP_MASK BITFIELD(1, 1) +#define OMAP4430_TESLA_DYNDEP_MASK (1 << 1) /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ #define OMAP4430_TESLA_STATDEP_SHIFT 1 -#define OMAP4430_TESLA_STATDEP_MASK BITFIELD(1, 1) +#define OMAP4430_TESLA_STATDEP_MASK (1 << 1) /* - * Used by CM_EMU_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, - * CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, - * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP + * Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_DUCATI_DYNAMICDEP, + * CM_EMU_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE, + * CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, + * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, + * CM_L4PER_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ #define OMAP4430_WINDOWSIZE_SHIFT 24 -#define OMAP4430_WINDOWSIZE_MASK BITFIELD(24, 27) +#define OMAP4430_WINDOWSIZE_MASK (0xf << 24) + +/* Used by REVISION_CM1, REVISION_CM2 */ +#define OMAP4430_X_MAJOR_SHIFT 8 +#define OMAP4430_X_MAJOR_MASK (0x7 << 8) + +/* Used by REVISION_CM1, REVISION_CM2 */ +#define OMAP4430_Y_MINOR_SHIFT 0 +#define OMAP4430_Y_MINOR_MASK (0x3f << 0) #endif diff --git a/arch/arm/mach-omap2/cm44xx.h b/arch/arm/mach-omap2/cm44xx.h index 336d94889e5b..3c35a87cb90c 100644 --- a/arch/arm/mach-omap2/cm44xx.h +++ b/arch/arm/mach-omap2/cm44xx.h @@ -195,6 +195,42 @@ #define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088 #define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0088) +/* CM1.RESTORE_CM1 register offsets */ +#define OMAP4_CM_CLKSEL_CORE_RESTORE_OFFSET 0x0000 +#define OMAP4430_CM_CLKSEL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0000) +#define OMAP4_CM_DIV_M2_DPLL_CORE_RESTORE_OFFSET 0x0004 +#define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0004) +#define OMAP4_CM_DIV_M3_DPLL_CORE_RESTORE_OFFSET 0x0008 +#define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0008) +#define OMAP4_CM_DIV_M4_DPLL_CORE_RESTORE_OFFSET 0x000c +#define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x000c) +#define OMAP4_CM_DIV_M5_DPLL_CORE_RESTORE_OFFSET 0x0010 +#define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0010) +#define OMAP4_CM_DIV_M6_DPLL_CORE_RESTORE_OFFSET 0x0014 +#define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0014) +#define OMAP4_CM_DIV_M7_DPLL_CORE_RESTORE_OFFSET 0x0018 +#define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0018) +#define OMAP4_CM_CLKSEL_DPLL_CORE_RESTORE_OFFSET 0x001c +#define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x001c) +#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE_OFFSET 0x0020 +#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0020) +#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE_OFFSET 0x0024 +#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0024) +#define OMAP4_CM_CLKMODE_DPLL_CORE_RESTORE_OFFSET 0x0028 +#define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0028) +#define OMAP4_CM_SHADOW_FREQ_CONFIG2_RESTORE_OFFSET 0x002c +#define OMAP4430_CM_SHADOW_FREQ_CONFIG2_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x002c) +#define OMAP4_CM_SHADOW_FREQ_CONFIG1_RESTORE_OFFSET 0x0030 +#define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0030) +#define OMAP4_CM_AUTOIDLE_DPLL_CORE_RESTORE_OFFSET 0x0034 +#define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0034) +#define OMAP4_CM_MPU_CLKSTCTRL_RESTORE_OFFSET 0x0038 +#define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0038) +#define OMAP4_CM_CM1_PROFILING_CLKCTRL_RESTORE_OFFSET 0x003c +#define OMAP4430_CM_CM1_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x003c) +#define OMAP4_CM_DYN_DEP_PRESCAL_RESTORE_OFFSET 0x0040 +#define OMAP4430_CM_DYN_DEP_PRESCAL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0040) + /* CM2 */ /* CM2.OCP_SOCKET_CM2 register offsets */ @@ -252,8 +288,6 @@ #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0068) #define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x006c) -#define OMAP4_CM_EMU_OVERRIDE_DPLL_PER_OFFSET 0x0070 -#define OMAP4430_CM_EMU_OVERRIDE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0070) #define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080 #define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0080) #define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084 @@ -296,6 +330,8 @@ #define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0030) #define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET 0x0038 #define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0038) +#define OMAP4_CM_ALWON_USBPHY_CLKCTRL_OFFSET 0x0040 +#define OMAP4430_CM_ALWON_USBPHY_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0040) /* CM2.CORE_CM2 register offsets */ #define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET 0x0000 @@ -578,4 +614,54 @@ #define OMAP4430_CM_CEFUSE_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0000) #define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020 #define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0020) + +/* CM2.RESTORE_CM2 register offsets */ +#define OMAP4_CM_L3_1_CLKSTCTRL_RESTORE_OFFSET 0x0000 +#define OMAP4430_CM_L3_1_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0000) +#define OMAP4_CM_L3_2_CLKSTCTRL_RESTORE_OFFSET 0x0004 +#define OMAP4430_CM_L3_2_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0004) +#define OMAP4_CM_L4CFG_CLKSTCTRL_RESTORE_OFFSET 0x0008 +#define OMAP4430_CM_L4CFG_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0008) +#define OMAP4_CM_MEMIF_CLKSTCTRL_RESTORE_OFFSET 0x000c +#define OMAP4430_CM_MEMIF_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x000c) +#define OMAP4_CM_L4PER_CLKSTCTRL_RESTORE_OFFSET 0x0010 +#define OMAP4430_CM_L4PER_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0010) +#define OMAP4_CM_L3INIT_CLKSTCTRL_RESTORE_OFFSET 0x0014 +#define OMAP4430_CM_L3INIT_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0014) +#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_RESTORE_OFFSET 0x0018 +#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0018) +#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE_OFFSET 0x001c +#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x001c) +#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE_OFFSET 0x0020 +#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0020) +#define OMAP4_CM_CM2_PROFILING_CLKCTRL_RESTORE_OFFSET 0x0024 +#define OMAP4430_CM_CM2_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0024) +#define OMAP4_CM_D2D_STATICDEP_RESTORE_OFFSET 0x0028 +#define OMAP4430_CM_D2D_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0028) +#define OMAP4_CM_L3_1_DYNAMICDEP_RESTORE_OFFSET 0x002c +#define OMAP4430_CM_L3_1_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x002c) +#define OMAP4_CM_L3_2_DYNAMICDEP_RESTORE_OFFSET 0x0030 +#define OMAP4430_CM_L3_2_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0030) +#define OMAP4_CM_D2D_DYNAMICDEP_RESTORE_OFFSET 0x0034 +#define OMAP4430_CM_D2D_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0034) +#define OMAP4_CM_L4CFG_DYNAMICDEP_RESTORE_OFFSET 0x0038 +#define OMAP4430_CM_L4CFG_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0038) +#define OMAP4_CM_L4PER_DYNAMICDEP_RESTORE_OFFSET 0x003c +#define OMAP4430_CM_L4PER_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x003c) +#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_RESTORE_OFFSET 0x0040 +#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0040) +#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_RESTORE_OFFSET 0x0044 +#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0044) +#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_RESTORE_OFFSET 0x0048 +#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0048) +#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_RESTORE_OFFSET 0x004c +#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x004c) +#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_RESTORE_OFFSET 0x0050 +#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0050) +#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE_OFFSET 0x0054 +#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0054) +#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE_OFFSET 0x0058 +#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0058) +#define OMAP4_CM_SDMA_STATICDEP_RESTORE_OFFSET 0x005c +#define OMAP4430_CM_SDMA_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x005c) #endif diff --git a/arch/arm/mach-omap2/cm4xxx.c b/arch/arm/mach-omap2/cm4xxx.c index b101091e95d6..f8a660a1a4a6 100644 --- a/arch/arm/mach-omap2/cm4xxx.c +++ b/arch/arm/mach-omap2/cm4xxx.c @@ -43,7 +43,6 @@ * using separate functional clock * 0x3 disabled: Module is disabled and cannot be accessed * - * TODO: Need to handle module accessible in idle state */ int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg) { @@ -52,9 +51,11 @@ int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg) if (!clkctrl_reg) return 0; - omap_test_timeout(((__raw_readl(clkctrl_reg) & - OMAP4430_IDLEST_MASK) == 0), - MAX_MODULE_READY_TIME, i); + omap_test_timeout(( + ((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) == 0) || + (((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) >> + OMAP4430_IDLEST_SHIFT) == 0x2)), + MAX_MODULE_READY_TIME, i); return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; } diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c new file mode 100644 index 000000000000..778929f7e92d --- /dev/null +++ b/arch/arm/mach-omap2/common.c @@ -0,0 +1,135 @@ +/* + * linux/arch/arm/mach-omap2/common.c + * + * Code common to all OMAP2+ machines. + * + * Copyright (C) 2009 Texas Instruments + * Copyright (C) 2010 Nokia Corporation + * Tony Lindgren <tony@atomide.com> + * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/clk.h> +#include <linux/io.h> + +#include <plat/common.h> +#include <plat/board.h> +#include <plat/mux.h> + +#include <plat/clock.h> + +#include "sdrc.h" +#include "control.h" + +/* Global address base setup code */ + +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) + +static void __init __omap2_set_globals(struct omap_globals *omap2_globals) +{ + omap2_set_globals_tap(omap2_globals); + omap2_set_globals_sdrc(omap2_globals); + omap2_set_globals_control(omap2_globals); + omap2_set_globals_prcm(omap2_globals); +} + +#endif + +#if defined(CONFIG_ARCH_OMAP2420) + +static struct omap_globals omap242x_globals = { + .class = OMAP242X_CLASS, + .tap = OMAP2_L4_IO_ADDRESS(0x48014000), + .sdrc = OMAP2420_SDRC_BASE, + .sms = OMAP2420_SMS_BASE, + .ctrl = OMAP242X_CTRL_BASE, + .prm = OMAP2420_PRM_BASE, + .cm = OMAP2420_CM_BASE, + .uart1_phys = OMAP2_UART1_BASE, + .uart2_phys = OMAP2_UART2_BASE, + .uart3_phys = OMAP2_UART3_BASE, +}; + +void __init omap2_set_globals_242x(void) +{ + __omap2_set_globals(&omap242x_globals); +} +#endif + +#if defined(CONFIG_ARCH_OMAP2430) + +static struct omap_globals omap243x_globals = { + .class = OMAP243X_CLASS, + .tap = OMAP2_L4_IO_ADDRESS(0x4900a000), + .sdrc = OMAP243X_SDRC_BASE, + .sms = OMAP243X_SMS_BASE, + .ctrl = OMAP243X_CTRL_BASE, + .prm = OMAP2430_PRM_BASE, + .cm = OMAP2430_CM_BASE, + .uart1_phys = OMAP2_UART1_BASE, + .uart2_phys = OMAP2_UART2_BASE, + .uart3_phys = OMAP2_UART3_BASE, +}; + +void __init omap2_set_globals_243x(void) +{ + __omap2_set_globals(&omap243x_globals); +} +#endif + +#if defined(CONFIG_ARCH_OMAP3) + +static struct omap_globals omap3_globals = { + .class = OMAP343X_CLASS, + .tap = OMAP2_L4_IO_ADDRESS(0x4830A000), + .sdrc = OMAP343X_SDRC_BASE, + .sms = OMAP343X_SMS_BASE, + .ctrl = OMAP343X_CTRL_BASE, + .prm = OMAP3430_PRM_BASE, + .cm = OMAP3430_CM_BASE, + .uart1_phys = OMAP3_UART1_BASE, + .uart2_phys = OMAP3_UART2_BASE, + .uart3_phys = OMAP3_UART3_BASE, + .uart4_phys = OMAP3_UART4_BASE, /* Only on 3630 */ +}; + +void __init omap2_set_globals_3xxx(void) +{ + __omap2_set_globals(&omap3_globals); +} + +void __init omap3_map_io(void) +{ + omap2_set_globals_3xxx(); + omap34xx_map_common_io(); +} +#endif + +#if defined(CONFIG_ARCH_OMAP4) +static struct omap_globals omap4_globals = { + .class = OMAP443X_CLASS, + .tap = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE), + .ctrl = OMAP443X_SCM_BASE, + .ctrl_pad = OMAP443X_CTRL_BASE, + .prm = OMAP4430_PRM_BASE, + .cm = OMAP4430_CM_BASE, + .cm2 = OMAP4430_CM2_BASE, + .uart1_phys = OMAP4_UART1_BASE, + .uart2_phys = OMAP4_UART2_BASE, + .uart3_phys = OMAP4_UART3_BASE, + .uart4_phys = OMAP4_UART4_BASE, +}; + +void __init omap2_set_globals_443x(void) +{ + omap2_set_globals_tap(&omap4_globals); + omap2_set_globals_control(&omap4_globals); + omap2_set_globals_prcm(&omap4_globals); +} +#endif + diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index a8d20eef2306..1fa3294b6048 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -16,15 +16,18 @@ #include <linux/io.h> #include <plat/common.h> -#include <plat/control.h> #include <plat/sdrc.h> + #include "cm-regbits-34xx.h" #include "prm-regbits-34xx.h" #include "cm.h" #include "prm.h" #include "sdrc.h" +#include "pm.h" +#include "control.h" static void __iomem *omap2_ctrl_base; +static void __iomem *omap4_ctrl_pad_base; #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) struct omap3_scratchpad { @@ -137,6 +140,7 @@ static struct omap3_control_regs control_context; #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ #define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg)) +#define OMAP4_CTRL_PAD_REGADDR(reg) (omap4_ctrl_pad_base + (reg)) void __init omap2_set_globals_control(struct omap_globals *omap2_globals) { @@ -145,6 +149,12 @@ void __init omap2_set_globals_control(struct omap_globals *omap2_globals) omap2_ctrl_base = ioremap(omap2_globals->ctrl, SZ_4K); WARN_ON(!omap2_ctrl_base); } + + /* Static mapping, never released */ + if (omap2_globals->ctrl_pad) { + omap4_ctrl_pad_base = ioremap(omap2_globals->ctrl_pad, SZ_4K); + WARN_ON(!omap4_ctrl_pad_base); + } } void __iomem *omap_ctrl_base_get(void) @@ -182,6 +192,23 @@ void omap_ctrl_writel(u32 val, u16 offset) __raw_writel(val, OMAP_CTRL_REGADDR(offset)); } +/* + * On OMAP4 control pad are not addressable from control + * core base. So the common omap_ctrl_read/write APIs breaks + * Hence export separate APIs to manage the omap4 pad control + * registers. This APIs will work only for OMAP4 + */ + +u32 omap4_ctrl_pad_readl(u16 offset) +{ + return __raw_readl(OMAP4_CTRL_PAD_REGADDR(offset)); +} + +void omap4_ctrl_pad_writel(u32 val, u16 offset) +{ + __raw_writel(val, OMAP4_CTRL_PAD_REGADDR(offset)); +} + #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) /* * Clears the scratchpad contents in case of cold boot- @@ -190,7 +217,7 @@ void omap_ctrl_writel(u32 val, u16 offset) void omap3_clear_scratchpad_contents(void) { u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET; - u32 *v_addr; + void __iomem *v_addr; u32 offset = 0; v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM); if (prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) & @@ -206,7 +233,7 @@ void omap3_clear_scratchpad_contents(void) /* Populate the scratchpad structure with restore structure */ void omap3_save_scratchpad_contents(void) { - void * __iomem scratchpad_address; + void __iomem *scratchpad_address; u32 arm_context_addr; struct omap3_scratchpad scratchpad_contents; struct omap3_scratchpad_prcm_block prcm_block_contents; diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/mach-omap2/control.h index 131bf405c2f6..b6c6b7c450b3 100644 --- a/arch/arm/plat-omap/include/plat/control.h +++ b/arch/arm/mach-omap2/control.h @@ -1,10 +1,10 @@ /* - * arch/arm/plat-omap/include/mach/control.h + * arch/arm/mach-omap2/control.h * * OMAP2/3/4 System Control Module definitions * - * Copyright (C) 2007-2009 Texas Instruments, Inc. - * Copyright (C) 2007-2008 Nokia Corporation + * Copyright (C) 2007-2010 Texas Instruments, Inc. + * Copyright (C) 2007-2008, 2010 Nokia Corporation * * Written by Paul Walmsley * @@ -13,10 +13,14 @@ * the Free Software Foundation. */ -#ifndef __ASM_ARCH_CONTROL_H -#define __ASM_ARCH_CONTROL_H +#ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H +#define __ARCH_ARM_MACH_OMAP2_CONTROL_H #include <mach/io.h> +#include <mach/ctrl_module_core_44xx.h> +#include <mach/ctrl_module_wkup_44xx.h> +#include <mach/ctrl_module_pad_core_44xx.h> +#include <mach/ctrl_module_pad_wkup_44xx.h> #ifndef __ASSEMBLY__ #define OMAP242X_CTRL_REGADDR(reg) \ @@ -204,12 +208,6 @@ #define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 #define OMAP3_PADCONF_SAD2D_IDLEACK 0x254 -/* 44xx control status register offset */ -#define OMAP44XX_CONTROL_STATUS 0x2c4 - -/* 44xx-only CONTROL_GENERAL register offsets */ -#define OMAP44XX_CONTROL_MMC1 0x628 -#define OMAP44XX_CONTROL_PBIAS_LITE 0x600 /* * REVISIT: This list of registers is not comprehensive - there are more * that should be added. @@ -225,6 +223,8 @@ #define OMAP2_MMCSDIO1ADPCLKISEL (1 << 24) /* MMC1 loop back clock */ #define OMAP24XX_USBSTANDBYCTRL (1 << 15) #define OMAP2_MCBSP2_CLKS_MASK (1 << 6) +#define OMAP2_MCBSP1_FSR_MASK (1 << 4) +#define OMAP2_MCBSP1_CLKR_MASK (1 << 3) #define OMAP2_MCBSP1_CLKS_MASK (1 << 2) /* CONTROL_DEVCONF1 bits */ @@ -255,23 +255,6 @@ #define OMAP2_PBIASLITEPWRDNZ0 (1 << 1) #define OMAP2_PBIASLITEVMODE0 (1 << 0) -/* CONTROL_PBIAS_LITE bits for OMAP4 */ -#define OMAP4_MMC1_PWRDNZ (1 << 26) -#define OMAP4_MMC1_PBIASLITE_HIZ_MODE (1 << 25) -#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT (1 << 24) -#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR (1 << 23) -#define OMAP4_MMC1_PBIASLITE_PWRDNZ (1 << 22) -#define OMAP4_MMC1_PBIASLITE_VMODE (1 << 21) -#define OMAP4_USBC1_ICUSB_PWRDNZ (1 << 20) - -#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP0 (1 << 31) -#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP1 (1 << 30) -#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP2 (1 << 29) -#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP3 (1 << 28) -#define OMAP4_CONTROL_SDMMC1_DR0_SPEEDCTRL (1 << 27) -#define OMAP4_CONTROL_SDMMC1_DR1_SPEEDCTRL (1 << 26) -#define OMAP4_CONTROL_SDMMC1_DR2_SPEEDCTRL (1 << 25) - /* CONTROL_PROG_IO1 bits */ #define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20) @@ -338,12 +321,12 @@ #define FEAT_L2CACHE_256KB 3 #define OMAP3_ISP_SHIFT 5 -#define OMAP3_ISP_MASK (1<< OMAP3_ISP_SHIFT) +#define OMAP3_ISP_MASK (1 << OMAP3_ISP_SHIFT) #define FEAT_ISP 0 #define FEAT_ISP_NONE 1 #define OMAP3_NEON_SHIFT 4 -#define OMAP3_NEON_MASK (1<< OMAP3_NEON_SHIFT) +#define OMAP3_NEON_MASK (1 << OMAP3_NEON_SHIFT) #define FEAT_NEON 0 #define FEAT_NEON_NONE 1 @@ -354,9 +337,11 @@ extern void __iomem *omap_ctrl_base_get(void); extern u8 omap_ctrl_readb(u16 offset); extern u16 omap_ctrl_readw(u16 offset); extern u32 omap_ctrl_readl(u16 offset); +extern u32 omap4_ctrl_pad_readl(u16 offset); extern void omap_ctrl_writeb(u8 val, u16 offset); extern void omap_ctrl_writew(u16 val, u16 offset); extern void omap_ctrl_writel(u32 val, u16 offset); +extern void omap4_ctrl_pad_writel(u32 val, u16 offset); extern void omap3_save_scratchpad_contents(void); extern void omap3_clear_scratchpad_contents(void); @@ -371,11 +356,13 @@ extern void omap3_control_restore_context(void); #define omap_ctrl_readb(x) 0 #define omap_ctrl_readw(x) 0 #define omap_ctrl_readl(x) 0 +#define omap4_ctrl_pad_readl(x) 0 #define omap_ctrl_writeb(x, y) WARN_ON(1) #define omap_ctrl_writew(x, y) WARN_ON(1) #define omap_ctrl_writel(x, y) WARN_ON(1) +#define omap4_ctrl_pad_writel(x, y) WARN_ON(1) #endif #endif /* __ASSEMBLY__ */ -#endif /* __ASM_ARCH_CONTROL_H */ +#endif /* __ARCH_ARM_MACH_OMAP2_CONTROL_H */ diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index 3d3d035db9af..0d50b45d041c 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c @@ -29,10 +29,10 @@ #include <plat/irqs.h> #include <plat/powerdomain.h> #include <plat/clockdomain.h> -#include <plat/control.h> #include <plat/serial.h> #include "pm.h" +#include "control.h" #ifdef CONFIG_CPU_IDLE @@ -60,7 +60,8 @@ struct omap3_processor_cx { struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES]; struct omap3_processor_cx current_cx_state; -struct powerdomain *mpu_pd, *core_pd; +struct powerdomain *mpu_pd, *core_pd, *per_pd; +struct powerdomain *cam_pd; /* * The latencies/thresholds for various C states have @@ -233,14 +234,60 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev, struct cpuidle_state *state) { struct cpuidle_state *new_state = next_valid_state(dev, state); + u32 core_next_state, per_next_state = 0, per_saved_state = 0; + u32 cam_state; + struct omap3_processor_cx *cx; + int ret; if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) { BUG_ON(!dev->safe_state); new_state = dev->safe_state; + goto select_state; } + cx = cpuidle_get_statedata(state); + core_next_state = cx->core_state; + + /* + * FIXME: we currently manage device-specific idle states + * for PER and CORE in combination with CPU-specific + * idle states. This is wrong, and device-specific + * idle managment needs to be separated out into + * its own code. + */ + + /* + * Prevent idle completely if CAM is active. + * CAM does not have wakeup capability in OMAP3. + */ + cam_state = pwrdm_read_pwrst(cam_pd); + if (cam_state == PWRDM_POWER_ON) { + new_state = dev->safe_state; + goto select_state; + } + + /* + * Prevent PER off if CORE is not in retention or off as this + * would disable PER wakeups completely. + */ + per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd); + if ((per_next_state == PWRDM_POWER_OFF) && + (core_next_state > PWRDM_POWER_RET)) + per_next_state = PWRDM_POWER_RET; + + /* Are we changing PER target state? */ + if (per_next_state != per_saved_state) + pwrdm_set_next_pwrst(per_pd, per_next_state); + +select_state: dev->last_state = new_state; - return omap3_enter_idle(dev, new_state); + ret = omap3_enter_idle(dev, new_state); + + /* Restore original PER state if it was modified */ + if (per_next_state != per_saved_state) + pwrdm_set_next_pwrst(per_pd, per_saved_state); + + return ret; } DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); @@ -328,7 +375,8 @@ void omap_init_power_states(void) cpuidle_params_table[OMAP3_STATE_C2].threshold; omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_ON; omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON; - omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID; + omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID | + CPUIDLE_FLAG_CHECK_BM; /* C3 . MPU CSWR + Core inactive */ omap3_power_states[OMAP3_STATE_C3].valid = @@ -426,6 +474,8 @@ int __init omap3_idle_init(void) mpu_pd = pwrdm_lookup("mpu_pwrdm"); core_pd = pwrdm_lookup("core_pwrdm"); + per_pd = pwrdm_lookup("per_pwrdm"); + cam_pd = pwrdm_lookup("cam_pwrdm"); omap_init_power_states(); cpuidle_register_driver(&omap3_idle_driver); diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 2dbb265bedd4..5a0c148e23bc 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -9,12 +9,12 @@ * (at your option) any later version. */ -#include <linux/module.h> #include <linux/kernel.h> #include <linux/init.h> #include <linux/platform_device.h> #include <linux/io.h> #include <linux/clk.h> +#include <linux/err.h> #include <mach/hardware.h> #include <mach/irqs.h> @@ -22,14 +22,17 @@ #include <asm/mach/map.h> #include <asm/pmu.h> -#include <plat/control.h> #include <plat/tc.h> #include <plat/board.h> +#include <plat/mcbsp.h> #include <mach/gpio.h> #include <plat/mmc.h> #include <plat/dma.h> +#include <plat/omap_hwmod.h> +#include <plat/omap_device.h> #include "mux.h" +#include "control.h" #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE) @@ -235,6 +238,43 @@ static inline void omap_init_mbox(void) { } static inline void omap_init_sti(void) {} +#if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE) + +static struct platform_device omap_pcm = { + .name = "omap-pcm-audio", + .id = -1, +}; + +/* + * OMAP2420 has 2 McBSP ports + * OMAP2430 has 5 McBSP ports + * OMAP3 has 5 McBSP ports + * OMAP4 has 4 McBSP ports + */ +OMAP_MCBSP_PLATFORM_DEVICE(1); +OMAP_MCBSP_PLATFORM_DEVICE(2); +OMAP_MCBSP_PLATFORM_DEVICE(3); +OMAP_MCBSP_PLATFORM_DEVICE(4); +OMAP_MCBSP_PLATFORM_DEVICE(5); + +static void omap_init_audio(void) +{ + platform_device_register(&omap_mcbsp1); + platform_device_register(&omap_mcbsp2); + if (cpu_is_omap243x() || cpu_is_omap34xx() || cpu_is_omap44xx()) { + platform_device_register(&omap_mcbsp3); + platform_device_register(&omap_mcbsp4); + } + if (cpu_is_omap243x() || cpu_is_omap34xx()) + platform_device_register(&omap_mcbsp5); + + platform_device_register(&omap_pcm); +} + +#else +static inline void omap_init_audio(void) {} +#endif + #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE) #include <plat/mcspi.h> @@ -498,6 +538,76 @@ static void omap_init_sham(void) static inline void omap_init_sham(void) { } #endif +#if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE) + +#ifdef CONFIG_ARCH_OMAP2 +static struct resource omap2_aes_resources[] = { + { + .start = OMAP24XX_SEC_AES_BASE, + .end = OMAP24XX_SEC_AES_BASE + 0x4C, + .flags = IORESOURCE_MEM, + }, + { + .start = OMAP24XX_DMA_AES_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = OMAP24XX_DMA_AES_RX, + .flags = IORESOURCE_DMA, + } +}; +static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources); +#else +#define omap2_aes_resources NULL +#define omap2_aes_resources_sz 0 +#endif + +#ifdef CONFIG_ARCH_OMAP3 +static struct resource omap3_aes_resources[] = { + { + .start = OMAP34XX_SEC_AES_BASE, + .end = OMAP34XX_SEC_AES_BASE + 0x4C, + .flags = IORESOURCE_MEM, + }, + { + .start = OMAP34XX_DMA_AES2_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = OMAP34XX_DMA_AES2_RX, + .flags = IORESOURCE_DMA, + } +}; +static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources); +#else +#define omap3_aes_resources NULL +#define omap3_aes_resources_sz 0 +#endif + +static struct platform_device aes_device = { + .name = "omap-aes", + .id = -1, +}; + +static void omap_init_aes(void) +{ + if (cpu_is_omap24xx()) { + aes_device.resource = omap2_aes_resources; + aes_device.num_resources = omap2_aes_resources_sz; + } else if (cpu_is_omap34xx()) { + aes_device.resource = omap3_aes_resources; + aes_device.num_resources = omap3_aes_resources_sz; + } else { + pr_err("%s: platform not supported\n", __func__); + return; + } + platform_device_register(&aes_device); +} + +#else +static inline void omap_init_aes(void) { } +#endif + /*-------------------------------------------------------------------------*/ #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) @@ -624,7 +734,7 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, omap_mux_init_signal("sdmmc_dat0", 0); omap_mux_init_signal("sdmmc_dat_dir0", 0); omap_mux_init_signal("sdmmc_cmd_dir", 0); - if (mmc_controller->slots[0].wires == 4) { + if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) { omap_mux_init_signal("sdmmc_dat1", 0); omap_mux_init_signal("sdmmc_dat2", 0); omap_mux_init_signal("sdmmc_dat3", 0); @@ -652,8 +762,8 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, OMAP_PIN_INPUT_PULLUP); omap_mux_init_signal("sdmmc1_dat0", OMAP_PIN_INPUT_PULLUP); - if (mmc_controller->slots[0].wires == 4 || - mmc_controller->slots[0].wires == 8) { + if (mmc_controller->slots[0].caps & + (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) { omap_mux_init_signal("sdmmc1_dat1", OMAP_PIN_INPUT_PULLUP); omap_mux_init_signal("sdmmc1_dat2", @@ -661,7 +771,8 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, omap_mux_init_signal("sdmmc1_dat3", OMAP_PIN_INPUT_PULLUP); } - if (mmc_controller->slots[0].wires == 8) { + if (mmc_controller->slots[0].caps & + MMC_CAP_8_BIT_DATA) { omap_mux_init_signal("sdmmc1_dat4", OMAP_PIN_INPUT_PULLUP); omap_mux_init_signal("sdmmc1_dat5", @@ -685,8 +796,8 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed * in the board-*.c files */ - if (mmc_controller->slots[0].wires == 4 || - mmc_controller->slots[0].wires == 8) { + if (mmc_controller->slots[0].caps & + (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) { omap_mux_init_signal("sdmmc2_dat1", OMAP_PIN_INPUT_PULLUP); omap_mux_init_signal("sdmmc2_dat2", @@ -694,7 +805,8 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, omap_mux_init_signal("sdmmc2_dat3", OMAP_PIN_INPUT_PULLUP); } - if (mmc_controller->slots[0].wires == 8) { + if (mmc_controller->slots[0].caps & + MMC_CAP_8_BIT_DATA) { omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4", OMAP_PIN_INPUT_PULLUP); omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5", @@ -745,13 +857,13 @@ void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, case 3: if (!cpu_is_omap44xx()) return; - base = OMAP4_MMC4_BASE + OMAP4_MMC_REG_OFFSET; + base = OMAP4_MMC4_BASE; irq = OMAP44XX_IRQ_MMC4; break; case 4: if (!cpu_is_omap44xx()) return; - base = OMAP4_MMC5_BASE + OMAP4_MMC_REG_OFFSET; + base = OMAP4_MMC5_BASE; irq = OMAP44XX_IRQ_MMC5; break; default: @@ -762,10 +874,8 @@ void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, size = OMAP2420_MMC_SIZE; name = "mmci-omap"; } else if (cpu_is_omap44xx()) { - if (i < 3) { - base += OMAP4_MMC_REG_OFFSET; + if (i < 3) irq += OMAP44XX_IRQ_GIC_START; - } size = OMAP4_HSMMC_SIZE; name = "mmci-omap-hs"; } else { @@ -841,12 +951,74 @@ static inline void omap_init_vout(void) {} /*-------------------------------------------------------------------------*/ +/* + * Inorder to avoid any assumptions from bootloader regarding WDT + * settings, WDT module is reset during init. This enables the watchdog + * timer. Hence it is required to disable the watchdog after the WDT reset + * during init. Otherwise the system would reboot as per the default + * watchdog timer registers settings. + */ +#define OMAP_WDT_WPS (0x34) +#define OMAP_WDT_SPR (0x48) + +static int omap2_disable_wdt(struct omap_hwmod *oh, void *unused) +{ + void __iomem *base; + int ret; + + if (!oh) { + pr_err("%s: Could not look up wdtimer_hwmod\n", __func__); + return -EINVAL; + } + + base = omap_hwmod_get_mpu_rt_va(oh); + if (!base) { + pr_err("%s: Could not get the base address for %s\n", + oh->name, __func__); + return -EINVAL; + } + + /* Enable the clocks before accessing the WDT registers */ + ret = omap_hwmod_enable(oh); + if (ret) { + pr_err("%s: Could not enable clocks for %s\n", + oh->name, __func__); + return ret; + } + + /* sequence required to disable watchdog */ + __raw_writel(0xAAAA, base + OMAP_WDT_SPR); + while (__raw_readl(base + OMAP_WDT_WPS) & 0x10) + cpu_relax(); + + __raw_writel(0x5555, base + OMAP_WDT_SPR); + while (__raw_readl(base + OMAP_WDT_WPS) & 0x10) + cpu_relax(); + + ret = omap_hwmod_idle(oh); + if (ret) + pr_err("%s: Could not disable clocks for %s\n", + oh->name, __func__); + + return ret; +} + +static void __init omap_disable_wdt(void) +{ + if (cpu_class_is_omap2()) + omap_hwmod_for_each_by_class("wd_timer", + omap2_disable_wdt, NULL); + return; +} + static int __init omap2_init_devices(void) { /* please keep these calls, and their implementations above, * in alphabetical order so they're easier to sort through. */ + omap_disable_wdt(); omap_hsmmc_reset(); + omap_init_audio(); omap_init_camera(); omap_init_mbox(); omap_init_mcspi(); @@ -854,8 +1026,45 @@ static int __init omap2_init_devices(void) omap_hdq_init(); omap_init_sti(); omap_init_sham(); + omap_init_aes(); omap_init_vout(); return 0; } arch_initcall(omap2_init_devices); + +#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE) +struct omap_device_pm_latency omap_wdt_latency[] = { + [0] = { + .deactivate_func = omap_device_idle_hwmods, + .activate_func = omap_device_enable_hwmods, + .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, + }, +}; + +static int __init omap_init_wdt(void) +{ + int id = -1; + struct omap_device *od; + struct omap_hwmod *oh; + char *oh_name = "wd_timer2"; + char *dev_name = "omap_wdt"; + + if (!cpu_class_is_omap2()) + return 0; + + oh = omap_hwmod_lookup(oh_name); + if (!oh) { + pr_err("Could not look up wd_timer%d hwmod\n", id); + return -EINVAL; + } + + od = omap_device_build(dev_name, id, oh, NULL, 0, + omap_wdt_latency, + ARRAY_SIZE(omap_wdt_latency), 0); + WARN(IS_ERR(od), "Cant build omap_device for %s:%s.\n", + dev_name, oh->name); + return 0; +} +subsys_initcall(omap_init_wdt); +#endif diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.c b/arch/arm/mach-omap2/gpmc-smsc911x.c new file mode 100644 index 000000000000..703f150dd01d --- /dev/null +++ b/arch/arm/mach-omap2/gpmc-smsc911x.c @@ -0,0 +1,113 @@ +/* + * linux/arch/arm/mach-omap2/gpmc-smsc911x.c + * + * Copyright (C) 2009 Li-Pro.Net + * Stephan Linz <linz@li-pro.net> + * + * Modified from linux/arch/arm/mach-omap2/gpmc-smc91x.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/gpio.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/smsc911x.h> + +#include <plat/board.h> +#include <plat/gpmc.h> +#include <plat/gpmc-smsc911x.h> + +static struct omap_smsc911x_platform_data *gpmc_cfg; + +static struct resource gpmc_smsc911x_resources[] = { + [0] = { + .flags = IORESOURCE_MEM, + }, + [1] = { + .flags = IORESOURCE_IRQ, + }, +}; + +static struct smsc911x_platform_config gpmc_smsc911x_config = { + .phy_interface = PHY_INTERFACE_MODE_MII, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, + .flags = SMSC911X_USE_16BIT, +}; + +static struct platform_device gpmc_smsc911x_device = { + .name = "smsc911x", + .id = -1, + .num_resources = ARRAY_SIZE(gpmc_smsc911x_resources), + .resource = gpmc_smsc911x_resources, + .dev = { + .platform_data = &gpmc_smsc911x_config, + }, +}; + +/* + * Initialize smsc911x device connected to the GPMC. Note that we + * assume that pin multiplexing is done in the board-*.c file, + * or in the bootloader. + */ +void __init gpmc_smsc911x_init(struct omap_smsc911x_platform_data *board_data) +{ + unsigned long cs_mem_base; + int ret; + + gpmc_cfg = board_data; + + if (gpmc_cs_request(gpmc_cfg->cs, SZ_16M, &cs_mem_base) < 0) { + printk(KERN_ERR "Failed to request GPMC mem for smsc911x\n"); + return; + } + + gpmc_smsc911x_resources[0].start = cs_mem_base + 0x0; + gpmc_smsc911x_resources[0].end = cs_mem_base + 0xff; + + if (gpio_request(gpmc_cfg->gpio_irq, "smsc911x irq") < 0) { + printk(KERN_ERR "Failed to request GPIO%d for smsc911x IRQ\n", + gpmc_cfg->gpio_irq); + goto free1; + } + + gpio_direction_input(gpmc_cfg->gpio_irq); + gpmc_smsc911x_resources[1].start = gpio_to_irq(gpmc_cfg->gpio_irq); + gpmc_smsc911x_resources[1].flags |= + (gpmc_cfg->flags & IRQF_TRIGGER_MASK); + + if (gpio_is_valid(gpmc_cfg->gpio_reset)) { + ret = gpio_request(gpmc_cfg->gpio_reset, "smsc911x reset"); + if (ret) { + printk(KERN_ERR "Failed to request GPIO%d for smsc911x reset\n", + gpmc_cfg->gpio_reset); + goto free2; + } + + gpio_direction_output(gpmc_cfg->gpio_reset, 1); + gpio_set_value(gpmc_cfg->gpio_reset, 0); + msleep(100); + gpio_set_value(gpmc_cfg->gpio_reset, 1); + } + + if (platform_device_register(&gpmc_smsc911x_device) < 0) { + printk(KERN_ERR "Unable to register smsc911x device\n"); + gpio_free(gpmc_cfg->gpio_reset); + goto free2; + } + + return; + +free2: + gpio_free(gpmc_cfg->gpio_irq); +free1: + gpmc_cs_free(gpmc_cfg->cs); + + printk(KERN_ERR "Could not initialize smsc911x\n"); +} diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c index c8f647b6205e..34272e4863fd 100644 --- a/arch/arm/mach-omap2/hsmmc.c +++ b/arch/arm/mach-omap2/hsmmc.c @@ -14,11 +14,11 @@ #include <linux/string.h> #include <linux/delay.h> #include <mach/hardware.h> -#include <plat/control.h> #include <plat/mmc.h> #include <plat/omap-pm.h> #include "hsmmc.h" +#include "control.h" #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) @@ -135,10 +135,11 @@ static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot, * * FIXME handle VMMC1A as needed ... */ - reg = omap_ctrl_readl(control_pbias_offset); - reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ | OMAP4_MMC1_PWRDNZ | - OMAP4_USBC1_ICUSB_PWRDNZ); - omap_ctrl_writel(reg, control_pbias_offset); + reg = omap4_ctrl_pad_readl(control_pbias_offset); + reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | + OMAP4_MMC1_PWRDNZ_MASK | + OMAP4_USBC1_ICUSB_PWRDNZ_MASK); + omap4_ctrl_pad_writel(reg, control_pbias_offset); } static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot, @@ -147,30 +148,33 @@ static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot, u32 reg; if (power_on) { - reg = omap_ctrl_readl(control_pbias_offset); - reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ; + reg = omap4_ctrl_pad_readl(control_pbias_offset); + reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK; if ((1 << vdd) <= MMC_VDD_165_195) - reg &= ~OMAP4_MMC1_PBIASLITE_VMODE; + reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK; else - reg |= OMAP4_MMC1_PBIASLITE_VMODE; - reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ | OMAP4_MMC1_PWRDNZ | - OMAP4_USBC1_ICUSB_PWRDNZ); - omap_ctrl_writel(reg, control_pbias_offset); + reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK; + reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | + OMAP4_MMC1_PWRDNZ_MASK | + OMAP4_USBC1_ICUSB_PWRDNZ_MASK); + omap4_ctrl_pad_writel(reg, control_pbias_offset); /* 4 microsec delay for comparator to generate an error*/ udelay(4); - reg = omap_ctrl_readl(control_pbias_offset); - if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR) { + reg = omap4_ctrl_pad_readl(control_pbias_offset); + if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) { pr_err("Pbias Voltage is not same as LDO\n"); /* Caution : On VMODE_ERROR Power Down MMC IO */ - reg &= ~(OMAP4_MMC1_PWRDNZ | OMAP4_USBC1_ICUSB_PWRDNZ); - omap_ctrl_writel(reg, control_pbias_offset); + reg &= ~(OMAP4_MMC1_PWRDNZ_MASK | + OMAP4_USBC1_ICUSB_PWRDNZ_MASK); + omap4_ctrl_pad_writel(reg, control_pbias_offset); } } else { - reg = omap_ctrl_readl(control_pbias_offset); - reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ | - OMAP4_MMC1_PBIASLITE_VMODE | OMAP4_MMC1_PWRDNZ | - OMAP4_USBC1_ICUSB_PWRDNZ); - omap_ctrl_writel(reg, control_pbias_offset); + reg = omap4_ctrl_pad_readl(control_pbias_offset); + reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | + OMAP4_MMC1_PWRDNZ_MASK | + OMAP4_MMC1_PBIASLITE_VMODE_MASK | + OMAP4_USBC1_ICUSB_PWRDNZ_MASK); + omap4_ctrl_pad_writel(reg, control_pbias_offset); } } @@ -218,17 +222,18 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; } } else { - control_pbias_offset = OMAP44XX_CONTROL_PBIAS_LITE; - control_mmc1 = OMAP44XX_CONTROL_MMC1; - reg = omap_ctrl_readl(control_mmc1); - reg |= (OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP0 | - OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP1); - reg &= ~(OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP2 | - OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP3); - reg |= (OMAP4_CONTROL_SDMMC1_DR0_SPEEDCTRL | - OMAP4_CONTROL_SDMMC1_DR1_SPEEDCTRL | - OMAP4_CONTROL_SDMMC1_DR2_SPEEDCTRL); - omap_ctrl_writel(reg, control_mmc1); + control_pbias_offset = + OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE; + control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1; + reg = omap4_ctrl_pad_readl(control_mmc1); + reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK | + OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK); + reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK | + OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK); + reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK| + OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK | + OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK); + omap4_ctrl_pad_writel(reg, control_mmc1); } for (c = controllers; c->mmc; c++) { @@ -258,9 +263,13 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) "mmc%islot%i", c->mmc, 1); mmc->slots[0].name = hc->name; mmc->nr_slots = 1; - mmc->slots[0].wires = c->wires; + mmc->slots[0].caps = c->caps; mmc->slots[0].internal_clock = !c->ext_clock; mmc->dma_mask = 0xffffffff; + if (cpu_is_omap44xx()) + mmc->reg_offset = OMAP4_MMC_REG_OFFSET; + else + mmc->reg_offset = 0; mmc->get_context_loss_count = hsmmc_get_context_loss; @@ -298,6 +307,9 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) else mmc->slots[0].features |= HSMMC_HAS_PBIAS; + if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0)) + mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET; + switch (c->mmc) { case 1: if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { @@ -316,16 +328,20 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) } /* Omap3630 HSMMC1 supports only 4-bit */ - if (cpu_is_omap3630() && c->wires > 4) { - c->wires = 4; - mmc->slots[0].wires = c->wires; + if (cpu_is_omap3630() && + (c->caps & MMC_CAP_8_BIT_DATA)) { + c->caps &= ~MMC_CAP_8_BIT_DATA; + c->caps |= MMC_CAP_4_BIT_DATA; + mmc->slots[0].caps = c->caps; } break; case 2: if (c->ext_clock) c->transceiver = 1; - if (c->transceiver && c->wires > 4) - c->wires = 4; + if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) { + c->caps &= ~MMC_CAP_8_BIT_DATA; + c->caps |= MMC_CAP_4_BIT_DATA; + } /* FALLTHROUGH */ case 3: if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { diff --git a/arch/arm/mach-omap2/hsmmc.h b/arch/arm/mach-omap2/hsmmc.h index 1fe6f0187177..f119348827d4 100644 --- a/arch/arm/mach-omap2/hsmmc.h +++ b/arch/arm/mach-omap2/hsmmc.h @@ -10,7 +10,8 @@ struct mmc_card; struct omap2_hsmmc_info { u8 mmc; /* controller 1/2/3 */ - u8 wires; /* 1/4/8 wires */ + u32 caps; /* 4/8 wires and any additional host + * capabilities OR'd (ref. linux/mmc/host.h) */ bool transceiver; /* MMC-2 option */ bool ext_clock; /* use external pin for input clock */ bool cover_only; /* No card detect - just cover switch */ @@ -23,7 +24,7 @@ struct omap2_hsmmc_info { char *name; /* or NULL for default */ struct device *dev; /* returned: pointer to mmc adapter */ int ocr_mask; /* temporary HACK */ - /* Remux (pad configuation) when powering on/off */ + /* Remux (pad configuration) when powering on/off */ void (*remux)(struct device *dev, int slot, int power_on); /* init some special card */ void (*init_card)(struct mmc_card *card); diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 9a879f959509..5f9086c65e48 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -22,11 +22,12 @@ #include <asm/cputype.h> #include <plat/common.h> -#include <plat/control.h> #include <plat/cpu.h> #include <mach/id.h> +#include "control.h" + static struct omap_chip_id omap_chip; static unsigned int omap_revision; @@ -60,7 +61,7 @@ int omap_type(void) } else if (cpu_is_omap34xx()) { val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); } else if (cpu_is_omap44xx()) { - val = omap_ctrl_readl(OMAP44XX_CONTROL_STATUS); + val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS); } else { pr_err("Cannot detect omap type!\n"); goto out; @@ -298,7 +299,6 @@ static void __init omap4_check_revision(void) u32 idcode; u16 hawkeye; u8 rev; - char *rev_name = "ES1.0"; /* * The IC rev detection is done with hawkeye and rev. @@ -309,14 +309,39 @@ static void __init omap4_check_revision(void) hawkeye = (idcode >> 12) & 0xffff; rev = (idcode >> 28) & 0xff; - if ((hawkeye == 0xb852) && (rev == 0x0)) { - omap_revision = OMAP4430_REV_ES1_0; - omap_chip.oc |= CHIP_IS_OMAP4430ES1; - pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name); - return; + /* + * Few initial ES2.0 samples IDCODE is same as ES1.0 + * Use ARM register to detect the correct ES version + */ + if (!rev) { + idcode = read_cpuid(CPUID_ID); + rev = (idcode & 0xf) - 1; + } + + switch (hawkeye) { + case 0xb852: + switch (rev) { + case 0: + omap_revision = OMAP4430_REV_ES1_0; + omap_chip.oc |= CHIP_IS_OMAP4430ES1; + break; + case 1: + omap_revision = OMAP4430_REV_ES2_0; + omap_chip.oc |= CHIP_IS_OMAP4430ES2; + break; + default: + omap_revision = OMAP4430_REV_ES2_0; + omap_chip.oc |= CHIP_IS_OMAP4430ES2; + } + break; + default: + /* Unknown default to latest silicon rev as default*/ + omap_revision = OMAP4430_REV_ES2_0; + omap_chip.oc |= CHIP_IS_OMAP4430ES2; } - pr_err("Unknown OMAP4 CPU id\n"); + pr_info("OMAP%04x ES%d.0\n", + omap_rev() >> 16, ((omap_rev() >> 12) & 0xf) + 1); } #define OMAP3_SHOW_FEATURE(feat) \ @@ -361,30 +386,54 @@ static void __init omap3_cpuinfo(void) strcpy(cpu_name, "OMAP3503"); } - switch (rev) { - case OMAP_REVBITS_00: - strcpy(cpu_rev, "1.0"); - break; - case OMAP_REVBITS_01: - strcpy(cpu_rev, "1.1"); - break; - case OMAP_REVBITS_02: - strcpy(cpu_rev, "1.2"); - break; - case OMAP_REVBITS_10: - strcpy(cpu_rev, "2.0"); - break; - case OMAP_REVBITS_20: - strcpy(cpu_rev, "2.1"); - break; - case OMAP_REVBITS_30: - strcpy(cpu_rev, "3.0"); - break; - case OMAP_REVBITS_40: - /* FALLTHROUGH */ - default: - /* Use the latest known revision as default */ - strcpy(cpu_rev, "3.1"); + if (cpu_is_omap3630()) { + switch (rev) { + case OMAP_REVBITS_00: + strcpy(cpu_rev, "1.0"); + break; + case OMAP_REVBITS_01: + strcpy(cpu_rev, "1.1"); + break; + case OMAP_REVBITS_02: + /* FALLTHROUGH */ + default: + /* Use the latest known revision as default */ + strcpy(cpu_rev, "1.2"); + } + } else if (cpu_is_omap3505() || cpu_is_omap3517()) { + switch (rev) { + case OMAP_REVBITS_00: + strcpy(cpu_rev, "1.0"); + break; + case OMAP_REVBITS_01: + /* FALLTHROUGH */ + default: + /* Use the latest known revision as default */ + strcpy(cpu_rev, "1.1"); + } + } else { + switch (rev) { + case OMAP_REVBITS_00: + strcpy(cpu_rev, "1.0"); + break; + case OMAP_REVBITS_01: + strcpy(cpu_rev, "2.0"); + break; + case OMAP_REVBITS_02: + strcpy(cpu_rev, "2.1"); + break; + case OMAP_REVBITS_03: + strcpy(cpu_rev, "3.0"); + break; + case OMAP_REVBITS_04: + strcpy(cpu_rev, "3.1"); + break; + case OMAP_REVBITS_05: + /* FALLTHROUGH */ + default: + /* Use the latest known revision as default */ + strcpy(cpu_rev, "3.1.2"); + } } /* Print verbose information */ diff --git a/arch/arm/mach-omap2/include/mach/board-rx51.h b/arch/arm/mach-omap2/include/mach/board-rx51.h new file mode 100644 index 000000000000..b76f49e7eed5 --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/board-rx51.h @@ -0,0 +1,11 @@ +/* + * Defines for rx51 boards + */ + +#ifndef _OMAP_BOARD_RX51_H +#define _OMAP_BOARD_RX51_H + +extern void __init rx51_peripherals_init(void); +extern void __init rx51_video_mem_init(void); + +#endif diff --git a/arch/arm/mach-omap2/include/mach/board-zoom.h b/arch/arm/mach-omap2/include/mach/board-zoom.h index 3af69d2c3dcd..f93ca3928c3b 100644 --- a/arch/arm/mach-omap2/include/mach/board-zoom.h +++ b/arch/arm/mach-omap2/include/mach/board-zoom.h @@ -1,11 +1,9 @@ /* * Defines for zoom boards */ -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> - #define ZOOM_NAND_CS 0 -extern void __init board_nand_init(struct mtd_partition *, u8 nr_parts, u8 cs); extern int __init zoom_debugboard_init(void); extern void __init zoom_peripherals_init(void); + +#define ZOOM2_HEADSET_EXTMUTE_GPIO 153 diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h new file mode 100644 index 000000000000..2f7ac70a20d8 --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h @@ -0,0 +1,391 @@ +/* + * OMAP44xx CTRL_MODULE_CORE registers and bitfields + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * + * Benoit Cousson (b-cousson@ti.com) + * Santosh Shilimkar (santosh.shilimkar@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H +#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H + + +/* Base address */ +#define OMAP4_CTRL_MODULE_CORE 0x4a002000 + +/* Registers offset */ +#define OMAP4_CTRL_MODULE_CORE_IP_REVISION 0x0000 +#define OMAP4_CTRL_MODULE_CORE_IP_HWINFO 0x0004 +#define OMAP4_CTRL_MODULE_CORE_IP_SYSCONFIG 0x0010 +#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_0 0x0200 +#define OMAP4_CTRL_MODULE_CORE_ID_CODE 0x0204 +#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_1 0x0208 +#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_2 0x020c +#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_3 0x0210 +#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_0 0x0214 +#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1 0x0218 +#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_USB_CONF 0x021c +#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_VDD_WKUP 0x0228 +#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_BGAP 0x0260 +#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_0 0x0264 +#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1 0x0268 +#define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4 +#define OMAP4_CTRL_MODULE_CORE_DEV_CONF 0x0300 +#define OMAP4_CTRL_MODULE_CORE_LDOVBB_IVA_VOLTAGE_CTRL 0x0314 +#define OMAP4_CTRL_MODULE_CORE_LDOVBB_MPU_VOLTAGE_CTRL 0x0318 +#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL 0x0320 +#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_MPU_VOLTAGE_CTRL 0x0324 +#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_CORE_VOLTAGE_CTRL 0x0328 +#define OMAP4_CTRL_MODULE_CORE_TEMP_SENSOR 0x032c +#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_0 0x0330 +#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_1 0x0334 +#define OMAP4_CTRL_MODULE_CORE_USBOTGHS_CONTROL 0x033c +#define OMAP4_CTRL_MODULE_CORE_DSS_CONTROL 0x0340 +#define OMAP4_CTRL_MODULE_CORE_HWOBS_CONTROL 0x0350 +#define OMAP4_CTRL_MODULE_CORE_DEBOBS_FINAL_MUX_SEL 0x0400 +#define OMAP4_CTRL_MODULE_CORE_DEBOBS_MMR_MPU 0x0408 +#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL0 0x042c +#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL1 0x0430 +#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL2 0x0434 +#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL3 0x0438 +#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL0 0x0440 +#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL1 0x0444 +#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL2 0x0448 +#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_FREQLOCK_SEL 0x044c +#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_TINITZ_SEL 0x0450 +#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_PHASELOCK_SEL 0x0454 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_0 0x0480 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_1 0x0484 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_2 0x0488 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_3 0x048c +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_4 0x0490 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_5 0x0494 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_6 0x0498 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_7 0x049c +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_8 0x04a0 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_9 0x04a4 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_10 0x04a8 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_11 0x04ac +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_12 0x04b0 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_13 0x04b4 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_14 0x04b8 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_15 0x04bc +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_16 0x04c0 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_17 0x04c4 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_18 0x04c8 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_19 0x04cc +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_20 0x04d0 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_21 0x04d4 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_22 0x04d8 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_23 0x04dc +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_24 0x04e0 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_25 0x04e4 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_26 0x04e8 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_27 0x04ec +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_28 0x04f0 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_29 0x04f4 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_30 0x04f8 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_31 0x04fc + +/* Registers shifts and masks */ + +/* IP_REVISION */ +#define OMAP4_IP_REV_SCHEME_SHIFT 30 +#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30) +#define OMAP4_IP_REV_FUNC_SHIFT 16 +#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16) +#define OMAP4_IP_REV_RTL_SHIFT 11 +#define OMAP4_IP_REV_RTL_MASK (0x1f << 11) +#define OMAP4_IP_REV_MAJOR_SHIFT 8 +#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8) +#define OMAP4_IP_REV_CUSTOM_SHIFT 6 +#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6) +#define OMAP4_IP_REV_MINOR_SHIFT 0 +#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0) + +/* IP_HWINFO */ +#define OMAP4_IP_HWINFO_SHIFT 0 +#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0) + +/* IP_SYSCONFIG */ +#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2 +#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2) + +/* STD_FUSE_DIE_ID_0 */ +#define OMAP4_STD_FUSE_DIE_ID_0_SHIFT 0 +#define OMAP4_STD_FUSE_DIE_ID_0_MASK (0xffffffff << 0) + +/* ID_CODE */ +#define OMAP4_STD_FUSE_IDCODE_SHIFT 0 +#define OMAP4_STD_FUSE_IDCODE_MASK (0xffffffff << 0) + +/* STD_FUSE_DIE_ID_1 */ +#define OMAP4_STD_FUSE_DIE_ID_1_SHIFT 0 +#define OMAP4_STD_FUSE_DIE_ID_1_MASK (0xffffffff << 0) + +/* STD_FUSE_DIE_ID_2 */ +#define OMAP4_STD_FUSE_DIE_ID_2_SHIFT 0 +#define OMAP4_STD_FUSE_DIE_ID_2_MASK (0xffffffff << 0) + +/* STD_FUSE_DIE_ID_3 */ +#define OMAP4_STD_FUSE_DIE_ID_3_SHIFT 0 +#define OMAP4_STD_FUSE_DIE_ID_3_MASK (0xffffffff << 0) + +/* STD_FUSE_PROD_ID_0 */ +#define OMAP4_STD_FUSE_PROD_ID_0_SHIFT 0 +#define OMAP4_STD_FUSE_PROD_ID_0_MASK (0xffffffff << 0) + +/* STD_FUSE_PROD_ID_1 */ +#define OMAP4_STD_FUSE_PROD_ID_1_SHIFT 0 +#define OMAP4_STD_FUSE_PROD_ID_1_MASK (0xffffffff << 0) + +/* STD_FUSE_USB_CONF */ +#define OMAP4_USB_PROD_ID_SHIFT 16 +#define OMAP4_USB_PROD_ID_MASK (0xffff << 16) +#define OMAP4_USB_VENDOR_ID_SHIFT 0 +#define OMAP4_USB_VENDOR_ID_MASK (0xffff << 0) + +/* STD_FUSE_OPP_VDD_WKUP */ +#define OMAP4_STD_FUSE_OPP_VDD_WKUP_SHIFT 0 +#define OMAP4_STD_FUSE_OPP_VDD_WKUP_MASK (0xffffffff << 0) + +/* STD_FUSE_OPP_BGAP */ +#define OMAP4_STD_FUSE_OPP_BGAP_SHIFT 0 +#define OMAP4_STD_FUSE_OPP_BGAP_MASK (0xffffffff << 0) + +/* STD_FUSE_OPP_DPLL_0 */ +#define OMAP4_STD_FUSE_OPP_DPLL_0_SHIFT 0 +#define OMAP4_STD_FUSE_OPP_DPLL_0_MASK (0xffffffff << 0) + +/* STD_FUSE_OPP_DPLL_1 */ +#define OMAP4_STD_FUSE_OPP_DPLL_1_SHIFT 0 +#define OMAP4_STD_FUSE_OPP_DPLL_1_MASK (0xffffffff << 0) + +/* STATUS */ +#define OMAP4_ATTILA_CONF_SHIFT 11 +#define OMAP4_ATTILA_CONF_MASK (0x3 << 11) +#define OMAP4_DEVICE_TYPE_SHIFT 8 +#define OMAP4_DEVICE_TYPE_MASK (0x7 << 8) +#define OMAP4_SYS_BOOT_SHIFT 0 +#define OMAP4_SYS_BOOT_MASK (0xff << 0) + +/* DEV_CONF */ +#define OMAP4_DEV_CONF_SHIFT 1 +#define OMAP4_DEV_CONF_MASK (0x7fffffff << 1) +#define OMAP4_USBPHY_PD_SHIFT 0 +#define OMAP4_USBPHY_PD_MASK (1 << 0) + +/* LDOVBB_IVA_VOLTAGE_CTRL */ +#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_SHIFT 26 +#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_MASK (1 << 26) +#define OMAP4_LDOVBBIVA_RBB_VSET_IN_SHIFT 21 +#define OMAP4_LDOVBBIVA_RBB_VSET_IN_MASK (0x1f << 21) +#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_SHIFT 16 +#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_MASK (0x1f << 16) +#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_SHIFT 10 +#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_MASK (1 << 10) +#define OMAP4_LDOVBBIVA_FBB_VSET_IN_SHIFT 5 +#define OMAP4_LDOVBBIVA_FBB_VSET_IN_MASK (0x1f << 5) +#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_SHIFT 0 +#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_MASK (0x1f << 0) + +/* LDOVBB_MPU_VOLTAGE_CTRL */ +#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_SHIFT 26 +#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_MASK (1 << 26) +#define OMAP4_LDOVBBMPU_RBB_VSET_IN_SHIFT 21 +#define OMAP4_LDOVBBMPU_RBB_VSET_IN_MASK (0x1f << 21) +#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_SHIFT 16 +#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_MASK (0x1f << 16) +#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_SHIFT 10 +#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_MASK (1 << 10) +#define OMAP4_LDOVBBMPU_FBB_VSET_IN_SHIFT 5 +#define OMAP4_LDOVBBMPU_FBB_VSET_IN_MASK (0x1f << 5) +#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_SHIFT 0 +#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_MASK (0x1f << 0) + +/* LDOSRAM_IVA_VOLTAGE_CTRL */ +#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_SHIFT 26 +#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_MASK (1 << 26) +#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_SHIFT 21 +#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_MASK (0x1f << 21) +#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_SHIFT 16 +#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_MASK (0x1f << 16) +#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_SHIFT 10 +#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_MASK (1 << 10) +#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_SHIFT 5 +#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_MASK (0x1f << 5) +#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_SHIFT 0 +#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_MASK (0x1f << 0) + +/* LDOSRAM_MPU_VOLTAGE_CTRL */ +#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_SHIFT 26 +#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_MASK (1 << 26) +#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_SHIFT 21 +#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_MASK (0x1f << 21) +#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_SHIFT 16 +#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_MASK (0x1f << 16) +#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_SHIFT 10 +#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_MASK (1 << 10) +#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_SHIFT 5 +#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_MASK (0x1f << 5) +#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_SHIFT 0 +#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_MASK (0x1f << 0) + +/* LDOSRAM_CORE_VOLTAGE_CTRL */ +#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_SHIFT 26 +#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_MASK (1 << 26) +#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_SHIFT 21 +#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_MASK (0x1f << 21) +#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_SHIFT 16 +#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_MASK (0x1f << 16) +#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_SHIFT 10 +#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_MASK (1 << 10) +#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_SHIFT 5 +#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_MASK (0x1f << 5) +#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_SHIFT 0 +#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_MASK (0x1f << 0) + +/* TEMP_SENSOR */ +#define OMAP4_BGAP_TEMPSOFF_SHIFT 12 +#define OMAP4_BGAP_TEMPSOFF_MASK (1 << 12) +#define OMAP4_BGAP_TSHUT_SHIFT 11 +#define OMAP4_BGAP_TSHUT_MASK (1 << 11) +#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_SHIFT 10 +#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_MASK (1 << 10) +#define OMAP4_BGAP_TEMP_SENSOR_SOC_SHIFT 9 +#define OMAP4_BGAP_TEMP_SENSOR_SOC_MASK (1 << 9) +#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_SHIFT 8 +#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_MASK (1 << 8) +#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_SHIFT 0 +#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_MASK (0xff << 0) + +/* DPLL_NWELL_TRIM_0 */ +#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_SHIFT 29 +#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_MASK (1 << 29) +#define OMAP4_DPLL_ABE_NWELL_TRIM_SHIFT 24 +#define OMAP4_DPLL_ABE_NWELL_TRIM_MASK (0x1f << 24) +#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_SHIFT 23 +#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_MASK (1 << 23) +#define OMAP4_DPLL_PER_NWELL_TRIM_SHIFT 18 +#define OMAP4_DPLL_PER_NWELL_TRIM_MASK (0x1f << 18) +#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_SHIFT 17 +#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_MASK (1 << 17) +#define OMAP4_DPLL_CORE_NWELL_TRIM_SHIFT 12 +#define OMAP4_DPLL_CORE_NWELL_TRIM_MASK (0x1f << 12) +#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_SHIFT 11 +#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_MASK (1 << 11) +#define OMAP4_DPLL_IVA_NWELL_TRIM_SHIFT 6 +#define OMAP4_DPLL_IVA_NWELL_TRIM_MASK (0x1f << 6) +#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_SHIFT 5 +#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_MASK (1 << 5) +#define OMAP4_DPLL_MPU_NWELL_TRIM_SHIFT 0 +#define OMAP4_DPLL_MPU_NWELL_TRIM_MASK (0x1f << 0) + +/* DPLL_NWELL_TRIM_1 */ +#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_SHIFT 29 +#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_MASK (1 << 29) +#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_SHIFT 24 +#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MASK (0x1f << 24) +#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_SHIFT 23 +#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_MASK (1 << 23) +#define OMAP4_DPLL_USB_NWELL_TRIM_SHIFT 18 +#define OMAP4_DPLL_USB_NWELL_TRIM_MASK (0x1f << 18) +#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_SHIFT 17 +#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_MASK (1 << 17) +#define OMAP4_DPLL_HDMI_NWELL_TRIM_SHIFT 12 +#define OMAP4_DPLL_HDMI_NWELL_TRIM_MASK (0x1f << 12) +#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_SHIFT 11 +#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_MASK (1 << 11) +#define OMAP4_DPLL_DSI2_NWELL_TRIM_SHIFT 6 +#define OMAP4_DPLL_DSI2_NWELL_TRIM_MASK (0x1f << 6) +#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_SHIFT 5 +#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_MASK (1 << 5) +#define OMAP4_DPLL_DSI1_NWELL_TRIM_SHIFT 0 +#define OMAP4_DPLL_DSI1_NWELL_TRIM_MASK (0x1f << 0) + +/* USBOTGHS_CONTROL */ +#define OMAP4_DISCHRGVBUS_SHIFT 8 +#define OMAP4_DISCHRGVBUS_MASK (1 << 8) +#define OMAP4_CHRGVBUS_SHIFT 7 +#define OMAP4_CHRGVBUS_MASK (1 << 7) +#define OMAP4_DRVVBUS_SHIFT 6 +#define OMAP4_DRVVBUS_MASK (1 << 6) +#define OMAP4_IDPULLUP_SHIFT 5 +#define OMAP4_IDPULLUP_MASK (1 << 5) +#define OMAP4_IDDIG_SHIFT 4 +#define OMAP4_IDDIG_MASK (1 << 4) +#define OMAP4_SESSEND_SHIFT 3 +#define OMAP4_SESSEND_MASK (1 << 3) +#define OMAP4_VBUSVALID_SHIFT 2 +#define OMAP4_VBUSVALID_MASK (1 << 2) +#define OMAP4_BVALID_SHIFT 1 +#define OMAP4_BVALID_MASK (1 << 1) +#define OMAP4_AVALID_SHIFT 0 +#define OMAP4_AVALID_MASK (1 << 0) + +/* DSS_CONTROL */ +#define OMAP4_DSS_MUX6_SELECT_SHIFT 0 +#define OMAP4_DSS_MUX6_SELECT_MASK (1 << 0) + +/* HWOBS_CONTROL */ +#define OMAP4_HWOBS_CLKDIV_SEL_SHIFT 3 +#define OMAP4_HWOBS_CLKDIV_SEL_MASK (0x1f << 3) +#define OMAP4_HWOBS_ALL_ZERO_MODE_SHIFT 2 +#define OMAP4_HWOBS_ALL_ZERO_MODE_MASK (1 << 2) +#define OMAP4_HWOBS_ALL_ONE_MODE_SHIFT 1 +#define OMAP4_HWOBS_ALL_ONE_MODE_MASK (1 << 1) +#define OMAP4_HWOBS_MACRO_ENABLE_SHIFT 0 +#define OMAP4_HWOBS_MACRO_ENABLE_MASK (1 << 0) + +/* DEBOBS_FINAL_MUX_SEL */ +#define OMAP4_SELECT_SHIFT 0 +#define OMAP4_SELECT_MASK (0xffffffff << 0) + +/* DEBOBS_MMR_MPU */ +#define OMAP4_SELECT_DEBOBS_MMR_MPU_SHIFT 0 +#define OMAP4_SELECT_DEBOBS_MMR_MPU_MASK (0xf << 0) + +/* CONF_SDMA_REQ_SEL0 */ +#define OMAP4_MULT_SHIFT 0 +#define OMAP4_MULT_MASK (0x7f << 0) + +/* CONF_CLK_SEL0 */ +#define OMAP4_MULT_CONF_CLK_SEL0_SHIFT 0 +#define OMAP4_MULT_CONF_CLK_SEL0_MASK (0x7 << 0) + +/* CONF_CLK_SEL1 */ +#define OMAP4_MULT_CONF_CLK_SEL1_SHIFT 0 +#define OMAP4_MULT_CONF_CLK_SEL1_MASK (0x7 << 0) + +/* CONF_CLK_SEL2 */ +#define OMAP4_MULT_CONF_CLK_SEL2_SHIFT 0 +#define OMAP4_MULT_CONF_CLK_SEL2_MASK (0x7 << 0) + +/* CONF_DPLL_FREQLOCK_SEL */ +#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_SHIFT 0 +#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_MASK (0x7 << 0) + +/* CONF_DPLL_TINITZ_SEL */ +#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_SHIFT 0 +#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_MASK (0x7 << 0) + +/* CONF_DPLL_PHASELOCK_SEL */ +#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_SHIFT 0 +#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_MASK (0x7 << 0) + +/* CONF_DEBUG_SEL_TST_0 */ +#define OMAP4_MODE_SHIFT 0 +#define OMAP4_MODE_MASK (0xf << 0) + +#endif diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h new file mode 100644 index 000000000000..c88420de1151 --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h @@ -0,0 +1,1409 @@ +/* + * OMAP44xx CTRL_MODULE_PAD_CORE registers and bitfields + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * + * Benoit Cousson (b-cousson@ti.com) + * Santosh Shilimkar (santosh.shilimkar@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H +#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H + + +/* Base address */ +#define OMAP4_CTRL_MODULE_PAD_CORE 0x4a100000 + +/* Registers offset */ +#define OMAP4_CTRL_MODULE_PAD_CORE_IP_REVISION 0x0000 +#define OMAP4_CTRL_MODULE_PAD_CORE_IP_HWINFO 0x0004 +#define OMAP4_CTRL_MODULE_PAD_CORE_IP_SYSCONFIG 0x0010 +#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_0 0x01d8 +#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_1 0x01dc +#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_2 0x01e0 +#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_3 0x01e4 +#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_4 0x01e8 +#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_5 0x01ec +#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_6 0x01f0 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_GLOBAL 0x05a0 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_MODE 0x05a4 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_0 0x05a8 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_1 0x05ac +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_0 0x05b0 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_1 0x05b4 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_0 0x05b8 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_1 0x05bc +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_2 0x05c0 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USBB_HSIC 0x05c4 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SLIMBUS 0x05c8 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE 0x0600 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0 0x0604 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX 0x0608 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_AVDAC 0x060c +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDMI_TX_PHY 0x0610 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC2 0x0614 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY 0x0618 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP 0x061c +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB2PHYCORE 0x0620 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1 0x0624 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1 0x0628 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HSI 0x062c +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB 0x0630 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDQ 0x0634 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_0 0x0638 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_1 0x063c +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_2 0x0640 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_3 0x0644 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_0 0x0648 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_1 0x064c +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_2 0x0650 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_3 0x0654 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_BUS_HOLD 0x0658 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_C2C 0x065c +#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_RW 0x0660 +#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R 0x0664 +#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R_C0 0x0668 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_1 0x0700 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_2 0x0704 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_3 0x0708 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_4 0x070c + +/* Registers shifts and masks */ + +/* IP_REVISION */ +#define OMAP4_IP_REV_SCHEME_SHIFT 30 +#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30) +#define OMAP4_IP_REV_FUNC_SHIFT 16 +#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16) +#define OMAP4_IP_REV_RTL_SHIFT 11 +#define OMAP4_IP_REV_RTL_MASK (0x1f << 11) +#define OMAP4_IP_REV_MAJOR_SHIFT 8 +#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8) +#define OMAP4_IP_REV_CUSTOM_SHIFT 6 +#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6) +#define OMAP4_IP_REV_MINOR_SHIFT 0 +#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0) + +/* IP_HWINFO */ +#define OMAP4_IP_HWINFO_SHIFT 0 +#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0) + +/* IP_SYSCONFIG */ +#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2 +#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2) + +/* PADCONF_WAKEUPEVENT_0 */ +#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_SHIFT 31 +#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 31) +#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_SHIFT 30 +#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_MASK (1 << 30) +#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_SHIFT 29 +#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_MASK (1 << 29) +#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_SHIFT 28 +#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_MASK (1 << 28) +#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_SHIFT 27 +#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_MASK (1 << 27) +#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_SHIFT 26 +#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_MASK (1 << 26) +#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_SHIFT 25 +#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_MASK (1 << 25) +#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_SHIFT 24 +#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_MASK (1 << 24) +#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_SHIFT 23 +#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_MASK (1 << 23) +#define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_SHIFT 22 +#define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_MASK (1 << 22) +#define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_SHIFT 21 +#define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_MASK (1 << 21) +#define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_SHIFT 20 +#define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_MASK (1 << 20) +#define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_SHIFT 19 +#define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_MASK (1 << 19) +#define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_SHIFT 18 +#define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_MASK (1 << 18) +#define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_SHIFT 17 +#define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_MASK (1 << 17) +#define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_SHIFT 16 +#define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_MASK (1 << 16) +#define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_SHIFT 15 +#define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_MASK (1 << 15) +#define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_SHIFT 14 +#define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_MASK (1 << 14) +#define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_SHIFT 13 +#define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_MASK (1 << 13) +#define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_SHIFT 12 +#define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_MASK (1 << 12) +#define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_SHIFT 11 +#define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_MASK (1 << 11) +#define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_SHIFT 10 +#define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_MASK (1 << 10) +#define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_SHIFT 9 +#define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_MASK (1 << 9) +#define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_SHIFT 8 +#define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_MASK (1 << 8) +#define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_SHIFT 7 +#define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_MASK (1 << 7) +#define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_SHIFT 6 +#define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_MASK (1 << 6) +#define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_SHIFT 5 +#define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_MASK (1 << 5) +#define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_SHIFT 4 +#define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_MASK (1 << 4) +#define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_SHIFT 3 +#define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_MASK (1 << 3) +#define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_SHIFT 2 +#define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_MASK (1 << 2) +#define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_SHIFT 1 +#define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_MASK (1 << 1) +#define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_SHIFT 0 +#define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_MASK (1 << 0) + +/* PADCONF_WAKEUPEVENT_1 */ +#define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 31 +#define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 31) +#define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_SHIFT 30 +#define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_MASK (1 << 30) +#define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_SHIFT 29 +#define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_MASK (1 << 29) +#define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_SHIFT 28 +#define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_MASK (1 << 28) +#define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_SHIFT 27 +#define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_MASK (1 << 27) +#define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_SHIFT 26 +#define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_MASK (1 << 26) +#define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_SHIFT 25 +#define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_MASK (1 << 25) +#define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_SHIFT 24 +#define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_MASK (1 << 24) +#define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_SHIFT 23 +#define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_MASK (1 << 23) +#define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_SHIFT 22 +#define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_MASK (1 << 22) +#define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_SHIFT 21 +#define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_MASK (1 << 21) +#define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_SHIFT 20 +#define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_MASK (1 << 20) +#define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_SHIFT 19 +#define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_MASK (1 << 19) +#define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_SHIFT 18 +#define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_MASK (1 << 18) +#define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_SHIFT 17 +#define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_MASK (1 << 17) +#define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_SHIFT 16 +#define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_MASK (1 << 16) +#define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_SHIFT 15 +#define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 15) +#define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_SHIFT 14 +#define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 14) +#define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_SHIFT 13 +#define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_MASK (1 << 13) +#define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_SHIFT 12 +#define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_MASK (1 << 12) +#define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_SHIFT 11 +#define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_MASK (1 << 11) +#define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_SHIFT 10 +#define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_MASK (1 << 10) +#define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_SHIFT 9 +#define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_MASK (1 << 9) +#define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_SHIFT 8 +#define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_MASK (1 << 8) +#define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_SHIFT 7 +#define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_MASK (1 << 7) +#define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_SHIFT 6 +#define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_MASK (1 << 6) +#define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_SHIFT 5 +#define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_MASK (1 << 5) +#define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_SHIFT 4 +#define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_MASK (1 << 4) +#define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_SHIFT 3 +#define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_MASK (1 << 3) +#define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_SHIFT 2 +#define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_MASK (1 << 2) +#define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_SHIFT 1 +#define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_MASK (1 << 1) +#define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_SHIFT 0 +#define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_MASK (1 << 0) + +/* PADCONF_WAKEUPEVENT_2 */ +#define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_SHIFT 31 +#define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_MASK (1 << 31) +#define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_SHIFT 30 +#define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_MASK (1 << 30) +#define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_SHIFT 29 +#define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_MASK (1 << 29) +#define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_SHIFT 28 +#define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_MASK (1 << 28) +#define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_SHIFT 27 +#define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_MASK (1 << 27) +#define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 26 +#define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 26) +#define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 25 +#define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 25) +#define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 24 +#define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 24) +#define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 23 +#define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 23) +#define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 22 +#define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 22) +#define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 21 +#define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 21) +#define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 20 +#define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 20) +#define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 19 +#define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 19) +#define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_SHIFT 18 +#define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_MASK (1 << 18) +#define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_SHIFT 17 +#define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 17) +#define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_SHIFT 16 +#define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_MASK (1 << 16) +#define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_SHIFT 15 +#define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_MASK (1 << 15) +#define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 14 +#define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 14) +#define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT 13 +#define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 13) +#define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 12 +#define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 12) +#define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 11 +#define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 11) +#define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 10 +#define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 10) +#define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 9 +#define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 9) +#define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 8 +#define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 8) +#define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 7 +#define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 7) +#define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 6 +#define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 6) +#define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 5 +#define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 5) +#define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT 4 +#define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK (1 << 4) +#define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT 3 +#define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK (1 << 3) +#define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT 2 +#define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK (1 << 2) +#define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT 1 +#define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 1) +#define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_SHIFT 0 +#define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_MASK (1 << 0) + +/* PADCONF_WAKEUPEVENT_3 */ +#define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_SHIFT 31 +#define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_MASK (1 << 31) +#define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_SHIFT 30 +#define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_MASK (1 << 30) +#define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_SHIFT 29 +#define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_MASK (1 << 29) +#define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_SHIFT 28 +#define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_MASK (1 << 28) +#define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_SHIFT 27 +#define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_MASK (1 << 27) +#define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_SHIFT 26 +#define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_MASK (1 << 26) +#define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_SHIFT 25 +#define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 25) +#define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_SHIFT 24 +#define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 24) +#define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_SHIFT 23 +#define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 23) +#define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_SHIFT 22 +#define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 22) +#define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_SHIFT 21 +#define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 21) +#define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_SHIFT 20 +#define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 20) +#define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_SHIFT 19 +#define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 19) +#define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_SHIFT 18 +#define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 18) +#define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_SHIFT 17 +#define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 17) +#define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_SHIFT 16 +#define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_MASK (1 << 16) +#define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_SHIFT 15 +#define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_MASK (1 << 15) +#define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_SHIFT 14 +#define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_MASK (1 << 14) +#define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_SHIFT 13 +#define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_MASK (1 << 13) +#define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_SHIFT 12 +#define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_MASK (1 << 12) +#define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_SHIFT 11 +#define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_MASK (1 << 11) +#define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_SHIFT 10 +#define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_MASK (1 << 10) +#define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_SHIFT 9 +#define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_MASK (1 << 9) +#define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_SHIFT 8 +#define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_MASK (1 << 8) +#define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_SHIFT 7 +#define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_MASK (1 << 7) +#define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_SHIFT 6 +#define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 6) +#define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_SHIFT 5 +#define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_MASK (1 << 5) +#define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_SHIFT 4 +#define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 4) +#define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_SHIFT 3 +#define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 3) +#define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_SHIFT 2 +#define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_MASK (1 << 2) +#define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_SHIFT 1 +#define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_MASK (1 << 1) +#define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_SHIFT 0 +#define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_MASK (1 << 0) + +/* PADCONF_WAKEUPEVENT_4 */ +#define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_SHIFT 31 +#define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_MASK (1 << 31) +#define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_SHIFT 30 +#define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_MASK (1 << 30) +#define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 29 +#define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 29) +#define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT 28 +#define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 28) +#define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 27 +#define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 27) +#define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 26 +#define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 26) +#define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 25 +#define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 25) +#define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 24 +#define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 24) +#define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 23 +#define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 23) +#define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 22 +#define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 22) +#define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 21 +#define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 21) +#define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 20 +#define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 20) +#define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT 19 +#define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK (1 << 19) +#define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT 18 +#define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK (1 << 18) +#define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT 17 +#define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK (1 << 17) +#define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT 16 +#define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 16) +#define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_SHIFT 15 +#define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_MASK (1 << 15) +#define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_SHIFT 14 +#define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_MASK (1 << 14) +#define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_SHIFT 13 +#define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_MASK (1 << 13) +#define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_SHIFT 12 +#define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_MASK (1 << 12) +#define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_SHIFT 11 +#define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_MASK (1 << 11) +#define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_SHIFT 10 +#define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 10) +#define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 9 +#define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 9) +#define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 8 +#define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 8) +#define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 7 +#define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 7) +#define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 6 +#define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 6) +#define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_SHIFT 5 +#define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_MASK (1 << 5) +#define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_SHIFT 4 +#define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 4) +#define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_SHIFT 3 +#define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_MASK (1 << 3) +#define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_SHIFT 2 +#define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_MASK (1 << 2) +#define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_SHIFT 1 +#define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_MASK (1 << 1) +#define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_SHIFT 0 +#define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_MASK (1 << 0) + +/* PADCONF_WAKEUPEVENT_5 */ +#define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_SHIFT 31 +#define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_MASK (1 << 31) +#define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_SHIFT 30 +#define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_MASK (1 << 30) +#define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_SHIFT 29 +#define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_MASK (1 << 29) +#define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_SHIFT 28 +#define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_MASK (1 << 28) +#define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_SHIFT 27 +#define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_MASK (1 << 27) +#define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_SHIFT 26 +#define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_MASK (1 << 26) +#define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_SHIFT 25 +#define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_MASK (1 << 25) +#define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_SHIFT 24 +#define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_MASK (1 << 24) +#define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_SHIFT 23 +#define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_MASK (1 << 23) +#define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_SHIFT 22 +#define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_MASK (1 << 22) +#define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_SHIFT 21 +#define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_MASK (1 << 21) +#define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_SHIFT 20 +#define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_MASK (1 << 20) +#define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_SHIFT 19 +#define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_MASK (1 << 19) +#define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_SHIFT 18 +#define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_MASK (1 << 18) +#define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_SHIFT 17 +#define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_MASK (1 << 17) +#define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_SHIFT 16 +#define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_MASK (1 << 16) +#define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_SHIFT 15 +#define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_MASK (1 << 15) +#define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_SHIFT 14 +#define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_MASK (1 << 14) +#define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_SHIFT 13 +#define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_MASK (1 << 13) +#define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_SHIFT 12 +#define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_MASK (1 << 12) +#define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_SHIFT 11 +#define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 11) +#define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_SHIFT 10 +#define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 10) +#define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_SHIFT 9 +#define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_MASK (1 << 9) +#define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_SHIFT 8 +#define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_MASK (1 << 8) +#define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_SHIFT 7 +#define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_MASK (1 << 7) +#define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_SHIFT 6 +#define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_MASK (1 << 6) +#define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_SHIFT 5 +#define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_MASK (1 << 5) +#define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_SHIFT 4 +#define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_MASK (1 << 4) +#define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_SHIFT 3 +#define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_MASK (1 << 3) +#define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_SHIFT 2 +#define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_MASK (1 << 2) +#define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_SHIFT 1 +#define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_MASK (1 << 1) +#define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_SHIFT 0 +#define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_MASK (1 << 0) + +/* PADCONF_WAKEUPEVENT_6 */ +#define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_SHIFT 7 +#define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_MASK (1 << 7) +#define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_SHIFT 6 +#define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_MASK (1 << 6) +#define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_SHIFT 5 +#define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_MASK (1 << 5) +#define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_SHIFT 4 +#define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_MASK (1 << 4) +#define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_SHIFT 3 +#define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_MASK (1 << 3) +#define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_SHIFT 2 +#define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_MASK (1 << 2) +#define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_SHIFT 1 +#define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_MASK (1 << 1) +#define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_SHIFT 0 +#define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_MASK (1 << 0) + +/* CONTROL_PADCONF_GLOBAL */ +#define OMAP4_FORCE_OFFMODE_EN_SHIFT 31 +#define OMAP4_FORCE_OFFMODE_EN_MASK (1 << 31) + +/* CONTROL_PADCONF_MODE */ +#define OMAP4_VDDS_DV_BANK0_SHIFT 31 +#define OMAP4_VDDS_DV_BANK0_MASK (1 << 31) +#define OMAP4_VDDS_DV_BANK1_SHIFT 30 +#define OMAP4_VDDS_DV_BANK1_MASK (1 << 30) +#define OMAP4_VDDS_DV_BANK3_SHIFT 29 +#define OMAP4_VDDS_DV_BANK3_MASK (1 << 29) +#define OMAP4_VDDS_DV_BANK4_SHIFT 28 +#define OMAP4_VDDS_DV_BANK4_MASK (1 << 28) +#define OMAP4_VDDS_DV_BANK5_SHIFT 27 +#define OMAP4_VDDS_DV_BANK5_MASK (1 << 27) +#define OMAP4_VDDS_DV_BANK6_SHIFT 26 +#define OMAP4_VDDS_DV_BANK6_MASK (1 << 26) +#define OMAP4_VDDS_DV_C2C_SHIFT 25 +#define OMAP4_VDDS_DV_C2C_MASK (1 << 25) +#define OMAP4_VDDS_DV_CAM_SHIFT 24 +#define OMAP4_VDDS_DV_CAM_MASK (1 << 24) +#define OMAP4_VDDS_DV_GPMC_SHIFT 23 +#define OMAP4_VDDS_DV_GPMC_MASK (1 << 23) +#define OMAP4_VDDS_DV_SDMMC2_SHIFT 22 +#define OMAP4_VDDS_DV_SDMMC2_MASK (1 << 22) + +/* CONTROL_SMART1IO_PADCONF_0 */ +#define OMAP4_ABE_DR0_SC_SHIFT 30 +#define OMAP4_ABE_DR0_SC_MASK (0x3 << 30) +#define OMAP4_CAM_DR0_SC_SHIFT 28 +#define OMAP4_CAM_DR0_SC_MASK (0x3 << 28) +#define OMAP4_FREF_DR2_SC_SHIFT 26 +#define OMAP4_FREF_DR2_SC_MASK (0x3 << 26) +#define OMAP4_FREF_DR3_SC_SHIFT 24 +#define OMAP4_FREF_DR3_SC_MASK (0x3 << 24) +#define OMAP4_GPIO_DR8_SC_SHIFT 22 +#define OMAP4_GPIO_DR8_SC_MASK (0x3 << 22) +#define OMAP4_GPIO_DR9_SC_SHIFT 20 +#define OMAP4_GPIO_DR9_SC_MASK (0x3 << 20) +#define OMAP4_GPMC_DR2_SC_SHIFT 18 +#define OMAP4_GPMC_DR2_SC_MASK (0x3 << 18) +#define OMAP4_GPMC_DR3_SC_SHIFT 16 +#define OMAP4_GPMC_DR3_SC_MASK (0x3 << 16) +#define OMAP4_GPMC_DR6_SC_SHIFT 14 +#define OMAP4_GPMC_DR6_SC_MASK (0x3 << 14) +#define OMAP4_HDMI_DR0_SC_SHIFT 12 +#define OMAP4_HDMI_DR0_SC_MASK (0x3 << 12) +#define OMAP4_MCSPI1_DR0_SC_SHIFT 10 +#define OMAP4_MCSPI1_DR0_SC_MASK (0x3 << 10) +#define OMAP4_UART1_DR0_SC_SHIFT 8 +#define OMAP4_UART1_DR0_SC_MASK (0x3 << 8) +#define OMAP4_UART3_DR0_SC_SHIFT 6 +#define OMAP4_UART3_DR0_SC_MASK (0x3 << 6) +#define OMAP4_UART3_DR1_SC_SHIFT 4 +#define OMAP4_UART3_DR1_SC_MASK (0x3 << 4) +#define OMAP4_UNIPRO_DR0_SC_SHIFT 2 +#define OMAP4_UNIPRO_DR0_SC_MASK (0x3 << 2) +#define OMAP4_UNIPRO_DR1_SC_SHIFT 0 +#define OMAP4_UNIPRO_DR1_SC_MASK (0x3 << 0) + +/* CONTROL_SMART1IO_PADCONF_1 */ +#define OMAP4_ABE_DR0_LB_SHIFT 30 +#define OMAP4_ABE_DR0_LB_MASK (0x3 << 30) +#define OMAP4_CAM_DR0_LB_SHIFT 28 +#define OMAP4_CAM_DR0_LB_MASK (0x3 << 28) +#define OMAP4_FREF_DR2_LB_SHIFT 26 +#define OMAP4_FREF_DR2_LB_MASK (0x3 << 26) +#define OMAP4_FREF_DR3_LB_SHIFT 24 +#define OMAP4_FREF_DR3_LB_MASK (0x3 << 24) +#define OMAP4_GPIO_DR8_LB_SHIFT 22 +#define OMAP4_GPIO_DR8_LB_MASK (0x3 << 22) +#define OMAP4_GPIO_DR9_LB_SHIFT 20 +#define OMAP4_GPIO_DR9_LB_MASK (0x3 << 20) +#define OMAP4_GPMC_DR2_LB_SHIFT 18 +#define OMAP4_GPMC_DR2_LB_MASK (0x3 << 18) +#define OMAP4_GPMC_DR3_LB_SHIFT 16 +#define OMAP4_GPMC_DR3_LB_MASK (0x3 << 16) +#define OMAP4_GPMC_DR6_LB_SHIFT 14 +#define OMAP4_GPMC_DR6_LB_MASK (0x3 << 14) +#define OMAP4_HDMI_DR0_LB_SHIFT 12 +#define OMAP4_HDMI_DR0_LB_MASK (0x3 << 12) +#define OMAP4_MCSPI1_DR0_LB_SHIFT 10 +#define OMAP4_MCSPI1_DR0_LB_MASK (0x3 << 10) +#define OMAP4_UART1_DR0_LB_SHIFT 8 +#define OMAP4_UART1_DR0_LB_MASK (0x3 << 8) +#define OMAP4_UART3_DR0_LB_SHIFT 6 +#define OMAP4_UART3_DR0_LB_MASK (0x3 << 6) +#define OMAP4_UART3_DR1_LB_SHIFT 4 +#define OMAP4_UART3_DR1_LB_MASK (0x3 << 4) +#define OMAP4_UNIPRO_DR0_LB_SHIFT 2 +#define OMAP4_UNIPRO_DR0_LB_MASK (0x3 << 2) +#define OMAP4_UNIPRO_DR1_LB_SHIFT 0 +#define OMAP4_UNIPRO_DR1_LB_MASK (0x3 << 0) + +/* CONTROL_SMART2IO_PADCONF_0 */ +#define OMAP4_C2C_DR0_LB_SHIFT 31 +#define OMAP4_C2C_DR0_LB_MASK (1 << 31) +#define OMAP4_DPM_DR1_LB_SHIFT 30 +#define OMAP4_DPM_DR1_LB_MASK (1 << 30) +#define OMAP4_DPM_DR2_LB_SHIFT 29 +#define OMAP4_DPM_DR2_LB_MASK (1 << 29) +#define OMAP4_DPM_DR3_LB_SHIFT 28 +#define OMAP4_DPM_DR3_LB_MASK (1 << 28) +#define OMAP4_GPIO_DR0_LB_SHIFT 27 +#define OMAP4_GPIO_DR0_LB_MASK (1 << 27) +#define OMAP4_GPIO_DR1_LB_SHIFT 26 +#define OMAP4_GPIO_DR1_LB_MASK (1 << 26) +#define OMAP4_GPIO_DR10_LB_SHIFT 25 +#define OMAP4_GPIO_DR10_LB_MASK (1 << 25) +#define OMAP4_GPIO_DR2_LB_SHIFT 24 +#define OMAP4_GPIO_DR2_LB_MASK (1 << 24) +#define OMAP4_GPMC_DR0_LB_SHIFT 23 +#define OMAP4_GPMC_DR0_LB_MASK (1 << 23) +#define OMAP4_GPMC_DR1_LB_SHIFT 22 +#define OMAP4_GPMC_DR1_LB_MASK (1 << 22) +#define OMAP4_GPMC_DR4_LB_SHIFT 21 +#define OMAP4_GPMC_DR4_LB_MASK (1 << 21) +#define OMAP4_GPMC_DR5_LB_SHIFT 20 +#define OMAP4_GPMC_DR5_LB_MASK (1 << 20) +#define OMAP4_GPMC_DR7_LB_SHIFT 19 +#define OMAP4_GPMC_DR7_LB_MASK (1 << 19) +#define OMAP4_HSI2_DR0_LB_SHIFT 18 +#define OMAP4_HSI2_DR0_LB_MASK (1 << 18) +#define OMAP4_HSI2_DR1_LB_SHIFT 17 +#define OMAP4_HSI2_DR1_LB_MASK (1 << 17) +#define OMAP4_HSI2_DR2_LB_SHIFT 16 +#define OMAP4_HSI2_DR2_LB_MASK (1 << 16) +#define OMAP4_KPD_DR0_LB_SHIFT 15 +#define OMAP4_KPD_DR0_LB_MASK (1 << 15) +#define OMAP4_KPD_DR1_LB_SHIFT 14 +#define OMAP4_KPD_DR1_LB_MASK (1 << 14) +#define OMAP4_PDM_DR0_LB_SHIFT 13 +#define OMAP4_PDM_DR0_LB_MASK (1 << 13) +#define OMAP4_SDMMC2_DR0_LB_SHIFT 12 +#define OMAP4_SDMMC2_DR0_LB_MASK (1 << 12) +#define OMAP4_SDMMC3_DR0_LB_SHIFT 11 +#define OMAP4_SDMMC3_DR0_LB_MASK (1 << 11) +#define OMAP4_SDMMC4_DR0_LB_SHIFT 10 +#define OMAP4_SDMMC4_DR0_LB_MASK (1 << 10) +#define OMAP4_SDMMC4_DR1_LB_SHIFT 9 +#define OMAP4_SDMMC4_DR1_LB_MASK (1 << 9) +#define OMAP4_SPI3_DR0_LB_SHIFT 8 +#define OMAP4_SPI3_DR0_LB_MASK (1 << 8) +#define OMAP4_SPI3_DR1_LB_SHIFT 7 +#define OMAP4_SPI3_DR1_LB_MASK (1 << 7) +#define OMAP4_UART3_DR2_LB_SHIFT 6 +#define OMAP4_UART3_DR2_LB_MASK (1 << 6) +#define OMAP4_UART3_DR3_LB_SHIFT 5 +#define OMAP4_UART3_DR3_LB_MASK (1 << 5) +#define OMAP4_UART3_DR4_LB_SHIFT 4 +#define OMAP4_UART3_DR4_LB_MASK (1 << 4) +#define OMAP4_UART3_DR5_LB_SHIFT 3 +#define OMAP4_UART3_DR5_LB_MASK (1 << 3) +#define OMAP4_USBA0_DR1_LB_SHIFT 2 +#define OMAP4_USBA0_DR1_LB_MASK (1 << 2) +#define OMAP4_USBA_DR2_LB_SHIFT 1 +#define OMAP4_USBA_DR2_LB_MASK (1 << 1) + +/* CONTROL_SMART2IO_PADCONF_1 */ +#define OMAP4_USBB1_DR0_LB_SHIFT 31 +#define OMAP4_USBB1_DR0_LB_MASK (1 << 31) +#define OMAP4_USBB2_DR0_LB_SHIFT 30 +#define OMAP4_USBB2_DR0_LB_MASK (1 << 30) +#define OMAP4_USBA0_DR0_LB_SHIFT 29 +#define OMAP4_USBA0_DR0_LB_MASK (1 << 29) + +/* CONTROL_SMART3IO_PADCONF_0 */ +#define OMAP4_DMIC_DR0_MB_SHIFT 30 +#define OMAP4_DMIC_DR0_MB_MASK (0x3 << 30) +#define OMAP4_GPIO_DR3_MB_SHIFT 28 +#define OMAP4_GPIO_DR3_MB_MASK (0x3 << 28) +#define OMAP4_GPIO_DR4_MB_SHIFT 26 +#define OMAP4_GPIO_DR4_MB_MASK (0x3 << 26) +#define OMAP4_GPIO_DR5_MB_SHIFT 24 +#define OMAP4_GPIO_DR5_MB_MASK (0x3 << 24) +#define OMAP4_GPIO_DR6_MB_SHIFT 22 +#define OMAP4_GPIO_DR6_MB_MASK (0x3 << 22) +#define OMAP4_HSI_DR1_MB_SHIFT 20 +#define OMAP4_HSI_DR1_MB_MASK (0x3 << 20) +#define OMAP4_HSI_DR2_MB_SHIFT 18 +#define OMAP4_HSI_DR2_MB_MASK (0x3 << 18) +#define OMAP4_HSI_DR3_MB_SHIFT 16 +#define OMAP4_HSI_DR3_MB_MASK (0x3 << 16) +#define OMAP4_MCBSP2_DR0_MB_SHIFT 14 +#define OMAP4_MCBSP2_DR0_MB_MASK (0x3 << 14) +#define OMAP4_MCSPI4_DR0_MB_SHIFT 12 +#define OMAP4_MCSPI4_DR0_MB_MASK (0x3 << 12) +#define OMAP4_MCSPI4_DR1_MB_SHIFT 10 +#define OMAP4_MCSPI4_DR1_MB_MASK (0x3 << 10) +#define OMAP4_SDMMC3_DR0_MB_SHIFT 8 +#define OMAP4_SDMMC3_DR0_MB_MASK (0x3 << 8) +#define OMAP4_SPI2_DR0_MB_SHIFT 0 +#define OMAP4_SPI2_DR0_MB_MASK (0x3 << 0) + +/* CONTROL_SMART3IO_PADCONF_1 */ +#define OMAP4_SPI2_DR1_MB_SHIFT 30 +#define OMAP4_SPI2_DR1_MB_MASK (0x3 << 30) +#define OMAP4_SPI2_DR2_MB_SHIFT 28 +#define OMAP4_SPI2_DR2_MB_MASK (0x3 << 28) +#define OMAP4_UART2_DR0_MB_SHIFT 26 +#define OMAP4_UART2_DR0_MB_MASK (0x3 << 26) +#define OMAP4_UART2_DR1_MB_SHIFT 24 +#define OMAP4_UART2_DR1_MB_MASK (0x3 << 24) +#define OMAP4_UART4_DR0_MB_SHIFT 22 +#define OMAP4_UART4_DR0_MB_MASK (0x3 << 22) +#define OMAP4_HSI_DR0_MB_SHIFT 20 +#define OMAP4_HSI_DR0_MB_MASK (0x3 << 20) + +/* CONTROL_SMART3IO_PADCONF_2 */ +#define OMAP4_DMIC_DR0_LB_SHIFT 31 +#define OMAP4_DMIC_DR0_LB_MASK (1 << 31) +#define OMAP4_GPIO_DR3_LB_SHIFT 30 +#define OMAP4_GPIO_DR3_LB_MASK (1 << 30) +#define OMAP4_GPIO_DR4_LB_SHIFT 29 +#define OMAP4_GPIO_DR4_LB_MASK (1 << 29) +#define OMAP4_GPIO_DR5_LB_SHIFT 28 +#define OMAP4_GPIO_DR5_LB_MASK (1 << 28) +#define OMAP4_GPIO_DR6_LB_SHIFT 27 +#define OMAP4_GPIO_DR6_LB_MASK (1 << 27) +#define OMAP4_HSI_DR1_LB_SHIFT 26 +#define OMAP4_HSI_DR1_LB_MASK (1 << 26) +#define OMAP4_HSI_DR2_LB_SHIFT 25 +#define OMAP4_HSI_DR2_LB_MASK (1 << 25) +#define OMAP4_HSI_DR3_LB_SHIFT 24 +#define OMAP4_HSI_DR3_LB_MASK (1 << 24) +#define OMAP4_MCBSP2_DR0_LB_SHIFT 23 +#define OMAP4_MCBSP2_DR0_LB_MASK (1 << 23) +#define OMAP4_MCSPI4_DR0_LB_SHIFT 22 +#define OMAP4_MCSPI4_DR0_LB_MASK (1 << 22) +#define OMAP4_MCSPI4_DR1_LB_SHIFT 21 +#define OMAP4_MCSPI4_DR1_LB_MASK (1 << 21) +#define OMAP4_SLIMBUS2_DR0_LB_SHIFT 18 +#define OMAP4_SLIMBUS2_DR0_LB_MASK (1 << 18) +#define OMAP4_SPI2_DR0_LB_SHIFT 16 +#define OMAP4_SPI2_DR0_LB_MASK (1 << 16) +#define OMAP4_SPI2_DR1_LB_SHIFT 15 +#define OMAP4_SPI2_DR1_LB_MASK (1 << 15) +#define OMAP4_SPI2_DR2_LB_SHIFT 14 +#define OMAP4_SPI2_DR2_LB_MASK (1 << 14) +#define OMAP4_UART2_DR0_LB_SHIFT 13 +#define OMAP4_UART2_DR0_LB_MASK (1 << 13) +#define OMAP4_UART2_DR1_LB_SHIFT 12 +#define OMAP4_UART2_DR1_LB_MASK (1 << 12) +#define OMAP4_UART4_DR0_LB_SHIFT 11 +#define OMAP4_UART4_DR0_LB_MASK (1 << 11) +#define OMAP4_HSI_DR0_LB_SHIFT 10 +#define OMAP4_HSI_DR0_LB_MASK (1 << 10) + +/* CONTROL_USBB_HSIC */ +#define OMAP4_USBB2_DR1_SR_SHIFT 30 +#define OMAP4_USBB2_DR1_SR_MASK (0x3 << 30) +#define OMAP4_USBB2_DR1_I_SHIFT 27 +#define OMAP4_USBB2_DR1_I_MASK (0x7 << 27) +#define OMAP4_USBB1_DR1_SR_SHIFT 25 +#define OMAP4_USBB1_DR1_SR_MASK (0x3 << 25) +#define OMAP4_USBB1_DR1_I_SHIFT 22 +#define OMAP4_USBB1_DR1_I_MASK (0x7 << 22) +#define OMAP4_USBB1_HSIC_DATA_WD_SHIFT 20 +#define OMAP4_USBB1_HSIC_DATA_WD_MASK (0x3 << 20) +#define OMAP4_USBB1_HSIC_STROBE_WD_SHIFT 18 +#define OMAP4_USBB1_HSIC_STROBE_WD_MASK (0x3 << 18) +#define OMAP4_USBB2_HSIC_DATA_WD_SHIFT 16 +#define OMAP4_USBB2_HSIC_DATA_WD_MASK (0x3 << 16) +#define OMAP4_USBB2_HSIC_STROBE_WD_SHIFT 14 +#define OMAP4_USBB2_HSIC_STROBE_WD_MASK (0x3 << 14) +#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT 13 +#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_MASK (1 << 13) +#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_SHIFT 11 +#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_MASK (0x3 << 11) +#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT 10 +#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK (1 << 10) +#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_SHIFT 8 +#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_MASK (0x3 << 8) +#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT 7 +#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_MASK (1 << 7) +#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_SHIFT 5 +#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_MASK (0x3 << 5) +#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT 4 +#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK (1 << 4) +#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_SHIFT 2 +#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_MASK (0x3 << 2) + +/* CONTROL_SLIMBUS */ +#define OMAP4_SLIMBUS1_DR0_MB_SHIFT 30 +#define OMAP4_SLIMBUS1_DR0_MB_MASK (0x3 << 30) +#define OMAP4_SLIMBUS1_DR1_MB_SHIFT 28 +#define OMAP4_SLIMBUS1_DR1_MB_MASK (0x3 << 28) +#define OMAP4_SLIMBUS2_DR0_MB_SHIFT 26 +#define OMAP4_SLIMBUS2_DR0_MB_MASK (0x3 << 26) +#define OMAP4_SLIMBUS2_DR1_MB_SHIFT 24 +#define OMAP4_SLIMBUS2_DR1_MB_MASK (0x3 << 24) +#define OMAP4_SLIMBUS2_DR2_MB_SHIFT 22 +#define OMAP4_SLIMBUS2_DR2_MB_MASK (0x3 << 22) +#define OMAP4_SLIMBUS2_DR3_MB_SHIFT 20 +#define OMAP4_SLIMBUS2_DR3_MB_MASK (0x3 << 20) +#define OMAP4_SLIMBUS1_DR0_LB_SHIFT 19 +#define OMAP4_SLIMBUS1_DR0_LB_MASK (1 << 19) +#define OMAP4_SLIMBUS2_DR1_LB_SHIFT 18 +#define OMAP4_SLIMBUS2_DR1_LB_MASK (1 << 18) + +/* CONTROL_PBIASLITE */ +#define OMAP4_USIM_PBIASLITE_HIZ_MODE_SHIFT 31 +#define OMAP4_USIM_PBIASLITE_HIZ_MODE_MASK (1 << 31) +#define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_SHIFT 30 +#define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_MASK (1 << 30) +#define OMAP4_USIM_PBIASLITE_VMODE_ERROR_SHIFT 29 +#define OMAP4_USIM_PBIASLITE_VMODE_ERROR_MASK (1 << 29) +#define OMAP4_USIM_PBIASLITE_PWRDNZ_SHIFT 28 +#define OMAP4_USIM_PBIASLITE_PWRDNZ_MASK (1 << 28) +#define OMAP4_USIM_PBIASLITE_VMODE_SHIFT 27 +#define OMAP4_USIM_PBIASLITE_VMODE_MASK (1 << 27) +#define OMAP4_MMC1_PWRDNZ_SHIFT 26 +#define OMAP4_MMC1_PWRDNZ_MASK (1 << 26) +#define OMAP4_MMC1_PBIASLITE_HIZ_MODE_SHIFT 25 +#define OMAP4_MMC1_PBIASLITE_HIZ_MODE_MASK (1 << 25) +#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_SHIFT 24 +#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_MASK (1 << 24) +#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_SHIFT 23 +#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK (1 << 23) +#define OMAP4_MMC1_PBIASLITE_PWRDNZ_SHIFT 22 +#define OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK (1 << 22) +#define OMAP4_MMC1_PBIASLITE_VMODE_SHIFT 21 +#define OMAP4_MMC1_PBIASLITE_VMODE_MASK (1 << 21) +#define OMAP4_USBC1_ICUSB_PWRDNZ_SHIFT 20 +#define OMAP4_USBC1_ICUSB_PWRDNZ_MASK (1 << 20) + +/* CONTROL_I2C_0 */ +#define OMAP4_I2C4_SDA_GLFENB_SHIFT 31 +#define OMAP4_I2C4_SDA_GLFENB_MASK (1 << 31) +#define OMAP4_I2C4_SDA_LOAD_BITS_SHIFT 29 +#define OMAP4_I2C4_SDA_LOAD_BITS_MASK (0x3 << 29) +#define OMAP4_I2C4_SDA_PULLUPRESX_SHIFT 28 +#define OMAP4_I2C4_SDA_PULLUPRESX_MASK (1 << 28) +#define OMAP4_I2C3_SDA_GLFENB_SHIFT 27 +#define OMAP4_I2C3_SDA_GLFENB_MASK (1 << 27) +#define OMAP4_I2C3_SDA_LOAD_BITS_SHIFT 25 +#define OMAP4_I2C3_SDA_LOAD_BITS_MASK (0x3 << 25) +#define OMAP4_I2C3_SDA_PULLUPRESX_SHIFT 24 +#define OMAP4_I2C3_SDA_PULLUPRESX_MASK (1 << 24) +#define OMAP4_I2C2_SDA_GLFENB_SHIFT 23 +#define OMAP4_I2C2_SDA_GLFENB_MASK (1 << 23) +#define OMAP4_I2C2_SDA_LOAD_BITS_SHIFT 21 +#define OMAP4_I2C2_SDA_LOAD_BITS_MASK (0x3 << 21) +#define OMAP4_I2C2_SDA_PULLUPRESX_SHIFT 20 +#define OMAP4_I2C2_SDA_PULLUPRESX_MASK (1 << 20) +#define OMAP4_I2C1_SDA_GLFENB_SHIFT 19 +#define OMAP4_I2C1_SDA_GLFENB_MASK (1 << 19) +#define OMAP4_I2C1_SDA_LOAD_BITS_SHIFT 17 +#define OMAP4_I2C1_SDA_LOAD_BITS_MASK (0x3 << 17) +#define OMAP4_I2C1_SDA_PULLUPRESX_SHIFT 16 +#define OMAP4_I2C1_SDA_PULLUPRESX_MASK (1 << 16) +#define OMAP4_I2C4_SCL_GLFENB_SHIFT 15 +#define OMAP4_I2C4_SCL_GLFENB_MASK (1 << 15) +#define OMAP4_I2C4_SCL_LOAD_BITS_SHIFT 13 +#define OMAP4_I2C4_SCL_LOAD_BITS_MASK (0x3 << 13) +#define OMAP4_I2C4_SCL_PULLUPRESX_SHIFT 12 +#define OMAP4_I2C4_SCL_PULLUPRESX_MASK (1 << 12) +#define OMAP4_I2C3_SCL_GLFENB_SHIFT 11 +#define OMAP4_I2C3_SCL_GLFENB_MASK (1 << 11) +#define OMAP4_I2C3_SCL_LOAD_BITS_SHIFT 9 +#define OMAP4_I2C3_SCL_LOAD_BITS_MASK (0x3 << 9) +#define OMAP4_I2C3_SCL_PULLUPRESX_SHIFT 8 +#define OMAP4_I2C3_SCL_PULLUPRESX_MASK (1 << 8) +#define OMAP4_I2C2_SCL_GLFENB_SHIFT 7 +#define OMAP4_I2C2_SCL_GLFENB_MASK (1 << 7) +#define OMAP4_I2C2_SCL_LOAD_BITS_SHIFT 5 +#define OMAP4_I2C2_SCL_LOAD_BITS_MASK (0x3 << 5) +#define OMAP4_I2C2_SCL_PULLUPRESX_SHIFT 4 +#define OMAP4_I2C2_SCL_PULLUPRESX_MASK (1 << 4) +#define OMAP4_I2C1_SCL_GLFENB_SHIFT 3 +#define OMAP4_I2C1_SCL_GLFENB_MASK (1 << 3) +#define OMAP4_I2C1_SCL_LOAD_BITS_SHIFT 1 +#define OMAP4_I2C1_SCL_LOAD_BITS_MASK (0x3 << 1) +#define OMAP4_I2C1_SCL_PULLUPRESX_SHIFT 0 +#define OMAP4_I2C1_SCL_PULLUPRESX_MASK (1 << 0) + +/* CONTROL_CAMERA_RX */ +#define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_SHIFT 31 +#define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_MASK (1 << 31) +#define OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT 29 +#define OMAP4_CAMERARX_CSI22_LANEENABLE_MASK (0x3 << 29) +#define OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT 24 +#define OMAP4_CAMERARX_CSI21_LANEENABLE_MASK (0x1f << 24) +#define OMAP4_CAMERARX_UNIPRO_CAMMODE_SHIFT 22 +#define OMAP4_CAMERARX_UNIPRO_CAMMODE_MASK (0x3 << 22) +#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_SHIFT 21 +#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK (1 << 21) +#define OMAP4_CAMERARX_CSI22_CAMMODE_SHIFT 19 +#define OMAP4_CAMERARX_CSI22_CAMMODE_MASK (0x3 << 19) +#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_SHIFT 18 +#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK (1 << 18) +#define OMAP4_CAMERARX_CSI21_CAMMODE_SHIFT 16 +#define OMAP4_CAMERARX_CSI21_CAMMODE_MASK (0x3 << 16) + +/* CONTROL_AVDAC */ +#define OMAP4_AVDAC_ACEN_SHIFT 31 +#define OMAP4_AVDAC_ACEN_MASK (1 << 31) +#define OMAP4_AVDAC_TVOUTBYPASS_SHIFT 30 +#define OMAP4_AVDAC_TVOUTBYPASS_MASK (1 << 30) +#define OMAP4_AVDAC_INPUTINV_SHIFT 29 +#define OMAP4_AVDAC_INPUTINV_MASK (1 << 29) +#define OMAP4_AVDAC_CTL_SHIFT 13 +#define OMAP4_AVDAC_CTL_MASK (0xffff << 13) +#define OMAP4_AVDAC_CTL_WR_ACK_SHIFT 12 +#define OMAP4_AVDAC_CTL_WR_ACK_MASK (1 << 12) + +/* CONTROL_HDMI_TX_PHY */ +#define OMAP4_HDMITXPHY_PADORDER_SHIFT 31 +#define OMAP4_HDMITXPHY_PADORDER_MASK (1 << 31) +#define OMAP4_HDMITXPHY_TXVALID_SHIFT 30 +#define OMAP4_HDMITXPHY_TXVALID_MASK (1 << 30) +#define OMAP4_HDMITXPHY_ENBYPASSCLK_SHIFT 29 +#define OMAP4_HDMITXPHY_ENBYPASSCLK_MASK (1 << 29) +#define OMAP4_HDMITXPHY_PD_PULLUPDET_SHIFT 28 +#define OMAP4_HDMITXPHY_PD_PULLUPDET_MASK (1 << 28) + +/* CONTROL_MMC2 */ +#define OMAP4_MMC2_FEEDBACK_CLK_SEL_SHIFT 31 +#define OMAP4_MMC2_FEEDBACK_CLK_SEL_MASK (1 << 31) + +/* CONTROL_DSIPHY */ +#define OMAP4_DSI2_LANEENABLE_SHIFT 29 +#define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29) +#define OMAP4_DSI1_LANEENABLE_SHIFT 24 +#define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24) +#define OMAP4_DSI1_PIPD_SHIFT 19 +#define OMAP4_DSI1_PIPD_MASK (0x1f << 19) +#define OMAP4_DSI2_PIPD_SHIFT 14 +#define OMAP4_DSI2_PIPD_MASK (0x1f << 14) + +/* CONTROL_MCBSPLP */ +#define OMAP4_ALBCTRLRX_FSX_SHIFT 31 +#define OMAP4_ALBCTRLRX_FSX_MASK (1 << 31) +#define OMAP4_ALBCTRLRX_CLKX_SHIFT 30 +#define OMAP4_ALBCTRLRX_CLKX_MASK (1 << 30) +#define OMAP4_ABE_MCBSP1_DR_EN_SHIFT 29 +#define OMAP4_ABE_MCBSP1_DR_EN_MASK (1 << 29) + +/* CONTROL_USB2PHYCORE */ +#define OMAP4_USB2PHY_AUTORESUME_EN_SHIFT 31 +#define OMAP4_USB2PHY_AUTORESUME_EN_MASK (1 << 31) +#define OMAP4_USB2PHY_DISCHGDET_SHIFT 30 +#define OMAP4_USB2PHY_DISCHGDET_MASK (1 << 30) +#define OMAP4_USB2PHY_GPIOMODE_SHIFT 29 +#define OMAP4_USB2PHY_GPIOMODE_MASK (1 << 29) +#define OMAP4_USB2PHY_CHG_DET_EXT_CTL_SHIFT 28 +#define OMAP4_USB2PHY_CHG_DET_EXT_CTL_MASK (1 << 28) +#define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_SHIFT 27 +#define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_MASK (1 << 27) +#define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_SHIFT 26 +#define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_MASK (1 << 26) +#define OMAP4_USB2PHY_CHG_VSRC_EN_SHIFT 25 +#define OMAP4_USB2PHY_CHG_VSRC_EN_MASK (1 << 25) +#define OMAP4_USB2PHY_CHG_ISINK_EN_SHIFT 24 +#define OMAP4_USB2PHY_CHG_ISINK_EN_MASK (1 << 24) +#define OMAP4_USB2PHY_CHG_DET_STATUS_SHIFT 21 +#define OMAP4_USB2PHY_CHG_DET_STATUS_MASK (0x7 << 21) +#define OMAP4_USB2PHY_CHG_DET_DM_COMP_SHIFT 20 +#define OMAP4_USB2PHY_CHG_DET_DM_COMP_MASK (1 << 20) +#define OMAP4_USB2PHY_CHG_DET_DP_COMP_SHIFT 19 +#define OMAP4_USB2PHY_CHG_DET_DP_COMP_MASK (1 << 19) +#define OMAP4_USB2PHY_DATADET_SHIFT 18 +#define OMAP4_USB2PHY_DATADET_MASK (1 << 18) +#define OMAP4_USB2PHY_SINKONDP_SHIFT 17 +#define OMAP4_USB2PHY_SINKONDP_MASK (1 << 17) +#define OMAP4_USB2PHY_SRCONDM_SHIFT 16 +#define OMAP4_USB2PHY_SRCONDM_MASK (1 << 16) +#define OMAP4_USB2PHY_RESTARTCHGDET_SHIFT 15 +#define OMAP4_USB2PHY_RESTARTCHGDET_MASK (1 << 15) +#define OMAP4_USB2PHY_CHGDETDONE_SHIFT 14 +#define OMAP4_USB2PHY_CHGDETDONE_MASK (1 << 14) +#define OMAP4_USB2PHY_CHGDETECTED_SHIFT 13 +#define OMAP4_USB2PHY_CHGDETECTED_MASK (1 << 13) +#define OMAP4_USB2PHY_MCPCPUEN_SHIFT 12 +#define OMAP4_USB2PHY_MCPCPUEN_MASK (1 << 12) +#define OMAP4_USB2PHY_MCPCMODEEN_SHIFT 11 +#define OMAP4_USB2PHY_MCPCMODEEN_MASK (1 << 11) +#define OMAP4_USB2PHY_RESETDONEMCLK_SHIFT 10 +#define OMAP4_USB2PHY_RESETDONEMCLK_MASK (1 << 10) +#define OMAP4_USB2PHY_UTMIRESETDONE_SHIFT 9 +#define OMAP4_USB2PHY_UTMIRESETDONE_MASK (1 << 9) +#define OMAP4_USB2PHY_TXBITSTUFFENABLE_SHIFT 8 +#define OMAP4_USB2PHY_TXBITSTUFFENABLE_MASK (1 << 8) +#define OMAP4_USB2PHY_DATAPOLARITYN_SHIFT 7 +#define OMAP4_USB2PHY_DATAPOLARITYN_MASK (1 << 7) +#define OMAP4_USBDPLL_FREQLOCK_SHIFT 6 +#define OMAP4_USBDPLL_FREQLOCK_MASK (1 << 6) +#define OMAP4_USB2PHY_RESETDONETCLK_SHIFT 5 +#define OMAP4_USB2PHY_RESETDONETCLK_MASK (1 << 5) + +/* CONTROL_I2C_1 */ +#define OMAP4_HDMI_DDC_SDA_GLFENB_SHIFT 31 +#define OMAP4_HDMI_DDC_SDA_GLFENB_MASK (1 << 31) +#define OMAP4_HDMI_DDC_SDA_LOAD_BITS_SHIFT 29 +#define OMAP4_HDMI_DDC_SDA_LOAD_BITS_MASK (0x3 << 29) +#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_SHIFT 28 +#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK (1 << 28) +#define OMAP4_HDMI_DDC_SCL_GLFENB_SHIFT 27 +#define OMAP4_HDMI_DDC_SCL_GLFENB_MASK (1 << 27) +#define OMAP4_HDMI_DDC_SCL_LOAD_BITS_SHIFT 25 +#define OMAP4_HDMI_DDC_SCL_LOAD_BITS_MASK (0x3 << 25) +#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_SHIFT 24 +#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK (1 << 24) +#define OMAP4_HDMI_DDC_SDA_HSMODE_SHIFT 23 +#define OMAP4_HDMI_DDC_SDA_HSMODE_MASK (1 << 23) +#define OMAP4_HDMI_DDC_SDA_NMODE_SHIFT 22 +#define OMAP4_HDMI_DDC_SDA_NMODE_MASK (1 << 22) +#define OMAP4_HDMI_DDC_SCL_HSMODE_SHIFT 21 +#define OMAP4_HDMI_DDC_SCL_HSMODE_MASK (1 << 21) +#define OMAP4_HDMI_DDC_SCL_NMODE_SHIFT 20 +#define OMAP4_HDMI_DDC_SCL_NMODE_MASK (1 << 20) + +/* CONTROL_MMC1 */ +#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_SHIFT 31 +#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK (1 << 31) +#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_SHIFT 30 +#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK (1 << 30) +#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_SHIFT 29 +#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK (1 << 29) +#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_SHIFT 28 +#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK (1 << 28) +#define OMAP4_SDMMC1_DR0_SPEEDCTRL_SHIFT 27 +#define OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK (1 << 27) +#define OMAP4_SDMMC1_DR1_SPEEDCTRL_SHIFT 26 +#define OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK (1 << 26) +#define OMAP4_SDMMC1_DR2_SPEEDCTRL_SHIFT 25 +#define OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK (1 << 25) +#define OMAP4_USBC1_DR0_SPEEDCTRL_SHIFT 24 +#define OMAP4_USBC1_DR0_SPEEDCTRL_MASK (1 << 24) +#define OMAP4_USB_FD_CDEN_SHIFT 23 +#define OMAP4_USB_FD_CDEN_MASK (1 << 23) +#define OMAP4_USBC1_ICUSB_DP_PDDIS_SHIFT 22 +#define OMAP4_USBC1_ICUSB_DP_PDDIS_MASK (1 << 22) +#define OMAP4_USBC1_ICUSB_DM_PDDIS_SHIFT 21 +#define OMAP4_USBC1_ICUSB_DM_PDDIS_MASK (1 << 21) + +/* CONTROL_HSI */ +#define OMAP4_HSI1_CALLOOP_SEL_SHIFT 31 +#define OMAP4_HSI1_CALLOOP_SEL_MASK (1 << 31) +#define OMAP4_HSI1_CALMUX_SEL_SHIFT 30 +#define OMAP4_HSI1_CALMUX_SEL_MASK (1 << 30) +#define OMAP4_HSI2_CALLOOP_SEL_SHIFT 29 +#define OMAP4_HSI2_CALLOOP_SEL_MASK (1 << 29) +#define OMAP4_HSI2_CALMUX_SEL_SHIFT 28 +#define OMAP4_HSI2_CALMUX_SEL_MASK (1 << 28) + +/* CONTROL_USB */ +#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_SHIFT 31 +#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_MASK (1 << 31) +#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_SHIFT 30 +#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_MASK (1 << 30) + +/* CONTROL_HDQ */ +#define OMAP4_HDQ_SIO_PWRDNZ_SHIFT 31 +#define OMAP4_HDQ_SIO_PWRDNZ_MASK (1 << 31) + +/* CONTROL_LPDDR2IO1_0 */ +#define OMAP4_LPDDR2IO1_GR4_SR_SHIFT 30 +#define OMAP4_LPDDR2IO1_GR4_SR_MASK (0x3 << 30) +#define OMAP4_LPDDR2IO1_GR4_I_SHIFT 27 +#define OMAP4_LPDDR2IO1_GR4_I_MASK (0x7 << 27) +#define OMAP4_LPDDR2IO1_GR4_WD_SHIFT 25 +#define OMAP4_LPDDR2IO1_GR4_WD_MASK (0x3 << 25) +#define OMAP4_LPDDR2IO1_GR3_SR_SHIFT 22 +#define OMAP4_LPDDR2IO1_GR3_SR_MASK (0x3 << 22) +#define OMAP4_LPDDR2IO1_GR3_I_SHIFT 19 +#define OMAP4_LPDDR2IO1_GR3_I_MASK (0x7 << 19) +#define OMAP4_LPDDR2IO1_GR3_WD_SHIFT 17 +#define OMAP4_LPDDR2IO1_GR3_WD_MASK (0x3 << 17) +#define OMAP4_LPDDR2IO1_GR2_SR_SHIFT 14 +#define OMAP4_LPDDR2IO1_GR2_SR_MASK (0x3 << 14) +#define OMAP4_LPDDR2IO1_GR2_I_SHIFT 11 +#define OMAP4_LPDDR2IO1_GR2_I_MASK (0x7 << 11) +#define OMAP4_LPDDR2IO1_GR2_WD_SHIFT 9 +#define OMAP4_LPDDR2IO1_GR2_WD_MASK (0x3 << 9) +#define OMAP4_LPDDR2IO1_GR1_SR_SHIFT 6 +#define OMAP4_LPDDR2IO1_GR1_SR_MASK (0x3 << 6) +#define OMAP4_LPDDR2IO1_GR1_I_SHIFT 3 +#define OMAP4_LPDDR2IO1_GR1_I_MASK (0x7 << 3) +#define OMAP4_LPDDR2IO1_GR1_WD_SHIFT 1 +#define OMAP4_LPDDR2IO1_GR1_WD_MASK (0x3 << 1) + +/* CONTROL_LPDDR2IO1_1 */ +#define OMAP4_LPDDR2IO1_GR8_SR_SHIFT 30 +#define OMAP4_LPDDR2IO1_GR8_SR_MASK (0x3 << 30) +#define OMAP4_LPDDR2IO1_GR8_I_SHIFT 27 +#define OMAP4_LPDDR2IO1_GR8_I_MASK (0x7 << 27) +#define OMAP4_LPDDR2IO1_GR8_WD_SHIFT 25 +#define OMAP4_LPDDR2IO1_GR8_WD_MASK (0x3 << 25) +#define OMAP4_LPDDR2IO1_GR7_SR_SHIFT 22 +#define OMAP4_LPDDR2IO1_GR7_SR_MASK (0x3 << 22) +#define OMAP4_LPDDR2IO1_GR7_I_SHIFT 19 +#define OMAP4_LPDDR2IO1_GR7_I_MASK (0x7 << 19) +#define OMAP4_LPDDR2IO1_GR7_WD_SHIFT 17 +#define OMAP4_LPDDR2IO1_GR7_WD_MASK (0x3 << 17) +#define OMAP4_LPDDR2IO1_GR6_SR_SHIFT 14 +#define OMAP4_LPDDR2IO1_GR6_SR_MASK (0x3 << 14) +#define OMAP4_LPDDR2IO1_GR6_I_SHIFT 11 +#define OMAP4_LPDDR2IO1_GR6_I_MASK (0x7 << 11) +#define OMAP4_LPDDR2IO1_GR6_WD_SHIFT 9 +#define OMAP4_LPDDR2IO1_GR6_WD_MASK (0x3 << 9) +#define OMAP4_LPDDR2IO1_GR5_SR_SHIFT 6 +#define OMAP4_LPDDR2IO1_GR5_SR_MASK (0x3 << 6) +#define OMAP4_LPDDR2IO1_GR5_I_SHIFT 3 +#define OMAP4_LPDDR2IO1_GR5_I_MASK (0x7 << 3) +#define OMAP4_LPDDR2IO1_GR5_WD_SHIFT 1 +#define OMAP4_LPDDR2IO1_GR5_WD_MASK (0x3 << 1) + +/* CONTROL_LPDDR2IO1_2 */ +#define OMAP4_LPDDR2IO1_GR11_SR_SHIFT 30 +#define OMAP4_LPDDR2IO1_GR11_SR_MASK (0x3 << 30) +#define OMAP4_LPDDR2IO1_GR11_I_SHIFT 27 +#define OMAP4_LPDDR2IO1_GR11_I_MASK (0x7 << 27) +#define OMAP4_LPDDR2IO1_GR11_WD_SHIFT 25 +#define OMAP4_LPDDR2IO1_GR11_WD_MASK (0x3 << 25) +#define OMAP4_LPDDR2IO1_GR10_SR_SHIFT 22 +#define OMAP4_LPDDR2IO1_GR10_SR_MASK (0x3 << 22) +#define OMAP4_LPDDR2IO1_GR10_I_SHIFT 19 +#define OMAP4_LPDDR2IO1_GR10_I_MASK (0x7 << 19) +#define OMAP4_LPDDR2IO1_GR10_WD_SHIFT 17 +#define OMAP4_LPDDR2IO1_GR10_WD_MASK (0x3 << 17) +#define OMAP4_LPDDR2IO1_GR9_SR_SHIFT 14 +#define OMAP4_LPDDR2IO1_GR9_SR_MASK (0x3 << 14) +#define OMAP4_LPDDR2IO1_GR9_I_SHIFT 11 +#define OMAP4_LPDDR2IO1_GR9_I_MASK (0x7 << 11) +#define OMAP4_LPDDR2IO1_GR9_WD_SHIFT 9 +#define OMAP4_LPDDR2IO1_GR9_WD_MASK (0x3 << 9) + +/* CONTROL_LPDDR2IO1_3 */ +#define OMAP4_LPDDR21_VREF_CA_CCAP0_SHIFT 31 +#define OMAP4_LPDDR21_VREF_CA_CCAP0_MASK (1 << 31) +#define OMAP4_LPDDR21_VREF_CA_CCAP1_SHIFT 30 +#define OMAP4_LPDDR21_VREF_CA_CCAP1_MASK (1 << 30) +#define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_SHIFT 29 +#define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_MASK (1 << 29) +#define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_SHIFT 28 +#define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_MASK (1 << 28) +#define OMAP4_LPDDR21_VREF_CA_INT_TAP0_SHIFT 27 +#define OMAP4_LPDDR21_VREF_CA_INT_TAP0_MASK (1 << 27) +#define OMAP4_LPDDR21_VREF_CA_INT_TAP1_SHIFT 26 +#define OMAP4_LPDDR21_VREF_CA_INT_TAP1_MASK (1 << 26) +#define OMAP4_LPDDR21_VREF_CA_TAP0_SHIFT 25 +#define OMAP4_LPDDR21_VREF_CA_TAP0_MASK (1 << 25) +#define OMAP4_LPDDR21_VREF_CA_TAP1_SHIFT 24 +#define OMAP4_LPDDR21_VREF_CA_TAP1_MASK (1 << 24) +#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_SHIFT 23 +#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_MASK (1 << 23) +#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_SHIFT 22 +#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_MASK (1 << 22) +#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_SHIFT 21 +#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_MASK (1 << 21) +#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_SHIFT 20 +#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_MASK (1 << 20) +#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_SHIFT 19 +#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_MASK (1 << 19) +#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_SHIFT 18 +#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_MASK (1 << 18) +#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_SHIFT 17 +#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_MASK (1 << 17) +#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_SHIFT 16 +#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_MASK (1 << 16) +#define OMAP4_LPDDR21_VREF_DQ_CCAP0_SHIFT 15 +#define OMAP4_LPDDR21_VREF_DQ_CCAP0_MASK (1 << 15) +#define OMAP4_LPDDR21_VREF_DQ_CCAP1_SHIFT 14 +#define OMAP4_LPDDR21_VREF_DQ_CCAP1_MASK (1 << 14) +#define OMAP4_LPDDR21_VREF_DQ_TAP0_SHIFT 13 +#define OMAP4_LPDDR21_VREF_DQ_TAP0_MASK (1 << 13) +#define OMAP4_LPDDR21_VREF_DQ_TAP1_SHIFT 12 +#define OMAP4_LPDDR21_VREF_DQ_TAP1_MASK (1 << 12) + +/* CONTROL_LPDDR2IO2_0 */ +#define OMAP4_LPDDR2IO2_GR4_SR_SHIFT 30 +#define OMAP4_LPDDR2IO2_GR4_SR_MASK (0x3 << 30) +#define OMAP4_LPDDR2IO2_GR4_I_SHIFT 27 +#define OMAP4_LPDDR2IO2_GR4_I_MASK (0x7 << 27) +#define OMAP4_LPDDR2IO2_GR4_WD_SHIFT 25 +#define OMAP4_LPDDR2IO2_GR4_WD_MASK (0x3 << 25) +#define OMAP4_LPDDR2IO2_GR3_SR_SHIFT 22 +#define OMAP4_LPDDR2IO2_GR3_SR_MASK (0x3 << 22) +#define OMAP4_LPDDR2IO2_GR3_I_SHIFT 19 +#define OMAP4_LPDDR2IO2_GR3_I_MASK (0x7 << 19) +#define OMAP4_LPDDR2IO2_GR3_WD_SHIFT 17 +#define OMAP4_LPDDR2IO2_GR3_WD_MASK (0x3 << 17) +#define OMAP4_LPDDR2IO2_GR2_SR_SHIFT 14 +#define OMAP4_LPDDR2IO2_GR2_SR_MASK (0x3 << 14) +#define OMAP4_LPDDR2IO2_GR2_I_SHIFT 11 +#define OMAP4_LPDDR2IO2_GR2_I_MASK (0x7 << 11) +#define OMAP4_LPDDR2IO2_GR2_WD_SHIFT 9 +#define OMAP4_LPDDR2IO2_GR2_WD_MASK (0x3 << 9) +#define OMAP4_LPDDR2IO2_GR1_SR_SHIFT 6 +#define OMAP4_LPDDR2IO2_GR1_SR_MASK (0x3 << 6) +#define OMAP4_LPDDR2IO2_GR1_I_SHIFT 3 +#define OMAP4_LPDDR2IO2_GR1_I_MASK (0x7 << 3) +#define OMAP4_LPDDR2IO2_GR1_WD_SHIFT 1 +#define OMAP4_LPDDR2IO2_GR1_WD_MASK (0x3 << 1) + +/* CONTROL_LPDDR2IO2_1 */ +#define OMAP4_LPDDR2IO2_GR8_SR_SHIFT 30 +#define OMAP4_LPDDR2IO2_GR8_SR_MASK (0x3 << 30) +#define OMAP4_LPDDR2IO2_GR8_I_SHIFT 27 +#define OMAP4_LPDDR2IO2_GR8_I_MASK (0x7 << 27) +#define OMAP4_LPDDR2IO2_GR8_WD_SHIFT 25 +#define OMAP4_LPDDR2IO2_GR8_WD_MASK (0x3 << 25) +#define OMAP4_LPDDR2IO2_GR7_SR_SHIFT 22 +#define OMAP4_LPDDR2IO2_GR7_SR_MASK (0x3 << 22) +#define OMAP4_LPDDR2IO2_GR7_I_SHIFT 19 +#define OMAP4_LPDDR2IO2_GR7_I_MASK (0x7 << 19) +#define OMAP4_LPDDR2IO2_GR7_WD_SHIFT 17 +#define OMAP4_LPDDR2IO2_GR7_WD_MASK (0x3 << 17) +#define OMAP4_LPDDR2IO2_GR6_SR_SHIFT 14 +#define OMAP4_LPDDR2IO2_GR6_SR_MASK (0x3 << 14) +#define OMAP4_LPDDR2IO2_GR6_I_SHIFT 11 +#define OMAP4_LPDDR2IO2_GR6_I_MASK (0x7 << 11) +#define OMAP4_LPDDR2IO2_GR6_WD_SHIFT 9 +#define OMAP4_LPDDR2IO2_GR6_WD_MASK (0x3 << 9) +#define OMAP4_LPDDR2IO2_GR5_SR_SHIFT 6 +#define OMAP4_LPDDR2IO2_GR5_SR_MASK (0x3 << 6) +#define OMAP4_LPDDR2IO2_GR5_I_SHIFT 3 +#define OMAP4_LPDDR2IO2_GR5_I_MASK (0x7 << 3) +#define OMAP4_LPDDR2IO2_GR5_WD_SHIFT 1 +#define OMAP4_LPDDR2IO2_GR5_WD_MASK (0x3 << 1) + +/* CONTROL_LPDDR2IO2_2 */ +#define OMAP4_LPDDR2IO2_GR11_SR_SHIFT 30 +#define OMAP4_LPDDR2IO2_GR11_SR_MASK (0x3 << 30) +#define OMAP4_LPDDR2IO2_GR11_I_SHIFT 27 +#define OMAP4_LPDDR2IO2_GR11_I_MASK (0x7 << 27) +#define OMAP4_LPDDR2IO2_GR11_WD_SHIFT 25 +#define OMAP4_LPDDR2IO2_GR11_WD_MASK (0x3 << 25) +#define OMAP4_LPDDR2IO2_GR10_SR_SHIFT 22 +#define OMAP4_LPDDR2IO2_GR10_SR_MASK (0x3 << 22) +#define OMAP4_LPDDR2IO2_GR10_I_SHIFT 19 +#define OMAP4_LPDDR2IO2_GR10_I_MASK (0x7 << 19) +#define OMAP4_LPDDR2IO2_GR10_WD_SHIFT 17 +#define OMAP4_LPDDR2IO2_GR10_WD_MASK (0x3 << 17) +#define OMAP4_LPDDR2IO2_GR9_SR_SHIFT 14 +#define OMAP4_LPDDR2IO2_GR9_SR_MASK (0x3 << 14) +#define OMAP4_LPDDR2IO2_GR9_I_SHIFT 11 +#define OMAP4_LPDDR2IO2_GR9_I_MASK (0x7 << 11) +#define OMAP4_LPDDR2IO2_GR9_WD_SHIFT 9 +#define OMAP4_LPDDR2IO2_GR9_WD_MASK (0x3 << 9) + +/* CONTROL_LPDDR2IO2_3 */ +#define OMAP4_LPDDR22_VREF_CA_CCAP0_SHIFT 31 +#define OMAP4_LPDDR22_VREF_CA_CCAP0_MASK (1 << 31) +#define OMAP4_LPDDR22_VREF_CA_CCAP1_SHIFT 30 +#define OMAP4_LPDDR22_VREF_CA_CCAP1_MASK (1 << 30) +#define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_SHIFT 29 +#define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_MASK (1 << 29) +#define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_SHIFT 28 +#define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_MASK (1 << 28) +#define OMAP4_LPDDR22_VREF_CA_INT_TAP0_SHIFT 27 +#define OMAP4_LPDDR22_VREF_CA_INT_TAP0_MASK (1 << 27) +#define OMAP4_LPDDR22_VREF_CA_INT_TAP1_SHIFT 26 +#define OMAP4_LPDDR22_VREF_CA_INT_TAP1_MASK (1 << 26) +#define OMAP4_LPDDR22_VREF_CA_TAP0_SHIFT 25 +#define OMAP4_LPDDR22_VREF_CA_TAP0_MASK (1 << 25) +#define OMAP4_LPDDR22_VREF_CA_TAP1_SHIFT 24 +#define OMAP4_LPDDR22_VREF_CA_TAP1_MASK (1 << 24) +#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_SHIFT 23 +#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_MASK (1 << 23) +#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_SHIFT 22 +#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_MASK (1 << 22) +#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_SHIFT 21 +#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_MASK (1 << 21) +#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_SHIFT 20 +#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_MASK (1 << 20) +#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_SHIFT 19 +#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_MASK (1 << 19) +#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_SHIFT 18 +#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_MASK (1 << 18) +#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_SHIFT 17 +#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_MASK (1 << 17) +#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_SHIFT 16 +#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_MASK (1 << 16) +#define OMAP4_LPDDR22_VREF_DQ_CCAP0_SHIFT 15 +#define OMAP4_LPDDR22_VREF_DQ_CCAP0_MASK (1 << 15) +#define OMAP4_LPDDR22_VREF_DQ_CCAP1_SHIFT 14 +#define OMAP4_LPDDR22_VREF_DQ_CCAP1_MASK (1 << 14) +#define OMAP4_LPDDR22_VREF_DQ_TAP0_SHIFT 13 +#define OMAP4_LPDDR22_VREF_DQ_TAP0_MASK (1 << 13) +#define OMAP4_LPDDR22_VREF_DQ_TAP1_SHIFT 12 +#define OMAP4_LPDDR22_VREF_DQ_TAP1_MASK (1 << 12) + +/* CONTROL_BUS_HOLD */ +#define OMAP4_ABE_DMIC_DIN3_EN_SHIFT 31 +#define OMAP4_ABE_DMIC_DIN3_EN_MASK (1 << 31) +#define OMAP4_MCSPI1_CS3_EN_SHIFT 30 +#define OMAP4_MCSPI1_CS3_EN_MASK (1 << 30) + +/* CONTROL_C2C */ +#define OMAP4_MIRROR_MODE_EN_SHIFT 31 +#define OMAP4_MIRROR_MODE_EN_MASK (1 << 31) +#define OMAP4_C2C_SPARE_SHIFT 24 +#define OMAP4_C2C_SPARE_MASK (0x7f << 24) + +/* CORE_CONTROL_SPARE_RW */ +#define OMAP4_CORE_CONTROL_SPARE_RW_SHIFT 0 +#define OMAP4_CORE_CONTROL_SPARE_RW_MASK (0xffffffff << 0) + +/* CORE_CONTROL_SPARE_R */ +#define OMAP4_CORE_CONTROL_SPARE_R_SHIFT 0 +#define OMAP4_CORE_CONTROL_SPARE_R_MASK (0xffffffff << 0) + +/* CORE_CONTROL_SPARE_R_C0 */ +#define OMAP4_CORE_CONTROL_SPARE_R_C0_SHIFT 31 +#define OMAP4_CORE_CONTROL_SPARE_R_C0_MASK (1 << 31) +#define OMAP4_CORE_CONTROL_SPARE_R_C1_SHIFT 30 +#define OMAP4_CORE_CONTROL_SPARE_R_C1_MASK (1 << 30) +#define OMAP4_CORE_CONTROL_SPARE_R_C2_SHIFT 29 +#define OMAP4_CORE_CONTROL_SPARE_R_C2_MASK (1 << 29) +#define OMAP4_CORE_CONTROL_SPARE_R_C3_SHIFT 28 +#define OMAP4_CORE_CONTROL_SPARE_R_C3_MASK (1 << 28) +#define OMAP4_CORE_CONTROL_SPARE_R_C4_SHIFT 27 +#define OMAP4_CORE_CONTROL_SPARE_R_C4_MASK (1 << 27) +#define OMAP4_CORE_CONTROL_SPARE_R_C5_SHIFT 26 +#define OMAP4_CORE_CONTROL_SPARE_R_C5_MASK (1 << 26) +#define OMAP4_CORE_CONTROL_SPARE_R_C6_SHIFT 25 +#define OMAP4_CORE_CONTROL_SPARE_R_C6_MASK (1 << 25) +#define OMAP4_CORE_CONTROL_SPARE_R_C7_SHIFT 24 +#define OMAP4_CORE_CONTROL_SPARE_R_C7_MASK (1 << 24) + +/* CONTROL_EFUSE_1 */ +#define OMAP4_AVDAC_TRIM_BYTE3_SHIFT 24 +#define OMAP4_AVDAC_TRIM_BYTE3_MASK (0x7f << 24) +#define OMAP4_AVDAC_TRIM_BYTE2_SHIFT 16 +#define OMAP4_AVDAC_TRIM_BYTE2_MASK (0xff << 16) +#define OMAP4_AVDAC_TRIM_BYTE1_SHIFT 8 +#define OMAP4_AVDAC_TRIM_BYTE1_MASK (0xff << 8) +#define OMAP4_AVDAC_TRIM_BYTE0_SHIFT 0 +#define OMAP4_AVDAC_TRIM_BYTE0_MASK (0xff << 0) + +/* CONTROL_EFUSE_2 */ +#define OMAP4_EFUSE_SMART2TEST_P0_SHIFT 31 +#define OMAP4_EFUSE_SMART2TEST_P0_MASK (1 << 31) +#define OMAP4_EFUSE_SMART2TEST_P1_SHIFT 30 +#define OMAP4_EFUSE_SMART2TEST_P1_MASK (1 << 30) +#define OMAP4_EFUSE_SMART2TEST_P2_SHIFT 29 +#define OMAP4_EFUSE_SMART2TEST_P2_MASK (1 << 29) +#define OMAP4_EFUSE_SMART2TEST_P3_SHIFT 28 +#define OMAP4_EFUSE_SMART2TEST_P3_MASK (1 << 28) +#define OMAP4_EFUSE_SMART2TEST_N0_SHIFT 27 +#define OMAP4_EFUSE_SMART2TEST_N0_MASK (1 << 27) +#define OMAP4_EFUSE_SMART2TEST_N1_SHIFT 26 +#define OMAP4_EFUSE_SMART2TEST_N1_MASK (1 << 26) +#define OMAP4_EFUSE_SMART2TEST_N2_SHIFT 25 +#define OMAP4_EFUSE_SMART2TEST_N2_MASK (1 << 25) +#define OMAP4_EFUSE_SMART2TEST_N3_SHIFT 24 +#define OMAP4_EFUSE_SMART2TEST_N3_MASK (1 << 24) +#define OMAP4_LPDDR2_PTV_N1_SHIFT 23 +#define OMAP4_LPDDR2_PTV_N1_MASK (1 << 23) +#define OMAP4_LPDDR2_PTV_N2_SHIFT 22 +#define OMAP4_LPDDR2_PTV_N2_MASK (1 << 22) +#define OMAP4_LPDDR2_PTV_N3_SHIFT 21 +#define OMAP4_LPDDR2_PTV_N3_MASK (1 << 21) +#define OMAP4_LPDDR2_PTV_N4_SHIFT 20 +#define OMAP4_LPDDR2_PTV_N4_MASK (1 << 20) +#define OMAP4_LPDDR2_PTV_N5_SHIFT 19 +#define OMAP4_LPDDR2_PTV_N5_MASK (1 << 19) +#define OMAP4_LPDDR2_PTV_P1_SHIFT 18 +#define OMAP4_LPDDR2_PTV_P1_MASK (1 << 18) +#define OMAP4_LPDDR2_PTV_P2_SHIFT 17 +#define OMAP4_LPDDR2_PTV_P2_MASK (1 << 17) +#define OMAP4_LPDDR2_PTV_P3_SHIFT 16 +#define OMAP4_LPDDR2_PTV_P3_MASK (1 << 16) +#define OMAP4_LPDDR2_PTV_P4_SHIFT 15 +#define OMAP4_LPDDR2_PTV_P4_MASK (1 << 15) +#define OMAP4_LPDDR2_PTV_P5_SHIFT 14 +#define OMAP4_LPDDR2_PTV_P5_MASK (1 << 14) + +/* CONTROL_EFUSE_3 */ +#define OMAP4_STD_FUSE_SPARE_1_SHIFT 24 +#define OMAP4_STD_FUSE_SPARE_1_MASK (0xff << 24) +#define OMAP4_STD_FUSE_SPARE_2_SHIFT 16 +#define OMAP4_STD_FUSE_SPARE_2_MASK (0xff << 16) +#define OMAP4_STD_FUSE_SPARE_3_SHIFT 8 +#define OMAP4_STD_FUSE_SPARE_3_MASK (0xff << 8) +#define OMAP4_STD_FUSE_SPARE_4_SHIFT 0 +#define OMAP4_STD_FUSE_SPARE_4_MASK (0xff << 0) + +/* CONTROL_EFUSE_4 */ +#define OMAP4_STD_FUSE_SPARE_5_SHIFT 24 +#define OMAP4_STD_FUSE_SPARE_5_MASK (0xff << 24) +#define OMAP4_STD_FUSE_SPARE_6_SHIFT 16 +#define OMAP4_STD_FUSE_SPARE_6_MASK (0xff << 16) +#define OMAP4_STD_FUSE_SPARE_7_SHIFT 8 +#define OMAP4_STD_FUSE_SPARE_7_MASK (0xff << 8) +#define OMAP4_STD_FUSE_SPARE_8_SHIFT 0 +#define OMAP4_STD_FUSE_SPARE_8_MASK (0xff << 0) + +#endif diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h new file mode 100644 index 000000000000..17c9b37042c0 --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h @@ -0,0 +1,236 @@ +/* + * OMAP44xx CTRL_MODULE_PAD_WKUP registers and bitfields + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * + * Benoit Cousson (b-cousson@ti.com) + * Santosh Shilimkar (santosh.shilimkar@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H +#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H + + +/* Base address */ +#define OMAP4_CTRL_MODULE_PAD_WKUP 0x4a31e000 + +/* Registers offset */ +#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_REVISION 0x0000 +#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_HWINFO 0x0004 +#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_SYSCONFIG 0x0010 +#define OMAP4_CTRL_MODULE_PAD_WKUP_PADCONF_WAKEUPEVENT_0 0x007c +#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_0 0x05a0 +#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_1 0x05a4 +#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_PADCONF_MODE 0x05a8 +#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_XTAL_OSCILLATOR 0x05ac +#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_USIMIO 0x0600 +#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2 0x0604 +#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_JTAG 0x0608 +#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SYS 0x060c +#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_RW 0x0614 +#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R 0x0618 +#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R_C0 0x061c + +/* Registers shifts and masks */ + +/* IP_REVISION */ +#define OMAP4_IP_REV_SCHEME_SHIFT 30 +#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30) +#define OMAP4_IP_REV_FUNC_SHIFT 16 +#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16) +#define OMAP4_IP_REV_RTL_SHIFT 11 +#define OMAP4_IP_REV_RTL_MASK (0x1f << 11) +#define OMAP4_IP_REV_MAJOR_SHIFT 8 +#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8) +#define OMAP4_IP_REV_CUSTOM_SHIFT 6 +#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6) +#define OMAP4_IP_REV_MINOR_SHIFT 0 +#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0) + +/* IP_HWINFO */ +#define OMAP4_IP_HWINFO_SHIFT 0 +#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0) + +/* IP_SYSCONFIG */ +#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2 +#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2) + +/* PADCONF_WAKEUPEVENT_0 */ +#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_SHIFT 24 +#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_MASK (1 << 24) +#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_SHIFT 23 +#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_MASK (1 << 23) +#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_SHIFT 22 +#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_MASK (1 << 22) +#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_SHIFT 21 +#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_MASK (1 << 21) +#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_SHIFT 20 +#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_MASK (1 << 20) +#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_SHIFT 19 +#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_MASK (1 << 19) +#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_SHIFT 18 +#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_MASK (1 << 18) +#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_SHIFT 17 +#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_MASK (1 << 17) +#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_SHIFT 16 +#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 16) +#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_SHIFT 15 +#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 15) +#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_SHIFT 14 +#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_MASK (1 << 14) +#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_SHIFT 13 +#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_MASK (1 << 13) +#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_SHIFT 12 +#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 12) +#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_SHIFT 11 +#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 11) +#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_SHIFT 10 +#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 10) +#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_SHIFT 9 +#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 9) +#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_SHIFT 8 +#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 8) +#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_SHIFT 7 +#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_MASK (1 << 7) +#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_SHIFT 6 +#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 6) +#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_SHIFT 5 +#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 5) +#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_SHIFT 4 +#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_MASK (1 << 4) +#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_SHIFT 3 +#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_MASK (1 << 3) +#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_SHIFT 2 +#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_MASK (1 << 2) +#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_SHIFT 1 +#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 1) +#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_SHIFT 0 +#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_MASK (1 << 0) + +/* CONTROL_SMART1NOPMIO_PADCONF_0 */ +#define OMAP4_FREF_DR0_SC_SHIFT 30 +#define OMAP4_FREF_DR0_SC_MASK (0x3 << 30) +#define OMAP4_FREF_DR1_SC_SHIFT 28 +#define OMAP4_FREF_DR1_SC_MASK (0x3 << 28) +#define OMAP4_FREF_DR4_SC_SHIFT 26 +#define OMAP4_FREF_DR4_SC_MASK (0x3 << 26) +#define OMAP4_FREF_DR5_SC_SHIFT 24 +#define OMAP4_FREF_DR5_SC_MASK (0x3 << 24) +#define OMAP4_FREF_DR6_SC_SHIFT 22 +#define OMAP4_FREF_DR6_SC_MASK (0x3 << 22) +#define OMAP4_FREF_DR7_SC_SHIFT 20 +#define OMAP4_FREF_DR7_SC_MASK (0x3 << 20) +#define OMAP4_GPIO_DR7_SC_SHIFT 18 +#define OMAP4_GPIO_DR7_SC_MASK (0x3 << 18) +#define OMAP4_DPM_DR0_SC_SHIFT 14 +#define OMAP4_DPM_DR0_SC_MASK (0x3 << 14) +#define OMAP4_SIM_DR0_SC_SHIFT 12 +#define OMAP4_SIM_DR0_SC_MASK (0x3 << 12) + +/* CONTROL_SMART1NOPMIO_PADCONF_1 */ +#define OMAP4_FREF_DR0_LB_SHIFT 30 +#define OMAP4_FREF_DR0_LB_MASK (0x3 << 30) +#define OMAP4_FREF_DR1_LB_SHIFT 28 +#define OMAP4_FREF_DR1_LB_MASK (0x3 << 28) +#define OMAP4_FREF_DR4_LB_SHIFT 26 +#define OMAP4_FREF_DR4_LB_MASK (0x3 << 26) +#define OMAP4_FREF_DR5_LB_SHIFT 24 +#define OMAP4_FREF_DR5_LB_MASK (0x3 << 24) +#define OMAP4_FREF_DR6_LB_SHIFT 22 +#define OMAP4_FREF_DR6_LB_MASK (0x3 << 22) +#define OMAP4_FREF_DR7_LB_SHIFT 20 +#define OMAP4_FREF_DR7_LB_MASK (0x3 << 20) +#define OMAP4_GPIO_DR7_LB_SHIFT 18 +#define OMAP4_GPIO_DR7_LB_MASK (0x3 << 18) +#define OMAP4_DPM_DR0_LB_SHIFT 14 +#define OMAP4_DPM_DR0_LB_MASK (0x3 << 14) +#define OMAP4_SIM_DR0_LB_SHIFT 12 +#define OMAP4_SIM_DR0_LB_MASK (0x3 << 12) + +/* CONTROL_PADCONF_MODE */ +#define OMAP4_VDDS_DV_FREF_SHIFT 31 +#define OMAP4_VDDS_DV_FREF_MASK (1 << 31) +#define OMAP4_VDDS_DV_BANK2_SHIFT 30 +#define OMAP4_VDDS_DV_BANK2_MASK (1 << 30) + +/* CONTROL_XTAL_OSCILLATOR */ +#define OMAP4_OSCILLATOR_BOOST_SHIFT 31 +#define OMAP4_OSCILLATOR_BOOST_MASK (1 << 31) +#define OMAP4_OSCILLATOR_OS_OUT_SHIFT 30 +#define OMAP4_OSCILLATOR_OS_OUT_MASK (1 << 30) + +/* CONTROL_USIMIO */ +#define OMAP4_PAD_USIM_CLK_LOW_SHIFT 31 +#define OMAP4_PAD_USIM_CLK_LOW_MASK (1 << 31) +#define OMAP4_PAD_USIM_RST_LOW_SHIFT 29 +#define OMAP4_PAD_USIM_RST_LOW_MASK (1 << 29) +#define OMAP4_USIM_PWRDNZ_SHIFT 28 +#define OMAP4_USIM_PWRDNZ_MASK (1 << 28) + +/* CONTROL_I2C_2 */ +#define OMAP4_SR_SDA_GLFENB_SHIFT 31 +#define OMAP4_SR_SDA_GLFENB_MASK (1 << 31) +#define OMAP4_SR_SDA_LOAD_BITS_SHIFT 29 +#define OMAP4_SR_SDA_LOAD_BITS_MASK (0x3 << 29) +#define OMAP4_SR_SDA_PULLUPRESX_SHIFT 28 +#define OMAP4_SR_SDA_PULLUPRESX_MASK (1 << 28) +#define OMAP4_SR_SCL_GLFENB_SHIFT 27 +#define OMAP4_SR_SCL_GLFENB_MASK (1 << 27) +#define OMAP4_SR_SCL_LOAD_BITS_SHIFT 25 +#define OMAP4_SR_SCL_LOAD_BITS_MASK (0x3 << 25) +#define OMAP4_SR_SCL_PULLUPRESX_SHIFT 24 +#define OMAP4_SR_SCL_PULLUPRESX_MASK (1 << 24) + +/* CONTROL_JTAG */ +#define OMAP4_JTAG_NTRST_EN_SHIFT 31 +#define OMAP4_JTAG_NTRST_EN_MASK (1 << 31) +#define OMAP4_JTAG_TCK_EN_SHIFT 30 +#define OMAP4_JTAG_TCK_EN_MASK (1 << 30) +#define OMAP4_JTAG_RTCK_EN_SHIFT 29 +#define OMAP4_JTAG_RTCK_EN_MASK (1 << 29) +#define OMAP4_JTAG_TDI_EN_SHIFT 28 +#define OMAP4_JTAG_TDI_EN_MASK (1 << 28) +#define OMAP4_JTAG_TDO_EN_SHIFT 27 +#define OMAP4_JTAG_TDO_EN_MASK (1 << 27) + +/* CONTROL_SYS */ +#define OMAP4_SYS_NRESWARM_PIPU_SHIFT 31 +#define OMAP4_SYS_NRESWARM_PIPU_MASK (1 << 31) + +/* WKUP_CONTROL_SPARE_RW */ +#define OMAP4_WKUP_CONTROL_SPARE_RW_SHIFT 0 +#define OMAP4_WKUP_CONTROL_SPARE_RW_MASK (0xffffffff << 0) + +/* WKUP_CONTROL_SPARE_R */ +#define OMAP4_WKUP_CONTROL_SPARE_R_SHIFT 0 +#define OMAP4_WKUP_CONTROL_SPARE_R_MASK (0xffffffff << 0) + +/* WKUP_CONTROL_SPARE_R_C0 */ +#define OMAP4_WKUP_CONTROL_SPARE_R_C0_SHIFT 31 +#define OMAP4_WKUP_CONTROL_SPARE_R_C0_MASK (1 << 31) +#define OMAP4_WKUP_CONTROL_SPARE_R_C1_SHIFT 30 +#define OMAP4_WKUP_CONTROL_SPARE_R_C1_MASK (1 << 30) +#define OMAP4_WKUP_CONTROL_SPARE_R_C2_SHIFT 29 +#define OMAP4_WKUP_CONTROL_SPARE_R_C2_MASK (1 << 29) +#define OMAP4_WKUP_CONTROL_SPARE_R_C3_SHIFT 28 +#define OMAP4_WKUP_CONTROL_SPARE_R_C3_MASK (1 << 28) +#define OMAP4_WKUP_CONTROL_SPARE_R_C4_SHIFT 27 +#define OMAP4_WKUP_CONTROL_SPARE_R_C4_MASK (1 << 27) +#define OMAP4_WKUP_CONTROL_SPARE_R_C5_SHIFT 26 +#define OMAP4_WKUP_CONTROL_SPARE_R_C5_MASK (1 << 26) +#define OMAP4_WKUP_CONTROL_SPARE_R_C6_SHIFT 25 +#define OMAP4_WKUP_CONTROL_SPARE_R_C6_MASK (1 << 25) +#define OMAP4_WKUP_CONTROL_SPARE_R_C7_SHIFT 24 +#define OMAP4_WKUP_CONTROL_SPARE_R_C7_MASK (1 << 24) + +#endif diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h new file mode 100644 index 000000000000..a0af9baec3f7 --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h @@ -0,0 +1,92 @@ +/* + * OMAP44xx CTRL_MODULE_WKUP registers and bitfields + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * + * Benoit Cousson (b-cousson@ti.com) + * Santosh Shilimkar (santosh.shilimkar@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_WKUP_44XX_H +#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_WKUP_44XX_H + + +/* Base address */ +#define OMAP4_CTRL_MODULE_WKUP 0x4a30c000 + +/* Registers offset */ +#define OMAP4_CTRL_MODULE_WKUP_IP_REVISION 0x0000 +#define OMAP4_CTRL_MODULE_WKUP_IP_HWINFO 0x0004 +#define OMAP4_CTRL_MODULE_WKUP_IP_SYSCONFIG 0x0010 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_0 0x0460 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_1 0x0464 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_2 0x0468 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_3 0x046c +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_4 0x0470 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_5 0x0474 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_6 0x0478 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_7 0x047c +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_8 0x0480 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_9 0x0484 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_10 0x0488 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_11 0x048c +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_12 0x0490 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_13 0x0494 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_14 0x0498 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_15 0x049c +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_16 0x04a0 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_17 0x04a4 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_18 0x04a8 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_19 0x04ac +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_20 0x04b0 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_21 0x04b4 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_22 0x04b8 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_23 0x04bc +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_24 0x04c0 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_25 0x04c4 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_26 0x04c8 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_27 0x04cc +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_28 0x04d0 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_29 0x04d4 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_30 0x04d8 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_31 0x04dc + +/* Registers shifts and masks */ + +/* IP_REVISION */ +#define OMAP4_IP_REV_SCHEME_SHIFT 30 +#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30) +#define OMAP4_IP_REV_FUNC_SHIFT 16 +#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16) +#define OMAP4_IP_REV_RTL_SHIFT 11 +#define OMAP4_IP_REV_RTL_MASK (0x1f << 11) +#define OMAP4_IP_REV_MAJOR_SHIFT 8 +#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8) +#define OMAP4_IP_REV_CUSTOM_SHIFT 6 +#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6) +#define OMAP4_IP_REV_MINOR_SHIFT 0 +#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0) + +/* IP_HWINFO */ +#define OMAP4_IP_HWINFO_SHIFT 0 +#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0) + +/* IP_SYSCONFIG */ +#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2 +#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2) + +/* CONF_DEBUG_SEL_TST_0 */ +#define OMAP4_WKUP_MODE_SHIFT 0 +#define OMAP4_WKUP_MODE_MASK (1 << 0) + +#endif diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index b9ea70bce563..40562ddd3ee4 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -36,6 +36,7 @@ #include "clock2xxx.h" #include "clock3xxx.h" #include "clock44xx.h" +#include "io.h" #include <plat/omap-pm.h> #include <plat/powerdomain.h> @@ -323,6 +324,9 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, omap2430_hwmod_init(); else if (cpu_is_omap34xx()) omap3xxx_hwmod_init(); + else if (cpu_is_omap44xx()) + omap44xx_hwmod_init(); + /* The OPP tables have to be registered before a clk init */ omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps); @@ -342,9 +346,7 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, #ifndef CONFIG_PM_RUNTIME skip_setup_idle = 1; #endif - if (cpu_is_omap24xx() || cpu_is_omap34xx()) /* FIXME: OMAP4 */ - omap_hwmod_late_init(skip_setup_idle); - + omap_hwmod_late_init(skip_setup_idle); if (cpu_is_omap24xx() || cpu_is_omap34xx()) { omap2_sdrc_init(sdrc_cs0, sdrc_cs1); _omap2_init_reprogram_sdrc(); diff --git a/arch/arm/mach-omap2/io.h b/arch/arm/mach-omap2/io.h new file mode 100644 index 000000000000..fd230c6cded5 --- /dev/null +++ b/arch/arm/mach-omap2/io.h @@ -0,0 +1,7 @@ + +#ifndef __MACH_OMAP2_IO_H__ +#define __MACH_OMAP2_IO_H__ + +extern int __init omap_sram_init(void); + +#endif /* __MACH_OMAP2_IO_H__ */ diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index 26aeef560aa3..32eeabe9d2ab 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c @@ -47,7 +47,6 @@ static struct omap_irq_bank { } __attribute__ ((aligned(4))) irq_banks[] = { { /* MPU INTC */ - .base_reg = 0, .nr_irqs = 96, }, }; diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c index 42dbfa46e656..40ddecab93a9 100644 --- a/arch/arm/mach-omap2/mailbox.c +++ b/arch/arm/mach-omap2/mailbox.c @@ -181,7 +181,7 @@ static int omap2_mbox_fifo_full(struct omap_mbox *mbox) static void omap2_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_type_t irq) { - struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv; + struct omap_mbox2_priv *p = mbox->priv; u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit; l = mbox_read_reg(p->irqenable); @@ -192,7 +192,7 @@ static void omap2_mbox_enable_irq(struct omap_mbox *mbox, static void omap2_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_type_t irq) { - struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv; + struct omap_mbox2_priv *p = mbox->priv; u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit; l = mbox_read_reg(p->irqdisable); l &= ~bit; @@ -202,7 +202,7 @@ static void omap2_mbox_disable_irq(struct omap_mbox *mbox, static void omap2_mbox_ack_irq(struct omap_mbox *mbox, omap_mbox_type_t irq) { - struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv; + struct omap_mbox2_priv *p = mbox->priv; u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit; mbox_write_reg(bit, p->irqstatus); @@ -214,7 +214,7 @@ static void omap2_mbox_ack_irq(struct omap_mbox *mbox, static int omap2_mbox_is_irq(struct omap_mbox *mbox, omap_mbox_type_t irq) { - struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv; + struct omap_mbox2_priv *p = mbox->priv; u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit; u32 enable = mbox_read_reg(p->irqenable); u32 status = mbox_read_reg(p->irqstatus); diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index 467aae245781..f9c9df5b5ff1 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -23,29 +23,86 @@ #include <plat/cpu.h> #include <plat/mcbsp.h> -#include "mux.h" +#include "control.h" -static void omap2_mcbsp2_mux_setup(void) + +/* McBSP internal signal muxing functions */ + +void omap2_mcbsp1_mux_clkr_src(u8 mux) { - omap_mux_init_signal("eac_ac_sclk.mcbsp2_clkx", OMAP_PULL_ENA); - omap_mux_init_signal("eac_ac_fs.mcbsp2_fsx", OMAP_PULL_ENA); - omap_mux_init_signal("eac_ac_din.mcbsp2_dr", OMAP_PULL_ENA); - omap_mux_init_signal("eac_ac_dout.mcbsp2_dx", OMAP_PULL_ENA); - omap_mux_init_gpio(117, OMAP_PULL_ENA); - /* - * TODO: Need to add MUX settings for OMAP 2430 SDP - */ + u32 v; + + v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); + if (mux == CLKR_SRC_CLKR) + v &= ~OMAP2_MCBSP1_CLKR_MASK; + else if (mux == CLKR_SRC_CLKX) + v |= OMAP2_MCBSP1_CLKR_MASK; + omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); } +EXPORT_SYMBOL(omap2_mcbsp1_mux_clkr_src); -static void omap2_mcbsp_request(unsigned int id) +void omap2_mcbsp1_mux_fsr_src(u8 mux) { - if (cpu_is_omap2420() && (id == OMAP_MCBSP2)) - omap2_mcbsp2_mux_setup(); + u32 v; + + v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); + if (mux == FSR_SRC_FSR) + v &= ~OMAP2_MCBSP1_FSR_MASK; + else if (mux == FSR_SRC_FSX) + v |= OMAP2_MCBSP1_FSR_MASK; + omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); } +EXPORT_SYMBOL(omap2_mcbsp1_mux_fsr_src); -static struct omap_mcbsp_ops omap2_mcbsp_ops = { - .request = omap2_mcbsp_request, -}; +/* McBSP CLKS source switching function */ + +int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id) +{ + struct omap_mcbsp *mcbsp; + struct clk *fck_src; + char *fck_src_name; + int r; + + if (!omap_mcbsp_check_valid_id(id)) { + pr_err("%s: Invalid id (%d)\n", __func__, id + 1); + return -EINVAL; + } + mcbsp = id_to_mcbsp_ptr(id); + + if (fck_src_id == MCBSP_CLKS_PAD_SRC) + fck_src_name = "pad_fck"; + else if (fck_src_id == MCBSP_CLKS_PRCM_SRC) + fck_src_name = "prcm_fck"; + else + return -EINVAL; + + fck_src = clk_get(mcbsp->dev, fck_src_name); + if (IS_ERR_OR_NULL(fck_src)) { + pr_err("omap-mcbsp: %s: could not clk_get() %s\n", "clks", + fck_src_name); + return -EINVAL; + } + + clk_disable(mcbsp->fclk); + + r = clk_set_parent(mcbsp->fclk, fck_src); + if (IS_ERR_VALUE(r)) { + pr_err("omap-mcbsp: %s: could not clk_set_parent() to %s\n", + "clks", fck_src_name); + clk_put(fck_src); + return -EINVAL; + } + + clk_enable(mcbsp->fclk); + + clk_put(fck_src); + + return 0; +} +EXPORT_SYMBOL(omap2_mcbsp_set_clks_src); + + +/* Platform data */ #ifdef CONFIG_ARCH_OMAP2420 static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { @@ -55,7 +112,6 @@ static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, .rx_irq = INT_24XX_MCBSP1_IRQ_RX, .tx_irq = INT_24XX_MCBSP1_IRQ_TX, - .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP24XX_MCBSP2_BASE, @@ -63,7 +119,6 @@ static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, .rx_irq = INT_24XX_MCBSP2_IRQ_RX, .tx_irq = INT_24XX_MCBSP2_IRQ_TX, - .ops = &omap2_mcbsp_ops, }, }; #define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata) @@ -82,7 +137,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, .rx_irq = INT_24XX_MCBSP1_IRQ_RX, .tx_irq = INT_24XX_MCBSP1_IRQ_TX, - .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP24XX_MCBSP2_BASE, @@ -90,7 +144,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, .rx_irq = INT_24XX_MCBSP2_IRQ_RX, .tx_irq = INT_24XX_MCBSP2_IRQ_TX, - .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP2430_MCBSP3_BASE, @@ -98,7 +151,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX, .rx_irq = INT_24XX_MCBSP3_IRQ_RX, .tx_irq = INT_24XX_MCBSP3_IRQ_TX, - .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP2430_MCBSP4_BASE, @@ -106,7 +158,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX, .rx_irq = INT_24XX_MCBSP4_IRQ_RX, .tx_irq = INT_24XX_MCBSP4_IRQ_TX, - .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP2430_MCBSP5_BASE, @@ -114,7 +165,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX, .rx_irq = INT_24XX_MCBSP5_IRQ_RX, .tx_irq = INT_24XX_MCBSP5_IRQ_TX, - .ops = &omap2_mcbsp_ops, }, }; #define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata) @@ -133,7 +183,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, .rx_irq = INT_24XX_MCBSP1_IRQ_RX, .tx_irq = INT_24XX_MCBSP1_IRQ_TX, - .ops = &omap2_mcbsp_ops, .buffer_size = 0x80, /* The FIFO has 128 locations */ }, { @@ -143,7 +192,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, .rx_irq = INT_24XX_MCBSP2_IRQ_RX, .tx_irq = INT_24XX_MCBSP2_IRQ_TX, - .ops = &omap2_mcbsp_ops, .buffer_size = 0x500, /* The FIFO has 1024 + 256 locations */ }, { @@ -153,7 +201,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX, .rx_irq = INT_24XX_MCBSP3_IRQ_RX, .tx_irq = INT_24XX_MCBSP3_IRQ_TX, - .ops = &omap2_mcbsp_ops, .buffer_size = 0x80, /* The FIFO has 128 locations */ }, { @@ -162,7 +209,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX, .rx_irq = INT_24XX_MCBSP4_IRQ_RX, .tx_irq = INT_24XX_MCBSP4_IRQ_TX, - .ops = &omap2_mcbsp_ops, .buffer_size = 0x80, /* The FIFO has 128 locations */ }, { @@ -171,7 +217,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX, .rx_irq = INT_24XX_MCBSP5_IRQ_RX, .tx_irq = INT_24XX_MCBSP5_IRQ_TX, - .ops = &omap2_mcbsp_ops, .buffer_size = 0x80, /* The FIFO has 128 locations */ }, }; @@ -189,28 +234,24 @@ static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = { .dma_rx_sync = OMAP44XX_DMA_MCBSP1_RX, .dma_tx_sync = OMAP44XX_DMA_MCBSP1_TX, .tx_irq = OMAP44XX_IRQ_MCBSP1, - .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP44XX_MCBSP2_BASE, .dma_rx_sync = OMAP44XX_DMA_MCBSP2_RX, .dma_tx_sync = OMAP44XX_DMA_MCBSP2_TX, .tx_irq = OMAP44XX_IRQ_MCBSP2, - .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP44XX_MCBSP3_BASE, .dma_rx_sync = OMAP44XX_DMA_MCBSP3_RX, .dma_tx_sync = OMAP44XX_DMA_MCBSP3_TX, .tx_irq = OMAP44XX_IRQ_MCBSP3, - .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP44XX_MCBSP4_BASE, .dma_rx_sync = OMAP44XX_DMA_MCBSP4_RX, .dma_tx_sync = OMAP44XX_DMA_MCBSP4_TX, .tx_irq = OMAP44XX_IRQ_MCBSP4, - .ops = &omap2_mcbsp_ops, }, }; #define OMAP44XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap44xx_mcbsp_pdata) diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index ab403b2ed26b..074536ae401f 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c @@ -23,12 +23,11 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA * */ -#include <linux/module.h> +#include <linux/kernel.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/slab.h> -#include <linux/spinlock.h> #include <linux/list.h> +#include <linux/slab.h> #include <linux/ctype.h> #include <linux/debugfs.h> #include <linux/seq_file.h> @@ -36,8 +35,7 @@ #include <asm/system.h> -#include <plat/control.h> - +#include "control.h" #include "mux.h" #define OMAP_MUX_BASE_OFFSET 0x30 /* Offset from CTRL_BASE */ @@ -87,7 +85,7 @@ static char *omap_mux_options; int __init omap_mux_init_gpio(int gpio, int val) { struct omap_mux_entry *e; - struct omap_mux *gpio_mux; + struct omap_mux *gpio_mux = NULL; u16 old_mode; u16 mux_mode; int found = 0; @@ -127,17 +125,16 @@ int __init omap_mux_init_gpio(int gpio, int val) return 0; } -int __init omap_mux_init_signal(char *muxname, int val) +int __init omap_mux_init_signal(const char *muxname, int val) { struct omap_mux_entry *e; - char *m0_name = NULL, *mode_name = NULL; - int found = 0; + const char *mode_name; + int found = 0, mode0_len = 0; mode_name = strchr(muxname, '.'); if (mode_name) { - *mode_name = '\0'; + mode0_len = strlen(muxname) - strlen(mode_name); mode_name++; - m0_name = muxname; } else { mode_name = muxname; } @@ -147,9 +144,11 @@ int __init omap_mux_init_signal(char *muxname, int val) char *m0_entry = m->muxnames[0]; int i; - if (m0_name && strcmp(m0_name, m0_entry)) + /* First check for full name in mode0.muxmode format */ + if (mode0_len && strncmp(muxname, m0_entry, mode0_len)) continue; + /* Then check for muxmode only */ for (i = 0; i < OMAP_MUX_NR_MODES; i++) { char *mode_cur = m->muxnames[i]; diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h index a8e040c2c7e9..350c04f27383 100644 --- a/arch/arm/mach-omap2/mux.h +++ b/arch/arm/mach-omap2/mux.h @@ -120,7 +120,7 @@ int omap_mux_init_gpio(int gpio, int val); * @muxname: Mux name in mode0_name.signal_name format * @val: Options for the mux register value */ -int omap_mux_init_signal(char *muxname, int val); +int omap_mux_init_signal(const char *muxname, int val); #else diff --git a/arch/arm/mach-omap2/mux2420.c b/arch/arm/mach-omap2/mux2420.c index fdb04a7eb8aa..414af5434456 100644 --- a/arch/arm/mach-omap2/mux2420.c +++ b/arch/arm/mach-omap2/mux2420.c @@ -507,7 +507,7 @@ static struct omap_mux __initdata omap2420_muxmodes[] = { * Balls for 447-pin POP package */ #ifdef CONFIG_DEBUG_FS -struct omap_ball __initdata omap2420_pop_ball[] = { +static struct omap_ball __initdata omap2420_pop_ball[] = { _OMAP2420_BALLENTRY(CAM_D0, "y4", NULL), _OMAP2420_BALLENTRY(CAM_D1, "y3", NULL), _OMAP2420_BALLENTRY(CAM_D2, "u7", NULL), diff --git a/arch/arm/mach-omap2/mux2430.c b/arch/arm/mach-omap2/mux2430.c index 7dcaaa8af32a..84d2c5a7ecd7 100644 --- a/arch/arm/mach-omap2/mux2430.c +++ b/arch/arm/mach-omap2/mux2430.c @@ -586,7 +586,7 @@ static struct omap_mux __initdata omap2430_muxmodes[] = { * 447-pin s-PBGA Package, 0.00mm Ball Pitch (Bottom) */ #ifdef CONFIG_DEBUG_FS -struct omap_ball __initdata omap2430_pop_ball[] = { +static struct omap_ball __initdata omap2430_pop_ball[] = { _OMAP2430_BALLENTRY(CAM_D0, "t8", NULL), _OMAP2430_BALLENTRY(CAM_D1, "t4", NULL), _OMAP2430_BALLENTRY(CAM_D10, "r4", NULL), diff --git a/arch/arm/mach-omap2/mux34xx.c b/arch/arm/mach-omap2/mux34xx.c index f64d7eea3451..574e54ea3ab7 100644 --- a/arch/arm/mach-omap2/mux34xx.c +++ b/arch/arm/mach-omap2/mux34xx.c @@ -931,7 +931,7 @@ struct omap_ball __initdata omap3_cbc_ball[] = { * Signals different on CUS package compared to superset */ #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CUS) -struct omap_mux __initdata omap3_cus_subset[] = { +static struct omap_mux __initdata omap3_cus_subset[] = { _OMAP3_MUXENTRY(CAM_D10, 109, "cam_d10", NULL, NULL, NULL, "gpio_109", NULL, NULL, "safe_mode"), @@ -1077,7 +1077,7 @@ struct omap_mux __initdata omap3_cus_subset[] = { */ #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \ && defined(CONFIG_OMAP_PACKAGE_CUS) -struct omap_ball __initdata omap3_cus_ball[] = { +static struct omap_ball __initdata omap3_cus_ball[] = { _OMAP3_BALLENTRY(CAM_D0, "ab18", NULL), _OMAP3_BALLENTRY(CAM_D1, "ac18", NULL), _OMAP3_BALLENTRY(CAM_D10, "f21", NULL), @@ -1269,7 +1269,7 @@ struct omap_ball __initdata omap3_cus_ball[] = { * Signals different on CBB package comapared to superset */ #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBB) -struct omap_mux __initdata omap3_cbb_subset[] = { +static struct omap_mux __initdata omap3_cbb_subset[] = { _OMAP3_MUXENTRY(CAM_D10, 109, "cam_d10", NULL, NULL, NULL, "gpio_109", NULL, NULL, "safe_mode"), @@ -1390,7 +1390,7 @@ struct omap_mux __initdata omap3_cbb_subset[] = { */ #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \ && defined(CONFIG_OMAP_PACKAGE_CBB) -struct omap_ball __initdata omap3_cbb_ball[] = { +static struct omap_ball __initdata omap3_cbb_ball[] = { _OMAP3_BALLENTRY(CAM_D0, "ag17", NULL), _OMAP3_BALLENTRY(CAM_D1, "ah17", NULL), _OMAP3_BALLENTRY(CAM_D10, "b25", NULL), @@ -1600,7 +1600,7 @@ struct omap_ball __initdata omap3_cbb_ball[] = { * Signals different on 36XX CBP package comapared to 34XX CBC package */ #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBP) -struct omap_mux __initdata omap36xx_cbp_subset[] = { +static struct omap_mux __initdata omap36xx_cbp_subset[] = { _OMAP3_MUXENTRY(CAM_D0, 99, "cam_d0", NULL, "csi2_dx2", NULL, "gpio_99", NULL, NULL, "safe_mode"), @@ -1818,7 +1818,7 @@ struct omap_mux __initdata omap36xx_cbp_subset[] = { */ #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \ && defined (CONFIG_OMAP_PACKAGE_CBP) -struct omap_ball __initdata omap36xx_cbp_ball[] = { +static struct omap_ball __initdata omap36xx_cbp_ball[] = { _OMAP3_BALLENTRY(CAM_D0, "ag17", NULL), _OMAP3_BALLENTRY(CAM_D1, "ah17", NULL), _OMAP3_BALLENTRY(CAM_D10, "b25", NULL), diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index 13dc9794dcc2..923f9f5f91ce 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -61,10 +61,14 @@ static int __init omap_l2_cache_init(void) omap_smc1(0x102, 0x1); /* - * 32KB way size, 16-way associativity, - * parity disabled + * 16-way associativity, parity disabled + * Way size - 32KB (es1.0) + * Way size - 64KB (es2.0 +) */ - l2x0_init(l2cache_base, 0x0e050000, 0xc0000fff); + if (omap_rev() == OMAP4430_REV_ES1_0) + l2x0_init(l2cache_base, 0x0e050000, 0xc0000fff); + else + l2x0_init(l2cache_base, 0x0e070000, 0xc0000fff); return 0; } diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index cb911d7d1a3c..5a30658444d0 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -13,10 +13,102 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * - * This code manages "OMAP modules" (on-chip devices) and their - * integration with Linux device driver and bus code. - * - * References: + * Introduction + * ------------ + * One way to view an OMAP SoC is as a collection of largely unrelated + * IP blocks connected by interconnects. The IP blocks include + * devices such as ARM processors, audio serial interfaces, UARTs, + * etc. Some of these devices, like the DSP, are created by TI; + * others, like the SGX, largely originate from external vendors. In + * TI's documentation, on-chip devices are referred to as "OMAP + * modules." Some of these IP blocks are identical across several + * OMAP versions. Others are revised frequently. + * + * These OMAP modules are tied together by various interconnects. + * Most of the address and data flow between modules is via OCP-based + * interconnects such as the L3 and L4 buses; but there are other + * interconnects that distribute the hardware clock tree, handle idle + * and reset signaling, supply power, and connect the modules to + * various pads or balls on the OMAP package. + * + * OMAP hwmod provides a consistent way to describe the on-chip + * hardware blocks and their integration into the rest of the chip. + * This description can be automatically generated from the TI + * hardware database. OMAP hwmod provides a standard, consistent API + * to reset, enable, idle, and disable these hardware blocks. And + * hwmod provides a way for other core code, such as the Linux device + * code or the OMAP power management and address space mapping code, + * to query the hardware database. + * + * Using hwmod + * ----------- + * Drivers won't call hwmod functions directly. That is done by the + * omap_device code, and in rare occasions, by custom integration code + * in arch/arm/ *omap*. The omap_device code includes functions to + * build a struct platform_device using omap_hwmod data, and that is + * currently how hwmod data is communicated to drivers and to the + * Linux driver model. Most drivers will call omap_hwmod functions only + * indirectly, via pm_runtime*() functions. + * + * From a layering perspective, here is where the OMAP hwmod code + * fits into the kernel software stack: + * + * +-------------------------------+ + * | Device driver code | + * | (e.g., drivers/) | + * +-------------------------------+ + * | Linux driver model | + * | (platform_device / | + * | platform_driver data/code) | + * +-------------------------------+ + * | OMAP core-driver integration | + * |(arch/arm/mach-omap2/devices.c)| + * +-------------------------------+ + * | omap_device code | + * | (../plat-omap/omap_device.c) | + * +-------------------------------+ + * ----> | omap_hwmod code/data | <----- + * | (../mach-omap2/omap_hwmod*) | + * +-------------------------------+ + * | OMAP clock/PRCM/register fns | + * | (__raw_{read,write}l, clk*) | + * +-------------------------------+ + * + * Device drivers should not contain any OMAP-specific code or data in + * them. They should only contain code to operate the IP block that + * the driver is responsible for. This is because these IP blocks can + * also appear in other SoCs, either from TI (such as DaVinci) or from + * other manufacturers; and drivers should be reusable across other + * platforms. + * + * The OMAP hwmod code also will attempt to reset and idle all on-chip + * devices upon boot. The goal here is for the kernel to be + * completely self-reliant and independent from bootloaders. This is + * to ensure a repeatable configuration, both to ensure consistent + * runtime behavior, and to make it easier for others to reproduce + * bugs. + * + * OMAP module activity states + * --------------------------- + * The hwmod code considers modules to be in one of several activity + * states. IP blocks start out in an UNKNOWN state, then once they + * are registered via the hwmod code, proceed to the REGISTERED state. + * Once their clock names are resolved to clock pointers, the module + * enters the CLKS_INITED state; and finally, once the module has been + * reset and the integration registers programmed, the INITIALIZED state + * is entered. The hwmod code will then place the module into either + * the IDLE state to save power, or in the case of a critical system + * module, the ENABLED state. + * + * OMAP core integration code can then call omap_hwmod*() functions + * directly to move the module between the IDLE, ENABLED, and DISABLED + * states, as needed. This is done during both the PM idle loop, and + * in the OMAP core integration code's implementation of the PM runtime + * functions. + * + * References + * ---------- + * This is a partial list. * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064) * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090) * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108) @@ -50,11 +142,13 @@ #include <plat/powerdomain.h> #include <plat/clock.h> #include <plat/omap_hwmod.h> +#include <plat/prcm.h> #include "cm.h" +#include "prm.h" -/* Maximum microseconds to wait for OMAP module to reset */ -#define MAX_MODULE_RESET_WAIT 10000 +/* Maximum microseconds to wait for OMAP module to softreset */ +#define MAX_MODULE_SOFTRESET_WAIT 10000 /* Name of the OMAP hwmod for the MPU */ #define MPU_INITIATOR_NAME "mpu" @@ -90,7 +184,7 @@ static int _update_sysc_cache(struct omap_hwmod *oh) /* XXX ensure module interface clock is up */ - oh->_sysc_cache = omap_hwmod_readl(oh, oh->class->sysc->sysc_offs); + oh->_sysc_cache = omap_hwmod_read(oh, oh->class->sysc->sysc_offs); if (!(oh->class->sysc->sysc_flags & SYSC_NO_CACHE)) oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED; @@ -117,7 +211,7 @@ static void _write_sysconfig(u32 v, struct omap_hwmod *oh) if (oh->_sysc_cache != v) { oh->_sysc_cache = v; - omap_hwmod_writel(v, oh, oh->class->sysc->sysc_offs); + omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs); } } @@ -544,6 +638,36 @@ static int _disable_clocks(struct omap_hwmod *oh) return 0; } +static void _enable_optional_clocks(struct omap_hwmod *oh) +{ + struct omap_hwmod_opt_clk *oc; + int i; + + pr_debug("omap_hwmod: %s: enabling optional clocks\n", oh->name); + + for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) + if (oc->_clk) { + pr_debug("omap_hwmod: enable %s:%s\n", oc->role, + oc->_clk->name); + clk_enable(oc->_clk); + } +} + +static void _disable_optional_clocks(struct omap_hwmod *oh) +{ + struct omap_hwmod_opt_clk *oc; + int i; + + pr_debug("omap_hwmod: %s: disabling optional clocks\n", oh->name); + + for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) + if (oc->_clk) { + pr_debug("omap_hwmod: disable %s:%s\n", oc->role, + oc->_clk->name); + clk_disable(oc->_clk); + } +} + /** * _find_mpu_port_index - find hwmod OCP slave port ID intended for MPU use * @oh: struct omap_hwmod * @@ -622,7 +746,7 @@ static void __iomem *_find_mpu_rt_base(struct omap_hwmod *oh, u8 index) } /** - * _sysc_enable - try to bring a module out of idle via OCP_SYSCONFIG + * _enable_sysc - try to bring a module out of idle via OCP_SYSCONFIG * @oh: struct omap_hwmod * * * If module is marked as SWSUP_SIDLE, force the module out of slave @@ -630,7 +754,7 @@ static void __iomem *_find_mpu_rt_base(struct omap_hwmod *oh, u8 index) * as SWSUP_MSUSPEND, force the module out of master standby; * otherwise, configure it for smart-standby. No return value. */ -static void _sysc_enable(struct omap_hwmod *oh) +static void _enable_sysc(struct omap_hwmod *oh) { u8 idlemode, sf; u32 v; @@ -653,14 +777,6 @@ static void _sysc_enable(struct omap_hwmod *oh) _set_master_standbymode(oh, idlemode, &v); } - if (sf & SYSC_HAS_AUTOIDLE) { - idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ? - 0 : 1; - _set_module_autoidle(oh, idlemode, &v); - } - - /* XXX OCP ENAWAKEUP bit? */ - /* * XXX The clock framework should handle this, by * calling into this code. But this must wait until the @@ -671,10 +787,25 @@ static void _sysc_enable(struct omap_hwmod *oh) _set_clockactivity(oh, oh->class->sysc->clockact, &v); _write_sysconfig(v, oh); + + /* If slave is in SMARTIDLE, also enable wakeup */ + if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE)) + _enable_wakeup(oh); + + /* + * Set the autoidle bit only after setting the smartidle bit + * Setting this will not have any impact on the other modules. + */ + if (sf & SYSC_HAS_AUTOIDLE) { + idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ? + 0 : 1; + _set_module_autoidle(oh, idlemode, &v); + _write_sysconfig(v, oh); + } } /** - * _sysc_idle - try to put a module into idle via OCP_SYSCONFIG + * _idle_sysc - try to put a module into idle via OCP_SYSCONFIG * @oh: struct omap_hwmod * * * If module is marked as SWSUP_SIDLE, force the module into slave @@ -682,7 +813,7 @@ static void _sysc_enable(struct omap_hwmod *oh) * as SWSUP_MSUSPEND, force the module into master standby; otherwise, * configure it for smart-standby. No return value. */ -static void _sysc_idle(struct omap_hwmod *oh) +static void _idle_sysc(struct omap_hwmod *oh) { u8 idlemode, sf; u32 v; @@ -709,13 +840,13 @@ static void _sysc_idle(struct omap_hwmod *oh) } /** - * _sysc_shutdown - force a module into idle via OCP_SYSCONFIG + * _shutdown_sysc - force a module into idle via OCP_SYSCONFIG * @oh: struct omap_hwmod * * * Force the module into slave idle and master suspend. No return * value. */ -static void _sysc_shutdown(struct omap_hwmod *oh) +static void _shutdown_sysc(struct omap_hwmod *oh) { u32 v; u8 sf; @@ -767,10 +898,10 @@ static struct omap_hwmod *_lookup(const char *name) * @data: not used; pass NULL * * Called by omap_hwmod_late_init() (after omap2_clk_init()). - * Resolves all clock names embedded in the hwmod. Must be called - * with omap_hwmod_mutex held. Returns -EINVAL if the omap_hwmod - * has not yet been registered or if the clocks have already been - * initialized, 0 on success, or a non-zero error on failure. + * Resolves all clock names embedded in the hwmod. Returns -EINVAL if + * the omap_hwmod has not yet been registered or if the clocks have + * already been initialized, 0 on success, or a non-zero error on + * failure. */ static int _init_clocks(struct omap_hwmod *oh, void *data) { @@ -834,56 +965,202 @@ static int _wait_target_ready(struct omap_hwmod *oh) } /** + * _lookup_hardreset - return the register bit shift for this hwmod/reset line + * @oh: struct omap_hwmod * + * @name: name of the reset line in the context of this hwmod + * + * Return the bit position of the reset line that match the + * input name. Return -ENOENT if not found. + */ +static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name) +{ + int i; + + for (i = 0; i < oh->rst_lines_cnt; i++) { + const char *rst_line = oh->rst_lines[i].name; + if (!strcmp(rst_line, name)) { + u8 shift = oh->rst_lines[i].rst_shift; + pr_debug("omap_hwmod: %s: _lookup_hardreset: %s: %d\n", + oh->name, rst_line, shift); + + return shift; + } + } + + return -ENOENT; +} + +/** + * _assert_hardreset - assert the HW reset line of submodules + * contained in the hwmod module. + * @oh: struct omap_hwmod * + * @name: name of the reset line to lookup and assert + * + * Some IP like dsp, ipu or iva contain processor that require + * an HW reset line to be assert / deassert in order to enable fully + * the IP. + */ +static int _assert_hardreset(struct omap_hwmod *oh, const char *name) +{ + u8 shift; + + if (!oh) + return -EINVAL; + + shift = _lookup_hardreset(oh, name); + if (IS_ERR_VALUE(shift)) + return shift; + + if (cpu_is_omap24xx() || cpu_is_omap34xx()) + return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs, + shift); + else if (cpu_is_omap44xx()) + return omap4_prm_assert_hardreset(oh->prcm.omap4.rstctrl_reg, + shift); + else + return -EINVAL; +} + +/** + * _deassert_hardreset - deassert the HW reset line of submodules contained + * in the hwmod module. + * @oh: struct omap_hwmod * + * @name: name of the reset line to look up and deassert + * + * Some IP like dsp, ipu or iva contain processor that require + * an HW reset line to be assert / deassert in order to enable fully + * the IP. + */ +static int _deassert_hardreset(struct omap_hwmod *oh, const char *name) +{ + u8 shift; + int r; + + if (!oh) + return -EINVAL; + + shift = _lookup_hardreset(oh, name); + if (IS_ERR_VALUE(shift)) + return shift; + + if (cpu_is_omap24xx() || cpu_is_omap34xx()) + r = omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs, + shift); + else if (cpu_is_omap44xx()) + r = omap4_prm_deassert_hardreset(oh->prcm.omap4.rstctrl_reg, + shift); + else + return -EINVAL; + + if (r == -EBUSY) + pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name); + + return r; +} + +/** + * _read_hardreset - read the HW reset line state of submodules + * contained in the hwmod module + * @oh: struct omap_hwmod * + * @name: name of the reset line to look up and read + * + * Return the state of the reset line. + */ +static int _read_hardreset(struct omap_hwmod *oh, const char *name) +{ + u8 shift; + + if (!oh) + return -EINVAL; + + shift = _lookup_hardreset(oh, name); + if (IS_ERR_VALUE(shift)) + return shift; + + if (cpu_is_omap24xx() || cpu_is_omap34xx()) { + return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs, + shift); + } else if (cpu_is_omap44xx()) { + return omap4_prm_is_hardreset_asserted(oh->prcm.omap4.rstctrl_reg, + shift); + } else { + return -EINVAL; + } +} + +/** * _reset - reset an omap_hwmod * @oh: struct omap_hwmod * * * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit. hwmod must be - * enabled for this to work. Must be called with omap_hwmod_mutex - * held. Returns -EINVAL if the hwmod cannot be reset this way or if - * the hwmod is in the wrong state, -ETIMEDOUT if the module did not - * reset in time, or 0 upon success. + * enabled for this to work. Returns -EINVAL if the hwmod cannot be + * reset this way or if the hwmod is in the wrong state, -ETIMEDOUT if + * the module did not reset in time, or 0 upon success. + * + * In OMAP3 a specific SYSSTATUS register is used to get the reset status. + * Starting in OMAP4, some IPs does not have SYSSTATUS register and instead + * use the SYSCONFIG softreset bit to provide the status. + * + * Note that some IP like McBSP does have a reset control but no reset status. */ static int _reset(struct omap_hwmod *oh) { - u32 r, v; + u32 v; int c = 0; + int ret = 0; if (!oh->class->sysc || - !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET) || - (oh->class->sysc->sysc_flags & SYSS_MISSING)) + !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) return -EINVAL; /* clocks must be on for this operation */ if (oh->_state != _HWMOD_STATE_ENABLED) { - WARN(1, "omap_hwmod: %s: reset can only be entered from " - "enabled state\n", oh->name); + pr_warning("omap_hwmod: %s: reset can only be entered from " + "enabled state\n", oh->name); return -EINVAL; } + /* For some modules, all optionnal clocks need to be enabled as well */ + if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) + _enable_optional_clocks(oh); + pr_debug("omap_hwmod: %s: resetting\n", oh->name); v = oh->_sysc_cache; - r = _set_softreset(oh, &v); - if (r) - return r; + ret = _set_softreset(oh, &v); + if (ret) + goto dis_opt_clks; _write_sysconfig(v, oh); - omap_test_timeout((omap_hwmod_readl(oh, oh->class->sysc->syss_offs) & - SYSS_RESETDONE_MASK), - MAX_MODULE_RESET_WAIT, c); - - if (c == MAX_MODULE_RESET_WAIT) - WARN(1, "omap_hwmod: %s: failed to reset in %d usec\n", - oh->name, MAX_MODULE_RESET_WAIT); + if (oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS) + omap_test_timeout((omap_hwmod_read(oh, + oh->class->sysc->syss_offs) + & SYSS_RESETDONE_MASK), + MAX_MODULE_SOFTRESET_WAIT, c); + else if (oh->class->sysc->sysc_flags & SYSC_HAS_RESET_STATUS) + omap_test_timeout(!(omap_hwmod_read(oh, + oh->class->sysc->sysc_offs) + & SYSC_TYPE2_SOFTRESET_MASK), + MAX_MODULE_SOFTRESET_WAIT, c); + + if (c == MAX_MODULE_SOFTRESET_WAIT) + pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n", + oh->name, MAX_MODULE_SOFTRESET_WAIT); else - pr_debug("omap_hwmod: %s: reset in %d usec\n", oh->name, c); + pr_debug("omap_hwmod: %s: softreset in %d usec\n", oh->name, c); /* * XXX add _HWMOD_STATE_WEDGED for modules that don't come back from * _wait_target_ready() or _reset() */ - return (c == MAX_MODULE_RESET_WAIT) ? -ETIMEDOUT : 0; + ret = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0; + +dis_opt_clks: + if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) + _disable_optional_clocks(oh); + + return ret; } /** @@ -891,9 +1168,11 @@ static int _reset(struct omap_hwmod *oh) * @oh: struct omap_hwmod * * * Enables an omap_hwmod @oh such that the MPU can access the hwmod's - * register target. Must be called with omap_hwmod_mutex held. - * Returns -EINVAL if the hwmod is in the wrong state or passes along - * the return value of _wait_target_ready(). + * register target. (This function has a full name -- + * _omap_hwmod_enable() rather than simply _enable() -- because it is + * currently required by the pm34xx.c idle loop.) Returns -EINVAL if + * the hwmod is in the wrong state or passes along the return value of + * _wait_target_ready(). */ int _omap_hwmod_enable(struct omap_hwmod *oh) { @@ -909,6 +1188,15 @@ int _omap_hwmod_enable(struct omap_hwmod *oh) pr_debug("omap_hwmod: %s: enabling\n", oh->name); + /* + * If an IP contains only one HW reset line, then de-assert it in order + * to allow to enable the clocks. Otherwise the PRCM will return + * Intransition status, and the init will failed. + */ + if ((oh->_state == _HWMOD_STATE_INITIALIZED || + oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1) + _deassert_hardreset(oh, oh->rst_lines[0].name); + /* XXX mux balls */ _add_initiator_dep(oh, mpu_oh); @@ -922,7 +1210,7 @@ int _omap_hwmod_enable(struct omap_hwmod *oh) if (oh->class->sysc) { if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED)) _update_sysc_cache(oh); - _sysc_enable(oh); + _enable_sysc(oh); } } else { pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n", @@ -933,12 +1221,14 @@ int _omap_hwmod_enable(struct omap_hwmod *oh) } /** - * _idle - idle an omap_hwmod + * _omap_hwmod_idle - idle an omap_hwmod * @oh: struct omap_hwmod * * * Idles an omap_hwmod @oh. This should be called once the hwmod has - * no further work. Returns -EINVAL if the hwmod is in the wrong - * state or returns 0. + * no further work. (This function has a full name -- + * _omap_hwmod_idle() rather than simply _idle() -- because it is + * currently required by the pm34xx.c idle loop.) Returns -EINVAL if + * the hwmod is in the wrong state or returns 0. */ int _omap_hwmod_idle(struct omap_hwmod *oh) { @@ -951,7 +1241,7 @@ int _omap_hwmod_idle(struct omap_hwmod *oh) pr_debug("omap_hwmod: %s: idling\n", oh->name); if (oh->class->sysc) - _sysc_idle(oh); + _idle_sysc(oh); _del_initiator_dep(oh, mpu_oh); _disable_clocks(oh); @@ -981,10 +1271,21 @@ static int _shutdown(struct omap_hwmod *oh) pr_debug("omap_hwmod: %s: disabling\n", oh->name); if (oh->class->sysc) - _sysc_shutdown(oh); - _del_initiator_dep(oh, mpu_oh); - /* XXX what about the other system initiators here? DMA, tesla, d2d */ - _disable_clocks(oh); + _shutdown_sysc(oh); + + /* + * If an IP contains only one HW reset line, then assert it + * before disabling the clocks and shutting down the IP. + */ + if (oh->rst_lines_cnt == 1) + _assert_hardreset(oh, oh->rst_lines[0].name); + + /* clocks and deps are already disabled in idle */ + if (oh->_state == _HWMOD_STATE_ENABLED) { + _del_initiator_dep(oh, mpu_oh); + /* XXX what about the other system initiators here? dma, dsp */ + _disable_clocks(oh); + } /* XXX Should this code also force-disable the optional clocks? */ /* XXX mux any associated balls to safe mode */ @@ -1000,11 +1301,10 @@ static int _shutdown(struct omap_hwmod *oh) * @skip_setup_idle_p: do not idle hwmods at the end of the fn if 1 * * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh - * OCP_SYSCONFIG register. Must be called with omap_hwmod_mutex held. - * @skip_setup_idle is intended to be used on a system that will not - * call omap_hwmod_enable() to enable devices (e.g., a system without - * PM runtime). Returns -EINVAL if the hwmod is in the wrong state or - * returns 0. + * OCP_SYSCONFIG register. @skip_setup_idle is intended to be used on + * a system that will not call omap_hwmod_enable() to enable devices + * (e.g., a system without PM runtime). Returns -EINVAL if the hwmod + * is in the wrong state or returns 0. */ static int _setup(struct omap_hwmod *oh, void *data) { @@ -1034,8 +1334,19 @@ static int _setup(struct omap_hwmod *oh, void *data) } } + mutex_init(&oh->_mutex); oh->_state = _HWMOD_STATE_INITIALIZED; + /* + * In the case of hwmod with hardreset that should not be + * de-assert at boot time, we have to keep the module + * initialized, because we cannot enable it properly with the + * reset asserted. Exit without warning because that behavior is + * expected. + */ + if ((oh->flags & HWMOD_INIT_NO_RESET) && oh->rst_lines_cnt == 1) + return 0; + r = _omap_hwmod_enable(oh); if (r) { pr_warning("omap_hwmod: %s: cannot be enabled (%d)\n", @@ -1044,16 +1355,16 @@ static int _setup(struct omap_hwmod *oh, void *data) } if (!(oh->flags & HWMOD_INIT_NO_RESET)) { + _reset(oh); + /* - * XXX Do the OCP_SYSCONFIG bits need to be - * reprogrammed after a reset? If not, then this can - * be removed. If they do, then probably the - * _omap_hwmod_enable() function should be split to avoid the - * rewrite of the OCP_SYSCONFIG register. + * OCP_SYSCONFIG bits need to be reprogrammed after a softreset. + * The _omap_hwmod_enable() function should be split to + * avoid the rewrite of the OCP_SYSCONFIG register. */ if (oh->class->sysc) { _update_sysc_cache(oh); - _sysc_enable(oh); + _enable_sysc(oh); } } @@ -1067,14 +1378,20 @@ static int _setup(struct omap_hwmod *oh, void *data) /* Public functions */ -u32 omap_hwmod_readl(struct omap_hwmod *oh, u16 reg_offs) +u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs) { - return __raw_readl(oh->_mpu_rt_va + reg_offs); + if (oh->flags & HWMOD_16BIT_REG) + return __raw_readw(oh->_mpu_rt_va + reg_offs); + else + return __raw_readl(oh->_mpu_rt_va + reg_offs); } -void omap_hwmod_writel(u32 v, struct omap_hwmod *oh, u16 reg_offs) +void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs) { - __raw_writel(v, oh->_mpu_rt_va + reg_offs); + if (oh->flags & HWMOD_16BIT_REG) + __raw_writew(v, oh->_mpu_rt_va + reg_offs); + else + __raw_writel(v, oh->_mpu_rt_va + reg_offs); } /** @@ -1309,7 +1626,7 @@ int omap_hwmod_unregister(struct omap_hwmod *oh) * omap_hwmod_enable - enable an omap_hwmod * @oh: struct omap_hwmod * * - * Enable an omap_hwomd @oh. Intended to be called by omap_device_enable(). + * Enable an omap_hwmod @oh. Intended to be called by omap_device_enable(). * Returns -EINVAL on error or passes along the return value from _enable(). */ int omap_hwmod_enable(struct omap_hwmod *oh) @@ -1319,9 +1636,9 @@ int omap_hwmod_enable(struct omap_hwmod *oh) if (!oh) return -EINVAL; - mutex_lock(&omap_hwmod_mutex); + mutex_lock(&oh->_mutex); r = _omap_hwmod_enable(oh); - mutex_unlock(&omap_hwmod_mutex); + mutex_unlock(&oh->_mutex); return r; } @@ -1331,7 +1648,7 @@ int omap_hwmod_enable(struct omap_hwmod *oh) * omap_hwmod_idle - idle an omap_hwmod * @oh: struct omap_hwmod * * - * Idle an omap_hwomd @oh. Intended to be called by omap_device_idle(). + * Idle an omap_hwmod @oh. Intended to be called by omap_device_idle(). * Returns -EINVAL on error or passes along the return value from _idle(). */ int omap_hwmod_idle(struct omap_hwmod *oh) @@ -1339,9 +1656,9 @@ int omap_hwmod_idle(struct omap_hwmod *oh) if (!oh) return -EINVAL; - mutex_lock(&omap_hwmod_mutex); + mutex_lock(&oh->_mutex); _omap_hwmod_idle(oh); - mutex_unlock(&omap_hwmod_mutex); + mutex_unlock(&oh->_mutex); return 0; } @@ -1350,7 +1667,7 @@ int omap_hwmod_idle(struct omap_hwmod *oh) * omap_hwmod_shutdown - shutdown an omap_hwmod * @oh: struct omap_hwmod * * - * Shutdown an omap_hwomd @oh. Intended to be called by + * Shutdown an omap_hwmod @oh. Intended to be called by * omap_device_shutdown(). Returns -EINVAL on error or passes along * the return value from _shutdown(). */ @@ -1359,9 +1676,9 @@ int omap_hwmod_shutdown(struct omap_hwmod *oh) if (!oh) return -EINVAL; - mutex_lock(&omap_hwmod_mutex); + mutex_lock(&oh->_mutex); _shutdown(oh); - mutex_unlock(&omap_hwmod_mutex); + mutex_unlock(&oh->_mutex); return 0; } @@ -1374,9 +1691,9 @@ int omap_hwmod_shutdown(struct omap_hwmod *oh) */ int omap_hwmod_enable_clocks(struct omap_hwmod *oh) { - mutex_lock(&omap_hwmod_mutex); + mutex_lock(&oh->_mutex); _enable_clocks(oh); - mutex_unlock(&omap_hwmod_mutex); + mutex_unlock(&oh->_mutex); return 0; } @@ -1389,9 +1706,9 @@ int omap_hwmod_enable_clocks(struct omap_hwmod *oh) */ int omap_hwmod_disable_clocks(struct omap_hwmod *oh) { - mutex_lock(&omap_hwmod_mutex); + mutex_lock(&oh->_mutex); _disable_clocks(oh); - mutex_unlock(&omap_hwmod_mutex); + mutex_unlock(&oh->_mutex); return 0; } @@ -1421,7 +1738,7 @@ void omap_hwmod_ocp_barrier(struct omap_hwmod *oh) * Forces posted writes to complete on the OCP thread handling * register writes */ - omap_hwmod_readl(oh, oh->class->sysc->sysc_offs); + omap_hwmod_read(oh, oh->class->sysc->sysc_offs); } /** @@ -1430,20 +1747,18 @@ void omap_hwmod_ocp_barrier(struct omap_hwmod *oh) * * Under some conditions, a driver may wish to reset the entire device. * Called from omap_device code. Returns -EINVAL on error or passes along - * the return value from _reset()/_enable(). + * the return value from _reset(). */ int omap_hwmod_reset(struct omap_hwmod *oh) { int r; - if (!oh || !(oh->_state & _HWMOD_STATE_ENABLED)) + if (!oh) return -EINVAL; - mutex_lock(&omap_hwmod_mutex); + mutex_lock(&oh->_mutex); r = _reset(oh); - if (!r) - r = _omap_hwmod_enable(oh); - mutex_unlock(&omap_hwmod_mutex); + mutex_unlock(&oh->_mutex); return r; } @@ -1468,7 +1783,7 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh) { int ret, i; - ret = oh->mpu_irqs_cnt + oh->sdma_chs_cnt; + ret = oh->mpu_irqs_cnt + oh->sdma_reqs_cnt; for (i = 0; i < oh->slaves_cnt; i++) ret += oh->slaves[i]->addr_cnt; @@ -1501,10 +1816,10 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) r++; } - for (i = 0; i < oh->sdma_chs_cnt; i++) { - (res + r)->name = (oh->sdma_chs + i)->name; - (res + r)->start = (oh->sdma_chs + i)->dma_ch; - (res + r)->end = (oh->sdma_chs + i)->dma_ch; + for (i = 0; i < oh->sdma_reqs_cnt; i++) { + (res + r)->name = (oh->sdma_reqs + i)->name; + (res + r)->start = (oh->sdma_reqs + i)->dma_req; + (res + r)->end = (oh->sdma_reqs + i)->dma_req; (res + r)->flags = IORESOURCE_DMA; r++; } @@ -1644,9 +1959,9 @@ int omap_hwmod_enable_wakeup(struct omap_hwmod *oh) !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) return -EINVAL; - mutex_lock(&omap_hwmod_mutex); + mutex_lock(&oh->_mutex); _enable_wakeup(oh); - mutex_unlock(&omap_hwmod_mutex); + mutex_unlock(&oh->_mutex); return 0; } @@ -1669,14 +1984,92 @@ int omap_hwmod_disable_wakeup(struct omap_hwmod *oh) !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) return -EINVAL; - mutex_lock(&omap_hwmod_mutex); + mutex_lock(&oh->_mutex); _disable_wakeup(oh); - mutex_unlock(&omap_hwmod_mutex); + mutex_unlock(&oh->_mutex); return 0; } /** + * omap_hwmod_assert_hardreset - assert the HW reset line of submodules + * contained in the hwmod module. + * @oh: struct omap_hwmod * + * @name: name of the reset line to lookup and assert + * + * Some IP like dsp, ipu or iva contain processor that require + * an HW reset line to be assert / deassert in order to enable fully + * the IP. Returns -EINVAL if @oh is null or if the operation is not + * yet supported on this OMAP; otherwise, passes along the return value + * from _assert_hardreset(). + */ +int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name) +{ + int ret; + + if (!oh) + return -EINVAL; + + mutex_lock(&oh->_mutex); + ret = _assert_hardreset(oh, name); + mutex_unlock(&oh->_mutex); + + return ret; +} + +/** + * omap_hwmod_deassert_hardreset - deassert the HW reset line of submodules + * contained in the hwmod module. + * @oh: struct omap_hwmod * + * @name: name of the reset line to look up and deassert + * + * Some IP like dsp, ipu or iva contain processor that require + * an HW reset line to be assert / deassert in order to enable fully + * the IP. Returns -EINVAL if @oh is null or if the operation is not + * yet supported on this OMAP; otherwise, passes along the return value + * from _deassert_hardreset(). + */ +int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name) +{ + int ret; + + if (!oh) + return -EINVAL; + + mutex_lock(&oh->_mutex); + ret = _deassert_hardreset(oh, name); + mutex_unlock(&oh->_mutex); + + return ret; +} + +/** + * omap_hwmod_read_hardreset - read the HW reset line state of submodules + * contained in the hwmod module + * @oh: struct omap_hwmod * + * @name: name of the reset line to look up and read + * + * Return the current state of the hwmod @oh's reset line named @name: + * returns -EINVAL upon parameter error or if this operation + * is unsupported on the current OMAP; otherwise, passes along the return + * value from _read_hardreset(). + */ +int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name) +{ + int ret; + + if (!oh) + return -EINVAL; + + mutex_lock(&oh->_mutex); + ret = _read_hardreset(oh, name); + mutex_unlock(&oh->_mutex); + + return ret; +} + + +/** * omap_hwmod_for_each_by_class - call @fn for each hwmod of class @classname * @classname: struct omap_hwmod_class name to search for * @fn: callback function pointer to call for each hwmod in class @classname diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index 3cc768e8bc04..adf6e3632a2b 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -15,10 +15,12 @@ #include <mach/irqs.h> #include <plat/cpu.h> #include <plat/dma.h> +#include <plat/serial.h> #include "omap_hwmod_common_data.h" #include "prm-regbits-24xx.h" +#include "cm-regbits-24xx.h" /* * OMAP2420 hardware module integration data @@ -33,6 +35,7 @@ static struct omap_hwmod omap2420_mpu_hwmod; static struct omap_hwmod omap2420_iva_hwmod; static struct omap_hwmod omap2420_l3_main_hwmod; static struct omap_hwmod omap2420_l4_core_hwmod; +static struct omap_hwmod omap2420_wd_timer2_hwmod; /* L3 -> L4_CORE interface */ static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = { @@ -71,6 +74,9 @@ static struct omap_hwmod omap2420_l3_main_hwmod = { }; static struct omap_hwmod omap2420_l4_wkup_hwmod; +static struct omap_hwmod omap2420_uart1_hwmod; +static struct omap_hwmod omap2420_uart2_hwmod; +static struct omap_hwmod omap2420_uart3_hwmod; /* L4_CORE -> L4_WKUP interface */ static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { @@ -79,6 +85,60 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* L4 CORE -> UART1 interface */ +static struct omap_hwmod_addr_space omap2420_uart1_addr_space[] = { + { + .pa_start = OMAP2_UART1_BASE, + .pa_end = OMAP2_UART1_BASE + SZ_8K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_uart1_hwmod, + .clk = "uart1_ick", + .addr = omap2420_uart1_addr_space, + .addr_cnt = ARRAY_SIZE(omap2420_uart1_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> UART2 interface */ +static struct omap_hwmod_addr_space omap2420_uart2_addr_space[] = { + { + .pa_start = OMAP2_UART2_BASE, + .pa_end = OMAP2_UART2_BASE + SZ_1K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_uart2_hwmod, + .clk = "uart2_ick", + .addr = omap2420_uart2_addr_space, + .addr_cnt = ARRAY_SIZE(omap2420_uart2_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 PER -> UART3 interface */ +static struct omap_hwmod_addr_space omap2420_uart3_addr_space[] = { + { + .pa_start = OMAP2_UART3_BASE, + .pa_end = OMAP2_UART3_BASE + SZ_1K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_uart3_hwmod, + .clk = "uart3_ick", + .addr = omap2420_uart3_addr_space, + .addr_cnt = ARRAY_SIZE(omap2420_uart3_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* Slave interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = { &omap2420_l3_main__l4_core, @@ -87,6 +147,9 @@ static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = { /* Master interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = { &omap2420_l4_core__l4_wkup, + &omap2_l4_core__uart1, + &omap2_l4_core__uart2, + &omap2_l4_core__uart3, }; /* L4 CORE */ @@ -165,12 +228,206 @@ static struct omap_hwmod omap2420_iva_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) }; +/* l4_wkup -> wd_timer2 */ +static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = { + { + .pa_start = 0x48022000, + .pa_end = 0x4802207f, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = { + .master = &omap2420_l4_wkup_hwmod, + .slave = &omap2420_wd_timer2_hwmod, + .clk = "mpu_wdt_ick", + .addr = omap2420_wd_timer2_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_wd_timer2_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* + * 'wd_timer' class + * 32-bit watchdog upward counter that generates a pulse on the reset pin on + * overflow condition + */ + +static struct omap_hwmod_class_sysconfig omap2420_wd_timer_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2420_wd_timer_hwmod_class = { + .name = "wd_timer", + .sysc = &omap2420_wd_timer_sysc, +}; + +/* wd_timer2 */ +static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = { + &omap2420_l4_wkup__wd_timer2, +}; + +static struct omap_hwmod omap2420_wd_timer2_hwmod = { + .name = "wd_timer2", + .class = &omap2420_wd_timer_hwmod_class, + .main_clk = "mpu_wdt_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, + }, + }, + .slaves = omap2420_wd_timer2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_wd_timer2_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), +}; + +/* UART */ + +static struct omap_hwmod_class_sysconfig uart_sysc = { + .rev_offs = 0x50, + .sysc_offs = 0x54, + .syss_offs = 0x58, + .sysc_flags = (SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class uart_class = { + .name = "uart", + .sysc = &uart_sysc, +}; + +/* UART1 */ + +static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { + { .irq = INT_24XX_UART1_IRQ, }, +}; + +static struct omap_hwmod_dma_info uart1_sdma_reqs[] = { + { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, + { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, +}; + +static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = { + &omap2_l4_core__uart1, +}; + +static struct omap_hwmod omap2420_uart1_hwmod = { + .name = "uart1", + .mpu_irqs = uart1_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), + .sdma_reqs = uart1_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs), + .main_clk = "uart1_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_UART1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, + }, + }, + .slaves = omap2420_uart1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves), + .class = &uart_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), +}; + +/* UART2 */ + +static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { + { .irq = INT_24XX_UART2_IRQ, }, +}; + +static struct omap_hwmod_dma_info uart2_sdma_reqs[] = { + { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, + { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, +}; + +static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = { + &omap2_l4_core__uart2, +}; + +static struct omap_hwmod omap2420_uart2_hwmod = { + .name = "uart2", + .mpu_irqs = uart2_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), + .sdma_reqs = uart2_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs), + .main_clk = "uart2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_UART2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, + }, + }, + .slaves = omap2420_uart2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves), + .class = &uart_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), +}; + +/* UART3 */ + +static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { + { .irq = INT_24XX_UART3_IRQ, }, +}; + +static struct omap_hwmod_dma_info uart3_sdma_reqs[] = { + { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, + { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, +}; + +static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = { + &omap2_l4_core__uart3, +}; + +static struct omap_hwmod omap2420_uart3_hwmod = { + .name = "uart3", + .mpu_irqs = uart3_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), + .sdma_reqs = uart3_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs), + .main_clk = "uart3_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 2, + .module_bit = OMAP24XX_EN_UART3_SHIFT, + .idlest_reg_id = 2, + .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, + }, + }, + .slaves = omap2420_uart3_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves), + .class = &uart_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), +}; + static __initdata struct omap_hwmod *omap2420_hwmods[] = { &omap2420_l3_main_hwmod, &omap2420_l4_core_hwmod, &omap2420_l4_wkup_hwmod, &omap2420_mpu_hwmod, &omap2420_iva_hwmod, + &omap2420_wd_timer2_hwmod, + &omap2420_uart1_hwmod, + &omap2420_uart2_hwmod, + &omap2420_uart3_hwmod, NULL, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 4526628ed287..12d939e456cf 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -15,10 +15,12 @@ #include <mach/irqs.h> #include <plat/cpu.h> #include <plat/dma.h> +#include <plat/serial.h> #include "omap_hwmod_common_data.h" #include "prm-regbits-24xx.h" +#include "cm-regbits-24xx.h" /* * OMAP2430 hardware module integration data @@ -33,6 +35,7 @@ static struct omap_hwmod omap2430_mpu_hwmod; static struct omap_hwmod omap2430_iva_hwmod; static struct omap_hwmod omap2430_l3_main_hwmod; static struct omap_hwmod omap2430_l4_core_hwmod; +static struct omap_hwmod omap2430_wd_timer2_hwmod; /* L3 -> L4_CORE interface */ static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = { @@ -71,6 +74,9 @@ static struct omap_hwmod omap2430_l3_main_hwmod = { }; static struct omap_hwmod omap2430_l4_wkup_hwmod; +static struct omap_hwmod omap2430_uart1_hwmod; +static struct omap_hwmod omap2430_uart2_hwmod; +static struct omap_hwmod omap2430_uart3_hwmod; /* L4_CORE -> L4_WKUP interface */ static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = { @@ -79,6 +85,60 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* L4 CORE -> UART1 interface */ +static struct omap_hwmod_addr_space omap2430_uart1_addr_space[] = { + { + .pa_start = OMAP2_UART1_BASE, + .pa_end = OMAP2_UART1_BASE + SZ_8K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_uart1_hwmod, + .clk = "uart1_ick", + .addr = omap2430_uart1_addr_space, + .addr_cnt = ARRAY_SIZE(omap2430_uart1_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> UART2 interface */ +static struct omap_hwmod_addr_space omap2430_uart2_addr_space[] = { + { + .pa_start = OMAP2_UART2_BASE, + .pa_end = OMAP2_UART2_BASE + SZ_1K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_uart2_hwmod, + .clk = "uart2_ick", + .addr = omap2430_uart2_addr_space, + .addr_cnt = ARRAY_SIZE(omap2430_uart2_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 PER -> UART3 interface */ +static struct omap_hwmod_addr_space omap2430_uart3_addr_space[] = { + { + .pa_start = OMAP2_UART3_BASE, + .pa_end = OMAP2_UART3_BASE + SZ_1K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_uart3_hwmod, + .clk = "uart3_ick", + .addr = omap2430_uart3_addr_space, + .addr_cnt = ARRAY_SIZE(omap2430_uart3_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* Slave interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = { &omap2430_l3_main__l4_core, @@ -104,6 +164,9 @@ static struct omap_hwmod omap2430_l4_core_hwmod = { /* Slave interfaces on the L4_WKUP interconnect */ static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = { &omap2430_l4_core__l4_wkup, + &omap2_l4_core__uart1, + &omap2_l4_core__uart2, + &omap2_l4_core__uart3, }; /* Master interfaces on the L4_WKUP interconnect */ @@ -165,12 +228,206 @@ static struct omap_hwmod omap2430_iva_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) }; +/* l4_wkup -> wd_timer2 */ +static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = { + { + .pa_start = 0x49016000, + .pa_end = 0x4901607f, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { + .master = &omap2430_l4_wkup_hwmod, + .slave = &omap2430_wd_timer2_hwmod, + .clk = "mpu_wdt_ick", + .addr = omap2430_wd_timer2_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_wd_timer2_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* + * 'wd_timer' class + * 32-bit watchdog upward counter that generates a pulse on the reset pin on + * overflow condition + */ + +static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = { + .rev_offs = 0x0, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = { + .name = "wd_timer", + .sysc = &omap2430_wd_timer_sysc, +}; + +/* wd_timer2 */ +static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = { + &omap2430_l4_wkup__wd_timer2, +}; + +static struct omap_hwmod omap2430_wd_timer2_hwmod = { + .name = "wd_timer2", + .class = &omap2430_wd_timer_hwmod_class, + .main_clk = "mpu_wdt_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, + }, + }, + .slaves = omap2430_wd_timer2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_wd_timer2_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* UART */ + +static struct omap_hwmod_class_sysconfig uart_sysc = { + .rev_offs = 0x50, + .sysc_offs = 0x54, + .syss_offs = 0x58, + .sysc_flags = (SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class uart_class = { + .name = "uart", + .sysc = &uart_sysc, +}; + +/* UART1 */ + +static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { + { .irq = INT_24XX_UART1_IRQ, }, +}; + +static struct omap_hwmod_dma_info uart1_sdma_reqs[] = { + { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, + { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, +}; + +static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = { + &omap2_l4_core__uart1, +}; + +static struct omap_hwmod omap2430_uart1_hwmod = { + .name = "uart1", + .mpu_irqs = uart1_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), + .sdma_reqs = uart1_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs), + .main_clk = "uart1_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_UART1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, + }, + }, + .slaves = omap2430_uart1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves), + .class = &uart_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* UART2 */ + +static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { + { .irq = INT_24XX_UART2_IRQ, }, +}; + +static struct omap_hwmod_dma_info uart2_sdma_reqs[] = { + { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, + { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, +}; + +static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = { + &omap2_l4_core__uart2, +}; + +static struct omap_hwmod omap2430_uart2_hwmod = { + .name = "uart2", + .mpu_irqs = uart2_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), + .sdma_reqs = uart2_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs), + .main_clk = "uart2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_UART2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, + }, + }, + .slaves = omap2430_uart2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves), + .class = &uart_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* UART3 */ + +static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { + { .irq = INT_24XX_UART3_IRQ, }, +}; + +static struct omap_hwmod_dma_info uart3_sdma_reqs[] = { + { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, + { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, +}; + +static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = { + &omap2_l4_core__uart3, +}; + +static struct omap_hwmod omap2430_uart3_hwmod = { + .name = "uart3", + .mpu_irqs = uart3_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), + .sdma_reqs = uart3_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs), + .main_clk = "uart3_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 2, + .module_bit = OMAP24XX_EN_UART3_SHIFT, + .idlest_reg_id = 2, + .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, + }, + }, + .slaves = omap2430_uart3_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves), + .class = &uart_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + static __initdata struct omap_hwmod *omap2430_hwmods[] = { &omap2430_l3_main_hwmod, &omap2430_l4_core_hwmod, &omap2430_l4_wkup_hwmod, &omap2430_mpu_hwmod, &omap2430_iva_hwmod, + &omap2430_wd_timer2_hwmod, + &omap2430_uart1_hwmod, + &omap2430_uart2_hwmod, + &omap2430_uart3_hwmod, NULL, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 5d8eb58ba5e3..cb97ecf0a3f6 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -17,10 +17,12 @@ #include <mach/irqs.h> #include <plat/cpu.h> #include <plat/dma.h> +#include <plat/serial.h> #include "omap_hwmod_common_data.h" #include "prm-regbits-34xx.h" +#include "cm-regbits-34xx.h" /* * OMAP3xxx hardware module integration data @@ -36,6 +38,7 @@ static struct omap_hwmod omap3xxx_iva_hwmod; static struct omap_hwmod omap3xxx_l3_main_hwmod; static struct omap_hwmod omap3xxx_l4_core_hwmod; static struct omap_hwmod omap3xxx_l4_per_hwmod; +static struct omap_hwmod omap3xxx_wd_timer2_hwmod; /* L3 -> L4_CORE interface */ static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { @@ -82,6 +85,10 @@ static struct omap_hwmod omap3xxx_l3_main_hwmod = { }; static struct omap_hwmod omap3xxx_l4_wkup_hwmod; +static struct omap_hwmod omap3xxx_uart1_hwmod; +static struct omap_hwmod omap3xxx_uart2_hwmod; +static struct omap_hwmod omap3xxx_uart3_hwmod; +static struct omap_hwmod omap3xxx_uart4_hwmod; /* L4_CORE -> L4_WKUP interface */ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { @@ -90,6 +97,78 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* L4 CORE -> UART1 interface */ +static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = { + { + .pa_start = OMAP3_UART1_BASE, + .pa_end = OMAP3_UART1_BASE + SZ_8K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_uart1_hwmod, + .clk = "uart1_ick", + .addr = omap3xxx_uart1_addr_space, + .addr_cnt = ARRAY_SIZE(omap3xxx_uart1_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> UART2 interface */ +static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = { + { + .pa_start = OMAP3_UART2_BASE, + .pa_end = OMAP3_UART2_BASE + SZ_1K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_uart2_hwmod, + .clk = "uart2_ick", + .addr = omap3xxx_uart2_addr_space, + .addr_cnt = ARRAY_SIZE(omap3xxx_uart2_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 PER -> UART3 interface */ +static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = { + { + .pa_start = OMAP3_UART3_BASE, + .pa_end = OMAP3_UART3_BASE + SZ_1K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_uart3_hwmod, + .clk = "uart3_ick", + .addr = omap3xxx_uart3_addr_space, + .addr_cnt = ARRAY_SIZE(omap3xxx_uart3_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 PER -> UART4 interface */ +static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = { + { + .pa_start = OMAP3_UART4_BASE, + .pa_end = OMAP3_UART4_BASE + SZ_1K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_uart4_hwmod, + .clk = "uart4_ick", + .addr = omap3xxx_uart4_addr_space, + .addr_cnt = ARRAY_SIZE(omap3xxx_uart4_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* Slave interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { &omap3xxx_l3_main__l4_core, @@ -98,6 +177,8 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { /* Master interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = { &omap3xxx_l4_core__l4_wkup, + &omap3_l4_core__uart1, + &omap3_l4_core__uart2, }; /* L4 CORE */ @@ -119,6 +200,8 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = { /* Master interfaces on the L4_PER interconnect */ static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = { + &omap3_l4_per__uart3, + &omap3_l4_per__uart4, }; /* L4 PER */ @@ -197,6 +280,235 @@ static struct omap_hwmod omap3xxx_iva_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) }; +/* l4_wkup -> wd_timer2 */ +static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = { + { + .pa_start = 0x48314000, + .pa_end = 0x4831407f, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { + .master = &omap3xxx_l4_wkup_hwmod, + .slave = &omap3xxx_wd_timer2_hwmod, + .clk = "wdt2_ick", + .addr = omap3xxx_wd_timer2_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* + * 'wd_timer' class + * 32-bit watchdog upward counter that generates a pulse on the reset pin on + * overflow condition + */ + +static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { + .name = "wd_timer", + .sysc = &omap3xxx_wd_timer_sysc, +}; + +/* wd_timer2 */ +static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = { + &omap3xxx_l4_wkup__wd_timer2, +}; + +static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { + .name = "wd_timer2", + .class = &omap3xxx_wd_timer_hwmod_class, + .main_clk = "wdt2_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_WDT2_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT, + }, + }, + .slaves = omap3xxx_wd_timer2_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* UART common */ + +static struct omap_hwmod_class_sysconfig uart_sysc = { + .rev_offs = 0x50, + .sysc_offs = 0x54, + .syss_offs = 0x58, + .sysc_flags = (SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class uart_class = { + .name = "uart", + .sysc = &uart_sysc, +}; + +/* UART1 */ + +static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { + { .irq = INT_24XX_UART1_IRQ, }, +}; + +static struct omap_hwmod_dma_info uart1_sdma_reqs[] = { + { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, + { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = { + &omap3_l4_core__uart1, +}; + +static struct omap_hwmod omap3xxx_uart1_hwmod = { + .name = "uart1", + .mpu_irqs = uart1_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), + .sdma_reqs = uart1_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs), + .main_clk = "uart1_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_UART1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT, + }, + }, + .slaves = omap3xxx_uart1_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves), + .class = &uart_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* UART2 */ + +static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { + { .irq = INT_24XX_UART2_IRQ, }, +}; + +static struct omap_hwmod_dma_info uart2_sdma_reqs[] = { + { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, + { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = { + &omap3_l4_core__uart2, +}; + +static struct omap_hwmod omap3xxx_uart2_hwmod = { + .name = "uart2", + .mpu_irqs = uart2_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), + .sdma_reqs = uart2_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs), + .main_clk = "uart2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_UART2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT, + }, + }, + .slaves = omap3xxx_uart2_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves), + .class = &uart_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* UART3 */ + +static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { + { .irq = INT_24XX_UART3_IRQ, }, +}; + +static struct omap_hwmod_dma_info uart3_sdma_reqs[] = { + { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, + { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = { + &omap3_l4_per__uart3, +}; + +static struct omap_hwmod omap3xxx_uart3_hwmod = { + .name = "uart3", + .mpu_irqs = uart3_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), + .sdma_reqs = uart3_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs), + .main_clk = "uart3_fck", + .prcm = { + .omap2 = { + .module_offs = OMAP3430_PER_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_UART3_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT, + }, + }, + .slaves = omap3xxx_uart3_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves), + .class = &uart_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* UART4 */ + +static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { + { .irq = INT_36XX_UART4_IRQ, }, +}; + +static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { + { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, }, + { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = { + &omap3_l4_per__uart4, +}; + +static struct omap_hwmod omap3xxx_uart4_hwmod = { + .name = "uart4", + .mpu_irqs = uart4_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(uart4_mpu_irqs), + .sdma_reqs = uart4_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(uart4_sdma_reqs), + .main_clk = "uart4_fck", + .prcm = { + .omap2 = { + .module_offs = OMAP3430_PER_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3630_EN_UART4_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT, + }, + }, + .slaves = omap3xxx_uart4_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves), + .class = &uart_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), +}; + static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { &omap3xxx_l3_main_hwmod, &omap3xxx_l4_core_hwmod, @@ -204,6 +516,11 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { &omap3xxx_l4_wkup_hwmod, &omap3xxx_mpu_hwmod, &omap3xxx_iva_hwmod, + &omap3xxx_wd_timer2_hwmod, + &omap3xxx_uart1_hwmod, + &omap3xxx_uart2_hwmod, + &omap3xxx_uart3_hwmod, + &omap3xxx_uart4_hwmod, NULL, }; @@ -211,5 +528,3 @@ int __init omap3xxx_hwmod_init(void) { return omap_hwmod_init(omap3xxx_hwmods); } - - diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c new file mode 100644 index 000000000000..7274db4de487 --- /dev/null +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -0,0 +1,850 @@ +/* + * Hardware modules present on the OMAP44xx chips + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * Copyright (C) 2009-2010 Nokia Corporation + * + * Paul Walmsley + * Benoit Cousson + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/io.h> + +#include <plat/omap_hwmod.h> +#include <plat/cpu.h> + +#include "omap_hwmod_common_data.h" + +#include "cm.h" +#include "prm-regbits-44xx.h" + +/* Base offset for all OMAP4 interrupts external to MPUSS */ +#define OMAP44XX_IRQ_GIC_START 32 + +/* Base offset for all OMAP4 dma requests */ +#define OMAP44XX_DMA_REQ_START 1 + +/* Backward references (IPs with Bus Master capability) */ +static struct omap_hwmod omap44xx_dmm_hwmod; +static struct omap_hwmod omap44xx_emif_fw_hwmod; +static struct omap_hwmod omap44xx_l3_instr_hwmod; +static struct omap_hwmod omap44xx_l3_main_1_hwmod; +static struct omap_hwmod omap44xx_l3_main_2_hwmod; +static struct omap_hwmod omap44xx_l3_main_3_hwmod; +static struct omap_hwmod omap44xx_l4_abe_hwmod; +static struct omap_hwmod omap44xx_l4_cfg_hwmod; +static struct omap_hwmod omap44xx_l4_per_hwmod; +static struct omap_hwmod omap44xx_l4_wkup_hwmod; +static struct omap_hwmod omap44xx_mpu_hwmod; +static struct omap_hwmod omap44xx_mpu_private_hwmod; + +/* + * Interconnects omap_hwmod structures + * hwmods that compose the global OMAP interconnect + */ + +/* + * 'dmm' class + * instance(s): dmm + */ +static struct omap_hwmod_class omap44xx_dmm_hwmod_class = { + .name = "dmm", +}; + +/* dmm interface data */ +/* l3_main_1 -> dmm */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { + .master = &omap44xx_l3_main_1_hwmod, + .slave = &omap44xx_dmm_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mpu -> dmm */ +static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { + .master = &omap44xx_mpu_hwmod, + .slave = &omap44xx_dmm_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dmm slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = { + &omap44xx_l3_main_1__dmm, + &omap44xx_mpu__dmm, +}; + +static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = { + { .irq = 113 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod omap44xx_dmm_hwmod = { + .name = "dmm", + .class = &omap44xx_dmm_hwmod_class, + .slaves = omap44xx_dmm_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves), + .mpu_irqs = omap44xx_dmm_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmm_irqs), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* + * 'emif_fw' class + * instance(s): emif_fw + */ +static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = { + .name = "emif_fw", +}; + +/* emif_fw interface data */ +/* dmm -> emif_fw */ +static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = { + .master = &omap44xx_dmm_hwmod, + .slave = &omap44xx_emif_fw_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_cfg -> emif_fw */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_emif_fw_hwmod, + .clk = "l4_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* emif_fw slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = { + &omap44xx_dmm__emif_fw, + &omap44xx_l4_cfg__emif_fw, +}; + +static struct omap_hwmod omap44xx_emif_fw_hwmod = { + .name = "emif_fw", + .class = &omap44xx_emif_fw_hwmod_class, + .slaves = omap44xx_emif_fw_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* + * 'l3' class + * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3 + */ +static struct omap_hwmod_class omap44xx_l3_hwmod_class = { + .name = "l3", +}; + +/* l3_instr interface data */ +/* l3_main_3 -> l3_instr */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { + .master = &omap44xx_l3_main_3_hwmod, + .slave = &omap44xx_l3_instr_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_instr slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = { + &omap44xx_l3_main_3__l3_instr, +}; + +static struct omap_hwmod omap44xx_l3_instr_hwmod = { + .name = "l3_instr", + .class = &omap44xx_l3_hwmod_class, + .slaves = omap44xx_l3_instr_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* l3_main_2 -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_l3_main_1_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_cfg -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_l3_main_1_hwmod, + .clk = "l4_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mpu -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { + .master = &omap44xx_mpu_hwmod, + .slave = &omap44xx_l3_main_1_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = { + &omap44xx_l3_main_2__l3_main_1, + &omap44xx_l4_cfg__l3_main_1, + &omap44xx_mpu__l3_main_1, +}; + +static struct omap_hwmod omap44xx_l3_main_1_hwmod = { + .name = "l3_main_1", + .class = &omap44xx_l3_hwmod_class, + .slaves = omap44xx_l3_main_1_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* l3_main_2 interface data */ +/* l3_main_1 -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { + .master = &omap44xx_l3_main_1_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_cfg -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l4_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_2 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = { + &omap44xx_l3_main_1__l3_main_2, + &omap44xx_l4_cfg__l3_main_2, +}; + +static struct omap_hwmod omap44xx_l3_main_2_hwmod = { + .name = "l3_main_2", + .class = &omap44xx_l3_hwmod_class, + .slaves = omap44xx_l3_main_2_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* l3_main_3 interface data */ +/* l3_main_1 -> l3_main_3 */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { + .master = &omap44xx_l3_main_1_hwmod, + .slave = &omap44xx_l3_main_3_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_2 -> l3_main_3 */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_l3_main_3_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_cfg -> l3_main_3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_l3_main_3_hwmod, + .clk = "l4_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_3 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = { + &omap44xx_l3_main_1__l3_main_3, + &omap44xx_l3_main_2__l3_main_3, + &omap44xx_l4_cfg__l3_main_3, +}; + +static struct omap_hwmod omap44xx_l3_main_3_hwmod = { + .name = "l3_main_3", + .class = &omap44xx_l3_hwmod_class, + .slaves = omap44xx_l3_main_3_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* + * 'l4' class + * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup + */ +static struct omap_hwmod_class omap44xx_l4_hwmod_class = { + .name = "l4", +}; + +/* l4_abe interface data */ +/* l3_main_1 -> l4_abe */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = { + .master = &omap44xx_l3_main_1_hwmod, + .slave = &omap44xx_l4_abe_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mpu -> l4_abe */ +static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = { + .master = &omap44xx_mpu_hwmod, + .slave = &omap44xx_l4_abe_hwmod, + .clk = "ocp_abe_iclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_abe slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = { + &omap44xx_l3_main_1__l4_abe, + &omap44xx_mpu__l4_abe, +}; + +static struct omap_hwmod omap44xx_l4_abe_hwmod = { + .name = "l4_abe", + .class = &omap44xx_l4_hwmod_class, + .slaves = omap44xx_l4_abe_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* l4_cfg interface data */ +/* l3_main_1 -> l4_cfg */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = { + .master = &omap44xx_l3_main_1_hwmod, + .slave = &omap44xx_l4_cfg_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_cfg slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = { + &omap44xx_l3_main_1__l4_cfg, +}; + +static struct omap_hwmod omap44xx_l4_cfg_hwmod = { + .name = "l4_cfg", + .class = &omap44xx_l4_hwmod_class, + .slaves = omap44xx_l4_cfg_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* l4_per interface data */ +/* l3_main_2 -> l4_per */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_l4_per_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = { + &omap44xx_l3_main_2__l4_per, +}; + +static struct omap_hwmod omap44xx_l4_per_hwmod = { + .name = "l4_per", + .class = &omap44xx_l4_hwmod_class, + .slaves = omap44xx_l4_per_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* l4_wkup interface data */ +/* l4_cfg -> l4_wkup */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_l4_wkup_hwmod, + .clk = "l4_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = { + &omap44xx_l4_cfg__l4_wkup, +}; + +static struct omap_hwmod omap44xx_l4_wkup_hwmod = { + .name = "l4_wkup", + .class = &omap44xx_l4_hwmod_class, + .slaves = omap44xx_l4_wkup_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* + * 'mpu_bus' class + * instance(s): mpu_private + */ +static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = { + .name = "mpu_bus", +}; + +/* mpu_private interface data */ +/* mpu -> mpu_private */ +static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { + .master = &omap44xx_mpu_hwmod, + .slave = &omap44xx_mpu_private_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mpu_private slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = { + &omap44xx_mpu__mpu_private, +}; + +static struct omap_hwmod omap44xx_mpu_private_hwmod = { + .name = "mpu_private", + .class = &omap44xx_mpu_bus_hwmod_class, + .slaves = omap44xx_mpu_private_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* + * 'mpu' class + * mpu sub-system + */ + +static struct omap_hwmod_class omap44xx_mpu_hwmod_class = { + .name = "mpu", +}; + +/* mpu */ +static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = { + { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START }, + { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START }, + { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START }, +}; + +/* mpu master ports */ +static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = { + &omap44xx_mpu__l3_main_1, + &omap44xx_mpu__l4_abe, + &omap44xx_mpu__dmm, +}; + +static struct omap_hwmod omap44xx_mpu_hwmod = { + .name = "mpu", + .class = &omap44xx_mpu_hwmod_class, + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), + .mpu_irqs = omap44xx_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mpu_irqs), + .main_clk = "dpll_mpu_m2_ck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL, + }, + }, + .masters = omap44xx_mpu_masters, + .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* + * 'wd_timer' class + * 32-bit watchdog upward counter that generates a pulse on the reset pin on + * overflow condition + */ + +static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | + SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +/* + * 'uart' class + * universal asynchronous receiver/transmitter (uart) + */ + +static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = { + .rev_offs = 0x0050, + .sysc_offs = 0x0054, + .syss_offs = 0x0058, + .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = { + .name = "wd_timer", + .sysc = &omap44xx_wd_timer_sysc, +}; + +/* wd_timer2 */ +static struct omap_hwmod omap44xx_wd_timer2_hwmod; +static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = { + { .irq = 80 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { + { + .pa_start = 0x4a314000, + .pa_end = 0x4a31407f, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_class omap44xx_uart_hwmod_class = { + .name = "uart", + .sysc = &omap44xx_uart_sysc, +}; + +/* uart1 */ +static struct omap_hwmod omap44xx_uart1_hwmod; +static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = { + { .irq = 72 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = { + { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START }, + { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = { + { + .pa_start = 0x4806a000, + .pa_end = 0x4806a0ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> uart1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_uart1_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_uart1_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_uart1_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* uart1 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = { + &omap44xx_l4_per__uart1, +}; + +static struct omap_hwmod omap44xx_uart1_hwmod = { + .name = "uart1", + .class = &omap44xx_uart_hwmod_class, + .mpu_irqs = omap44xx_uart1_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart1_irqs), + .sdma_reqs = omap44xx_uart1_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart1_sdma_reqs), + .main_clk = "uart1_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL, + }, + }, + .slaves = omap44xx_uart1_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* uart2 */ +static struct omap_hwmod omap44xx_uart2_hwmod; +static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = { + { .irq = 73 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = { + { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START }, + { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = { + { + .pa_start = 0x4806c000, + .pa_end = 0x4806c0ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_wkup -> wd_timer2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { + .master = &omap44xx_l4_wkup_hwmod, + .slave = &omap44xx_wd_timer2_hwmod, + .clk = "l4_wkup_clk_mux_ck", + .addr = omap44xx_wd_timer2_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer2_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* wd_timer2 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = { + &omap44xx_l4_wkup__wd_timer2, +}; + +static struct omap_hwmod omap44xx_wd_timer2_hwmod = { + .name = "wd_timer2", + .class = &omap44xx_wd_timer_hwmod_class, + .mpu_irqs = omap44xx_wd_timer2_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer2_irqs), + .main_clk = "wd_timer2_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, + }, + }, + .slaves = omap44xx_wd_timer2_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* wd_timer3 */ +static struct omap_hwmod omap44xx_wd_timer3_hwmod; +static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = { + { .irq = 36 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { + { + .pa_start = 0x40130000, + .pa_end = 0x4013007f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> uart2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_uart2_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_uart2_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_uart2_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* uart2 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = { + &omap44xx_l4_per__uart2, +}; + +static struct omap_hwmod omap44xx_uart2_hwmod = { + .name = "uart2", + .class = &omap44xx_uart_hwmod_class, + .mpu_irqs = omap44xx_uart2_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart2_irqs), + .sdma_reqs = omap44xx_uart2_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart2_sdma_reqs), + .main_clk = "uart2_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL, + }, + }, + .slaves = omap44xx_uart2_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* uart3 */ +static struct omap_hwmod omap44xx_uart3_hwmod; +static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = { + { .irq = 74 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = { + { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START }, + { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = { + { + .pa_start = 0x48020000, + .pa_end = 0x480200ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_abe -> wd_timer3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_wd_timer3_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_wd_timer3_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_addrs), + .user = OCP_USER_MPU, +}; + +/* l4_abe -> wd_timer3 (dma) */ +static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { + { + .pa_start = 0x49030000, + .pa_end = 0x4903007f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> uart3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_uart3_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_uart3_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_uart3_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* uart3 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = { + &omap44xx_l4_per__uart3, +}; + +static struct omap_hwmod omap44xx_uart3_hwmod = { + .name = "uart3", + .class = &omap44xx_uart_hwmod_class, + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), + .mpu_irqs = omap44xx_uart3_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart3_irqs), + .sdma_reqs = omap44xx_uart3_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart3_sdma_reqs), + .main_clk = "uart3_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL, + }, + }, + .slaves = omap44xx_uart3_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* uart4 */ +static struct omap_hwmod omap44xx_uart4_hwmod; +static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = { + { .irq = 70 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = { + { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START }, + { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = { + { + .pa_start = 0x4806e000, + .pa_end = 0x4806e0ff, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_wd_timer3_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_wd_timer3_dma_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs), + .user = OCP_USER_SDMA, +}; + +/* wd_timer3 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = { + &omap44xx_l4_abe__wd_timer3, + &omap44xx_l4_abe__wd_timer3_dma, +}; + +static struct omap_hwmod omap44xx_wd_timer3_hwmod = { + .name = "wd_timer3", + .class = &omap44xx_wd_timer_hwmod_class, + .mpu_irqs = omap44xx_wd_timer3_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer3_irqs), + .main_clk = "wd_timer3_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, + }, + }, + .slaves = omap44xx_wd_timer3_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* l4_per -> uart4 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_uart4_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_uart4_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_uart4_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* uart4 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = { + &omap44xx_l4_per__uart4, +}; + +static struct omap_hwmod omap44xx_uart4_hwmod = { + .name = "uart4", + .class = &omap44xx_uart_hwmod_class, + .mpu_irqs = omap44xx_uart4_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart4_irqs), + .sdma_reqs = omap44xx_uart4_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart4_sdma_reqs), + .main_clk = "uart4_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL, + }, + }, + .slaves = omap44xx_uart4_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +static __initdata struct omap_hwmod *omap44xx_hwmods[] = { + /* dmm class */ + &omap44xx_dmm_hwmod, + /* emif_fw class */ + &omap44xx_emif_fw_hwmod, + /* l3 class */ + &omap44xx_l3_instr_hwmod, + &omap44xx_l3_main_1_hwmod, + &omap44xx_l3_main_2_hwmod, + &omap44xx_l3_main_3_hwmod, + /* l4 class */ + &omap44xx_l4_abe_hwmod, + &omap44xx_l4_cfg_hwmod, + &omap44xx_l4_per_hwmod, + &omap44xx_l4_wkup_hwmod, + /* mpu_bus class */ + &omap44xx_mpu_private_hwmod, + + /* mpu class */ + &omap44xx_mpu_hwmod, + /* wd_timer class */ + &omap44xx_wd_timer2_hwmod, + &omap44xx_wd_timer3_hwmod, + + /* uart class */ + &omap44xx_uart1_hwmod, + &omap44xx_uart2_hwmod, + &omap44xx_uart3_hwmod, + &omap44xx_uart4_hwmod, + NULL, +}; + +int __init omap44xx_hwmod_init(void) +{ + return omap_hwmod_init(omap44xx_hwmods); +} + diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c index 723b44e252fd..5e81517a7af2 100644 --- a/arch/arm/mach-omap2/pm-debug.c +++ b/arch/arm/mach-omap2/pm-debug.c @@ -31,12 +31,17 @@ #include <plat/board.h> #include <plat/powerdomain.h> #include <plat/clockdomain.h> +#include <plat/dmtimer.h> #include "prm.h" #include "cm.h" #include "pm.h" int omap2_pm_debug; +u32 enable_off_mode; +u32 sleep_while_idle; +u32 wakeup_timer_seconds; +u32 wakeup_timer_milliseconds; #define DUMP_PRM_MOD_REG(mod, reg) \ regs[reg_count].name = #mod "." #reg; \ @@ -162,7 +167,7 @@ void omap2_pm_dump(int mode, int resume, unsigned int us) static void pm_dbg_regset_store(u32 *ptr); -struct dentry *pm_dbg_dir; +static struct dentry *pm_dbg_dir; static int pm_dbg_init_done; @@ -349,6 +354,23 @@ void pm_dbg_update_time(struct powerdomain *pwrdm, int prev) pwrdm->timer = t; } +void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds) +{ + u32 tick_rate, cycles; + + if (!seconds && !milliseconds) + return; + + tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup)); + cycles = tick_rate * seconds + tick_rate * milliseconds / 1000; + omap_dm_timer_stop(gptimer_wakeup); + omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles); + + pr_info("PM: Resume timer in %u.%03u secs" + " (%d ticks at %d ticks/sec.)\n", + seconds, milliseconds, cycles, tick_rate); +} + static int clkdm_dbg_show_counter(struct clockdomain *clkdm, void *user) { struct seq_file *s = (struct seq_file *)user; @@ -494,8 +516,10 @@ int pm_dbg_regset_init(int reg_set) static int pwrdm_suspend_get(void *data, u64 *val) { - int ret; - ret = omap3_pm_get_suspend_state((struct powerdomain *)data); + int ret = -EINVAL; + + if (cpu_is_omap34xx()) + ret = omap3_pm_get_suspend_state((struct powerdomain *)data); *val = ret; if (ret >= 0) @@ -505,7 +529,10 @@ static int pwrdm_suspend_get(void *data, u64 *val) static int pwrdm_suspend_set(void *data, u64 val) { - return omap3_pm_set_suspend_state((struct powerdomain *)data, (int)val); + if (cpu_is_omap34xx()) + return omap3_pm_set_suspend_state( + (struct powerdomain *)data, (int)val); + return -EINVAL; } DEFINE_SIMPLE_ATTRIBUTE(pwrdm_suspend_fops, pwrdm_suspend_get, @@ -553,8 +580,10 @@ static int option_set(void *data, u64 val) *option = val; - if (option == &enable_off_mode) - omap3_pm_off_mode_enable(val); + if (option == &enable_off_mode) { + if (cpu_is_omap34xx()) + omap3_pm_off_mode_enable(val); + } return 0; } @@ -609,6 +638,9 @@ static int __init pm_dbg_init(void) &sleep_while_idle, &pm_dbg_option_fops); (void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUGO, d, &wakeup_timer_seconds, &pm_dbg_option_fops); + (void) debugfs_create_file("wakeup_timer_milliseconds", + S_IRUGO | S_IWUGO, d, &wakeup_timer_milliseconds, + &pm_dbg_option_fops); pm_dbg_init_done = 1; return 0; diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index 68f9f2e95891..59ca03b0e691 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -18,11 +18,15 @@ #include <plat/omap_device.h> #include <plat/common.h> +#include <plat/powerdomain.h> +#include <plat/clockdomain.h> + static struct omap_device_pm_latency *pm_lats; static struct device *mpu_dev; -static struct device *dsp_dev; +static struct device *iva_dev; static struct device *l3_dev; +static struct device *dsp_dev; struct device *omap2_get_mpuss_device(void) { @@ -30,10 +34,10 @@ struct device *omap2_get_mpuss_device(void) return mpu_dev; } -struct device *omap2_get_dsp_device(void) +struct device *omap2_get_iva_device(void) { - WARN_ON_ONCE(!dsp_dev); - return dsp_dev; + WARN_ON_ONCE(!iva_dev); + return iva_dev; } struct device *omap2_get_l3_device(void) @@ -42,6 +46,13 @@ struct device *omap2_get_l3_device(void) return l3_dev; } +struct device *omap4_get_dsp_device(void) +{ + WARN_ON_ONCE(!dsp_dev); + return dsp_dev; +} +EXPORT_SYMBOL(omap4_get_dsp_device); + /* static int _init_omap_device(struct omap_hwmod *oh, void *user) */ static int _init_omap_device(char *name, struct device **new_dev) { @@ -69,8 +80,60 @@ static int _init_omap_device(char *name, struct device **new_dev) static void omap2_init_processor_devices(void) { _init_omap_device("mpu", &mpu_dev); - _init_omap_device("iva", &dsp_dev); - _init_omap_device("l3_main", &l3_dev); + _init_omap_device("iva", &iva_dev); + if (cpu_is_omap44xx()) { + _init_omap_device("l3_main_1", &l3_dev); + _init_omap_device("dsp", &dsp_dev); + } else { + _init_omap_device("l3_main", &l3_dev); + } +} + +/* + * This sets pwrdm state (other than mpu & core. Currently only ON & + * RET are supported. Function is assuming that clkdm doesn't have + * hw_sup mode enabled. + */ +int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state) +{ + u32 cur_state; + int sleep_switch = 0; + int ret = 0; + + if (pwrdm == NULL || IS_ERR(pwrdm)) + return -EINVAL; + + while (!(pwrdm->pwrsts & (1 << state))) { + if (state == PWRDM_POWER_OFF) + return ret; + state--; + } + + cur_state = pwrdm_read_next_pwrst(pwrdm); + if (cur_state == state) + return ret; + + if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) { + omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]); + sleep_switch = 1; + pwrdm_wait_transition(pwrdm); + } + + ret = pwrdm_set_next_pwrst(pwrdm, state); + if (ret) { + printk(KERN_ERR "Unable to set state of powerdomain: %s\n", + pwrdm->name); + goto err; + } + + if (sleep_switch) { + omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]); + pwrdm_wait_transition(pwrdm); + pwrdm_state_switch(pwrdm); + } + +err: + return ret; } static int __init omap2_common_pm_init(void) diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index 3de6ece23fc8..0d75bfd1fdbe 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h @@ -13,14 +13,11 @@ #include <plat/powerdomain.h> -extern u32 enable_off_mode; -extern u32 sleep_while_idle; - extern void *omap3_secure_ram_storage; extern void omap3_pm_off_mode_enable(int); extern void omap_sram_idle(void); extern int omap3_can_sleep(void); -extern int set_pwrdm_state(struct powerdomain *pwrdm, u32 state); +extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state); extern int omap3_idle_init(void); struct cpuidle_params { @@ -48,10 +45,16 @@ extern struct omap_dm_timer *gptimer_wakeup; #ifdef CONFIG_PM_DEBUG extern void omap2_pm_dump(int mode, int resume, unsigned int us); +extern void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds); extern int omap2_pm_debug; +extern u32 enable_off_mode; +extern u32 sleep_while_idle; #else #define omap2_pm_dump(mode, resume, us) do {} while (0); +#define omap2_pm_wakeup_on_timer(seconds, milliseconds) do {} while (0); #define omap2_pm_debug 0 +#define enable_off_mode 0 +#define sleep_while_idle 0 #endif #if defined(CONFIG_CPU_IDLE) diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index 6aeedeacdad8..a40457d81927 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -38,7 +38,6 @@ #include <mach/irqs.h> #include <plat/clock.h> #include <plat/sram.h> -#include <plat/control.h> #include <plat/dma.h> #include <plat/board.h> @@ -48,6 +47,7 @@ #include "cm-regbits-24xx.h" #include "sdrc.h" #include "pm.h" +#include "control.h" #include <plat/powerdomain.h> #include <plat/clockdomain.h> @@ -245,6 +245,8 @@ static int omap2_can_sleep(void) { if (omap2_fclks_active()) return 0; + if (!omap_uart_can_sleep()) + return 0; if (osc_ck->usecount > 1) return 0; if (omap_dma_running()) diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 7b03426c72a3..75c0cd13ad8e 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -32,13 +32,11 @@ #include <plat/sram.h> #include <plat/clockdomain.h> #include <plat/powerdomain.h> -#include <plat/control.h> #include <plat/serial.h> #include <plat/sdrc.h> #include <plat/prcm.h> #include <plat/gpmc.h> #include <plat/dma.h> -#include <plat/dmtimer.h> #include <asm/tlbflush.h> @@ -49,16 +47,12 @@ #include "prm.h" #include "pm.h" #include "sdrc.h" +#include "control.h" /* Scratchpad offsets */ -#define OMAP343X_TABLE_ADDRESS_OFFSET 0x31 -#define OMAP343X_TABLE_VALUE_OFFSET 0x30 -#define OMAP343X_CONTROL_REG_VALUE_OFFSET 0x32 - -u32 enable_off_mode; -u32 sleep_while_idle; -u32 wakeup_timer_seconds; -u32 wakeup_timer_milliseconds; +#define OMAP343X_TABLE_ADDRESS_OFFSET 0xc4 +#define OMAP343X_TABLE_VALUE_OFFSET 0xc0 +#define OMAP343X_CONTROL_REG_VALUE_OFFSET 0xc8 struct power_state { struct powerdomain *pwrdm; @@ -316,7 +310,7 @@ static void restore_control_register(u32 val) /* Function to restore the table entry that was modified for enabling MMU */ static void restore_table_entry(void) { - u32 *scratchpad_address; + void __iomem *scratchpad_address; u32 previous_value, control_reg_value; u32 *address; @@ -351,7 +345,6 @@ void omap_sram_idle(void) int core_next_state = PWRDM_POWER_ON; int core_prev_state, per_prev_state; u32 sdrc_pwr = 0; - int per_state_modified = 0; if (!_omap_sram_idle) return; @@ -385,9 +378,9 @@ void omap_sram_idle(void) /* Enable IO-PAD and IO-CHAIN wakeups */ per_next_state = pwrdm_read_next_pwrst(per_pwrdm); core_next_state = pwrdm_read_next_pwrst(core_pwrdm); - if (omap3_has_io_wakeup() && \ - (per_next_state < PWRDM_POWER_ON || - core_next_state < PWRDM_POWER_ON)) { + if (omap3_has_io_wakeup() && + (per_next_state < PWRDM_POWER_ON || + core_next_state < PWRDM_POWER_ON)) { prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); omap3_enable_io_chain(); } @@ -395,20 +388,12 @@ void omap_sram_idle(void) /* PER */ if (per_next_state < PWRDM_POWER_ON) { omap_uart_prepare_idle(2); + omap_uart_prepare_idle(3); omap2_gpio_prepare_for_idle(per_next_state); - if (per_next_state == PWRDM_POWER_OFF) { - if (core_next_state == PWRDM_POWER_ON) { - per_next_state = PWRDM_POWER_RET; - pwrdm_set_next_pwrst(per_pwrdm, per_next_state); - per_state_modified = 1; - } else + if (per_next_state == PWRDM_POWER_OFF) omap3_per_save_context(); - } } - if (pwrdm_read_pwrst(cam_pwrdm) == PWRDM_POWER_ON) - omap2_clkdm_deny_idle(mpu_pwrdm->pwrdm_clkdms[0]); - /* CORE */ if (core_next_state < PWRDM_POWER_ON) { omap_uart_prepare_idle(0); @@ -475,8 +460,7 @@ void omap_sram_idle(void) if (per_prev_state == PWRDM_POWER_OFF) omap3_per_restore_context(); omap_uart_resume_idle(2); - if (per_state_modified) - pwrdm_set_next_pwrst(per_pwrdm, PWRDM_POWER_OFF); + omap_uart_resume_idle(3); } /* Disable IO-PAD and IO-CHAIN wakeup */ @@ -501,51 +485,6 @@ int omap3_can_sleep(void) return 1; } -/* This sets pwrdm state (other than mpu & core. Currently only ON & - * RET are supported. Function is assuming that clkdm doesn't have - * hw_sup mode enabled. */ -int set_pwrdm_state(struct powerdomain *pwrdm, u32 state) -{ - u32 cur_state; - int sleep_switch = 0; - int ret = 0; - - if (pwrdm == NULL || IS_ERR(pwrdm)) - return -EINVAL; - - while (!(pwrdm->pwrsts & (1 << state))) { - if (state == PWRDM_POWER_OFF) - return ret; - state--; - } - - cur_state = pwrdm_read_next_pwrst(pwrdm); - if (cur_state == state) - return ret; - - if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) { - omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]); - sleep_switch = 1; - pwrdm_wait_transition(pwrdm); - } - - ret = pwrdm_set_next_pwrst(pwrdm, state); - if (ret) { - printk(KERN_ERR "Unable to set state of powerdomain: %s\n", - pwrdm->name); - goto err; - } - - if (sleep_switch) { - omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]); - pwrdm_wait_transition(pwrdm); - pwrdm_state_switch(pwrdm); - } - -err: - return ret; -} - static void omap3_pm_idle(void) { local_irq_disable(); @@ -567,23 +506,6 @@ out: #ifdef CONFIG_SUSPEND static suspend_state_t suspend_state; -static void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds) -{ - u32 tick_rate, cycles; - - if (!seconds && !milliseconds) - return; - - tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup)); - cycles = tick_rate * seconds + tick_rate * milliseconds / 1000; - omap_dm_timer_stop(gptimer_wakeup); - omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles); - - pr_info("PM: Resume timer in %u.%03u secs" - " (%d ticks at %d ticks/sec.)\n", - seconds, milliseconds, cycles, tick_rate); -} - static int omap3_pm_prepare(void) { disable_hlt(); @@ -604,7 +526,7 @@ static int omap3_pm_suspend(void) pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); /* Set ones wanted by suspend */ list_for_each_entry(pwrst, &pwrst_list, node) { - if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) + if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) goto restore; if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) goto restore; @@ -625,7 +547,7 @@ restore: pwrst->pwrdm->name, pwrst->next_state); ret = -1; } - set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); + omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); } if (ret) printk(KERN_ERR "Could not enter target state in pm_suspend\n"); @@ -756,6 +678,14 @@ static void __init omap3_d2d_idle(void) static void __init prcm_setup_regs(void) { + u32 omap3630_auto_uart4_mask = cpu_is_omap3630() ? + OMAP3630_AUTO_UART4_MASK : 0; + u32 omap3630_en_uart4_mask = cpu_is_omap3630() ? + OMAP3630_EN_UART4_MASK : 0; + u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ? + OMAP3630_GRPSEL_UART4_MASK : 0; + + /* XXX Reset all wkdeps. This should be done when initializing * powerdomains */ prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP); @@ -842,6 +772,7 @@ static void __init prcm_setup_regs(void) CM_AUTOIDLE); cm_write_mod_reg( + omap3630_auto_uart4_mask | OMAP3430_AUTO_GPIO6_MASK | OMAP3430_AUTO_GPIO5_MASK | OMAP3430_AUTO_GPIO4_MASK | @@ -918,14 +849,16 @@ static void __init prcm_setup_regs(void) OMAP3430_DSS_MOD, PM_WKEN); /* Enable wakeups in PER */ - prm_write_mod_reg(OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK | + prm_write_mod_reg(omap3630_en_uart4_mask | + OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK | OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK | OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK | OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK | OMAP3430_EN_MCBSP4_MASK, OMAP3430_PER_MOD, PM_WKEN); /* and allow them to wake up MPU */ - prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2_MASK | + prm_write_mod_reg(omap3630_grpsel_uart4_mask | + OMAP3430_GRPSEL_GPIO2_MASK | OMAP3430_GRPSEL_GPIO3_MASK | OMAP3430_GRPSEL_GPIO4_MASK | OMAP3430_GRPSEL_GPIO5_MASK | @@ -974,7 +907,7 @@ void omap3_pm_off_mode_enable(int enable) list_for_each_entry(pwrst, &pwrst_list, node) { pwrst->next_state = state; - set_pwrdm_state(pwrst->pwrdm, state); + omap_set_pwrdm_state(pwrst->pwrdm, state); } } @@ -1019,7 +952,7 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) if (pwrdm_has_hdwr_sar(pwrdm)) pwrdm_enable_hdwr_sar(pwrdm); - return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); + return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); } /* @@ -1029,9 +962,6 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) */ static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) { - clkdm_clear_all_wkdeps(clkdm); - clkdm_clear_all_sleepdeps(clkdm); - if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) omap2_clkdm_allow_idle(clkdm); else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && diff --git a/arch/arm/mach-omap2/pm_bus.c b/arch/arm/mach-omap2/pm_bus.c new file mode 100644 index 000000000000..784989f8f2f5 --- /dev/null +++ b/arch/arm/mach-omap2/pm_bus.c @@ -0,0 +1,85 @@ +/* + * Runtime PM support code for OMAP + * + * Author: Kevin Hilman, Deep Root Systems, LLC + * + * Copyright (C) 2010 Texas Instruments, Inc. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/io.h> +#include <linux/pm_runtime.h> +#include <linux/platform_device.h> +#include <linux/mutex.h> + +#include <plat/omap_device.h> +#include <plat/omap-pm.h> + +#ifdef CONFIG_PM_RUNTIME +int omap_pm_runtime_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + int r, ret = 0; + + dev_dbg(dev, "%s\n", __func__); + + ret = pm_generic_runtime_suspend(dev); + + if (!ret && dev->parent == &omap_device_parent) { + r = omap_device_idle(pdev); + WARN_ON(r); + } + + return ret; +}; + +int omap_pm_runtime_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + int r; + + dev_dbg(dev, "%s\n", __func__); + + if (dev->parent == &omap_device_parent) { + r = omap_device_enable(pdev); + WARN_ON(r); + } + + return pm_generic_runtime_resume(dev); +}; +#else +#define omap_pm_runtime_suspend NULL +#define omap_pm_runtime_resume NULL +#endif /* CONFIG_PM_RUNTIME */ + +static int __init omap_pm_runtime_init(void) +{ + const struct dev_pm_ops *pm; + struct dev_pm_ops *omap_pm; + + pm = platform_bus_get_pm_ops(); + if (!pm) { + pr_err("%s: unable to get dev_pm_ops from platform_bus\n", + __func__); + return -ENODEV; + } + + omap_pm = kmemdup(pm, sizeof(struct dev_pm_ops), GFP_KERNEL); + if (!omap_pm) { + pr_err("%s: unable to alloc memory for new dev_pm_ops\n", + __func__); + return -ENOMEM; + } + + omap_pm->runtime_suspend = omap_pm_runtime_suspend; + omap_pm->runtime_resume = omap_pm_runtime_resume; + + platform_bus_set_pm_ops(omap_pm); + + return 0; +} +core_initcall(omap_pm_runtime_init); diff --git a/arch/arm/mach-omap2/powerdomains44xx.h b/arch/arm/mach-omap2/powerdomains44xx.h index c7219513472a..9c01b55d6102 100644 --- a/arch/arm/mach-omap2/powerdomains44xx.h +++ b/arch/arm/mach-omap2/powerdomains44xx.h @@ -98,7 +98,7 @@ static struct powerdomain dss_44xx_pwrdm = { .prcm_offs = OMAP4430_PRM_DSS_MOD, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, + .pwrsts_logic_ret = PWRSTS_OFF, .banks = 1, .pwrsts_mem_ret = { [0] = PWRDM_POWER_OFF, /* dss_mem */ diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index 995b7edbf18d..298a22a754e2 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h @@ -382,6 +382,9 @@ #define OMAP3430_EN_MPU_SHIFT 1 /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */ + +#define OMAP3630_EN_UART4_MASK (1 << 18) +#define OMAP3630_EN_UART4_SHIFT 18 #define OMAP3430_EN_GPIO6_MASK (1 << 17) #define OMAP3430_EN_GPIO6_SHIFT 17 #define OMAP3430_EN_GPIO5_MASK (1 << 16) @@ -422,6 +425,8 @@ #define OMAP3430_EN_MCBSP2_SHIFT 0 /* CM_IDLEST_PER, PM_WKST_PER shared bits */ +#define OMAP3630_ST_UART4_SHIFT 18 +#define OMAP3630_ST_UART4_MASK (1 << 18) #define OMAP3430_ST_GPIO6_SHIFT 17 #define OMAP3430_ST_GPIO6_MASK (1 << 17) #define OMAP3430_ST_GPIO5_SHIFT 16 diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c index c20137497c92..a51846e3a6fa 100644 --- a/arch/arm/mach-omap2/prcm.c +++ b/arch/arm/mach-omap2/prcm.c @@ -26,13 +26,14 @@ #include <plat/common.h> #include <plat/prcm.h> #include <plat/irqs.h> -#include <plat/control.h> #include "clock.h" #include "clock2xxx.h" #include "cm.h" #include "prm.h" #include "prm-regbits-24xx.h" +#include "prm-regbits-44xx.h" +#include "control.h" static void __iomem *prm_base; static void __iomem *cm_base; @@ -118,7 +119,7 @@ struct omap3_prcm_regs { u32 wkup_pm_wken; }; -struct omap3_prcm_regs prcm_context; +static struct omap3_prcm_regs prcm_context; u32 omap_prcm_get_reset_sources(void) { @@ -161,8 +162,8 @@ void omap_prcm_arch_reset(char mode, const char *cmd) prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs, OMAP2_RM_RSTCTRL); if (cpu_is_omap44xx()) - prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs, - OMAP4_RM_RSTCTRL); + prm_set_mod_reg_bits(OMAP4430_RST_GLOBAL_WARM_SW_MASK, + prcm_offs, OMAP4_RM_RSTCTRL); } static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg) @@ -215,6 +216,30 @@ u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask) return v; } +/* Read a PRM register, AND it, and shift the result down to bit 0 */ +u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask) +{ + u32 v; + + v = __raw_readl(reg); + v &= mask; + v >>= __ffs(mask); + + return v; +} + +/* Read-modify-write a register in a PRM module. Caller must lock */ +u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg) +{ + u32 v; + + v = __raw_readl(reg); + v &= ~mask; + v |= bits; + __raw_writel(v, reg); + + return v; +} /* Read a register in a CM module */ u32 cm_read_mod_reg(s16 module, u16 idx) { diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h index 7fd6023edf96..9e63cb743a97 100644 --- a/arch/arm/mach-omap2/prm-regbits-34xx.h +++ b/arch/arm/mach-omap2/prm-regbits-34xx.h @@ -122,6 +122,7 @@ #define OMAP3430_MEMRETSTATE_MASK (1 << 8) /* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */ +#define OMAP3630_GRPSEL_UART4_MASK (1 << 18) #define OMAP3430_GRPSEL_GPIO6_MASK (1 << 17) #define OMAP3430_GRPSEL_GPIO5_MASK (1 << 16) #define OMAP3430_GRPSEL_GPIO4_MASK (1 << 15) diff --git a/arch/arm/mach-omap2/prm-regbits-44xx.h b/arch/arm/mach-omap2/prm-regbits-44xx.h index 597be4a2b9ff..25b19b610177 100644 --- a/arch/arm/mach-omap2/prm-regbits-44xx.h +++ b/arch/arm/mach-omap2/prm-regbits-44xx.h @@ -1,8 +1,8 @@ /* * OMAP44xx Power Management register bits * - * Copyright (C) 2009 Texas Instruments, Inc. - * Copyright (C) 2009 Nokia Corporation + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * Copyright (C) 2009-2010 Nokia Corporation * * Paul Walmsley (paul@pwsan.com) * Rajendra Nayak (rnayak@ti.com) @@ -30,587 +30,611 @@ * PRM_LDO_SRAM_MPU_SETUP */ #define OMAP4430_ABBOFF_ACT_EXPORT_SHIFT 1 -#define OMAP4430_ABBOFF_ACT_EXPORT_MASK BITFIELD(1, 1) +#define OMAP4430_ABBOFF_ACT_EXPORT_MASK (1 << 1) /* * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, * PRM_LDO_SRAM_MPU_SETUP */ #define OMAP4430_ABBOFF_SLEEP_EXPORT_SHIFT 2 -#define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK BITFIELD(2, 2) +#define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK (1 << 2) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_ABB_IVA_DONE_EN_SHIFT 31 -#define OMAP4430_ABB_IVA_DONE_EN_MASK BITFIELD(31, 31) +#define OMAP4430_ABB_IVA_DONE_EN_MASK (1 << 31) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_ABB_IVA_DONE_ST_SHIFT 31 -#define OMAP4430_ABB_IVA_DONE_ST_MASK BITFIELD(31, 31) +#define OMAP4430_ABB_IVA_DONE_ST_MASK (1 << 31) /* Used by PRM_IRQENABLE_MPU_2 */ #define OMAP4430_ABB_MPU_DONE_EN_SHIFT 7 -#define OMAP4430_ABB_MPU_DONE_EN_MASK BITFIELD(7, 7) +#define OMAP4430_ABB_MPU_DONE_EN_MASK (1 << 7) /* Used by PRM_IRQSTATUS_MPU_2 */ #define OMAP4430_ABB_MPU_DONE_ST_SHIFT 7 -#define OMAP4430_ABB_MPU_DONE_ST_MASK BITFIELD(7, 7) +#define OMAP4430_ABB_MPU_DONE_ST_MASK (1 << 7) /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ #define OMAP4430_ACTIVE_FBB_SEL_SHIFT 2 -#define OMAP4430_ACTIVE_FBB_SEL_MASK BITFIELD(2, 2) +#define OMAP4430_ACTIVE_FBB_SEL_MASK (1 << 2) /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ #define OMAP4430_ACTIVE_RBB_SEL_SHIFT 1 -#define OMAP4430_ACTIVE_RBB_SEL_MASK BITFIELD(1, 1) +#define OMAP4430_ACTIVE_RBB_SEL_MASK (1 << 1) /* Used by PM_ABE_PWRSTCTRL */ #define OMAP4430_AESSMEM_ONSTATE_SHIFT 16 -#define OMAP4430_AESSMEM_ONSTATE_MASK BITFIELD(16, 17) +#define OMAP4430_AESSMEM_ONSTATE_MASK (0x3 << 16) /* Used by PM_ABE_PWRSTCTRL */ #define OMAP4430_AESSMEM_RETSTATE_SHIFT 8 -#define OMAP4430_AESSMEM_RETSTATE_MASK BITFIELD(8, 8) +#define OMAP4430_AESSMEM_RETSTATE_MASK (1 << 8) /* Used by PM_ABE_PWRSTST */ #define OMAP4430_AESSMEM_STATEST_SHIFT 4 -#define OMAP4430_AESSMEM_STATEST_MASK BITFIELD(4, 5) +#define OMAP4430_AESSMEM_STATEST_MASK (0x3 << 4) /* * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, * PRM_LDO_SRAM_MPU_SETUP */ #define OMAP4430_AIPOFF_SHIFT 8 -#define OMAP4430_AIPOFF_MASK BITFIELD(8, 8) +#define OMAP4430_AIPOFF_MASK (1 << 8) /* Used by PRM_VOLTCTRL */ #define OMAP4430_AUTO_CTRL_VDD_CORE_L_SHIFT 0 -#define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK BITFIELD(0, 1) +#define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK (0x3 << 0) /* Used by PRM_VOLTCTRL */ #define OMAP4430_AUTO_CTRL_VDD_IVA_L_SHIFT 4 -#define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK BITFIELD(4, 5) +#define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK (0x3 << 4) /* Used by PRM_VOLTCTRL */ #define OMAP4430_AUTO_CTRL_VDD_MPU_L_SHIFT 2 -#define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK BITFIELD(2, 3) +#define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK (0x3 << 2) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_BYPS_RA_ERR_SHIFT 25 +#define OMAP4430_BYPS_RA_ERR_MASK (1 << 25) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_BYPS_SA_ERR_SHIFT 24 +#define OMAP4430_BYPS_SA_ERR_MASK (1 << 24) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_BYPS_TIMEOUT_ERR_SHIFT 26 +#define OMAP4430_BYPS_TIMEOUT_ERR_MASK (1 << 26) + +/* Used by PRM_RSTST */ +#define OMAP4430_C2C_RST_SHIFT 10 +#define OMAP4430_C2C_RST_MASK (1 << 10) /* Used by PM_CAM_PWRSTCTRL */ #define OMAP4430_CAM_MEM_ONSTATE_SHIFT 16 -#define OMAP4430_CAM_MEM_ONSTATE_MASK BITFIELD(16, 17) +#define OMAP4430_CAM_MEM_ONSTATE_MASK (0x3 << 16) /* Used by PM_CAM_PWRSTST */ #define OMAP4430_CAM_MEM_STATEST_SHIFT 4 -#define OMAP4430_CAM_MEM_STATEST_MASK BITFIELD(4, 5) +#define OMAP4430_CAM_MEM_STATEST_MASK (0x3 << 4) /* Used by PRM_CLKREQCTRL */ #define OMAP4430_CLKREQ_COND_SHIFT 0 -#define OMAP4430_CLKREQ_COND_MASK BITFIELD(0, 2) +#define OMAP4430_CLKREQ_COND_MASK (0x7 << 0) /* Used by PRM_VC_VAL_SMPS_RA_CMD */ #define OMAP4430_CMDRA_VDD_CORE_L_SHIFT 0 -#define OMAP4430_CMDRA_VDD_CORE_L_MASK BITFIELD(0, 7) +#define OMAP4430_CMDRA_VDD_CORE_L_MASK (0xff << 0) /* Used by PRM_VC_VAL_SMPS_RA_CMD */ #define OMAP4430_CMDRA_VDD_IVA_L_SHIFT 8 -#define OMAP4430_CMDRA_VDD_IVA_L_MASK BITFIELD(8, 15) +#define OMAP4430_CMDRA_VDD_IVA_L_MASK (0xff << 8) /* Used by PRM_VC_VAL_SMPS_RA_CMD */ #define OMAP4430_CMDRA_VDD_MPU_L_SHIFT 16 -#define OMAP4430_CMDRA_VDD_MPU_L_MASK BITFIELD(16, 23) +#define OMAP4430_CMDRA_VDD_MPU_L_MASK (0xff << 16) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_CMD_VDD_CORE_L_SHIFT 4 -#define OMAP4430_CMD_VDD_CORE_L_MASK BITFIELD(4, 4) +#define OMAP4430_CMD_VDD_CORE_L_MASK (1 << 4) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_CMD_VDD_IVA_L_SHIFT 12 -#define OMAP4430_CMD_VDD_IVA_L_MASK BITFIELD(12, 12) +#define OMAP4430_CMD_VDD_IVA_L_MASK (1 << 12) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_CMD_VDD_MPU_L_SHIFT 17 -#define OMAP4430_CMD_VDD_MPU_L_MASK BITFIELD(17, 17) +#define OMAP4430_CMD_VDD_MPU_L_MASK (1 << 17) /* Used by PM_CORE_PWRSTCTRL */ #define OMAP4430_CORE_OCMRAM_ONSTATE_SHIFT 18 -#define OMAP4430_CORE_OCMRAM_ONSTATE_MASK BITFIELD(18, 19) +#define OMAP4430_CORE_OCMRAM_ONSTATE_MASK (0x3 << 18) /* Used by PM_CORE_PWRSTCTRL */ #define OMAP4430_CORE_OCMRAM_RETSTATE_SHIFT 9 -#define OMAP4430_CORE_OCMRAM_RETSTATE_MASK BITFIELD(9, 9) +#define OMAP4430_CORE_OCMRAM_RETSTATE_MASK (1 << 9) /* Used by PM_CORE_PWRSTST */ #define OMAP4430_CORE_OCMRAM_STATEST_SHIFT 6 -#define OMAP4430_CORE_OCMRAM_STATEST_MASK BITFIELD(6, 7) +#define OMAP4430_CORE_OCMRAM_STATEST_MASK (0x3 << 6) /* Used by PM_CORE_PWRSTCTRL */ #define OMAP4430_CORE_OTHER_BANK_ONSTATE_SHIFT 16 -#define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK BITFIELD(16, 17) +#define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK (0x3 << 16) /* Used by PM_CORE_PWRSTCTRL */ #define OMAP4430_CORE_OTHER_BANK_RETSTATE_SHIFT 8 -#define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK BITFIELD(8, 8) +#define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK (1 << 8) /* Used by PM_CORE_PWRSTST */ #define OMAP4430_CORE_OTHER_BANK_STATEST_SHIFT 4 -#define OMAP4430_CORE_OTHER_BANK_STATEST_MASK BITFIELD(4, 5) +#define OMAP4430_CORE_OTHER_BANK_STATEST_MASK (0x3 << 4) + +/* Used by REVISION_PRM */ +#define OMAP4430_CUSTOM_SHIFT 6 +#define OMAP4430_CUSTOM_MASK (0x3 << 6) /* Used by PRM_VC_VAL_BYPASS */ #define OMAP4430_DATA_SHIFT 16 -#define OMAP4430_DATA_MASK BITFIELD(16, 23) +#define OMAP4430_DATA_MASK (0xff << 16) /* Used by PRM_DEVICE_OFF_CTRL */ #define OMAP4430_DEVICE_OFF_ENABLE_SHIFT 0 -#define OMAP4430_DEVICE_OFF_ENABLE_MASK BITFIELD(0, 0) +#define OMAP4430_DEVICE_OFF_ENABLE_MASK (1 << 0) /* Used by PRM_VC_CFG_I2C_MODE */ #define OMAP4430_DFILTEREN_SHIFT 6 -#define OMAP4430_DFILTEREN_MASK BITFIELD(6, 6) +#define OMAP4430_DFILTEREN_MASK (1 << 6) -/* Used by PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ +/* + * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, + * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP + */ +#define OMAP4430_DISABLE_RTA_EXPORT_SHIFT 0 +#define OMAP4430_DISABLE_RTA_EXPORT_MASK (1 << 0) + +/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ #define OMAP4430_DPLL_ABE_RECAL_EN_SHIFT 4 -#define OMAP4430_DPLL_ABE_RECAL_EN_MASK BITFIELD(4, 4) +#define OMAP4430_DPLL_ABE_RECAL_EN_MASK (1 << 4) -/* Used by PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ +/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ #define OMAP4430_DPLL_ABE_RECAL_ST_SHIFT 4 -#define OMAP4430_DPLL_ABE_RECAL_ST_MASK BITFIELD(4, 4) +#define OMAP4430_DPLL_ABE_RECAL_ST_MASK (1 << 4) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_DPLL_CORE_RECAL_EN_SHIFT 0 -#define OMAP4430_DPLL_CORE_RECAL_EN_MASK BITFIELD(0, 0) +#define OMAP4430_DPLL_CORE_RECAL_EN_MASK (1 << 0) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_DPLL_CORE_RECAL_ST_SHIFT 0 -#define OMAP4430_DPLL_CORE_RECAL_ST_MASK BITFIELD(0, 0) +#define OMAP4430_DPLL_CORE_RECAL_ST_MASK (1 << 0) /* Used by PRM_IRQENABLE_MPU */ #define OMAP4430_DPLL_DDRPHY_RECAL_EN_SHIFT 6 -#define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK BITFIELD(6, 6) +#define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK (1 << 6) /* Used by PRM_IRQSTATUS_MPU */ #define OMAP4430_DPLL_DDRPHY_RECAL_ST_SHIFT 6 -#define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK BITFIELD(6, 6) +#define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK (1 << 6) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ #define OMAP4430_DPLL_IVA_RECAL_EN_SHIFT 2 -#define OMAP4430_DPLL_IVA_RECAL_EN_MASK BITFIELD(2, 2) +#define OMAP4430_DPLL_IVA_RECAL_EN_MASK (1 << 2) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ #define OMAP4430_DPLL_IVA_RECAL_ST_SHIFT 2 -#define OMAP4430_DPLL_IVA_RECAL_ST_MASK BITFIELD(2, 2) +#define OMAP4430_DPLL_IVA_RECAL_ST_MASK (1 << 2) /* Used by PRM_IRQENABLE_MPU */ #define OMAP4430_DPLL_MPU_RECAL_EN_SHIFT 1 -#define OMAP4430_DPLL_MPU_RECAL_EN_MASK BITFIELD(1, 1) +#define OMAP4430_DPLL_MPU_RECAL_EN_MASK (1 << 1) /* Used by PRM_IRQSTATUS_MPU */ #define OMAP4430_DPLL_MPU_RECAL_ST_SHIFT 1 -#define OMAP4430_DPLL_MPU_RECAL_ST_MASK BITFIELD(1, 1) +#define OMAP4430_DPLL_MPU_RECAL_ST_MASK (1 << 1) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_DPLL_PER_RECAL_EN_SHIFT 3 -#define OMAP4430_DPLL_PER_RECAL_EN_MASK BITFIELD(3, 3) +#define OMAP4430_DPLL_PER_RECAL_EN_MASK (1 << 3) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_DPLL_PER_RECAL_ST_SHIFT 3 -#define OMAP4430_DPLL_PER_RECAL_ST_MASK BITFIELD(3, 3) +#define OMAP4430_DPLL_PER_RECAL_ST_MASK (1 << 3) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_DPLL_UNIPRO_RECAL_EN_SHIFT 7 -#define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK BITFIELD(7, 7) +#define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK (1 << 7) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_DPLL_UNIPRO_RECAL_ST_SHIFT 7 -#define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK BITFIELD(7, 7) - -/* Used by PRM_IRQENABLE_MPU */ -#define OMAP4430_DPLL_USB_RECAL_EN_SHIFT 5 -#define OMAP4430_DPLL_USB_RECAL_EN_MASK BITFIELD(5, 5) - -/* Used by PRM_IRQSTATUS_MPU */ -#define OMAP4430_DPLL_USB_RECAL_ST_SHIFT 5 -#define OMAP4430_DPLL_USB_RECAL_ST_MASK BITFIELD(5, 5) +#define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK (1 << 7) /* Used by PM_DSS_PWRSTCTRL */ #define OMAP4430_DSS_MEM_ONSTATE_SHIFT 16 -#define OMAP4430_DSS_MEM_ONSTATE_MASK BITFIELD(16, 17) +#define OMAP4430_DSS_MEM_ONSTATE_MASK (0x3 << 16) /* Used by PM_DSS_PWRSTCTRL */ #define OMAP4430_DSS_MEM_RETSTATE_SHIFT 8 -#define OMAP4430_DSS_MEM_RETSTATE_MASK BITFIELD(8, 8) +#define OMAP4430_DSS_MEM_RETSTATE_MASK (1 << 8) /* Used by PM_DSS_PWRSTST */ #define OMAP4430_DSS_MEM_STATEST_SHIFT 4 -#define OMAP4430_DSS_MEM_STATEST_MASK BITFIELD(4, 5) +#define OMAP4430_DSS_MEM_STATEST_MASK (0x3 << 4) /* Used by PM_CORE_PWRSTCTRL */ #define OMAP4430_DUCATI_L2RAM_ONSTATE_SHIFT 20 -#define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK BITFIELD(20, 21) +#define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK (0x3 << 20) /* Used by PM_CORE_PWRSTCTRL */ #define OMAP4430_DUCATI_L2RAM_RETSTATE_SHIFT 10 -#define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK BITFIELD(10, 10) +#define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK (1 << 10) /* Used by PM_CORE_PWRSTST */ #define OMAP4430_DUCATI_L2RAM_STATEST_SHIFT 8 -#define OMAP4430_DUCATI_L2RAM_STATEST_MASK BITFIELD(8, 9) +#define OMAP4430_DUCATI_L2RAM_STATEST_MASK (0x3 << 8) /* Used by PM_CORE_PWRSTCTRL */ #define OMAP4430_DUCATI_UNICACHE_ONSTATE_SHIFT 22 -#define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK BITFIELD(22, 23) +#define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK (0x3 << 22) /* Used by PM_CORE_PWRSTCTRL */ #define OMAP4430_DUCATI_UNICACHE_RETSTATE_SHIFT 11 -#define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK BITFIELD(11, 11) +#define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK (1 << 11) /* Used by PM_CORE_PWRSTST */ #define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT 10 -#define OMAP4430_DUCATI_UNICACHE_STATEST_MASK BITFIELD(10, 11) +#define OMAP4430_DUCATI_UNICACHE_STATEST_MASK (0x3 << 10) /* Used by RM_MPU_RSTST */ #define OMAP4430_EMULATION_RST_SHIFT 0 -#define OMAP4430_EMULATION_RST_MASK BITFIELD(0, 0) +#define OMAP4430_EMULATION_RST_MASK (1 << 0) /* Used by RM_DUCATI_RSTST */ #define OMAP4430_EMULATION_RST1ST_SHIFT 3 -#define OMAP4430_EMULATION_RST1ST_MASK BITFIELD(3, 3) +#define OMAP4430_EMULATION_RST1ST_MASK (1 << 3) /* Used by RM_DUCATI_RSTST */ #define OMAP4430_EMULATION_RST2ST_SHIFT 4 -#define OMAP4430_EMULATION_RST2ST_MASK BITFIELD(4, 4) +#define OMAP4430_EMULATION_RST2ST_MASK (1 << 4) /* Used by RM_IVAHD_RSTST */ #define OMAP4430_EMULATION_SEQ1_RST1ST_SHIFT 3 -#define OMAP4430_EMULATION_SEQ1_RST1ST_MASK BITFIELD(3, 3) +#define OMAP4430_EMULATION_SEQ1_RST1ST_MASK (1 << 3) /* Used by RM_IVAHD_RSTST */ #define OMAP4430_EMULATION_SEQ2_RST2ST_SHIFT 4 -#define OMAP4430_EMULATION_SEQ2_RST2ST_MASK BITFIELD(4, 4) +#define OMAP4430_EMULATION_SEQ2_RST2ST_MASK (1 << 4) /* Used by PM_EMU_PWRSTCTRL */ #define OMAP4430_EMU_BANK_ONSTATE_SHIFT 16 -#define OMAP4430_EMU_BANK_ONSTATE_MASK BITFIELD(16, 17) +#define OMAP4430_EMU_BANK_ONSTATE_MASK (0x3 << 16) /* Used by PM_EMU_PWRSTST */ #define OMAP4430_EMU_BANK_STATEST_SHIFT 4 -#define OMAP4430_EMU_BANK_STATEST_MASK BITFIELD(4, 5) - -/* - * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, - * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP - */ -#define OMAP4430_ENABLE_RTA_EXPORT_SHIFT 0 -#define OMAP4430_ENABLE_RTA_EXPORT_MASK BITFIELD(0, 0) +#define OMAP4430_EMU_BANK_STATEST_MASK (0x3 << 4) /* * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, * PRM_LDO_SRAM_MPU_SETUP */ -#define OMAP4430_ENFUNC1_SHIFT 3 -#define OMAP4430_ENFUNC1_MASK BITFIELD(3, 3) +#define OMAP4430_ENFUNC1_EXPORT_SHIFT 3 +#define OMAP4430_ENFUNC1_EXPORT_MASK (1 << 3) /* * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, * PRM_LDO_SRAM_MPU_SETUP */ -#define OMAP4430_ENFUNC3_SHIFT 5 -#define OMAP4430_ENFUNC3_MASK BITFIELD(5, 5) +#define OMAP4430_ENFUNC3_EXPORT_SHIFT 5 +#define OMAP4430_ENFUNC3_EXPORT_MASK (1 << 5) /* * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, * PRM_LDO_SRAM_MPU_SETUP */ #define OMAP4430_ENFUNC4_SHIFT 6 -#define OMAP4430_ENFUNC4_MASK BITFIELD(6, 6) +#define OMAP4430_ENFUNC4_MASK (1 << 6) /* * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, * PRM_LDO_SRAM_MPU_SETUP */ #define OMAP4430_ENFUNC5_SHIFT 7 -#define OMAP4430_ENFUNC5_MASK BITFIELD(7, 7) +#define OMAP4430_ENFUNC5_MASK (1 << 7) /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ #define OMAP4430_ERRORGAIN_SHIFT 16 -#define OMAP4430_ERRORGAIN_MASK BITFIELD(16, 23) +#define OMAP4430_ERRORGAIN_MASK (0xff << 16) /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ #define OMAP4430_ERROROFFSET_SHIFT 24 -#define OMAP4430_ERROROFFSET_MASK BITFIELD(24, 31) +#define OMAP4430_ERROROFFSET_MASK (0xff << 24) /* Used by PRM_RSTST */ #define OMAP4430_EXTERNAL_WARM_RST_SHIFT 5 -#define OMAP4430_EXTERNAL_WARM_RST_MASK BITFIELD(5, 5) +#define OMAP4430_EXTERNAL_WARM_RST_MASK (1 << 5) /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ #define OMAP4430_FORCEUPDATE_SHIFT 1 -#define OMAP4430_FORCEUPDATE_MASK BITFIELD(1, 1) +#define OMAP4430_FORCEUPDATE_MASK (1 << 1) /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */ #define OMAP4430_FORCEUPDATEWAIT_SHIFT 8 -#define OMAP4430_FORCEUPDATEWAIT_MASK BITFIELD(8, 31) +#define OMAP4430_FORCEUPDATEWAIT_MASK (0xffffff << 8) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_TESLA */ #define OMAP4430_FORCEWKUP_EN_SHIFT 10 -#define OMAP4430_FORCEWKUP_EN_MASK BITFIELD(10, 10) +#define OMAP4430_FORCEWKUP_EN_MASK (1 << 10) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_TESLA */ #define OMAP4430_FORCEWKUP_ST_SHIFT 10 -#define OMAP4430_FORCEWKUP_ST_MASK BITFIELD(10, 10) +#define OMAP4430_FORCEWKUP_ST_MASK (1 << 10) + +/* Used by REVISION_PRM */ +#define OMAP4430_FUNC_SHIFT 16 +#define OMAP4430_FUNC_MASK (0xfff << 16) /* Used by PM_GFX_PWRSTCTRL */ #define OMAP4430_GFX_MEM_ONSTATE_SHIFT 16 -#define OMAP4430_GFX_MEM_ONSTATE_MASK BITFIELD(16, 17) +#define OMAP4430_GFX_MEM_ONSTATE_MASK (0x3 << 16) /* Used by PM_GFX_PWRSTST */ #define OMAP4430_GFX_MEM_STATEST_SHIFT 4 -#define OMAP4430_GFX_MEM_STATEST_MASK BITFIELD(4, 5) +#define OMAP4430_GFX_MEM_STATEST_MASK (0x3 << 4) /* Used by PRM_RSTST */ #define OMAP4430_GLOBAL_COLD_RST_SHIFT 0 -#define OMAP4430_GLOBAL_COLD_RST_MASK BITFIELD(0, 0) +#define OMAP4430_GLOBAL_COLD_RST_MASK (1 << 0) /* Used by PRM_RSTST */ #define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT 1 -#define OMAP4430_GLOBAL_WARM_SW_RST_MASK BITFIELD(1, 1) +#define OMAP4430_GLOBAL_WARM_SW_RST_MASK (1 << 1) /* Used by PRM_IO_PMCTRL */ #define OMAP4430_GLOBAL_WUEN_SHIFT 16 -#define OMAP4430_GLOBAL_WUEN_MASK BITFIELD(16, 16) +#define OMAP4430_GLOBAL_WUEN_MASK (1 << 16) /* Used by PRM_VC_CFG_I2C_MODE */ #define OMAP4430_HSMCODE_SHIFT 0 -#define OMAP4430_HSMCODE_MASK BITFIELD(0, 2) +#define OMAP4430_HSMCODE_MASK (0x7 << 0) /* Used by PRM_VC_CFG_I2C_MODE */ #define OMAP4430_HSMODEEN_SHIFT 3 -#define OMAP4430_HSMODEEN_MASK BITFIELD(3, 3) +#define OMAP4430_HSMODEEN_MASK (1 << 3) /* Used by PRM_VC_CFG_I2C_CLK */ #define OMAP4430_HSSCLH_SHIFT 16 -#define OMAP4430_HSSCLH_MASK BITFIELD(16, 23) +#define OMAP4430_HSSCLH_MASK (0xff << 16) /* Used by PRM_VC_CFG_I2C_CLK */ #define OMAP4430_HSSCLL_SHIFT 24 -#define OMAP4430_HSSCLL_MASK BITFIELD(24, 31) +#define OMAP4430_HSSCLL_MASK (0xff << 24) /* Used by PM_IVAHD_PWRSTCTRL */ #define OMAP4430_HWA_MEM_ONSTATE_SHIFT 16 -#define OMAP4430_HWA_MEM_ONSTATE_MASK BITFIELD(16, 17) +#define OMAP4430_HWA_MEM_ONSTATE_MASK (0x3 << 16) /* Used by PM_IVAHD_PWRSTCTRL */ #define OMAP4430_HWA_MEM_RETSTATE_SHIFT 8 -#define OMAP4430_HWA_MEM_RETSTATE_MASK BITFIELD(8, 8) +#define OMAP4430_HWA_MEM_RETSTATE_MASK (1 << 8) /* Used by PM_IVAHD_PWRSTST */ #define OMAP4430_HWA_MEM_STATEST_SHIFT 4 -#define OMAP4430_HWA_MEM_STATEST_MASK BITFIELD(4, 5) +#define OMAP4430_HWA_MEM_STATEST_MASK (0x3 << 4) /* Used by RM_MPU_RSTST */ #define OMAP4430_ICECRUSHER_MPU_RST_SHIFT 1 -#define OMAP4430_ICECRUSHER_MPU_RST_MASK BITFIELD(1, 1) +#define OMAP4430_ICECRUSHER_MPU_RST_MASK (1 << 1) /* Used by RM_DUCATI_RSTST */ #define OMAP4430_ICECRUSHER_RST1ST_SHIFT 5 -#define OMAP4430_ICECRUSHER_RST1ST_MASK BITFIELD(5, 5) +#define OMAP4430_ICECRUSHER_RST1ST_MASK (1 << 5) /* Used by RM_DUCATI_RSTST */ #define OMAP4430_ICECRUSHER_RST2ST_SHIFT 6 -#define OMAP4430_ICECRUSHER_RST2ST_MASK BITFIELD(6, 6) +#define OMAP4430_ICECRUSHER_RST2ST_MASK (1 << 6) /* Used by RM_IVAHD_RSTST */ #define OMAP4430_ICECRUSHER_SEQ1_RST1ST_SHIFT 5 -#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK BITFIELD(5, 5) +#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK (1 << 5) /* Used by RM_IVAHD_RSTST */ #define OMAP4430_ICECRUSHER_SEQ2_RST2ST_SHIFT 6 -#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK BITFIELD(6, 6) +#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK (1 << 6) /* Used by PRM_RSTST */ #define OMAP4430_ICEPICK_RST_SHIFT 9 -#define OMAP4430_ICEPICK_RST_MASK BITFIELD(9, 9) +#define OMAP4430_ICEPICK_RST_MASK (1 << 9) /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ #define OMAP4430_INITVDD_SHIFT 2 -#define OMAP4430_INITVDD_MASK BITFIELD(2, 2) +#define OMAP4430_INITVDD_MASK (1 << 2) /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ #define OMAP4430_INITVOLTAGE_SHIFT 8 -#define OMAP4430_INITVOLTAGE_MASK BITFIELD(8, 15) +#define OMAP4430_INITVOLTAGE_MASK (0xff << 8) /* - * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST, - * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST, - * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST + * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST, + * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST, + * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST */ #define OMAP4430_INTRANSITION_SHIFT 20 -#define OMAP4430_INTRANSITION_MASK BITFIELD(20, 20) +#define OMAP4430_INTRANSITION_MASK (1 << 20) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_IO_EN_SHIFT 9 -#define OMAP4430_IO_EN_MASK BITFIELD(9, 9) +#define OMAP4430_IO_EN_MASK (1 << 9) /* Used by PRM_IO_PMCTRL */ #define OMAP4430_IO_ON_STATUS_SHIFT 5 -#define OMAP4430_IO_ON_STATUS_MASK BITFIELD(5, 5) +#define OMAP4430_IO_ON_STATUS_MASK (1 << 5) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_IO_ST_SHIFT 9 -#define OMAP4430_IO_ST_MASK BITFIELD(9, 9) +#define OMAP4430_IO_ST_MASK (1 << 9) /* Used by PRM_IO_PMCTRL */ #define OMAP4430_ISOCLK_OVERRIDE_SHIFT 0 -#define OMAP4430_ISOCLK_OVERRIDE_MASK BITFIELD(0, 0) +#define OMAP4430_ISOCLK_OVERRIDE_MASK (1 << 0) /* Used by PRM_IO_PMCTRL */ #define OMAP4430_ISOCLK_STATUS_SHIFT 1 -#define OMAP4430_ISOCLK_STATUS_MASK BITFIELD(1, 1) +#define OMAP4430_ISOCLK_STATUS_MASK (1 << 1) /* Used by PRM_IO_PMCTRL */ #define OMAP4430_ISOOVR_EXTEND_SHIFT 4 -#define OMAP4430_ISOOVR_EXTEND_MASK BITFIELD(4, 4) +#define OMAP4430_ISOOVR_EXTEND_MASK (1 << 4) /* Used by PRM_IO_COUNT */ #define OMAP4430_ISO_2_ON_TIME_SHIFT 0 -#define OMAP4430_ISO_2_ON_TIME_MASK BITFIELD(0, 7) +#define OMAP4430_ISO_2_ON_TIME_MASK (0xff << 0) /* Used by PM_L3INIT_PWRSTCTRL */ #define OMAP4430_L3INIT_BANK1_ONSTATE_SHIFT 16 -#define OMAP4430_L3INIT_BANK1_ONSTATE_MASK BITFIELD(16, 17) +#define OMAP4430_L3INIT_BANK1_ONSTATE_MASK (0x3 << 16) /* Used by PM_L3INIT_PWRSTCTRL */ #define OMAP4430_L3INIT_BANK1_RETSTATE_SHIFT 8 -#define OMAP4430_L3INIT_BANK1_RETSTATE_MASK BITFIELD(8, 8) +#define OMAP4430_L3INIT_BANK1_RETSTATE_MASK (1 << 8) /* Used by PM_L3INIT_PWRSTST */ #define OMAP4430_L3INIT_BANK1_STATEST_SHIFT 4 -#define OMAP4430_L3INIT_BANK1_STATEST_MASK BITFIELD(4, 5) +#define OMAP4430_L3INIT_BANK1_STATEST_MASK (0x3 << 4) + +/* + * Used by PM_ABE_PWRSTST, PM_CORE_PWRSTST, PM_IVAHD_PWRSTST, + * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST + */ +#define OMAP4430_LASTPOWERSTATEENTERED_SHIFT 24 +#define OMAP4430_LASTPOWERSTATEENTERED_MASK (0x3 << 24) /* - * Used by PM_CORE_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_ABE_PWRSTCTRL, - * PM_MPU_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_TESLA_PWRSTCTRL, - * PM_IVAHD_PWRSTCTRL + * Used by PM_ABE_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, + * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, + * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL */ #define OMAP4430_LOGICRETSTATE_SHIFT 2 -#define OMAP4430_LOGICRETSTATE_MASK BITFIELD(2, 2) +#define OMAP4430_LOGICRETSTATE_MASK (1 << 2) /* - * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST, - * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST, - * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST + * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST, + * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST, + * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST */ #define OMAP4430_LOGICSTATEST_SHIFT 2 -#define OMAP4430_LOGICSTATEST_MASK BITFIELD(2, 2) +#define OMAP4430_LOGICSTATEST_MASK (1 << 2) /* - * Used by RM_WKUP_GPIO1_CONTEXT, RM_WKUP_KEYBOARD_CONTEXT, - * RM_WKUP_L4WKUP_CONTEXT, RM_WKUP_RTC_CONTEXT, RM_WKUP_SARRAM_CONTEXT, - * RM_WKUP_SYNCTIMER_CONTEXT, RM_WKUP_TIMER12_CONTEXT, RM_WKUP_TIMER1_CONTEXT, - * RM_WKUP_USIM_CONTEXT, RM_WKUP_WDT1_CONTEXT, RM_WKUP_WDT2_CONTEXT, - * RM_EMU_DEBUGSS_CONTEXT, RM_D2D_SAD2D_CONTEXT, RM_D2D_SAD2D_FW_CONTEXT, - * RM_DUCATI_DUCATI_CONTEXT, RM_L3INSTR_L3_3_CONTEXT, - * RM_L3INSTR_L3_INSTR_CONTEXT, RM_L3INSTR_OCP_WP1_CONTEXT, - * RM_L3_1_L3_1_CONTEXT, RM_L3_2_L3_2_CONTEXT, RM_L3_2_OCMC_RAM_CONTEXT, - * RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_SAR_ROM_CONTEXT, RM_MEMIF_DLL_CONTEXT, - * RM_MEMIF_DLL_H_CONTEXT, RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_FW_CONTEXT, - * RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT, RM_L3INIT_CCPTX_CONTEXT, - * RM_L3INIT_EMAC_CONTEXT, RM_L3INIT_P1500_CONTEXT, RM_L3INIT_PCIESS_CONTEXT, - * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT, - * RM_L3INIT_USBPHYOCP2SCP_CONTEXT, RM_L3INIT_XHPI_CONTEXT, - * RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT, + * Used by RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT, * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT, * RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT, RM_ABE_TIMER5_CONTEXT, * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT, - * RM_ABE_WDT3_CONTEXT, RM_GFX_GFX_CONTEXT, RM_MPU_MPU_CONTEXT, - * RM_CEFUSE_CEFUSE_CONTEXT, RM_ALWON_MDMINTC_CONTEXT, - * RM_ALWON_SR_CORE_CONTEXT, RM_ALWON_SR_IVA_CONTEXT, RM_ALWON_SR_MPU_CONTEXT, - * RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT, RM_L4PER_ADC_CONTEXT, - * RM_L4PER_DMTIMER10_CONTEXT, RM_L4PER_DMTIMER11_CONTEXT, - * RM_L4PER_DMTIMER2_CONTEXT, RM_L4PER_DMTIMER3_CONTEXT, - * RM_L4PER_DMTIMER4_CONTEXT, RM_L4PER_DMTIMER9_CONTEXT, RM_L4PER_ELM_CONTEXT, - * RM_L4PER_HDQ1W_CONTEXT, RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, - * RM_L4PER_I2C2_CONTEXT, RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT, - * RM_L4PER_I2C5_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCASP2_CONTEXT, - * RM_L4PER_MCASP3_CONTEXT, RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MCSPI1_CONTEXT, - * RM_L4PER_MCSPI2_CONTEXT, RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT, - * RM_L4PER_MGATE_CONTEXT, RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, - * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_MSPROHG_CONTEXT, - * RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT, - * RM_TESLA_TESLA_CONTEXT, RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT + * RM_ABE_WDT3_CONTEXT, RM_ALWON_MDMINTC_CONTEXT, RM_ALWON_SR_CORE_CONTEXT, + * RM_ALWON_SR_IVA_CONTEXT, RM_ALWON_SR_MPU_CONTEXT, RM_CAM_FDIF_CONTEXT, + * RM_CAM_ISS_CONTEXT, RM_CEFUSE_CEFUSE_CONTEXT, RM_D2D_SAD2D_CONTEXT, + * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT, + * RM_DUCATI_DUCATI_CONTEXT, RM_EMU_DEBUGSS_CONTEXT, RM_GFX_GFX_CONTEXT, + * RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT, RM_L3INIT_CCPTX_CONTEXT, + * RM_L3INIT_EMAC_CONTEXT, RM_L3INIT_P1500_CONTEXT, RM_L3INIT_PCIESS_CONTEXT, + * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT, + * RM_L3INIT_USBPHYOCP2SCP_CONTEXT, RM_L3INIT_XHPI_CONTEXT, + * RM_L3INSTR_L3_3_CONTEXT, RM_L3INSTR_L3_INSTR_CONTEXT, + * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_L3_2_CONTEXT, + * RM_L3_2_OCMC_RAM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_SAR_ROM_CONTEXT, + * RM_L4PER_ADC_CONTEXT, RM_L4PER_DMTIMER10_CONTEXT, + * RM_L4PER_DMTIMER11_CONTEXT, RM_L4PER_DMTIMER2_CONTEXT, + * RM_L4PER_DMTIMER3_CONTEXT, RM_L4PER_DMTIMER4_CONTEXT, + * RM_L4PER_DMTIMER9_CONTEXT, RM_L4PER_ELM_CONTEXT, RM_L4PER_HDQ1W_CONTEXT, + * RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, RM_L4PER_I2C2_CONTEXT, + * RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT, RM_L4PER_I2C5_CONTEXT, + * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCASP2_CONTEXT, RM_L4PER_MCASP3_CONTEXT, + * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MCSPI1_CONTEXT, RM_L4PER_MCSPI2_CONTEXT, + * RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT, RM_L4PER_MGATE_CONTEXT, + * RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, RM_L4PER_MMCSD5_CONTEXT, + * RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, + * RM_L4SEC_PKAEIP29_CONTEXT, RM_MEMIF_DLL_CONTEXT, RM_MEMIF_DLL_H_CONTEXT, + * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT, + * RM_MEMIF_EMIF_FW_CONTEXT, RM_MPU_MPU_CONTEXT, RM_TESLA_TESLA_CONTEXT, + * RM_WKUP_GPIO1_CONTEXT, RM_WKUP_KEYBOARD_CONTEXT, RM_WKUP_L4WKUP_CONTEXT, + * RM_WKUP_RTC_CONTEXT, RM_WKUP_SARRAM_CONTEXT, RM_WKUP_SYNCTIMER_CONTEXT, + * RM_WKUP_TIMER12_CONTEXT, RM_WKUP_TIMER1_CONTEXT, RM_WKUP_USIM_CONTEXT, + * RM_WKUP_WDT1_CONTEXT, RM_WKUP_WDT2_CONTEXT */ #define OMAP4430_LOSTCONTEXT_DFF_SHIFT 0 -#define OMAP4430_LOSTCONTEXT_DFF_MASK BITFIELD(0, 0) +#define OMAP4430_LOSTCONTEXT_DFF_MASK (1 << 0) /* * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_D2D_SAD2D_CONTEXT, - * RM_D2D_SAD2D_FW_CONTEXT, RM_DUCATI_DUCATI_CONTEXT, RM_L3INSTR_L3_3_CONTEXT, + * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DSS_CONTEXT, RM_DUCATI_DUCATI_CONTEXT, + * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, + * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_USB_HOST_CONTEXT, + * RM_L3INIT_USB_HOST_FS_CONTEXT, RM_L3INIT_USB_OTG_CONTEXT, + * RM_L3INIT_USB_TLL_CONTEXT, RM_L3INSTR_L3_3_CONTEXT, * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_GPMC_CONTEXT, * RM_L3_2_L3_2_CONTEXT, RM_L4CFG_HW_SEM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT, - * RM_L4CFG_MAILBOX_CONTEXT, RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, - * RM_MEMIF_EMIF_2_CONTEXT, RM_MEMIF_EMIF_FW_CONTEXT, RM_MEMIF_EMIF_H1_CONTEXT, - * RM_MEMIF_EMIF_H2_CONTEXT, RM_SDMA_SDMA_CONTEXT, RM_L3INIT_HSI_CONTEXT, - * RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, RM_L3INIT_MMC6_CONTEXT, - * RM_L3INIT_USB_HOST_CONTEXT, RM_L3INIT_USB_HOST_FS_CONTEXT, - * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_USB_TLL_CONTEXT, RM_DSS_DSS_CONTEXT, - * RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT, RM_L4PER_GPIO4_CONTEXT, - * RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT, RM_L4PER_I2C1_CONTEXT, - * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT, - * RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4SEC_AES1_CONTEXT, - * RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT, RM_L4SEC_DES3DES_CONTEXT, - * RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT, RM_TESLA_TESLA_CONTEXT + * RM_L4CFG_MAILBOX_CONTEXT, RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT, + * RM_L4PER_GPIO4_CONTEXT, RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT, + * RM_L4PER_I2C1_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT, + * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, + * RM_L4SEC_AES1_CONTEXT, RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT, + * RM_L4SEC_DES3DES_CONTEXT, RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT, + * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT, + * RM_MEMIF_EMIF_FW_CONTEXT, RM_MEMIF_EMIF_H1_CONTEXT, + * RM_MEMIF_EMIF_H2_CONTEXT, RM_SDMA_SDMA_CONTEXT, RM_TESLA_TESLA_CONTEXT */ #define OMAP4430_LOSTCONTEXT_RFF_SHIFT 1 -#define OMAP4430_LOSTCONTEXT_RFF_MASK BITFIELD(1, 1) +#define OMAP4430_LOSTCONTEXT_RFF_MASK (1 << 1) /* Used by RM_ABE_AESS_CONTEXT */ #define OMAP4430_LOSTMEM_AESSMEM_SHIFT 8 -#define OMAP4430_LOSTMEM_AESSMEM_MASK BITFIELD(8, 8) +#define OMAP4430_LOSTMEM_AESSMEM_MASK (1 << 8) /* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */ #define OMAP4430_LOSTMEM_CAM_MEM_SHIFT 8 -#define OMAP4430_LOSTMEM_CAM_MEM_MASK BITFIELD(8, 8) +#define OMAP4430_LOSTMEM_CAM_MEM_MASK (1 << 8) /* Used by RM_L3INSTR_OCP_WP1_CONTEXT */ #define OMAP4430_LOSTMEM_CORE_NRET_BANK_SHIFT 8 -#define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK BITFIELD(8, 8) +#define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK (1 << 8) /* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_MEMIF_DMM_CONTEXT */ #define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_SHIFT 9 -#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK BITFIELD(9, 9) +#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK (1 << 9) /* Used by RM_L3_2_OCMC_RAM_CONTEXT */ #define OMAP4430_LOSTMEM_CORE_OCMRAM_SHIFT 8 -#define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK BITFIELD(8, 8) +#define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK (1 << 8) /* * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_MEMIF_DMM_CONTEXT, * RM_SDMA_SDMA_CONTEXT */ #define OMAP4430_LOSTMEM_CORE_OTHER_BANK_SHIFT 8 -#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK BITFIELD(8, 8) +#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK (1 << 8) /* Used by RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT */ #define OMAP4430_LOSTMEM_DSS_MEM_SHIFT 8 -#define OMAP4430_LOSTMEM_DSS_MEM_MASK BITFIELD(8, 8) +#define OMAP4430_LOSTMEM_DSS_MEM_MASK (1 << 8) /* Used by RM_DUCATI_DUCATI_CONTEXT */ #define OMAP4430_LOSTMEM_DUCATI_L2RAM_SHIFT 9 -#define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK BITFIELD(9, 9) +#define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK (1 << 9) /* Used by RM_DUCATI_DUCATI_CONTEXT */ #define OMAP4430_LOSTMEM_DUCATI_UNICACHE_SHIFT 8 -#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK BITFIELD(8, 8) +#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK (1 << 8) /* Used by RM_EMU_DEBUGSS_CONTEXT */ #define OMAP4430_LOSTMEM_EMU_BANK_SHIFT 8 -#define OMAP4430_LOSTMEM_EMU_BANK_MASK BITFIELD(8, 8) +#define OMAP4430_LOSTMEM_EMU_BANK_MASK (1 << 8) /* Used by RM_GFX_GFX_CONTEXT */ #define OMAP4430_LOSTMEM_GFX_MEM_SHIFT 8 -#define OMAP4430_LOSTMEM_GFX_MEM_MASK BITFIELD(8, 8) +#define OMAP4430_LOSTMEM_GFX_MEM_MASK (1 << 8) /* Used by RM_IVAHD_IVAHD_CONTEXT */ #define OMAP4430_LOSTMEM_HWA_MEM_SHIFT 10 -#define OMAP4430_LOSTMEM_HWA_MEM_MASK BITFIELD(10, 10) +#define OMAP4430_LOSTMEM_HWA_MEM_MASK (1 << 10) /* * Used by RM_L3INIT_CCPTX_CONTEXT, RM_L3INIT_EMAC_CONTEXT, @@ -620,19 +644,19 @@ * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_XHPI_CONTEXT */ #define OMAP4430_LOSTMEM_L3INIT_BANK1_SHIFT 8 -#define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK BITFIELD(8, 8) +#define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK (1 << 8) /* Used by RM_MPU_MPU_CONTEXT */ #define OMAP4430_LOSTMEM_MPU_L1_SHIFT 8 -#define OMAP4430_LOSTMEM_MPU_L1_MASK BITFIELD(8, 8) +#define OMAP4430_LOSTMEM_MPU_L1_MASK (1 << 8) /* Used by RM_MPU_MPU_CONTEXT */ #define OMAP4430_LOSTMEM_MPU_L2_SHIFT 9 -#define OMAP4430_LOSTMEM_MPU_L2_MASK BITFIELD(9, 9) +#define OMAP4430_LOSTMEM_MPU_L2_MASK (1 << 9) /* Used by RM_MPU_MPU_CONTEXT */ #define OMAP4430_LOSTMEM_MPU_RAM_SHIFT 10 -#define OMAP4430_LOSTMEM_MPU_RAM_MASK BITFIELD(10, 10) +#define OMAP4430_LOSTMEM_MPU_RAM_MASK (1 << 10) /* * Used by RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, @@ -640,14 +664,14 @@ * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT */ #define OMAP4430_LOSTMEM_NONRETAINED_BANK_SHIFT 8 -#define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK BITFIELD(8, 8) +#define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK (1 << 8) /* * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, * RM_ABE_MCBSP3_CONTEXT, RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT */ #define OMAP4430_LOSTMEM_PERIHPMEM_SHIFT 8 -#define OMAP4430_LOSTMEM_PERIHPMEM_MASK BITFIELD(8, 8) +#define OMAP4430_LOSTMEM_PERIHPMEM_MASK (1 << 8) /* * Used by RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_UART1_CONTEXT, @@ -655,245 +679,237 @@ * RM_L4SEC_CRYPTODMA_CONTEXT */ #define OMAP4430_LOSTMEM_RETAINED_BANK_SHIFT 8 -#define OMAP4430_LOSTMEM_RETAINED_BANK_MASK BITFIELD(8, 8) +#define OMAP4430_LOSTMEM_RETAINED_BANK_MASK (1 << 8) /* Used by RM_IVAHD_SL2_CONTEXT */ #define OMAP4430_LOSTMEM_SL2_MEM_SHIFT 8 -#define OMAP4430_LOSTMEM_SL2_MEM_MASK BITFIELD(8, 8) +#define OMAP4430_LOSTMEM_SL2_MEM_MASK (1 << 8) /* Used by RM_IVAHD_IVAHD_CONTEXT */ #define OMAP4430_LOSTMEM_TCM1_MEM_SHIFT 8 -#define OMAP4430_LOSTMEM_TCM1_MEM_MASK BITFIELD(8, 8) +#define OMAP4430_LOSTMEM_TCM1_MEM_MASK (1 << 8) /* Used by RM_IVAHD_IVAHD_CONTEXT */ #define OMAP4430_LOSTMEM_TCM2_MEM_SHIFT 9 -#define OMAP4430_LOSTMEM_TCM2_MEM_MASK BITFIELD(9, 9) +#define OMAP4430_LOSTMEM_TCM2_MEM_MASK (1 << 9) /* Used by RM_TESLA_TESLA_CONTEXT */ #define OMAP4430_LOSTMEM_TESLA_EDMA_SHIFT 10 -#define OMAP4430_LOSTMEM_TESLA_EDMA_MASK BITFIELD(10, 10) +#define OMAP4430_LOSTMEM_TESLA_EDMA_MASK (1 << 10) /* Used by RM_TESLA_TESLA_CONTEXT */ #define OMAP4430_LOSTMEM_TESLA_L1_SHIFT 8 -#define OMAP4430_LOSTMEM_TESLA_L1_MASK BITFIELD(8, 8) +#define OMAP4430_LOSTMEM_TESLA_L1_MASK (1 << 8) /* Used by RM_TESLA_TESLA_CONTEXT */ #define OMAP4430_LOSTMEM_TESLA_L2_SHIFT 9 -#define OMAP4430_LOSTMEM_TESLA_L2_MASK BITFIELD(9, 9) +#define OMAP4430_LOSTMEM_TESLA_L2_MASK (1 << 9) /* Used by RM_WKUP_SARRAM_CONTEXT */ #define OMAP4430_LOSTMEM_WKUP_BANK_SHIFT 8 -#define OMAP4430_LOSTMEM_WKUP_BANK_MASK BITFIELD(8, 8) +#define OMAP4430_LOSTMEM_WKUP_BANK_MASK (1 << 8) /* - * Used by PM_CORE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, - * PM_ABE_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, - * PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_TESLA_PWRSTCTRL, PM_IVAHD_PWRSTCTRL + * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, + * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_IVAHD_PWRSTCTRL, + * PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL */ #define OMAP4430_LOWPOWERSTATECHANGE_SHIFT 4 -#define OMAP4430_LOWPOWERSTATECHANGE_MASK BITFIELD(4, 4) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_MEMORYCHANGE_SHIFT 3 -#define OMAP4430_MEMORYCHANGE_MASK BITFIELD(3, 3) +#define OMAP4430_LOWPOWERSTATECHANGE_MASK (1 << 4) /* Used by PRM_MODEM_IF_CTRL */ #define OMAP4430_MODEM_READY_SHIFT 1 -#define OMAP4430_MODEM_READY_MASK BITFIELD(1, 1) +#define OMAP4430_MODEM_READY_MASK (1 << 1) /* Used by PRM_MODEM_IF_CTRL */ #define OMAP4430_MODEM_SHUTDOWN_IRQ_SHIFT 9 -#define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK BITFIELD(9, 9) +#define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK (1 << 9) /* Used by PRM_MODEM_IF_CTRL */ #define OMAP4430_MODEM_SLEEP_ST_SHIFT 16 -#define OMAP4430_MODEM_SLEEP_ST_MASK BITFIELD(16, 16) +#define OMAP4430_MODEM_SLEEP_ST_MASK (1 << 16) /* Used by PRM_MODEM_IF_CTRL */ #define OMAP4430_MODEM_WAKE_IRQ_SHIFT 8 -#define OMAP4430_MODEM_WAKE_IRQ_MASK BITFIELD(8, 8) +#define OMAP4430_MODEM_WAKE_IRQ_MASK (1 << 8) /* Used by PM_MPU_PWRSTCTRL */ #define OMAP4430_MPU_L1_ONSTATE_SHIFT 16 -#define OMAP4430_MPU_L1_ONSTATE_MASK BITFIELD(16, 17) +#define OMAP4430_MPU_L1_ONSTATE_MASK (0x3 << 16) /* Used by PM_MPU_PWRSTCTRL */ #define OMAP4430_MPU_L1_RETSTATE_SHIFT 8 -#define OMAP4430_MPU_L1_RETSTATE_MASK BITFIELD(8, 8) +#define OMAP4430_MPU_L1_RETSTATE_MASK (1 << 8) /* Used by PM_MPU_PWRSTST */ #define OMAP4430_MPU_L1_STATEST_SHIFT 4 -#define OMAP4430_MPU_L1_STATEST_MASK BITFIELD(4, 5) +#define OMAP4430_MPU_L1_STATEST_MASK (0x3 << 4) /* Used by PM_MPU_PWRSTCTRL */ #define OMAP4430_MPU_L2_ONSTATE_SHIFT 18 -#define OMAP4430_MPU_L2_ONSTATE_MASK BITFIELD(18, 19) +#define OMAP4430_MPU_L2_ONSTATE_MASK (0x3 << 18) /* Used by PM_MPU_PWRSTCTRL */ #define OMAP4430_MPU_L2_RETSTATE_SHIFT 9 -#define OMAP4430_MPU_L2_RETSTATE_MASK BITFIELD(9, 9) +#define OMAP4430_MPU_L2_RETSTATE_MASK (1 << 9) /* Used by PM_MPU_PWRSTST */ #define OMAP4430_MPU_L2_STATEST_SHIFT 6 -#define OMAP4430_MPU_L2_STATEST_MASK BITFIELD(6, 7) +#define OMAP4430_MPU_L2_STATEST_MASK (0x3 << 6) /* Used by PM_MPU_PWRSTCTRL */ #define OMAP4430_MPU_RAM_ONSTATE_SHIFT 20 -#define OMAP4430_MPU_RAM_ONSTATE_MASK BITFIELD(20, 21) +#define OMAP4430_MPU_RAM_ONSTATE_MASK (0x3 << 20) /* Used by PM_MPU_PWRSTCTRL */ #define OMAP4430_MPU_RAM_RETSTATE_SHIFT 10 -#define OMAP4430_MPU_RAM_RETSTATE_MASK BITFIELD(10, 10) +#define OMAP4430_MPU_RAM_RETSTATE_MASK (1 << 10) /* Used by PM_MPU_PWRSTST */ #define OMAP4430_MPU_RAM_STATEST_SHIFT 8 -#define OMAP4430_MPU_RAM_STATEST_MASK BITFIELD(8, 9) +#define OMAP4430_MPU_RAM_STATEST_MASK (0x3 << 8) /* Used by PRM_RSTST */ #define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT 2 -#define OMAP4430_MPU_SECURITY_VIOL_RST_MASK BITFIELD(2, 2) +#define OMAP4430_MPU_SECURITY_VIOL_RST_MASK (1 << 2) /* Used by PRM_RSTST */ #define OMAP4430_MPU_WDT_RST_SHIFT 3 -#define OMAP4430_MPU_WDT_RST_MASK BITFIELD(3, 3) +#define OMAP4430_MPU_WDT_RST_MASK (1 << 3) /* Used by PM_L4PER_PWRSTCTRL */ #define OMAP4430_NONRETAINED_BANK_ONSTATE_SHIFT 18 -#define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK BITFIELD(18, 19) +#define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK (0x3 << 18) /* Used by PM_L4PER_PWRSTCTRL */ #define OMAP4430_NONRETAINED_BANK_RETSTATE_SHIFT 9 -#define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK BITFIELD(9, 9) +#define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK (1 << 9) /* Used by PM_L4PER_PWRSTST */ #define OMAP4430_NONRETAINED_BANK_STATEST_SHIFT 6 -#define OMAP4430_NONRETAINED_BANK_STATEST_MASK BITFIELD(6, 7) +#define OMAP4430_NONRETAINED_BANK_STATEST_MASK (0x3 << 6) /* Used by PM_CORE_PWRSTCTRL */ #define OMAP4430_OCP_NRET_BANK_ONSTATE_SHIFT 24 -#define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK BITFIELD(24, 25) +#define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK (0x3 << 24) /* Used by PM_CORE_PWRSTCTRL */ #define OMAP4430_OCP_NRET_BANK_RETSTATE_SHIFT 12 -#define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK BITFIELD(12, 12) +#define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK (1 << 12) /* Used by PM_CORE_PWRSTST */ #define OMAP4430_OCP_NRET_BANK_STATEST_SHIFT 12 -#define OMAP4430_OCP_NRET_BANK_STATEST_MASK BITFIELD(12, 13) +#define OMAP4430_OCP_NRET_BANK_STATEST_MASK (0x3 << 12) /* * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, * PRM_VC_VAL_CMD_VDD_MPU_L */ #define OMAP4430_OFF_SHIFT 0 -#define OMAP4430_OFF_MASK BITFIELD(0, 7) - -/* Used by PRM_LDO_BANDGAP_CTRL */ -#define OMAP4430_OFF_ENABLE_SHIFT 0 -#define OMAP4430_OFF_ENABLE_MASK BITFIELD(0, 0) +#define OMAP4430_OFF_MASK (0xff << 0) /* * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, * PRM_VC_VAL_CMD_VDD_MPU_L */ #define OMAP4430_ON_SHIFT 24 -#define OMAP4430_ON_MASK BITFIELD(24, 31) +#define OMAP4430_ON_MASK (0xff << 24) /* * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, * PRM_VC_VAL_CMD_VDD_MPU_L */ #define OMAP4430_ONLP_SHIFT 16 -#define OMAP4430_ONLP_MASK BITFIELD(16, 23) +#define OMAP4430_ONLP_MASK (0xff << 16) /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ #define OMAP4430_OPP_CHANGE_SHIFT 2 -#define OMAP4430_OPP_CHANGE_MASK BITFIELD(2, 2) +#define OMAP4430_OPP_CHANGE_MASK (1 << 2) /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ #define OMAP4430_OPP_SEL_SHIFT 0 -#define OMAP4430_OPP_SEL_MASK BITFIELD(0, 1) +#define OMAP4430_OPP_SEL_MASK (0x3 << 0) /* Used by PRM_SRAM_COUNT */ #define OMAP4430_PCHARGECNT_VALUE_SHIFT 0 -#define OMAP4430_PCHARGECNT_VALUE_MASK BITFIELD(0, 5) +#define OMAP4430_PCHARGECNT_VALUE_MASK (0x3f << 0) /* Used by PRM_PSCON_COUNT */ #define OMAP4430_PCHARGE_TIME_SHIFT 0 -#define OMAP4430_PCHARGE_TIME_MASK BITFIELD(0, 7) +#define OMAP4430_PCHARGE_TIME_MASK (0xff << 0) /* Used by PM_ABE_PWRSTCTRL */ #define OMAP4430_PERIPHMEM_ONSTATE_SHIFT 20 -#define OMAP4430_PERIPHMEM_ONSTATE_MASK BITFIELD(20, 21) +#define OMAP4430_PERIPHMEM_ONSTATE_MASK (0x3 << 20) /* Used by PM_ABE_PWRSTCTRL */ #define OMAP4430_PERIPHMEM_RETSTATE_SHIFT 10 -#define OMAP4430_PERIPHMEM_RETSTATE_MASK BITFIELD(10, 10) +#define OMAP4430_PERIPHMEM_RETSTATE_MASK (1 << 10) /* Used by PM_ABE_PWRSTST */ #define OMAP4430_PERIPHMEM_STATEST_SHIFT 8 -#define OMAP4430_PERIPHMEM_STATEST_MASK BITFIELD(8, 9) +#define OMAP4430_PERIPHMEM_STATEST_MASK (0x3 << 8) /* Used by PRM_PHASE1_CNDP */ #define OMAP4430_PHASE1_CNDP_SHIFT 0 -#define OMAP4430_PHASE1_CNDP_MASK BITFIELD(0, 31) +#define OMAP4430_PHASE1_CNDP_MASK (0xffffffff << 0) /* Used by PRM_PHASE2A_CNDP */ #define OMAP4430_PHASE2A_CNDP_SHIFT 0 -#define OMAP4430_PHASE2A_CNDP_MASK BITFIELD(0, 31) +#define OMAP4430_PHASE2A_CNDP_MASK (0xffffffff << 0) /* Used by PRM_PHASE2B_CNDP */ #define OMAP4430_PHASE2B_CNDP_SHIFT 0 -#define OMAP4430_PHASE2B_CNDP_MASK BITFIELD(0, 31) +#define OMAP4430_PHASE2B_CNDP_MASK (0xffffffff << 0) /* Used by PRM_PSCON_COUNT */ #define OMAP4430_PONOUT_2_PGOODIN_TIME_SHIFT 8 -#define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK BITFIELD(8, 15) +#define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK (0xff << 8) /* - * Used by PM_EMU_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_CAM_PWRSTCTRL, - * PM_L3INIT_PWRSTCTRL, PM_ABE_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, - * PM_CEFUSE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, - * PM_TESLA_PWRSTCTRL, PM_IVAHD_PWRSTCTRL + * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, + * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_EMU_PWRSTCTRL, PM_GFX_PWRSTCTRL, + * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, + * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL */ #define OMAP4430_POWERSTATE_SHIFT 0 -#define OMAP4430_POWERSTATE_MASK BITFIELD(0, 1) +#define OMAP4430_POWERSTATE_MASK (0x3 << 0) /* - * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST, - * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST, - * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST + * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST, + * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST, + * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST */ #define OMAP4430_POWERSTATEST_SHIFT 0 -#define OMAP4430_POWERSTATEST_MASK BITFIELD(0, 1) +#define OMAP4430_POWERSTATEST_MASK (0x3 << 0) /* Used by PRM_PWRREQCTRL */ #define OMAP4430_PWRREQ_COND_SHIFT 0 -#define OMAP4430_PWRREQ_COND_MASK BITFIELD(0, 1) +#define OMAP4430_PWRREQ_COND_MASK (0x3 << 0) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_RACEN_VDD_CORE_L_SHIFT 3 -#define OMAP4430_RACEN_VDD_CORE_L_MASK BITFIELD(3, 3) +#define OMAP4430_RACEN_VDD_CORE_L_MASK (1 << 3) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_RACEN_VDD_IVA_L_SHIFT 11 -#define OMAP4430_RACEN_VDD_IVA_L_MASK BITFIELD(11, 11) +#define OMAP4430_RACEN_VDD_IVA_L_MASK (1 << 11) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_RACEN_VDD_MPU_L_SHIFT 20 -#define OMAP4430_RACEN_VDD_MPU_L_MASK BITFIELD(20, 20) +#define OMAP4430_RACEN_VDD_MPU_L_MASK (1 << 20) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_RAC_VDD_CORE_L_SHIFT 2 -#define OMAP4430_RAC_VDD_CORE_L_MASK BITFIELD(2, 2) +#define OMAP4430_RAC_VDD_CORE_L_MASK (1 << 2) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_RAC_VDD_IVA_L_SHIFT 10 -#define OMAP4430_RAC_VDD_IVA_L_MASK BITFIELD(10, 10) +#define OMAP4430_RAC_VDD_IVA_L_MASK (1 << 10) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_RAC_VDD_MPU_L_SHIFT 19 -#define OMAP4430_RAC_VDD_MPU_L_MASK BITFIELD(19, 19) +#define OMAP4430_RAC_VDD_MPU_L_MASK (1 << 19) /* * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, @@ -901,7 +917,7 @@ * PRM_VOLTSETUP_MPU_RET_SLEEP */ #define OMAP4430_RAMP_DOWN_COUNT_SHIFT 16 -#define OMAP4430_RAMP_DOWN_COUNT_MASK BITFIELD(16, 21) +#define OMAP4430_RAMP_DOWN_COUNT_MASK (0x3f << 16) /* * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, @@ -909,7 +925,7 @@ * PRM_VOLTSETUP_MPU_RET_SLEEP */ #define OMAP4430_RAMP_DOWN_PRESCAL_SHIFT 24 -#define OMAP4430_RAMP_DOWN_PRESCAL_MASK BITFIELD(24, 25) +#define OMAP4430_RAMP_DOWN_PRESCAL_MASK (0x3 << 24) /* * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, @@ -917,7 +933,7 @@ * PRM_VOLTSETUP_MPU_RET_SLEEP */ #define OMAP4430_RAMP_UP_COUNT_SHIFT 0 -#define OMAP4430_RAMP_UP_COUNT_MASK BITFIELD(0, 5) +#define OMAP4430_RAMP_UP_COUNT_MASK (0x3f << 0) /* * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, @@ -925,1281 +941,1381 @@ * PRM_VOLTSETUP_MPU_RET_SLEEP */ #define OMAP4430_RAMP_UP_PRESCAL_SHIFT 8 -#define OMAP4430_RAMP_UP_PRESCAL_MASK BITFIELD(8, 9) +#define OMAP4430_RAMP_UP_PRESCAL_MASK (0x3 << 8) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_RAV_VDD_CORE_L_SHIFT 1 -#define OMAP4430_RAV_VDD_CORE_L_MASK BITFIELD(1, 1) +#define OMAP4430_RAV_VDD_CORE_L_MASK (1 << 1) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_RAV_VDD_IVA_L_SHIFT 9 -#define OMAP4430_RAV_VDD_IVA_L_MASK BITFIELD(9, 9) +#define OMAP4430_RAV_VDD_IVA_L_MASK (1 << 9) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_RAV_VDD_MPU_L_SHIFT 18 -#define OMAP4430_RAV_VDD_MPU_L_MASK BITFIELD(18, 18) +#define OMAP4430_RAV_VDD_MPU_L_MASK (1 << 18) /* Used by PRM_VC_VAL_BYPASS */ #define OMAP4430_REGADDR_SHIFT 8 -#define OMAP4430_REGADDR_MASK BITFIELD(8, 15) +#define OMAP4430_REGADDR_MASK (0xff << 8) /* * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, * PRM_VC_VAL_CMD_VDD_MPU_L */ #define OMAP4430_RET_SHIFT 8 -#define OMAP4430_RET_MASK BITFIELD(8, 15) +#define OMAP4430_RET_MASK (0xff << 8) /* Used by PM_L4PER_PWRSTCTRL */ #define OMAP4430_RETAINED_BANK_ONSTATE_SHIFT 16 -#define OMAP4430_RETAINED_BANK_ONSTATE_MASK BITFIELD(16, 17) +#define OMAP4430_RETAINED_BANK_ONSTATE_MASK (0x3 << 16) /* Used by PM_L4PER_PWRSTCTRL */ #define OMAP4430_RETAINED_BANK_RETSTATE_SHIFT 8 -#define OMAP4430_RETAINED_BANK_RETSTATE_MASK BITFIELD(8, 8) +#define OMAP4430_RETAINED_BANK_RETSTATE_MASK (1 << 8) /* Used by PM_L4PER_PWRSTST */ #define OMAP4430_RETAINED_BANK_STATEST_SHIFT 4 -#define OMAP4430_RETAINED_BANK_STATEST_MASK BITFIELD(4, 5) +#define OMAP4430_RETAINED_BANK_STATEST_MASK (0x3 << 4) /* * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, * PRM_LDO_SRAM_MPU_CTRL */ #define OMAP4430_RETMODE_ENABLE_SHIFT 0 -#define OMAP4430_RETMODE_ENABLE_MASK BITFIELD(0, 0) +#define OMAP4430_RETMODE_ENABLE_MASK (1 << 0) -/* Used by REVISION_PRM */ -#define OMAP4430_REV_SHIFT 0 -#define OMAP4430_REV_MASK BITFIELD(0, 7) - -/* Used by RM_DUCATI_RSTCTRL, RM_TESLA_RSTCTRL, RM_IVAHD_RSTCTRL */ +/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */ #define OMAP4430_RST1_SHIFT 0 -#define OMAP4430_RST1_MASK BITFIELD(0, 0) +#define OMAP4430_RST1_MASK (1 << 0) -/* Used by RM_DUCATI_RSTST, RM_TESLA_RSTST, RM_IVAHD_RSTST */ +/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */ #define OMAP4430_RST1ST_SHIFT 0 -#define OMAP4430_RST1ST_MASK BITFIELD(0, 0) +#define OMAP4430_RST1ST_MASK (1 << 0) -/* Used by RM_DUCATI_RSTCTRL, RM_TESLA_RSTCTRL, RM_IVAHD_RSTCTRL */ +/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */ #define OMAP4430_RST2_SHIFT 1 -#define OMAP4430_RST2_MASK BITFIELD(1, 1) +#define OMAP4430_RST2_MASK (1 << 1) -/* Used by RM_DUCATI_RSTST, RM_TESLA_RSTST, RM_IVAHD_RSTST */ +/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */ #define OMAP4430_RST2ST_SHIFT 1 -#define OMAP4430_RST2ST_MASK BITFIELD(1, 1) +#define OMAP4430_RST2ST_MASK (1 << 1) /* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL */ #define OMAP4430_RST3_SHIFT 2 -#define OMAP4430_RST3_MASK BITFIELD(2, 2) +#define OMAP4430_RST3_MASK (1 << 2) /* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST */ #define OMAP4430_RST3ST_SHIFT 2 -#define OMAP4430_RST3ST_MASK BITFIELD(2, 2) +#define OMAP4430_RST3ST_MASK (1 << 2) /* Used by PRM_RSTTIME */ #define OMAP4430_RSTTIME1_SHIFT 0 -#define OMAP4430_RSTTIME1_MASK BITFIELD(0, 9) +#define OMAP4430_RSTTIME1_MASK (0x3ff << 0) /* Used by PRM_RSTTIME */ #define OMAP4430_RSTTIME2_SHIFT 10 -#define OMAP4430_RSTTIME2_MASK BITFIELD(10, 14) +#define OMAP4430_RSTTIME2_MASK (0x1f << 10) /* Used by PRM_RSTCTRL */ #define OMAP4430_RST_GLOBAL_COLD_SW_SHIFT 1 -#define OMAP4430_RST_GLOBAL_COLD_SW_MASK BITFIELD(1, 1) +#define OMAP4430_RST_GLOBAL_COLD_SW_MASK (1 << 1) /* Used by PRM_RSTCTRL */ #define OMAP4430_RST_GLOBAL_WARM_SW_SHIFT 0 -#define OMAP4430_RST_GLOBAL_WARM_SW_MASK BITFIELD(0, 0) +#define OMAP4430_RST_GLOBAL_WARM_SW_MASK (1 << 0) + +/* Used by REVISION_PRM */ +#define OMAP4430_R_RTL_SHIFT 11 +#define OMAP4430_R_RTL_MASK (0x1f << 11) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_SA_VDD_CORE_L_SHIFT 0 -#define OMAP4430_SA_VDD_CORE_L_MASK BITFIELD(0, 0) +#define OMAP4430_SA_VDD_CORE_L_MASK (1 << 0) /* Renamed from SA_VDD_CORE_L Used by PRM_VC_SMPS_SA */ #define OMAP4430_SA_VDD_CORE_L_0_6_SHIFT 0 -#define OMAP4430_SA_VDD_CORE_L_0_6_MASK BITFIELD(0, 6) +#define OMAP4430_SA_VDD_CORE_L_0_6_MASK (0x7f << 0) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_SA_VDD_IVA_L_SHIFT 8 -#define OMAP4430_SA_VDD_IVA_L_MASK BITFIELD(8, 8) +#define OMAP4430_SA_VDD_IVA_L_MASK (1 << 8) /* Renamed from SA_VDD_IVA_L Used by PRM_VC_SMPS_SA */ #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT 8 -#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK BITFIELD(8, 14) +#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK (0x7f << 8) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_SA_VDD_MPU_L_SHIFT 16 -#define OMAP4430_SA_VDD_MPU_L_MASK BITFIELD(16, 16) +#define OMAP4430_SA_VDD_MPU_L_MASK (1 << 16) /* Renamed from SA_VDD_MPU_L Used by PRM_VC_SMPS_SA */ #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT 16 -#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK BITFIELD(16, 22) +#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK (0x7f << 16) + +/* Used by REVISION_PRM */ +#define OMAP4430_SCHEME_SHIFT 30 +#define OMAP4430_SCHEME_MASK (0x3 << 30) /* Used by PRM_VC_CFG_I2C_CLK */ #define OMAP4430_SCLH_SHIFT 0 -#define OMAP4430_SCLH_MASK BITFIELD(0, 7) +#define OMAP4430_SCLH_MASK (0xff << 0) /* Used by PRM_VC_CFG_I2C_CLK */ #define OMAP4430_SCLL_SHIFT 8 -#define OMAP4430_SCLL_MASK BITFIELD(8, 15) +#define OMAP4430_SCLL_MASK (0xff << 8) /* Used by PRM_RSTST */ #define OMAP4430_SECURE_WDT_RST_SHIFT 4 -#define OMAP4430_SECURE_WDT_RST_MASK BITFIELD(4, 4) +#define OMAP4430_SECURE_WDT_RST_MASK (1 << 4) /* Used by PM_IVAHD_PWRSTCTRL */ #define OMAP4430_SL2_MEM_ONSTATE_SHIFT 18 -#define OMAP4430_SL2_MEM_ONSTATE_MASK BITFIELD(18, 19) +#define OMAP4430_SL2_MEM_ONSTATE_MASK (0x3 << 18) /* Used by PM_IVAHD_PWRSTCTRL */ #define OMAP4430_SL2_MEM_RETSTATE_SHIFT 9 -#define OMAP4430_SL2_MEM_RETSTATE_MASK BITFIELD(9, 9) +#define OMAP4430_SL2_MEM_RETSTATE_MASK (1 << 9) /* Used by PM_IVAHD_PWRSTST */ #define OMAP4430_SL2_MEM_STATEST_SHIFT 6 -#define OMAP4430_SL2_MEM_STATEST_MASK BITFIELD(6, 7) +#define OMAP4430_SL2_MEM_STATEST_MASK (0x3 << 6) /* Used by PRM_VC_VAL_BYPASS */ #define OMAP4430_SLAVEADDR_SHIFT 0 -#define OMAP4430_SLAVEADDR_MASK BITFIELD(0, 6) +#define OMAP4430_SLAVEADDR_MASK (0x7f << 0) /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ #define OMAP4430_SLEEP_RBB_SEL_SHIFT 3 -#define OMAP4430_SLEEP_RBB_SEL_MASK BITFIELD(3, 3) +#define OMAP4430_SLEEP_RBB_SEL_MASK (1 << 3) /* Used by PRM_SRAM_COUNT */ #define OMAP4430_SLPCNT_VALUE_SHIFT 16 -#define OMAP4430_SLPCNT_VALUE_MASK BITFIELD(16, 23) +#define OMAP4430_SLPCNT_VALUE_MASK (0xff << 16) /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ #define OMAP4430_SMPSWAITTIMEMAX_SHIFT 8 -#define OMAP4430_SMPSWAITTIMEMAX_MASK BITFIELD(8, 23) +#define OMAP4430_SMPSWAITTIMEMAX_MASK (0xffff << 8) /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ #define OMAP4430_SMPSWAITTIMEMIN_SHIFT 8 -#define OMAP4430_SMPSWAITTIMEMIN_MASK BITFIELD(8, 23) +#define OMAP4430_SMPSWAITTIMEMIN_MASK (0xffff << 8) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_SMPS_RA_ERR_CORE_SHIFT 1 +#define OMAP4430_SMPS_RA_ERR_CORE_MASK (1 << 1) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_SMPS_RA_ERR_IVA_SHIFT 9 +#define OMAP4430_SMPS_RA_ERR_IVA_MASK (1 << 9) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_SMPS_RA_ERR_MPU_SHIFT 17 +#define OMAP4430_SMPS_RA_ERR_MPU_MASK (1 << 17) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_SMPS_SA_ERR_CORE_SHIFT 0 +#define OMAP4430_SMPS_SA_ERR_CORE_MASK (1 << 0) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_SMPS_SA_ERR_IVA_SHIFT 8 +#define OMAP4430_SMPS_SA_ERR_IVA_MASK (1 << 8) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_SMPS_SA_ERR_MPU_SHIFT 16 +#define OMAP4430_SMPS_SA_ERR_MPU_MASK (1 << 16) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_SMPS_TIMEOUT_ERR_CORE_SHIFT 2 +#define OMAP4430_SMPS_TIMEOUT_ERR_CORE_MASK (1 << 2) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_SMPS_TIMEOUT_ERR_IVA_SHIFT 10 +#define OMAP4430_SMPS_TIMEOUT_ERR_IVA_MASK (1 << 10) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_SMPS_TIMEOUT_ERR_MPU_SHIFT 18 +#define OMAP4430_SMPS_TIMEOUT_ERR_MPU_MASK (1 << 18) /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ #define OMAP4430_SR2EN_SHIFT 0 -#define OMAP4430_SR2EN_MASK BITFIELD(0, 0) +#define OMAP4430_SR2EN_MASK (1 << 0) /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ #define OMAP4430_SR2_IN_TRANSITION_SHIFT 6 -#define OMAP4430_SR2_IN_TRANSITION_MASK BITFIELD(6, 6) +#define OMAP4430_SR2_IN_TRANSITION_MASK (1 << 6) /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ #define OMAP4430_SR2_STATUS_SHIFT 3 -#define OMAP4430_SR2_STATUS_MASK BITFIELD(3, 4) +#define OMAP4430_SR2_STATUS_MASK (0x3 << 3) /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ #define OMAP4430_SR2_WTCNT_VALUE_SHIFT 8 -#define OMAP4430_SR2_WTCNT_VALUE_MASK BITFIELD(8, 15) +#define OMAP4430_SR2_WTCNT_VALUE_MASK (0xff << 8) /* * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, * PRM_LDO_SRAM_MPU_CTRL */ #define OMAP4430_SRAMLDO_STATUS_SHIFT 8 -#define OMAP4430_SRAMLDO_STATUS_MASK BITFIELD(8, 8) +#define OMAP4430_SRAMLDO_STATUS_MASK (1 << 8) /* * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, * PRM_LDO_SRAM_MPU_CTRL */ #define OMAP4430_SRAM_IN_TRANSITION_SHIFT 9 -#define OMAP4430_SRAM_IN_TRANSITION_MASK BITFIELD(9, 9) +#define OMAP4430_SRAM_IN_TRANSITION_MASK (1 << 9) /* Used by PRM_VC_CFG_I2C_MODE */ #define OMAP4430_SRMODEEN_SHIFT 4 -#define OMAP4430_SRMODEEN_MASK BITFIELD(4, 4) +#define OMAP4430_SRMODEEN_MASK (1 << 4) /* Used by PRM_VOLTSETUP_WARMRESET */ #define OMAP4430_STABLE_COUNT_SHIFT 0 -#define OMAP4430_STABLE_COUNT_MASK BITFIELD(0, 5) +#define OMAP4430_STABLE_COUNT_MASK (0x3f << 0) /* Used by PRM_VOLTSETUP_WARMRESET */ #define OMAP4430_STABLE_PRESCAL_SHIFT 8 -#define OMAP4430_STABLE_PRESCAL_MASK BITFIELD(8, 9) +#define OMAP4430_STABLE_PRESCAL_MASK (0x3 << 8) + +/* Used by PRM_LDO_BANDGAP_SETUP */ +#define OMAP4430_STARTUP_COUNT_SHIFT 0 +#define OMAP4430_STARTUP_COUNT_MASK (0xff << 0) + +/* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */ +#define OMAP4430_STARTUP_COUNT_24_31_SHIFT 24 +#define OMAP4430_STARTUP_COUNT_24_31_MASK (0xff << 24) /* Used by PM_IVAHD_PWRSTCTRL */ #define OMAP4430_TCM1_MEM_ONSTATE_SHIFT 20 -#define OMAP4430_TCM1_MEM_ONSTATE_MASK BITFIELD(20, 21) +#define OMAP4430_TCM1_MEM_ONSTATE_MASK (0x3 << 20) /* Used by PM_IVAHD_PWRSTCTRL */ #define OMAP4430_TCM1_MEM_RETSTATE_SHIFT 10 -#define OMAP4430_TCM1_MEM_RETSTATE_MASK BITFIELD(10, 10) +#define OMAP4430_TCM1_MEM_RETSTATE_MASK (1 << 10) /* Used by PM_IVAHD_PWRSTST */ #define OMAP4430_TCM1_MEM_STATEST_SHIFT 8 -#define OMAP4430_TCM1_MEM_STATEST_MASK BITFIELD(8, 9) +#define OMAP4430_TCM1_MEM_STATEST_MASK (0x3 << 8) /* Used by PM_IVAHD_PWRSTCTRL */ #define OMAP4430_TCM2_MEM_ONSTATE_SHIFT 22 -#define OMAP4430_TCM2_MEM_ONSTATE_MASK BITFIELD(22, 23) +#define OMAP4430_TCM2_MEM_ONSTATE_MASK (0x3 << 22) /* Used by PM_IVAHD_PWRSTCTRL */ #define OMAP4430_TCM2_MEM_RETSTATE_SHIFT 11 -#define OMAP4430_TCM2_MEM_RETSTATE_MASK BITFIELD(11, 11) +#define OMAP4430_TCM2_MEM_RETSTATE_MASK (1 << 11) /* Used by PM_IVAHD_PWRSTST */ #define OMAP4430_TCM2_MEM_STATEST_SHIFT 10 -#define OMAP4430_TCM2_MEM_STATEST_MASK BITFIELD(10, 11) +#define OMAP4430_TCM2_MEM_STATEST_MASK (0x3 << 10) /* Used by RM_TESLA_RSTST */ #define OMAP4430_TESLASS_EMU_RSTST_SHIFT 2 -#define OMAP4430_TESLASS_EMU_RSTST_MASK BITFIELD(2, 2) +#define OMAP4430_TESLASS_EMU_RSTST_MASK (1 << 2) /* Used by RM_TESLA_RSTST */ #define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_SHIFT 3 -#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK BITFIELD(3, 3) +#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK (1 << 3) /* Used by PM_TESLA_PWRSTCTRL */ #define OMAP4430_TESLA_EDMA_ONSTATE_SHIFT 20 -#define OMAP4430_TESLA_EDMA_ONSTATE_MASK BITFIELD(20, 21) +#define OMAP4430_TESLA_EDMA_ONSTATE_MASK (0x3 << 20) /* Used by PM_TESLA_PWRSTCTRL */ #define OMAP4430_TESLA_EDMA_RETSTATE_SHIFT 10 -#define OMAP4430_TESLA_EDMA_RETSTATE_MASK BITFIELD(10, 10) +#define OMAP4430_TESLA_EDMA_RETSTATE_MASK (1 << 10) /* Used by PM_TESLA_PWRSTST */ #define OMAP4430_TESLA_EDMA_STATEST_SHIFT 8 -#define OMAP4430_TESLA_EDMA_STATEST_MASK BITFIELD(8, 9) +#define OMAP4430_TESLA_EDMA_STATEST_MASK (0x3 << 8) /* Used by PM_TESLA_PWRSTCTRL */ #define OMAP4430_TESLA_L1_ONSTATE_SHIFT 16 -#define OMAP4430_TESLA_L1_ONSTATE_MASK BITFIELD(16, 17) +#define OMAP4430_TESLA_L1_ONSTATE_MASK (0x3 << 16) /* Used by PM_TESLA_PWRSTCTRL */ #define OMAP4430_TESLA_L1_RETSTATE_SHIFT 8 -#define OMAP4430_TESLA_L1_RETSTATE_MASK BITFIELD(8, 8) +#define OMAP4430_TESLA_L1_RETSTATE_MASK (1 << 8) /* Used by PM_TESLA_PWRSTST */ #define OMAP4430_TESLA_L1_STATEST_SHIFT 4 -#define OMAP4430_TESLA_L1_STATEST_MASK BITFIELD(4, 5) +#define OMAP4430_TESLA_L1_STATEST_MASK (0x3 << 4) /* Used by PM_TESLA_PWRSTCTRL */ #define OMAP4430_TESLA_L2_ONSTATE_SHIFT 18 -#define OMAP4430_TESLA_L2_ONSTATE_MASK BITFIELD(18, 19) +#define OMAP4430_TESLA_L2_ONSTATE_MASK (0x3 << 18) /* Used by PM_TESLA_PWRSTCTRL */ #define OMAP4430_TESLA_L2_RETSTATE_SHIFT 9 -#define OMAP4430_TESLA_L2_RETSTATE_MASK BITFIELD(9, 9) +#define OMAP4430_TESLA_L2_RETSTATE_MASK (1 << 9) /* Used by PM_TESLA_PWRSTST */ #define OMAP4430_TESLA_L2_STATEST_SHIFT 6 -#define OMAP4430_TESLA_L2_STATEST_MASK BITFIELD(6, 7) +#define OMAP4430_TESLA_L2_STATEST_MASK (0x3 << 6) /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ #define OMAP4430_TIMEOUT_SHIFT 0 -#define OMAP4430_TIMEOUT_MASK BITFIELD(0, 15) +#define OMAP4430_TIMEOUT_MASK (0xffff << 0) /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ #define OMAP4430_TIMEOUTEN_SHIFT 3 -#define OMAP4430_TIMEOUTEN_MASK BITFIELD(3, 3) +#define OMAP4430_TIMEOUTEN_MASK (1 << 3) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_TRANSITION_EN_SHIFT 8 -#define OMAP4430_TRANSITION_EN_MASK BITFIELD(8, 8) +#define OMAP4430_TRANSITION_EN_MASK (1 << 8) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_TRANSITION_ST_SHIFT 8 -#define OMAP4430_TRANSITION_ST_MASK BITFIELD(8, 8) +#define OMAP4430_TRANSITION_ST_MASK (1 << 8) /* Used by PRM_VC_VAL_BYPASS */ #define OMAP4430_VALID_SHIFT 24 -#define OMAP4430_VALID_MASK BITFIELD(24, 24) +#define OMAP4430_VALID_MASK (1 << 24) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VC_BYPASSACK_EN_SHIFT 14 -#define OMAP4430_VC_BYPASSACK_EN_MASK BITFIELD(14, 14) +#define OMAP4430_VC_BYPASSACK_EN_MASK (1 << 14) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VC_BYPASSACK_ST_SHIFT 14 -#define OMAP4430_VC_BYPASSACK_ST_MASK BITFIELD(14, 14) +#define OMAP4430_VC_BYPASSACK_ST_MASK (1 << 14) + +/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ +#define OMAP4430_VC_CORE_VPACK_EN_SHIFT 22 +#define OMAP4430_VC_CORE_VPACK_EN_MASK (1 << 22) + +/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ +#define OMAP4430_VC_CORE_VPACK_ST_SHIFT 22 +#define OMAP4430_VC_CORE_VPACK_ST_MASK (1 << 22) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VC_IVA_VPACK_EN_SHIFT 30 -#define OMAP4430_VC_IVA_VPACK_EN_MASK BITFIELD(30, 30) +#define OMAP4430_VC_IVA_VPACK_EN_MASK (1 << 30) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VC_IVA_VPACK_ST_SHIFT 30 -#define OMAP4430_VC_IVA_VPACK_ST_MASK BITFIELD(30, 30) +#define OMAP4430_VC_IVA_VPACK_ST_MASK (1 << 30) /* Used by PRM_IRQENABLE_MPU_2 */ #define OMAP4430_VC_MPU_VPACK_EN_SHIFT 6 -#define OMAP4430_VC_MPU_VPACK_EN_MASK BITFIELD(6, 6) +#define OMAP4430_VC_MPU_VPACK_EN_MASK (1 << 6) /* Used by PRM_IRQSTATUS_MPU_2 */ #define OMAP4430_VC_MPU_VPACK_ST_SHIFT 6 -#define OMAP4430_VC_MPU_VPACK_ST_MASK BITFIELD(6, 6) +#define OMAP4430_VC_MPU_VPACK_ST_MASK (1 << 6) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VC_RAERR_EN_SHIFT 12 -#define OMAP4430_VC_RAERR_EN_MASK BITFIELD(12, 12) +#define OMAP4430_VC_RAERR_EN_MASK (1 << 12) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VC_RAERR_ST_SHIFT 12 -#define OMAP4430_VC_RAERR_ST_MASK BITFIELD(12, 12) +#define OMAP4430_VC_RAERR_ST_MASK (1 << 12) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VC_SAERR_EN_SHIFT 11 -#define OMAP4430_VC_SAERR_EN_MASK BITFIELD(11, 11) +#define OMAP4430_VC_SAERR_EN_MASK (1 << 11) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VC_SAERR_ST_SHIFT 11 -#define OMAP4430_VC_SAERR_ST_MASK BITFIELD(11, 11) +#define OMAP4430_VC_SAERR_ST_MASK (1 << 11) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VC_TOERR_EN_SHIFT 13 -#define OMAP4430_VC_TOERR_EN_MASK BITFIELD(13, 13) +#define OMAP4430_VC_TOERR_EN_MASK (1 << 13) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VC_TOERR_ST_SHIFT 13 -#define OMAP4430_VC_TOERR_ST_MASK BITFIELD(13, 13) +#define OMAP4430_VC_TOERR_ST_MASK (1 << 13) /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ #define OMAP4430_VDDMAX_SHIFT 24 -#define OMAP4430_VDDMAX_MASK BITFIELD(24, 31) +#define OMAP4430_VDDMAX_MASK (0xff << 24) /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ #define OMAP4430_VDDMIN_SHIFT 16 -#define OMAP4430_VDDMIN_MASK BITFIELD(16, 23) +#define OMAP4430_VDDMIN_MASK (0xff << 16) /* Used by PRM_VOLTCTRL */ #define OMAP4430_VDD_CORE_I2C_DISABLE_SHIFT 12 -#define OMAP4430_VDD_CORE_I2C_DISABLE_MASK BITFIELD(12, 12) +#define OMAP4430_VDD_CORE_I2C_DISABLE_MASK (1 << 12) /* Used by PRM_RSTST */ #define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT 8 -#define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK BITFIELD(8, 8) +#define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK (1 << 8) /* Used by PRM_VOLTCTRL */ #define OMAP4430_VDD_IVA_I2C_DISABLE_SHIFT 14 -#define OMAP4430_VDD_IVA_I2C_DISABLE_MASK BITFIELD(14, 14) +#define OMAP4430_VDD_IVA_I2C_DISABLE_MASK (1 << 14) /* Used by PRM_VOLTCTRL */ #define OMAP4430_VDD_IVA_PRESENCE_SHIFT 9 -#define OMAP4430_VDD_IVA_PRESENCE_MASK BITFIELD(9, 9) +#define OMAP4430_VDD_IVA_PRESENCE_MASK (1 << 9) /* Used by PRM_RSTST */ #define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT 7 -#define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK BITFIELD(7, 7) +#define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK (1 << 7) /* Used by PRM_VOLTCTRL */ #define OMAP4430_VDD_MPU_I2C_DISABLE_SHIFT 13 -#define OMAP4430_VDD_MPU_I2C_DISABLE_MASK BITFIELD(13, 13) +#define OMAP4430_VDD_MPU_I2C_DISABLE_MASK (1 << 13) /* Used by PRM_VOLTCTRL */ #define OMAP4430_VDD_MPU_PRESENCE_SHIFT 8 -#define OMAP4430_VDD_MPU_PRESENCE_MASK BITFIELD(8, 8) +#define OMAP4430_VDD_MPU_PRESENCE_MASK (1 << 8) /* Used by PRM_RSTST */ #define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT 6 -#define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK BITFIELD(6, 6) +#define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK (1 << 6) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_VFSM_RA_ERR_CORE_SHIFT 4 +#define OMAP4430_VFSM_RA_ERR_CORE_MASK (1 << 4) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_VFSM_RA_ERR_IVA_SHIFT 12 +#define OMAP4430_VFSM_RA_ERR_IVA_MASK (1 << 12) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_VFSM_RA_ERR_MPU_SHIFT 20 +#define OMAP4430_VFSM_RA_ERR_MPU_MASK (1 << 20) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_VFSM_SA_ERR_CORE_SHIFT 3 +#define OMAP4430_VFSM_SA_ERR_CORE_MASK (1 << 3) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_VFSM_SA_ERR_IVA_SHIFT 11 +#define OMAP4430_VFSM_SA_ERR_IVA_MASK (1 << 11) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_VFSM_SA_ERR_MPU_SHIFT 19 +#define OMAP4430_VFSM_SA_ERR_MPU_MASK (1 << 19) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_VFSM_TIMEOUT_ERR_CORE_SHIFT 5 +#define OMAP4430_VFSM_TIMEOUT_ERR_CORE_MASK (1 << 5) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_VFSM_TIMEOUT_ERR_IVA_SHIFT 13 +#define OMAP4430_VFSM_TIMEOUT_ERR_IVA_MASK (1 << 13) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_VFSM_TIMEOUT_ERR_MPU_SHIFT 21 +#define OMAP4430_VFSM_TIMEOUT_ERR_MPU_MASK (1 << 21) /* Used by PRM_VC_VAL_SMPS_RA_VOL */ #define OMAP4430_VOLRA_VDD_CORE_L_SHIFT 0 -#define OMAP4430_VOLRA_VDD_CORE_L_MASK BITFIELD(0, 7) +#define OMAP4430_VOLRA_VDD_CORE_L_MASK (0xff << 0) /* Used by PRM_VC_VAL_SMPS_RA_VOL */ #define OMAP4430_VOLRA_VDD_IVA_L_SHIFT 8 -#define OMAP4430_VOLRA_VDD_IVA_L_MASK BITFIELD(8, 15) +#define OMAP4430_VOLRA_VDD_IVA_L_MASK (0xff << 8) /* Used by PRM_VC_VAL_SMPS_RA_VOL */ #define OMAP4430_VOLRA_VDD_MPU_L_SHIFT 16 -#define OMAP4430_VOLRA_VDD_MPU_L_MASK BITFIELD(16, 23) +#define OMAP4430_VOLRA_VDD_MPU_L_MASK (0xff << 16) /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ #define OMAP4430_VPENABLE_SHIFT 0 -#define OMAP4430_VPENABLE_MASK BITFIELD(0, 0) +#define OMAP4430_VPENABLE_MASK (1 << 0) /* Used by PRM_VP_CORE_STATUS, PRM_VP_IVA_STATUS, PRM_VP_MPU_STATUS */ #define OMAP4430_VPINIDLE_SHIFT 0 -#define OMAP4430_VPINIDLE_MASK BITFIELD(0, 0) +#define OMAP4430_VPINIDLE_MASK (1 << 0) /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */ #define OMAP4430_VPVOLTAGE_SHIFT 0 -#define OMAP4430_VPVOLTAGE_MASK BITFIELD(0, 7) +#define OMAP4430_VPVOLTAGE_MASK (0xff << 0) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_CORE_EQVALUE_EN_SHIFT 20 -#define OMAP4430_VP_CORE_EQVALUE_EN_MASK BITFIELD(20, 20) +#define OMAP4430_VP_CORE_EQVALUE_EN_MASK (1 << 20) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_CORE_EQVALUE_ST_SHIFT 20 -#define OMAP4430_VP_CORE_EQVALUE_ST_MASK BITFIELD(20, 20) +#define OMAP4430_VP_CORE_EQVALUE_ST_MASK (1 << 20) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_CORE_MAXVDD_EN_SHIFT 18 -#define OMAP4430_VP_CORE_MAXVDD_EN_MASK BITFIELD(18, 18) +#define OMAP4430_VP_CORE_MAXVDD_EN_MASK (1 << 18) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_CORE_MAXVDD_ST_SHIFT 18 -#define OMAP4430_VP_CORE_MAXVDD_ST_MASK BITFIELD(18, 18) +#define OMAP4430_VP_CORE_MAXVDD_ST_MASK (1 << 18) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_CORE_MINVDD_EN_SHIFT 17 -#define OMAP4430_VP_CORE_MINVDD_EN_MASK BITFIELD(17, 17) +#define OMAP4430_VP_CORE_MINVDD_EN_MASK (1 << 17) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_CORE_MINVDD_ST_SHIFT 17 -#define OMAP4430_VP_CORE_MINVDD_ST_MASK BITFIELD(17, 17) +#define OMAP4430_VP_CORE_MINVDD_ST_MASK (1 << 17) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_CORE_NOSMPSACK_EN_SHIFT 19 -#define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK BITFIELD(19, 19) +#define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK (1 << 19) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_CORE_NOSMPSACK_ST_SHIFT 19 -#define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK BITFIELD(19, 19) +#define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK (1 << 19) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_SHIFT 16 -#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK BITFIELD(16, 16) +#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK (1 << 16) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_SHIFT 16 -#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK BITFIELD(16, 16) +#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK (1 << 16) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_CORE_TRANXDONE_EN_SHIFT 21 -#define OMAP4430_VP_CORE_TRANXDONE_EN_MASK BITFIELD(21, 21) +#define OMAP4430_VP_CORE_TRANXDONE_EN_MASK (1 << 21) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_CORE_TRANXDONE_ST_SHIFT 21 -#define OMAP4430_VP_CORE_TRANXDONE_ST_MASK BITFIELD(21, 21) +#define OMAP4430_VP_CORE_TRANXDONE_ST_MASK (1 << 21) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_IVA_EQVALUE_EN_SHIFT 28 -#define OMAP4430_VP_IVA_EQVALUE_EN_MASK BITFIELD(28, 28) +#define OMAP4430_VP_IVA_EQVALUE_EN_MASK (1 << 28) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_IVA_EQVALUE_ST_SHIFT 28 -#define OMAP4430_VP_IVA_EQVALUE_ST_MASK BITFIELD(28, 28) +#define OMAP4430_VP_IVA_EQVALUE_ST_MASK (1 << 28) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_IVA_MAXVDD_EN_SHIFT 26 -#define OMAP4430_VP_IVA_MAXVDD_EN_MASK BITFIELD(26, 26) +#define OMAP4430_VP_IVA_MAXVDD_EN_MASK (1 << 26) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_IVA_MAXVDD_ST_SHIFT 26 -#define OMAP4430_VP_IVA_MAXVDD_ST_MASK BITFIELD(26, 26) +#define OMAP4430_VP_IVA_MAXVDD_ST_MASK (1 << 26) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_IVA_MINVDD_EN_SHIFT 25 -#define OMAP4430_VP_IVA_MINVDD_EN_MASK BITFIELD(25, 25) +#define OMAP4430_VP_IVA_MINVDD_EN_MASK (1 << 25) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_IVA_MINVDD_ST_SHIFT 25 -#define OMAP4430_VP_IVA_MINVDD_ST_MASK BITFIELD(25, 25) +#define OMAP4430_VP_IVA_MINVDD_ST_MASK (1 << 25) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_IVA_NOSMPSACK_EN_SHIFT 27 -#define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK BITFIELD(27, 27) +#define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK (1 << 27) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_IVA_NOSMPSACK_ST_SHIFT 27 -#define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK BITFIELD(27, 27) +#define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK (1 << 27) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_SHIFT 24 -#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK BITFIELD(24, 24) +#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK (1 << 24) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_SHIFT 24 -#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK BITFIELD(24, 24) +#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK (1 << 24) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_IVA_TRANXDONE_EN_SHIFT 29 -#define OMAP4430_VP_IVA_TRANXDONE_EN_MASK BITFIELD(29, 29) +#define OMAP4430_VP_IVA_TRANXDONE_EN_MASK (1 << 29) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_IVA_TRANXDONE_ST_SHIFT 29 -#define OMAP4430_VP_IVA_TRANXDONE_ST_MASK BITFIELD(29, 29) +#define OMAP4430_VP_IVA_TRANXDONE_ST_MASK (1 << 29) /* Used by PRM_IRQENABLE_MPU_2 */ #define OMAP4430_VP_MPU_EQVALUE_EN_SHIFT 4 -#define OMAP4430_VP_MPU_EQVALUE_EN_MASK BITFIELD(4, 4) +#define OMAP4430_VP_MPU_EQVALUE_EN_MASK (1 << 4) /* Used by PRM_IRQSTATUS_MPU_2 */ #define OMAP4430_VP_MPU_EQVALUE_ST_SHIFT 4 -#define OMAP4430_VP_MPU_EQVALUE_ST_MASK BITFIELD(4, 4) +#define OMAP4430_VP_MPU_EQVALUE_ST_MASK (1 << 4) /* Used by PRM_IRQENABLE_MPU_2 */ #define OMAP4430_VP_MPU_MAXVDD_EN_SHIFT 2 -#define OMAP4430_VP_MPU_MAXVDD_EN_MASK BITFIELD(2, 2) +#define OMAP4430_VP_MPU_MAXVDD_EN_MASK (1 << 2) /* Used by PRM_IRQSTATUS_MPU_2 */ #define OMAP4430_VP_MPU_MAXVDD_ST_SHIFT 2 -#define OMAP4430_VP_MPU_MAXVDD_ST_MASK BITFIELD(2, 2) +#define OMAP4430_VP_MPU_MAXVDD_ST_MASK (1 << 2) /* Used by PRM_IRQENABLE_MPU_2 */ #define OMAP4430_VP_MPU_MINVDD_EN_SHIFT 1 -#define OMAP4430_VP_MPU_MINVDD_EN_MASK BITFIELD(1, 1) +#define OMAP4430_VP_MPU_MINVDD_EN_MASK (1 << 1) /* Used by PRM_IRQSTATUS_MPU_2 */ #define OMAP4430_VP_MPU_MINVDD_ST_SHIFT 1 -#define OMAP4430_VP_MPU_MINVDD_ST_MASK BITFIELD(1, 1) +#define OMAP4430_VP_MPU_MINVDD_ST_MASK (1 << 1) /* Used by PRM_IRQENABLE_MPU_2 */ #define OMAP4430_VP_MPU_NOSMPSACK_EN_SHIFT 3 -#define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK BITFIELD(3, 3) +#define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK (1 << 3) /* Used by PRM_IRQSTATUS_MPU_2 */ #define OMAP4430_VP_MPU_NOSMPSACK_ST_SHIFT 3 -#define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK BITFIELD(3, 3) +#define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK (1 << 3) /* Used by PRM_IRQENABLE_MPU_2 */ #define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_SHIFT 0 -#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK BITFIELD(0, 0) +#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK (1 << 0) /* Used by PRM_IRQSTATUS_MPU_2 */ #define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_SHIFT 0 -#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK BITFIELD(0, 0) +#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK (1 << 0) /* Used by PRM_IRQENABLE_MPU_2 */ #define OMAP4430_VP_MPU_TRANXDONE_EN_SHIFT 5 -#define OMAP4430_VP_MPU_TRANXDONE_EN_MASK BITFIELD(5, 5) +#define OMAP4430_VP_MPU_TRANXDONE_EN_MASK (1 << 5) /* Used by PRM_IRQSTATUS_MPU_2 */ #define OMAP4430_VP_MPU_TRANXDONE_ST_SHIFT 5 -#define OMAP4430_VP_MPU_TRANXDONE_ST_MASK BITFIELD(5, 5) +#define OMAP4430_VP_MPU_TRANXDONE_ST_MASK (1 << 5) /* Used by PRM_SRAM_COUNT */ #define OMAP4430_VSETUPCNT_VALUE_SHIFT 8 -#define OMAP4430_VSETUPCNT_VALUE_MASK BITFIELD(8, 15) +#define OMAP4430_VSETUPCNT_VALUE_MASK (0xff << 8) /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ #define OMAP4430_VSTEPMAX_SHIFT 0 -#define OMAP4430_VSTEPMAX_MASK BITFIELD(0, 7) +#define OMAP4430_VSTEPMAX_MASK (0xff << 0) /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ #define OMAP4430_VSTEPMIN_SHIFT 0 -#define OMAP4430_VSTEPMIN_MASK BITFIELD(0, 7) +#define OMAP4430_VSTEPMIN_MASK (0xff << 0) /* Used by PRM_MODEM_IF_CTRL */ #define OMAP4430_WAKE_MODEM_SHIFT 0 -#define OMAP4430_WAKE_MODEM_MASK BITFIELD(0, 0) +#define OMAP4430_WAKE_MODEM_MASK (1 << 0) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DISPC_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK (1 << 1) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DISPC_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DISPC_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_DISPC_MPU_MASK (1 << 0) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DISPC_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_DISPC_SDMA_MASK BITFIELD(3, 3) +#define OMAP4430_WKUPDEP_DISPC_SDMA_MASK (1 << 3) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DISPC_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_DISPC_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_DISPC_TESLA_MASK (1 << 2) /* Used by PM_ABE_DMIC_WKDEP */ #define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK BITFIELD(7, 7) +#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK (1 << 7) /* Used by PM_ABE_DMIC_WKDEP */ #define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK BITFIELD(6, 6) +#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK (1 << 6) /* Used by PM_ABE_DMIC_WKDEP */ #define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK (1 << 0) /* Used by PM_ABE_DMIC_WKDEP */ #define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK (1 << 2) /* Used by PM_L4PER_DMTIMER10_WKDEP */ #define OMAP4430_WKUPDEP_DMTIMER10_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK (1 << 0) /* Used by PM_L4PER_DMTIMER11_WKDEP */ #define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK (1 << 1) /* Used by PM_L4PER_DMTIMER11_WKDEP */ #define OMAP4430_WKUPDEP_DMTIMER11_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK (1 << 0) /* Used by PM_L4PER_DMTIMER2_WKDEP */ #define OMAP4430_WKUPDEP_DMTIMER2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK (1 << 0) /* Used by PM_L4PER_DMTIMER3_WKDEP */ #define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK (1 << 1) /* Used by PM_L4PER_DMTIMER3_WKDEP */ #define OMAP4430_WKUPDEP_DMTIMER3_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK (1 << 0) /* Used by PM_L4PER_DMTIMER4_WKDEP */ #define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK (1 << 1) /* Used by PM_L4PER_DMTIMER4_WKDEP */ #define OMAP4430_WKUPDEP_DMTIMER4_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK (1 << 0) /* Used by PM_L4PER_DMTIMER9_WKDEP */ #define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK (1 << 1) /* Used by PM_L4PER_DMTIMER9_WKDEP */ #define OMAP4430_WKUPDEP_DMTIMER9_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK (1 << 0) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DSI1_DUCATI_SHIFT 5 -#define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK BITFIELD(5, 5) +#define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK (1 << 5) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DSI1_MPU_SHIFT 4 -#define OMAP4430_WKUPDEP_DSI1_MPU_MASK BITFIELD(4, 4) +#define OMAP4430_WKUPDEP_DSI1_MPU_MASK (1 << 4) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DSI1_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_DSI1_SDMA_MASK BITFIELD(7, 7) +#define OMAP4430_WKUPDEP_DSI1_SDMA_MASK (1 << 7) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DSI1_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_DSI1_TESLA_MASK BITFIELD(6, 6) +#define OMAP4430_WKUPDEP_DSI1_TESLA_MASK (1 << 6) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DSI2_DUCATI_SHIFT 9 -#define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK BITFIELD(9, 9) +#define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK (1 << 9) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DSI2_MPU_SHIFT 8 -#define OMAP4430_WKUPDEP_DSI2_MPU_MASK BITFIELD(8, 8) +#define OMAP4430_WKUPDEP_DSI2_MPU_MASK (1 << 8) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DSI2_SDMA_SHIFT 11 -#define OMAP4430_WKUPDEP_DSI2_SDMA_MASK BITFIELD(11, 11) +#define OMAP4430_WKUPDEP_DSI2_SDMA_MASK (1 << 11) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DSI2_TESLA_SHIFT 10 -#define OMAP4430_WKUPDEP_DSI2_TESLA_MASK BITFIELD(10, 10) +#define OMAP4430_WKUPDEP_DSI2_TESLA_MASK (1 << 10) /* Used by PM_WKUP_GPIO1_WKDEP */ #define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK (1 << 1) /* Used by PM_WKUP_GPIO1_WKDEP */ #define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK (1 << 0) /* Used by PM_WKUP_GPIO1_WKDEP */ #define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK BITFIELD(6, 6) +#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK (1 << 6) /* Used by PM_L4PER_GPIO2_WKDEP */ #define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK (1 << 1) /* Used by PM_L4PER_GPIO2_WKDEP */ #define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK (1 << 0) /* Used by PM_L4PER_GPIO2_WKDEP */ #define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK BITFIELD(6, 6) +#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK (1 << 6) /* Used by PM_L4PER_GPIO3_WKDEP */ #define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK (1 << 0) /* Used by PM_L4PER_GPIO3_WKDEP */ #define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK BITFIELD(6, 6) +#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK (1 << 6) /* Used by PM_L4PER_GPIO4_WKDEP */ #define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK (1 << 0) /* Used by PM_L4PER_GPIO4_WKDEP */ #define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK BITFIELD(6, 6) +#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK (1 << 6) /* Used by PM_L4PER_GPIO5_WKDEP */ #define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK (1 << 0) /* Used by PM_L4PER_GPIO5_WKDEP */ #define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK BITFIELD(6, 6) +#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK (1 << 6) /* Used by PM_L4PER_GPIO6_WKDEP */ #define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK (1 << 0) /* Used by PM_L4PER_GPIO6_WKDEP */ #define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK BITFIELD(6, 6) +#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK (1 << 6) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_HDMIDMA_SDMA_SHIFT 19 -#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK BITFIELD(19, 19) +#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK (1 << 19) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_SHIFT 13 -#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK BITFIELD(13, 13) +#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK (1 << 13) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_HDMIIRQ_MPU_SHIFT 12 -#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK BITFIELD(12, 12) +#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK (1 << 12) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_SHIFT 14 -#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK BITFIELD(14, 14) +#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK (1 << 14) /* Used by PM_L4PER_HECC1_WKDEP */ #define OMAP4430_WKUPDEP_HECC1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_HECC1_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_HECC1_MPU_MASK (1 << 0) /* Used by PM_L4PER_HECC2_WKDEP */ #define OMAP4430_WKUPDEP_HECC2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_HECC2_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_HECC2_MPU_MASK (1 << 0) /* Used by PM_L3INIT_HSI_WKDEP */ #define OMAP4430_WKUPDEP_HSI_DSP_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK BITFIELD(6, 6) +#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK (1 << 6) /* Used by PM_L3INIT_HSI_WKDEP */ #define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK (1 << 1) /* Used by PM_L3INIT_HSI_WKDEP */ #define OMAP4430_WKUPDEP_HSI_MCU_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK (1 << 0) /* Used by PM_L4PER_I2C1_WKDEP */ #define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK BITFIELD(7, 7) +#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK (1 << 7) /* Used by PM_L4PER_I2C1_WKDEP */ #define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK (1 << 1) /* Used by PM_L4PER_I2C1_WKDEP */ #define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK (1 << 0) /* Used by PM_L4PER_I2C2_WKDEP */ #define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK BITFIELD(7, 7) +#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK (1 << 7) /* Used by PM_L4PER_I2C2_WKDEP */ #define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK (1 << 1) /* Used by PM_L4PER_I2C2_WKDEP */ #define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK (1 << 0) /* Used by PM_L4PER_I2C3_WKDEP */ #define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK BITFIELD(7, 7) +#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK (1 << 7) /* Used by PM_L4PER_I2C3_WKDEP */ #define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK (1 << 1) /* Used by PM_L4PER_I2C3_WKDEP */ #define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK (1 << 0) /* Used by PM_L4PER_I2C4_WKDEP */ #define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK BITFIELD(7, 7) +#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK (1 << 7) /* Used by PM_L4PER_I2C4_WKDEP */ #define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK (1 << 1) /* Used by PM_L4PER_I2C4_WKDEP */ #define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK (1 << 0) /* Used by PM_L4PER_I2C5_WKDEP */ #define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK BITFIELD(7, 7) +#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK (1 << 7) /* Used by PM_L4PER_I2C5_WKDEP */ #define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK (1 << 0) /* Used by PM_WKUP_KEYBOARD_WKDEP */ #define OMAP4430_WKUPDEP_KEYBOARD_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK (1 << 0) /* Used by PM_ABE_MCASP_WKDEP */ #define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK BITFIELD(7, 7) +#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK (1 << 7) /* Used by PM_ABE_MCASP_WKDEP */ #define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK BITFIELD(6, 6) +#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK (1 << 6) /* Used by PM_ABE_MCASP_WKDEP */ #define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK (1 << 0) /* Used by PM_ABE_MCASP_WKDEP */ #define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK (1 << 2) /* Used by PM_L4PER_MCASP2_WKDEP */ #define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK BITFIELD(7, 7) +#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK (1 << 7) /* Used by PM_L4PER_MCASP2_WKDEP */ #define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK BITFIELD(6, 6) +#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK (1 << 6) /* Used by PM_L4PER_MCASP2_WKDEP */ #define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK (1 << 0) /* Used by PM_L4PER_MCASP2_WKDEP */ #define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK (1 << 2) /* Used by PM_L4PER_MCASP3_WKDEP */ #define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK BITFIELD(7, 7) +#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK (1 << 7) /* Used by PM_L4PER_MCASP3_WKDEP */ #define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK BITFIELD(6, 6) +#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK (1 << 6) /* Used by PM_L4PER_MCASP3_WKDEP */ #define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK (1 << 0) /* Used by PM_L4PER_MCASP3_WKDEP */ #define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK (1 << 2) /* Used by PM_ABE_MCBSP1_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK (1 << 0) /* Used by PM_ABE_MCBSP1_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP1_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK BITFIELD(3, 3) +#define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK (1 << 3) /* Used by PM_ABE_MCBSP1_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP1_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK (1 << 2) /* Used by PM_ABE_MCBSP2_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK (1 << 0) /* Used by PM_ABE_MCBSP2_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP2_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK BITFIELD(3, 3) +#define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK (1 << 3) /* Used by PM_ABE_MCBSP2_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP2_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK (1 << 2) /* Used by PM_ABE_MCBSP3_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP3_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK (1 << 0) /* Used by PM_ABE_MCBSP3_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP3_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK BITFIELD(3, 3) +#define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK (1 << 3) /* Used by PM_ABE_MCBSP3_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP3_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK (1 << 2) /* Used by PM_L4PER_MCBSP4_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP4_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK (1 << 0) /* Used by PM_L4PER_MCBSP4_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP4_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK BITFIELD(3, 3) +#define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK (1 << 3) /* Used by PM_L4PER_MCBSP4_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP4_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK (1 << 2) /* Used by PM_L4PER_MCSPI1_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI1_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK (1 << 1) /* Used by PM_L4PER_MCSPI1_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK (1 << 0) /* Used by PM_L4PER_MCSPI1_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI1_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK BITFIELD(3, 3) +#define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK (1 << 3) /* Used by PM_L4PER_MCSPI1_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI1_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK (1 << 2) /* Used by PM_L4PER_MCSPI2_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI2_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK (1 << 1) /* Used by PM_L4PER_MCSPI2_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK (1 << 0) /* Used by PM_L4PER_MCSPI2_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI2_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK BITFIELD(3, 3) +#define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK (1 << 3) /* Used by PM_L4PER_MCSPI3_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI3_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK (1 << 0) /* Used by PM_L4PER_MCSPI3_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI3_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK BITFIELD(3, 3) +#define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK (1 << 3) /* Used by PM_L4PER_MCSPI4_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI4_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK (1 << 0) /* Used by PM_L4PER_MCSPI4_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI4_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK BITFIELD(3, 3) +#define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK (1 << 3) /* Used by PM_L3INIT_MMC1_WKDEP */ #define OMAP4430_WKUPDEP_MMC1_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK (1 << 1) /* Used by PM_L3INIT_MMC1_WKDEP */ #define OMAP4430_WKUPDEP_MMC1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MMC1_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_MMC1_MPU_MASK (1 << 0) /* Used by PM_L3INIT_MMC1_WKDEP */ #define OMAP4430_WKUPDEP_MMC1_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MMC1_SDMA_MASK BITFIELD(3, 3) +#define OMAP4430_WKUPDEP_MMC1_SDMA_MASK (1 << 3) /* Used by PM_L3INIT_MMC1_WKDEP */ #define OMAP4430_WKUPDEP_MMC1_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MMC1_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_MMC1_TESLA_MASK (1 << 2) /* Used by PM_L3INIT_MMC2_WKDEP */ #define OMAP4430_WKUPDEP_MMC2_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK (1 << 1) /* Used by PM_L3INIT_MMC2_WKDEP */ #define OMAP4430_WKUPDEP_MMC2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MMC2_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_MMC2_MPU_MASK (1 << 0) /* Used by PM_L3INIT_MMC2_WKDEP */ #define OMAP4430_WKUPDEP_MMC2_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MMC2_SDMA_MASK BITFIELD(3, 3) +#define OMAP4430_WKUPDEP_MMC2_SDMA_MASK (1 << 3) /* Used by PM_L3INIT_MMC2_WKDEP */ #define OMAP4430_WKUPDEP_MMC2_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MMC2_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_MMC2_TESLA_MASK (1 << 2) /* Used by PM_L3INIT_MMC6_WKDEP */ #define OMAP4430_WKUPDEP_MMC6_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK (1 << 1) /* Used by PM_L3INIT_MMC6_WKDEP */ #define OMAP4430_WKUPDEP_MMC6_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MMC6_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_MMC6_MPU_MASK (1 << 0) /* Used by PM_L3INIT_MMC6_WKDEP */ #define OMAP4430_WKUPDEP_MMC6_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MMC6_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_MMC6_TESLA_MASK (1 << 2) /* Used by PM_L4PER_MMCSD3_WKDEP */ #define OMAP4430_WKUPDEP_MMCSD3_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK (1 << 1) /* Used by PM_L4PER_MMCSD3_WKDEP */ #define OMAP4430_WKUPDEP_MMCSD3_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK (1 << 0) /* Used by PM_L4PER_MMCSD3_WKDEP */ #define OMAP4430_WKUPDEP_MMCSD3_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK BITFIELD(3, 3) +#define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK (1 << 3) /* Used by PM_L4PER_MMCSD4_WKDEP */ #define OMAP4430_WKUPDEP_MMCSD4_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK (1 << 1) /* Used by PM_L4PER_MMCSD4_WKDEP */ #define OMAP4430_WKUPDEP_MMCSD4_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK (1 << 0) /* Used by PM_L4PER_MMCSD4_WKDEP */ #define OMAP4430_WKUPDEP_MMCSD4_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK BITFIELD(3, 3) +#define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK (1 << 3) /* Used by PM_L4PER_MMCSD5_WKDEP */ #define OMAP4430_WKUPDEP_MMCSD5_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK (1 << 1) /* Used by PM_L4PER_MMCSD5_WKDEP */ #define OMAP4430_WKUPDEP_MMCSD5_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK (1 << 0) /* Used by PM_L4PER_MMCSD5_WKDEP */ #define OMAP4430_WKUPDEP_MMCSD5_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK BITFIELD(3, 3) +#define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK (1 << 3) /* Used by PM_L3INIT_PCIESS_WKDEP */ #define OMAP4430_WKUPDEP_PCIESS_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_PCIESS_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_PCIESS_MPU_MASK (1 << 0) /* Used by PM_L3INIT_PCIESS_WKDEP */ #define OMAP4430_WKUPDEP_PCIESS_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK (1 << 2) /* Used by PM_ABE_PDM_WKDEP */ #define OMAP4430_WKUPDEP_PDM_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK BITFIELD(7, 7) +#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK (1 << 7) /* Used by PM_ABE_PDM_WKDEP */ #define OMAP4430_WKUPDEP_PDM_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK BITFIELD(6, 6) +#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK (1 << 6) /* Used by PM_ABE_PDM_WKDEP */ #define OMAP4430_WKUPDEP_PDM_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK (1 << 0) /* Used by PM_ABE_PDM_WKDEP */ #define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK (1 << 2) /* Used by PM_WKUP_RTC_WKDEP */ #define OMAP4430_WKUPDEP_RTC_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_RTC_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_RTC_MPU_MASK (1 << 0) /* Used by PM_L3INIT_SATA_WKDEP */ #define OMAP4430_WKUPDEP_SATA_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_SATA_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_SATA_MPU_MASK (1 << 0) /* Used by PM_L3INIT_SATA_WKDEP */ #define OMAP4430_WKUPDEP_SATA_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_SATA_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_SATA_TESLA_MASK (1 << 2) /* Used by PM_ABE_SLIMBUS_WKDEP */ #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK BITFIELD(7, 7) +#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK (1 << 7) /* Used by PM_ABE_SLIMBUS_WKDEP */ #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK BITFIELD(6, 6) +#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK (1 << 6) /* Used by PM_ABE_SLIMBUS_WKDEP */ #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK (1 << 0) /* Used by PM_ABE_SLIMBUS_WKDEP */ #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK (1 << 2) /* Used by PM_L4PER_SLIMBUS2_WKDEP */ #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK BITFIELD(7, 7) +#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK (1 << 7) /* Used by PM_L4PER_SLIMBUS2_WKDEP */ #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK BITFIELD(6, 6) +#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK (1 << 6) /* Used by PM_L4PER_SLIMBUS2_WKDEP */ #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK (1 << 0) /* Used by PM_L4PER_SLIMBUS2_WKDEP */ #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK (1 << 2) /* Used by PM_ALWON_SR_CORE_WKDEP */ #define OMAP4430_WKUPDEP_SR_CORE_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK (1 << 1) /* Used by PM_ALWON_SR_CORE_WKDEP */ #define OMAP4430_WKUPDEP_SR_CORE_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK (1 << 0) /* Used by PM_ALWON_SR_IVA_WKDEP */ #define OMAP4430_WKUPDEP_SR_IVA_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK (1 << 1) /* Used by PM_ALWON_SR_IVA_WKDEP */ #define OMAP4430_WKUPDEP_SR_IVA_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK (1 << 0) /* Used by PM_ALWON_SR_MPU_WKDEP */ #define OMAP4430_WKUPDEP_SR_MPU_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK (1 << 0) /* Used by PM_WKUP_TIMER12_WKDEP */ #define OMAP4430_WKUPDEP_TIMER12_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_TIMER12_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_TIMER12_MPU_MASK (1 << 0) /* Used by PM_WKUP_TIMER1_WKDEP */ #define OMAP4430_WKUPDEP_TIMER1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_TIMER1_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_TIMER1_MPU_MASK (1 << 0) /* Used by PM_ABE_TIMER5_WKDEP */ #define OMAP4430_WKUPDEP_TIMER5_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_TIMER5_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_TIMER5_MPU_MASK (1 << 0) /* Used by PM_ABE_TIMER5_WKDEP */ #define OMAP4430_WKUPDEP_TIMER5_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK (1 << 2) /* Used by PM_ABE_TIMER6_WKDEP */ #define OMAP4430_WKUPDEP_TIMER6_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_TIMER6_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_TIMER6_MPU_MASK (1 << 0) /* Used by PM_ABE_TIMER6_WKDEP */ #define OMAP4430_WKUPDEP_TIMER6_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK (1 << 2) /* Used by PM_ABE_TIMER7_WKDEP */ #define OMAP4430_WKUPDEP_TIMER7_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_TIMER7_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_TIMER7_MPU_MASK (1 << 0) /* Used by PM_ABE_TIMER7_WKDEP */ #define OMAP4430_WKUPDEP_TIMER7_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK (1 << 2) /* Used by PM_ABE_TIMER8_WKDEP */ #define OMAP4430_WKUPDEP_TIMER8_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_TIMER8_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_TIMER8_MPU_MASK (1 << 0) /* Used by PM_ABE_TIMER8_WKDEP */ #define OMAP4430_WKUPDEP_TIMER8_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK (1 << 2) /* Used by PM_L4PER_UART1_WKDEP */ #define OMAP4430_WKUPDEP_UART1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_UART1_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_UART1_MPU_MASK (1 << 0) /* Used by PM_L4PER_UART1_WKDEP */ #define OMAP4430_WKUPDEP_UART1_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_UART1_SDMA_MASK BITFIELD(3, 3) +#define OMAP4430_WKUPDEP_UART1_SDMA_MASK (1 << 3) /* Used by PM_L4PER_UART2_WKDEP */ #define OMAP4430_WKUPDEP_UART2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_UART2_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_UART2_MPU_MASK (1 << 0) /* Used by PM_L4PER_UART2_WKDEP */ #define OMAP4430_WKUPDEP_UART2_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_UART2_SDMA_MASK BITFIELD(3, 3) +#define OMAP4430_WKUPDEP_UART2_SDMA_MASK (1 << 3) /* Used by PM_L4PER_UART3_WKDEP */ #define OMAP4430_WKUPDEP_UART3_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_UART3_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_UART3_DUCATI_MASK (1 << 1) /* Used by PM_L4PER_UART3_WKDEP */ #define OMAP4430_WKUPDEP_UART3_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_UART3_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_UART3_MPU_MASK (1 << 0) /* Used by PM_L4PER_UART3_WKDEP */ #define OMAP4430_WKUPDEP_UART3_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_UART3_SDMA_MASK BITFIELD(3, 3) +#define OMAP4430_WKUPDEP_UART3_SDMA_MASK (1 << 3) /* Used by PM_L4PER_UART3_WKDEP */ #define OMAP4430_WKUPDEP_UART3_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_UART3_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_UART3_TESLA_MASK (1 << 2) /* Used by PM_L4PER_UART4_WKDEP */ #define OMAP4430_WKUPDEP_UART4_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_UART4_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_UART4_MPU_MASK (1 << 0) /* Used by PM_L4PER_UART4_WKDEP */ #define OMAP4430_WKUPDEP_UART4_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_UART4_SDMA_MASK BITFIELD(3, 3) +#define OMAP4430_WKUPDEP_UART4_SDMA_MASK (1 << 3) /* Used by PM_L3INIT_UNIPRO1_WKDEP */ #define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK (1 << 1) /* Used by PM_L3INIT_UNIPRO1_WKDEP */ #define OMAP4430_WKUPDEP_UNIPRO1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK (1 << 0) /* Used by PM_L3INIT_USB_HOST_WKDEP */ #define OMAP4430_WKUPDEP_USB_HOST_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK (1 << 1) /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */ #define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK (1 << 1) /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */ #define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK (1 << 0) /* Used by PM_L3INIT_USB_HOST_WKDEP */ #define OMAP4430_WKUPDEP_USB_HOST_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK (1 << 0) /* Used by PM_L3INIT_USB_OTG_WKDEP */ #define OMAP4430_WKUPDEP_USB_OTG_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK (1 << 1) /* Used by PM_L3INIT_USB_OTG_WKDEP */ #define OMAP4430_WKUPDEP_USB_OTG_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK (1 << 0) /* Used by PM_L3INIT_USB_TLL_WKDEP */ #define OMAP4430_WKUPDEP_USB_TLL_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK (1 << 1) /* Used by PM_L3INIT_USB_TLL_WKDEP */ #define OMAP4430_WKUPDEP_USB_TLL_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK (1 << 0) /* Used by PM_WKUP_USIM_WKDEP */ #define OMAP4430_WKUPDEP_USIM_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_USIM_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_USIM_MPU_MASK (1 << 0) /* Used by PM_WKUP_USIM_WKDEP */ #define OMAP4430_WKUPDEP_USIM_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_USIM_SDMA_MASK BITFIELD(3, 3) +#define OMAP4430_WKUPDEP_USIM_SDMA_MASK (1 << 3) /* Used by PM_WKUP_WDT2_WKDEP */ #define OMAP4430_WKUPDEP_WDT2_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK (1 << 1) /* Used by PM_WKUP_WDT2_WKDEP */ #define OMAP4430_WKUPDEP_WDT2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_WDT2_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_WDT2_MPU_MASK (1 << 0) /* Used by PM_ABE_WDT3_WKDEP */ #define OMAP4430_WKUPDEP_WDT3_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_WDT3_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_WDT3_MPU_MASK (1 << 0) /* Used by PM_L3INIT_HSI_WKDEP */ #define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_SHIFT 8 -#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK BITFIELD(8, 8) +#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK (1 << 8) /* Used by PM_L3INIT_XHPI_WKDEP */ #define OMAP4430_WKUPDEP_XHPI_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK (1 << 1) /* Used by PRM_IO_PMCTRL */ #define OMAP4430_WUCLK_CTRL_SHIFT 8 -#define OMAP4430_WUCLK_CTRL_MASK BITFIELD(8, 8) +#define OMAP4430_WUCLK_CTRL_MASK (1 << 8) /* Used by PRM_IO_PMCTRL */ #define OMAP4430_WUCLK_STATUS_SHIFT 9 -#define OMAP4430_WUCLK_STATUS_MASK BITFIELD(9, 9) +#define OMAP4430_WUCLK_STATUS_MASK (1 << 9) + +/* Used by REVISION_PRM */ +#define OMAP4430_X_MAJOR_SHIFT 8 +#define OMAP4430_X_MAJOR_MASK (0x7 << 8) + +/* Used by REVISION_PRM */ +#define OMAP4430_Y_MINOR_SHIFT 0 +#define OMAP4430_Y_MINOR_MASK (0x3f << 0) #endif diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h index 588873b9303a..7be040b2fdab 100644 --- a/arch/arm/mach-omap2/prm.h +++ b/arch/arm/mach-omap2/prm.h @@ -5,7 +5,7 @@ * OMAP2/3 Power/Reset Management (PRM) register definitions * * Copyright (C) 2007-2009 Texas Instruments, Inc. - * Copyright (C) 2009 Nokia Corporation + * Copyright (C) 2010 Nokia Corporation * * Written by Paul Walmsley * @@ -246,6 +246,15 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) return prm_rmw_mod_reg_bits(bits, 0x0, module, idx); } +/* These omap2_ PRM functions apply to both OMAP2 and 3 */ +int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift); +int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift); +int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift); + +int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift); +int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift); +int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift); + #endif /* @@ -398,4 +407,11 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) #define OMAP_POWERSTATE_MASK (0x3 << 0) +/* + * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP + * submodule to exit hardreset + */ +#define MAX_MODULE_HARDRESET_WAIT 10000 + + #endif diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c new file mode 100644 index 000000000000..421771eee450 --- /dev/null +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c @@ -0,0 +1,110 @@ +/* + * OMAP2/3 PRM module functions + * + * Copyright (C) 2010 Texas Instruments, Inc. + * Copyright (C) 2010 Nokia Corporation + * Benoît Cousson + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/delay.h> +#include <linux/errno.h> +#include <linux/err.h> + +#include <plat/common.h> +#include <plat/cpu.h> +#include <plat/prcm.h> + +#include "prm.h" +#include "prm-regbits-24xx.h" +#include "prm-regbits-34xx.h" + +/** + * omap2_prm_is_hardreset_asserted - read the HW reset line state of + * submodules contained in the hwmod module + * @prm_mod: PRM submodule base (e.g. CORE_MOD) + * @shift: register bit shift corresponding to the reset line to check + * + * Returns 1 if the (sub)module hardreset line is currently asserted, + * 0 if the (sub)module hardreset line is not currently asserted, or + * -EINVAL if called while running on a non-OMAP2/3 chip. + */ +int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift) +{ + if (!(cpu_is_omap24xx() || cpu_is_omap34xx())) + return -EINVAL; + + return prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, + (1 << shift)); +} + +/** + * omap2_prm_assert_hardreset - assert the HW reset line of a submodule + * @prm_mod: PRM submodule base (e.g. CORE_MOD) + * @shift: register bit shift corresponding to the reset line to assert + * + * Some IPs like dsp or iva contain processors that require an HW + * reset line to be asserted / deasserted in order to fully enable the + * IP. These modules may have multiple hard-reset lines that reset + * different 'submodules' inside the IP block. This function will + * place the submodule into reset. Returns 0 upon success or -EINVAL + * upon an argument error. + */ +int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift) +{ + u32 mask; + + if (!(cpu_is_omap24xx() || cpu_is_omap34xx())) + return -EINVAL; + + mask = 1 << shift; + prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL); + + return 0; +} + +/** + * omap2_prm_deassert_hardreset - deassert a submodule hardreset line and wait + * @prm_mod: PRM submodule base (e.g. CORE_MOD) + * @shift: register bit shift corresponding to the reset line to deassert + * + * Some IPs like dsp or iva contain processors that require an HW + * reset line to be asserted / deasserted in order to fully enable the + * IP. These modules may have multiple hard-reset lines that reset + * different 'submodules' inside the IP block. This function will + * take the submodule out of reset and wait until the PRCM indicates + * that the reset has completed before returning. Returns 0 upon success or + * -EINVAL upon an argument error, -EEXIST if the submodule was already out + * of reset, or -EBUSY if the submodule did not exit reset promptly. + */ +int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift) +{ + u32 mask; + int c; + + if (!(cpu_is_omap24xx() || cpu_is_omap34xx())) + return -EINVAL; + + mask = 1 << shift; + + /* Check the current status to avoid de-asserting the line twice */ + if (prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, mask) == 0) + return -EEXIST; + + /* Clear the reset status by writing 1 to the status bit */ + prm_rmw_mod_reg_bits(0xffffffff, mask, prm_mod, OMAP2_RM_RSTST); + /* de-assert the reset control line */ + prm_rmw_mod_reg_bits(mask, 0, prm_mod, OMAP2_RM_RSTCTRL); + /* wait the status to be set */ + omap_test_timeout(prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTST, + mask), + MAX_MODULE_HARDRESET_WAIT, c); + + return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0; +} + diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c new file mode 100644 index 000000000000..a1ff918d9bed --- /dev/null +++ b/arch/arm/mach-omap2/prm44xx.c @@ -0,0 +1,116 @@ +/* + * OMAP4 PRM module functions + * + * Copyright (C) 2010 Texas Instruments, Inc. + * Copyright (C) 2010 Nokia Corporation + * Benoît Cousson + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/delay.h> +#include <linux/errno.h> +#include <linux/err.h> + +#include <plat/common.h> +#include <plat/cpu.h> +#include <plat/prcm.h> + +#include "prm.h" +#include "prm-regbits-44xx.h" + +/* + * Address offset (in bytes) between the reset control and the reset + * status registers: 4 bytes on OMAP4 + */ +#define OMAP4_RST_CTRL_ST_OFFSET 4 + +/** + * omap4_prm_is_hardreset_asserted - read the HW reset line state of + * submodules contained in the hwmod module + * @rstctrl_reg: RM_RSTCTRL register address for this module + * @shift: register bit shift corresponding to the reset line to check + * + * Returns 1 if the (sub)module hardreset line is currently asserted, + * 0 if the (sub)module hardreset line is not currently asserted, or + * -EINVAL upon parameter error. + */ +int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift) +{ + if (!cpu_is_omap44xx() || !rstctrl_reg) + return -EINVAL; + + return omap4_prm_read_bits_shift(rstctrl_reg, (1 << shift)); +} + +/** + * omap4_prm_assert_hardreset - assert the HW reset line of a submodule + * @rstctrl_reg: RM_RSTCTRL register address for this module + * @shift: register bit shift corresponding to the reset line to assert + * + * Some IPs like dsp, ipu or iva contain processors that require an HW + * reset line to be asserted / deasserted in order to fully enable the + * IP. These modules may have multiple hard-reset lines that reset + * different 'submodules' inside the IP block. This function will + * place the submodule into reset. Returns 0 upon success or -EINVAL + * upon an argument error. + */ +int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift) +{ + u32 mask; + + if (!cpu_is_omap44xx() || !rstctrl_reg) + return -EINVAL; + + mask = 1 << shift; + omap4_prm_rmw_reg_bits(mask, mask, rstctrl_reg); + + return 0; +} + +/** + * omap4_prm_deassert_hardreset - deassert a submodule hardreset line and wait + * @rstctrl_reg: RM_RSTCTRL register address for this module + * @shift: register bit shift corresponding to the reset line to deassert + * + * Some IPs like dsp, ipu or iva contain processors that require an HW + * reset line to be asserted / deasserted in order to fully enable the + * IP. These modules may have multiple hard-reset lines that reset + * different 'submodules' inside the IP block. This function will + * take the submodule out of reset and wait until the PRCM indicates + * that the reset has completed before returning. Returns 0 upon success or + * -EINVAL upon an argument error, -EEXIST if the submodule was already out + * of reset, or -EBUSY if the submodule did not exit reset promptly. + */ +int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift) +{ + u32 mask; + void __iomem *rstst_reg; + int c; + + if (!cpu_is_omap44xx() || !rstctrl_reg) + return -EINVAL; + + rstst_reg = rstctrl_reg + OMAP4_RST_CTRL_ST_OFFSET; + + mask = 1 << shift; + + /* Check the current status to avoid de-asserting the line twice */ + if (omap4_prm_read_bits_shift(rstctrl_reg, mask) == 0) + return -EEXIST; + + /* Clear the reset status by writing 1 to the status bit */ + omap4_prm_rmw_reg_bits(0xffffffff, mask, rstst_reg); + /* de-assert the reset control line */ + omap4_prm_rmw_reg_bits(mask, 0, rstctrl_reg); + /* wait the status to be set */ + omap_test_timeout(omap4_prm_read_bits_shift(rstst_reg, mask), + MAX_MODULE_HARDRESET_WAIT, c); + + return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0; +} + diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h index fe8ef26431e5..59839dbabd84 100644 --- a/arch/arm/mach-omap2/prm44xx.h +++ b/arch/arm/mach-omap2/prm44xx.h @@ -44,14 +44,12 @@ #define OMAP4430_PRM_IRQSTATUS_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0030) #define OMAP4_PRM_IRQENABLE_TESLA_OFFSET 0x0038 #define OMAP4430_PRM_IRQENABLE_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0038) -#define OMAP4_PRM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040 -#define OMAP4430_PRM_PRM_PROFILING_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0040) +#define OMAP4_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040 +#define OMAP4430_CM_PRM_PROFILING_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0040) /* PRM.CKGEN_PRM register offsets */ #define OMAP4_CM_ABE_DSS_SYS_CLKSEL_OFFSET 0x0000 #define OMAP4430_CM_ABE_DSS_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0000) -#define OMAP4_CM_DPLL_SYS_REF_CLKSEL_OFFSET 0x0004 -#define OMAP4430_CM_DPLL_SYS_REF_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0004) #define OMAP4_CM_L4_WKUP_CLKSEL_OFFSET 0x0008 #define OMAP4430_CM_L4_WKUP_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0008) #define OMAP4_CM_ABE_PLL_REF_CLKSEL_OFFSET 0x000c @@ -686,8 +684,8 @@ #define OMAP4430_PRM_LDO_ABB_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d8) #define OMAP4_PRM_LDO_ABB_IVA_CTRL_OFFSET 0x00dc #define OMAP4430_PRM_LDO_ABB_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00dc) -#define OMAP4_PRM_LDO_BANDGAP_CTRL_OFFSET 0x00e0 -#define OMAP4430_PRM_LDO_BANDGAP_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e0) +#define OMAP4_PRM_LDO_BANDGAP_SETUP_OFFSET 0x00e0 +#define OMAP4430_PRM_LDO_BANDGAP_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e0) #define OMAP4_PRM_DEVICE_OFF_CTRL_OFFSET 0x00e4 #define OMAP4430_PRM_DEVICE_OFF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e4) #define OMAP4_PRM_PHASE1_CNDP_OFFSET 0x00e8 @@ -698,6 +696,8 @@ #define OMAP4430_PRM_PHASE2B_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f0) #define OMAP4_PRM_MODEM_IF_CTRL_OFFSET 0x00f4 #define OMAP4430_PRM_MODEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f4) +#define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8 +#define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f8) /* * PRCM_MPU @@ -715,6 +715,8 @@ /* PRCM_MPU.DEVICE_PRM register offsets */ #define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000 #define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0000) +#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004 +#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0004) /* PRCM_MPU.CPU0 register offsets */ #define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000 diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 566e991ede81..becf0e38ef7e 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -19,20 +19,31 @@ */ #include <linux/kernel.h> #include <linux/init.h> -#include <linux/serial_8250.h> #include <linux/serial_reg.h> #include <linux/clk.h> #include <linux/io.h> #include <linux/delay.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/serial_8250.h> +#include <linux/pm_runtime.h> + +#ifdef CONFIG_SERIAL_OMAP +#include <plat/omap-serial.h> +#endif #include <plat/common.h> #include <plat/board.h> #include <plat/clock.h> -#include <plat/control.h> +#include <plat/dma.h> +#include <plat/omap_hwmod.h> +#include <plat/omap_device.h> #include "prm.h" #include "pm.h" +#include "cm.h" #include "prm-regbits-34xx.h" +#include "control.h" #define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52 #define UART_OMAP_WER 0x17 /* Wake-up enable register */ @@ -48,6 +59,8 @@ */ #define DEFAULT_TIMEOUT 0 +#define MAX_UART_HWMOD_NAME_LEN 16 + struct omap_uart_state { int num; int can_sleep; @@ -58,14 +71,21 @@ struct omap_uart_state { void __iomem *wk_en; u32 wk_mask; u32 padconf; + u32 dma_enabled; struct clk *ick; struct clk *fck; int clocked; - struct plat_serial8250_port *p; + int irq; + int regshift; + int irqflags; + void __iomem *membase; + resource_size_t mapbase; + struct list_head node; - struct platform_device pdev; + struct omap_hwmod *oh; + struct platform_device *pdev; u32 errata; #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) @@ -83,75 +103,47 @@ struct omap_uart_state { }; static LIST_HEAD(uart_list); +static u8 num_uarts; -static struct plat_serial8250_port serial_platform_data0[] = { - { - .irq = 72, - .flags = UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = OMAP24XX_BASE_BAUD * 16, - }, { - .flags = 0 - } -}; +/* + * Since these idle/enable hooks are used in the idle path itself + * which has interrupts disabled, use the non-locking versions of + * the hwmod enable/disable functions. + */ +static int uart_idle_hwmod(struct omap_device *od) +{ + _omap_hwmod_idle(od->hwmods[0]); -static struct plat_serial8250_port serial_platform_data1[] = { - { - .irq = 73, - .flags = UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = OMAP24XX_BASE_BAUD * 16, - }, { - .flags = 0 - } -}; + return 0; +} -static struct plat_serial8250_port serial_platform_data2[] = { - { - .irq = 74, - .flags = UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = OMAP24XX_BASE_BAUD * 16, - }, { - .flags = 0 - } -}; +static int uart_enable_hwmod(struct omap_device *od) +{ + _omap_hwmod_enable(od->hwmods[0]); -static struct plat_serial8250_port serial_platform_data3[] = { + return 0; +} + +static struct omap_device_pm_latency omap_uart_latency[] = { { - .irq = 70, - .flags = UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = OMAP24XX_BASE_BAUD * 16, - }, { - .flags = 0 - } + .deactivate_func = uart_idle_hwmod, + .activate_func = uart_enable_hwmod, + .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, + }, }; -void __init omap2_set_globals_uart(struct omap_globals *omap2_globals) -{ - serial_platform_data0[0].mapbase = omap2_globals->uart1_phys; - serial_platform_data1[0].mapbase = omap2_globals->uart2_phys; - serial_platform_data2[0].mapbase = omap2_globals->uart3_phys; - serial_platform_data3[0].mapbase = omap2_globals->uart4_phys; -} - static inline unsigned int __serial_read_reg(struct uart_port *up, - int offset) + int offset) { offset <<= up->regshift; return (unsigned int)__raw_readb(up->membase + offset); } -static inline unsigned int serial_read_reg(struct plat_serial8250_port *up, +static inline unsigned int serial_read_reg(struct omap_uart_state *uart, int offset) { - offset <<= up->regshift; - return (unsigned int)__raw_readb(up->membase + offset); + offset <<= uart->regshift; + return (unsigned int)__raw_readb(uart->membase + offset); } static inline void __serial_write_reg(struct uart_port *up, int offset, @@ -161,11 +153,11 @@ static inline void __serial_write_reg(struct uart_port *up, int offset, __raw_writeb(value, up->membase + offset); } -static inline void serial_write_reg(struct plat_serial8250_port *p, int offset, +static inline void serial_write_reg(struct omap_uart_state *uart, int offset, int value) { - offset <<= p->regshift; - __raw_writeb(value, p->membase + offset); + offset <<= uart->regshift; + __raw_writeb(value, uart->membase + offset); } /* @@ -173,14 +165,12 @@ static inline void serial_write_reg(struct plat_serial8250_port *p, int offset, * properly. Note that the TX watermark initialization may not be needed * once the 8250.c watermark handling code is merged. */ + static inline void __init omap_uart_reset(struct omap_uart_state *uart) { - struct plat_serial8250_port *p = uart->p; - - serial_write_reg(p, UART_OMAP_MDR1, 0x07); - serial_write_reg(p, UART_OMAP_SCR, 0x08); - serial_write_reg(p, UART_OMAP_MDR1, 0x00); - serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0)); + serial_write_reg(uart, UART_OMAP_MDR1, 0x07); + serial_write_reg(uart, UART_OMAP_SCR, 0x08); + serial_write_reg(uart, UART_OMAP_MDR1, 0x00); } #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) @@ -197,24 +187,23 @@ static inline void __init omap_uart_reset(struct omap_uart_state *uart) static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val, u8 fcr_val) { - struct plat_serial8250_port *p = uart->p; u8 timeout = 255; - serial_write_reg(p, UART_OMAP_MDR1, mdr1_val); + serial_write_reg(uart, UART_OMAP_MDR1, mdr1_val); udelay(2); - serial_write_reg(p, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT | + serial_write_reg(uart, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR); /* * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and * TX_FIFO_E bit is 1. */ - while (UART_LSR_THRE != (serial_read_reg(p, UART_LSR) & + while (UART_LSR_THRE != (serial_read_reg(uart, UART_LSR) & (UART_LSR_THRE | UART_LSR_DR))) { timeout--; if (!timeout) { /* Should *never* happen. we warn and carry on */ - dev_crit(&uart->pdev.dev, "Errata i202: timedout %x\n", - serial_read_reg(p, UART_LSR)); + dev_crit(&uart->pdev->dev, "Errata i202: timedout %x\n", + serial_read_reg(uart, UART_LSR)); break; } udelay(1); @@ -224,23 +213,22 @@ static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val, static void omap_uart_save_context(struct omap_uart_state *uart) { u16 lcr = 0; - struct plat_serial8250_port *p = uart->p; if (!enable_off_mode) return; - lcr = serial_read_reg(p, UART_LCR); - serial_write_reg(p, UART_LCR, 0xBF); - uart->dll = serial_read_reg(p, UART_DLL); - uart->dlh = serial_read_reg(p, UART_DLM); - serial_write_reg(p, UART_LCR, lcr); - uart->ier = serial_read_reg(p, UART_IER); - uart->sysc = serial_read_reg(p, UART_OMAP_SYSC); - uart->scr = serial_read_reg(p, UART_OMAP_SCR); - uart->wer = serial_read_reg(p, UART_OMAP_WER); - serial_write_reg(p, UART_LCR, 0x80); - uart->mcr = serial_read_reg(p, UART_MCR); - serial_write_reg(p, UART_LCR, lcr); + lcr = serial_read_reg(uart, UART_LCR); + serial_write_reg(uart, UART_LCR, 0xBF); + uart->dll = serial_read_reg(uart, UART_DLL); + uart->dlh = serial_read_reg(uart, UART_DLM); + serial_write_reg(uart, UART_LCR, lcr); + uart->ier = serial_read_reg(uart, UART_IER); + uart->sysc = serial_read_reg(uart, UART_OMAP_SYSC); + uart->scr = serial_read_reg(uart, UART_OMAP_SCR); + uart->wer = serial_read_reg(uart, UART_OMAP_WER); + serial_write_reg(uart, UART_LCR, 0x80); + uart->mcr = serial_read_reg(uart, UART_MCR); + serial_write_reg(uart, UART_LCR, lcr); uart->context_valid = 1; } @@ -248,7 +236,6 @@ static void omap_uart_save_context(struct omap_uart_state *uart) static void omap_uart_restore_context(struct omap_uart_state *uart) { u16 efr = 0; - struct plat_serial8250_port *p = uart->p; if (!enable_off_mode) return; @@ -261,29 +248,30 @@ static void omap_uart_restore_context(struct omap_uart_state *uart) if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS) omap_uart_mdr1_errataset(uart, 0x07, 0xA0); else - serial_write_reg(p, UART_OMAP_MDR1, 0x7); - serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ - efr = serial_read_reg(p, UART_EFR); - serial_write_reg(p, UART_EFR, UART_EFR_ECB); - serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */ - serial_write_reg(p, UART_IER, 0x0); - serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ - serial_write_reg(p, UART_DLL, uart->dll); - serial_write_reg(p, UART_DLM, uart->dlh); - serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */ - serial_write_reg(p, UART_IER, uart->ier); - serial_write_reg(p, UART_LCR, 0x80); - serial_write_reg(p, UART_MCR, uart->mcr); - serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ - serial_write_reg(p, UART_EFR, efr); - serial_write_reg(p, UART_LCR, UART_LCR_WLEN8); - serial_write_reg(p, UART_OMAP_SCR, uart->scr); - serial_write_reg(p, UART_OMAP_WER, uart->wer); - serial_write_reg(p, UART_OMAP_SYSC, uart->sysc); + serial_write_reg(uart, UART_OMAP_MDR1, 0x7); + serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */ + efr = serial_read_reg(uart, UART_EFR); + serial_write_reg(uart, UART_EFR, UART_EFR_ECB); + serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */ + serial_write_reg(uart, UART_IER, 0x0); + serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */ + serial_write_reg(uart, UART_DLL, uart->dll); + serial_write_reg(uart, UART_DLM, uart->dlh); + serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */ + serial_write_reg(uart, UART_IER, uart->ier); + serial_write_reg(uart, UART_LCR, 0x80); + serial_write_reg(uart, UART_MCR, uart->mcr); + serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */ + serial_write_reg(uart, UART_EFR, efr); + serial_write_reg(uart, UART_LCR, UART_LCR_WLEN8); + serial_write_reg(uart, UART_OMAP_SCR, uart->scr); + serial_write_reg(uart, UART_OMAP_WER, uart->wer); + serial_write_reg(uart, UART_OMAP_SYSC, uart->sysc); if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS) omap_uart_mdr1_errataset(uart, 0x00, 0xA1); else - serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */ + /* UART 16x mode */ + serial_write_reg(uart, UART_OMAP_MDR1, 0x00); } #else static inline void omap_uart_save_context(struct omap_uart_state *uart) {} @@ -295,8 +283,7 @@ static inline void omap_uart_enable_clocks(struct omap_uart_state *uart) if (uart->clocked) return; - clk_enable(uart->ick); - clk_enable(uart->fck); + omap_device_enable(uart->pdev); uart->clocked = 1; omap_uart_restore_context(uart); } @@ -310,8 +297,7 @@ static inline void omap_uart_disable_clocks(struct omap_uart_state *uart) omap_uart_save_context(uart); uart->clocked = 0; - clk_disable(uart->ick); - clk_disable(uart->fck); + omap_device_idle(uart->pdev); } static void omap_uart_enable_wakeup(struct omap_uart_state *uart) @@ -349,18 +335,24 @@ static void omap_uart_disable_wakeup(struct omap_uart_state *uart) } static void omap_uart_smart_idle_enable(struct omap_uart_state *uart, - int enable) + int enable) { - struct plat_serial8250_port *p = uart->p; - u16 sysc; + u8 idlemode; - sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7; - if (enable) - sysc |= 0x2 << 3; - else - sysc |= 0x1 << 3; + if (enable) { + /** + * Errata 2.15: [UART]:Cannot Acknowledge Idle Requests + * in Smartidle Mode When Configured for DMA Operations. + */ + if (uart->dma_enabled) + idlemode = HWMOD_IDLEMODE_FORCE; + else + idlemode = HWMOD_IDLEMODE_SMART; + } else { + idlemode = HWMOD_IDLEMODE_NO; + } - serial_write_reg(p, UART_OMAP_SYSC, sysc); + omap_hwmod_set_slave_idlemode(uart->oh, idlemode); } static void omap_uart_block_sleep(struct omap_uart_state *uart) @@ -377,7 +369,7 @@ static void omap_uart_block_sleep(struct omap_uart_state *uart) static void omap_uart_allow_sleep(struct omap_uart_state *uart) { - if (device_may_wakeup(&uart->pdev.dev)) + if (device_may_wakeup(&uart->pdev->dev)) omap_uart_enable_wakeup(uart); else omap_uart_disable_wakeup(uart); @@ -472,6 +464,7 @@ int omap_uart_can_sleep(void) * UART will not idle or sleep for its timeout period. * **/ +/* static int first_interrupt; */ static irqreturn_t omap_uart_interrupt(int irq, void *dev_id) { struct omap_uart_state *uart = dev_id; @@ -483,7 +476,6 @@ static irqreturn_t omap_uart_interrupt(int irq, void *dev_id) static void omap_uart_idle_init(struct omap_uart_state *uart) { - struct plat_serial8250_port *p = uart->p; int ret; uart->can_sleep = 0; @@ -495,7 +487,7 @@ static void omap_uart_idle_init(struct omap_uart_state *uart) omap_uart_smart_idle_enable(uart, 0); if (cpu_is_omap34xx()) { - u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD; + u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD; u32 wk_mask = 0; u32 padconf = 0; @@ -514,19 +506,17 @@ static void omap_uart_idle_init(struct omap_uart_state *uart) wk_mask = OMAP3430_ST_UART3_MASK; padconf = 0x19e; break; + case 3: + wk_mask = OMAP3630_ST_UART4_MASK; + padconf = 0x0d2; + break; } uart->wk_mask = wk_mask; uart->padconf = padconf; } else if (cpu_is_omap24xx()) { u32 wk_mask = 0; + u32 wk_en = PM_WKEN1, wk_st = PM_WKST1; - if (cpu_is_omap2430()) { - uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1); - uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1); - } else if (cpu_is_omap2420()) { - uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1); - uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1); - } switch (uart->num) { case 0: wk_mask = OMAP24XX_ST_UART1_MASK; @@ -535,10 +525,19 @@ static void omap_uart_idle_init(struct omap_uart_state *uart) wk_mask = OMAP24XX_ST_UART2_MASK; break; case 2: + wk_en = OMAP24XX_PM_WKEN2; + wk_st = OMAP24XX_PM_WKST2; wk_mask = OMAP24XX_ST_UART3_MASK; break; } uart->wk_mask = wk_mask; + if (cpu_is_omap2430()) { + uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, wk_en); + uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, wk_st); + } else if (cpu_is_omap2420()) { + uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, wk_en); + uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, wk_st); + } } else { uart->wk_en = NULL; uart->wk_st = NULL; @@ -546,9 +545,9 @@ static void omap_uart_idle_init(struct omap_uart_state *uart) uart->padconf = 0; } - p->irqflags |= IRQF_SHARED; - ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED, - "serial idle", (void *)uart); + uart->irqflags |= IRQF_SHARED; + ret = request_threaded_irq(uart->irq, NULL, omap_uart_interrupt, + IRQF_SHARED, "serial idle", (void *)uart); WARN_ON(ret); } @@ -558,11 +557,17 @@ void omap_uart_enable_irqs(int enable) struct omap_uart_state *uart; list_for_each_entry(uart, &uart_list, node) { - if (enable) - ret = request_irq(uart->p->irq, omap_uart_interrupt, - IRQF_SHARED, "serial idle", (void *)uart); - else - free_irq(uart->p->irq, (void *)uart); + if (enable) { + pm_runtime_put_sync(&uart->pdev->dev); + ret = request_threaded_irq(uart->irq, NULL, + omap_uart_interrupt, + IRQF_SHARED, + "serial idle", + (void *)uart); + } else { + pm_runtime_get_noresume(&uart->pdev->dev); + free_irq(uart->irq, (void *)uart); + } } } @@ -570,10 +575,9 @@ static ssize_t sleep_timeout_show(struct device *dev, struct device_attribute *attr, char *buf) { - struct platform_device *pdev = container_of(dev, - struct platform_device, dev); - struct omap_uart_state *uart = container_of(pdev, - struct omap_uart_state, pdev); + struct platform_device *pdev = to_platform_device(dev); + struct omap_device *odev = to_omap_device(pdev); + struct omap_uart_state *uart = odev->hwmods[0]->dev_attr; return sprintf(buf, "%u\n", uart->timeout / HZ); } @@ -582,10 +586,9 @@ static ssize_t sleep_timeout_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) { - struct platform_device *pdev = container_of(dev, - struct platform_device, dev); - struct omap_uart_state *uart = container_of(pdev, - struct omap_uart_state, pdev); + struct platform_device *pdev = to_platform_device(dev); + struct omap_device *odev = to_omap_device(pdev); + struct omap_uart_state *uart = odev->hwmods[0]->dev_attr; unsigned int value; if (sscanf(buf, "%u", &value) != 1) { @@ -608,48 +611,15 @@ static DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr)) #else static inline void omap_uart_idle_init(struct omap_uart_state *uart) {} +static void omap_uart_block_sleep(struct omap_uart_state *uart) +{ + /* Needed to enable UART clocks when built without CONFIG_PM */ + omap_uart_enable_clocks(uart); +} #define DEV_CREATE_FILE(dev, attr) #endif /* CONFIG_PM */ -static struct omap_uart_state omap_uart[] = { - { - .pdev = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = serial_platform_data0, - }, - }, - }, { - .pdev = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM1, - .dev = { - .platform_data = serial_platform_data1, - }, - }, - }, { - .pdev = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM2, - .dev = { - .platform_data = serial_platform_data2, - }, - }, - }, -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) - { - .pdev = { - .name = "serial8250", - .id = 3, - .dev = { - .platform_data = serial_platform_data3, - }, - }, - }, -#endif -}; - +#ifndef CONFIG_SERIAL_OMAP /* * Override the default 8250 read handler: mem_serial_in() * Empty RX fifo read causes an abort on omap3630 and omap4 @@ -682,71 +652,44 @@ static void serial_out_override(struct uart_port *up, int offset, int value) } __serial_write_reg(up, offset, value); } +#endif + void __init omap_serial_early_init(void) { - int i, nr_ports; - char name[16]; + int i = 0; - if (!(cpu_is_omap3630() || cpu_is_omap4430())) - nr_ports = 3; - else - nr_ports = ARRAY_SIZE(omap_uart); + do { + char oh_name[MAX_UART_HWMOD_NAME_LEN]; + struct omap_hwmod *oh; + struct omap_uart_state *uart; - /* - * Make sure the serial ports are muxed on at this point. - * You have to mux them off in device drivers later on - * if not needed. - */ + snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN, + "uart%d", i + 1); + oh = omap_hwmod_lookup(oh_name); + if (!oh) + break; - for (i = 0; i < nr_ports; i++) { - struct omap_uart_state *uart = &omap_uart[i]; - struct platform_device *pdev = &uart->pdev; - struct device *dev = &pdev->dev; - struct plat_serial8250_port *p = dev->platform_data; + uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL); + if (WARN_ON(!uart)) + return; + + uart->oh = oh; + uart->num = i++; + list_add_tail(&uart->node, &uart_list); + num_uarts++; - /* Don't map zero-based physical address */ - if (p->mapbase == 0) { - dev_warn(dev, "no physical address for uart#%d," - " so skipping early_init...\n", i); - continue; - } /* - * Module 4KB + L4 interconnect 4KB - * Static mapping, never released + * NOTE: omap_hwmod_init() has not yet been called, + * so no hwmod functions will work yet. */ - p->membase = ioremap(p->mapbase, SZ_8K); - if (!p->membase) { - dev_err(dev, "ioremap failed for uart%i\n", i + 1); - continue; - } - - sprintf(name, "uart%d_ick", i + 1); - uart->ick = clk_get(NULL, name); - if (IS_ERR(uart->ick)) { - dev_err(dev, "Could not get uart%d_ick\n", i + 1); - uart->ick = NULL; - } - sprintf(name, "uart%d_fck", i+1); - uart->fck = clk_get(NULL, name); - if (IS_ERR(uart->fck)) { - dev_err(dev, "Could not get uart%d_fck\n", i + 1); - uart->fck = NULL; - } - - /* FIXME: Remove this once the clkdev is ready */ - if (!cpu_is_omap44xx()) { - if (!uart->ick || !uart->fck) - continue; - } - - uart->num = i; - p->private_data = uart; - uart->p = p; - - if (cpu_is_omap44xx()) - p->irq += 32; - } + /* + * During UART early init, device need to be probed + * to determine SoC specific init before omap_device + * is ready. Therefore, don't allow idle here + */ + uart->oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET; + } while (1); } /** @@ -763,53 +706,135 @@ void __init omap_serial_early_init(void) void __init omap_serial_init_port(int port) { struct omap_uart_state *uart; - struct platform_device *pdev; - struct device *dev; - - BUG_ON(port < 0); - BUG_ON(port >= ARRAY_SIZE(omap_uart)); - - uart = &omap_uart[port]; - pdev = &uart->pdev; - dev = &pdev->dev; + struct omap_hwmod *oh; + struct omap_device *od; + void *pdata = NULL; + u32 pdata_size = 0; + char *name; +#ifndef CONFIG_SERIAL_OMAP + struct plat_serial8250_port ports[2] = { + {}, + {.flags = 0}, + }; + struct plat_serial8250_port *p = &ports[0]; +#else + struct omap_uart_port_info omap_up; +#endif - /* Don't proceed if there's no clocks available */ - if (unlikely(!uart->ick || !uart->fck)) { - WARN(1, "%s: can't init uart%d, no clocks available\n", - kobject_name(&dev->kobj), port); + if (WARN_ON(port < 0)) + return; + if (WARN_ON(port >= num_uarts)) return; - } - - omap_uart_enable_clocks(uart); - - omap_uart_reset(uart); - omap_uart_idle_init(uart); - list_add_tail(&uart->node, &uart_list); + list_for_each_entry(uart, &uart_list, node) + if (port == uart->num) + break; - if (WARN_ON(platform_device_register(pdev))) - return; + oh = uart->oh; + uart->dma_enabled = 0; +#ifndef CONFIG_SERIAL_OMAP + name = "serial8250"; - if ((cpu_is_omap34xx() && uart->padconf) || - (uart->wk_en && uart->wk_mask)) { - device_init_wakeup(dev, true); - DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout); - } + /* + * !! 8250 driver does not use standard IORESOURCE* It + * has it's own custom pdata that can be taken from + * the hwmod resource data. But, this needs to be + * done after the build. + * + * ?? does it have to be done before the register ?? + * YES, because platform_device_data_add() copies + * pdata, it does not use a pointer. + */ + p->flags = UPF_BOOT_AUTOCONF; + p->iotype = UPIO_MEM; + p->regshift = 2; + p->uartclk = OMAP24XX_BASE_BAUD * 16; + p->irq = oh->mpu_irqs[0].irq; + p->mapbase = oh->slaves[0]->addr->pa_start; + p->membase = omap_hwmod_get_mpu_rt_va(oh); + p->irqflags = IRQF_SHARED; + p->private_data = uart; /* * omap44xx: Never read empty UART fifo * omap3xxx: Never read empty UART fifo on UARTs * with IP rev >=0x52 */ + uart->regshift = p->regshift; + uart->membase = p->membase; if (cpu_is_omap44xx()) uart->errata |= UART_ERRATA_FIFO_FULL_ABORT; - else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF) + else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF) >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) uart->errata |= UART_ERRATA_FIFO_FULL_ABORT; if (uart->errata & UART_ERRATA_FIFO_FULL_ABORT) { - uart->p->serial_in = serial_in_override; - uart->p->serial_out = serial_out_override; + p->serial_in = serial_in_override; + p->serial_out = serial_out_override; + } + + pdata = &ports[0]; + pdata_size = 2 * sizeof(struct plat_serial8250_port); +#else + + name = DRIVER_NAME; + + omap_up.dma_enabled = uart->dma_enabled; + omap_up.uartclk = OMAP24XX_BASE_BAUD * 16; + omap_up.mapbase = oh->slaves[0]->addr->pa_start; + omap_up.membase = omap_hwmod_get_mpu_rt_va(oh); + omap_up.irqflags = IRQF_SHARED; + omap_up.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; + + pdata = &omap_up; + pdata_size = sizeof(struct omap_uart_port_info); +#endif + + if (WARN_ON(!oh)) + return; + + od = omap_device_build(name, uart->num, oh, pdata, pdata_size, + omap_uart_latency, + ARRAY_SIZE(omap_uart_latency), false); + WARN(IS_ERR(od), "Could not build omap_device for %s: %s.\n", + name, oh->name); + + uart->irq = oh->mpu_irqs[0].irq; + uart->regshift = 2; + uart->mapbase = oh->slaves[0]->addr->pa_start; + uart->membase = omap_hwmod_get_mpu_rt_va(oh); + uart->pdev = &od->pdev; + + oh->dev_attr = uart; + + /* + * Because of early UART probing, UART did not get idled + * on init. Now that omap_device is ready, ensure full idle + * before doing omap_device_enable(). + */ + omap_hwmod_idle(uart->oh); + + omap_device_enable(uart->pdev); + omap_uart_idle_init(uart); + omap_uart_reset(uart); + omap_hwmod_enable_wakeup(uart->oh); + omap_device_idle(uart->pdev); + + /* + * Need to block sleep long enough for interrupt driven + * driver to start. Console driver is in polling mode + * so device needs to be kept enabled while polling driver + * is in use. + */ + if (uart->timeout) + uart->timeout = (30 * HZ); + omap_uart_block_sleep(uart); + uart->timeout = DEFAULT_TIMEOUT; + + if ((cpu_is_omap34xx() && uart->padconf) || + (uart->wk_en && uart->wk_mask)) { + device_init_wakeup(&od->pdev.dev, true); + DEV_CREATE_FILE(&od->pdev.dev, &dev_attr_sleep_timeout); } /* Enable the MDR1 errata for OMAP3 */ @@ -826,13 +851,8 @@ void __init omap_serial_init_port(int port) */ void __init omap_serial_init(void) { - int i, nr_ports; - - if (!(cpu_is_omap3630() || cpu_is_omap4430())) - nr_ports = 3; - else - nr_ports = ARRAY_SIZE(omap_uart); + struct omap_uart_state *uart; - for (i = 0; i < nr_ports; i++) - omap_serial_init_port(i); + list_for_each_entry(uart, &uart_list, node) + omap_serial_init_port(uart->num); } diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S index ba53191ae4c5..2fb205a7f285 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S @@ -27,11 +27,11 @@ #include <linux/linkage.h> #include <asm/assembler.h> #include <mach/io.h> -#include <plat/control.h> #include "cm.h" #include "prm.h" #include "sdrc.h" +#include "control.h" #define SDRC_SCRATCHPAD_SEM_V 0xfa00291c diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S index de99ba2a57ab..3637274af5be 100644 --- a/arch/arm/mach-omap2/sram34xx.S +++ b/arch/arm/mach-omap2/sram34xx.S @@ -129,8 +129,11 @@ ENTRY(omap3_sram_configure_core_dpll) ldr r4, [sp, #80] str r4, omap_sdrc_mr_1_val skip_cs1_params: + mrc p15, 0, r8, c1, c0, 0 @ read ctrl register + bic r10, r8, #0x800 @ clear Z-bit, disable branch prediction + mcr p15, 0, r10, c1, c0, 0 @ write ctrl register dsb @ flush buffered writes to interconnect - + isb @ prevent speculative exec past here cmp r3, #1 @ if increasing SDRC clk rate, bleq configure_sdrc @ program the SDRC regs early (for RFR) cmp r1, #SDRC_UNLOCK_DLL @ set the intended DLL state @@ -148,6 +151,7 @@ skip_cs1_params: beq return_to_sdram @ return to SDRAM code, otherwise, bl configure_sdrc @ reprogram SDRC regs now return_to_sdram: + mcr p15, 0, r8, c1, c0, 0 @ restore ctrl register isb @ prevent speculative exec past here mov r0, #0 @ return value ldmfd sp!, {r1-r12, pc} @ restore regs and return diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c index 74fbed8491f2..e13c29eecf2b 100644 --- a/arch/arm/mach-omap2/timer-gp.c +++ b/arch/arm/mach-omap2/timer-gp.c @@ -40,6 +40,8 @@ #include <plat/dmtimer.h> #include <asm/localtimer.h> +#include "timer-gp.h" + /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */ #define MAX_GPTIMER_ID 12 @@ -228,8 +230,10 @@ static void __init omap2_gp_clocksource_init(void) static void __init omap2_gp_timer_init(void) { #ifdef CONFIG_LOCAL_TIMERS - twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256); - BUG_ON(!twd_base); + if (cpu_is_omap44xx()) { + twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256); + BUG_ON(!twd_base); + } #endif omap_dm_timer_init(); diff --git a/arch/arm/plat-omap/include/plat/timer-gp.h b/arch/arm/mach-omap2/timer-gp.h index c88d346b59d9..5c1072c6783b 100644 --- a/arch/arm/plat-omap/include/plat/timer-gp.h +++ b/arch/arm/mach-omap2/timer-gp.h @@ -11,7 +11,6 @@ #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H -int __init omap2_gp_clockevent_set_gptimer(u8 id); +extern int __init omap2_gp_clockevent_set_gptimer(u8 id); #endif - diff --git a/arch/arm/mach-omap2/usb-fs.c b/arch/arm/mach-omap2/usb-fs.c index a216d88b04b5..1481078763b8 100644 --- a/arch/arm/mach-omap2/usb-fs.c +++ b/arch/arm/mach-omap2/usb-fs.c @@ -29,18 +29,18 @@ #include <asm/irq.h> -#include <plat/control.h> #include <plat/usb.h> #include <plat/board.h> +#include "control.h" +#include "mux.h" + #define INT_USB_IRQ_GEN INT_24XX_USB_IRQ_GEN #define INT_USB_IRQ_NISO INT_24XX_USB_IRQ_NISO #define INT_USB_IRQ_ISO INT_24XX_USB_IRQ_ISO #define INT_USB_IRQ_HGEN INT_24XX_USB_IRQ_HGEN #define INT_USB_IRQ_OTG INT_24XX_USB_IRQ_OTG -#include "mux.h" - #if defined(CONFIG_ARCH_OMAP2) #ifdef CONFIG_USB_GADGET_OMAP diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c index 33a5cde1c227..72605584bfff 100644 --- a/arch/arm/mach-omap2/usb-musb.c +++ b/arch/arm/mach-omap2/usb-musb.c @@ -28,6 +28,7 @@ #include <mach/hardware.h> #include <mach/irqs.h> +#include <mach/am35xx.h> #include <plat/usb.h> #ifdef CONFIG_USB_MUSB_SOC @@ -89,6 +90,9 @@ void __init usb_musb_init(struct omap_musb_board_data *board_data) { if (cpu_is_omap243x()) { musb_resources[0].start = OMAP243X_HS_BASE; + } else if (cpu_is_omap3517() || cpu_is_omap3505()) { + musb_resources[0].start = AM35XX_IPSS_USBOTGSS_BASE; + musb_resources[1].start = INT_35XX_USBOTG_IRQ; } else if (cpu_is_omap34xx()) { musb_resources[0].start = OMAP34XX_HSUSB_OTG_BASE; } else if (cpu_is_omap44xx()) { diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c index 08b410343870..aaa1166df964 100644 --- a/arch/arm/mach-pxa/devices.c +++ b/arch/arm/mach-pxa/devices.c @@ -382,6 +382,31 @@ struct platform_device pxa_device_i2s = { .num_resources = ARRAY_SIZE(pxai2s_resources), }; +struct platform_device pxa_device_asoc_ssp1 = { + .name = "pxa-ssp-dai", + .id = 0, +}; + +struct platform_device pxa_device_asoc_ssp2= { + .name = "pxa-ssp-dai", + .id = 1, +}; + +struct platform_device pxa_device_asoc_ssp3 = { + .name = "pxa-ssp-dai", + .id = 2, +}; + +struct platform_device pxa_device_asoc_ssp4 = { + .name = "pxa-ssp-dai", + .id = 3, +}; + +struct platform_device pxa_device_asoc_platform = { + .name = "pxa-pcm-audio", + .id = -1, +}; + static u64 pxaficp_dmamask = ~(u32)0; struct platform_device pxa_device_ficp = { diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h index 715e8bd02e24..2fd5a8b35757 100644 --- a/arch/arm/mach-pxa/devices.h +++ b/arch/arm/mach-pxa/devices.h @@ -39,4 +39,10 @@ extern struct platform_device pxa3xx_device_i2c_power; extern struct platform_device pxa3xx_device_gcu; +extern struct platform_device pxa_device_asoc_platform; +extern struct platform_device pxa_device_asoc_ssp1; +extern struct platform_device pxa_device_asoc_ssp2; +extern struct platform_device pxa_device_asoc_ssp3; +extern struct platform_device pxa_device_asoc_ssp4; + void __init pxa_register_device(struct platform_device *dev, void *data); diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index 12e5b9f01e6f..d1fbf29d561c 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -385,6 +385,10 @@ static struct platform_device *devices[] __initdata = { &pxa27x_device_udc, &pxa_device_pmu, &pxa_device_i2s, + &pxa_device_asoc_ssp1, + &pxa_device_asoc_ssp2, + &pxa_device_asoc_ssp3, + &pxa_device_asoc_platform, &sa1100_device_rtc, &pxa_device_rtc, &pxa27x_device_ssp1, diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index c85c3a7abd31..d1c747cdacf8 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -593,6 +593,11 @@ static struct platform_device *devices[] __initdata = { &pxa27x_device_udc, &pxa_device_pmu, &pxa_device_i2s, + &pxa_device_asoc_ssp1, + &pxa_device_asoc_ssp2, + &pxa_device_asoc_ssp3, + &pxa_device_asoc_ssp4, + &pxa_device_asoc_platform, &sa1100_device_rtc, &pxa_device_rtc, &pxa27x_device_ssp1, diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c index f25fb6245bd7..702f7a68e87d 100644 --- a/arch/arm/mach-pxa/zylonite.c +++ b/arch/arm/mach-pxa/zylonite.c @@ -45,6 +45,16 @@ int wm9713_irq; int lcd_id; int lcd_orientation; +struct platform_device pxa_device_wm9713_audio = { + .name = "wm9713-codec", + .id = -1, +}; + +static void __init zylonite_init_wm9713_audio(void) +{ + platform_device_register(&pxa_device_wm9713_audio); +} + static struct resource smc91x_resources[] = { [0] = { .start = ZYLONITE_ETH_PHYS + 0x300, @@ -408,6 +418,7 @@ static void __init zylonite_init(void) zylonite_init_nand(); zylonite_init_leds(); zylonite_init_ohci(); + zylonite_init_wm9713_audio(); } MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)") diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c2440/mach-at2440evb.c index e3810c86a5e6..6c98b789b8c6 100644 --- a/arch/arm/mach-s3c2440/mach-at2440evb.c +++ b/arch/arm/mach-s3c2440/mach-at2440evb.c @@ -5,7 +5,7 @@ * and modifications by SBZ <sbz@spgui.org> and * Weibing <http://weibing.blogbus.com> * - * For product information, visit http://www.arm9e.com/ + * For product information, visit http://www.arm.com/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/arch/arm/mach-s3c64xx/dev-audio.c b/arch/arm/mach-s3c64xx/dev-audio.c index 9648fbc36eec..3838335f125b 100644 --- a/arch/arm/mach-s3c64xx/dev-audio.c +++ b/arch/arm/mach-s3c64xx/dev-audio.c @@ -43,8 +43,10 @@ static int s3c64xx_i2sv3_cfg_gpio(struct platform_device *pdev) s3c_gpio_cfgpin(S3C64XX_GPE(2), S3C64XX_GPE2_I2S1_LRCLK); s3c_gpio_cfgpin(S3C64XX_GPE(3), S3C64XX_GPE3_I2S1_DI); s3c_gpio_cfgpin(S3C64XX_GPE(4), S3C64XX_GPE4_I2S1_D0); + break; default: - printk(KERN_DEBUG "Invalid I2S Controller number!"); + printk(KERN_DEBUG "Invalid I2S Controller number: %d\n", + pdev->id); return -EINVAL; } @@ -184,7 +186,8 @@ static int s3c64xx_pcm_cfg_gpio(struct platform_device *pdev) s3c_gpio_cfgpin(S3C64XX_GPE(4), S3C64XX_GPE4_PCM1_SOUT); break; default: - printk(KERN_DEBUG "Invalid PCM Controller number!"); + printk(KERN_DEBUG "Invalid PCM Controller number: %d\n", + pdev->id); return -EINVAL; } @@ -333,3 +336,16 @@ void __init s3c64xx_ac97_setup_gpio(int num) else s3c_ac97_pdata.cfg_gpio = s3c64xx_ac97_cfg_gpe; } + +static u64 s3c_device_audio_dmamask = 0xffffffffUL; + +struct platform_device s3c_device_pcm = { + .name = "s3c24xx-pcm-audio", + .id = -1, + .dev = { + .dma_mask = &s3c_device_audio_dmamask, + .coherent_dma_mask = 0xffffffffUL + } +}; +EXPORT_SYMBOL(s3c_device_pcm); + diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c index ec8865c03a19..77488facfe4c 100644 --- a/arch/arm/mach-s3c64xx/mach-smdk6410.c +++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c @@ -283,6 +283,7 @@ static struct platform_device *smdk6410_devices[] __initdata = { &s3c_device_fb, &s3c_device_ohci, &s3c_device_usb_hsotg, + &s3c_device_pcm, &s3c64xx_device_iisv4, &samsung_device_keypad, diff --git a/arch/arm/mach-sa1100/Kconfig b/arch/arm/mach-sa1100/Kconfig index fd4c52b7ccb6..5da8c35aa0de 100644 --- a/arch/arm/mach-sa1100/Kconfig +++ b/arch/arm/mach-sa1100/Kconfig @@ -90,8 +90,8 @@ config SA1100_JORNADA720 # FIXME: select CPU_FREQ_SA11x0 help Say Y here if you want to build a kernel for the HP Jornada 720 - handheld computer. See <http://www.hp.com/jornada/products/720> - for details. + handheld computer. See + <http://h10025.www1.hp.com/ewfrf/wc/product?product=61677&cc=us&lc=en&dlc=en&product=61677#> config SA1100_JORNADA720_SSP bool "HP Jornada 720 Extended SSP driver" @@ -145,7 +145,7 @@ config SA1100_SIMPAD FLASH. The SL4 version got 64 MB RAM and 32 MB FLASH and a PCMCIA-Slot. The version for the Germany Telecom (DTAG) is the same like CL4 in additional it has a PCMCIA-Slot. For more information - visit <http://www.my-siemens.com/> or <http://www.siemens.ch/>. + visit <http://www.usa.siemens.com/> or <http://www.siemens.ch/>. config SA1100_SSP tristate "Generic PIO SSP" diff --git a/arch/arm/mach-sa1100/cpu-sa1100.c b/arch/arm/mach-sa1100/cpu-sa1100.c index ef817876a5d6..c0a13ef5436f 100644 --- a/arch/arm/mach-sa1100/cpu-sa1100.c +++ b/arch/arm/mach-sa1100/cpu-sa1100.c @@ -13,7 +13,7 @@ * This software has been developed while working on the LART * computing board (http://www.lartmaker.nl/), which is * sponsored by the Mobile Multi-media Communications - * (http://www.mmc.tudelft.nl/) and Ubiquitous Communications + * (http://www.mobimedia.org/) and Ubiquitous Communications * (http://www.ubicom.tudelft.nl/) projects. * * The authors can be reached at: diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index a57713c1954a..acd9552f8ada 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -16,6 +16,10 @@ config ARCH_TEGRA_2x_SOC endchoice +config TEGRA_PCI + bool "PCI Express support" + select PCI + comment "Tegra board type" config MACH_HARMONY @@ -47,4 +51,11 @@ config TEGRA_DEBUG_UARTE endchoice +config TEGRA_SYSTEM_DMA + bool "Enable system DMA driver for NVIDIA Tegra SoCs" + default y + help + Adds system DMA functionality for NVIDIA Tegra SoCs, used by + several Tegra device drivers + endif diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 51e9370eed99..cdbc68e4c0ca 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -1,14 +1,21 @@ obj-y += common.o obj-y += io.o -obj-y += irq.o +obj-y += irq.o legacy_irq.o obj-y += clock.o obj-y += timer.o obj-y += gpio.o obj-y += pinmux.o +obj-y += fuse.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clock.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o +obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_dvfs.o +obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pinmux-t2-tables.o obj-$(CONFIG_SMP) += platsmp.o localtimer.o headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o +obj-$(CONFIG_TEGRA_SYSTEM_DMA) += dma.o +obj-$(CONFIG_CPU_FREQ) += cpu-tegra.o +obj-$(CONFIG_TEGRA_PCI) += pcie.o obj-${CONFIG_MACH_HARMONY} += board-harmony.o obj-${CONFIG_MACH_HARMONY} += board-harmony-pinmux.o +obj-${CONFIG_MACH_HARMONY} += board-harmony-pcie.o diff --git a/arch/arm/mach-tegra/board-harmony-pcie.c b/arch/arm/mach-tegra/board-harmony-pcie.c new file mode 100644 index 000000000000..f7e7d4514b6a --- /dev/null +++ b/arch/arm/mach-tegra/board-harmony-pcie.c @@ -0,0 +1,57 @@ +/* + * arch/arm/mach-tegra/board-harmony-pcie.c + * + * Copyright (C) 2010 CompuLab, Ltd. + * Mike Rapoport <mike@compulab.co.il> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/kernel.h> +#include <linux/gpio.h> +#include <linux/err.h> +#include <linux/regulator/consumer.h> + +#include <asm/mach-types.h> + +#include <mach/pinmux.h> +#include "board.h" + +#ifdef CONFIG_TEGRA_PCI + +static int __init harmony_pcie_init(void) +{ + int err; + + if (!machine_is_harmony()) + return 0; + + tegra_pinmux_set_tristate(TEGRA_PINGROUP_GPV, TEGRA_TRI_NORMAL); + tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXA, TEGRA_TRI_NORMAL); + tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXK, TEGRA_TRI_NORMAL); + + err = tegra_pcie_init(true, true); + if (err) + goto err_pcie; + + return 0; + +err_pcie: + tegra_pinmux_set_tristate(TEGRA_PINGROUP_GPV, TEGRA_TRI_TRISTATE); + tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXA, TEGRA_TRI_TRISTATE); + tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXK, TEGRA_TRI_TRISTATE); + + return err; +} + +subsys_initcall(harmony_pcie_init); + +#endif diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h index 3d06354136f2..0de565ca37c5 100644 --- a/arch/arm/mach-tegra/board.h +++ b/arch/arm/mach-tegra/board.h @@ -27,6 +27,7 @@ void __init tegra_common_init(void); void __init tegra_map_common_io(void); void __init tegra_init_irq(void); void __init tegra_init_clock(void); +int __init tegra_pcie_init(bool init_port0, bool init_port1); extern struct sys_timer tegra_timer; #endif diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index 03ad578349b9..ae19f95585be 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -24,13 +24,80 @@ #include <linux/debugfs.h> #include <linux/slab.h> #include <linux/seq_file.h> +#include <linux/regulator/consumer.h> #include <asm/clkdev.h> #include "clock.h" +#include "board.h" +#include "fuse.h" static LIST_HEAD(clocks); static DEFINE_SPINLOCK(clock_lock); +static DEFINE_MUTEX(dvfs_lock); + +static int clk_is_dvfs(struct clk *c) +{ + return (c->dvfs != NULL); +}; + +static int dvfs_set_rate(struct dvfs *d, unsigned long rate) +{ + struct dvfs_table *t; + + if (d->table == NULL) + return -ENODEV; + + for (t = d->table; t->rate != 0; t++) { + if (rate <= t->rate) { + if (!d->reg) + return 0; + + return regulator_set_voltage(d->reg, + t->millivolts * 1000, + d->max_millivolts * 1000); + } + } + + return -EINVAL; +} + +static void dvfs_init(struct clk *c) +{ + int process_id; + int i; + struct dvfs_table *table; + + process_id = c->dvfs->cpu ? tegra_core_process_id() : + tegra_cpu_process_id(); + + for (i = 0; i < c->dvfs->process_id_table_length; i++) + if (process_id == c->dvfs->process_id_table[i].process_id) + c->dvfs->table = c->dvfs->process_id_table[i].table; + + if (c->dvfs->table == NULL) { + pr_err("Failed to find dvfs table for clock %s process %d\n", + c->name, process_id); + return; + } + + c->dvfs->max_millivolts = 0; + for (table = c->dvfs->table; table->rate != 0; table++) + if (c->dvfs->max_millivolts < table->millivolts) + c->dvfs->max_millivolts = table->millivolts; + + c->dvfs->reg = regulator_get(NULL, c->dvfs->reg_id); + + if (IS_ERR(c->dvfs->reg)) { + pr_err("Failed to get regulator %s for clock %s\n", + c->dvfs->reg_id, c->name); + c->dvfs->reg = NULL; + return; + } + + if (c->refcnt > 0) + dvfs_set_rate(c->dvfs, c->rate); +} struct clk *tegra_get_clock_by_name(const char *name) { @@ -48,14 +115,31 @@ struct clk *tegra_get_clock_by_name(const char *name) return ret; } +static void clk_recalculate_rate(struct clk *c) +{ + u64 rate; + + if (!c->parent) + return; + + rate = c->parent->rate; + + if (c->mul != 0 && c->div != 0) { + rate = rate * c->mul; + do_div(rate, c->div); + } + + if (rate > c->max_rate) + pr_warn("clocks: Set clock %s to rate %llu, max is %lu\n", + c->name, rate, c->max_rate); + + c->rate = rate; +} + int clk_reparent(struct clk *c, struct clk *parent) { pr_debug("%s: %s\n", __func__, c->name); - if (c->refcnt && c->parent) - clk_disable_locked(c->parent); c->parent = parent; - if (c->refcnt && c->parent) - clk_enable_locked(c->parent); list_del(&c->sibling); list_add_tail(&c->sibling, &parent->children); return 0; @@ -67,8 +151,7 @@ static void propagate_rate(struct clk *c) pr_debug("%s: %s\n", __func__, c->name); list_for_each_entry(clkp, &c->children, sibling) { pr_debug(" %s\n", clkp->name); - if (clkp->ops->recalculate_rate) - clkp->ops->recalculate_rate(clkp); + clk_recalculate_rate(clkp); propagate_rate(clkp); } } @@ -77,6 +160,8 @@ void clk_init(struct clk *c) { unsigned long flags; + pr_debug("%s: %s\n", __func__, c->name); + spin_lock_irqsave(&clock_lock, flags); INIT_LIST_HEAD(&c->children); @@ -85,6 +170,8 @@ void clk_init(struct clk *c) if (c->ops && c->ops->init) c->ops->init(c); + clk_recalculate_rate(c); + list_add(&c->node, &clocks); if (c->parent) @@ -122,13 +209,38 @@ int clk_enable_locked(struct clk *c) return 0; } +int clk_enable_cansleep(struct clk *c) +{ + int ret; + unsigned long flags; + + mutex_lock(&dvfs_lock); + + if (clk_is_dvfs(c) && c->refcnt > 0) + dvfs_set_rate(c->dvfs, c->rate); + + spin_lock_irqsave(&clock_lock, flags); + ret = clk_enable_locked(c); + spin_unlock_irqrestore(&clock_lock, flags); + + mutex_unlock(&dvfs_lock); + + return ret; +} +EXPORT_SYMBOL(clk_enable_cansleep); + int clk_enable(struct clk *c) { int ret; unsigned long flags; + + if (clk_is_dvfs(c)) + BUG(); + spin_lock_irqsave(&clock_lock, flags); ret = clk_enable_locked(c); spin_unlock_irqrestore(&clock_lock, flags); + return ret; } EXPORT_SYMBOL(clk_enable); @@ -152,9 +264,30 @@ void clk_disable_locked(struct clk *c) c->refcnt--; } +void clk_disable_cansleep(struct clk *c) +{ + unsigned long flags; + + mutex_lock(&dvfs_lock); + + spin_lock_irqsave(&clock_lock, flags); + clk_disable_locked(c); + spin_unlock_irqrestore(&clock_lock, flags); + + if (clk_is_dvfs(c) && c->refcnt == 0) + dvfs_set_rate(c->dvfs, c->rate); + + mutex_unlock(&dvfs_lock); +} +EXPORT_SYMBOL(clk_disable_cansleep); + void clk_disable(struct clk *c) { unsigned long flags; + + if (clk_is_dvfs(c)) + BUG(); + spin_lock_irqsave(&clock_lock, flags); clk_disable_locked(c); spin_unlock_irqrestore(&clock_lock, flags); @@ -175,6 +308,8 @@ int clk_set_parent_locked(struct clk *c, struct clk *parent) if (ret) return ret; + clk_recalculate_rate(c); + propagate_rate(c); return 0; @@ -197,22 +332,69 @@ struct clk *clk_get_parent(struct clk *c) } EXPORT_SYMBOL(clk_get_parent); -int clk_set_rate(struct clk *c, unsigned long rate) +int clk_set_rate_locked(struct clk *c, unsigned long rate) +{ + int ret; + + if (rate > c->max_rate) + rate = c->max_rate; + + if (!c->ops || !c->ops->set_rate) + return -ENOSYS; + + ret = c->ops->set_rate(c, rate); + + if (ret) + return ret; + + clk_recalculate_rate(c); + + propagate_rate(c); + + return 0; +} + +int clk_set_rate_cansleep(struct clk *c, unsigned long rate) { int ret = 0; unsigned long flags; + pr_debug("%s: %s\n", __func__, c->name); + + mutex_lock(&dvfs_lock); + + if (rate > c->rate) + ret = dvfs_set_rate(c->dvfs, rate); + if (ret) + goto out; + spin_lock_irqsave(&clock_lock, flags); + ret = clk_set_rate_locked(c, rate); + spin_unlock_irqrestore(&clock_lock, flags); - pr_debug("%s: %s\n", __func__, c->name); + if (ret) + goto out; - if (c->ops && c->ops->set_rate) - ret = c->ops->set_rate(c, rate); - else - ret = -ENOSYS; + ret = dvfs_set_rate(c->dvfs, rate); - propagate_rate(c); +out: + mutex_unlock(&dvfs_lock); + return ret; +} +EXPORT_SYMBOL(clk_set_rate_cansleep); + +int clk_set_rate(struct clk *c, unsigned long rate) +{ + int ret = 0; + unsigned long flags; + + pr_debug("%s: %s\n", __func__, c->name); + + if (clk_is_dvfs(c)) + BUG(); + spin_lock_irqsave(&clock_lock, flags); + ret = clk_set_rate_locked(c, rate); spin_unlock_irqrestore(&clock_lock, flags); return ret; @@ -235,6 +417,20 @@ unsigned long clk_get_rate(struct clk *c) } EXPORT_SYMBOL(clk_get_rate); +long clk_round_rate(struct clk *c, unsigned long rate) +{ + pr_debug("%s: %s\n", __func__, c->name); + + if (!c->ops || !c->ops->round_rate) + return -ENOSYS; + + if (rate > c->max_rate) + rate = c->max_rate; + + return c->ops->round_rate(c, rate); +} +EXPORT_SYMBOL(clk_round_rate); + static int tegra_clk_init_one_from_table(struct tegra_clk_init_table *table) { struct clk *c; @@ -308,13 +504,28 @@ void tegra_periph_reset_assert(struct clk *c) } EXPORT_SYMBOL(tegra_periph_reset_assert); -int __init tegra_init_clock(void) +void __init tegra_init_clock(void) { tegra2_init_clocks(); +} + +int __init tegra_init_dvfs(void) +{ + struct clk *c, *safe; + + mutex_lock(&dvfs_lock); + + list_for_each_entry_safe(c, safe, &clocks, node) + if (c->dvfs) + dvfs_init(c); + + mutex_unlock(&dvfs_lock); return 0; } +late_initcall(tegra_init_dvfs); + #ifdef CONFIG_DEBUG_FS static struct dentry *clk_debugfs_root; @@ -324,7 +535,7 @@ static void clock_tree_show_one(struct seq_file *s, struct clk *c, int level) struct clk *child; struct clk *safe; const char *state = "uninit"; - char div[5] = {0}; + char div[8] = {0}; if (c->state == ON) state = "on"; @@ -332,16 +543,26 @@ static void clock_tree_show_one(struct seq_file *s, struct clk *c, int level) state = "off"; if (c->mul != 0 && c->div != 0) { - BUG_ON(c->mul > 2); - if (c->mul > c->div) - snprintf(div, sizeof(div), "x%d", c->mul / c->div); - else + if (c->mul > c->div) { + int mul = c->mul / c->div; + int mul2 = (c->mul * 10 / c->div) % 10; + int mul3 = (c->mul * 10) % c->div; + if (mul2 == 0 && mul3 == 0) + snprintf(div, sizeof(div), "x%d", mul); + else if (mul3 == 0) + snprintf(div, sizeof(div), "x%d.%d", mul, mul2); + else + snprintf(div, sizeof(div), "x%d.%d..", mul, mul2); + } else { snprintf(div, sizeof(div), "%d%s", c->div / c->mul, (c->div % c->mul) ? ".5" : ""); + } } - seq_printf(s, "%*s%-*s %-6s %-3d %-5s %-10lu\n", - level * 3 + 1, c->set ? "" : "*", + seq_printf(s, "%*s%c%c%-*s %-6s %-3d %-8s %-10lu\n", + level * 3 + 1, "", + c->rate > c->max_rate ? '!' : ' ', + !c->set ? '*' : ' ', 30 - level * 3, c->name, state, c->refcnt, div, c->rate); list_for_each_entry_safe(child, safe, &c->children, sibling) { @@ -353,8 +574,8 @@ static int clock_tree_show(struct seq_file *s, void *data) { struct clk *c; unsigned long flags; - seq_printf(s, " clock state ref div rate \n"); - seq_printf(s, "-----------------------------------------------------------\n"); + seq_printf(s, " clock state ref div rate\n"); + seq_printf(s, "--------------------------------------------------------------\n"); spin_lock_irqsave(&clock_lock, flags); list_for_each_entry(c, &clocks, node) if (c->parent == NULL) diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h index af7c70e2a3ba..94fd859770f1 100644 --- a/arch/arm/mach-tegra/clock.h +++ b/arch/arm/mach-tegra/clock.h @@ -27,18 +27,43 @@ #define DIV_U71 (1 << 1) #define DIV_U71_FIXED (1 << 2) #define DIV_2 (1 << 3) -#define PLL_FIXED (1 << 4) -#define PLL_HAS_CPCON (1 << 5) -#define MUX (1 << 6) -#define PLLD (1 << 7) -#define PERIPH_NO_RESET (1 << 8) -#define PERIPH_NO_ENB (1 << 9) -#define PERIPH_EMC_ENB (1 << 10) -#define PERIPH_MANUAL_RESET (1 << 11) -#define PLL_ALT_MISC_REG (1 << 12) +#define DIV_U16 (1 << 4) +#define PLL_FIXED (1 << 5) +#define PLL_HAS_CPCON (1 << 6) +#define MUX (1 << 7) +#define PLLD (1 << 8) +#define PERIPH_NO_RESET (1 << 9) +#define PERIPH_NO_ENB (1 << 10) +#define PERIPH_EMC_ENB (1 << 11) +#define PERIPH_MANUAL_RESET (1 << 12) +#define PLL_ALT_MISC_REG (1 << 13) +#define PLLU (1 << 14) #define ENABLE_ON_INIT (1 << 28) struct clk; +struct regulator; + +struct dvfs_table { + unsigned long rate; + int millivolts; +}; + +struct dvfs_process_id_table { + int process_id; + struct dvfs_table *table; +}; + + +struct dvfs { + struct regulator *reg; + struct dvfs_table *table; + int max_millivolts; + + int process_id_table_length; + const char *reg_id; + bool cpu; + struct dvfs_process_id_table process_id_table[]; +}; struct clk_mux_sel { struct clk *input; @@ -58,12 +83,9 @@ struct clk_ops { void (*init)(struct clk *); int (*enable)(struct clk *); void (*disable)(struct clk *); - void (*recalc)(struct clk *); int (*set_parent)(struct clk *, struct clk *); int (*set_rate)(struct clk *, unsigned long); - unsigned long (*get_rate)(struct clk *); long (*round_rate)(struct clk *, unsigned long); - unsigned long (*recalculate_rate)(struct clk *); }; enum clk_state { @@ -85,6 +107,7 @@ struct clk { struct clk *parent; struct clk_lookup lookup; unsigned long rate; + unsigned long max_rate; u32 flags; u32 refcnt; const char *name; @@ -103,10 +126,6 @@ struct clk { unsigned long cf_max; unsigned long vco_min; unsigned long vco_max; - u32 m; - u32 n; - u32 p; - u32 cpcon; const struct clk_pll_table *pll_table; /* DIV */ @@ -117,6 +136,12 @@ struct clk { const struct clk_mux_sel *inputs; u32 sel; u32 reg_mask; + + /* Virtual cpu clock */ + struct clk *main; + struct clk *backup; + + struct dvfs *dvfs; }; @@ -141,6 +166,7 @@ unsigned long clk_measure_input_freq(void); void clk_disable_locked(struct clk *c); int clk_enable_locked(struct clk *c); int clk_set_parent_locked(struct clk *c, struct clk *parent); +int clk_set_rate_locked(struct clk *c, unsigned long rate); int clk_reparent(struct clk *c, struct clk *parent); void tegra_clk_init_from_table(struct tegra_clk_init_table *table); diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 039a514b61ef..7c91e2b9d643 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -19,13 +19,17 @@ #include <linux/init.h> #include <linux/io.h> +#include <linux/clk.h> +#include <linux/delay.h> #include <asm/hardware/cache-l2x0.h> #include <mach/iomap.h> +#include <mach/dma.h> #include "board.h" #include "clock.h" +#include "fuse.h" static __initdata struct tegra_clk_init_table common_clk_init_table[] = { /* name parent rate enabled */ @@ -35,8 +39,8 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = { { "pll_p_out2", "pll_p", 48000000, true }, { "pll_p_out3", "pll_p", 72000000, true }, { "pll_p_out4", "pll_p", 108000000, true }, - { "sys", "pll_p_out4", 108000000, true }, - { "hclk", "sys", 108000000, true }, + { "sclk", "pll_p_out4", 108000000, true }, + { "hclk", "sclk", 108000000, true }, { "pclk", "hclk", 54000000, true }, { NULL, NULL, 0, 0}, }; @@ -51,11 +55,16 @@ void __init tegra_init_cache(void) l2x0_init(p, 0x6C080001, 0x8200c3fe); #endif + } void __init tegra_common_init(void) { + tegra_init_fuse(); tegra_init_clock(); tegra_clk_init_from_table(common_clk_init_table); tegra_init_cache(); +#ifdef CONFIG_TEGRA_SYSTEM_DMA + tegra_dma_init(); +#endif } diff --git a/arch/arm/mach-tegra/cpu-tegra.c b/arch/arm/mach-tegra/cpu-tegra.c new file mode 100644 index 000000000000..fea5719c7072 --- /dev/null +++ b/arch/arm/mach-tegra/cpu-tegra.c @@ -0,0 +1,185 @@ +/* + * arch/arm/mach-tegra/cpu-tegra.c + * + * Copyright (C) 2010 Google, Inc. + * + * Author: + * Colin Cross <ccross@google.com> + * Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/types.h> +#include <linux/sched.h> +#include <linux/cpufreq.h> +#include <linux/delay.h> +#include <linux/init.h> +#include <linux/err.h> +#include <linux/clk.h> +#include <linux/io.h> + +#include <asm/system.h> + +#include <mach/hardware.h> +#include <mach/clk.h> + +/* Frequency table index must be sequential starting at 0 */ +static struct cpufreq_frequency_table freq_table[] = { + { 0, 312000 }, + { 1, 456000 }, + { 2, 608000 }, + { 3, 760000 }, + { 4, 816000 }, + { 5, 912000 }, + { 6, 1000000 }, + { 7, CPUFREQ_TABLE_END }, +}; + +#define NUM_CPUS 2 + +static struct clk *cpu_clk; + +static unsigned long target_cpu_speed[NUM_CPUS]; + +int tegra_verify_speed(struct cpufreq_policy *policy) +{ + return cpufreq_frequency_table_verify(policy, freq_table); +} + +unsigned int tegra_getspeed(unsigned int cpu) +{ + unsigned long rate; + + if (cpu >= NUM_CPUS) + return 0; + + rate = clk_get_rate(cpu_clk) / 1000; + return rate; +} + +static int tegra_update_cpu_speed(void) +{ + int i; + unsigned long rate = 0; + int ret = 0; + struct cpufreq_freqs freqs; + + for_each_online_cpu(i) + rate = max(rate, target_cpu_speed[i]); + + freqs.old = tegra_getspeed(0); + freqs.new = rate; + + if (freqs.old == freqs.new) + return ret; + + for_each_online_cpu(freqs.cpu) + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + +#ifdef CONFIG_CPU_FREQ_DEBUG + printk(KERN_DEBUG "cpufreq-tegra: transition: %u --> %u\n", + freqs.old, freqs.new); +#endif + + ret = clk_set_rate_cansleep(cpu_clk, freqs.new * 1000); + if (ret) { + pr_err("cpu-tegra: Failed to set cpu frequency to %d kHz\n", + freqs.new); + return ret; + } + + for_each_online_cpu(freqs.cpu) + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + + return 0; +} + +static int tegra_target(struct cpufreq_policy *policy, + unsigned int target_freq, + unsigned int relation) +{ + int idx; + unsigned int freq; + + cpufreq_frequency_table_target(policy, freq_table, target_freq, + relation, &idx); + + freq = freq_table[idx].frequency; + + target_cpu_speed[policy->cpu] = freq; + + return tegra_update_cpu_speed(); +} + +static int tegra_cpu_init(struct cpufreq_policy *policy) +{ + if (policy->cpu >= NUM_CPUS) + return -EINVAL; + + cpu_clk = clk_get_sys(NULL, "cpu"); + if (IS_ERR(cpu_clk)) + return PTR_ERR(cpu_clk); + + cpufreq_frequency_table_cpuinfo(policy, freq_table); + cpufreq_frequency_table_get_attr(freq_table, policy->cpu); + policy->cur = tegra_getspeed(policy->cpu); + target_cpu_speed[policy->cpu] = policy->cur; + + /* FIXME: what's the actual transition time? */ + policy->cpuinfo.transition_latency = 300 * 1000; + + policy->shared_type = CPUFREQ_SHARED_TYPE_ALL; + cpumask_copy(policy->related_cpus, cpu_possible_mask); + + return 0; +} + +static int tegra_cpu_exit(struct cpufreq_policy *policy) +{ + cpufreq_frequency_table_cpuinfo(policy, freq_table); + clk_put(cpu_clk); + return 0; +} + +static struct freq_attr *tegra_cpufreq_attr[] = { + &cpufreq_freq_attr_scaling_available_freqs, + NULL, +}; + +static struct cpufreq_driver tegra_cpufreq_driver = { + .verify = tegra_verify_speed, + .target = tegra_target, + .get = tegra_getspeed, + .init = tegra_cpu_init, + .exit = tegra_cpu_exit, + .name = "tegra", + .attr = tegra_cpufreq_attr, +}; + +static int __init tegra_cpufreq_init(void) +{ + return cpufreq_register_driver(&tegra_cpufreq_driver); +} + +static void __exit tegra_cpufreq_exit(void) +{ + cpufreq_unregister_driver(&tegra_cpufreq_driver); +} + + +MODULE_AUTHOR("Colin Cross <ccross@android.com>"); +MODULE_DESCRIPTION("cpufreq driver for Nvidia Tegra2"); +MODULE_LICENSE("GPL"); +module_init(tegra_cpufreq_init); +module_exit(tegra_cpufreq_exit); diff --git a/arch/arm/mach-tegra/dma.c b/arch/arm/mach-tegra/dma.c new file mode 100644 index 000000000000..edda6ec5e925 --- /dev/null +++ b/arch/arm/mach-tegra/dma.c @@ -0,0 +1,752 @@ +/* + * arch/arm/mach-tegra/dma.c + * + * System DMA driver for NVIDIA Tegra SoCs + * + * Copyright (c) 2008-2009, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#include <linux/io.h> +#include <linux/interrupt.h> +#include <linux/module.h> +#include <linux/spinlock.h> +#include <linux/err.h> +#include <linux/irq.h> +#include <linux/delay.h> +#include <mach/dma.h> +#include <mach/irqs.h> +#include <mach/iomap.h> + +#define APB_DMA_GEN 0x000 +#define GEN_ENABLE (1<<31) + +#define APB_DMA_CNTRL 0x010 + +#define APB_DMA_IRQ_MASK 0x01c + +#define APB_DMA_IRQ_MASK_SET 0x020 + +#define APB_DMA_CHAN_CSR 0x000 +#define CSR_ENB (1<<31) +#define CSR_IE_EOC (1<<30) +#define CSR_HOLD (1<<29) +#define CSR_DIR (1<<28) +#define CSR_ONCE (1<<27) +#define CSR_FLOW (1<<21) +#define CSR_REQ_SEL_SHIFT 16 +#define CSR_REQ_SEL_MASK (0x1F<<CSR_REQ_SEL_SHIFT) +#define CSR_REQ_SEL_INVALID (31<<CSR_REQ_SEL_SHIFT) +#define CSR_WCOUNT_SHIFT 2 +#define CSR_WCOUNT_MASK 0xFFFC + +#define APB_DMA_CHAN_STA 0x004 +#define STA_BUSY (1<<31) +#define STA_ISE_EOC (1<<30) +#define STA_HALT (1<<29) +#define STA_PING_PONG (1<<28) +#define STA_COUNT_SHIFT 2 +#define STA_COUNT_MASK 0xFFFC + +#define APB_DMA_CHAN_AHB_PTR 0x010 + +#define APB_DMA_CHAN_AHB_SEQ 0x014 +#define AHB_SEQ_INTR_ENB (1<<31) +#define AHB_SEQ_BUS_WIDTH_SHIFT 28 +#define AHB_SEQ_BUS_WIDTH_MASK (0x7<<AHB_SEQ_BUS_WIDTH_SHIFT) +#define AHB_SEQ_BUS_WIDTH_8 (0<<AHB_SEQ_BUS_WIDTH_SHIFT) +#define AHB_SEQ_BUS_WIDTH_16 (1<<AHB_SEQ_BUS_WIDTH_SHIFT) +#define AHB_SEQ_BUS_WIDTH_32 (2<<AHB_SEQ_BUS_WIDTH_SHIFT) +#define AHB_SEQ_BUS_WIDTH_64 (3<<AHB_SEQ_BUS_WIDTH_SHIFT) +#define AHB_SEQ_BUS_WIDTH_128 (4<<AHB_SEQ_BUS_WIDTH_SHIFT) +#define AHB_SEQ_DATA_SWAP (1<<27) +#define AHB_SEQ_BURST_MASK (0x7<<24) +#define AHB_SEQ_BURST_1 (4<<24) +#define AHB_SEQ_BURST_4 (5<<24) +#define AHB_SEQ_BURST_8 (6<<24) +#define AHB_SEQ_DBL_BUF (1<<19) +#define AHB_SEQ_WRAP_SHIFT 16 +#define AHB_SEQ_WRAP_MASK (0x7<<AHB_SEQ_WRAP_SHIFT) + +#define APB_DMA_CHAN_APB_PTR 0x018 + +#define APB_DMA_CHAN_APB_SEQ 0x01c +#define APB_SEQ_BUS_WIDTH_SHIFT 28 +#define APB_SEQ_BUS_WIDTH_MASK (0x7<<APB_SEQ_BUS_WIDTH_SHIFT) +#define APB_SEQ_BUS_WIDTH_8 (0<<APB_SEQ_BUS_WIDTH_SHIFT) +#define APB_SEQ_BUS_WIDTH_16 (1<<APB_SEQ_BUS_WIDTH_SHIFT) +#define APB_SEQ_BUS_WIDTH_32 (2<<APB_SEQ_BUS_WIDTH_SHIFT) +#define APB_SEQ_BUS_WIDTH_64 (3<<APB_SEQ_BUS_WIDTH_SHIFT) +#define APB_SEQ_BUS_WIDTH_128 (4<<APB_SEQ_BUS_WIDTH_SHIFT) +#define APB_SEQ_DATA_SWAP (1<<27) +#define APB_SEQ_WRAP_SHIFT 16 +#define APB_SEQ_WRAP_MASK (0x7<<APB_SEQ_WRAP_SHIFT) + +#define TEGRA_SYSTEM_DMA_CH_NR 16 +#define TEGRA_SYSTEM_DMA_AVP_CH_NUM 4 +#define TEGRA_SYSTEM_DMA_CH_MIN 0 +#define TEGRA_SYSTEM_DMA_CH_MAX \ + (TEGRA_SYSTEM_DMA_CH_NR - TEGRA_SYSTEM_DMA_AVP_CH_NUM - 1) + +#define NV_DMA_MAX_TRASFER_SIZE 0x10000 + +const unsigned int ahb_addr_wrap_table[8] = { + 0, 32, 64, 128, 256, 512, 1024, 2048 +}; + +const unsigned int apb_addr_wrap_table[8] = {0, 1, 2, 4, 8, 16, 32, 64}; + +const unsigned int bus_width_table[5] = {8, 16, 32, 64, 128}; + +#define TEGRA_DMA_NAME_SIZE 16 +struct tegra_dma_channel { + struct list_head list; + int id; + spinlock_t lock; + char name[TEGRA_DMA_NAME_SIZE]; + void __iomem *addr; + int mode; + int irq; + + /* Register shadow */ + u32 csr; + u32 ahb_seq; + u32 ahb_ptr; + u32 apb_seq; + u32 apb_ptr; +}; + +#define NV_DMA_MAX_CHANNELS 32 + +static DECLARE_BITMAP(channel_usage, NV_DMA_MAX_CHANNELS); +static struct tegra_dma_channel dma_channels[NV_DMA_MAX_CHANNELS]; + +static void tegra_dma_update_hw(struct tegra_dma_channel *ch, + struct tegra_dma_req *req); +static void tegra_dma_update_hw_partial(struct tegra_dma_channel *ch, + struct tegra_dma_req *req); +static void tegra_dma_init_hw(struct tegra_dma_channel *ch); +static void tegra_dma_stop(struct tegra_dma_channel *ch); + +void tegra_dma_flush(struct tegra_dma_channel *ch) +{ +} +EXPORT_SYMBOL(tegra_dma_flush); + +void tegra_dma_dequeue(struct tegra_dma_channel *ch) +{ + struct tegra_dma_req *req; + + req = list_entry(ch->list.next, typeof(*req), node); + + tegra_dma_dequeue_req(ch, req); + return; +} + +void tegra_dma_stop(struct tegra_dma_channel *ch) +{ + unsigned int csr; + unsigned int status; + + csr = ch->csr; + csr &= ~CSR_IE_EOC; + writel(csr, ch->addr + APB_DMA_CHAN_CSR); + + csr &= ~CSR_ENB; + writel(csr, ch->addr + APB_DMA_CHAN_CSR); + + status = readl(ch->addr + APB_DMA_CHAN_STA); + if (status & STA_ISE_EOC) + writel(status, ch->addr + APB_DMA_CHAN_STA); +} + +int tegra_dma_cancel(struct tegra_dma_channel *ch) +{ + unsigned int csr; + unsigned long irq_flags; + + spin_lock_irqsave(&ch->lock, irq_flags); + while (!list_empty(&ch->list)) + list_del(ch->list.next); + + csr = ch->csr; + csr &= ~CSR_REQ_SEL_MASK; + csr |= CSR_REQ_SEL_INVALID; + + /* Set the enable as that is not shadowed */ + csr |= CSR_ENB; + writel(csr, ch->addr + APB_DMA_CHAN_CSR); + + tegra_dma_stop(ch); + + spin_unlock_irqrestore(&ch->lock, irq_flags); + return 0; +} + +int tegra_dma_dequeue_req(struct tegra_dma_channel *ch, + struct tegra_dma_req *_req) +{ + unsigned int csr; + unsigned int status; + struct tegra_dma_req *req = NULL; + int found = 0; + unsigned long irq_flags; + int to_transfer; + int req_transfer_count; + + spin_lock_irqsave(&ch->lock, irq_flags); + list_for_each_entry(req, &ch->list, node) { + if (req == _req) { + list_del(&req->node); + found = 1; + break; + } + } + if (!found) { + spin_unlock_irqrestore(&ch->lock, irq_flags); + return 0; + } + + /* STOP the DMA and get the transfer count. + * Getting the transfer count is tricky. + * - Change the source selector to invalid to stop the DMA from + * FIFO to memory. + * - Read the status register to know the number of pending + * bytes to be transfered. + * - Finally stop or program the DMA to the next buffer in the + * list. + */ + csr = ch->csr; + csr &= ~CSR_REQ_SEL_MASK; + csr |= CSR_REQ_SEL_INVALID; + + /* Set the enable as that is not shadowed */ + csr |= CSR_ENB; + writel(csr, ch->addr + APB_DMA_CHAN_CSR); + + /* Get the transfer count */ + status = readl(ch->addr + APB_DMA_CHAN_STA); + to_transfer = (status & STA_COUNT_MASK) >> STA_COUNT_SHIFT; + req_transfer_count = (ch->csr & CSR_WCOUNT_MASK) >> CSR_WCOUNT_SHIFT; + req_transfer_count += 1; + to_transfer += 1; + + req->bytes_transferred = req_transfer_count; + + if (status & STA_BUSY) + req->bytes_transferred -= to_transfer; + + /* In continous transfer mode, DMA only tracks the count of the + * half DMA buffer. So, if the DMA already finished half the DMA + * then add the half buffer to the completed count. + * + * FIXME: There can be a race here. What if the req to + * dequue happens at the same time as the DMA just moved to + * the new buffer and SW didn't yet received the interrupt? + */ + if (ch->mode & TEGRA_DMA_MODE_CONTINOUS) + if (req->buffer_status == TEGRA_DMA_REQ_BUF_STATUS_HALF_FULL) + req->bytes_transferred += req_transfer_count; + + req->bytes_transferred *= 4; + + tegra_dma_stop(ch); + if (!list_empty(&ch->list)) { + /* if the list is not empty, queue the next request */ + struct tegra_dma_req *next_req; + next_req = list_entry(ch->list.next, + typeof(*next_req), node); + tegra_dma_update_hw(ch, next_req); + } + req->status = -TEGRA_DMA_REQ_ERROR_ABORTED; + + spin_unlock_irqrestore(&ch->lock, irq_flags); + + /* Callback should be called without any lock */ + req->complete(req); + return 0; +} +EXPORT_SYMBOL(tegra_dma_dequeue_req); + +bool tegra_dma_is_empty(struct tegra_dma_channel *ch) +{ + unsigned long irq_flags; + bool is_empty; + + spin_lock_irqsave(&ch->lock, irq_flags); + if (list_empty(&ch->list)) + is_empty = true; + else + is_empty = false; + spin_unlock_irqrestore(&ch->lock, irq_flags); + return is_empty; +} +EXPORT_SYMBOL(tegra_dma_is_empty); + +bool tegra_dma_is_req_inflight(struct tegra_dma_channel *ch, + struct tegra_dma_req *_req) +{ + unsigned long irq_flags; + struct tegra_dma_req *req; + + spin_lock_irqsave(&ch->lock, irq_flags); + list_for_each_entry(req, &ch->list, node) { + if (req == _req) { + spin_unlock_irqrestore(&ch->lock, irq_flags); + return true; + } + } + spin_unlock_irqrestore(&ch->lock, irq_flags); + return false; +} +EXPORT_SYMBOL(tegra_dma_is_req_inflight); + +int tegra_dma_enqueue_req(struct tegra_dma_channel *ch, + struct tegra_dma_req *req) +{ + unsigned long irq_flags; + int start_dma = 0; + + if (req->size > NV_DMA_MAX_TRASFER_SIZE || + req->source_addr & 0x3 || req->dest_addr & 0x3) { + pr_err("Invalid DMA request for channel %d\n", ch->id); + return -EINVAL; + } + + spin_lock_irqsave(&ch->lock, irq_flags); + + req->bytes_transferred = 0; + req->status = 0; + req->buffer_status = 0; + if (list_empty(&ch->list)) + start_dma = 1; + + list_add_tail(&req->node, &ch->list); + + if (start_dma) + tegra_dma_update_hw(ch, req); + + spin_unlock_irqrestore(&ch->lock, irq_flags); + + return 0; +} +EXPORT_SYMBOL(tegra_dma_enqueue_req); + +struct tegra_dma_channel *tegra_dma_allocate_channel(int mode) +{ + int channel; + struct tegra_dma_channel *ch; + + /* first channel is the shared channel */ + if (mode & TEGRA_DMA_SHARED) { + channel = TEGRA_SYSTEM_DMA_CH_MIN; + } else { + channel = find_first_zero_bit(channel_usage, + ARRAY_SIZE(dma_channels)); + if (channel >= ARRAY_SIZE(dma_channels)) + return NULL; + } + __set_bit(channel, channel_usage); + ch = &dma_channels[channel]; + ch->mode = mode; + return ch; +} +EXPORT_SYMBOL(tegra_dma_allocate_channel); + +void tegra_dma_free_channel(struct tegra_dma_channel *ch) +{ + if (ch->mode & TEGRA_DMA_SHARED) + return; + tegra_dma_cancel(ch); + __clear_bit(ch->id, channel_usage); +} +EXPORT_SYMBOL(tegra_dma_free_channel); + +static void tegra_dma_update_hw_partial(struct tegra_dma_channel *ch, + struct tegra_dma_req *req) +{ + if (req->to_memory) { + ch->apb_ptr = req->source_addr; + ch->ahb_ptr = req->dest_addr; + } else { + ch->apb_ptr = req->dest_addr; + ch->ahb_ptr = req->source_addr; + } + writel(ch->apb_ptr, ch->addr + APB_DMA_CHAN_APB_PTR); + writel(ch->ahb_ptr, ch->addr + APB_DMA_CHAN_AHB_PTR); + + req->status = TEGRA_DMA_REQ_INFLIGHT; + return; +} + +static void tegra_dma_update_hw(struct tegra_dma_channel *ch, + struct tegra_dma_req *req) +{ + int ahb_addr_wrap; + int apb_addr_wrap; + int ahb_bus_width; + int apb_bus_width; + int index; + unsigned long csr; + + + ch->csr |= CSR_FLOW; + ch->csr &= ~CSR_REQ_SEL_MASK; + ch->csr |= req->req_sel << CSR_REQ_SEL_SHIFT; + ch->ahb_seq &= ~AHB_SEQ_BURST_MASK; + ch->ahb_seq |= AHB_SEQ_BURST_1; + + /* One shot mode is always single buffered, + * continuous mode is always double buffered + * */ + if (ch->mode & TEGRA_DMA_MODE_ONESHOT) { + ch->csr |= CSR_ONCE; + ch->ahb_seq &= ~AHB_SEQ_DBL_BUF; + ch->csr &= ~CSR_WCOUNT_MASK; + ch->csr |= ((req->size>>2) - 1) << CSR_WCOUNT_SHIFT; + } else { + ch->csr &= ~CSR_ONCE; + ch->ahb_seq |= AHB_SEQ_DBL_BUF; + + /* In double buffered mode, we set the size to half the + * requested size and interrupt when half the buffer + * is full */ + ch->csr &= ~CSR_WCOUNT_MASK; + ch->csr |= ((req->size>>3) - 1) << CSR_WCOUNT_SHIFT; + } + + if (req->to_memory) { + ch->csr &= ~CSR_DIR; + ch->apb_ptr = req->source_addr; + ch->ahb_ptr = req->dest_addr; + + apb_addr_wrap = req->source_wrap; + ahb_addr_wrap = req->dest_wrap; + apb_bus_width = req->source_bus_width; + ahb_bus_width = req->dest_bus_width; + + } else { + ch->csr |= CSR_DIR; + ch->apb_ptr = req->dest_addr; + ch->ahb_ptr = req->source_addr; + + apb_addr_wrap = req->dest_wrap; + ahb_addr_wrap = req->source_wrap; + apb_bus_width = req->dest_bus_width; + ahb_bus_width = req->source_bus_width; + } + + apb_addr_wrap >>= 2; + ahb_addr_wrap >>= 2; + + /* set address wrap for APB size */ + index = 0; + do { + if (apb_addr_wrap_table[index] == apb_addr_wrap) + break; + index++; + } while (index < ARRAY_SIZE(apb_addr_wrap_table)); + BUG_ON(index == ARRAY_SIZE(apb_addr_wrap_table)); + ch->apb_seq &= ~APB_SEQ_WRAP_MASK; + ch->apb_seq |= index << APB_SEQ_WRAP_SHIFT; + + /* set address wrap for AHB size */ + index = 0; + do { + if (ahb_addr_wrap_table[index] == ahb_addr_wrap) + break; + index++; + } while (index < ARRAY_SIZE(ahb_addr_wrap_table)); + BUG_ON(index == ARRAY_SIZE(ahb_addr_wrap_table)); + ch->ahb_seq &= ~AHB_SEQ_WRAP_MASK; + ch->ahb_seq |= index << AHB_SEQ_WRAP_SHIFT; + + for (index = 0; index < ARRAY_SIZE(bus_width_table); index++) { + if (bus_width_table[index] == ahb_bus_width) + break; + } + BUG_ON(index == ARRAY_SIZE(bus_width_table)); + ch->ahb_seq &= ~AHB_SEQ_BUS_WIDTH_MASK; + ch->ahb_seq |= index << AHB_SEQ_BUS_WIDTH_SHIFT; + + for (index = 0; index < ARRAY_SIZE(bus_width_table); index++) { + if (bus_width_table[index] == apb_bus_width) + break; + } + BUG_ON(index == ARRAY_SIZE(bus_width_table)); + ch->apb_seq &= ~APB_SEQ_BUS_WIDTH_MASK; + ch->apb_seq |= index << APB_SEQ_BUS_WIDTH_SHIFT; + + ch->csr |= CSR_IE_EOC; + + /* update hw registers with the shadow */ + writel(ch->csr, ch->addr + APB_DMA_CHAN_CSR); + writel(ch->apb_seq, ch->addr + APB_DMA_CHAN_APB_SEQ); + writel(ch->apb_ptr, ch->addr + APB_DMA_CHAN_APB_PTR); + writel(ch->ahb_seq, ch->addr + APB_DMA_CHAN_AHB_SEQ); + writel(ch->ahb_ptr, ch->addr + APB_DMA_CHAN_AHB_PTR); + + csr = ch->csr | CSR_ENB; + writel(csr, ch->addr + APB_DMA_CHAN_CSR); + + req->status = TEGRA_DMA_REQ_INFLIGHT; +} + +static void tegra_dma_init_hw(struct tegra_dma_channel *ch) +{ + /* One shot with an interrupt to CPU after transfer */ + ch->csr = CSR_ONCE | CSR_IE_EOC; + ch->ahb_seq = AHB_SEQ_BUS_WIDTH_32 | AHB_SEQ_INTR_ENB; + ch->apb_seq = APB_SEQ_BUS_WIDTH_32 | 1 << APB_SEQ_WRAP_SHIFT; +} + +static void handle_oneshot_dma(struct tegra_dma_channel *ch) +{ + struct tegra_dma_req *req; + + spin_lock(&ch->lock); + if (list_empty(&ch->list)) { + spin_unlock(&ch->lock); + return; + } + + req = list_entry(ch->list.next, typeof(*req), node); + if (req) { + int bytes_transferred; + + bytes_transferred = + (ch->csr & CSR_WCOUNT_MASK) >> CSR_WCOUNT_SHIFT; + bytes_transferred += 1; + bytes_transferred <<= 2; + + list_del(&req->node); + req->bytes_transferred = bytes_transferred; + req->status = TEGRA_DMA_REQ_SUCCESS; + + spin_unlock(&ch->lock); + /* Callback should be called without any lock */ + pr_debug("%s: transferred %d bytes\n", __func__, + req->bytes_transferred); + req->complete(req); + spin_lock(&ch->lock); + } + + if (!list_empty(&ch->list)) { + req = list_entry(ch->list.next, typeof(*req), node); + /* the complete function we just called may have enqueued + another req, in which case dma has already started */ + if (req->status != TEGRA_DMA_REQ_INFLIGHT) + tegra_dma_update_hw(ch, req); + } + spin_unlock(&ch->lock); +} + +static void handle_continuous_dma(struct tegra_dma_channel *ch) +{ + struct tegra_dma_req *req; + + spin_lock(&ch->lock); + if (list_empty(&ch->list)) { + spin_unlock(&ch->lock); + return; + } + + req = list_entry(ch->list.next, typeof(*req), node); + if (req) { + if (req->buffer_status == TEGRA_DMA_REQ_BUF_STATUS_EMPTY) { + /* Load the next request into the hardware, if available + * */ + if (!list_is_last(&req->node, &ch->list)) { + struct tegra_dma_req *next_req; + + next_req = list_entry(req->node.next, + typeof(*next_req), node); + tegra_dma_update_hw_partial(ch, next_req); + } + req->buffer_status = TEGRA_DMA_REQ_BUF_STATUS_HALF_FULL; + req->status = TEGRA_DMA_REQ_SUCCESS; + /* DMA lock is NOT held when callback is called */ + spin_unlock(&ch->lock); + if (likely(req->threshold)) + req->threshold(req); + return; + + } else if (req->buffer_status == + TEGRA_DMA_REQ_BUF_STATUS_HALF_FULL) { + /* Callback when the buffer is completely full (i.e on + * the second interrupt */ + int bytes_transferred; + + bytes_transferred = + (ch->csr & CSR_WCOUNT_MASK) >> CSR_WCOUNT_SHIFT; + bytes_transferred += 1; + bytes_transferred <<= 3; + + req->buffer_status = TEGRA_DMA_REQ_BUF_STATUS_FULL; + req->bytes_transferred = bytes_transferred; + req->status = TEGRA_DMA_REQ_SUCCESS; + list_del(&req->node); + + /* DMA lock is NOT held when callbak is called */ + spin_unlock(&ch->lock); + req->complete(req); + return; + + } else { + BUG(); + } + } + spin_unlock(&ch->lock); +} + +static irqreturn_t dma_isr(int irq, void *data) +{ + struct tegra_dma_channel *ch = data; + unsigned long status; + + status = readl(ch->addr + APB_DMA_CHAN_STA); + if (status & STA_ISE_EOC) + writel(status, ch->addr + APB_DMA_CHAN_STA); + else { + pr_warning("Got a spurious ISR for DMA channel %d\n", ch->id); + return IRQ_HANDLED; + } + return IRQ_WAKE_THREAD; +} + +static irqreturn_t dma_thread_fn(int irq, void *data) +{ + struct tegra_dma_channel *ch = data; + + if (ch->mode & TEGRA_DMA_MODE_ONESHOT) + handle_oneshot_dma(ch); + else + handle_continuous_dma(ch); + + + return IRQ_HANDLED; +} + +int __init tegra_dma_init(void) +{ + int ret = 0; + int i; + unsigned int irq; + void __iomem *addr; + + addr = IO_ADDRESS(TEGRA_APB_DMA_BASE); + writel(GEN_ENABLE, addr + APB_DMA_GEN); + writel(0, addr + APB_DMA_CNTRL); + writel(0xFFFFFFFFul >> (31 - TEGRA_SYSTEM_DMA_CH_MAX), + addr + APB_DMA_IRQ_MASK_SET); + + memset(channel_usage, 0, sizeof(channel_usage)); + memset(dma_channels, 0, sizeof(dma_channels)); + + /* Reserve all the channels we are not supposed to touch */ + for (i = 0; i < TEGRA_SYSTEM_DMA_CH_MIN; i++) + __set_bit(i, channel_usage); + + for (i = TEGRA_SYSTEM_DMA_CH_MIN; i <= TEGRA_SYSTEM_DMA_CH_MAX; i++) { + struct tegra_dma_channel *ch = &dma_channels[i]; + + __clear_bit(i, channel_usage); + + ch->id = i; + snprintf(ch->name, TEGRA_DMA_NAME_SIZE, "dma_channel_%d", i); + + ch->addr = IO_ADDRESS(TEGRA_APB_DMA_CH0_BASE + + TEGRA_APB_DMA_CH0_SIZE * i); + + spin_lock_init(&ch->lock); + INIT_LIST_HEAD(&ch->list); + tegra_dma_init_hw(ch); + + irq = INT_APB_DMA_CH0 + i; + ret = request_threaded_irq(irq, dma_isr, dma_thread_fn, 0, + dma_channels[i].name, ch); + if (ret) { + pr_err("Failed to register IRQ %d for DMA %d\n", + irq, i); + goto fail; + } + ch->irq = irq; + } + /* mark the shared channel allocated */ + __set_bit(TEGRA_SYSTEM_DMA_CH_MIN, channel_usage); + + for (i = TEGRA_SYSTEM_DMA_CH_MAX+1; i < NV_DMA_MAX_CHANNELS; i++) + __set_bit(i, channel_usage); + + return ret; +fail: + writel(0, addr + APB_DMA_GEN); + for (i = TEGRA_SYSTEM_DMA_CH_MIN; i <= TEGRA_SYSTEM_DMA_CH_MAX; i++) { + struct tegra_dma_channel *ch = &dma_channels[i]; + if (ch->irq) + free_irq(ch->irq, ch); + } + return ret; +} + +#ifdef CONFIG_PM +static u32 apb_dma[5*TEGRA_SYSTEM_DMA_CH_NR + 3]; + +void tegra_dma_suspend(void) +{ + void __iomem *addr = IO_ADDRESS(TEGRA_APB_DMA_BASE); + u32 *ctx = apb_dma; + int i; + + *ctx++ = readl(addr + APB_DMA_GEN); + *ctx++ = readl(addr + APB_DMA_CNTRL); + *ctx++ = readl(addr + APB_DMA_IRQ_MASK); + + for (i = 0; i < TEGRA_SYSTEM_DMA_CH_NR; i++) { + addr = IO_ADDRESS(TEGRA_APB_DMA_CH0_BASE + + TEGRA_APB_DMA_CH0_SIZE * i); + + *ctx++ = readl(addr + APB_DMA_CHAN_CSR); + *ctx++ = readl(addr + APB_DMA_CHAN_AHB_PTR); + *ctx++ = readl(addr + APB_DMA_CHAN_AHB_SEQ); + *ctx++ = readl(addr + APB_DMA_CHAN_APB_PTR); + *ctx++ = readl(addr + APB_DMA_CHAN_APB_SEQ); + } +} + +void tegra_dma_resume(void) +{ + void __iomem *addr = IO_ADDRESS(TEGRA_APB_DMA_BASE); + u32 *ctx = apb_dma; + int i; + + writel(*ctx++, addr + APB_DMA_GEN); + writel(*ctx++, addr + APB_DMA_CNTRL); + writel(*ctx++, addr + APB_DMA_IRQ_MASK); + + for (i = 0; i < TEGRA_SYSTEM_DMA_CH_NR; i++) { + addr = IO_ADDRESS(TEGRA_APB_DMA_CH0_BASE + + TEGRA_APB_DMA_CH0_SIZE * i); + + writel(*ctx++, addr + APB_DMA_CHAN_CSR); + writel(*ctx++, addr + APB_DMA_CHAN_AHB_PTR); + writel(*ctx++, addr + APB_DMA_CHAN_AHB_SEQ); + writel(*ctx++, addr + APB_DMA_CHAN_APB_PTR); + writel(*ctx++, addr + APB_DMA_CHAN_APB_SEQ); + } +} + +#endif diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c new file mode 100644 index 000000000000..1fa26d9a1a68 --- /dev/null +++ b/arch/arm/mach-tegra/fuse.c @@ -0,0 +1,84 @@ +/* + * arch/arm/mach-tegra/fuse.c + * + * Copyright (C) 2010 Google, Inc. + * + * Author: + * Colin Cross <ccross@android.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/kernel.h> +#include <linux/io.h> + +#include <mach/iomap.h> + +#include "fuse.h" + +#define FUSE_UID_LOW 0x108 +#define FUSE_UID_HIGH 0x10c +#define FUSE_SKU_INFO 0x110 +#define FUSE_SPARE_BIT 0x200 + +static inline u32 fuse_readl(unsigned long offset) +{ + return readl(IO_TO_VIRT(TEGRA_FUSE_BASE + offset)); +} + +static inline void fuse_writel(u32 value, unsigned long offset) +{ + writel(value, IO_TO_VIRT(TEGRA_FUSE_BASE + offset)); +} + +void tegra_init_fuse(void) +{ + u32 reg = readl(IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48)); + reg |= 1 << 28; + writel(reg, IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48)); + + pr_info("Tegra SKU: %d CPU Process: %d Core Process: %d\n", + tegra_sku_id(), tegra_cpu_process_id(), + tegra_core_process_id()); +} + +unsigned long long tegra_chip_uid(void) +{ + unsigned long long lo, hi; + + lo = fuse_readl(FUSE_UID_LOW); + hi = fuse_readl(FUSE_UID_HIGH); + return (hi << 32ull) | lo; +} + +int tegra_sku_id(void) +{ + int sku_id; + u32 reg = fuse_readl(FUSE_SKU_INFO); + sku_id = reg & 0xFF; + return sku_id; +} + +int tegra_cpu_process_id(void) +{ + int cpu_process_id; + u32 reg = fuse_readl(FUSE_SPARE_BIT); + cpu_process_id = (reg >> 6) & 3; + return cpu_process_id; +} + +int tegra_core_process_id(void) +{ + int core_process_id; + u32 reg = fuse_readl(FUSE_SPARE_BIT); + core_process_id = (reg >> 12) & 3; + return core_process_id; +} diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h new file mode 100644 index 000000000000..584b2e27dbda --- /dev/null +++ b/arch/arm/mach-tegra/fuse.h @@ -0,0 +1,24 @@ +/* + * arch/arm/mach-tegra/fuse.c + * + * Copyright (C) 2010 Google, Inc. + * + * Author: + * Colin Cross <ccross@android.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +unsigned long long tegra_chip_uid(void); +int tegra_sku_id(void); +int tegra_cpu_process_id(void); +int tegra_core_process_id(void); +void tegra_init_fuse(void); diff --git a/arch/arm/mach-tegra/gpio.c b/arch/arm/mach-tegra/gpio.c index fe78fba25f3c..0775265e69f5 100644 --- a/arch/arm/mach-tegra/gpio.c +++ b/arch/arm/mach-tegra/gpio.c @@ -19,6 +19,7 @@ #include <linux/init.h> #include <linux/irq.h> +#include <linux/interrupt.h> #include <linux/io.h> #include <linux/gpio.h> @@ -60,6 +61,13 @@ struct tegra_gpio_bank { int bank; int irq; spinlock_t lvl_lock[4]; +#ifdef CONFIG_PM + u32 cnf[4]; + u32 out[4]; + u32 oe[4]; + u32 int_enb[4]; + u32 int_lvl[4]; +#endif }; @@ -131,7 +139,7 @@ static struct gpio_chip tegra_gpio_chip = { .direction_output = tegra_gpio_direction_output, .set = tegra_gpio_set, .base = 0, - .ngpio = ARCH_NR_GPIOS, + .ngpio = TEGRA_NR_GPIOS, }; static void tegra_gpio_irq_ack(unsigned int irq) @@ -244,6 +252,76 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) } +#ifdef CONFIG_PM +void tegra_gpio_resume(void) +{ + unsigned long flags; + int b, p, i; + + local_irq_save(flags); + + for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) { + struct tegra_gpio_bank *bank = &tegra_gpio_banks[b]; + + for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { + unsigned int gpio = (b<<5) | (p<<3); + __raw_writel(bank->cnf[p], GPIO_CNF(gpio)); + __raw_writel(bank->out[p], GPIO_OUT(gpio)); + __raw_writel(bank->oe[p], GPIO_OE(gpio)); + __raw_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio)); + __raw_writel(bank->int_enb[p], GPIO_INT_ENB(gpio)); + } + } + + local_irq_restore(flags); + + for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) { + struct irq_desc *desc = irq_to_desc(i); + if (!desc || (desc->status & IRQ_WAKEUP)) + continue; + enable_irq(i); + } +} + +void tegra_gpio_suspend(void) +{ + unsigned long flags; + int b, p, i; + + for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) { + struct irq_desc *desc = irq_to_desc(i); + if (!desc) + continue; + if (desc->status & IRQ_WAKEUP) { + int gpio = i - INT_GPIO_BASE; + pr_debug("gpio %d.%d is wakeup\n", gpio/8, gpio&7); + continue; + } + disable_irq(i); + } + + local_irq_save(flags); + for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) { + struct tegra_gpio_bank *bank = &tegra_gpio_banks[b]; + + for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { + unsigned int gpio = (b<<5) | (p<<3); + bank->cnf[p] = __raw_readl(GPIO_CNF(gpio)); + bank->out[p] = __raw_readl(GPIO_OUT(gpio)); + bank->oe[p] = __raw_readl(GPIO_OE(gpio)); + bank->int_enb[p] = __raw_readl(GPIO_INT_ENB(gpio)); + bank->int_lvl[p] = __raw_readl(GPIO_INT_LVL(gpio)); + } + } + local_irq_restore(flags); +} + +static int tegra_gpio_wake_enable(unsigned int irq, unsigned int enable) +{ + struct tegra_gpio_bank *bank = get_irq_chip_data(irq); + return set_irq_wake(bank->irq, enable); +} +#endif static struct irq_chip tegra_gpio_irq_chip = { .name = "GPIO", @@ -251,6 +329,9 @@ static struct irq_chip tegra_gpio_irq_chip = { .mask = tegra_gpio_irq_mask, .unmask = tegra_gpio_irq_unmask, .set_type = tegra_gpio_irq_set_type, +#ifdef CONFIG_PM + .set_wake = tegra_gpio_wake_enable, +#endif }; @@ -274,7 +355,7 @@ static int __init tegra_gpio_init(void) gpiochip_add(&tegra_gpio_chip); - for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + ARCH_NR_GPIOS); i++) { + for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) { bank = &tegra_gpio_banks[GPIO_BANK(irq_to_gpio(i))]; lockdep_set_class(&irq_desc[i].lock, &gpio_lock_class); @@ -312,15 +393,16 @@ static int dbg_gpio_show(struct seq_file *s, void *unused) for (i = 0; i < 7; i++) { for (j = 0; j < 4; j++) { int gpio = tegra_gpio_compose(i, j, 0); - seq_printf(s, "%d:%d %02x %02x %02x %02x %02x %02x %06x\n", - i, j, - __raw_readl(GPIO_CNF(gpio)), - __raw_readl(GPIO_OE(gpio)), - __raw_readl(GPIO_OUT(gpio)), - __raw_readl(GPIO_IN(gpio)), - __raw_readl(GPIO_INT_STA(gpio)), - __raw_readl(GPIO_INT_ENB(gpio)), - __raw_readl(GPIO_INT_LVL(gpio))); + seq_printf(s, + "%d:%d %02x %02x %02x %02x %02x %02x %06x\n", + i, j, + __raw_readl(GPIO_CNF(gpio)), + __raw_readl(GPIO_OE(gpio)), + __raw_readl(GPIO_OUT(gpio)), + __raw_readl(GPIO_IN(gpio)), + __raw_readl(GPIO_INT_STA(gpio)), + __raw_readl(GPIO_INT_ENB(gpio)), + __raw_readl(GPIO_INT_LVL(gpio))); } } return 0; diff --git a/arch/arm/mach-tegra/include/mach/clk.h b/arch/arm/mach-tegra/include/mach/clk.h index 2896f25ebfb5..d7723955dac7 100644 --- a/arch/arm/mach-tegra/include/mach/clk.h +++ b/arch/arm/mach-tegra/include/mach/clk.h @@ -23,4 +23,9 @@ void tegra_periph_reset_deassert(struct clk *c); void tegra_periph_reset_assert(struct clk *c); +int clk_enable_cansleep(struct clk *clk); +void clk_disable_cansleep(struct clk *clk); +int clk_set_rate_cansleep(struct clk *clk, unsigned long rate); +int clk_set_parent_cansleep(struct clk *clk, struct clk *parent); + #endif diff --git a/arch/arm/mach-tegra/include/mach/dma.h b/arch/arm/mach-tegra/include/mach/dma.h new file mode 100644 index 000000000000..39011bd9a925 --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/dma.h @@ -0,0 +1,155 @@ +/* + * arch/arm/mach-tegra/include/mach/dma.h + * + * Copyright (c) 2008-2009, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef __MACH_TEGRA_DMA_H +#define __MACH_TEGRA_DMA_H + +#include <linux/list.h> + +#if defined(CONFIG_TEGRA_SYSTEM_DMA) + +struct tegra_dma_req; +struct tegra_dma_channel; + +#define TEGRA_DMA_REQ_SEL_CNTR 0 +#define TEGRA_DMA_REQ_SEL_I2S_2 1 +#define TEGRA_DMA_REQ_SEL_I2S_1 2 +#define TEGRA_DMA_REQ_SEL_SPD_I 3 +#define TEGRA_DMA_REQ_SEL_UI_I 4 +#define TEGRA_DMA_REQ_SEL_MIPI 5 +#define TEGRA_DMA_REQ_SEL_I2S2_2 6 +#define TEGRA_DMA_REQ_SEL_I2S2_1 7 +#define TEGRA_DMA_REQ_SEL_UARTA 8 +#define TEGRA_DMA_REQ_SEL_UARTB 9 +#define TEGRA_DMA_REQ_SEL_UARTC 10 +#define TEGRA_DMA_REQ_SEL_SPI 11 +#define TEGRA_DMA_REQ_SEL_AC97 12 +#define TEGRA_DMA_REQ_SEL_ACMODEM 13 +#define TEGRA_DMA_REQ_SEL_SL4B 14 +#define TEGRA_DMA_REQ_SEL_SL2B1 15 +#define TEGRA_DMA_REQ_SEL_SL2B2 16 +#define TEGRA_DMA_REQ_SEL_SL2B3 17 +#define TEGRA_DMA_REQ_SEL_SL2B4 18 +#define TEGRA_DMA_REQ_SEL_UARTD 19 +#define TEGRA_DMA_REQ_SEL_UARTE 20 +#define TEGRA_DMA_REQ_SEL_I2C 21 +#define TEGRA_DMA_REQ_SEL_I2C2 22 +#define TEGRA_DMA_REQ_SEL_I2C3 23 +#define TEGRA_DMA_REQ_SEL_DVC_I2C 24 +#define TEGRA_DMA_REQ_SEL_OWR 25 +#define TEGRA_DMA_REQ_SEL_INVALID 31 + +enum tegra_dma_mode { + TEGRA_DMA_SHARED = 1, + TEGRA_DMA_MODE_CONTINOUS = 2, + TEGRA_DMA_MODE_ONESHOT = 4, +}; + +enum tegra_dma_req_error { + TEGRA_DMA_REQ_SUCCESS = 0, + TEGRA_DMA_REQ_ERROR_ABORTED, + TEGRA_DMA_REQ_INFLIGHT, +}; + +enum tegra_dma_req_buff_status { + TEGRA_DMA_REQ_BUF_STATUS_EMPTY = 0, + TEGRA_DMA_REQ_BUF_STATUS_HALF_FULL, + TEGRA_DMA_REQ_BUF_STATUS_FULL, +}; + +struct tegra_dma_req { + struct list_head node; + unsigned int modid; + int instance; + + /* Called when the req is complete and from the DMA ISR context. + * When this is called the req structure is no longer queued by + * the DMA channel. + * + * State of the DMA depends on the number of req it has. If there are + * no DMA requests queued up, then it will STOP the DMA. It there are + * more requests in the DMA, then it will queue the next request. + */ + void (*complete)(struct tegra_dma_req *req); + + /* This is a called from the DMA ISR context when the DMA is still in + * progress and is actively filling same buffer. + * + * In case of continous mode receive, this threshold is 1/2 the buffer + * size. In other cases, this will not even be called as there is no + * hardware support for it. + * + * In the case of continous mode receive, if there is next req already + * queued, DMA programs the HW to use that req when this req is + * completed. If there is no "next req" queued, then DMA ISR doesn't do + * anything before calling this callback. + * + * This is mainly used by the cases, where the clients has queued + * only one req and want to get some sort of DMA threshold + * callback to program the next buffer. + * + */ + void (*threshold)(struct tegra_dma_req *req); + + /* 1 to copy to memory. + * 0 to copy from the memory to device FIFO */ + int to_memory; + + void *virt_addr; + + unsigned long source_addr; + unsigned long dest_addr; + unsigned long dest_wrap; + unsigned long source_wrap; + unsigned long source_bus_width; + unsigned long dest_bus_width; + unsigned long req_sel; + unsigned int size; + + /* Updated by the DMA driver on the conpletion of the request. */ + int bytes_transferred; + int status; + + /* DMA completion tracking information */ + int buffer_status; + + /* Client specific data */ + void *dev; +}; + +int tegra_dma_enqueue_req(struct tegra_dma_channel *ch, + struct tegra_dma_req *req); +int tegra_dma_dequeue_req(struct tegra_dma_channel *ch, + struct tegra_dma_req *req); +void tegra_dma_dequeue(struct tegra_dma_channel *ch); +void tegra_dma_flush(struct tegra_dma_channel *ch); + +bool tegra_dma_is_req_inflight(struct tegra_dma_channel *ch, + struct tegra_dma_req *req); +bool tegra_dma_is_empty(struct tegra_dma_channel *ch); + +struct tegra_dma_channel *tegra_dma_allocate_channel(int mode); +void tegra_dma_free_channel(struct tegra_dma_channel *ch); + +int __init tegra_dma_init(void); + +#endif + +#endif diff --git a/arch/arm/mach-tegra/include/mach/gpio.h b/arch/arm/mach-tegra/include/mach/gpio.h index 540e822e50f7..e31f486d69a2 100644 --- a/arch/arm/mach-tegra/include/mach/gpio.h +++ b/arch/arm/mach-tegra/include/mach/gpio.h @@ -22,7 +22,7 @@ #include <mach/irqs.h> -#define ARCH_NR_GPIOS INT_GPIO_NR +#define TEGRA_NR_GPIOS INT_GPIO_NR #include <asm-generic/gpio.h> @@ -35,7 +35,7 @@ static inline int gpio_to_irq(unsigned int gpio) { - if (gpio < ARCH_NR_GPIOS) + if (gpio < TEGRA_NR_GPIOS) return INT_GPIO_BASE + gpio; return -EINVAL; } diff --git a/arch/arm/mach-tegra/include/mach/hardware.h b/arch/arm/mach-tegra/include/mach/hardware.h index 6014edf60d93..56e43b3a5b97 100644 --- a/arch/arm/mach-tegra/include/mach/hardware.h +++ b/arch/arm/mach-tegra/include/mach/hardware.h @@ -21,4 +21,8 @@ #ifndef __MACH_TEGRA_HARDWARE_H #define __MACH_TEGRA_HARDWARE_H +#define PCIBIOS_MIN_IO 0x1000 +#define PCIBIOS_MIN_MEM 0 +#define pcibios_assign_all_busses() 1 + #endif diff --git a/arch/arm/mach-tegra/include/mach/io.h b/arch/arm/mach-tegra/include/mach/io.h index 35edfc32ffc9..f0981b1ac59e 100644 --- a/arch/arm/mach-tegra/include/mach/io.h +++ b/arch/arm/mach-tegra/include/mach/io.h @@ -21,7 +21,7 @@ #ifndef __MACH_TEGRA_IO_H #define __MACH_TEGRA_IO_H -#define IO_SPACE_LIMIT 0xffffffff +#define IO_SPACE_LIMIT 0xffff /* On TEGRA, many peripherals are very closely packed in * two 256MB io windows (that actually only use about 64KB @@ -33,6 +33,10 @@ * */ +#define IO_IRAM_PHYS 0x40000000 +#define IO_IRAM_VIRT 0xFE400000 +#define IO_IRAM_SIZE SZ_256K + #define IO_CPU_PHYS 0x50040000 #define IO_CPU_VIRT 0xFE000000 #define IO_CPU_SIZE SZ_16K @@ -55,6 +59,8 @@ IO_TO_VIRT_XLATE((n), IO_APB_PHYS, IO_APB_VIRT) : \ IO_TO_VIRT_BETWEEN((n), IO_CPU_PHYS, IO_CPU_SIZE) ? \ IO_TO_VIRT_XLATE((n), IO_CPU_PHYS, IO_CPU_VIRT) : \ + IO_TO_VIRT_BETWEEN((n), IO_IRAM_PHYS, IO_IRAM_SIZE) ? \ + IO_TO_VIRT_XLATE((n), IO_IRAM_PHYS, IO_IRAM_VIRT) : \ 0) #ifndef __ASSEMBLER__ @@ -67,10 +73,20 @@ void tegra_iounmap(volatile void __iomem *addr); #define IO_ADDRESS(n) ((void __iomem *) IO_TO_VIRT(n)) +#ifdef CONFIG_TEGRA_PCI +extern void __iomem *tegra_pcie_io_base; + +static inline void __iomem *__io(unsigned long addr) +{ + return tegra_pcie_io_base + (addr & IO_SPACE_LIMIT); +} +#else static inline void __iomem *__io(unsigned long addr) { return (void __iomem *)addr; } +#endif + #define __io(a) __io(a) #define __mem_pci(a) (a) diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h index 1741f7dd7a9b..44a4f4bcf91f 100644 --- a/arch/arm/mach-tegra/include/mach/iomap.h +++ b/arch/arm/mach-tegra/include/mach/iomap.h @@ -23,9 +23,15 @@ #include <asm/sizes.h> +#define TEGRA_IRAM_BASE 0x40000000 +#define TEGRA_IRAM_SIZE SZ_256K + #define TEGRA_ARM_PERIF_BASE 0x50040000 #define TEGRA_ARM_PERIF_SIZE SZ_8K +#define TEGRA_ARM_PL310_BASE 0x50043000 +#define TEGRA_ARM_PL310_SIZE SZ_4K + #define TEGRA_ARM_INT_DIST_BASE 0x50041000 #define TEGRA_ARM_INT_DIST_SIZE SZ_4K @@ -68,7 +74,22 @@ #define TEGRA_FLOW_CTRL_BASE 0x60007000 #define TEGRA_FLOW_CTRL_SIZE 20 -#define TEGRA_STATMON_BASE 0x6000C4000 +#define TEGRA_AHB_DMA_BASE 0x60008000 +#define TEGRA_AHB_DMA_SIZE SZ_4K + +#define TEGRA_AHB_DMA_CH0_BASE 0x60009000 +#define TEGRA_AHB_DMA_CH0_SIZE 32 + +#define TEGRA_APB_DMA_BASE 0x6000A000 +#define TEGRA_APB_DMA_SIZE SZ_4K + +#define TEGRA_APB_DMA_CH0_BASE 0x6000B000 +#define TEGRA_APB_DMA_CH0_SIZE 32 + +#define TEGRA_AHB_GIZMO_BASE 0x6000C004 +#define TEGRA_AHB_GIZMO_SIZE 0x10C + +#define TEGRA_STATMON_BASE 0x6000C400 #define TEGRA_STATMON_SIZE SZ_1K #define TEGRA_GPIO_BASE 0x6000D000 @@ -137,7 +158,7 @@ #define TEGRA_I2C3_BASE 0x7000C500 #define TEGRA_I2C3_SIZE SZ_256 -#define TEGRA_OWR_BASE 0x7000D000 +#define TEGRA_OWR_BASE 0x7000C600 #define TEGRA_OWR_SIZE 80 #define TEGRA_DVC_BASE 0x7000D000 @@ -182,12 +203,12 @@ #define TEGRA_USB_BASE 0xC5000000 #define TEGRA_USB_SIZE SZ_16K -#define TEGRA_USB1_BASE 0xC5004000 -#define TEGRA_USB1_SIZE SZ_16K - -#define TEGRA_USB2_BASE 0xC5008000 +#define TEGRA_USB2_BASE 0xC5004000 #define TEGRA_USB2_SIZE SZ_16K +#define TEGRA_USB3_BASE 0xC5008000 +#define TEGRA_USB3_SIZE SZ_16K + #define TEGRA_SDMMC1_BASE 0xC8000000 #define TEGRA_SDMMC1_SIZE SZ_512 diff --git a/arch/arm/mach-tegra/include/mach/irqs.h b/arch/arm/mach-tegra/include/mach/irqs.h index 20f640edaa0d..71bbf3422953 100644 --- a/arch/arm/mach-tegra/include/mach/irqs.h +++ b/arch/arm/mach-tegra/include/mach/irqs.h @@ -25,6 +25,7 @@ #define IRQ_LOCALTIMER 29 +#ifdef CONFIG_ARCH_TEGRA_2x_SOC /* Primary Interrupt Controller */ #define INT_PRI_BASE (INT_GIC_BASE + 32) #define INT_TMR1 (INT_PRI_BASE + 0) @@ -169,5 +170,6 @@ #define INT_GPIO_NR (28 * 8) #define NR_IRQS (INT_GPIO_BASE + INT_GPIO_NR) +#endif #endif diff --git a/arch/arm/mach-tegra/include/mach/legacy_irq.h b/arch/arm/mach-tegra/include/mach/legacy_irq.h new file mode 100644 index 000000000000..db1eb3dd04c8 --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/legacy_irq.h @@ -0,0 +1,31 @@ +/* + * arch/arm/mach-tegra/include/mach/legacy_irq.h + * + * Copyright (C) 2010 Google, Inc. + * Author: Colin Cross <ccross@android.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _ARCH_ARM_MACH_TEGRA_LEGARY_IRQ_H +#define _ARCH_ARM_MACH_TEGRA_LEGARY_IRQ_H + +void tegra_legacy_mask_irq(unsigned int irq); +void tegra_legacy_unmask_irq(unsigned int irq); +void tegra_legacy_select_fiq(unsigned int irq, bool fiq); +void tegra_legacy_force_irq_set(unsigned int irq); +void tegra_legacy_force_irq_clr(unsigned int irq); +int tegra_legacy_force_irq_status(unsigned int irq); +void tegra_legacy_select_fiq(unsigned int irq, bool fiq); +unsigned long tegra_legacy_vfiq(int nr); +unsigned long tegra_legacy_class(int nr); + +#endif diff --git a/arch/arm/mach-tegra/include/mach/pinmux-t2.h b/arch/arm/mach-tegra/include/mach/pinmux-t2.h new file mode 100644 index 000000000000..e5b9d740f973 --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/pinmux-t2.h @@ -0,0 +1,174 @@ +/* + * linux/arch/arm/mach-tegra/include/mach/pinmux-t2.h + * + * Copyright (C) 2010 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __MACH_TEGRA_PINMUX_T2_H +#define __MACH_TEGRA_PINMUX_T2_H + +enum tegra_pingroup { + TEGRA_PINGROUP_ATA = 0, + TEGRA_PINGROUP_ATB, + TEGRA_PINGROUP_ATC, + TEGRA_PINGROUP_ATD, + TEGRA_PINGROUP_ATE, + TEGRA_PINGROUP_CDEV1, + TEGRA_PINGROUP_CDEV2, + TEGRA_PINGROUP_CRTP, + TEGRA_PINGROUP_CSUS, + TEGRA_PINGROUP_DAP1, + TEGRA_PINGROUP_DAP2, + TEGRA_PINGROUP_DAP3, + TEGRA_PINGROUP_DAP4, + TEGRA_PINGROUP_DDC, + TEGRA_PINGROUP_DTA, + TEGRA_PINGROUP_DTB, + TEGRA_PINGROUP_DTC, + TEGRA_PINGROUP_DTD, + TEGRA_PINGROUP_DTE, + TEGRA_PINGROUP_DTF, + TEGRA_PINGROUP_GMA, + TEGRA_PINGROUP_GMB, + TEGRA_PINGROUP_GMC, + TEGRA_PINGROUP_GMD, + TEGRA_PINGROUP_GME, + TEGRA_PINGROUP_GPU, + TEGRA_PINGROUP_GPU7, + TEGRA_PINGROUP_GPV, + TEGRA_PINGROUP_HDINT, + TEGRA_PINGROUP_I2CP, + TEGRA_PINGROUP_IRRX, + TEGRA_PINGROUP_IRTX, + TEGRA_PINGROUP_KBCA, + TEGRA_PINGROUP_KBCB, + TEGRA_PINGROUP_KBCC, + TEGRA_PINGROUP_KBCD, + TEGRA_PINGROUP_KBCE, + TEGRA_PINGROUP_KBCF, + TEGRA_PINGROUP_LCSN, + TEGRA_PINGROUP_LD0, + TEGRA_PINGROUP_LD1, + TEGRA_PINGROUP_LD10, + TEGRA_PINGROUP_LD11, + TEGRA_PINGROUP_LD12, + TEGRA_PINGROUP_LD13, + TEGRA_PINGROUP_LD14, + TEGRA_PINGROUP_LD15, + TEGRA_PINGROUP_LD16, + TEGRA_PINGROUP_LD17, + TEGRA_PINGROUP_LD2, + TEGRA_PINGROUP_LD3, + TEGRA_PINGROUP_LD4, + TEGRA_PINGROUP_LD5, + TEGRA_PINGROUP_LD6, + TEGRA_PINGROUP_LD7, + TEGRA_PINGROUP_LD8, + TEGRA_PINGROUP_LD9, + TEGRA_PINGROUP_LDC, + TEGRA_PINGROUP_LDI, + TEGRA_PINGROUP_LHP0, + TEGRA_PINGROUP_LHP1, + TEGRA_PINGROUP_LHP2, + TEGRA_PINGROUP_LHS, + TEGRA_PINGROUP_LM0, + TEGRA_PINGROUP_LM1, + TEGRA_PINGROUP_LPP, + TEGRA_PINGROUP_LPW0, + TEGRA_PINGROUP_LPW1, + TEGRA_PINGROUP_LPW2, + TEGRA_PINGROUP_LSC0, + TEGRA_PINGROUP_LSC1, + TEGRA_PINGROUP_LSCK, + TEGRA_PINGROUP_LSDA, + TEGRA_PINGROUP_LSDI, + TEGRA_PINGROUP_LSPI, + TEGRA_PINGROUP_LVP0, + TEGRA_PINGROUP_LVP1, + TEGRA_PINGROUP_LVS, + TEGRA_PINGROUP_OWC, + TEGRA_PINGROUP_PMC, + TEGRA_PINGROUP_PTA, + TEGRA_PINGROUP_RM, + TEGRA_PINGROUP_SDB, + TEGRA_PINGROUP_SDC, + TEGRA_PINGROUP_SDD, + TEGRA_PINGROUP_SDIO1, + TEGRA_PINGROUP_SLXA, + TEGRA_PINGROUP_SLXC, + TEGRA_PINGROUP_SLXD, + TEGRA_PINGROUP_SLXK, + TEGRA_PINGROUP_SPDI, + TEGRA_PINGROUP_SPDO, + TEGRA_PINGROUP_SPIA, + TEGRA_PINGROUP_SPIB, + TEGRA_PINGROUP_SPIC, + TEGRA_PINGROUP_SPID, + TEGRA_PINGROUP_SPIE, + TEGRA_PINGROUP_SPIF, + TEGRA_PINGROUP_SPIG, + TEGRA_PINGROUP_SPIH, + TEGRA_PINGROUP_UAA, + TEGRA_PINGROUP_UAB, + TEGRA_PINGROUP_UAC, + TEGRA_PINGROUP_UAD, + TEGRA_PINGROUP_UCA, + TEGRA_PINGROUP_UCB, + TEGRA_PINGROUP_UDA, + /* these pin groups only have pullup and pull down control */ + TEGRA_PINGROUP_CK32, + TEGRA_PINGROUP_DDRC, + TEGRA_PINGROUP_PMCA, + TEGRA_PINGROUP_PMCB, + TEGRA_PINGROUP_PMCC, + TEGRA_PINGROUP_PMCD, + TEGRA_PINGROUP_PMCE, + TEGRA_PINGROUP_XM2C, + TEGRA_PINGROUP_XM2D, + TEGRA_MAX_PINGROUP, +}; + +enum tegra_drive_pingroup { + TEGRA_DRIVE_PINGROUP_AO1 = 0, + TEGRA_DRIVE_PINGROUP_AO2, + TEGRA_DRIVE_PINGROUP_AT1, + TEGRA_DRIVE_PINGROUP_AT2, + TEGRA_DRIVE_PINGROUP_CDEV1, + TEGRA_DRIVE_PINGROUP_CDEV2, + TEGRA_DRIVE_PINGROUP_CSUS, + TEGRA_DRIVE_PINGROUP_DAP1, + TEGRA_DRIVE_PINGROUP_DAP2, + TEGRA_DRIVE_PINGROUP_DAP3, + TEGRA_DRIVE_PINGROUP_DAP4, + TEGRA_DRIVE_PINGROUP_DBG, + TEGRA_DRIVE_PINGROUP_LCD1, + TEGRA_DRIVE_PINGROUP_LCD2, + TEGRA_DRIVE_PINGROUP_SDMMC2, + TEGRA_DRIVE_PINGROUP_SDMMC3, + TEGRA_DRIVE_PINGROUP_SPI, + TEGRA_DRIVE_PINGROUP_UAA, + TEGRA_DRIVE_PINGROUP_UAB, + TEGRA_DRIVE_PINGROUP_UART2, + TEGRA_DRIVE_PINGROUP_UART3, + TEGRA_DRIVE_PINGROUP_VI1, + TEGRA_DRIVE_PINGROUP_VI2, + TEGRA_DRIVE_PINGROUP_XM2A, + TEGRA_DRIVE_PINGROUP_XM2C, + TEGRA_DRIVE_PINGROUP_XM2D, + TEGRA_DRIVE_PINGROUP_XM2CLK, + TEGRA_DRIVE_PINGROUP_MEMCOMP, + TEGRA_MAX_DRIVE_PINGROUP, +}; + +#endif + diff --git a/arch/arm/mach-tegra/include/mach/pinmux.h b/arch/arm/mach-tegra/include/mach/pinmux.h index 41c8ce5b7c27..defd8775defa 100644 --- a/arch/arm/mach-tegra/include/mach/pinmux.h +++ b/arch/arm/mach-tegra/include/mach/pinmux.h @@ -17,126 +17,11 @@ #ifndef __MACH_TEGRA_PINMUX_H #define __MACH_TEGRA_PINMUX_H -enum tegra_pingroup { - TEGRA_PINGROUP_ATA = 0, - TEGRA_PINGROUP_ATB, - TEGRA_PINGROUP_ATC, - TEGRA_PINGROUP_ATD, - TEGRA_PINGROUP_ATE, - TEGRA_PINGROUP_CDEV1, - TEGRA_PINGROUP_CDEV2, - TEGRA_PINGROUP_CRTP, - TEGRA_PINGROUP_CSUS, - TEGRA_PINGROUP_DAP1, - TEGRA_PINGROUP_DAP2, - TEGRA_PINGROUP_DAP3, - TEGRA_PINGROUP_DAP4, - TEGRA_PINGROUP_DDC, - TEGRA_PINGROUP_DTA, - TEGRA_PINGROUP_DTB, - TEGRA_PINGROUP_DTC, - TEGRA_PINGROUP_DTD, - TEGRA_PINGROUP_DTE, - TEGRA_PINGROUP_DTF, - TEGRA_PINGROUP_GMA, - TEGRA_PINGROUP_GMB, - TEGRA_PINGROUP_GMC, - TEGRA_PINGROUP_GMD, - TEGRA_PINGROUP_GME, - TEGRA_PINGROUP_GPU, - TEGRA_PINGROUP_GPU7, - TEGRA_PINGROUP_GPV, - TEGRA_PINGROUP_HDINT, - TEGRA_PINGROUP_I2CP, - TEGRA_PINGROUP_IRRX, - TEGRA_PINGROUP_IRTX, - TEGRA_PINGROUP_KBCA, - TEGRA_PINGROUP_KBCB, - TEGRA_PINGROUP_KBCC, - TEGRA_PINGROUP_KBCD, - TEGRA_PINGROUP_KBCE, - TEGRA_PINGROUP_KBCF, - TEGRA_PINGROUP_LCSN, - TEGRA_PINGROUP_LD0, - TEGRA_PINGROUP_LD1, - TEGRA_PINGROUP_LD10, - TEGRA_PINGROUP_LD11, - TEGRA_PINGROUP_LD12, - TEGRA_PINGROUP_LD13, - TEGRA_PINGROUP_LD14, - TEGRA_PINGROUP_LD15, - TEGRA_PINGROUP_LD16, - TEGRA_PINGROUP_LD17, - TEGRA_PINGROUP_LD2, - TEGRA_PINGROUP_LD3, - TEGRA_PINGROUP_LD4, - TEGRA_PINGROUP_LD5, - TEGRA_PINGROUP_LD6, - TEGRA_PINGROUP_LD7, - TEGRA_PINGROUP_LD8, - TEGRA_PINGROUP_LD9, - TEGRA_PINGROUP_LDC, - TEGRA_PINGROUP_LDI, - TEGRA_PINGROUP_LHP0, - TEGRA_PINGROUP_LHP1, - TEGRA_PINGROUP_LHP2, - TEGRA_PINGROUP_LHS, - TEGRA_PINGROUP_LM0, - TEGRA_PINGROUP_LM1, - TEGRA_PINGROUP_LPP, - TEGRA_PINGROUP_LPW0, - TEGRA_PINGROUP_LPW1, - TEGRA_PINGROUP_LPW2, - TEGRA_PINGROUP_LSC0, - TEGRA_PINGROUP_LSC1, - TEGRA_PINGROUP_LSCK, - TEGRA_PINGROUP_LSDA, - TEGRA_PINGROUP_LSDI, - TEGRA_PINGROUP_LSPI, - TEGRA_PINGROUP_LVP0, - TEGRA_PINGROUP_LVP1, - TEGRA_PINGROUP_LVS, - TEGRA_PINGROUP_OWC, - TEGRA_PINGROUP_PMC, - TEGRA_PINGROUP_PTA, - TEGRA_PINGROUP_RM, - TEGRA_PINGROUP_SDB, - TEGRA_PINGROUP_SDC, - TEGRA_PINGROUP_SDD, - TEGRA_PINGROUP_SDIO1, - TEGRA_PINGROUP_SLXA, - TEGRA_PINGROUP_SLXC, - TEGRA_PINGROUP_SLXD, - TEGRA_PINGROUP_SLXK, - TEGRA_PINGROUP_SPDI, - TEGRA_PINGROUP_SPDO, - TEGRA_PINGROUP_SPIA, - TEGRA_PINGROUP_SPIB, - TEGRA_PINGROUP_SPIC, - TEGRA_PINGROUP_SPID, - TEGRA_PINGROUP_SPIE, - TEGRA_PINGROUP_SPIF, - TEGRA_PINGROUP_SPIG, - TEGRA_PINGROUP_SPIH, - TEGRA_PINGROUP_UAA, - TEGRA_PINGROUP_UAB, - TEGRA_PINGROUP_UAC, - TEGRA_PINGROUP_UAD, - TEGRA_PINGROUP_UCA, - TEGRA_PINGROUP_UCB, - TEGRA_PINGROUP_UDA, - /* these pin groups only have pullup and pull down control */ - TEGRA_PINGROUP_CK32, - TEGRA_PINGROUP_DDRC, - TEGRA_PINGROUP_PMCA, - TEGRA_PINGROUP_PMCB, - TEGRA_PINGROUP_PMCC, - TEGRA_PINGROUP_PMCD, - TEGRA_PINGROUP_PMCE, - TEGRA_PINGROUP_XM2C, - TEGRA_PINGROUP_XM2D, - TEGRA_MAX_PINGROUP, -}; +#if defined(CONFIG_ARCH_TEGRA_2x_SOC) +#include "pinmux-t2.h" +#else +#error "Undefined Tegra architecture" +#endif enum tegra_mux_func { TEGRA_MUX_RSVD = 0x8000, @@ -205,6 +90,7 @@ enum tegra_mux_func { TEGRA_MUX_VI, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_MUX_XIO, + TEGRA_MUX_SAFE, TEGRA_MAX_MUX, }; @@ -219,6 +105,18 @@ enum tegra_tristate { TEGRA_TRI_TRISTATE = 1, }; +enum tegra_vddio { + TEGRA_VDDIO_BB = 0, + TEGRA_VDDIO_LCD, + TEGRA_VDDIO_VI, + TEGRA_VDDIO_UART, + TEGRA_VDDIO_DDR, + TEGRA_VDDIO_NAND, + TEGRA_VDDIO_SYS, + TEGRA_VDDIO_AUDIO, + TEGRA_VDDIO_SD, +}; + struct tegra_pingroup_config { enum tegra_pingroup pingroup; enum tegra_mux_func func; @@ -270,38 +168,6 @@ enum tegra_pull_strength { TEGRA_MAX_PULL, }; -enum tegra_drive_pingroup { - TEGRA_DRIVE_PINGROUP_AO1 = 0, - TEGRA_DRIVE_PINGROUP_AO2, - TEGRA_DRIVE_PINGROUP_AT1, - TEGRA_DRIVE_PINGROUP_AT2, - TEGRA_DRIVE_PINGROUP_CDEV1, - TEGRA_DRIVE_PINGROUP_CDEV2, - TEGRA_DRIVE_PINGROUP_CSUS, - TEGRA_DRIVE_PINGROUP_DAP1, - TEGRA_DRIVE_PINGROUP_DAP2, - TEGRA_DRIVE_PINGROUP_DAP3, - TEGRA_DRIVE_PINGROUP_DAP4, - TEGRA_DRIVE_PINGROUP_DBG, - TEGRA_DRIVE_PINGROUP_LCD1, - TEGRA_DRIVE_PINGROUP_LCD2, - TEGRA_DRIVE_PINGROUP_SDMMC2, - TEGRA_DRIVE_PINGROUP_SDMMC3, - TEGRA_DRIVE_PINGROUP_SPI, - TEGRA_DRIVE_PINGROUP_UAA, - TEGRA_DRIVE_PINGROUP_UAB, - TEGRA_DRIVE_PINGROUP_UART2, - TEGRA_DRIVE_PINGROUP_UART3, - TEGRA_DRIVE_PINGROUP_VI1, - TEGRA_DRIVE_PINGROUP_VI2, - TEGRA_DRIVE_PINGROUP_XM2A, - TEGRA_DRIVE_PINGROUP_XM2C, - TEGRA_DRIVE_PINGROUP_XM2D, - TEGRA_DRIVE_PINGROUP_XM2CLK, - TEGRA_DRIVE_PINGROUP_MEMCOMP, - TEGRA_MAX_DRIVE_PINGROUP, -}; - enum tegra_drive { TEGRA_DRIVE_DIV_8 = 0, TEGRA_DRIVE_DIV_4, @@ -331,18 +197,44 @@ struct tegra_drive_pingroup_config { enum tegra_slew slew_falling; }; -int tegra_pinmux_set_func(enum tegra_pingroup pg, enum tegra_mux_func func); -int tegra_pinmux_set_tristate(enum tegra_pingroup pg, enum tegra_tristate tristate); -int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg, enum tegra_pullupdown pupd); +struct tegra_drive_pingroup_desc { + const char *name; + s16 reg; +}; + +struct tegra_pingroup_desc { + const char *name; + int funcs[4]; + int func_safe; + int vddio; + s16 tri_reg; /* offset into the TRISTATE_REG_* register bank */ + s16 mux_reg; /* offset into the PIN_MUX_CTL_* register bank */ + s16 pupd_reg; /* offset into the PULL_UPDOWN_REG_* register bank */ + s8 tri_bit; /* offset into the TRISTATE_REG_* register bit */ + s8 mux_bit; /* offset into the PIN_MUX_CTL_* register bit */ + s8 pupd_bit; /* offset into the PULL_UPDOWN_REG_* register bit */ +}; + +extern const struct tegra_pingroup_desc tegra_soc_pingroups[]; +extern const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[]; -void tegra_pinmux_config_pingroup(enum tegra_pingroup pingroup, - enum tegra_mux_func func, enum tegra_pullupdown pupd, +int tegra_pinmux_set_tristate(enum tegra_pingroup pg, enum tegra_tristate tristate); +int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg, + enum tegra_pullupdown pupd); -void tegra_pinmux_config_table(struct tegra_pingroup_config *config, int len); +void tegra_pinmux_config_table(const struct tegra_pingroup_config *config, + int len); void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config, int len); - +void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config, + int len); +void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config, + int len); +void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config, + int len, enum tegra_tristate tristate); +void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config, + int len, enum tegra_pullupdown pupd); #endif diff --git a/arch/arm/mach-tegra/io.c b/arch/arm/mach-tegra/io.c index 9fe2c5c683d4..31848a9592f8 100644 --- a/arch/arm/mach-tegra/io.c +++ b/arch/arm/mach-tegra/io.c @@ -49,6 +49,12 @@ static struct map_desc tegra_io_desc[] __initdata = { .length = IO_CPU_SIZE, .type = MT_DEVICE, }, + { + .virtual = IO_IRAM_VIRT, + .pfn = __phys_to_pfn(IO_IRAM_PHYS), + .length = IO_IRAM_SIZE, + .type = MT_DEVICE, + }, }; void __init tegra_map_common_io(void) diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c index 1fdbe708d43d..50a8dfb9a0cf 100644 --- a/arch/arm/mach-tegra/irq.c +++ b/arch/arm/mach-tegra/irq.c @@ -4,6 +4,8 @@ * Author: * Colin Cross <ccross@google.com> * + * Copyright (C) 2010, NVIDIA Corporation + * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. @@ -27,8 +29,143 @@ #include "board.h" +#define INT_SYS_NR (INT_GPIO_BASE - INT_PRI_BASE) +#define INT_SYS_SZ (INT_SEC_BASE - INT_PRI_BASE) +#define PPI_NR ((INT_SYS_NR+INT_SYS_SZ-1)/INT_SYS_SZ) + +#define APBDMA_IRQ_STA_CPU 0x14 +#define APBDMA_IRQ_MASK_SET 0x20 +#define APBDMA_IRQ_MASK_CLR 0x24 + +#define ICTLR_CPU_IER 0x20 +#define ICTLR_CPU_IER_SET 0x24 +#define ICTLR_CPU_IER_CLR 0x28 +#define ICTLR_CPU_IEP_CLASS 0x2c +#define ICTLR_COP_IER 0x30 +#define ICTLR_COP_IER_SET 0x34 +#define ICTLR_COP_IER_CLR 0x38 +#define ICTLR_COP_IEP_CLASS 0x3c + +static void (*gic_mask_irq)(unsigned int irq); +static void (*gic_unmask_irq)(unsigned int irq); + +#define irq_to_ictlr(irq) (((irq)-32) >> 5) +static void __iomem *tegra_ictlr_base = IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE); +#define ictlr_to_virt(ictlr) (tegra_ictlr_base + (ictlr)*0x100) + +static void tegra_mask(unsigned int irq) +{ + void __iomem *addr = ictlr_to_virt(irq_to_ictlr(irq)); + gic_mask_irq(irq); + writel(1<<(irq&31), addr+ICTLR_CPU_IER_CLR); +} + +static void tegra_unmask(unsigned int irq) +{ + void __iomem *addr = ictlr_to_virt(irq_to_ictlr(irq)); + gic_unmask_irq(irq); + writel(1<<(irq&31), addr+ICTLR_CPU_IER_SET); +} + +#ifdef CONFIG_PM + +static int tegra_set_wake(unsigned int irq, unsigned int on) +{ + return 0; +} +#endif + +static struct irq_chip tegra_irq = { + .name = "PPI", + .mask = tegra_mask, + .unmask = tegra_unmask, +#ifdef CONFIG_PM + .set_wake = tegra_set_wake, +#endif +}; + void __init tegra_init_irq(void) { + struct irq_chip *gic; + unsigned int i; + + for (i = 0; i < PPI_NR; i++) { + writel(~0, ictlr_to_virt(i) + ICTLR_CPU_IER_CLR); + writel(0, ictlr_to_virt(i) + ICTLR_CPU_IEP_CLASS); + } + gic_dist_init(0, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE), 29); gic_cpu_init(0, IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); + + gic = get_irq_chip(29); + gic_unmask_irq = gic->unmask; + gic_mask_irq = gic->mask; + tegra_irq.ack = gic->ack; +#ifdef CONFIG_SMP + tegra_irq.set_affinity = gic->set_affinity; +#endif + + for (i = INT_PRI_BASE; i < INT_GPIO_BASE; i++) { + set_irq_chip(i, &tegra_irq); + set_irq_handler(i, handle_level_irq); + set_irq_flags(i, IRQF_VALID); + } +} + +#ifdef CONFIG_PM +static u32 cop_ier[PPI_NR]; +static u32 cpu_ier[PPI_NR]; +static u32 cpu_iep[PPI_NR]; + +void tegra_irq_suspend(void) +{ + unsigned long flags; + int i; + + for (i = INT_PRI_BASE; i < INT_GPIO_BASE; i++) { + struct irq_desc *desc = irq_to_desc(i); + if (!desc) + continue; + if (desc->status & IRQ_WAKEUP) { + pr_debug("irq %d is wakeup\n", i); + continue; + } + disable_irq(i); + } + + local_irq_save(flags); + for (i = 0; i < PPI_NR; i++) { + void __iomem *ictlr = ictlr_to_virt(i); + cpu_ier[i] = readl(ictlr + ICTLR_CPU_IER); + cpu_iep[i] = readl(ictlr + ICTLR_CPU_IEP_CLASS); + cop_ier[i] = readl(ictlr + ICTLR_COP_IER); + writel(~0, ictlr + ICTLR_COP_IER_CLR); + } + local_irq_restore(flags); +} + +void tegra_irq_resume(void) +{ + unsigned long flags; + int i; + + local_irq_save(flags); + for (i = 0; i < PPI_NR; i++) { + void __iomem *ictlr = ictlr_to_virt(i); + writel(cpu_iep[i], ictlr + ICTLR_CPU_IEP_CLASS); + writel(~0ul, ictlr + ICTLR_CPU_IER_CLR); + writel(cpu_ier[i], ictlr + ICTLR_CPU_IER_SET); + writel(0, ictlr + ICTLR_COP_IEP_CLASS); + writel(~0ul, ictlr + ICTLR_COP_IER_CLR); + writel(cop_ier[i], ictlr + ICTLR_COP_IER_SET); + } + local_irq_restore(flags); + + for (i = INT_PRI_BASE; i < INT_GPIO_BASE; i++) { + struct irq_desc *desc = irq_to_desc(i); + if (!desc || (desc->status & IRQ_WAKEUP)) + continue; + enable_irq(i); + } } +#endif diff --git a/arch/arm/mach-tegra/legacy_irq.c b/arch/arm/mach-tegra/legacy_irq.c new file mode 100644 index 000000000000..7cc8601c19ff --- /dev/null +++ b/arch/arm/mach-tegra/legacy_irq.c @@ -0,0 +1,114 @@ +/* + * arch/arm/mach-tegra/legacy_irq.c + * + * Copyright (C) 2010 Google, Inc. + * Author: Colin Cross <ccross@android.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/io.h> +#include <linux/kernel.h> +#include <mach/iomap.h> +#include <mach/legacy_irq.h> + +#define ICTLR_CPU_IER 0x20 +#define ICTLR_CPU_IER_SET 0x24 +#define ICTLR_CPU_IER_CLR 0x28 +#define ICTLR_CPU_IEP_CLASS 0x2C +#define ICTLR_CPU_IEP_VFIQ 0x08 +#define ICTLR_CPU_IEP_FIR 0x14 +#define ICTLR_CPU_IEP_FIR_SET 0x18 +#define ICTLR_CPU_IEP_FIR_CLR 0x1c + +static void __iomem *ictlr_reg_base[] = { + IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE), + IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE), + IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE), + IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE), +}; + +/* When going into deep sleep, the CPU is powered down, taking the GIC with it + In order to wake, the wake interrupts need to be enabled in the legacy + interrupt controller. */ +void tegra_legacy_unmask_irq(unsigned int irq) +{ + void __iomem *base; + pr_debug("%s: %d\n", __func__, irq); + + irq -= 32; + base = ictlr_reg_base[irq>>5]; + writel(1 << (irq & 31), base + ICTLR_CPU_IER_SET); +} + +void tegra_legacy_mask_irq(unsigned int irq) +{ + void __iomem *base; + pr_debug("%s: %d\n", __func__, irq); + + irq -= 32; + base = ictlr_reg_base[irq>>5]; + writel(1 << (irq & 31), base + ICTLR_CPU_IER_CLR); +} + +void tegra_legacy_force_irq_set(unsigned int irq) +{ + void __iomem *base; + pr_debug("%s: %d\n", __func__, irq); + + irq -= 32; + base = ictlr_reg_base[irq>>5]; + writel(1 << (irq & 31), base + ICTLR_CPU_IEP_FIR_SET); +} + +void tegra_legacy_force_irq_clr(unsigned int irq) +{ + void __iomem *base; + pr_debug("%s: %d\n", __func__, irq); + + irq -= 32; + base = ictlr_reg_base[irq>>5]; + writel(1 << (irq & 31), base + ICTLR_CPU_IEP_FIR_CLR); +} + +int tegra_legacy_force_irq_status(unsigned int irq) +{ + void __iomem *base; + pr_debug("%s: %d\n", __func__, irq); + + irq -= 32; + base = ictlr_reg_base[irq>>5]; + return !!(readl(base + ICTLR_CPU_IEP_FIR) & (1 << (irq & 31))); +} + +void tegra_legacy_select_fiq(unsigned int irq, bool fiq) +{ + void __iomem *base; + pr_debug("%s: %d\n", __func__, irq); + + irq -= 32; + base = ictlr_reg_base[irq>>5]; + writel(fiq << (irq & 31), base + ICTLR_CPU_IEP_CLASS); +} + +unsigned long tegra_legacy_vfiq(int nr) +{ + void __iomem *base; + base = ictlr_reg_base[nr]; + return readl(base + ICTLR_CPU_IEP_VFIQ); +} + +unsigned long tegra_legacy_class(int nr) +{ + void __iomem *base; + base = ictlr_reg_base[nr]; + return readl(base + ICTLR_CPU_IEP_CLASS); +} diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c new file mode 100644 index 000000000000..53f5fa37014a --- /dev/null +++ b/arch/arm/mach-tegra/pcie.c @@ -0,0 +1,915 @@ +/* + * arch/arm/mach-tegra/pci.c + * + * PCIe host controller driver for TEGRA(2) SOCs + * + * Copyright (c) 2010, CompuLab, Ltd. + * Author: Mike Rapoport <mike@compulab.co.il> + * + * Based on NVIDIA PCIe driver + * Copyright (c) 2008-2009, NVIDIA Corporation. + * + * Bits taken from arch/arm/mach-dove/pcie.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#include <linux/kernel.h> +#include <linux/pci.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/clk.h> +#include <linux/delay.h> + +#include <asm/sizes.h> +#include <asm/mach/pci.h> + +#include <mach/pinmux.h> +#include <mach/iomap.h> +#include <mach/clk.h> + +/* register definitions */ +#define AFI_OFFSET 0x3800 +#define PADS_OFFSET 0x3000 +#define RP0_OFFSET 0x0000 +#define RP1_OFFSET 0x1000 + +#define AFI_AXI_BAR0_SZ 0x00 +#define AFI_AXI_BAR1_SZ 0x04 +#define AFI_AXI_BAR2_SZ 0x08 +#define AFI_AXI_BAR3_SZ 0x0c +#define AFI_AXI_BAR4_SZ 0x10 +#define AFI_AXI_BAR5_SZ 0x14 + +#define AFI_AXI_BAR0_START 0x18 +#define AFI_AXI_BAR1_START 0x1c +#define AFI_AXI_BAR2_START 0x20 +#define AFI_AXI_BAR3_START 0x24 +#define AFI_AXI_BAR4_START 0x28 +#define AFI_AXI_BAR5_START 0x2c + +#define AFI_FPCI_BAR0 0x30 +#define AFI_FPCI_BAR1 0x34 +#define AFI_FPCI_BAR2 0x38 +#define AFI_FPCI_BAR3 0x3c +#define AFI_FPCI_BAR4 0x40 +#define AFI_FPCI_BAR5 0x44 + +#define AFI_CACHE_BAR0_SZ 0x48 +#define AFI_CACHE_BAR0_ST 0x4c +#define AFI_CACHE_BAR1_SZ 0x50 +#define AFI_CACHE_BAR1_ST 0x54 + +#define AFI_MSI_BAR_SZ 0x60 +#define AFI_MSI_FPCI_BAR_ST 0x64 +#define AFI_MSI_AXI_BAR_ST 0x68 + +#define AFI_CONFIGURATION 0xac +#define AFI_CONFIGURATION_EN_FPCI (1 << 0) + +#define AFI_FPCI_ERROR_MASKS 0xb0 + +#define AFI_INTR_MASK 0xb4 +#define AFI_INTR_MASK_INT_MASK (1 << 0) +#define AFI_INTR_MASK_MSI_MASK (1 << 8) + +#define AFI_INTR_CODE 0xb8 +#define AFI_INTR_CODE_MASK 0xf +#define AFI_INTR_MASTER_ABORT 4 +#define AFI_INTR_LEGACY 6 + +#define AFI_INTR_SIGNATURE 0xbc +#define AFI_SM_INTR_ENABLE 0xc4 + +#define AFI_AFI_INTR_ENABLE 0xc8 +#define AFI_INTR_EN_INI_SLVERR (1 << 0) +#define AFI_INTR_EN_INI_DECERR (1 << 1) +#define AFI_INTR_EN_TGT_SLVERR (1 << 2) +#define AFI_INTR_EN_TGT_DECERR (1 << 3) +#define AFI_INTR_EN_TGT_WRERR (1 << 4) +#define AFI_INTR_EN_DFPCI_DECERR (1 << 5) +#define AFI_INTR_EN_AXI_DECERR (1 << 6) +#define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7) + +#define AFI_PCIE_CONFIG 0x0f8 +#define AFI_PCIE_CONFIG_PCIEC0_DISABLE_DEVICE (1 << 1) +#define AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE (1 << 2) +#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20) +#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20) +#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20) + +#define AFI_FUSE 0x104 +#define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2) + +#define AFI_PEX0_CTRL 0x110 +#define AFI_PEX1_CTRL 0x118 +#define AFI_PEX_CTRL_RST (1 << 0) +#define AFI_PEX_CTRL_REFCLK_EN (1 << 3) + +#define RP_VEND_XP 0x00000F00 +#define RP_VEND_XP_DL_UP (1 << 30) + +#define RP_LINK_CONTROL_STATUS 0x00000090 +#define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000 + +#define PADS_CTL_SEL 0x0000009C + +#define PADS_CTL 0x000000A0 +#define PADS_CTL_IDDQ_1L (1 << 0) +#define PADS_CTL_TX_DATA_EN_1L (1 << 6) +#define PADS_CTL_RX_DATA_EN_1L (1 << 10) + +#define PADS_PLL_CTL 0x000000B8 +#define PADS_PLL_CTL_RST_B4SM (1 << 1) +#define PADS_PLL_CTL_LOCKDET (1 << 8) +#define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16) +#define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0 << 16) +#define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (1 << 16) +#define PADS_PLL_CTL_REFCLK_EXTERNAL (2 << 16) +#define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20) +#define PADS_PLL_CTL_TXCLKREF_DIV10 (0 << 20) +#define PADS_PLL_CTL_TXCLKREF_DIV5 (1 << 20) + +/* PMC access is required for PCIE xclk (un)clamping */ +#define PMC_SCRATCH42 0x144 +#define PMC_SCRATCH42_PCX_CLAMP (1 << 0) + +static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE); + +#define pmc_writel(value, reg) \ + __raw_writel(value, (u32)reg_pmc_base + (reg)) +#define pmc_readl(reg) \ + __raw_readl((u32)reg_pmc_base + (reg)) + +/* + * Tegra2 defines 1GB in the AXI address map for PCIe. + * + * That address space is split into different regions, with sizes and + * offsets as follows: + * + * 0x80000000 - 0x80003fff - PCI controller registers + * 0x80004000 - 0x80103fff - PCI configuration space + * 0x80104000 - 0x80203fff - PCI extended configuration space + * 0x80203fff - 0x803fffff - unused + * 0x80400000 - 0x8040ffff - downstream IO + * 0x80410000 - 0x8fffffff - unused + * 0x90000000 - 0x9fffffff - non-prefetchable memory + * 0xa0000000 - 0xbfffffff - prefetchable memory + */ +#define TEGRA_PCIE_BASE 0x80000000 + +#define PCIE_REGS_SZ SZ_16K +#define PCIE_CFG_OFF PCIE_REGS_SZ +#define PCIE_CFG_SZ SZ_1M +#define PCIE_EXT_CFG_OFF (PCIE_CFG_SZ + PCIE_CFG_OFF) +#define PCIE_EXT_CFG_SZ SZ_1M +#define PCIE_IOMAP_SZ (PCIE_REGS_SZ + PCIE_CFG_SZ + PCIE_EXT_CFG_SZ) + +#define MMIO_BASE (TEGRA_PCIE_BASE + SZ_4M) +#define MMIO_SIZE SZ_64K +#define MEM_BASE_0 (TEGRA_PCIE_BASE + SZ_256M) +#define MEM_SIZE_0 SZ_128M +#define MEM_BASE_1 (MEM_BASE_0 + MEM_SIZE_0) +#define MEM_SIZE_1 SZ_128M +#define PREFETCH_MEM_BASE_0 (MEM_BASE_1 + MEM_SIZE_1) +#define PREFETCH_MEM_SIZE_0 SZ_128M +#define PREFETCH_MEM_BASE_1 (PREFETCH_MEM_BASE_0 + PREFETCH_MEM_SIZE_0) +#define PREFETCH_MEM_SIZE_1 SZ_128M + +#define PCIE_CONF_BUS(b) ((b) << 16) +#define PCIE_CONF_DEV(d) ((d) << 11) +#define PCIE_CONF_FUNC(f) ((f) << 8) +#define PCIE_CONF_REG(r) \ + (((r) & ~0x3) | (((r) < 256) ? PCIE_CFG_OFF : PCIE_EXT_CFG_OFF)) + +struct tegra_pcie_port { + int index; + u8 root_bus_nr; + void __iomem *base; + + bool link_up; + + char io_space_name[16]; + char mem_space_name[16]; + char prefetch_space_name[20]; + struct resource res[3]; +}; + +struct tegra_pcie_info { + struct tegra_pcie_port port[2]; + int num_ports; + + void __iomem *regs; + struct resource res_mmio; + + struct clk *pex_clk; + struct clk *afi_clk; + struct clk *pcie_xclk; + struct clk *pll_e; +}; + +static struct tegra_pcie_info tegra_pcie = { + .res_mmio = { + .name = "PCI IO", + .start = MMIO_BASE, + .end = MMIO_BASE + MMIO_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +void __iomem *tegra_pcie_io_base; +EXPORT_SYMBOL(tegra_pcie_io_base); + +static inline void afi_writel(u32 value, unsigned long offset) +{ + writel(value, offset + AFI_OFFSET + tegra_pcie.regs); +} + +static inline u32 afi_readl(unsigned long offset) +{ + return readl(offset + AFI_OFFSET + tegra_pcie.regs); +} + +static inline void pads_writel(u32 value, unsigned long offset) +{ + writel(value, offset + PADS_OFFSET + tegra_pcie.regs); +} + +static inline u32 pads_readl(unsigned long offset) +{ + return readl(offset + PADS_OFFSET + tegra_pcie.regs); +} + +static struct tegra_pcie_port *bus_to_port(int bus) +{ + int i; + + for (i = tegra_pcie.num_ports - 1; i >= 0; i--) { + int rbus = tegra_pcie.port[i].root_bus_nr; + if (rbus != -1 && rbus == bus) + break; + } + + return i >= 0 ? tegra_pcie.port + i : NULL; +} + +static int tegra_pcie_read_conf(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) +{ + struct tegra_pcie_port *pp = bus_to_port(bus->number); + void __iomem *addr; + + if (pp) { + if (devfn != 0) { + *val = 0xffffffff; + return PCIBIOS_DEVICE_NOT_FOUND; + } + + addr = pp->base + (where & ~0x3); + } else { + addr = tegra_pcie.regs + (PCIE_CONF_BUS(bus->number) + + PCIE_CONF_DEV(PCI_SLOT(devfn)) + + PCIE_CONF_FUNC(PCI_FUNC(devfn)) + + PCIE_CONF_REG(where)); + } + + *val = readl(addr); + + if (size == 1) + *val = (*val >> (8 * (where & 3))) & 0xff; + else if (size == 2) + *val = (*val >> (8 * (where & 3))) & 0xffff; + + return PCIBIOS_SUCCESSFUL; +} + +static int tegra_pcie_write_conf(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + struct tegra_pcie_port *pp = bus_to_port(bus->number); + void __iomem *addr; + + u32 mask; + u32 tmp; + + if (pp) { + if (devfn != 0) + return PCIBIOS_DEVICE_NOT_FOUND; + + addr = pp->base + (where & ~0x3); + } else { + addr = tegra_pcie.regs + (PCIE_CONF_BUS(bus->number) + + PCIE_CONF_DEV(PCI_SLOT(devfn)) + + PCIE_CONF_FUNC(PCI_FUNC(devfn)) + + PCIE_CONF_REG(where)); + } + + if (size == 4) { + writel(val, addr); + return PCIBIOS_SUCCESSFUL; + } + + if (size == 2) + mask = ~(0xffff << ((where & 0x3) * 8)); + else if (size == 1) + mask = ~(0xff << ((where & 0x3) * 8)); + else + return PCIBIOS_BAD_REGISTER_NUMBER; + + tmp = readl(addr) & mask; + tmp |= val << ((where & 0x3) * 8); + writel(tmp, addr); + + return PCIBIOS_SUCCESSFUL; +} + +static struct pci_ops tegra_pcie_ops = { + .read = tegra_pcie_read_conf, + .write = tegra_pcie_write_conf, +}; + +static void __devinit tegra_pcie_fixup_bridge(struct pci_dev *dev) +{ + u16 reg; + + if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE) { + pci_read_config_word(dev, PCI_COMMAND, ®); + reg |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER | PCI_COMMAND_SERR); + pci_write_config_word(dev, PCI_COMMAND, reg); + } +} +DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_fixup_bridge); + +/* Tegra PCIE root complex wrongly reports device class */ +static void __devinit tegra_pcie_fixup_class(struct pci_dev *dev) +{ + dev->class = PCI_CLASS_BRIDGE_PCI << 8; +} +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, tegra_pcie_fixup_class); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class); + +/* Tegra PCIE requires relaxed ordering */ +static void __devinit tegra_pcie_relax_enable(struct pci_dev *dev) +{ + u16 val16; + int pos = pci_find_capability(dev, PCI_CAP_ID_EXP); + + if (pos <= 0) { + dev_err(&dev->dev, "skipping relaxed ordering fixup\n"); + return; + } + + pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &val16); + val16 |= PCI_EXP_DEVCTL_RELAX_EN; + pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, val16); +} +DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable); + +static int tegra_pcie_setup(int nr, struct pci_sys_data *sys) +{ + struct tegra_pcie_port *pp; + + if (nr >= tegra_pcie.num_ports) + return 0; + + pp = tegra_pcie.port + nr; + pp->root_bus_nr = sys->busnr; + + /* + * IORESOURCE_IO + */ + snprintf(pp->io_space_name, sizeof(pp->io_space_name), + "PCIe %d I/O", pp->index); + pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0; + pp->res[0].name = pp->io_space_name; + if (pp->index == 0) { + pp->res[0].start = PCIBIOS_MIN_IO; + pp->res[0].end = pp->res[0].start + SZ_32K - 1; + } else { + pp->res[0].start = PCIBIOS_MIN_IO + SZ_32K; + pp->res[0].end = IO_SPACE_LIMIT; + } + pp->res[0].flags = IORESOURCE_IO; + if (request_resource(&ioport_resource, &pp->res[0])) + panic("Request PCIe IO resource failed\n"); + sys->resource[0] = &pp->res[0]; + + /* + * IORESOURCE_MEM + */ + snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), + "PCIe %d MEM", pp->index); + pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0; + pp->res[1].name = pp->mem_space_name; + if (pp->index == 0) { + pp->res[1].start = MEM_BASE_0; + pp->res[1].end = pp->res[1].start + MEM_SIZE_0 - 1; + } else { + pp->res[1].start = MEM_BASE_1; + pp->res[1].end = pp->res[1].start + MEM_SIZE_1 - 1; + } + pp->res[1].flags = IORESOURCE_MEM; + if (request_resource(&iomem_resource, &pp->res[1])) + panic("Request PCIe Memory resource failed\n"); + sys->resource[1] = &pp->res[1]; + + /* + * IORESOURCE_MEM | IORESOURCE_PREFETCH + */ + snprintf(pp->prefetch_space_name, sizeof(pp->prefetch_space_name), + "PCIe %d PREFETCH MEM", pp->index); + pp->prefetch_space_name[sizeof(pp->prefetch_space_name) - 1] = 0; + pp->res[2].name = pp->prefetch_space_name; + if (pp->index == 0) { + pp->res[2].start = PREFETCH_MEM_BASE_0; + pp->res[2].end = pp->res[2].start + PREFETCH_MEM_SIZE_0 - 1; + } else { + pp->res[2].start = PREFETCH_MEM_BASE_1; + pp->res[2].end = pp->res[2].start + PREFETCH_MEM_SIZE_1 - 1; + } + pp->res[2].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; + if (request_resource(&iomem_resource, &pp->res[2])) + panic("Request PCIe Prefetch Memory resource failed\n"); + sys->resource[2] = &pp->res[2]; + + return 1; +} + +static int tegra_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + return INT_PCIE_INTR; +} + +static struct pci_bus __init *tegra_pcie_scan_bus(int nr, + struct pci_sys_data *sys) +{ + struct tegra_pcie_port *pp; + + if (nr >= tegra_pcie.num_ports) + return 0; + + pp = tegra_pcie.port + nr; + pp->root_bus_nr = sys->busnr; + + return pci_scan_bus(sys->busnr, &tegra_pcie_ops, sys); +} + +static struct hw_pci tegra_pcie_hw __initdata = { + .nr_controllers = 2, + .setup = tegra_pcie_setup, + .scan = tegra_pcie_scan_bus, + .swizzle = pci_std_swizzle, + .map_irq = tegra_pcie_map_irq, +}; + + +static irqreturn_t tegra_pcie_isr(int irq, void *arg) +{ + const char *err_msg[] = { + "Unknown", + "AXI slave error", + "AXI decode error", + "Target abort", + "Master abort", + "Invalid write", + "Response decoding error", + "AXI response decoding error", + "Transcation timeout", + }; + + u32 code, signature; + + code = afi_readl(AFI_INTR_CODE) & AFI_INTR_CODE_MASK; + signature = afi_readl(AFI_INTR_SIGNATURE); + afi_writel(0, AFI_INTR_CODE); + + if (code == AFI_INTR_LEGACY) + return IRQ_NONE; + + if (code >= ARRAY_SIZE(err_msg)) + code = 0; + + /* + * do not pollute kernel log with master abort reports since they + * happen a lot during enumeration + */ + if (code == AFI_INTR_MASTER_ABORT) + pr_debug("PCIE: %s, signature: %08x\n", err_msg[code], signature); + else + pr_err("PCIE: %s, signature: %08x\n", err_msg[code], signature); + + return IRQ_HANDLED; +} + +static void tegra_pcie_setup_translations(void) +{ + u32 fpci_bar; + u32 size; + u32 axi_address; + + /* Bar 0: config Bar */ + fpci_bar = ((u32)0xfdff << 16); + size = PCIE_CFG_SZ; + axi_address = TEGRA_PCIE_BASE + PCIE_CFG_OFF; + afi_writel(axi_address, AFI_AXI_BAR0_START); + afi_writel(size >> 12, AFI_AXI_BAR0_SZ); + afi_writel(fpci_bar, AFI_FPCI_BAR0); + + /* Bar 1: extended config Bar */ + fpci_bar = ((u32)0xfe1 << 20); + size = PCIE_EXT_CFG_SZ; + axi_address = TEGRA_PCIE_BASE + PCIE_EXT_CFG_OFF; + afi_writel(axi_address, AFI_AXI_BAR1_START); + afi_writel(size >> 12, AFI_AXI_BAR1_SZ); + afi_writel(fpci_bar, AFI_FPCI_BAR1); + + /* Bar 2: downstream IO bar */ + fpci_bar = ((__u32)0xfdfc << 16); + size = MMIO_SIZE; + axi_address = MMIO_BASE; + afi_writel(axi_address, AFI_AXI_BAR2_START); + afi_writel(size >> 12, AFI_AXI_BAR2_SZ); + afi_writel(fpci_bar, AFI_FPCI_BAR2); + + /* Bar 3: prefetchable memory BAR */ + fpci_bar = (((PREFETCH_MEM_BASE_0 >> 12) & 0x0fffffff) << 4) | 0x1; + size = PREFETCH_MEM_SIZE_0 + PREFETCH_MEM_SIZE_1; + axi_address = PREFETCH_MEM_BASE_0; + afi_writel(axi_address, AFI_AXI_BAR3_START); + afi_writel(size >> 12, AFI_AXI_BAR3_SZ); + afi_writel(fpci_bar, AFI_FPCI_BAR3); + + /* Bar 4: non prefetchable memory BAR */ + fpci_bar = (((MEM_BASE_0 >> 12) & 0x0FFFFFFF) << 4) | 0x1; + size = MEM_SIZE_0 + MEM_SIZE_1; + axi_address = MEM_BASE_0; + afi_writel(axi_address, AFI_AXI_BAR4_START); + afi_writel(size >> 12, AFI_AXI_BAR4_SZ); + afi_writel(fpci_bar, AFI_FPCI_BAR4); + + /* Bar 5: NULL out the remaining BAR as it is not used */ + fpci_bar = 0; + size = 0; + axi_address = 0; + afi_writel(axi_address, AFI_AXI_BAR5_START); + afi_writel(size >> 12, AFI_AXI_BAR5_SZ); + afi_writel(fpci_bar, AFI_FPCI_BAR5); + + /* map all upstream transactions as uncached */ + afi_writel(PHYS_OFFSET, AFI_CACHE_BAR0_ST); + afi_writel(0, AFI_CACHE_BAR0_SZ); + afi_writel(0, AFI_CACHE_BAR1_ST); + afi_writel(0, AFI_CACHE_BAR1_SZ); + + /* No MSI */ + afi_writel(0, AFI_MSI_FPCI_BAR_ST); + afi_writel(0, AFI_MSI_BAR_SZ); + afi_writel(0, AFI_MSI_AXI_BAR_ST); + afi_writel(0, AFI_MSI_BAR_SZ); +} + +static void tegra_pcie_enable_controller(void) +{ + u32 val, reg; + int i; + + /* Enable slot clock and pulse the reset signals */ + for (i = 0, reg = AFI_PEX0_CTRL; i < 2; i++, reg += 0x8) { + val = afi_readl(reg) | AFI_PEX_CTRL_REFCLK_EN; + afi_writel(val, reg); + val &= ~AFI_PEX_CTRL_RST; + afi_writel(val, reg); + + val = afi_readl(reg) | AFI_PEX_CTRL_RST; + afi_writel(val, reg); + } + + /* Enable dual controller and both ports */ + val = afi_readl(AFI_PCIE_CONFIG); + val &= ~(AFI_PCIE_CONFIG_PCIEC0_DISABLE_DEVICE | + AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE | + AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK); + val |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL; + afi_writel(val, AFI_PCIE_CONFIG); + + val = afi_readl(AFI_FUSE) & ~AFI_FUSE_PCIE_T0_GEN2_DIS; + afi_writel(val, AFI_FUSE); + + /* Initialze internal PHY, enable up to 16 PCIE lanes */ + pads_writel(0x0, PADS_CTL_SEL); + + /* override IDDQ to 1 on all 4 lanes */ + val = pads_readl(PADS_CTL) | PADS_CTL_IDDQ_1L; + pads_writel(val, PADS_CTL); + + /* + * set up PHY PLL inputs select PLLE output as refclock, + * set TX ref sel to div10 (not div5) + */ + val = pads_readl(PADS_PLL_CTL); + val &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK); + val |= (PADS_PLL_CTL_REFCLK_INTERNAL_CML | PADS_PLL_CTL_TXCLKREF_DIV10); + pads_writel(val, PADS_PLL_CTL); + + /* take PLL out of reset */ + val = pads_readl(PADS_PLL_CTL) | PADS_PLL_CTL_RST_B4SM; + pads_writel(val, PADS_PLL_CTL); + + /* + * Hack, set the clock voltage to the DEFAULT provided by hw folks. + * This doesn't exist in the documentation + */ + pads_writel(0xfa5cfa5c, 0xc8); + + /* Wait for the PLL to lock */ + do { + val = pads_readl(PADS_PLL_CTL); + } while (!(val & PADS_PLL_CTL_LOCKDET)); + + /* turn off IDDQ override */ + val = pads_readl(PADS_CTL) & ~PADS_CTL_IDDQ_1L; + pads_writel(val, PADS_CTL); + + /* enable TX/RX data */ + val = pads_readl(PADS_CTL); + val |= (PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L); + pads_writel(val, PADS_CTL); + + /* Take the PCIe interface module out of reset */ + tegra_periph_reset_deassert(tegra_pcie.pcie_xclk); + + /* Finally enable PCIe */ + val = afi_readl(AFI_CONFIGURATION) | AFI_CONFIGURATION_EN_FPCI; + afi_writel(val, AFI_CONFIGURATION); + + val = (AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR | + AFI_INTR_EN_TGT_SLVERR | AFI_INTR_EN_TGT_DECERR | + AFI_INTR_EN_TGT_WRERR | AFI_INTR_EN_DFPCI_DECERR); + afi_writel(val, AFI_AFI_INTR_ENABLE); + afi_writel(0xffffffff, AFI_SM_INTR_ENABLE); + + /* FIXME: No MSI for now, only INT */ + afi_writel(AFI_INTR_MASK_INT_MASK, AFI_INTR_MASK); + + /* Disable all execptions */ + afi_writel(0, AFI_FPCI_ERROR_MASKS); + + return; +} + +static void tegra_pcie_xclk_clamp(bool clamp) +{ + u32 reg; + + reg = pmc_readl(PMC_SCRATCH42) & ~PMC_SCRATCH42_PCX_CLAMP; + + if (clamp) + reg |= PMC_SCRATCH42_PCX_CLAMP; + + pmc_writel(reg, PMC_SCRATCH42); +} + +static int tegra_pcie_power_on(void) +{ + tegra_pcie_xclk_clamp(true); + tegra_periph_reset_assert(tegra_pcie.pcie_xclk); + tegra_pcie_xclk_clamp(false); + + clk_enable(tegra_pcie.afi_clk); + clk_enable(tegra_pcie.pex_clk); + return clk_enable(tegra_pcie.pll_e); +} + +static void tegra_pcie_power_off(void) +{ + tegra_periph_reset_assert(tegra_pcie.pcie_xclk); + tegra_periph_reset_assert(tegra_pcie.afi_clk); + tegra_periph_reset_assert(tegra_pcie.pex_clk); + + tegra_pcie_xclk_clamp(true); +} + +static int tegra_pcie_clocks_get(void) +{ + int err; + + tegra_pcie.pex_clk = clk_get(NULL, "pex"); + if (IS_ERR(tegra_pcie.pex_clk)) + return PTR_ERR(tegra_pcie.pex_clk); + + tegra_pcie.afi_clk = clk_get(NULL, "afi"); + if (IS_ERR(tegra_pcie.afi_clk)) { + err = PTR_ERR(tegra_pcie.afi_clk); + goto err_afi_clk; + } + + tegra_pcie.pcie_xclk = clk_get(NULL, "pcie_xclk"); + if (IS_ERR(tegra_pcie.pcie_xclk)) { + err = PTR_ERR(tegra_pcie.pcie_xclk); + goto err_pcie_xclk; + } + + tegra_pcie.pll_e = clk_get_sys(NULL, "pll_e"); + if (IS_ERR(tegra_pcie.pll_e)) { + err = PTR_ERR(tegra_pcie.pll_e); + goto err_pll_e; + } + + return 0; + +err_pll_e: + clk_put(tegra_pcie.pcie_xclk); +err_pcie_xclk: + clk_put(tegra_pcie.afi_clk); +err_afi_clk: + clk_put(tegra_pcie.pex_clk); + + return err; +} + +static void tegra_pcie_clocks_put(void) +{ + clk_put(tegra_pcie.pll_e); + clk_put(tegra_pcie.pcie_xclk); + clk_put(tegra_pcie.afi_clk); + clk_put(tegra_pcie.pex_clk); +} + +static int __init tegra_pcie_get_resources(void) +{ + struct resource *res_mmio = &tegra_pcie.res_mmio; + int err; + + err = tegra_pcie_clocks_get(); + if (err) { + pr_err("PCIE: failed to get clocks: %d\n", err); + return err; + } + + err = tegra_pcie_power_on(); + if (err) { + pr_err("PCIE: failed to power up: %d\n", err); + goto err_pwr_on; + } + + tegra_pcie.regs = ioremap_nocache(TEGRA_PCIE_BASE, PCIE_IOMAP_SZ); + if (tegra_pcie.regs == NULL) { + pr_err("PCIE: Failed to map PCI/AFI registers\n"); + err = -ENOMEM; + goto err_map_reg; + } + + err = request_resource(&iomem_resource, res_mmio); + if (err) { + pr_err("PCIE: Failed to request resources: %d\n", err); + goto err_req_io; + } + + tegra_pcie_io_base = ioremap_nocache(res_mmio->start, + resource_size(res_mmio)); + if (tegra_pcie_io_base == NULL) { + pr_err("PCIE: Failed to map IO\n"); + err = -ENOMEM; + goto err_map_io; + } + + err = request_irq(INT_PCIE_INTR, tegra_pcie_isr, + IRQF_SHARED, "PCIE", &tegra_pcie); + if (err) { + pr_err("PCIE: Failed to register IRQ: %d\n", err); + goto err_irq; + } + set_irq_flags(INT_PCIE_INTR, IRQF_VALID); + + return 0; + +err_irq: + iounmap(tegra_pcie_io_base); +err_map_io: + release_resource(&tegra_pcie.res_mmio); +err_req_io: + iounmap(tegra_pcie.regs); +err_map_reg: + tegra_pcie_power_off(); +err_pwr_on: + tegra_pcie_clocks_put(); + + return err; +} + +/* + * FIXME: If there are no PCIe cards attached, then calling this function + * can result in the increase of the bootup time as there are big timeout + * loops. + */ +#define TEGRA_PCIE_LINKUP_TIMEOUT 200 /* up to 1.2 seconds */ +static bool tegra_pcie_check_link(struct tegra_pcie_port *pp, int idx, + u32 reset_reg) +{ + u32 reg; + int retries = 3; + int timeout; + + do { + timeout = TEGRA_PCIE_LINKUP_TIMEOUT; + while (timeout) { + reg = readl(pp->base + RP_VEND_XP); + + if (reg & RP_VEND_XP_DL_UP) + break; + + mdelay(1); + timeout--; + } + + if (!timeout) { + pr_err("PCIE: port %d: link down, retrying\n", idx); + goto retry; + } + + timeout = TEGRA_PCIE_LINKUP_TIMEOUT; + while (timeout) { + reg = readl(pp->base + RP_LINK_CONTROL_STATUS); + + if (reg & 0x20000000) + return true; + + mdelay(1); + timeout--; + } + +retry: + /* Pulse the PEX reset */ + reg = afi_readl(reset_reg) | AFI_PEX_CTRL_RST; + afi_writel(reg, reset_reg); + mdelay(1); + reg = afi_readl(reset_reg) & ~AFI_PEX_CTRL_RST; + afi_writel(reg, reset_reg); + + retries--; + } while (retries); + + return false; +} + +static void __init tegra_pcie_add_port(int index, u32 offset, u32 reset_reg) +{ + struct tegra_pcie_port *pp; + + pp = tegra_pcie.port + tegra_pcie.num_ports; + + pp->index = -1; + pp->base = tegra_pcie.regs + offset; + pp->link_up = tegra_pcie_check_link(pp, index, reset_reg); + + if (!pp->link_up) { + pp->base = NULL; + printk(KERN_INFO "PCIE: port %d: link down, ignoring\n", index); + return; + } + + tegra_pcie.num_ports++; + pp->index = index; + pp->root_bus_nr = -1; + memset(pp->res, 0, sizeof(pp->res)); +} + +int __init tegra_pcie_init(bool init_port0, bool init_port1) +{ + int err; + + if (!(init_port0 || init_port1)) + return -ENODEV; + + err = tegra_pcie_get_resources(); + if (err) + return err; + + tegra_pcie_enable_controller(); + + /* setup the AFI address translations */ + tegra_pcie_setup_translations(); + + if (init_port0) + tegra_pcie_add_port(0, RP0_OFFSET, AFI_PEX0_CTRL); + + if (init_port1) + tegra_pcie_add_port(1, RP1_OFFSET, AFI_PEX1_CTRL); + + pci_common_init(&tegra_pcie_hw); + + return 0; +} diff --git a/arch/arm/mach-tegra/pinmux-t2-tables.c b/arch/arm/mach-tegra/pinmux-t2-tables.c new file mode 100644 index 000000000000..a6ea34e782dc --- /dev/null +++ b/arch/arm/mach-tegra/pinmux-t2-tables.c @@ -0,0 +1,260 @@ +/* + * linux/arch/arm/mach-tegra/pinmux-t2-tables.c + * + * Common pinmux configurations for Tegra 2 SoCs + * + * Copyright (C) 2010 NVIDIA Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/spinlock.h> +#include <linux/io.h> +#include <linux/init.h> +#include <linux/string.h> + +#include <mach/iomap.h> +#include <mach/pinmux.h> + +#define DRIVE_PINGROUP(pg_name, r) \ + [TEGRA_DRIVE_PINGROUP_ ## pg_name] = { \ + .name = #pg_name, \ + .reg = r \ + } + +const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = { + DRIVE_PINGROUP(AO1, 0x868), + DRIVE_PINGROUP(AO2, 0x86c), + DRIVE_PINGROUP(AT1, 0x870), + DRIVE_PINGROUP(AT2, 0x874), + DRIVE_PINGROUP(CDEV1, 0x878), + DRIVE_PINGROUP(CDEV2, 0x87c), + DRIVE_PINGROUP(CSUS, 0x880), + DRIVE_PINGROUP(DAP1, 0x884), + DRIVE_PINGROUP(DAP2, 0x888), + DRIVE_PINGROUP(DAP3, 0x88c), + DRIVE_PINGROUP(DAP4, 0x890), + DRIVE_PINGROUP(DBG, 0x894), + DRIVE_PINGROUP(LCD1, 0x898), + DRIVE_PINGROUP(LCD2, 0x89c), + DRIVE_PINGROUP(SDMMC2, 0x8a0), + DRIVE_PINGROUP(SDMMC3, 0x8a4), + DRIVE_PINGROUP(SPI, 0x8a8), + DRIVE_PINGROUP(UAA, 0x8ac), + DRIVE_PINGROUP(UAB, 0x8b0), + DRIVE_PINGROUP(UART2, 0x8b4), + DRIVE_PINGROUP(UART3, 0x8b8), + DRIVE_PINGROUP(VI1, 0x8bc), + DRIVE_PINGROUP(VI2, 0x8c0), + DRIVE_PINGROUP(XM2A, 0x8c4), + DRIVE_PINGROUP(XM2C, 0x8c8), + DRIVE_PINGROUP(XM2D, 0x8cc), + DRIVE_PINGROUP(XM2CLK, 0x8d0), + DRIVE_PINGROUP(MEMCOMP, 0x8d4), +}; + +#define PINGROUP(pg_name, vdd, f0, f1, f2, f3, f_safe, \ + tri_r, tri_b, mux_r, mux_b, pupd_r, pupd_b) \ + [TEGRA_PINGROUP_ ## pg_name] = { \ + .name = #pg_name, \ + .vddio = TEGRA_VDDIO_ ## vdd, \ + .funcs = { \ + TEGRA_MUX_ ## f0, \ + TEGRA_MUX_ ## f1, \ + TEGRA_MUX_ ## f2, \ + TEGRA_MUX_ ## f3, \ + }, \ + .func_safe = TEGRA_MUX_ ## f_safe, \ + .tri_reg = tri_r, \ + .tri_bit = tri_b, \ + .mux_reg = mux_r, \ + .mux_bit = mux_b, \ + .pupd_reg = pupd_r, \ + .pupd_bit = pupd_b, \ + } + +const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = { + PINGROUP(ATA, NAND, IDE, NAND, GMI, RSVD, IDE, 0x14, 0, 0x80, 24, 0xA0, 0), + PINGROUP(ATB, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 1, 0x80, 16, 0xA0, 2), + PINGROUP(ATC, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 2, 0x80, 22, 0xA0, 4), + PINGROUP(ATD, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 3, 0x80, 20, 0xA0, 6), + PINGROUP(ATE, NAND, IDE, NAND, GMI, RSVD, IDE, 0x18, 25, 0x80, 12, 0xA0, 8), + PINGROUP(CDEV1, AUDIO, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, OSC, 0x14, 4, 0x88, 2, 0xA8, 0), + PINGROUP(CDEV2, AUDIO, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, OSC, 0x14, 5, 0x88, 4, 0xA8, 2), + PINGROUP(CRTP, LCD, CRT, RSVD, RSVD, RSVD, RSVD, 0x20, 14, 0x98, 20, 0xA4, 24), + PINGROUP(CSUS, VI, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK, PLLC_OUT1, 0x14, 6, 0x88, 6, 0xAC, 24), + PINGROUP(DAP1, AUDIO, DAP1, RSVD, GMI, SDIO2, DAP1, 0x14, 7, 0x88, 20, 0xA0, 10), + PINGROUP(DAP2, AUDIO, DAP2, TWC, RSVD, GMI, DAP2, 0x14, 8, 0x88, 22, 0xA0, 12), + PINGROUP(DAP3, BB, DAP3, RSVD, RSVD, RSVD, DAP3, 0x14, 9, 0x88, 24, 0xA0, 14), + PINGROUP(DAP4, UART, DAP4, RSVD, GMI, RSVD, DAP4, 0x14, 10, 0x88, 26, 0xA0, 16), + PINGROUP(DDC, LCD, I2C2, RSVD, RSVD, RSVD, RSVD4, 0x18, 31, 0x88, 0, 0xB0, 28), + PINGROUP(DTA, VI, RSVD, SDIO2, VI, RSVD, RSVD4, 0x14, 11, 0x84, 20, 0xA0, 18), + PINGROUP(DTB, VI, RSVD, RSVD, VI, SPI1, RSVD1, 0x14, 12, 0x84, 22, 0xA0, 20), + PINGROUP(DTC, VI, RSVD, RSVD, VI, RSVD, RSVD1, 0x14, 13, 0x84, 26, 0xA0, 22), + PINGROUP(DTD, VI, RSVD, SDIO2, VI, RSVD, RSVD1, 0x14, 14, 0x84, 28, 0xA0, 24), + PINGROUP(DTE, VI, RSVD, RSVD, VI, SPI1, RSVD1, 0x14, 15, 0x84, 30, 0xA0, 26), + PINGROUP(DTF, VI, I2C3, RSVD, VI, RSVD, RSVD4, 0x20, 12, 0x98, 30, 0xA0, 28), + PINGROUP(GMA, NAND, UARTE, SPI3, GMI, SDIO4, SPI3, 0x14, 28, 0x84, 0, 0xB0, 20), + PINGROUP(GMB, NAND, IDE, NAND, GMI, GMI_INT, GMI, 0x18, 29, 0x88, 28, 0xB0, 22), + PINGROUP(GMC, NAND, UARTD, SPI4, GMI, SFLASH, SPI4, 0x14, 29, 0x84, 2, 0xB0, 24), + PINGROUP(GMD, NAND, RSVD, NAND, GMI, SFLASH, GMI, 0x18, 30, 0x88, 30, 0xB0, 26), + PINGROUP(GME, NAND, RSVD, DAP5, GMI, SDIO4, GMI, 0x18, 0, 0x8C, 0, 0xA8, 24), + PINGROUP(GPU, UART, PWM, UARTA, GMI, RSVD, RSVD4, 0x14, 16, 0x8C, 4, 0xA4, 20), + PINGROUP(GPU7, SYS, RTCK, RSVD, RSVD, RSVD, RTCK, 0x20, 11, 0x98, 28, 0xA4, 6), + PINGROUP(GPV, SD, PCIE, RSVD, RSVD, RSVD, PCIE, 0x14, 17, 0x8C, 2, 0xA0, 30), + PINGROUP(HDINT, LCD, HDMI, RSVD, RSVD, RSVD, HDMI, 0x1C, 23, 0x84, 4, 0xAC, 22), + PINGROUP(I2CP, SYS, I2C, RSVD, RSVD, RSVD, RSVD4, 0x14, 18, 0x88, 8, 0xA4, 2), + PINGROUP(IRRX, UART, UARTA, UARTB, GMI, SPI4, UARTB, 0x14, 20, 0x88, 18, 0xA8, 22), + PINGROUP(IRTX, UART, UARTA, UARTB, GMI, SPI4, UARTB, 0x14, 19, 0x88, 16, 0xA8, 20), + PINGROUP(KBCA, SYS, KBC, NAND, SDIO2, EMC_TEST0_DLL, KBC, 0x14, 22, 0x88, 10, 0xA4, 8), + PINGROUP(KBCB, SYS, KBC, NAND, SDIO2, MIO, KBC, 0x14, 21, 0x88, 12, 0xA4, 10), + PINGROUP(KBCC, SYS, KBC, NAND, TRACE, EMC_TEST1_DLL, KBC, 0x18, 26, 0x88, 14, 0xA4, 12), + PINGROUP(KBCD, SYS, KBC, NAND, SDIO2, MIO, KBC, 0x20, 10, 0x98, 26, 0xA4, 14), + PINGROUP(KBCE, SYS, KBC, NAND, OWR, RSVD, KBC, 0x14, 26, 0x80, 28, 0xB0, 2), + PINGROUP(KBCF, SYS, KBC, NAND, TRACE, MIO, KBC, 0x14, 27, 0x80, 26, 0xB0, 0), + PINGROUP(LCSN, LCD, DISPLAYA, DISPLAYB, SPI3, RSVD, RSVD4, 0x1C, 31, 0x90, 12, 0xAC, 20), + PINGROUP(LD0, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 0, 0x94, 0, 0xAC, 12), + PINGROUP(LD1, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 1, 0x94, 2, 0xAC, 12), + PINGROUP(LD10, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 10, 0x94, 20, 0xAC, 12), + PINGROUP(LD11, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 11, 0x94, 22, 0xAC, 12), + PINGROUP(LD12, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 12, 0x94, 24, 0xAC, 12), + PINGROUP(LD13, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 13, 0x94, 26, 0xAC, 12), + PINGROUP(LD14, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 14, 0x94, 28, 0xAC, 12), + PINGROUP(LD15, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 15, 0x94, 30, 0xAC, 12), + PINGROUP(LD16, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 16, 0x98, 0, 0xAC, 12), + PINGROUP(LD17, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 17, 0x98, 2, 0xAC, 12), + PINGROUP(LD2, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 2, 0x94, 4, 0xAC, 12), + PINGROUP(LD3, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 3, 0x94, 6, 0xAC, 12), + PINGROUP(LD4, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 4, 0x94, 8, 0xAC, 12), + PINGROUP(LD5, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 5, 0x94, 10, 0xAC, 12), + PINGROUP(LD6, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 6, 0x94, 12, 0xAC, 12), + PINGROUP(LD7, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 7, 0x94, 14, 0xAC, 12), + PINGROUP(LD8, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 8, 0x94, 16, 0xAC, 12), + PINGROUP(LD9, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 9, 0x94, 18, 0xAC, 12), + PINGROUP(LDC, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 30, 0x90, 14, 0xAC, 20), + PINGROUP(LDI, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x20, 6, 0x98, 16, 0xAC, 18), + PINGROUP(LHP0, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 18, 0x98, 10, 0xAC, 16), + PINGROUP(LHP1, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 19, 0x98, 4, 0xAC, 14), + PINGROUP(LHP2, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 20, 0x98, 6, 0xAC, 14), + PINGROUP(LHS, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x20, 7, 0x90, 22, 0xAC, 22), + PINGROUP(LM0, LCD, DISPLAYA, DISPLAYB, SPI3, RSVD, RSVD4, 0x1C, 24, 0x90, 26, 0xAC, 22), + PINGROUP(LM1, LCD, DISPLAYA, DISPLAYB, RSVD, CRT, RSVD3, 0x1C, 25, 0x90, 28, 0xAC, 22), + PINGROUP(LPP, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x20, 8, 0x98, 14, 0xAC, 18), + PINGROUP(LPW0, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 3, 0x90, 0, 0xAC, 20), + PINGROUP(LPW1, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x20, 4, 0x90, 2, 0xAC, 20), + PINGROUP(LPW2, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 5, 0x90, 4, 0xAC, 20), + PINGROUP(LSC0, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 27, 0x90, 18, 0xAC, 22), + PINGROUP(LSC1, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x1C, 28, 0x90, 20, 0xAC, 20), + PINGROUP(LSCK, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x1C, 29, 0x90, 16, 0xAC, 20), + PINGROUP(LSDA, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 1, 0x90, 8, 0xAC, 20), + PINGROUP(LSDI, LCD, DISPLAYA, DISPLAYB, SPI3, RSVD, DISPLAYA, 0x20, 2, 0x90, 6, 0xAC, 20), + PINGROUP(LSPI, LCD, DISPLAYA, DISPLAYB, XIO, HDMI, DISPLAYA, 0x20, 0, 0x90, 10, 0xAC, 22), + PINGROUP(LVP0, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 21, 0x90, 30, 0xAC, 22), + PINGROUP(LVP1, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 22, 0x98, 8, 0xAC, 16), + PINGROUP(LVS, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 26, 0x90, 24, 0xAC, 22), + PINGROUP(OWC, SYS, OWR, RSVD, RSVD, RSVD, OWR, 0x14, 31, 0x84, 8, 0xB0, 30), + PINGROUP(PMC, SYS, PWR_ON, PWR_INTR, RSVD, RSVD, PWR_ON, 0x14, 23, 0x98, 18, -1, -1), + PINGROUP(PTA, NAND, I2C2, HDMI, GMI, RSVD, RSVD4, 0x14, 24, 0x98, 22, 0xA4, 4), + PINGROUP(RM, UART, I2C, RSVD, RSVD, RSVD, RSVD4, 0x14, 25, 0x80, 14, 0xA4, 0), + PINGROUP(SDB, SD, UARTA, PWM, SDIO3, SPI2, PWM, 0x20, 15, 0x8C, 10, -1, -1), + PINGROUP(SDC, SD, PWM, TWC, SDIO3, SPI3, TWC, 0x18, 1, 0x8C, 12, 0xAC, 28), + PINGROUP(SDD, SD, UARTA, PWM, SDIO3, SPI3, PWM, 0x18, 2, 0x8C, 14, 0xAC, 30), + PINGROUP(SDIO1, BB, SDIO1, RSVD, UARTE, UARTA, RSVD2, 0x14, 30, 0x80, 30, 0xB0, 18), + PINGROUP(SLXA, SD, PCIE, SPI4, SDIO3, SPI2, PCIE, 0x18, 3, 0x84, 6, 0xA4, 22), + PINGROUP(SLXC, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4, 0x18, 5, 0x84, 10, 0xA4, 26), + PINGROUP(SLXD, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4, 0x18, 6, 0x84, 12, 0xA4, 28), + PINGROUP(SLXK, SD, PCIE, SPI4, SDIO3, SPI2, PCIE, 0x18, 7, 0x84, 14, 0xA4, 30), + PINGROUP(SPDI, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2, 0x18, 8, 0x8C, 8, 0xA4, 16), + PINGROUP(SPDO, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2, 0x18, 9, 0x8C, 6, 0xA4, 18), + PINGROUP(SPIA, AUDIO, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 10, 0x8C, 30, 0xA8, 4), + PINGROUP(SPIB, AUDIO, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 11, 0x8C, 28, 0xA8, 6), + PINGROUP(SPIC, AUDIO, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 12, 0x8C, 26, 0xA8, 8), + PINGROUP(SPID, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI, 0x18, 13, 0x8C, 24, 0xA8, 10), + PINGROUP(SPIE, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI, 0x18, 14, 0x8C, 22, 0xA8, 12), + PINGROUP(SPIF, AUDIO, SPI3, SPI1, SPI2, RSVD, RSVD4, 0x18, 15, 0x8C, 20, 0xA8, 14), + PINGROUP(SPIG, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT, 0x18, 16, 0x8C, 18, 0xA8, 16), + PINGROUP(SPIH, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT, 0x18, 17, 0x8C, 16, 0xA8, 18), + PINGROUP(UAA, BB, SPI3, MIPI_HS, UARTA, ULPI, MIPI_HS, 0x18, 18, 0x80, 0, 0xAC, 0), + PINGROUP(UAB, BB, SPI2, MIPI_HS, UARTA, ULPI, MIPI_HS, 0x18, 19, 0x80, 2, 0xAC, 2), + PINGROUP(UAC, BB, OWR, RSVD, RSVD, RSVD, RSVD4, 0x18, 20, 0x80, 4, 0xAC, 4), + PINGROUP(UAD, UART, IRDA, SPDIF, UARTA, SPI4, SPDIF, 0x18, 21, 0x80, 6, 0xAC, 6), + PINGROUP(UCA, UART, UARTC, RSVD, GMI, RSVD, RSVD4, 0x18, 22, 0x84, 16, 0xAC, 8), + PINGROUP(UCB, UART, UARTC, PWM, GMI, RSVD, RSVD4, 0x18, 23, 0x84, 18, 0xAC, 10), + PINGROUP(UDA, BB, SPI1, RSVD, UARTD, ULPI, RSVD2, 0x20, 13, 0x80, 8, 0xB0, 16), + /* these pin groups only have pullup and pull down control */ + PINGROUP(CK32, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 14), + PINGROUP(DDRC, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xAC, 26), + PINGROUP(PMCA, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 4), + PINGROUP(PMCB, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 6), + PINGROUP(PMCC, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 8), + PINGROUP(PMCD, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 10), + PINGROUP(PMCE, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 12), + PINGROUP(XM2C, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 30), + PINGROUP(XM2D, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 28), +}; + +#ifdef CONFIG_PM +#define TRISTATE_REG_A 0x14 +#define TRISTATE_REG_NUM 4 +#define PIN_MUX_CTL_REG_A 0x80 +#define PIN_MUX_CTL_REG_NUM 8 +#define PULLUPDOWN_REG_A 0xa0 +#define PULLUPDOWN_REG_NUM 5 + +static u32 pinmux_reg[TRISTATE_REG_NUM + PIN_MUX_CTL_REG_NUM + + PULLUPDOWN_REG_NUM]; + +static inline unsigned long pg_readl(unsigned long offset) +{ + return readl(IO_TO_VIRT(TEGRA_APB_MISC_BASE + offset)); +} + +static inline void pg_writel(unsigned long value, unsigned long offset) +{ + writel(value, IO_TO_VIRT(TEGRA_APB_MISC_BASE + offset)); +} + +void tegra_pinmux_suspend(void) +{ + unsigned int i; + u32 *ctx = pinmux_reg; + + for (i = 0; i < TRISTATE_REG_NUM; i++) + *ctx++ = pg_readl(TRISTATE_REG_A + i*4); + + for (i = 0; i < PIN_MUX_CTL_REG_NUM; i++) + *ctx++ = pg_readl(PIN_MUX_CTL_REG_A + i*4); + + for (i = 0; i < PULLUPDOWN_REG_NUM; i++) + *ctx++ = pg_readl(PULLUPDOWN_REG_A + i*4); +} + +void tegra_pinmux_resume(void) +{ + unsigned int i; + u32 *ctx = pinmux_reg; + + for (i = 0; i < PIN_MUX_CTL_REG_NUM; i++) + pg_writel(*ctx++, PIN_MUX_CTL_REG_A + i*4); + + for (i = 0; i < PULLUPDOWN_REG_NUM; i++) + pg_writel(*ctx++, PULLUPDOWN_REG_A + i*4); + + for (i = 0; i < TRISTATE_REG_NUM; i++) + pg_writel(*ctx++, TRISTATE_REG_A + i*4); +} +#endif diff --git a/arch/arm/mach-tegra/pinmux.c b/arch/arm/mach-tegra/pinmux.c index 13ae10237e84..f80d507671bc 100644 --- a/arch/arm/mach-tegra/pinmux.c +++ b/arch/arm/mach-tegra/pinmux.c @@ -14,7 +14,8 @@ * */ - +#include <linux/init.h> +#include <linux/module.h> #include <linux/kernel.h> #include <linux/errno.h> #include <linux/spinlock.h> @@ -23,21 +24,6 @@ #include <mach/iomap.h> #include <mach/pinmux.h> - -#define TEGRA_TRI_STATE(x) (0x14 + (4 * (x))) -#define TEGRA_PP_MUX_CTL(x) (0x80 + (4 * (x))) -#define TEGRA_PP_PU_PD(x) (0xa0 + (4 * (x))) - -#define REG_A 0 -#define REG_B 1 -#define REG_C 2 -#define REG_D 3 -#define REG_E 4 -#define REG_F 5 -#define REG_G 6 - -#define REG_N -1 - #define HSM_EN(reg) (((reg) >> 2) & 0x1) #define SCHMT_EN(reg) (((reg) >> 3) & 0x1) #define LPMD(reg) (((reg) >> 4) & 0x3) @@ -46,154 +32,8 @@ #define SLWR(reg) (((reg) >> 28) & 0x3) #define SLWF(reg) (((reg) >> 30) & 0x3) -struct tegra_pingroup_desc { - const char *name; - int funcs[4]; - s8 tri_reg; /* offset into the TRISTATE_REG_* register bank */ - s8 tri_bit; /* offset into the TRISTATE_REG_* register bit */ - s8 mux_reg; /* offset into the PIN_MUX_CTL_* register bank */ - s8 mux_bit; /* offset into the PIN_MUX_CTL_* register bit */ - s8 pupd_reg; /* offset into the PULL_UPDOWN_REG_* register bank */ - s8 pupd_bit; /* offset into the PULL_UPDOWN_REG_* register bit */ -}; - -#define PINGROUP(pg_name, f0, f1, f2, f3, \ - tri_r, tri_b, mux_r, mux_b, pupd_r, pupd_b) \ - [TEGRA_PINGROUP_ ## pg_name] = { \ - .name = #pg_name, \ - .funcs = { \ - TEGRA_MUX_ ## f0, \ - TEGRA_MUX_ ## f1, \ - TEGRA_MUX_ ## f2, \ - TEGRA_MUX_ ## f3, \ - }, \ - .tri_reg = REG_ ## tri_r, \ - .tri_bit = tri_b, \ - .mux_reg = REG_ ## mux_r, \ - .mux_bit = mux_b, \ - .pupd_reg = REG_ ## pupd_r, \ - .pupd_bit = pupd_b, \ - } - -static const struct tegra_pingroup_desc pingroups[TEGRA_MAX_PINGROUP] = { - PINGROUP(ATA, IDE, NAND, GMI, RSVD, A, 0, A, 24, A, 0), - PINGROUP(ATB, IDE, NAND, GMI, SDIO4, A, 1, A, 16, A, 2), - PINGROUP(ATC, IDE, NAND, GMI, SDIO4, A, 2, A, 22, A, 4), - PINGROUP(ATD, IDE, NAND, GMI, SDIO4, A, 3, A, 20, A, 6), - PINGROUP(ATE, IDE, NAND, GMI, RSVD, B, 25, A, 12, A, 8), - PINGROUP(CDEV1, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, A, 4, C, 2, C, 0), - PINGROUP(CDEV2, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, A, 5, C, 4, C, 2), - PINGROUP(CRTP, CRT, RSVD, RSVD, RSVD, D, 14, G, 20, B, 24), - PINGROUP(CSUS, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK, A, 6, C, 6, D, 24), - PINGROUP(DAP1, DAP1, RSVD, GMI, SDIO2, A, 7, C, 20, A, 10), - PINGROUP(DAP2, DAP2, TWC, RSVD, GMI, A, 8, C, 22, A, 12), - PINGROUP(DAP3, DAP3, RSVD, RSVD, RSVD, A, 9, C, 24, A, 14), - PINGROUP(DAP4, DAP4, RSVD, GMI, RSVD, A, 10, C, 26, A, 16), - PINGROUP(DDC, I2C2, RSVD, RSVD, RSVD, B, 31, C, 0, E, 28), - PINGROUP(DTA, RSVD, SDIO2, VI, RSVD, A, 11, B, 20, A, 18), - PINGROUP(DTB, RSVD, RSVD, VI, SPI1, A, 12, B, 22, A, 20), - PINGROUP(DTC, RSVD, RSVD, VI, RSVD, A, 13, B, 26, A, 22), - PINGROUP(DTD, RSVD, SDIO2, VI, RSVD, A, 14, B, 28, A, 24), - PINGROUP(DTE, RSVD, RSVD, VI, SPI1, A, 15, B, 30, A, 26), - PINGROUP(DTF, I2C3, RSVD, VI, RSVD, D, 12, G, 30, A, 28), - PINGROUP(GMA, UARTE, SPI3, GMI, SDIO4, A, 28, B, 0, E, 20), - PINGROUP(GMB, IDE, NAND, GMI, GMI_INT, B, 29, C, 28, E, 22), - PINGROUP(GMC, UARTD, SPI4, GMI, SFLASH, A, 29, B, 2, E, 24), - PINGROUP(GMD, RSVD, NAND, GMI, SFLASH, B, 30, C, 30, E, 26), - PINGROUP(GME, RSVD, DAP5, GMI, SDIO4, B, 0, D, 0, C, 24), - PINGROUP(GPU, PWM, UARTA, GMI, RSVD, A, 16, D, 4, B, 20), - PINGROUP(GPU7, RTCK, RSVD, RSVD, RSVD, D, 11, G, 28, B, 6), - PINGROUP(GPV, PCIE, RSVD, RSVD, RSVD, A, 17, D, 2, A, 30), - PINGROUP(HDINT, HDMI, RSVD, RSVD, RSVD, C, 23, B, 4, D, 22), - PINGROUP(I2CP, I2C, RSVD, RSVD, RSVD, A, 18, C, 8, B, 2), - PINGROUP(IRRX, UARTA, UARTB, GMI, SPI4, A, 20, C, 18, C, 22), - PINGROUP(IRTX, UARTA, UARTB, GMI, SPI4, A, 19, C, 16, C, 20), - PINGROUP(KBCA, KBC, NAND, SDIO2, EMC_TEST0_DLL, A, 22, C, 10, B, 8), - PINGROUP(KBCB, KBC, NAND, SDIO2, MIO, A, 21, C, 12, B, 10), - PINGROUP(KBCC, KBC, NAND, TRACE, EMC_TEST1_DLL, B, 26, C, 14, B, 12), - PINGROUP(KBCD, KBC, NAND, SDIO2, MIO, D, 10, G, 26, B, 14), - PINGROUP(KBCE, KBC, NAND, OWR, RSVD, A, 26, A, 28, E, 2), - PINGROUP(KBCF, KBC, NAND, TRACE, MIO, A, 27, A, 26, E, 0), - PINGROUP(LCSN, DISPLAYA, DISPLAYB, SPI3, RSVD, C, 31, E, 12, D, 20), - PINGROUP(LD0, DISPLAYA, DISPLAYB, XIO, RSVD, C, 0, F, 0, D, 12), - PINGROUP(LD1, DISPLAYA, DISPLAYB, XIO, RSVD, C, 1, F, 2, D, 12), - PINGROUP(LD10, DISPLAYA, DISPLAYB, XIO, RSVD, C, 10, F, 20, D, 12), - PINGROUP(LD11, DISPLAYA, DISPLAYB, XIO, RSVD, C, 11, F, 22, D, 12), - PINGROUP(LD12, DISPLAYA, DISPLAYB, XIO, RSVD, C, 12, F, 24, D, 12), - PINGROUP(LD13, DISPLAYA, DISPLAYB, XIO, RSVD, C, 13, F, 26, D, 12), - PINGROUP(LD14, DISPLAYA, DISPLAYB, XIO, RSVD, C, 14, F, 28, D, 12), - PINGROUP(LD15, DISPLAYA, DISPLAYB, XIO, RSVD, C, 15, F, 30, D, 12), - PINGROUP(LD16, DISPLAYA, DISPLAYB, XIO, RSVD, C, 16, G, 0, D, 12), - PINGROUP(LD17, DISPLAYA, DISPLAYB, RSVD, RSVD, C, 17, G, 2, D, 12), - PINGROUP(LD2, DISPLAYA, DISPLAYB, XIO, RSVD, C, 2, F, 4, D, 12), - PINGROUP(LD3, DISPLAYA, DISPLAYB, XIO, RSVD, C, 3, F, 6, D, 12), - PINGROUP(LD4, DISPLAYA, DISPLAYB, XIO, RSVD, C, 4, F, 8, D, 12), - PINGROUP(LD5, DISPLAYA, DISPLAYB, XIO, RSVD, C, 5, F, 10, D, 12), - PINGROUP(LD6, DISPLAYA, DISPLAYB, XIO, RSVD, C, 6, F, 12, D, 12), - PINGROUP(LD7, DISPLAYA, DISPLAYB, XIO, RSVD, C, 7, F, 14, D, 12), - PINGROUP(LD8, DISPLAYA, DISPLAYB, XIO, RSVD, C, 8, F, 16, D, 12), - PINGROUP(LD9, DISPLAYA, DISPLAYB, XIO, RSVD, C, 9, F, 18, D, 12), - PINGROUP(LDC, DISPLAYA, DISPLAYB, RSVD, RSVD, C, 30, E, 14, D, 20), - PINGROUP(LDI, DISPLAYA, DISPLAYB, RSVD, RSVD, D, 6, G, 16, D, 18), - PINGROUP(LHP0, DISPLAYA, DISPLAYB, RSVD, RSVD, C, 18, G, 10, D, 16), - PINGROUP(LHP1, DISPLAYA, DISPLAYB, RSVD, RSVD, C, 19, G, 4, D, 14), - PINGROUP(LHP2, DISPLAYA, DISPLAYB, RSVD, RSVD, C, 20, G, 6, D, 14), - PINGROUP(LHS, DISPLAYA, DISPLAYB, XIO, RSVD, D, 7, E, 22, D, 22), - PINGROUP(LM0, DISPLAYA, DISPLAYB, SPI3, RSVD, C, 24, E, 26, D, 22), - PINGROUP(LM1, DISPLAYA, DISPLAYB, RSVD, CRT, C, 25, E, 28, D, 22), - PINGROUP(LPP, DISPLAYA, DISPLAYB, RSVD, RSVD, D, 8, G, 14, D, 18), - PINGROUP(LPW0, DISPLAYA, DISPLAYB, SPI3, HDMI, D, 3, E, 0, D, 20), - PINGROUP(LPW1, DISPLAYA, DISPLAYB, RSVD, RSVD, D, 4, E, 2, D, 20), - PINGROUP(LPW2, DISPLAYA, DISPLAYB, SPI3, HDMI, D, 5, E, 4, D, 20), - PINGROUP(LSC0, DISPLAYA, DISPLAYB, XIO, RSVD, C, 27, E, 18, D, 22), - PINGROUP(LSC1, DISPLAYA, DISPLAYB, SPI3, HDMI, C, 28, E, 20, D, 20), - PINGROUP(LSCK, DISPLAYA, DISPLAYB, SPI3, HDMI, C, 29, E, 16, D, 20), - PINGROUP(LSDA, DISPLAYA, DISPLAYB, SPI3, HDMI, D, 1, E, 8, D, 20), - PINGROUP(LSDI, DISPLAYA, DISPLAYB, SPI3, RSVD, D, 2, E, 6, D, 20), - PINGROUP(LSPI, DISPLAYA, DISPLAYB, XIO, HDMI, D, 0, E, 10, D, 22), - PINGROUP(LVP0, DISPLAYA, DISPLAYB, RSVD, RSVD, C, 21, E, 30, D, 22), - PINGROUP(LVP1, DISPLAYA, DISPLAYB, RSVD, RSVD, C, 22, G, 8, D, 16), - PINGROUP(LVS, DISPLAYA, DISPLAYB, XIO, RSVD, C, 26, E, 24, D, 22), - PINGROUP(OWC, OWR, RSVD, RSVD, RSVD, A, 31, B, 8, E, 30), - PINGROUP(PMC, PWR_ON, PWR_INTR, RSVD, RSVD, A, 23, G, 18, N, -1), - PINGROUP(PTA, I2C2, HDMI, GMI, RSVD, A, 24, G, 22, B, 4), - PINGROUP(RM, I2C, RSVD, RSVD, RSVD, A, 25, A, 14, B, 0), - PINGROUP(SDB, UARTA, PWM, SDIO3, SPI2, D, 15, D, 10, N, -1), - PINGROUP(SDC, PWM, TWC, SDIO3, SPI3, B, 1, D, 12, D, 28), - PINGROUP(SDD, UARTA, PWM, SDIO3, SPI3, B, 2, D, 14, D, 30), - PINGROUP(SDIO1, SDIO1, RSVD, UARTE, UARTA, A, 30, A, 30, E, 18), - PINGROUP(SLXA, PCIE, SPI4, SDIO3, SPI2, B, 3, B, 6, B, 22), - PINGROUP(SLXC, SPDIF, SPI4, SDIO3, SPI2, B, 5, B, 10, B, 26), - PINGROUP(SLXD, SPDIF, SPI4, SDIO3, SPI2, B, 6, B, 12, B, 28), - PINGROUP(SLXK, PCIE, SPI4, SDIO3, SPI2, B, 7, B, 14, B, 30), - PINGROUP(SPDI, SPDIF, RSVD, I2C, SDIO2, B, 8, D, 8, B, 16), - PINGROUP(SPDO, SPDIF, RSVD, I2C, SDIO2, B, 9, D, 6, B, 18), - PINGROUP(SPIA, SPI1, SPI2, SPI3, GMI, B, 10, D, 30, C, 4), - PINGROUP(SPIB, SPI1, SPI2, SPI3, GMI, B, 11, D, 28, C, 6), - PINGROUP(SPIC, SPI1, SPI2, SPI3, GMI, B, 12, D, 26, C, 8), - PINGROUP(SPID, SPI2, SPI1, SPI2_ALT, GMI, B, 13, D, 24, C, 10), - PINGROUP(SPIE, SPI2, SPI1, SPI2_ALT, GMI, B, 14, D, 22, C, 12), - PINGROUP(SPIF, SPI3, SPI1, SPI2, RSVD, B, 15, D, 20, C, 14), - PINGROUP(SPIG, SPI3, SPI2, SPI2_ALT, I2C, B, 16, D, 18, C, 16), - PINGROUP(SPIH, SPI3, SPI2, SPI2_ALT, I2C, B, 17, D, 16, C, 18), - PINGROUP(UAA, SPI3, MIPI_HS, UARTA, ULPI, B, 18, A, 0, D, 0), - PINGROUP(UAB, SPI2, MIPI_HS, UARTA, ULPI, B, 19, A, 2, D, 2), - PINGROUP(UAC, OWR, RSVD, RSVD, RSVD, B, 20, A, 4, D, 4), - PINGROUP(UAD, IRDA, SPDIF, UARTA, SPI4, B, 21, A, 6, D, 6), - PINGROUP(UCA, UARTC, RSVD, GMI, RSVD, B, 22, B, 16, D, 8), - PINGROUP(UCB, UARTC, PWM, GMI, RSVD, B, 23, B, 18, D, 10), - PINGROUP(UDA, SPI1, RSVD, UARTD, ULPI, D, 13, A, 8, E, 16), - /* these pin groups only have pullup and pull down control */ - PINGROUP(CK32, RSVD, RSVD, RSVD, RSVD, N, -1, N, -1, E, 14), - PINGROUP(DDRC, RSVD, RSVD, RSVD, RSVD, N, -1, N, -1, D, 26), - PINGROUP(PMCA, RSVD, RSVD, RSVD, RSVD, N, -1, N, -1, E, 4), - PINGROUP(PMCB, RSVD, RSVD, RSVD, RSVD, N, -1, N, -1, E, 6), - PINGROUP(PMCC, RSVD, RSVD, RSVD, RSVD, N, -1, N, -1, E, 8), - PINGROUP(PMCD, RSVD, RSVD, RSVD, RSVD, N, -1, N, -1, E, 10), - PINGROUP(PMCE, RSVD, RSVD, RSVD, RSVD, N, -1, N, -1, E, 12), - PINGROUP(XM2C, RSVD, RSVD, RSVD, RSVD, N, -1, N, -1, C, 30), - PINGROUP(XM2D, RSVD, RSVD, RSVD, RSVD, N, -1, N, -1, C, 28), -}; +static const struct tegra_pingroup_desc *const pingroups = tegra_soc_pingroups; +static const struct tegra_drive_pingroup_desc *const drive_pingroups = tegra_soc_drive_pingroups; static char *tegra_mux_names[TEGRA_MAX_MUX] = { [TEGRA_MUX_AHB_CLK] = "AHB_CLK", @@ -256,48 +96,7 @@ static char *tegra_mux_names[TEGRA_MAX_MUX] = { [TEGRA_MUX_VI] = "VI", [TEGRA_MUX_VI_SENSOR_CLK] = "VI_SENSOR_CLK", [TEGRA_MUX_XIO] = "XIO", -}; - -struct tegra_drive_pingroup_desc { - const char *name; - s16 reg; -}; - -#define DRIVE_PINGROUP(pg_name, r) \ - [TEGRA_DRIVE_PINGROUP_ ## pg_name] = { \ - .name = #pg_name, \ - .reg = r \ - } - -static const struct tegra_drive_pingroup_desc drive_pingroups[TEGRA_MAX_PINGROUP] = { - DRIVE_PINGROUP(AO1, 0x868), - DRIVE_PINGROUP(AO2, 0x86c), - DRIVE_PINGROUP(AT1, 0x870), - DRIVE_PINGROUP(AT2, 0x874), - DRIVE_PINGROUP(CDEV1, 0x878), - DRIVE_PINGROUP(CDEV2, 0x87c), - DRIVE_PINGROUP(CSUS, 0x880), - DRIVE_PINGROUP(DAP1, 0x884), - DRIVE_PINGROUP(DAP2, 0x888), - DRIVE_PINGROUP(DAP3, 0x88c), - DRIVE_PINGROUP(DAP4, 0x890), - DRIVE_PINGROUP(DBG, 0x894), - DRIVE_PINGROUP(LCD1, 0x898), - DRIVE_PINGROUP(LCD2, 0x89c), - DRIVE_PINGROUP(SDMMC2, 0x8a0), - DRIVE_PINGROUP(SDMMC3, 0x8a4), - DRIVE_PINGROUP(SPI, 0x8a8), - DRIVE_PINGROUP(UAA, 0x8ac), - DRIVE_PINGROUP(UAB, 0x8b0), - DRIVE_PINGROUP(UART2, 0x8b4), - DRIVE_PINGROUP(UART3, 0x8b8), - DRIVE_PINGROUP(VI1, 0x8bc), - DRIVE_PINGROUP(VI2, 0x8c0), - DRIVE_PINGROUP(XM2A, 0x8c4), - DRIVE_PINGROUP(XM2C, 0x8c8), - DRIVE_PINGROUP(XM2D, 0x8cc), - DRIVE_PINGROUP(XM2CLK, 0x8d0), - DRIVE_PINGROUP(MEMCOMP, 0x8d4), + [TEGRA_MUX_SAFE] = "<safe>", }; static const char *tegra_drive_names[TEGRA_MAX_DRIVE] = { @@ -381,22 +180,27 @@ static inline void pg_writel(unsigned long value, unsigned long offset) writel(value, IO_TO_VIRT(TEGRA_APB_MISC_BASE + offset)); } -int tegra_pinmux_set_func(enum tegra_pingroup pg, enum tegra_mux_func func) +static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config) { int mux = -1; int i; unsigned long reg; unsigned long flags; + enum tegra_pingroup pg = config->pingroup; + enum tegra_mux_func func = config->func; if (pg < 0 || pg >= TEGRA_MAX_PINGROUP) return -ERANGE; - if (pingroups[pg].mux_reg == REG_N) + if (pingroups[pg].mux_reg < 0) return -EINVAL; if (func < 0) return -ERANGE; + if (func == TEGRA_MUX_SAFE) + func = pingroups[pg].func_safe; + if (func & TEGRA_MUX_RSVD) { mux = func & 0x3; } else { @@ -413,10 +217,10 @@ int tegra_pinmux_set_func(enum tegra_pingroup pg, enum tegra_mux_func func) spin_lock_irqsave(&mux_lock, flags); - reg = pg_readl(TEGRA_PP_MUX_CTL(pingroups[pg].mux_reg)); + reg = pg_readl(pingroups[pg].mux_reg); reg &= ~(0x3 << pingroups[pg].mux_bit); reg |= mux << pingroups[pg].mux_bit; - pg_writel(reg, TEGRA_PP_MUX_CTL(pingroups[pg].mux_reg)); + pg_writel(reg, pingroups[pg].mux_reg); spin_unlock_irqrestore(&mux_lock, flags); @@ -432,16 +236,16 @@ int tegra_pinmux_set_tristate(enum tegra_pingroup pg, if (pg < 0 || pg >= TEGRA_MAX_PINGROUP) return -ERANGE; - if (pingroups[pg].tri_reg == REG_N) + if (pingroups[pg].tri_reg < 0) return -EINVAL; spin_lock_irqsave(&mux_lock, flags); - reg = pg_readl(TEGRA_TRI_STATE(pingroups[pg].tri_reg)); + reg = pg_readl(pingroups[pg].tri_reg); reg &= ~(0x1 << pingroups[pg].tri_bit); if (tristate) reg |= 1 << pingroups[pg].tri_bit; - pg_writel(reg, TEGRA_TRI_STATE(pingroups[pg].tri_reg)); + pg_writel(reg, pingroups[pg].tri_reg); spin_unlock_irqrestore(&mux_lock, flags); @@ -457,7 +261,7 @@ int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg, if (pg < 0 || pg >= TEGRA_MAX_PINGROUP) return -ERANGE; - if (pingroups[pg].pupd_reg == REG_N) + if (pingroups[pg].pupd_reg < 0) return -EINVAL; if (pupd != TEGRA_PUPD_NORMAL && @@ -468,38 +272,39 @@ int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg, spin_lock_irqsave(&mux_lock, flags); - reg = pg_readl(TEGRA_PP_PU_PD(pingroups[pg].pupd_reg)); + reg = pg_readl(pingroups[pg].pupd_reg); reg &= ~(0x3 << pingroups[pg].pupd_bit); reg |= pupd << pingroups[pg].pupd_bit; - pg_writel(reg, TEGRA_PP_PU_PD(pingroups[pg].pupd_reg)); + pg_writel(reg, pingroups[pg].pupd_reg); spin_unlock_irqrestore(&mux_lock, flags); return 0; } -void tegra_pinmux_config_pingroup(enum tegra_pingroup pingroup, - enum tegra_mux_func func, - enum tegra_pullupdown pupd, - enum tegra_tristate tristate) +static void tegra_pinmux_config_pingroup(const struct tegra_pingroup_config *config) { + enum tegra_pingroup pingroup = config->pingroup; + enum tegra_mux_func func = config->func; + enum tegra_pullupdown pupd = config->pupd; + enum tegra_tristate tristate = config->tristate; int err; - if (pingroups[pingroup].mux_reg != REG_N) { - err = tegra_pinmux_set_func(pingroup, func); + if (pingroups[pingroup].mux_reg >= 0) { + err = tegra_pinmux_set_func(config); if (err < 0) pr_err("pinmux: can't set pingroup %s func to %s: %d\n", pingroup_name(pingroup), func_name(func), err); } - if (pingroups[pingroup].pupd_reg != REG_N) { + if (pingroups[pingroup].pupd_reg >= 0) { err = tegra_pinmux_set_pullupdown(pingroup, pupd); if (err < 0) pr_err("pinmux: can't set pingroup %s pullupdown to %s: %d\n", pingroup_name(pingroup), pupd_name(pupd), err); } - if (pingroups[pingroup].tri_reg != REG_N) { + if (pingroups[pingroup].tri_reg >= 0) { err = tegra_pinmux_set_tristate(pingroup, tristate); if (err < 0) pr_err("pinmux: can't set pingroup %s tristate to %s: %d\n", @@ -507,17 +312,12 @@ void tegra_pinmux_config_pingroup(enum tegra_pingroup pingroup, } } - - -void tegra_pinmux_config_table(struct tegra_pingroup_config *config, int len) +void tegra_pinmux_config_table(const struct tegra_pingroup_config *config, int len) { int i; for (i = 0; i < len; i++) - tegra_pinmux_config_pingroup(config[i].pingroup, - config[i].func, - config[i].pupd, - config[i].tristate); + tegra_pinmux_config_pingroup(&config[i]); } static const char *drive_pinmux_name(enum tegra_drive_pingroup pg) @@ -784,6 +584,86 @@ void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config, config[i].slew_falling); } +void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config, + int len) +{ + int i; + struct tegra_pingroup_config c; + + for (i = 0; i < len; i++) { + int err; + c = config[i]; + if (c.pingroup < 0 || c.pingroup >= TEGRA_MAX_PINGROUP) { + WARN_ON(1); + continue; + } + c.func = pingroups[c.pingroup].func_safe; + err = tegra_pinmux_set_func(&c); + if (err < 0) + pr_err("%s: tegra_pinmux_set_func returned %d setting " + "%s to %s\n", __func__, err, + pingroup_name(c.pingroup), func_name(c.func)); + } +} + +void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config, + int len) +{ + int i; + + for (i = 0; i < len; i++) { + int err; + if (config[i].pingroup < 0 || + config[i].pingroup >= TEGRA_MAX_PINGROUP) { + WARN_ON(1); + continue; + } + err = tegra_pinmux_set_func(&config[i]); + if (err < 0) + pr_err("%s: tegra_pinmux_set_func returned %d setting " + "%s to %s\n", __func__, err, + pingroup_name(config[i].pingroup), + func_name(config[i].func)); + } +} + +void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config, + int len, enum tegra_tristate tristate) +{ + int i; + int err; + enum tegra_pingroup pingroup; + + for (i = 0; i < len; i++) { + pingroup = config[i].pingroup; + if (pingroups[pingroup].tri_reg >= 0) { + err = tegra_pinmux_set_tristate(pingroup, tristate); + if (err < 0) + pr_err("pinmux: can't set pingroup %s tristate" + " to %s: %d\n", pingroup_name(pingroup), + tri_name(tristate), err); + } + } +} + +void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config, + int len, enum tegra_pullupdown pupd) +{ + int i; + int err; + enum tegra_pingroup pingroup; + + for (i = 0; i < len; i++) { + pingroup = config[i].pingroup; + if (pingroups[pingroup].pupd_reg >= 0) { + err = tegra_pinmux_set_pullupdown(pingroup, pupd); + if (err < 0) + pr_err("pinmux: can't set pingroup %s pullupdown" + " to %s: %d\n", pingroup_name(pingroup), + pupd_name(pupd), err); + } + } +} #ifdef CONFIG_DEBUG_FS @@ -812,11 +692,11 @@ static int dbg_pinmux_show(struct seq_file *s, void *unused) len = strlen(pingroups[i].name); dbg_pad_field(s, 5 - len); - if (pingroups[i].mux_reg == REG_N) { + if (pingroups[i].mux_reg < 0) { seq_printf(s, "TEGRA_MUX_NONE"); len = strlen("NONE"); } else { - mux = (pg_readl(TEGRA_PP_MUX_CTL(pingroups[i].mux_reg)) >> + mux = (pg_readl(pingroups[i].mux_reg) >> pingroups[i].mux_bit) & 0x3; if (pingroups[i].funcs[mux] == TEGRA_MUX_RSVD) { seq_printf(s, "TEGRA_MUX_RSVD%1lu", mux+1); @@ -829,21 +709,21 @@ static int dbg_pinmux_show(struct seq_file *s, void *unused) } dbg_pad_field(s, 13-len); - if (pingroups[i].mux_reg == REG_N) { + if (pingroups[i].pupd_reg < 0) { seq_printf(s, "TEGRA_PUPD_NORMAL"); len = strlen("NORMAL"); } else { - pupd = (pg_readl(TEGRA_PP_PU_PD(pingroups[i].pupd_reg)) >> + pupd = (pg_readl(pingroups[i].pupd_reg) >> pingroups[i].pupd_bit) & 0x3; seq_printf(s, "TEGRA_PUPD_%s", pupd_name(pupd)); len = strlen(pupd_name(pupd)); } dbg_pad_field(s, 9 - len); - if (pingroups[i].tri_reg == REG_N) { + if (pingroups[i].tri_reg < 0) { seq_printf(s, "TEGRA_TRI_NORMAL"); } else { - tri = (pg_readl(TEGRA_TRI_STATE(pingroups[i].tri_reg)) >> + tri = (pg_readl(pingroups[i].tri_reg) >> pingroups[i].tri_bit) & 0x1; seq_printf(s, "TEGRA_TRI_%s", tri_name(tri)); diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index 426163231fff..ae3b308e22a4 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c @@ -30,14 +30,21 @@ #include <mach/iomap.h> #include "clock.h" +#include "fuse.h" +#include "tegra2_dvfs.h" #define RST_DEVICES 0x004 #define RST_DEVICES_SET 0x300 #define RST_DEVICES_CLR 0x304 +#define RST_DEVICES_NUM 3 #define CLK_OUT_ENB 0x010 #define CLK_OUT_ENB_SET 0x320 #define CLK_OUT_ENB_CLR 0x324 +#define CLK_OUT_ENB_NUM 3 + +#define CLK_MASK_ARM 0x44 +#define MISC_CLK_ENB 0x48 #define OSC_CTRL 0x50 #define OSC_CTRL_OSC_FREQ_MASK (3<<30) @@ -45,6 +52,7 @@ #define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30) #define OSC_CTRL_OSC_FREQ_12MHZ (2<<30) #define OSC_CTRL_OSC_FREQ_26MHZ (3<<30) +#define OSC_CTRL_MASK 0x3f2 #define OSC_FREQ_DET 0x58 #define OSC_FREQ_DET_TRIG (1<<31) @@ -53,10 +61,17 @@ #define OSC_FREQ_DET_BUSY (1<<31) #define OSC_FREQ_DET_CNT_MASK 0xFFFF +#define PERIPH_CLK_SOURCE_I2S1 0x100 +#define PERIPH_CLK_SOURCE_EMC 0x19c +#define PERIPH_CLK_SOURCE_OSC 0x1fc +#define PERIPH_CLK_SOURCE_NUM \ + ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4) + #define PERIPH_CLK_SOURCE_MASK (3<<30) #define PERIPH_CLK_SOURCE_SHIFT 30 #define PERIPH_CLK_SOURCE_ENABLE (1<<28) -#define PERIPH_CLK_SOURCE_DIV_MASK 0xFF +#define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF +#define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF #define PERIPH_CLK_SOURCE_DIV_SHIFT 0 #define PLL_BASE 0x0 @@ -79,8 +94,9 @@ #define PLL_OUT_RESET_DISABLE (1<<0) #define PLL_MISC(c) (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc) +#define PLL_MISC_LOCK_ENABLE(c) (((c)->flags & PLLU) ? (1<<22) : (1<<18)) + #define PLL_MISC_DCCON_SHIFT 20 -#define PLL_MISC_LOCK_ENABLE (1<<18) #define PLL_MISC_CPCON_SHIFT 8 #define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT) #define PLL_MISC_LFCON_SHIFT 4 @@ -88,10 +104,14 @@ #define PLL_MISC_VCOCON_SHIFT 0 #define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT) +#define PLLU_BASE_POST_DIV (1<<20) + #define PLLD_MISC_CLKENABLE (1<<30) #define PLLD_MISC_DIV_RST (1<<23) #define PLLD_MISC_DCCON_SHIFT 12 +#define PLLE_MISC_READY (1 << 15) + #define PERIPH_CLK_TO_ENB_REG(c) ((c->clk_num / 32) * 4) #define PERIPH_CLK_TO_ENB_SET_REG(c) ((c->clk_num / 32) * 8) #define PERIPH_CLK_TO_ENB_BIT(c) (1 << (c->clk_num % 32)) @@ -143,30 +163,37 @@ unsigned long clk_measure_input_freq(void) } } -static int clk_div71_get_divider(struct clk *c, unsigned long rate) +static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate) { - unsigned long divider_u71; + s64 divider_u71 = parent_rate * 2; + divider_u71 += rate - 1; + do_div(divider_u71, rate); - divider_u71 = DIV_ROUND_UP(c->rate * 2, rate); + if (divider_u71 - 2 < 0) + return 0; - if (divider_u71 - 2 > 255 || divider_u71 - 2 < 0) + if (divider_u71 - 2 > 255) return -EINVAL; return divider_u71 - 2; } -static unsigned long tegra2_clk_recalculate_rate(struct clk *c) +static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate) { - unsigned long rate; - rate = c->parent->rate; + s64 divider_u16; - if (c->mul != 0 && c->div != 0) - c->rate = rate * c->mul / c->div; - else - c->rate = rate; - return c->rate; -} + divider_u16 = parent_rate; + divider_u16 += rate - 1; + do_div(divider_u16, rate); + + if (divider_u16 - 1 < 0) + return 0; + if (divider_u16 - 1 > 255) + return -EINVAL; + + return divider_u16 - 1; +} /* clk_m functions */ static unsigned long tegra2_clk_m_autodetect_rate(struct clk *c) @@ -244,7 +271,6 @@ static void tegra2_super_clk_init(struct clk *c) } BUG_ON(sel->input == NULL); c->parent = sel->input; - tegra2_clk_recalculate_rate(c); } static int tegra2_super_clk_enable(struct clk *c) @@ -266,6 +292,7 @@ static int tegra2_super_clk_set_parent(struct clk *c, struct clk *p) u32 val; const struct clk_mux_sel *sel; int shift; + val = clk_readl(c->reg + SUPER_CLK_MUX);; BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) && ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE)); @@ -273,11 +300,18 @@ static int tegra2_super_clk_set_parent(struct clk *c, struct clk *p) SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT; for (sel = c->inputs; sel->input != NULL; sel++) { if (sel->input == p) { - clk_reparent(c, p); val &= ~(SUPER_SOURCE_MASK << shift); val |= sel->value << shift; + + if (c->refcnt) + clk_enable_locked(p); + clk_writel(val, c->reg); - c->rate = c->parent->rate; + + if (c->refcnt && c->parent) + clk_disable_locked(c->parent); + + clk_reparent(c, p); return 0; } } @@ -289,7 +323,61 @@ static struct clk_ops tegra_super_ops = { .enable = tegra2_super_clk_enable, .disable = tegra2_super_clk_disable, .set_parent = tegra2_super_clk_set_parent, - .recalculate_rate = tegra2_clk_recalculate_rate, +}; + +/* virtual cpu clock functions */ +/* some clocks can not be stopped (cpu, memory bus) while the SoC is running. + To change the frequency of these clocks, the parent pll may need to be + reprogrammed, so the clock must be moved off the pll, the pll reprogrammed, + and then the clock moved back to the pll. To hide this sequence, a virtual + clock handles it. + */ +static void tegra2_cpu_clk_init(struct clk *c) +{ +} + +static int tegra2_cpu_clk_enable(struct clk *c) +{ + return 0; +} + +static void tegra2_cpu_clk_disable(struct clk *c) +{ + pr_debug("%s on clock %s\n", __func__, c->name); + + /* oops - don't disable the CPU clock! */ + BUG(); +} + +static int tegra2_cpu_clk_set_rate(struct clk *c, unsigned long rate) +{ + int ret; + ret = clk_set_parent_locked(c->parent, c->backup); + if (ret) { + pr_err("Failed to switch cpu to clock %s\n", c->backup->name); + return ret; + } + + ret = clk_set_rate_locked(c->main, rate); + if (ret) { + pr_err("Failed to change cpu pll to %lu\n", rate); + return ret; + } + + ret = clk_set_parent_locked(c->parent, c->main); + if (ret) { + pr_err("Failed to switch cpu to clock %s\n", c->main->name); + return ret; + } + + return 0; +} + +static struct clk_ops tegra_cpu_ops = { + .init = tegra2_cpu_clk_init, + .enable = tegra2_cpu_clk_enable, + .disable = tegra2_cpu_clk_disable, + .set_rate = tegra2_cpu_clk_set_rate, }; /* bus clock functions */ @@ -299,7 +387,6 @@ static void tegra2_bus_clk_init(struct clk *c) c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON; c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1; c->mul = 1; - tegra2_clk_recalculate_rate(c); } static int tegra2_bus_clk_enable(struct clk *c) @@ -340,27 +427,15 @@ static struct clk_ops tegra_bus_ops = { .enable = tegra2_bus_clk_enable, .disable = tegra2_bus_clk_disable, .set_rate = tegra2_bus_clk_set_rate, - .recalculate_rate = tegra2_clk_recalculate_rate, }; /* PLL Functions */ -static unsigned long tegra2_pll_clk_recalculate_rate(struct clk *c) -{ - u64 rate; - rate = c->parent->rate; - rate *= c->n; - do_div(rate, c->m); - if (c->p == 2) - rate >>= 1; - c->rate = rate; - return c->rate; -} - static int tegra2_pll_clk_wait_for_lock(struct clk *c) { ktime_t before; before = ktime_get(); + while (!(clk_readl(c->reg + PLL_BASE) & PLL_BASE_LOCK)) { if (ktime_us_delta(ktime_get(), before) > 5000) { pr_err("Timed out waiting for lock bit on pll %s", @@ -380,24 +455,19 @@ static void tegra2_pll_clk_init(struct clk *c) if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) { pr_warning("Clock %s has unknown fixed frequency\n", c->name); - c->n = 1; - c->m = 0; - c->p = 1; + c->mul = 1; + c->div = 1; } else if (val & PLL_BASE_BYPASS) { - c->n = 1; - c->m = 1; - c->p = 1; + c->mul = 1; + c->div = 1; } else { - c->n = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT; - c->m = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT; - c->p = (val & PLL_BASE_DIVP_MASK) ? 2 : 1; + c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT; + c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT; + if (c->flags & PLLU) + c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2; + else + c->div *= (val & PLL_BASE_DIVP_MASK) ? 2 : 1; } - - val = clk_readl(c->reg + PLL_MISC(c)); - if (c->flags & PLL_HAS_CPCON) - c->cpcon = (val & PLL_MISC_CPCON_MASK) >> PLL_MISC_CPCON_SHIFT; - - tegra2_pll_clk_recalculate_rate(c); } static int tegra2_pll_clk_enable(struct clk *c) @@ -411,7 +481,7 @@ static int tegra2_pll_clk_enable(struct clk *c) clk_writel(val, c->reg + PLL_BASE); val = clk_readl(c->reg + PLL_MISC(c)); - val |= PLL_MISC_LOCK_ENABLE; + val |= PLL_MISC_LOCK_ENABLE(c); clk_writel(val, c->reg + PLL_MISC(c)); tegra2_pll_clk_wait_for_lock(c); @@ -441,33 +511,36 @@ static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate) input_rate = c->parent->rate; for (sel = c->pll_table; sel->input_rate != 0; sel++) { if (sel->input_rate == input_rate && sel->output_rate == rate) { - c->n = sel->n; - c->m = sel->m; - c->p = sel->p; - c->cpcon = sel->cpcon; + c->mul = sel->n; + c->div = sel->m * sel->p; val = clk_readl(c->reg + PLL_BASE); if (c->flags & PLL_FIXED) val |= PLL_BASE_OVERRIDE; val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK | PLL_BASE_DIVM_MASK); - val |= (c->m << PLL_BASE_DIVM_SHIFT) | - (c->n << PLL_BASE_DIVN_SHIFT); - BUG_ON(c->p > 2); - if (c->p == 2) - val |= 1 << PLL_BASE_DIVP_SHIFT; + val |= (sel->m << PLL_BASE_DIVM_SHIFT) | + (sel->n << PLL_BASE_DIVN_SHIFT); + BUG_ON(sel->p < 1 || sel->p > 2); + if (c->flags & PLLU) { + if (sel->p == 1) + val |= PLLU_BASE_POST_DIV; + } else { + if (sel->p == 2) + val |= 1 << PLL_BASE_DIVP_SHIFT; + } clk_writel(val, c->reg + PLL_BASE); if (c->flags & PLL_HAS_CPCON) { - val = c->cpcon << PLL_MISC_CPCON_SHIFT; - val |= PLL_MISC_LOCK_ENABLE; + val = clk_readl(c->reg + PLL_MISC(c)); + val &= ~PLL_MISC_CPCON_MASK; + val |= sel->cpcon << PLL_MISC_CPCON_SHIFT; clk_writel(val, c->reg + PLL_MISC(c)); } if (c->state == ON) tegra2_pll_clk_enable(c); - c->rate = rate; return 0; } } @@ -479,7 +552,46 @@ static struct clk_ops tegra_pll_ops = { .enable = tegra2_pll_clk_enable, .disable = tegra2_pll_clk_disable, .set_rate = tegra2_pll_clk_set_rate, - .recalculate_rate = tegra2_pll_clk_recalculate_rate, +}; + +static void tegra2_pllx_clk_init(struct clk *c) +{ + tegra2_pll_clk_init(c); + + if (tegra_sku_id() == 7) + c->max_rate = 750000000; +} + +static struct clk_ops tegra_pllx_ops = { + .init = tegra2_pllx_clk_init, + .enable = tegra2_pll_clk_enable, + .disable = tegra2_pll_clk_disable, + .set_rate = tegra2_pll_clk_set_rate, +}; + +static int tegra2_plle_clk_enable(struct clk *c) +{ + u32 val; + + pr_debug("%s on clock %s\n", __func__, c->name); + + mdelay(1); + + val = clk_readl(c->reg + PLL_BASE); + if (!(val & PLLE_MISC_READY)) + return -EBUSY; + + val = clk_readl(c->reg + PLL_BASE); + val |= PLL_BASE_ENABLE | PLL_BASE_BYPASS; + clk_writel(val, c->reg + PLL_BASE); + + return 0; +} + +static struct clk_ops tegra_plle_ops = { + .init = tegra2_pll_clk_init, + .enable = tegra2_plle_clk_enable, + .set_rate = tegra2_pll_clk_set_rate, }; /* Clock divider ops */ @@ -503,8 +615,6 @@ static void tegra2_pll_div_clk_init(struct clk *c) c->div = 1; c->mul = 1; } - - tegra2_clk_recalculate_rate(c); } static int tegra2_pll_div_clk_enable(struct clk *c) @@ -565,7 +675,7 @@ static int tegra2_pll_div_clk_set_rate(struct clk *c, unsigned long rate) int divider_u71; pr_debug("%s: %s %lu\n", __func__, c->name, rate); if (c->flags & DIV_U71) { - divider_u71 = clk_div71_get_divider(c->parent, rate); + divider_u71 = clk_div71_get_divider(c->parent->rate, rate); if (divider_u71 >= 0) { val = clk_readl(c->reg); new_val = val >> c->reg_shift; @@ -580,25 +690,37 @@ static int tegra2_pll_div_clk_set_rate(struct clk *c, unsigned long rate) clk_writel(val, c->reg); c->div = divider_u71 + 2; c->mul = 2; - tegra2_clk_recalculate_rate(c); return 0; } } else if (c->flags & DIV_2) { - if (c->parent->rate == rate * 2) { - c->rate = rate; + if (c->parent->rate == rate * 2) return 0; - } } return -EINVAL; } +static long tegra2_pll_div_clk_round_rate(struct clk *c, unsigned long rate) +{ + int divider; + pr_debug("%s: %s %lu\n", __func__, c->name, rate); + + if (c->flags & DIV_U71) { + divider = clk_div71_get_divider(c->parent->rate, rate); + if (divider < 0) + return divider; + return c->parent->rate * 2 / (divider + 2); + } else if (c->flags & DIV_2) { + return c->parent->rate / 2; + } + return -EINVAL; +} static struct clk_ops tegra_pll_div_ops = { .init = tegra2_pll_div_clk_init, .enable = tegra2_pll_div_clk_enable, .disable = tegra2_pll_div_clk_disable, .set_rate = tegra2_pll_div_clk_set_rate, - .recalculate_rate = tegra2_clk_recalculate_rate, + .round_rate = tegra2_pll_div_clk_round_rate, }; /* Periph clk ops */ @@ -621,9 +743,13 @@ static void tegra2_periph_clk_init(struct clk *c) } if (c->flags & DIV_U71) { - u32 divu71 = val & PERIPH_CLK_SOURCE_DIV_MASK; + u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK; c->div = divu71 + 2; c->mul = 2; + } else if (c->flags & DIV_U16) { + u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK; + c->div = divu16 + 1; + c->mul = 1; } else { c->div = 1; c->mul = 1; @@ -637,7 +763,6 @@ static void tegra2_periph_clk_init(struct clk *c) if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_ENB_BIT(c)) c->state = OFF; - tegra2_clk_recalculate_rate(c); } static int tegra2_periph_clk_enable(struct clk *c) @@ -692,12 +817,19 @@ static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p) pr_debug("%s: %s %s\n", __func__, c->name, p->name); for (sel = c->inputs; sel->input != NULL; sel++) { if (sel->input == p) { - clk_reparent(c, p); val = clk_readl(c->reg); val &= ~PERIPH_CLK_SOURCE_MASK; val |= (sel->value) << PERIPH_CLK_SOURCE_SHIFT; + + if (c->refcnt) + clk_enable_locked(p); + clk_writel(val, c->reg); - c->rate = c->parent->rate; + + if (c->refcnt && c->parent) + clk_disable_locked(c->parent); + + clk_reparent(c, p); return 0; } } @@ -708,20 +840,55 @@ static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p) static int tegra2_periph_clk_set_rate(struct clk *c, unsigned long rate) { u32 val; - int divider_u71; + int divider; pr_debug("%s: %lu\n", __func__, rate); if (c->flags & DIV_U71) { - divider_u71 = clk_div71_get_divider(c->parent, rate); - if (divider_u71 >= 0) { + divider = clk_div71_get_divider(c->parent->rate, rate); + if (divider >= 0) { val = clk_readl(c->reg); - val &= ~PERIPH_CLK_SOURCE_DIV_MASK; - val |= divider_u71; + val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK; + val |= divider; clk_writel(val, c->reg); - c->div = divider_u71 + 2; + c->div = divider + 2; c->mul = 2; - tegra2_clk_recalculate_rate(c); return 0; } + } else if (c->flags & DIV_U16) { + divider = clk_div16_get_divider(c->parent->rate, rate); + if (divider >= 0) { + val = clk_readl(c->reg); + val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK; + val |= divider; + clk_writel(val, c->reg); + c->div = divider + 1; + c->mul = 1; + return 0; + } + } else if (c->parent->rate <= rate) { + c->div = 1; + c->mul = 1; + return 0; + } + return -EINVAL; +} + +static long tegra2_periph_clk_round_rate(struct clk *c, + unsigned long rate) +{ + int divider; + pr_debug("%s: %s %lu\n", __func__, c->name, rate); + + if (c->flags & DIV_U71) { + divider = clk_div71_get_divider(c->parent->rate, rate); + if (divider < 0) + return divider; + + return c->parent->rate * 2 / (divider + 2); + } else if (c->flags & DIV_U16) { + divider = clk_div16_get_divider(c->parent->rate, rate); + if (divider < 0) + return divider; + return c->parent->rate / (divider + 1); } return -EINVAL; } @@ -732,7 +899,7 @@ static struct clk_ops tegra_periph_clk_ops = { .disable = &tegra2_periph_clk_disable, .set_parent = &tegra2_periph_clk_set_parent, .set_rate = &tegra2_periph_clk_set_rate, - .recalculate_rate = &tegra2_clk_recalculate_rate, + .round_rate = &tegra2_periph_clk_round_rate, }; /* Clock doubler ops */ @@ -744,21 +911,108 @@ static void tegra2_clk_double_init(struct clk *c) if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_ENB_BIT(c))) c->state = OFF; - tegra2_clk_recalculate_rate(c); }; +static int tegra2_clk_double_set_rate(struct clk *c, unsigned long rate) +{ + if (rate != 2 * c->parent->rate) + return -EINVAL; + c->mul = 2; + c->div = 1; + return 0; +} + static struct clk_ops tegra_clk_double_ops = { .init = &tegra2_clk_double_init, .enable = &tegra2_periph_clk_enable, .disable = &tegra2_periph_clk_disable, - .recalculate_rate = &tegra2_clk_recalculate_rate, + .set_rate = &tegra2_clk_double_set_rate, +}; + +static void tegra2_audio_sync_clk_init(struct clk *c) +{ + int source; + const struct clk_mux_sel *sel; + u32 val = clk_readl(c->reg); + c->state = (val & (1<<4)) ? OFF : ON; + source = val & 0xf; + for (sel = c->inputs; sel->input != NULL; sel++) + if (sel->value == source) + break; + BUG_ON(sel->input == NULL); + c->parent = sel->input; +} + +static int tegra2_audio_sync_clk_enable(struct clk *c) +{ + clk_writel(0, c->reg); + return 0; +} + +static void tegra2_audio_sync_clk_disable(struct clk *c) +{ + clk_writel(1, c->reg); +} + +static int tegra2_audio_sync_clk_set_parent(struct clk *c, struct clk *p) +{ + u32 val; + const struct clk_mux_sel *sel; + for (sel = c->inputs; sel->input != NULL; sel++) { + if (sel->input == p) { + val = clk_readl(c->reg); + val &= ~0xf; + val |= sel->value; + + if (c->refcnt) + clk_enable_locked(p); + + clk_writel(val, c->reg); + + if (c->refcnt && c->parent) + clk_disable_locked(c->parent); + + clk_reparent(c, p); + return 0; + } + } + + return -EINVAL; +} + +static int tegra2_audio_sync_clk_set_rate(struct clk *c, unsigned long rate) +{ + unsigned long parent_rate; + if (!c->parent) { + pr_err("%s: clock has no parent\n", __func__); + return -EINVAL; + } + parent_rate = c->parent->rate; + if (rate != parent_rate) { + pr_err("%s: %s/%ld differs from parent %s/%ld\n", + __func__, + c->name, rate, + c->parent->name, parent_rate); + return -EINVAL; + } + c->rate = parent_rate; + return 0; +} + +static struct clk_ops tegra_audio_sync_clk_ops = { + .init = tegra2_audio_sync_clk_init, + .enable = tegra2_audio_sync_clk_enable, + .disable = tegra2_audio_sync_clk_disable, + .set_rate = tegra2_audio_sync_clk_set_rate, + .set_parent = tegra2_audio_sync_clk_set_parent, }; /* Clock definitions */ static struct clk tegra_clk_32k = { .name = "clk_32k", - .rate = 32678, + .rate = 32768, .ops = NULL, + .max_rate = 32768, }; static struct clk_pll_table tegra_pll_s_table[] = { @@ -782,6 +1036,7 @@ static struct clk tegra_pll_s = { .vco_min = 12000000, .vco_max = 26000000, .pll_table = tegra_pll_s_table, + .max_rate = 26000000, }; static struct clk_mux_sel tegra_clk_m_sel[] = { @@ -797,6 +1052,7 @@ static struct clk tegra_clk_m = { .reg = 0x1fc, .reg_mask = (1<<28), .reg_shift = 28, + .max_rate = 26000000, }; static struct clk_pll_table tegra_pll_c_table[] = { @@ -816,6 +1072,7 @@ static struct clk tegra_pll_c = { .vco_min = 20000000, .vco_max = 1400000000, .pll_table = tegra_pll_c_table, + .max_rate = 600000000, }; static struct clk tegra_pll_c_out1 = { @@ -825,9 +1082,18 @@ static struct clk tegra_pll_c_out1 = { .parent = &tegra_pll_c, .reg = 0x84, .reg_shift = 0, + .max_rate = 600000000, }; static struct clk_pll_table tegra_pll_m_table[] = { + { 12000000, 666000000, 666, 12, 1, 8}, + { 13000000, 666000000, 666, 13, 1, 8}, + { 19200000, 666000000, 555, 16, 1, 8}, + { 26000000, 666000000, 666, 26, 1, 8}, + { 12000000, 600000000, 600, 12, 1, 8}, + { 13000000, 600000000, 600, 13, 1, 8}, + { 19200000, 600000000, 375, 12, 1, 6}, + { 26000000, 600000000, 600, 26, 1, 8}, { 0, 0, 0, 0, 0, 0 }, }; @@ -844,6 +1110,7 @@ static struct clk tegra_pll_m = { .vco_min = 20000000, .vco_max = 1200000000, .pll_table = tegra_pll_m_table, + .max_rate = 800000000, }; static struct clk tegra_pll_m_out1 = { @@ -853,6 +1120,7 @@ static struct clk tegra_pll_m_out1 = { .parent = &tegra_pll_m, .reg = 0x94, .reg_shift = 0, + .max_rate = 600000000, }; static struct clk_pll_table tegra_pll_p_table[] = { @@ -880,6 +1148,7 @@ static struct clk tegra_pll_p = { .vco_min = 20000000, .vco_max = 1400000000, .pll_table = tegra_pll_p_table, + .max_rate = 432000000, }; static struct clk tegra_pll_p_out1 = { @@ -889,6 +1158,7 @@ static struct clk tegra_pll_p_out1 = { .parent = &tegra_pll_p, .reg = 0xa4, .reg_shift = 0, + .max_rate = 432000000, }; static struct clk tegra_pll_p_out2 = { @@ -898,6 +1168,7 @@ static struct clk tegra_pll_p_out2 = { .parent = &tegra_pll_p, .reg = 0xa4, .reg_shift = 16, + .max_rate = 432000000, }; static struct clk tegra_pll_p_out3 = { @@ -907,6 +1178,7 @@ static struct clk tegra_pll_p_out3 = { .parent = &tegra_pll_p, .reg = 0xa8, .reg_shift = 0, + .max_rate = 432000000, }; static struct clk tegra_pll_p_out4 = { @@ -916,6 +1188,7 @@ static struct clk tegra_pll_p_out4 = { .parent = &tegra_pll_p, .reg = 0xa8, .reg_shift = 16, + .max_rate = 432000000, }; static struct clk_pll_table tegra_pll_a_table[] = { @@ -923,6 +1196,7 @@ static struct clk_pll_table tegra_pll_a_table[] = { { 28800000, 73728000, 64, 25, 1, 1}, { 28800000, 11289600, 49, 25, 1, 1}, { 28800000, 12288000, 64, 25, 1, 1}, + { 28800000, 24000000, 5, 6, 1, 1}, { 0, 0, 0, 0, 0, 0 }, }; @@ -939,6 +1213,7 @@ static struct clk tegra_pll_a = { .vco_min = 20000000, .vco_max = 1400000000, .pll_table = tegra_pll_a_table, + .max_rate = 56448000, }; static struct clk tegra_pll_a_out0 = { @@ -948,6 +1223,7 @@ static struct clk tegra_pll_a_out0 = { .parent = &tegra_pll_a, .reg = 0xb4, .reg_shift = 0, + .max_rate = 56448000, }; static struct clk_pll_table tegra_pll_d_table[] = { @@ -971,6 +1247,7 @@ static struct clk tegra_pll_d = { .vco_min = 40000000, .vco_max = 1000000000, .pll_table = tegra_pll_d_table, + .max_rate = 1000000000, }; static struct clk tegra_pll_d_out0 = { @@ -978,19 +1255,20 @@ static struct clk tegra_pll_d_out0 = { .ops = &tegra_pll_div_ops, .flags = DIV_2 | PLLD, .parent = &tegra_pll_d, + .max_rate = 500000000, }; static struct clk_pll_table tegra_pll_u_table[] = { - { 12000000, 480000000, 960, 12, 1, 0}, - { 13000000, 480000000, 960, 13, 1, 0}, - { 19200000, 480000000, 200, 4, 1, 0}, - { 26000000, 480000000, 960, 26, 1, 0}, + { 12000000, 480000000, 960, 12, 2, 0}, + { 13000000, 480000000, 960, 13, 2, 0}, + { 19200000, 480000000, 200, 4, 2, 0}, + { 26000000, 480000000, 960, 26, 2, 0}, { 0, 0, 0, 0, 0, 0 }, }; static struct clk tegra_pll_u = { .name = "pll_u", - .flags = 0, + .flags = PLLU, .ops = &tegra_pll_ops, .reg = 0xc0, .input_min = 2000000, @@ -1001,24 +1279,59 @@ static struct clk tegra_pll_u = { .vco_min = 480000000, .vco_max = 960000000, .pll_table = tegra_pll_u_table, + .max_rate = 480000000, }; static struct clk_pll_table tegra_pll_x_table[] = { + /* 1 GHz */ { 12000000, 1000000000, 1000, 12, 1, 12}, { 13000000, 1000000000, 1000, 13, 1, 12}, { 19200000, 1000000000, 625, 12, 1, 8}, { 26000000, 1000000000, 1000, 26, 1, 12}, - { 12000000, 750000000, 750, 12, 1, 12}, - { 13000000, 750000000, 750, 13, 1, 12}, - { 19200000, 750000000, 625, 16, 1, 8}, - { 26000000, 750000000, 750, 26, 1, 12}, + + /* 912 MHz */ + { 12000000, 912000000, 912, 12, 1, 12}, + { 13000000, 912000000, 912, 13, 1, 12}, + { 19200000, 912000000, 760, 16, 1, 8}, + { 26000000, 912000000, 912, 26, 1, 12}, + + /* 816 MHz */ + { 12000000, 816000000, 816, 12, 1, 12}, + { 13000000, 816000000, 816, 13, 1, 12}, + { 19200000, 816000000, 680, 16, 1, 8}, + { 26000000, 816000000, 816, 26, 1, 12}, + + /* 760 MHz */ + { 12000000, 760000000, 760, 12, 1, 12}, + { 13000000, 760000000, 760, 13, 1, 12}, + { 19200000, 760000000, 950, 24, 1, 8}, + { 26000000, 760000000, 760, 26, 1, 12}, + + /* 608 MHz */ + { 12000000, 608000000, 760, 12, 1, 12}, + { 13000000, 608000000, 760, 13, 1, 12}, + { 19200000, 608000000, 380, 12, 1, 8}, + { 26000000, 608000000, 760, 26, 1, 12}, + + /* 456 MHz */ + { 12000000, 456000000, 456, 12, 1, 12}, + { 13000000, 456000000, 456, 13, 1, 12}, + { 19200000, 456000000, 380, 16, 1, 8}, + { 26000000, 456000000, 456, 26, 1, 12}, + + /* 312 MHz */ + { 12000000, 312000000, 312, 12, 1, 12}, + { 13000000, 312000000, 312, 13, 1, 12}, + { 19200000, 312000000, 260, 16, 1, 8}, + { 26000000, 312000000, 312, 26, 1, 12}, + { 0, 0, 0, 0, 0, 0 }, }; static struct clk tegra_pll_x = { .name = "pll_x", .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG, - .ops = &tegra_pll_ops, + .ops = &tegra_pllx_ops, .reg = 0xe0, .input_min = 2000000, .input_max = 31000000, @@ -1028,6 +1341,24 @@ static struct clk tegra_pll_x = { .vco_min = 20000000, .vco_max = 1200000000, .pll_table = tegra_pll_x_table, + .max_rate = 1000000000, +}; + +static struct clk_pll_table tegra_pll_e_table[] = { + { 12000000, 100000000, 200, 24, 1, 0 }, + { 0, 0, 0, 0, 0, 0 }, +}; + +static struct clk tegra_pll_e = { + .name = "pll_e", + .flags = PLL_ALT_MISC_REG, + .ops = &tegra_plle_ops, + .input_min = 12000000, + .input_max = 12000000, + .max_rate = 100000000, + .parent = &tegra_clk_m, + .reg = 0xe8, + .pll_table = tegra_pll_e_table, }; static struct clk tegra_clk_d = { @@ -1038,19 +1369,77 @@ static struct clk tegra_clk_d = { .reg = 0x34, .reg_shift = 12, .parent = &tegra_clk_m, + .max_rate = 52000000, +}; + +/* initialized before peripheral clocks */ +static struct clk_mux_sel mux_audio_sync_clk[8+1]; +static const struct audio_sources { + const char *name; + int value; +} mux_audio_sync_clk_sources[] = { + { .name = "spdif_in", .value = 0 }, + { .name = "i2s1", .value = 1 }, + { .name = "i2s2", .value = 2 }, + { .name = "pll_a_out0", .value = 4 }, +#if 0 /* FIXME: not implemented */ + { .name = "ac97", .value = 3 }, + { .name = "ext_audio_clk2", .value = 5 }, + { .name = "ext_audio_clk1", .value = 6 }, + { .name = "ext_vimclk", .value = 7 }, +#endif + { 0, 0 } +}; + +static struct clk tegra_clk_audio = { + .name = "audio", + .inputs = mux_audio_sync_clk, + .reg = 0x38, + .max_rate = 24000000, + .ops = &tegra_audio_sync_clk_ops }; -/* FIXME: need tegra_audio static struct clk tegra_clk_audio_2x = { - .name = "clk_d", + .name = "audio_2x", .flags = PERIPH_NO_RESET, + .max_rate = 48000000, .ops = &tegra_clk_double_ops, .clk_num = 89, .reg = 0x34, .reg_shift = 8, - .parent = &tegra_audio, + .parent = &tegra_clk_audio, +}; + +struct clk_lookup tegra_audio_clk_lookups[] = { + { .con_id = "audio", .clk = &tegra_clk_audio }, + { .con_id = "audio_2x", .clk = &tegra_clk_audio_2x } +}; + +/* This is called after peripheral clocks are initialized, as the + * audio_sync clock depends on some of the peripheral clocks. + */ + +static void init_audio_sync_clock_mux(void) +{ + int i; + struct clk_mux_sel *sel = mux_audio_sync_clk; + const struct audio_sources *src = mux_audio_sync_clk_sources; + struct clk_lookup *lookup; + + for (i = 0; src->name; i++, sel++, src++) { + sel->input = tegra_get_clock_by_name(src->name); + if (!sel->input) + pr_err("%s: could not find clk %s\n", __func__, + src->name); + sel->value = src->value; + } + + lookup = tegra_audio_clk_lookups; + for (i = 0; i < ARRAY_SIZE(tegra_audio_clk_lookups); i++, lookup++) { + clk_init(lookup->clk); + clkdev_add(lookup); + } } -*/ static struct clk_mux_sel mux_cclk[] = { { .input = &tegra_clk_m, .value = 0}, @@ -1077,27 +1466,40 @@ static struct clk_mux_sel mux_sclk[] = { { 0, 0}, }; -static struct clk tegra_clk_cpu = { - .name = "cpu", +static struct clk tegra_clk_cclk = { + .name = "cclk", .inputs = mux_cclk, .reg = 0x20, .ops = &tegra_super_ops, + .max_rate = 1000000000, }; -static struct clk tegra_clk_sys = { - .name = "sys", +static struct clk tegra_clk_sclk = { + .name = "sclk", .inputs = mux_sclk, .reg = 0x28, .ops = &tegra_super_ops, + .max_rate = 600000000, +}; + +static struct clk tegra_clk_virtual_cpu = { + .name = "cpu", + .parent = &tegra_clk_cclk, + .main = &tegra_pll_x, + .backup = &tegra_clk_m, + .ops = &tegra_cpu_ops, + .max_rate = 1000000000, + .dvfs = &tegra_dvfs_virtual_cpu_dvfs, }; static struct clk tegra_clk_hclk = { .name = "hclk", .flags = DIV_BUS, - .parent = &tegra_clk_sys, + .parent = &tegra_clk_sclk, .reg = 0x30, .reg_shift = 4, .ops = &tegra_bus_ops, + .max_rate = 240000000, }; static struct clk tegra_clk_pclk = { @@ -1107,6 +1509,7 @@ static struct clk tegra_clk_pclk = { .reg = 0x30, .reg_shift = 0, .ops = &tegra_bus_ops, + .max_rate = 108000000, }; static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = { @@ -1133,10 +1536,9 @@ static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = { { 0, 0}, }; -static struct clk_mux_sel mux_plla_audio_pllp_clkm[] = { - {.input = &tegra_pll_a, .value = 0}, - /* FIXME: no mux defined for tegra_audio - {.input = &tegra_audio, .value = 1},*/ +static struct clk_mux_sel mux_pllaout0_audio2x_pllp_clkm[] = { + {.input = &tegra_pll_a_out0, .value = 0}, + {.input = &tegra_clk_audio_2x, .value = 1}, {.input = &tegra_pll_p, .value = 2}, {.input = &tegra_clk_m, .value = 3}, { 0, 0}, @@ -1153,8 +1555,7 @@ static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = { static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32[] = { {.input = &tegra_pll_p, .value = 0}, {.input = &tegra_pll_c, .value = 1}, - /* FIXME: no mux defined for tegra_audio - {.input = &tegra_audio, .value = 2},*/ + {.input = &tegra_clk_audio, .value = 2}, {.input = &tegra_clk_m, .value = 3}, {.input = &tegra_clk_32k, .value = 4}, { 0, 0}, @@ -1187,7 +1588,7 @@ static struct clk_mux_sel mux_clk_32k[] = { { 0, 0}, }; -#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _inputs, _flags) \ +#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \ { \ .name = _name, \ .lookup = { \ @@ -1199,72 +1600,79 @@ static struct clk_mux_sel mux_clk_32k[] = { .reg = _reg, \ .inputs = _inputs, \ .flags = _flags, \ + .max_rate = _max, \ } struct clk tegra_periph_clks[] = { - PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, mux_clk_32k, PERIPH_NO_RESET), - PERIPH_CLK("timer", "timer", NULL, 5, 0, mux_clk_m, 0), - PERIPH_CLK("i2s1", "i2s.0", NULL, 11, 0x100, mux_plla_audio_pllp_clkm, MUX | DIV_U71), - PERIPH_CLK("i2s2", "i2s.1", NULL, 18, 0x104, mux_plla_audio_pllp_clkm, MUX | DIV_U71), + PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET), + PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0), + PERIPH_CLK("i2s1", "i2s.0", NULL, 11, 0x100, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71), + PERIPH_CLK("i2s2", "i2s.1", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71), /* FIXME: spdif has 2 clocks but 1 enable */ - PERIPH_CLK("spdif_out", "spdif_out", NULL, 10, 0x108, mux_plla_audio_pllp_clkm, MUX | DIV_U71), - PERIPH_CLK("spdif_in", "spdif_in", NULL, 10, 0x10c, mux_pllp_pllc_pllm, MUX | DIV_U71), - PERIPH_CLK("pwm", "pwm", NULL, 17, 0x110, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71), - PERIPH_CLK("spi", "spi", NULL, 43, 0x114, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), - PERIPH_CLK("xio", "xio", NULL, 45, 0x120, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), - PERIPH_CLK("twc", "twc", NULL, 16, 0x12c, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), - PERIPH_CLK("sbc1", "spi_tegra.0", NULL, 41, 0x134, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), - PERIPH_CLK("sbc2", "spi_tegra.1", NULL, 44, 0x118, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), - PERIPH_CLK("sbc3", "spi_tegra.2", NULL, 46, 0x11c, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), - PERIPH_CLK("sbc4", "spi_tegra.3", NULL, 68, 0x1b4, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), - PERIPH_CLK("ide", "ide", NULL, 25, 0x144, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), - PERIPH_CLK("ndflash", "tegra_nand", NULL, 13, 0x160, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("spdif_out", "spdif_out", NULL, 10, 0x108, 100000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71), + PERIPH_CLK("spdif_in", "spdif_in", NULL, 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71), + PERIPH_CLK("pwm", "pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71), + PERIPH_CLK("spi", "spi", NULL, 43, 0x114, 40000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("xio", "xio", NULL, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("twc", "twc", NULL, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("sbc1", "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("sbc2", "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("sbc3", "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("sbc4", "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("ide", "ide", NULL, 25, 0x144, 100000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */ + PERIPH_CLK("ndflash", "tegra_nand", NULL, 13, 0x160, 164000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ /* FIXME: vfir shares an enable with uartb */ - PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), - PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), - PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), - PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), - PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x160, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), - PERIPH_CLK("vde", "vde", NULL, 61, 0x1c8, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), - PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ + PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ + PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ + PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x160, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ + PERIPH_CLK("vde", "vde", NULL, 61, 0x1c8, 250000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage and process_id */ + PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* max rate ??? */ /* FIXME: what is la? */ - PERIPH_CLK("la", "la", NULL, 76, 0x1f8, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), - PERIPH_CLK("owr", "owr", NULL, 71, 0x1cc, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), - PERIPH_CLK("nor", "nor", NULL, 42, 0x1d0, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), - PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), - PERIPH_CLK("i2c1", "tegra-i2c.0", NULL, 12, 0x124, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), - PERIPH_CLK("i2c2", "tegra-i2c.1", NULL, 54, 0x198, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), - PERIPH_CLK("i2c3", "tegra-i2c.2", NULL, 67, 0x1b8, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), - PERIPH_CLK("dvc", "tegra-i2c.3", NULL, 47, 0x128, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), - PERIPH_CLK("i2c1_i2c", "tegra-i2c.0", "i2c", 0, 0, mux_pllp_out3, 0), - PERIPH_CLK("i2c2_i2c", "tegra-i2c.1", "i2c", 0, 0, mux_pllp_out3, 0), - PERIPH_CLK("i2c3_i2c", "tegra-i2c.2", "i2c", 0, 0, mux_pllp_out3, 0), - PERIPH_CLK("dvc_i2c", "tegra-i2c.3", "i2c", 0, 0, mux_pllp_out3, 0), - PERIPH_CLK("uarta", "uart.0", NULL, 6, 0x178, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), - PERIPH_CLK("uartb", "uart.1", NULL, 7, 0x17c, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), - PERIPH_CLK("uartc", "uart.2", NULL, 55, 0x1a0, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), - PERIPH_CLK("uartd", "uart.3", NULL, 65, 0x1c0, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), - PERIPH_CLK("uarte", "uart.4", NULL, 66, 0x1c4, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), - PERIPH_CLK("3d", "3d", NULL, 24, 0x158, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET), - PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), + PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("nor", "nor", NULL, 42, 0x1d0, 92000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */ + PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ + PERIPH_CLK("i2c1", "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16), + PERIPH_CLK("i2c2", "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16), + PERIPH_CLK("i2c3", "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16), + PERIPH_CLK("dvc", "tegra-i2c.3", NULL, 47, 0x128, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16), + PERIPH_CLK("i2c1_i2c", "tegra-i2c.0", "i2c", 0, 0, 72000000, mux_pllp_out3, 0), + PERIPH_CLK("i2c2_i2c", "tegra-i2c.1", "i2c", 0, 0, 72000000, mux_pllp_out3, 0), + PERIPH_CLK("i2c3_i2c", "tegra-i2c.2", "i2c", 0, 0, 72000000, mux_pllp_out3, 0), + PERIPH_CLK("dvc_i2c", "tegra-i2c.3", "i2c", 0, 0, 72000000, mux_pllp_out3, 0), + PERIPH_CLK("uarta", "uart.0", NULL, 6, 0x178, 216000000, mux_pllp_pllc_pllm_clkm, MUX), + PERIPH_CLK("uartb", "uart.1", NULL, 7, 0x17c, 216000000, mux_pllp_pllc_pllm_clkm, MUX), + PERIPH_CLK("uartc", "uart.2", NULL, 55, 0x1a0, 216000000, mux_pllp_pllc_pllm_clkm, MUX), + PERIPH_CLK("uartd", "uart.3", NULL, 65, 0x1c0, 216000000, mux_pllp_pllc_pllm_clkm, MUX), + PERIPH_CLK("uarte", "uart.4", NULL, 66, 0x1c4, 216000000, mux_pllp_pllc_pllm_clkm, MUX), + PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */ + PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */ /* FIXME: vi and vi_sensor share an enable */ - PERIPH_CLK("vi", "vi", NULL, 20, 0x148, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), - PERIPH_CLK("vi_sensor", "vi_sensor", NULL, 20, 0x1a8, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), - PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), - PERIPH_CLK("mpe", "mpe", NULL, 60, 0x170, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), - PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), + PERIPH_CLK("vi", "vi", NULL, 20, 0x148, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */ + PERIPH_CLK("vi_sensor", "vi_sensor", NULL, 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET), /* scales with voltage and process_id */ + PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */ + PERIPH_CLK("mpe", "mpe", NULL, 60, 0x170, 250000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */ + PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 166000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */ /* FIXME: cve and tvo share an enable */ - PERIPH_CLK("cve", "cve", NULL, 49, 0x140, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), - PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), - PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), - PERIPH_CLK("tvdac", "tvdac", NULL, 53, 0x194, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), - PERIPH_CLK("disp1", "tegrafb.0", NULL, 27, 0x138, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), - PERIPH_CLK("disp2", "tegrafb.1", NULL, 26, 0x13c, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), - PERIPH_CLK("usbd", "fsl-tegra-udc", NULL, 22, 0, mux_clk_m, 0), - PERIPH_CLK("usb2", "usb.1", NULL, 58, 0, mux_clk_m, 0), - PERIPH_CLK("usb3", "usb.2", NULL, 59, 0, mux_clk_m, 0), - PERIPH_CLK("emc", "emc", NULL, 57, 0x19c, mux_pllm_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_EMC_ENB), - PERIPH_CLK("dsi", "dsi", NULL, 48, 0, mux_plld, 0), + PERIPH_CLK("cve", "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */ + PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */ + PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 148500000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */ + PERIPH_CLK("tvdac", "tvdac", NULL, 53, 0x194, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */ + PERIPH_CLK("disp1", "tegrafb.0", NULL, 27, 0x138, 190000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* scales with voltage and process_id */ + PERIPH_CLK("disp2", "tegrafb.1", NULL, 26, 0x13c, 190000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* scales with voltage and process_id */ + PERIPH_CLK("usbd", "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0), /* requires min voltage */ + PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0), /* requires min voltage */ + PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0), /* requires min voltage */ + PERIPH_CLK("emc", "emc", NULL, 57, 0x19c, 800000000, mux_pllm_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_EMC_ENB), + PERIPH_CLK("dsi", "dsi", NULL, 48, 0, 500000000, mux_plld, 0), /* scales with voltage */ + PERIPH_CLK("csi", "csi", NULL, 52, 0, 72000000, mux_pllp_out3, 0), + PERIPH_CLK("isp", "isp", NULL, 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */ + PERIPH_CLK("csus", "csus", NULL, 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET), + PERIPH_CLK("pex", NULL, "pex", 70, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET), + PERIPH_CLK("afi", NULL, "afi", 72, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET), + PERIPH_CLK("pcie_xclk", NULL, "pcie_xclk", 74, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET), }; #define CLK_DUPLICATE(_name, _dev, _con) \ @@ -1286,6 +1694,9 @@ struct clk_duplicate tegra_clk_duplicates[] = { CLK_DUPLICATE("uartc", "tegra_uart.2", NULL), CLK_DUPLICATE("uartd", "tegra_uart.3", NULL), CLK_DUPLICATE("uarte", "tegra_uart.4", NULL), + CLK_DUPLICATE("host1x", "tegrafb.0", "host1x"), + CLK_DUPLICATE("host1x", "tegrafb.1", "host1x"), + CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL), }; #define CLK(dev, con, ck) \ @@ -1315,11 +1726,13 @@ struct clk_lookup tegra_clk_lookups[] = { CLK(NULL, "pll_d_out0", &tegra_pll_d_out0), CLK(NULL, "pll_u", &tegra_pll_u), CLK(NULL, "pll_x", &tegra_pll_x), - CLK(NULL, "cpu", &tegra_clk_cpu), - CLK(NULL, "sys", &tegra_clk_sys), + CLK(NULL, "pll_e", &tegra_pll_e), + CLK(NULL, "cclk", &tegra_clk_cclk), + CLK(NULL, "sclk", &tegra_clk_sclk), CLK(NULL, "hclk", &tegra_clk_hclk), CLK(NULL, "pclk", &tegra_clk_pclk), CLK(NULL, "clk_d", &tegra_clk_d), + CLK(NULL, "cpu", &tegra_clk_virtual_cpu), }; void __init tegra2_init_clocks(void) @@ -1356,4 +1769,75 @@ void __init tegra2_init_clocks(void) cd->name); } } + + init_audio_sync_clock_mux(); +} + +#ifdef CONFIG_PM +static u32 clk_rst_suspend[RST_DEVICES_NUM + CLK_OUT_ENB_NUM + + PERIPH_CLK_SOURCE_NUM + 3]; + +void tegra_clk_suspend(void) +{ + unsigned long off, i; + u32 *ctx = clk_rst_suspend; + + *ctx++ = clk_readl(OSC_CTRL) & OSC_CTRL_MASK; + + for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC; + off += 4) { + if (off == PERIPH_CLK_SOURCE_EMC) + continue; + *ctx++ = clk_readl(off); + } + + off = RST_DEVICES; + for (i = 0; i < RST_DEVICES_NUM; i++, off += 4) + *ctx++ = clk_readl(off); + + off = CLK_OUT_ENB; + for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4) + *ctx++ = clk_readl(off); + + *ctx++ = clk_readl(MISC_CLK_ENB); + *ctx++ = clk_readl(CLK_MASK_ARM); +} + +void tegra_clk_resume(void) +{ + unsigned long off, i; + const u32 *ctx = clk_rst_suspend; + u32 val; + + val = clk_readl(OSC_CTRL) & ~OSC_CTRL_MASK; + val |= *ctx++; + clk_writel(val, OSC_CTRL); + + /* enable all clocks before configuring clock sources */ + clk_writel(0xbffffff9ul, CLK_OUT_ENB); + clk_writel(0xfefffff7ul, CLK_OUT_ENB + 4); + clk_writel(0x77f01bfful, CLK_OUT_ENB + 8); + wmb(); + + for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC; + off += 4) { + if (off == PERIPH_CLK_SOURCE_EMC) + continue; + clk_writel(*ctx++, off); + } + wmb(); + + off = RST_DEVICES; + for (i = 0; i < RST_DEVICES_NUM; i++, off += 4) + clk_writel(*ctx++, off); + wmb(); + + off = CLK_OUT_ENB; + for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4) + clk_writel(*ctx++, off); + wmb(); + + clk_writel(*ctx++, MISC_CLK_ENB); + clk_writel(*ctx++, CLK_MASK_ARM); } +#endif diff --git a/arch/arm/mach-tegra/tegra2_dvfs.c b/arch/arm/mach-tegra/tegra2_dvfs.c new file mode 100644 index 000000000000..5529c238dd77 --- /dev/null +++ b/arch/arm/mach-tegra/tegra2_dvfs.c @@ -0,0 +1,86 @@ +/* + * arch/arm/mach-tegra/tegra2_dvfs.c + * + * Copyright (C) 2010 Google, Inc. + * + * Author: + * Colin Cross <ccross@google.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/kernel.h> + +#include "clock.h" +#include "tegra2_dvfs.h" + +static struct dvfs_table virtual_cpu_process_0[] = { + {314000000, 750}, + {456000000, 825}, + {608000000, 900}, + {760000000, 975}, + {817000000, 1000}, + {912000000, 1050}, + {1000000000, 1100}, + {0, 0}, +}; + +static struct dvfs_table virtual_cpu_process_1[] = { + {314000000, 750}, + {456000000, 825}, + {618000000, 900}, + {770000000, 975}, + {827000000, 1000}, + {922000000, 1050}, + {1000000000, 1100}, + {0, 0}, +}; + +static struct dvfs_table virtual_cpu_process_2[] = { + {494000000, 750}, + {675000000, 825}, + {817000000, 875}, + {922000000, 925}, + {1000000000, 975}, + {0, 0}, +}; + +static struct dvfs_table virtual_cpu_process_3[] = { + {730000000, 750}, + {760000000, 775}, + {845000000, 800}, + {1000000000, 875}, + {0, 0}, +}; + +struct dvfs tegra_dvfs_virtual_cpu_dvfs = { + .reg_id = "vdd_cpu", + .process_id_table = { + { + .process_id = 0, + .table = virtual_cpu_process_0, + }, + { + .process_id = 1, + .table = virtual_cpu_process_1, + }, + { + .process_id = 2, + .table = virtual_cpu_process_2, + }, + { + .process_id = 3, + .table = virtual_cpu_process_3, + }, + }, + .process_id_table_length = 4, + .cpu = 1, +}; diff --git a/arch/arm/mach-tegra/tegra2_dvfs.h b/arch/arm/mach-tegra/tegra2_dvfs.h new file mode 100644 index 000000000000..f8c1adba96a6 --- /dev/null +++ b/arch/arm/mach-tegra/tegra2_dvfs.h @@ -0,0 +1,20 @@ +/* + * arch/arm/mach-tegra/tegra2_dvfs.h + * + * Copyright (C) 2010 Google, Inc. + * + * Author: + * Colin Cross <ccross@google.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +extern struct dvfs tegra_dvfs_virtual_cpu_dvfs; diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c index 2f420210d406..9057d6fd1d31 100644 --- a/arch/arm/mach-tegra/timer.c +++ b/arch/arm/mach-tegra/timer.c @@ -28,7 +28,6 @@ #include <linux/cnt32_to_63.h> #include <asm/mach/time.h> -#include <asm/mach/time.h> #include <asm/localtimer.h> #include <mach/iomap.h> diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index fcb587f825cc..cac83a694880 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -18,12 +18,14 @@ #include <linux/amba/pl022.h> #include <linux/spi/spi.h> #include <linux/mfd/ab8500.h> +#include <linux/input/matrix_keypad.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <plat/pincfg.h> #include <plat/i2c.h> +#include <plat/ske.h> #include <mach/hardware.h> #include <mach/setup.h> @@ -49,6 +51,24 @@ static pin_cfg_t mop500_pins[] = { GPIO11_I2C2_SCL, GPIO229_I2C3_SDA, GPIO230_I2C3_SCL, + + /* SKE keypad */ + GPIO153_KP_I7, + GPIO154_KP_I6, + GPIO155_KP_I5, + GPIO156_KP_I4, + GPIO157_KP_O7, + GPIO158_KP_O6, + GPIO159_KP_O5, + GPIO160_KP_O4, + GPIO161_KP_I3, + GPIO162_KP_I2, + GPIO163_KP_I1, + GPIO164_KP_I0, + GPIO165_KP_O3, + GPIO166_KP_O2, + GPIO167_KP_O1, + GPIO168_KP_O0, }; static void ab4500_spi_cs_control(u32 command) @@ -148,12 +168,120 @@ static struct amba_device *amba_devs[] __initdata = { &u8500_ssp0_device, }; +static const unsigned int ux500_keymap[] = { + KEY(2, 5, KEY_END), + KEY(4, 1, KEY_POWER), + KEY(3, 5, KEY_VOLUMEDOWN), + KEY(1, 3, KEY_3), + KEY(5, 2, KEY_RIGHT), + KEY(5, 0, KEY_9), + + KEY(0, 5, KEY_MENU), + KEY(7, 6, KEY_ENTER), + KEY(4, 5, KEY_0), + KEY(6, 7, KEY_2), + KEY(3, 4, KEY_UP), + KEY(3, 3, KEY_DOWN), + + KEY(6, 4, KEY_SEND), + KEY(6, 2, KEY_BACK), + KEY(4, 2, KEY_VOLUMEUP), + KEY(5, 5, KEY_1), + KEY(4, 3, KEY_LEFT), + KEY(3, 2, KEY_7), +}; + +static const struct matrix_keymap_data ux500_keymap_data = { + .keymap = ux500_keymap, + .keymap_size = ARRAY_SIZE(ux500_keymap), +}; + +/* + * Nomadik SKE keypad + */ +#define ROW_PIN_I0 164 +#define ROW_PIN_I1 163 +#define ROW_PIN_I2 162 +#define ROW_PIN_I3 161 +#define ROW_PIN_I4 156 +#define ROW_PIN_I5 155 +#define ROW_PIN_I6 154 +#define ROW_PIN_I7 153 +#define COL_PIN_O0 168 +#define COL_PIN_O1 167 +#define COL_PIN_O2 166 +#define COL_PIN_O3 165 +#define COL_PIN_O4 160 +#define COL_PIN_O5 159 +#define COL_PIN_O6 158 +#define COL_PIN_O7 157 + +#define SKE_KPD_MAX_ROWS 8 +#define SKE_KPD_MAX_COLS 8 + +static int ske_kp_rows[] = { + ROW_PIN_I0, ROW_PIN_I1, ROW_PIN_I2, ROW_PIN_I3, + ROW_PIN_I4, ROW_PIN_I5, ROW_PIN_I6, ROW_PIN_I7, +}; + +/* + * ske_set_gpio_row: request and set gpio rows + */ +static int ske_set_gpio_row(int gpio) +{ + int ret; + + ret = gpio_request(gpio, "ske-kp"); + if (ret < 0) { + pr_err("ske_set_gpio_row: gpio request failed\n"); + return ret; + } + + ret = gpio_direction_output(gpio, 1); + if (ret < 0) { + pr_err("ske_set_gpio_row: gpio direction failed\n"); + gpio_free(gpio); + } + + return ret; +} + +/* + * ske_kp_init - enable the gpio configuration + */ +static int ske_kp_init(void) +{ + int ret, i; + + for (i = 0; i < SKE_KPD_MAX_ROWS; i++) { + ret = ske_set_gpio_row(ske_kp_rows[i]); + if (ret < 0) { + pr_err("ske_kp_init: failed init\n"); + return ret; + } + } + + return 0; +} + +static struct ske_keypad_platform_data ske_keypad_board = { + .init = ske_kp_init, + .keymap_data = &ux500_keymap_data, + .no_autorepeat = true, + .krow = SKE_KPD_MAX_ROWS, /* 8x8 matrix */ + .kcol = SKE_KPD_MAX_COLS, + .debounce_ms = 40, /* in millsecs */ +}; + + + /* add any platform devices here - TODO */ static struct platform_device *platform_devs[] __initdata = { &u8500_i2c0_device, &ux500_i2c1_device, &ux500_i2c2_device, &ux500_i2c3_device, + &ux500_ske_keypad_device, }; static void __init u8500_init_machine(void) @@ -168,6 +296,7 @@ static void __init u8500_init_machine(void) ux500_i2c1_device.dev.platform_data = &u8500_i2c1_data; ux500_i2c2_device.dev.platform_data = &u8500_i2c2_data; ux500_i2c3_device.dev.platform_data = &u8500_i2c3_data; + ux500_ske_keypad_device.dev.platform_data = &ske_keypad_board; u8500_ssp0_device.dev.platform_data = &ssp0_platform_data; diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c index d8ab7f184fe4..1675047daf20 100644 --- a/arch/arm/mach-ux500/clock.c +++ b/arch/arm/mach-ux500/clock.c @@ -477,6 +477,7 @@ static struct clk_lookup u8500_common_clks[] = { CLK(sdi5, "sdi5", NULL), CLK(uart2, "uart2", NULL), CLK(ske, "ske", NULL), + CLK(ske, "nmk-ske-keypad", NULL), CLK(sdi2, "sdi2", NULL), CLK(i2c0, "nmk-i2c.0", NULL), CLK(fsmc, "fsmc", NULL), diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c index 40032fecbc16..4a94be3304b9 100644 --- a/arch/arm/mach-ux500/devices-db8500.c +++ b/arch/arm/mach-ux500/devices-db8500.c @@ -208,35 +208,25 @@ static struct resource dma40_resources[] = { /* Default configuration for physcial memcpy */ struct stedma40_chan_cfg dma40_memcpy_conf_phy = { - .channel_type = (STEDMA40_CHANNEL_IN_PHY_MODE | - STEDMA40_LOW_PRIORITY_CHANNEL | - STEDMA40_PCHAN_BASIC_MODE), + .mode = STEDMA40_MODE_PHYSICAL, .dir = STEDMA40_MEM_TO_MEM, - .src_info.endianess = STEDMA40_LITTLE_ENDIAN, .src_info.data_width = STEDMA40_BYTE_WIDTH, .src_info.psize = STEDMA40_PSIZE_PHY_1, .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, - .dst_info.endianess = STEDMA40_LITTLE_ENDIAN, .dst_info.data_width = STEDMA40_BYTE_WIDTH, .dst_info.psize = STEDMA40_PSIZE_PHY_1, .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, }; /* Default configuration for logical memcpy */ struct stedma40_chan_cfg dma40_memcpy_conf_log = { - .channel_type = (STEDMA40_CHANNEL_IN_LOG_MODE | - STEDMA40_LOW_PRIORITY_CHANNEL | - STEDMA40_LCHAN_SRC_LOG_DST_LOG | - STEDMA40_NO_TIM_FOR_LINK), .dir = STEDMA40_MEM_TO_MEM, - .src_info.endianess = STEDMA40_LITTLE_ENDIAN, .src_info.data_width = STEDMA40_BYTE_WIDTH, .src_info.psize = STEDMA40_PSIZE_LOG_1, .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, - .dst_info.endianess = STEDMA40_LITTLE_ENDIAN, .dst_info.data_width = STEDMA40_BYTE_WIDTH, .dst_info.psize = STEDMA40_PSIZE_LOG_1, .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, @@ -269,7 +259,6 @@ static struct stedma40_platform_data dma40_plat_data = { .memcpy_len = ARRAY_SIZE(dma40_memcpy_event), .memcpy_conf_phy = &dma40_memcpy_conf_phy, .memcpy_conf_log = &dma40_memcpy_conf_log, - .llis_per_log = 8, .disabled_channels = {-1}, }; @@ -292,3 +281,23 @@ void dma40_u8500ed_fixup(void) dma40_resources[1].start = U8500_DMA_LCPA_BASE_ED; dma40_resources[1].end = U8500_DMA_LCPA_BASE_ED + 2 * SZ_1K - 1; } + +struct resource keypad_resources[] = { + [0] = { + .start = U8500_SKE_BASE, + .end = U8500_SKE_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_DB8500_KB, + .end = IRQ_DB8500_KB, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device ux500_ske_keypad_device = { + .name = "nmk-ske-keypad", + .id = -1, + .num_resources = ARRAY_SIZE(keypad_resources), + .resource = keypad_resources, +}; diff --git a/arch/arm/mach-ux500/include/mach/devices.h b/arch/arm/mach-ux500/include/mach/devices.h index 33a120c2e82e..b91a4d1211a2 100644 --- a/arch/arm/mach-ux500/include/mach/devices.h +++ b/arch/arm/mach-ux500/include/mach/devices.h @@ -26,6 +26,7 @@ extern struct platform_device ux500_i2c3_device; extern struct platform_device u8500_i2c0_device; extern struct platform_device u8500_i2c4_device; extern struct platform_device u8500_dma40_device; +extern struct platform_device ux500_ske_keypad_device; extern struct amba_device u8500_sdi0_device; extern struct amba_device u8500_sdi1_device; diff --git a/arch/arm/mach-ux500/pins-db8500.h b/arch/arm/mach-ux500/pins-db8500.h index 66f8761cc823..f923764ee16c 100644 --- a/arch/arm/mach-ux500/pins-db8500.h +++ b/arch/arm/mach-ux500/pins-db8500.h @@ -459,82 +459,82 @@ #define GPIO152_KP_O9 PIN_CFG(152, ALT_C) #define GPIO153_GPIO PIN_CFG(153, GPIO) -#define GPIO153_KP_I7 PIN_CFG(153, ALT_A) +#define GPIO153_KP_I7 PIN_CFG_PULL(153, ALT_A, DOWN) #define GPIO153_LCD_D24 PIN_CFG(153, ALT_B) #define GPIO153_U2_RXD PIN_CFG(153, ALT_C) #define GPIO154_GPIO PIN_CFG(154, GPIO) -#define GPIO154_KP_I6 PIN_CFG(154, ALT_A) +#define GPIO154_KP_I6 PIN_CFG_PULL(154, ALT_A, DOWN) #define GPIO154_LCD_D25 PIN_CFG(154, ALT_B) #define GPIO154_U2_TXD PIN_CFG(154, ALT_C) #define GPIO155_GPIO PIN_CFG(155, GPIO) -#define GPIO155_KP_I5 PIN_CFG(155, ALT_A) +#define GPIO155_KP_I5 PIN_CFG_PULL(155, ALT_A, DOWN) #define GPIO155_LCD_D26 PIN_CFG(155, ALT_B) #define GPIO155_STMAPE_CLK PIN_CFG(155, ALT_C) #define GPIO156_GPIO PIN_CFG(156, GPIO) -#define GPIO156_KP_I4 PIN_CFG(156, ALT_A) +#define GPIO156_KP_I4 PIN_CFG_PULL(156, ALT_A, DOWN) #define GPIO156_LCD_D27 PIN_CFG(156, ALT_B) #define GPIO156_STMAPE_DAT3 PIN_CFG(156, ALT_C) #define GPIO157_GPIO PIN_CFG(157, GPIO) -#define GPIO157_KP_O7 PIN_CFG(157, ALT_A) +#define GPIO157_KP_O7 PIN_CFG_PULL(157, ALT_A, UP) #define GPIO157_LCD_D28 PIN_CFG(157, ALT_B) #define GPIO157_STMAPE_DAT2 PIN_CFG(157, ALT_C) #define GPIO158_GPIO PIN_CFG(158, GPIO) -#define GPIO158_KP_O6 PIN_CFG(158, ALT_A) +#define GPIO158_KP_O6 PIN_CFG_PULL(158, ALT_A, UP) #define GPIO158_LCD_D29 PIN_CFG(158, ALT_B) #define GPIO158_STMAPE_DAT1 PIN_CFG(158, ALT_C) #define GPIO159_GPIO PIN_CFG(159, GPIO) -#define GPIO159_KP_O5 PIN_CFG(159, ALT_A) +#define GPIO159_KP_O5 PIN_CFG_PULL(159, ALT_A, UP) #define GPIO159_LCD_D30 PIN_CFG(159, ALT_B) #define GPIO159_STMAPE_DAT0 PIN_CFG(159, ALT_C) #define GPIO160_GPIO PIN_CFG(160, GPIO) -#define GPIO160_KP_O4 PIN_CFG(160, ALT_A) +#define GPIO160_KP_O4 PIN_CFG_PULL(160, ALT_A, UP) #define GPIO160_LCD_D31 PIN_CFG(160, ALT_B) #define GPIO160_NONE PIN_CFG(160, ALT_C) #define GPIO161_GPIO PIN_CFG(161, GPIO) -#define GPIO161_KP_I3 PIN_CFG(161, ALT_A) +#define GPIO161_KP_I3 PIN_CFG_PULL(161, ALT_A, DOWN) #define GPIO161_LCD_D32 PIN_CFG(161, ALT_B) #define GPIO161_UARTMOD_RXD PIN_CFG(161, ALT_C) #define GPIO162_GPIO PIN_CFG(162, GPIO) -#define GPIO162_KP_I2 PIN_CFG(162, ALT_A) +#define GPIO162_KP_I2 PIN_CFG_PULL(162, ALT_A, DOWN) #define GPIO162_LCD_D33 PIN_CFG(162, ALT_B) #define GPIO162_UARTMOD_TXD PIN_CFG(162, ALT_C) #define GPIO163_GPIO PIN_CFG(163, GPIO) -#define GPIO163_KP_I1 PIN_CFG(163, ALT_A) +#define GPIO163_KP_I1 PIN_CFG_PULL(163, ALT_A, DOWN) #define GPIO163_LCD_D34 PIN_CFG(163, ALT_B) #define GPIO163_STMMOD_CLK PIN_CFG(163, ALT_C) #define GPIO164_GPIO PIN_CFG(164, GPIO) -#define GPIO164_KP_I0 PIN_CFG(164, ALT_A) +#define GPIO164_KP_I0 PIN_CFG_PULL(164, ALT_A, UP) #define GPIO164_LCD_D35 PIN_CFG(164, ALT_B) #define GPIO164_STMMOD_DAT3 PIN_CFG(164, ALT_C) #define GPIO165_GPIO PIN_CFG(165, GPIO) -#define GPIO165_KP_O3 PIN_CFG(165, ALT_A) +#define GPIO165_KP_O3 PIN_CFG_PULL(165, ALT_A, UP) #define GPIO165_LCD_D36 PIN_CFG(165, ALT_B) #define GPIO165_STMMOD_DAT2 PIN_CFG(165, ALT_C) #define GPIO166_GPIO PIN_CFG(166, GPIO) -#define GPIO166_KP_O2 PIN_CFG(166, ALT_A) +#define GPIO166_KP_O2 PIN_CFG_PULL(166, ALT_A, UP) #define GPIO166_LCD_D37 PIN_CFG(166, ALT_B) #define GPIO166_STMMOD_DAT1 PIN_CFG(166, ALT_C) #define GPIO167_GPIO PIN_CFG(167, GPIO) -#define GPIO167_KP_O1 PIN_CFG(167, ALT_A) +#define GPIO167_KP_O1 PIN_CFG_PULL(167, ALT_A, UP) #define GPIO167_LCD_D38 PIN_CFG(167, ALT_B) #define GPIO167_STMMOD_DAT0 PIN_CFG(167, ALT_C) #define GPIO168_GPIO PIN_CFG(168, GPIO) -#define GPIO168_KP_O0 PIN_CFG(168, ALT_A) +#define GPIO168_KP_O0 PIN_CFG_PULL(168, ALT_A, UP) #define GPIO168_LCD_D39 PIN_CFG(168, ALT_B) #define GPIO168_NONE PIN_CFG(168, ALT_C) diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c index 8440d952ba6d..c493d7244d3d 100644 --- a/arch/arm/mm/fault-armv.c +++ b/arch/arm/mm/fault-armv.c @@ -89,13 +89,13 @@ static int adjust_pte(struct vm_area_struct *vma, unsigned long address, * open-code the spin-locking. */ ptl = pte_lockptr(vma->vm_mm, pmd); - pte = pte_offset_map_nested(pmd, address); + pte = pte_offset_map(pmd, address); spin_lock(ptl); ret = do_adjust_pte(vma, address, pfn, pte); spin_unlock(ptl); - pte_unmap_nested(pte); + pte_unmap(pte); return ret; } diff --git a/arch/arm/mm/highmem.c b/arch/arm/mm/highmem.c index 1fbdb55bfd1b..c435fd9e1da9 100644 --- a/arch/arm/mm/highmem.c +++ b/arch/arm/mm/highmem.c @@ -36,18 +36,17 @@ void kunmap(struct page *page) } EXPORT_SYMBOL(kunmap); -void *kmap_atomic(struct page *page, enum km_type type) +void *__kmap_atomic(struct page *page) { unsigned int idx; unsigned long vaddr; void *kmap; + int type; pagefault_disable(); if (!PageHighMem(page)) return page_address(page); - debug_kmap_atomic(type); - #ifdef CONFIG_DEBUG_HIGHMEM /* * There is no cache coherency issue when non VIVT, so force the @@ -61,6 +60,8 @@ void *kmap_atomic(struct page *page, enum km_type type) if (kmap) return kmap; + type = kmap_atomic_idx_push(); + idx = type + KM_TYPE_NR * smp_processor_id(); vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); #ifdef CONFIG_DEBUG_HIGHMEM @@ -80,14 +81,17 @@ void *kmap_atomic(struct page *page, enum km_type type) return (void *)vaddr; } -EXPORT_SYMBOL(kmap_atomic); +EXPORT_SYMBOL(__kmap_atomic); -void kunmap_atomic_notypecheck(void *kvaddr, enum km_type type) +void __kunmap_atomic(void *kvaddr) { unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK; - unsigned int idx = type + KM_TYPE_NR * smp_processor_id(); + int idx, type; if (kvaddr >= (void *)FIXADDR_START) { + type = kmap_atomic_idx(); + idx = type + KM_TYPE_NR * smp_processor_id(); + if (cache_is_vivt()) __cpuc_flush_dcache_area((void *)vaddr, PAGE_SIZE); #ifdef CONFIG_DEBUG_HIGHMEM @@ -97,21 +101,23 @@ void kunmap_atomic_notypecheck(void *kvaddr, enum km_type type) #else (void) idx; /* to kill a warning */ #endif + kmap_atomic_idx_pop(); } else if (vaddr >= PKMAP_ADDR(0) && vaddr < PKMAP_ADDR(LAST_PKMAP)) { /* this address was obtained through kmap_high_get() */ kunmap_high(pte_page(pkmap_page_table[PKMAP_NR(vaddr)])); } pagefault_enable(); } -EXPORT_SYMBOL(kunmap_atomic_notypecheck); +EXPORT_SYMBOL(__kunmap_atomic); -void *kmap_atomic_pfn(unsigned long pfn, enum km_type type) +void *kmap_atomic_pfn(unsigned long pfn) { - unsigned int idx; unsigned long vaddr; + int idx, type; pagefault_disable(); + type = kmap_atomic_idx_push(); idx = type + KM_TYPE_NR * smp_processor_id(); vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); #ifdef CONFIG_DEBUG_HIGHMEM diff --git a/arch/arm/mm/pgd.c b/arch/arm/mm/pgd.c index be5f58e153bf..69bbfc6645a6 100644 --- a/arch/arm/mm/pgd.c +++ b/arch/arm/mm/pgd.c @@ -57,9 +57,9 @@ pgd_t *get_pgd_slow(struct mm_struct *mm) goto no_pte; init_pmd = pmd_offset(init_pgd, 0); - init_pte = pte_offset_map_nested(init_pmd, 0); + init_pte = pte_offset_map(init_pmd, 0); set_pte_ext(new_pte, *init_pte, 0); - pte_unmap_nested(init_pte); + pte_unmap(init_pte); pte_unmap(new_pte); } diff --git a/arch/arm/nwfpe/milieu.h b/arch/arm/nwfpe/milieu.h index a3892ab2dca4..09a4f2ddeb77 100644 --- a/arch/arm/nwfpe/milieu.h +++ b/arch/arm/nwfpe/milieu.h @@ -12,8 +12,8 @@ National Science Foundation under grant MIP-9311980. The original version of this code was written as part of a project to build a fixed-point vector processor in collaboration with the University of California at Berkeley, overseen by Profs. Nelson Morgan and John Wawrzynek. More information -is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/ -arithmetic/softfloat.html'. +is available through the Web page +http://www.jhauser.us/arithmetic/SoftFloat-2b/SoftFloat-source.txt THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT diff --git a/arch/arm/nwfpe/softfloat-macros b/arch/arm/nwfpe/softfloat-macros index 5a060f95a58f..cf2a6173149e 100644 --- a/arch/arm/nwfpe/softfloat-macros +++ b/arch/arm/nwfpe/softfloat-macros @@ -12,8 +12,8 @@ National Science Foundation under grant MIP-9311980. The original version of this code was written as part of a project to build a fixed-point vector processor in collaboration with the University of California at Berkeley, overseen by Profs. Nelson Morgan and John Wawrzynek. More information -is available through the web page `http://HTTP.CS.Berkeley.EDU/~jhauser/ -arithmetic/softfloat.html'. +is available through the web page +http://www.jhauser.us/arithmetic/SoftFloat-2b/SoftFloat-source.txt THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT diff --git a/arch/arm/nwfpe/softfloat-specialize b/arch/arm/nwfpe/softfloat-specialize index d4a4c8e06635..679a0269dd25 100644 --- a/arch/arm/nwfpe/softfloat-specialize +++ b/arch/arm/nwfpe/softfloat-specialize @@ -12,8 +12,8 @@ National Science Foundation under grant MIP-9311980. The original version of this code was written as part of a project to build a fixed-point vector processor in collaboration with the University of California at Berkeley, overseen by Profs. Nelson Morgan and John Wawrzynek. More information -is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/ -arithmetic/softfloat.html'. +is available through the Web page +http://www.jhauser.us/arithmetic/SoftFloat-2b/SoftFloat-source.txt THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT diff --git a/arch/arm/nwfpe/softfloat.c b/arch/arm/nwfpe/softfloat.c index 0f9656e482ba..ffa6b438786b 100644 --- a/arch/arm/nwfpe/softfloat.c +++ b/arch/arm/nwfpe/softfloat.c @@ -11,8 +11,8 @@ National Science Foundation under grant MIP-9311980. The original version of this code was written as part of a project to build a fixed-point vector processor in collaboration with the University of California at Berkeley, overseen by Profs. Nelson Morgan and John Wawrzynek. More information -is available through the web page `http://HTTP.CS.Berkeley.EDU/~jhauser/ -arithmetic/softfloat.html'. +is available through the web page +http://www.jhauser.us/arithmetic/SoftFloat-2b/SoftFloat-source.txt THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT diff --git a/arch/arm/nwfpe/softfloat.h b/arch/arm/nwfpe/softfloat.h index 13e479c5da57..df4d243a2b7c 100644 --- a/arch/arm/nwfpe/softfloat.h +++ b/arch/arm/nwfpe/softfloat.h @@ -12,8 +12,8 @@ National Science Foundation under grant MIP-9311980. The original version of this code was written as part of a project to build a fixed-point vector processor in collaboration with the University of California at Berkeley, overseen by Profs. Nelson Morgan and John Wawrzynek. More information -is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/ -arithmetic/softfloat.html'. +is available through the Web page +http://www.jhauser.us/arithmetic/SoftFloat-2b/SoftFloat-source.txt THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c index 62920490c0d6..0be1ac7f421b 100644 --- a/arch/arm/plat-mxc/audmux-v2.c +++ b/arch/arm/plat-mxc/audmux-v2.c @@ -137,6 +137,7 @@ static ssize_t audmux_read_file(struct file *file, char __user *user_buf, static const struct file_operations audmux_debugfs_fops = { .open = audmux_open_file, .read = audmux_read_file, + .llseek = default_llseek, }; static void audmux_debugfs_init(void) diff --git a/arch/arm/plat-mxc/include/mach/dma.h b/arch/arm/plat-mxc/include/mach/dma.h new file mode 100644 index 000000000000..ef7751546f5f --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/dma.h @@ -0,0 +1,67 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MXC_DMA_H__ +#define __ASM_ARCH_MXC_DMA_H__ + +#include <linux/scatterlist.h> +#include <linux/device.h> +#include <linux/dmaengine.h> + +/* + * This enumerates peripheral types. Used for SDMA. + */ +enum sdma_peripheral_type { + IMX_DMATYPE_SSI, /* MCU domain SSI */ + IMX_DMATYPE_SSI_SP, /* Shared SSI */ + IMX_DMATYPE_MMC, /* MMC */ + IMX_DMATYPE_SDHC, /* SDHC */ + IMX_DMATYPE_UART, /* MCU domain UART */ + IMX_DMATYPE_UART_SP, /* Shared UART */ + IMX_DMATYPE_FIRI, /* FIRI */ + IMX_DMATYPE_CSPI, /* MCU domain CSPI */ + IMX_DMATYPE_CSPI_SP, /* Shared CSPI */ + IMX_DMATYPE_SIM, /* SIM */ + IMX_DMATYPE_ATA, /* ATA */ + IMX_DMATYPE_CCM, /* CCM */ + IMX_DMATYPE_EXT, /* External peripheral */ + IMX_DMATYPE_MSHC, /* Memory Stick Host Controller */ + IMX_DMATYPE_MSHC_SP, /* Shared Memory Stick Host Controller */ + IMX_DMATYPE_DSP, /* DSP */ + IMX_DMATYPE_MEMORY, /* Memory */ + IMX_DMATYPE_FIFO_MEMORY,/* FIFO type Memory */ + IMX_DMATYPE_SPDIF, /* SPDIF */ + IMX_DMATYPE_IPU_MEMORY, /* IPU Memory */ + IMX_DMATYPE_ASRC, /* ASRC */ + IMX_DMATYPE_ESAI, /* ESAI */ +}; + +enum imx_dma_prio { + DMA_PRIO_HIGH = 0, + DMA_PRIO_MEDIUM = 1, + DMA_PRIO_LOW = 2 +}; + +struct imx_dma_data { + int dma_request; /* DMA request line */ + enum sdma_peripheral_type peripheral_type; + int priority; +}; + +static inline int imx_dma_is_ipu(struct dma_chan *chan) +{ + return !strcmp(dev_name(chan->device->dev), "ipu-core"); +} + +static inline int imx_dma_is_general_purpose(struct dma_chan *chan) +{ + return !strcmp(dev_name(chan->device->dev), "imx-sdma") || + !strcmp(dev_name(chan->device->dev), "imx-dma"); +} + +#endif diff --git a/arch/arm/plat-mxc/include/mach/sdma.h b/arch/arm/plat-mxc/include/mach/sdma.h new file mode 100644 index 000000000000..9be112227ac4 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/sdma.h @@ -0,0 +1,17 @@ +#ifndef __MACH_MXC_SDMA_H__ +#define __MACH_MXC_SDMA_H__ + +/** + * struct sdma_platform_data - platform specific data for SDMA engine + * + * @sdma_version The version of this SDMA engine + * @cpu_name used to generate the firmware name + * @to_version CPU Tape out version + */ +struct sdma_platform_data { + int sdma_version; + char *cpu_name; + int to_version; +}; + +#endif /* __MACH_MXC_SDMA_H__ */ diff --git a/arch/arm/plat-nomadik/include/plat/ske.h b/arch/arm/plat-nomadik/include/plat/ske.h new file mode 100644 index 000000000000..31382fbc07dc --- /dev/null +++ b/arch/arm/plat-nomadik/include/plat/ske.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * License Terms: GNU General Public License v2 + * Author: Naveen Kumar Gaddipati <naveen.gaddipati@stericsson.com> + * + * ux500 Scroll key and Keypad Encoder (SKE) header + */ + +#ifndef __SKE_H +#define __SKE_H + +#include <linux/input/matrix_keypad.h> + +/* register definitions for SKE peripheral */ +#define SKE_CR 0x00 +#define SKE_VAL0 0x04 +#define SKE_VAL1 0x08 +#define SKE_DBCR 0x0C +#define SKE_IMSC 0x10 +#define SKE_RIS 0x14 +#define SKE_MIS 0x18 +#define SKE_ICR 0x1C + +/* + * Keypad module + */ + +/** + * struct keypad_platform_data - structure for platform specific data + * @init: pointer to keypad init function + * @exit: pointer to keypad deinitialisation function + * @keymap_data: matrix scan code table for keycodes + * @krow: maximum number of rows + * @kcol: maximum number of columns + * @debounce_ms: platform specific debounce time + * @no_autorepeat: flag for auto repetition + * @wakeup_enable: allow waking up the system + */ +struct ske_keypad_platform_data { + int (*init)(void); + int (*exit)(void); + const struct matrix_keymap_data *keymap_data; + u8 krow; + u8 kcol; + u8 debounce_ms; + bool no_autorepeat; + bool wakeup_enable; +}; +#endif /*__SKE_KPD_H*/ diff --git a/arch/arm/plat-nomadik/include/plat/ste_dma40.h b/arch/arm/plat-nomadik/include/plat/ste_dma40.h index 5fbde4b8dc12..74b62f10d07f 100644 --- a/arch/arm/plat-nomadik/include/plat/ste_dma40.h +++ b/arch/arm/plat-nomadik/include/plat/ste_dma40.h @@ -1,10 +1,8 @@ /* - * arch/arm/plat-nomadik/include/plat/ste_dma40.h - * - * Copyright (C) ST-Ericsson 2007-2010 + * Copyright (C) ST-Ericsson SA 2007-2010 + * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson + * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson * License terms: GNU General Public License (GPL) version 2 - * Author: Per Friden <per.friden@stericsson.com> - * Author: Jonas Aaberg <jonas.aberg@stericsson.com> */ @@ -14,43 +12,25 @@ #include <linux/dmaengine.h> #include <linux/workqueue.h> #include <linux/interrupt.h> -#include <linux/dmaengine.h> /* dev types for memcpy */ #define STEDMA40_DEV_DST_MEMORY (-1) #define STEDMA40_DEV_SRC_MEMORY (-1) -/* - * Description of bitfields of channel_type variable is available in - * the info structure. - */ +enum stedma40_mode { + STEDMA40_MODE_LOGICAL = 0, + STEDMA40_MODE_PHYSICAL, + STEDMA40_MODE_OPERATION, +}; -/* Priority */ -#define STEDMA40_INFO_PRIO_TYPE_POS 2 -#define STEDMA40_HIGH_PRIORITY_CHANNEL (0x1 << STEDMA40_INFO_PRIO_TYPE_POS) -#define STEDMA40_LOW_PRIORITY_CHANNEL (0x2 << STEDMA40_INFO_PRIO_TYPE_POS) - -/* Mode */ -#define STEDMA40_INFO_CH_MODE_TYPE_POS 6 -#define STEDMA40_CHANNEL_IN_PHY_MODE (0x1 << STEDMA40_INFO_CH_MODE_TYPE_POS) -#define STEDMA40_CHANNEL_IN_LOG_MODE (0x2 << STEDMA40_INFO_CH_MODE_TYPE_POS) -#define STEDMA40_CHANNEL_IN_OPER_MODE (0x3 << STEDMA40_INFO_CH_MODE_TYPE_POS) - -/* Mode options */ -#define STEDMA40_INFO_CH_MODE_OPT_POS 8 -#define STEDMA40_PCHAN_BASIC_MODE (0x1 << STEDMA40_INFO_CH_MODE_OPT_POS) -#define STEDMA40_PCHAN_MODULO_MODE (0x2 << STEDMA40_INFO_CH_MODE_OPT_POS) -#define STEDMA40_PCHAN_DOUBLE_DST_MODE (0x3 << STEDMA40_INFO_CH_MODE_OPT_POS) -#define STEDMA40_LCHAN_SRC_PHY_DST_LOG (0x1 << STEDMA40_INFO_CH_MODE_OPT_POS) -#define STEDMA40_LCHAN_SRC_LOG_DST_PHS (0x2 << STEDMA40_INFO_CH_MODE_OPT_POS) -#define STEDMA40_LCHAN_SRC_LOG_DST_LOG (0x3 << STEDMA40_INFO_CH_MODE_OPT_POS) - -/* Interrupt */ -#define STEDMA40_INFO_TIM_POS 10 -#define STEDMA40_NO_TIM_FOR_LINK (0x0 << STEDMA40_INFO_TIM_POS) -#define STEDMA40_TIM_FOR_LINK (0x1 << STEDMA40_INFO_TIM_POS) - -/* End of channel_type configuration */ +enum stedma40_mode_opt { + STEDMA40_PCHAN_BASIC_MODE = 0, + STEDMA40_LCHAN_SRC_LOG_DST_LOG = 0, + STEDMA40_PCHAN_MODULO_MODE, + STEDMA40_PCHAN_DOUBLE_DST_MODE, + STEDMA40_LCHAN_SRC_PHY_DST_LOG, + STEDMA40_LCHAN_SRC_LOG_DST_PHY, +}; #define STEDMA40_ESIZE_8_BIT 0x0 #define STEDMA40_ESIZE_16_BIT 0x1 @@ -73,16 +53,14 @@ #define STEDMA40_PSIZE_LOG_8 STEDMA40_PSIZE_PHY_8 #define STEDMA40_PSIZE_LOG_16 STEDMA40_PSIZE_PHY_16 +/* Maximum number of possible physical channels */ +#define STEDMA40_MAX_PHYS 32 + enum stedma40_flow_ctrl { STEDMA40_NO_FLOW_CTRL, STEDMA40_FLOW_CTRL, }; -enum stedma40_endianess { - STEDMA40_LITTLE_ENDIAN, - STEDMA40_BIG_ENDIAN -}; - enum stedma40_periph_data_width { STEDMA40_BYTE_WIDTH = STEDMA40_ESIZE_8_BIT, STEDMA40_HALFWORD_WIDTH = STEDMA40_ESIZE_16_BIT, @@ -90,15 +68,8 @@ enum stedma40_periph_data_width { STEDMA40_DOUBLEWORD_WIDTH = STEDMA40_ESIZE_64_BIT }; -struct stedma40_half_channel_info { - enum stedma40_endianess endianess; - enum stedma40_periph_data_width data_width; - int psize; - enum stedma40_flow_ctrl flow_ctrl; -}; - enum stedma40_xfer_dir { - STEDMA40_MEM_TO_MEM, + STEDMA40_MEM_TO_MEM = 1, STEDMA40_MEM_TO_PERIPH, STEDMA40_PERIPH_TO_MEM, STEDMA40_PERIPH_TO_PERIPH @@ -106,18 +77,31 @@ enum stedma40_xfer_dir { /** + * struct stedma40_chan_cfg - dst/src channel configuration + * + * @big_endian: true if the src/dst should be read as big endian + * @data_width: Data width of the src/dst hardware + * @p_size: Burst size + * @flow_ctrl: Flow control on/off. + */ +struct stedma40_half_channel_info { + bool big_endian; + enum stedma40_periph_data_width data_width; + int psize; + enum stedma40_flow_ctrl flow_ctrl; +}; + +/** * struct stedma40_chan_cfg - Structure to be filled by client drivers. * * @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH - * @channel_type: priority, mode, mode options and interrupt configuration. + * @high_priority: true if high-priority + * @mode: channel mode: physical, logical, or operation + * @mode_opt: options for the chosen channel mode * @src_dev_type: Src device type * @dst_dev_type: Dst device type * @src_info: Parameters for dst half channel * @dst_info: Parameters for dst half channel - * @pre_transfer_data: Data to be passed on to the pre_transfer() function. - * @pre_transfer: Callback used if needed before preparation of transfer. - * Only called if device is set. size of bytes to transfer - * (in case of multiple element transfer size is size of the first element). * * * This structure has to be filled by the client drivers. @@ -126,15 +110,13 @@ enum stedma40_xfer_dir { */ struct stedma40_chan_cfg { enum stedma40_xfer_dir dir; - unsigned int channel_type; + bool high_priority; + enum stedma40_mode mode; + enum stedma40_mode_opt mode_opt; int src_dev_type; int dst_dev_type; struct stedma40_half_channel_info src_info; struct stedma40_half_channel_info dst_info; - void *pre_transfer_data; - int (*pre_transfer) (struct dma_chan *chan, - void *data, - int size); }; /** @@ -147,7 +129,6 @@ struct stedma40_chan_cfg { * @memcpy_len: length of memcpy * @memcpy_conf_phy: default configuration of physical channel memcpy * @memcpy_conf_log: default configuration of logical channel memcpy - * @llis_per_log: number of max linked list items per logical channel * @disabled_channels: A vector, ending with -1, that marks physical channels * that are for different reasons not available for the driver. */ @@ -159,23 +140,10 @@ struct stedma40_platform_data { u32 memcpy_len; struct stedma40_chan_cfg *memcpy_conf_phy; struct stedma40_chan_cfg *memcpy_conf_log; - unsigned int llis_per_log; - int disabled_channels[8]; + int disabled_channels[STEDMA40_MAX_PHYS]; }; -/** - * setdma40_set_psize() - Used for changing the package size of an - * already configured dma channel. - * - * @chan: dmaengine handle - * @src_psize: new package side for src. (STEDMA40_PSIZE*) - * @src_psize: new package side for dst. (STEDMA40_PSIZE*) - * - * returns 0 on ok, otherwise negative error number. - */ -int stedma40_set_psize(struct dma_chan *chan, - int src_psize, - int dst_psize); +#ifdef CONFIG_STE_DMA40 /** * stedma40_filter() - Provides stedma40_chan_cfg to the @@ -238,4 +206,21 @@ dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan, direction, flags); } +#else +static inline bool stedma40_filter(struct dma_chan *chan, void *data) +{ + return false; +} + +static inline struct +dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan, + dma_addr_t addr, + unsigned int size, + enum dma_data_direction direction, + unsigned long flags) +{ + return NULL; +} +#endif + #endif diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index a92cb499313f..92c5bb7909f5 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig @@ -19,7 +19,7 @@ config ARCH_OMAP2PLUS bool "TI OMAP2/3/4" select COMMON_CLKDEV help - "Systems based on omap24xx, omap34xx or omap44xx" + "Systems based on OMAP2, OMAP3 or OMAP4" endchoice diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile index 9405831b746a..a4a12859fdd5 100644 --- a/arch/arm/plat-omap/Makefile +++ b/arch/arm/plat-omap/Makefile @@ -4,7 +4,7 @@ # Common support obj-y := common.o sram.o clock.o devices.o dma.o mux.o gpio.o \ - usb.o fb.o io.o + usb.o fb.o io.o counter_32k.o obj-m := obj-n := obj- := @@ -31,4 +31,4 @@ obj-y += $(i2c-omap-m) $(i2c-omap-y) # OMAP mailbox framework obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o -obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o
\ No newline at end of file +obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c index 7190cbd92620..fc62fb5fc20b 100644 --- a/arch/arm/plat-omap/clock.c +++ b/arch/arm/plat-omap/clock.c @@ -60,7 +60,7 @@ void clk_disable(struct clk *clk) spin_lock_irqsave(&clockfw_lock, flags); if (clk->usecount == 0) { - printk(KERN_ERR "Trying disable clock %s with 0 usecount\n", + pr_err("Trying disable clock %s with 0 usecount\n", clk->name); WARN_ON(1); goto out; @@ -397,6 +397,7 @@ static int __init clk_disable_unused(void) struct clk *ck; unsigned long flags; + pr_info("clock: disabling unused clocks to save power\n"); list_for_each_entry(ck, &clocks, node) { if (ck->ops == &clkops_null) continue; @@ -418,7 +419,7 @@ late_initcall(clk_disable_unused); int __init clk_init(struct clk_functions * custom_clocks) { if (!custom_clocks) { - printk(KERN_ERR "No custom clock functions registered\n"); + pr_err("No custom clock functions registered\n"); BUG(); } diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c index 3008e7104487..221a675ebbae 100644 --- a/arch/arm/plat-omap/common.c +++ b/arch/arm/plat-omap/common.c @@ -11,38 +11,15 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -#include <linux/module.h> #include <linux/kernel.h> #include <linux/init.h> -#include <linux/delay.h> -#include <linux/console.h> -#include <linux/serial.h> -#include <linux/tty.h> -#include <linux/serial_8250.h> -#include <linux/serial_reg.h> -#include <linux/clk.h> #include <linux/io.h> #include <linux/omapfb.h> -#include <mach/hardware.h> -#include <asm/system.h> -#include <asm/pgtable.h> -#include <asm/mach/map.h> -#include <asm/setup.h> - #include <plat/common.h> #include <plat/board.h> -#include <plat/control.h> -#include <plat/mux.h> -#include <plat/fpga.h> -#include <plat/serial.h> #include <plat/vram.h> -#include <plat/clock.h> - -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) -# include "../mach-omap2/sdrc.h" -#endif #define NO_LENGTH_CHECK 0xffffffff @@ -88,270 +65,3 @@ void __init omap_reserve(void) omapfb_reserve_sdram_memblock(); omap_vram_reserve_sdram_memblock(); } - -/* - * 32KHz clocksource ... always available, on pretty most chips except - * OMAP 730 and 1510. Other timers could be used as clocksources, with - * higher resolution in free-running counter modes (e.g. 12 MHz xtal), - * but systems won't necessarily want to spend resources that way. - */ - -#define OMAP16XX_TIMER_32K_SYNCHRONIZED 0xfffbc410 - -#if !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX)) - -#include <linux/clocksource.h> - -/* - * offset_32k holds the init time counter value. It is then subtracted - * from every counter read to achieve a counter that counts time from the - * kernel boot (needed for sched_clock()). - */ -static u32 offset_32k __read_mostly; - -#ifdef CONFIG_ARCH_OMAP16XX -static cycle_t omap16xx_32k_read(struct clocksource *cs) -{ - return omap_readl(OMAP16XX_TIMER_32K_SYNCHRONIZED) - offset_32k; -} -#else -#define omap16xx_32k_read NULL -#endif - -#ifdef CONFIG_ARCH_OMAP2420 -static cycle_t omap2420_32k_read(struct clocksource *cs) -{ - return omap_readl(OMAP2420_32KSYNCT_BASE + 0x10) - offset_32k; -} -#else -#define omap2420_32k_read NULL -#endif - -#ifdef CONFIG_ARCH_OMAP2430 -static cycle_t omap2430_32k_read(struct clocksource *cs) -{ - return omap_readl(OMAP2430_32KSYNCT_BASE + 0x10) - offset_32k; -} -#else -#define omap2430_32k_read NULL -#endif - -#ifdef CONFIG_ARCH_OMAP3 -static cycle_t omap34xx_32k_read(struct clocksource *cs) -{ - return omap_readl(OMAP3430_32KSYNCT_BASE + 0x10) - offset_32k; -} -#else -#define omap34xx_32k_read NULL -#endif - -#ifdef CONFIG_ARCH_OMAP4 -static cycle_t omap44xx_32k_read(struct clocksource *cs) -{ - return omap_readl(OMAP4430_32KSYNCT_BASE + 0x10) - offset_32k; -} -#else -#define omap44xx_32k_read NULL -#endif - -/* - * Kernel assumes that sched_clock can be called early but may not have - * things ready yet. - */ -static cycle_t omap_32k_read_dummy(struct clocksource *cs) -{ - return 0; -} - -static struct clocksource clocksource_32k = { - .name = "32k_counter", - .rating = 250, - .read = omap_32k_read_dummy, - .mask = CLOCKSOURCE_MASK(32), - .shift = 10, - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -/* - * Returns current time from boot in nsecs. It's OK for this to wrap - * around for now, as it's just a relative time stamp. - */ -unsigned long long sched_clock(void) -{ - return clocksource_cyc2ns(clocksource_32k.read(&clocksource_32k), - clocksource_32k.mult, clocksource_32k.shift); -} - -/** - * read_persistent_clock - Return time from a persistent clock. - * - * Reads the time from a source which isn't disabled during PM, the - * 32k sync timer. Convert the cycles elapsed since last read into - * nsecs and adds to a monotonically increasing timespec. - */ -static struct timespec persistent_ts; -static cycles_t cycles, last_cycles; -void read_persistent_clock(struct timespec *ts) -{ - unsigned long long nsecs; - cycles_t delta; - struct timespec *tsp = &persistent_ts; - - last_cycles = cycles; - cycles = clocksource_32k.read(&clocksource_32k); - delta = cycles - last_cycles; - - nsecs = clocksource_cyc2ns(delta, - clocksource_32k.mult, clocksource_32k.shift); - - timespec_add_ns(tsp, nsecs); - *ts = *tsp; -} - -static int __init omap_init_clocksource_32k(void) -{ - static char err[] __initdata = KERN_ERR - "%s: can't register clocksource!\n"; - - if (cpu_is_omap16xx() || cpu_class_is_omap2()) { - struct clk *sync_32k_ick; - - if (cpu_is_omap16xx()) - clocksource_32k.read = omap16xx_32k_read; - else if (cpu_is_omap2420()) - clocksource_32k.read = omap2420_32k_read; - else if (cpu_is_omap2430()) - clocksource_32k.read = omap2430_32k_read; - else if (cpu_is_omap34xx()) - clocksource_32k.read = omap34xx_32k_read; - else if (cpu_is_omap44xx()) - clocksource_32k.read = omap44xx_32k_read; - else - return -ENODEV; - - sync_32k_ick = clk_get(NULL, "omap_32ksync_ick"); - if (sync_32k_ick) - clk_enable(sync_32k_ick); - - clocksource_32k.mult = clocksource_hz2mult(32768, - clocksource_32k.shift); - - offset_32k = clocksource_32k.read(&clocksource_32k); - - if (clocksource_register(&clocksource_32k)) - printk(err, clocksource_32k.name); - } - return 0; -} -arch_initcall(omap_init_clocksource_32k); - -#endif /* !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX)) */ - -/* Global address base setup code */ - -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) - -static void __init __omap2_set_globals(struct omap_globals *omap2_globals) -{ - omap2_set_globals_tap(omap2_globals); - omap2_set_globals_sdrc(omap2_globals); - omap2_set_globals_control(omap2_globals); - omap2_set_globals_prcm(omap2_globals); - omap2_set_globals_uart(omap2_globals); -} - -#endif - -#if defined(CONFIG_ARCH_OMAP2420) - -static struct omap_globals omap242x_globals = { - .class = OMAP242X_CLASS, - .tap = OMAP2_L4_IO_ADDRESS(0x48014000), - .sdrc = OMAP2420_SDRC_BASE, - .sms = OMAP2420_SMS_BASE, - .ctrl = OMAP2420_CTRL_BASE, - .prm = OMAP2420_PRM_BASE, - .cm = OMAP2420_CM_BASE, - .uart1_phys = OMAP2_UART1_BASE, - .uart2_phys = OMAP2_UART2_BASE, - .uart3_phys = OMAP2_UART3_BASE, -}; - -void __init omap2_set_globals_242x(void) -{ - __omap2_set_globals(&omap242x_globals); -} -#endif - -#if defined(CONFIG_ARCH_OMAP2430) - -static struct omap_globals omap243x_globals = { - .class = OMAP243X_CLASS, - .tap = OMAP2_L4_IO_ADDRESS(0x4900a000), - .sdrc = OMAP243X_SDRC_BASE, - .sms = OMAP243X_SMS_BASE, - .ctrl = OMAP243X_CTRL_BASE, - .prm = OMAP2430_PRM_BASE, - .cm = OMAP2430_CM_BASE, - .uart1_phys = OMAP2_UART1_BASE, - .uart2_phys = OMAP2_UART2_BASE, - .uart3_phys = OMAP2_UART3_BASE, -}; - -void __init omap2_set_globals_243x(void) -{ - __omap2_set_globals(&omap243x_globals); -} -#endif - -#if defined(CONFIG_ARCH_OMAP3) - -static struct omap_globals omap3_globals = { - .class = OMAP343X_CLASS, - .tap = OMAP2_L4_IO_ADDRESS(0x4830A000), - .sdrc = OMAP343X_SDRC_BASE, - .sms = OMAP343X_SMS_BASE, - .ctrl = OMAP343X_CTRL_BASE, - .prm = OMAP3430_PRM_BASE, - .cm = OMAP3430_CM_BASE, - .uart1_phys = OMAP3_UART1_BASE, - .uart2_phys = OMAP3_UART2_BASE, - .uart3_phys = OMAP3_UART3_BASE, - .uart4_phys = OMAP3_UART4_BASE, /* Only on 3630 */ -}; - -void __init omap2_set_globals_3xxx(void) -{ - __omap2_set_globals(&omap3_globals); -} - -void __init omap3_map_io(void) -{ - omap2_set_globals_3xxx(); - omap34xx_map_common_io(); -} -#endif - -#if defined(CONFIG_ARCH_OMAP4) -static struct omap_globals omap4_globals = { - .class = OMAP443X_CLASS, - .tap = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE), - .ctrl = OMAP443X_CTRL_BASE, - .prm = OMAP4430_PRM_BASE, - .cm = OMAP4430_CM_BASE, - .cm2 = OMAP4430_CM2_BASE, - .uart1_phys = OMAP4_UART1_BASE, - .uart2_phys = OMAP4_UART2_BASE, - .uart3_phys = OMAP4_UART3_BASE, - .uart4_phys = OMAP4_UART4_BASE, -}; - -void __init omap2_set_globals_443x(void) -{ - omap2_set_globals_tap(&omap4_globals); - omap2_set_globals_control(&omap4_globals); - omap2_set_globals_prcm(&omap4_globals); - omap2_set_globals_uart(&omap4_globals); -} -#endif - diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c new file mode 100644 index 000000000000..155fe43a672b --- /dev/null +++ b/arch/arm/plat-omap/counter_32k.c @@ -0,0 +1,183 @@ +/* + * OMAP 32ksynctimer/counter_32k-related code + * + * Copyright (C) 2009 Texas Instruments + * Copyright (C) 2010 Nokia Corporation + * Tony Lindgren <tony@atomide.com> + * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * NOTE: This timer is not the same timer as the old OMAP1 MPU timer. + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/clk.h> +#include <linux/io.h> + +#include <plat/common.h> +#include <plat/board.h> + +#include <plat/clock.h> + + +/* + * 32KHz clocksource ... always available, on pretty most chips except + * OMAP 730 and 1510. Other timers could be used as clocksources, with + * higher resolution in free-running counter modes (e.g. 12 MHz xtal), + * but systems won't necessarily want to spend resources that way. + */ + +#define OMAP16XX_TIMER_32K_SYNCHRONIZED 0xfffbc410 + +#if !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX)) + +#include <linux/clocksource.h> + +/* + * offset_32k holds the init time counter value. It is then subtracted + * from every counter read to achieve a counter that counts time from the + * kernel boot (needed for sched_clock()). + */ +static u32 offset_32k __read_mostly; + +#ifdef CONFIG_ARCH_OMAP16XX +static cycle_t omap16xx_32k_read(struct clocksource *cs) +{ + return omap_readl(OMAP16XX_TIMER_32K_SYNCHRONIZED) - offset_32k; +} +#else +#define omap16xx_32k_read NULL +#endif + +#ifdef CONFIG_ARCH_OMAP2420 +static cycle_t omap2420_32k_read(struct clocksource *cs) +{ + return omap_readl(OMAP2420_32KSYNCT_BASE + 0x10) - offset_32k; +} +#else +#define omap2420_32k_read NULL +#endif + +#ifdef CONFIG_ARCH_OMAP2430 +static cycle_t omap2430_32k_read(struct clocksource *cs) +{ + return omap_readl(OMAP2430_32KSYNCT_BASE + 0x10) - offset_32k; +} +#else +#define omap2430_32k_read NULL +#endif + +#ifdef CONFIG_ARCH_OMAP3 +static cycle_t omap34xx_32k_read(struct clocksource *cs) +{ + return omap_readl(OMAP3430_32KSYNCT_BASE + 0x10) - offset_32k; +} +#else +#define omap34xx_32k_read NULL +#endif + +#ifdef CONFIG_ARCH_OMAP4 +static cycle_t omap44xx_32k_read(struct clocksource *cs) +{ + return omap_readl(OMAP4430_32KSYNCT_BASE + 0x10) - offset_32k; +} +#else +#define omap44xx_32k_read NULL +#endif + +/* + * Kernel assumes that sched_clock can be called early but may not have + * things ready yet. + */ +static cycle_t omap_32k_read_dummy(struct clocksource *cs) +{ + return 0; +} + +static struct clocksource clocksource_32k = { + .name = "32k_counter", + .rating = 250, + .read = omap_32k_read_dummy, + .mask = CLOCKSOURCE_MASK(32), + .shift = 10, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +/* + * Returns current time from boot in nsecs. It's OK for this to wrap + * around for now, as it's just a relative time stamp. + */ +unsigned long long sched_clock(void) +{ + return clocksource_cyc2ns(clocksource_32k.read(&clocksource_32k), + clocksource_32k.mult, clocksource_32k.shift); +} + +/** + * read_persistent_clock - Return time from a persistent clock. + * + * Reads the time from a source which isn't disabled during PM, the + * 32k sync timer. Convert the cycles elapsed since last read into + * nsecs and adds to a monotonically increasing timespec. + */ +static struct timespec persistent_ts; +static cycles_t cycles, last_cycles; +void read_persistent_clock(struct timespec *ts) +{ + unsigned long long nsecs; + cycles_t delta; + struct timespec *tsp = &persistent_ts; + + last_cycles = cycles; + cycles = clocksource_32k.read(&clocksource_32k); + delta = cycles - last_cycles; + + nsecs = clocksource_cyc2ns(delta, + clocksource_32k.mult, clocksource_32k.shift); + + timespec_add_ns(tsp, nsecs); + *ts = *tsp; +} + +static int __init omap_init_clocksource_32k(void) +{ + static char err[] __initdata = KERN_ERR + "%s: can't register clocksource!\n"; + + if (cpu_is_omap16xx() || cpu_class_is_omap2()) { + struct clk *sync_32k_ick; + + if (cpu_is_omap16xx()) + clocksource_32k.read = omap16xx_32k_read; + else if (cpu_is_omap2420()) + clocksource_32k.read = omap2420_32k_read; + else if (cpu_is_omap2430()) + clocksource_32k.read = omap2430_32k_read; + else if (cpu_is_omap34xx()) + clocksource_32k.read = omap34xx_32k_read; + else if (cpu_is_omap44xx()) + clocksource_32k.read = omap44xx_32k_read; + else + return -ENODEV; + + sync_32k_ick = clk_get(NULL, "omap_32ksync_ick"); + if (sync_32k_ick) + clk_enable(sync_32k_ick); + + clocksource_32k.mult = clocksource_hz2mult(32768, + clocksource_32k.shift); + + offset_32k = clocksource_32k.read(&clocksource_32k); + + if (clocksource_register(&clocksource_32k)) + printk(err, clocksource_32k.name); + } + return 0; +} +arch_initcall(omap_init_clocksource_32k); + +#endif /* !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX)) */ + diff --git a/arch/arm/plat-omap/cpu-omap.c b/arch/arm/plat-omap/cpu-omap.c index 6d3d33360056..11c54ec8d47f 100644 --- a/arch/arm/plat-omap/cpu-omap.c +++ b/arch/arm/plat-omap/cpu-omap.c @@ -40,7 +40,7 @@ static struct clk *mpu_clk; /* TODO: Add support for SDRAM timing changes */ -int omap_verify_speed(struct cpufreq_policy *policy) +static int omap_verify_speed(struct cpufreq_policy *policy) { if (freq_table) return cpufreq_frequency_table_verify(policy, freq_table); @@ -58,7 +58,7 @@ int omap_verify_speed(struct cpufreq_policy *policy) return 0; } -unsigned int omap_getspeed(unsigned int cpu) +static unsigned int omap_getspeed(unsigned int cpu) { unsigned long rate; diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c index d1920be7833b..1e2383eae638 100644 --- a/arch/arm/plat-omap/devices.c +++ b/arch/arm/plat-omap/devices.c @@ -21,7 +21,6 @@ #include <asm/mach/map.h> #include <plat/tc.h> -#include <plat/control.h> #include <plat/board.h> #include <plat/mmc.h> #include <mach/gpio.h> @@ -232,46 +231,6 @@ static void omap_init_uwire(void) static inline void omap_init_uwire(void) {} #endif -/*-------------------------------------------------------------------------*/ - -#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE) - -static struct resource wdt_resources[] = { - { - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device omap_wdt_device = { - .name = "omap_wdt", - .id = -1, - .num_resources = ARRAY_SIZE(wdt_resources), - .resource = wdt_resources, -}; - -static void omap_init_wdt(void) -{ - if (cpu_is_omap16xx()) - wdt_resources[0].start = 0xfffeb000; - else if (cpu_is_omap2420()) - wdt_resources[0].start = 0x48022000; /* WDT2 */ - else if (cpu_is_omap2430()) - wdt_resources[0].start = 0x49016000; /* WDT2 */ - else if (cpu_is_omap343x()) - wdt_resources[0].start = 0x48314000; /* WDT2 */ - else if (cpu_is_omap44xx()) - wdt_resources[0].start = 0x4a314000; - else - return; - - wdt_resources[0].end = wdt_resources[0].start + 0x4f; - - (void) platform_device_register(&omap_wdt_device); -} -#else -static inline void omap_init_wdt(void) {} -#endif - /* * This gets called after board-specific INIT_MACHINE, and initializes most * on-chip peripherals accessible on this board (except for few like USB): @@ -300,7 +259,6 @@ static int __init omap_init_devices(void) omap_init_rng(); omap_init_mcpdm(); omap_init_uwire(); - omap_init_wdt(); return 0; } arch_initcall(omap_init_devices); diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index ec7eddf9e525..f5c5b8da9a87 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -30,6 +30,7 @@ #include <linux/irq.h> #include <linux/io.h> #include <linux/slab.h> +#include <linux/delay.h> #include <asm/system.h> #include <mach/hardware.h> @@ -996,11 +997,17 @@ void omap_start_dma(int lch) l = dma_read(CCR(lch)); /* - * Errata: On ES2.0 BUFFERING disable must be set. - * This will always fail on ES1.0 + * Errata: Inter Frame DMA buffering issue (All OMAP2420 and + * OMAP2430ES1.0): DMA will wrongly buffer elements if packing and + * bursting is enabled. This might result in data gets stalled in + * FIFO at the end of the block. + * Workaround: DMA channels must have BUFFERING_DISABLED bit set to + * guarantee no data will stay in the DMA FIFO in case inter frame + * buffering occurs. */ - if (cpu_is_omap24xx()) - l |= OMAP_DMA_CCR_EN; + if (cpu_is_omap2420() || + (cpu_is_omap2430() && (omap_type() == OMAP2430_REV_ES1_0))) + l |= OMAP_DMA_CCR_BUFFERING_DISABLE; l |= OMAP_DMA_CCR_EN; dma_write(l, CCR(lch)); @@ -1018,8 +1025,39 @@ void omap_stop_dma(int lch) dma_write(0, CICR(lch)); l = dma_read(CCR(lch)); - l &= ~OMAP_DMA_CCR_EN; - dma_write(l, CCR(lch)); + /* OMAP3 Errata i541: sDMA FIFO draining does not finish */ + if (cpu_is_omap34xx() && (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) { + int i = 0; + u32 sys_cf; + + /* Configure No-Standby */ + l = dma_read(OCP_SYSCONFIG); + sys_cf = l; + l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK; + l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE); + dma_write(l , OCP_SYSCONFIG); + + l = dma_read(CCR(lch)); + l &= ~OMAP_DMA_CCR_EN; + dma_write(l, CCR(lch)); + + /* Wait for sDMA FIFO drain */ + l = dma_read(CCR(lch)); + while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE | + OMAP_DMA_CCR_WR_ACTIVE))) { + udelay(5); + i++; + l = dma_read(CCR(lch)); + } + if (i >= 100) + printk(KERN_ERR "DMA drain did not complete on " + "lch %d\n", lch); + /* Restore OCP_SYSCONFIG */ + dma_write(sys_cf, OCP_SYSCONFIG); + } else { + l &= ~OMAP_DMA_CCR_EN; + dma_write(l, CCR(lch)); + } if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { int next_lch, cur_lch = lch; diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 44bafdab2dce..1d706cf63ca0 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -581,7 +581,7 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) * When the functional clock disappears, too quick writes seem * to cause an abort. XXX Is this still necessary? */ - __delay(150000); + __delay(300000); return ret; } diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c index 71934817e172..c9e5d7298c40 100644 --- a/arch/arm/plat-omap/fb.c +++ b/arch/arm/plat-omap/fb.c @@ -36,6 +36,8 @@ #include <plat/board.h> #include <plat/sram.h> +#include "fb.h" + #if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE) static struct omapfb_platform_data omapfb_config; @@ -94,7 +96,7 @@ static int fbmem_region_reserved(unsigned long start, size_t size) * Get the region_idx`th region from board config/ATAG and convert it to * our internal format. */ -static int get_fbmem_region(int region_idx, struct omapfb_mem_region *rg) +static int __init get_fbmem_region(int region_idx, struct omapfb_mem_region *rg) { const struct omap_fbmem_config *conf; u32 paddr; @@ -126,7 +128,7 @@ static int set_fbmem_region_type(struct omapfb_mem_region *rg, int mem_type, * type = 0 && paddr = 0, a default don't care case maps to * the SDRAM type. */ - if (rg->type || (!rg->type && !rg->paddr)) + if (rg->type || !rg->paddr) return 0; if (ranges_overlap(rg->paddr, rg->size, mem_start, mem_size)) { rg->type = mem_type; @@ -258,7 +260,7 @@ void __init omapfb_reserve_sdram_memblock(void) * this point, since the driver built as a module would have problem with * freeing / reallocating the regions. */ -unsigned long omapfb_reserve_sram(unsigned long sram_pstart, +unsigned long __init omapfb_reserve_sram(unsigned long sram_pstart, unsigned long sram_vstart, unsigned long sram_size, unsigned long pstart_avail, @@ -332,7 +334,7 @@ void omapfb_set_ctrl_platform_data(void *data) omapfb_config.ctrl_platform_data = data; } -static inline int omap_init_fb(void) +static int __init omap_init_fb(void) { const struct omap_lcd_config *conf; @@ -377,7 +379,7 @@ void omapfb_set_platform_data(struct omapfb_platform_data *data) omapfb_config = *data; } -static inline int omap_init_fb(void) +static int __init omap_init_fb(void) { return platform_device_register(&omap_fb_device); } @@ -388,7 +390,7 @@ void omapfb_reserve_sdram_memblock(void) { } -unsigned long omapfb_reserve_sram(unsigned long sram_pstart, +unsigned long __init omapfb_reserve_sram(unsigned long sram_pstart, unsigned long sram_vstart, unsigned long sram_size, unsigned long start_avail, @@ -407,7 +409,7 @@ void omapfb_reserve_sdram_memblock(void) { } -unsigned long omapfb_reserve_sram(unsigned long sram_pstart, +unsigned long __init omapfb_reserve_sram(unsigned long sram_pstart, unsigned long sram_vstart, unsigned long sram_size, unsigned long start_avail, diff --git a/arch/arm/plat-omap/fb.h b/arch/arm/plat-omap/fb.h new file mode 100644 index 000000000000..d765d0bd8520 --- /dev/null +++ b/arch/arm/plat-omap/fb.h @@ -0,0 +1,10 @@ +#ifndef __PLAT_OMAP_FB_H__ +#define __PLAT_OMAP_FB_H__ + +extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart, + unsigned long sram_vstart, + unsigned long sram_size, + unsigned long pstart_avail, + unsigned long size_avail); + +#endif /* __PLAT_OMAP_FB_H__ */ diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 7951eefe1a0e..c05c653d1674 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -2084,9 +2084,10 @@ void omap2_gpio_prepare_for_idle(int power_state) for (i = min; i < gpio_bank_count; i++) { struct gpio_bank *bank = &gpio_bank[i]; - u32 l1, l2; + u32 l1 = 0, l2 = 0; + int j; - if (bank->dbck_enable_mask) + for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) clk_disable(bank->dbck); if (power_state > PWRDM_POWER_OFF) @@ -2151,9 +2152,10 @@ void omap2_gpio_resume_after_idle(void) min = 1; for (i = min; i < gpio_bank_count; i++) { struct gpio_bank *bank = &gpio_bank[i]; - u32 l, gen, gen0, gen1; + u32 l = 0, gen, gen0, gen1; + int j; - if (bank->dbck_enable_mask) + for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) clk_enable(bank->dbck); if (!workaround_enabled) diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h index 9776b41ad76f..a9d69a09920d 100644 --- a/arch/arm/plat-omap/include/plat/common.h +++ b/arch/arm/plat-omap/include/plat/common.h @@ -47,6 +47,7 @@ struct omap_globals { unsigned long sdrc; /* SDRAM Controller */ unsigned long sms; /* SDRAM Memory Scheduler */ unsigned long ctrl; /* System Control Module */ + unsigned long ctrl_pad; /* PAD Control Module */ unsigned long prm; /* Power and Reset Management */ unsigned long cm; /* Clock Management */ unsigned long cm2; @@ -66,7 +67,6 @@ void omap2_set_globals_tap(struct omap_globals *); void omap2_set_globals_sdrc(struct omap_globals *); void omap2_set_globals_control(struct omap_globals *); void omap2_set_globals_prcm(struct omap_globals *); -void omap2_set_globals_uart(struct omap_globals *); void omap3_map_io(void); @@ -91,7 +91,8 @@ void omap3_map_io(void); }) extern struct device *omap2_get_mpuss_device(void); -extern struct device *omap2_get_dsp_device(void); +extern struct device *omap2_get_iva_device(void); extern struct device *omap2_get_l3_device(void); +extern struct device *omap4_get_dsp_device(void); #endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */ diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index 2e2ae530fced..3fd8b4055727 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h @@ -68,10 +68,9 @@ unsigned int omap_rev(void); #define OMAP_REVBITS_00 0x00 #define OMAP_REVBITS_01 0x01 #define OMAP_REVBITS_02 0x02 -#define OMAP_REVBITS_10 0x10 -#define OMAP_REVBITS_20 0x20 -#define OMAP_REVBITS_30 0x30 -#define OMAP_REVBITS_40 0x40 +#define OMAP_REVBITS_03 0x03 +#define OMAP_REVBITS_04 0x04 +#define OMAP_REVBITS_05 0x05 /* * Get the CPU revision for OMAP devices @@ -363,23 +362,24 @@ IS_OMAP_TYPE(3517, 0x3517) /* Various silicon revisions for omap2 */ #define OMAP242X_CLASS 0x24200024 -#define OMAP2420_REV_ES1_0 0x24200024 -#define OMAP2420_REV_ES2_0 0x24201024 +#define OMAP2420_REV_ES1_0 OMAP242X_CLASS +#define OMAP2420_REV_ES2_0 (OMAP242X_CLASS | (OMAP_REVBITS_01 << 8)) #define OMAP243X_CLASS 0x24300024 -#define OMAP2430_REV_ES1_0 0x24300024 +#define OMAP2430_REV_ES1_0 OMAP243X_CLASS #define OMAP343X_CLASS 0x34300034 -#define OMAP3430_REV_ES1_0 0x34300034 -#define OMAP3430_REV_ES2_0 0x34301034 -#define OMAP3430_REV_ES2_1 0x34302034 -#define OMAP3430_REV_ES3_0 0x34303034 -#define OMAP3430_REV_ES3_1 0x34304034 -#define OMAP3430_REV_ES3_1_2 0x34305034 - -#define OMAP3630_REV_ES1_0 0x36300034 -#define OMAP3630_REV_ES1_1 0x36300134 -#define OMAP3630_REV_ES1_2 0x36300234 +#define OMAP3430_REV_ES1_0 OMAP343X_CLASS +#define OMAP3430_REV_ES2_0 (OMAP343X_CLASS | (OMAP_REVBITS_01 << 8)) +#define OMAP3430_REV_ES2_1 (OMAP343X_CLASS | (OMAP_REVBITS_02 << 8)) +#define OMAP3430_REV_ES3_0 (OMAP343X_CLASS | (OMAP_REVBITS_03 << 8)) +#define OMAP3430_REV_ES3_1 (OMAP343X_CLASS | (OMAP_REVBITS_04 << 8)) +#define OMAP3430_REV_ES3_1_2 (OMAP343X_CLASS | (OMAP_REVBITS_05 << 8)) + +#define OMAP363X_CLASS 0x36300034 +#define OMAP3630_REV_ES1_0 OMAP363X_CLASS +#define OMAP3630_REV_ES1_1 (OMAP363X_CLASS | (OMAP_REVBITS_01 << 8)) +#define OMAP3630_REV_ES1_2 (OMAP363X_CLASS | (OMAP_REVBITS_02 << 8)) #define OMAP35XX_CLASS 0x35000034 #define OMAP3503_REV(v) (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8)) @@ -390,7 +390,8 @@ IS_OMAP_TYPE(3517, 0x3517) #define OMAP3517_REV(v) (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8)) #define OMAP443X_CLASS 0x44300044 -#define OMAP4430_REV_ES1_0 0x44300044 +#define OMAP4430_REV_ES1_0 OMAP443X_CLASS +#define OMAP4430_REV_ES2_0 0x44301044 /* * omap_chip bits @@ -417,10 +418,12 @@ IS_OMAP_TYPE(3517, 0x3517) #define CHIP_IS_OMAP4430ES1 (1 << 8) #define CHIP_IS_OMAP3630ES1_1 (1 << 9) #define CHIP_IS_OMAP3630ES1_2 (1 << 10) +#define CHIP_IS_OMAP4430ES2 (1 << 11) #define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) -#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1) +#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1 | \ + CHIP_IS_OMAP4430ES2) /* * "GE" here represents "greater than or equal to" in terms of ES diff --git a/arch/arm/plat-omap/include/plat/display.h b/arch/arm/plat-omap/include/plat/display.h index 8bd15bdb4132..c915a661f1f5 100644 --- a/arch/arm/plat-omap/include/plat/display.h +++ b/arch/arm/plat-omap/include/plat/display.h @@ -81,37 +81,6 @@ enum omap_color_mode { OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */ OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */ OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */ - - OMAP_DSS_COLOR_GFX_OMAP2 = - OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 | - OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 | - OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 | - OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P, - - OMAP_DSS_COLOR_VID_OMAP2 = - OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U | - OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 | - OMAP_DSS_COLOR_UYVY, - - OMAP_DSS_COLOR_GFX_OMAP3 = - OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 | - OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 | - OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 | - OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U | - OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 | - OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32, - - OMAP_DSS_COLOR_VID1_OMAP3 = - OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 | - OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P | - OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY, - - OMAP_DSS_COLOR_VID2_OMAP3 = - OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 | - OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U | - OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 | - OMAP_DSS_COLOR_UYVY | OMAP_DSS_COLOR_ARGB32 | - OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32, }; enum omap_lcd_display_type { diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h index af3a03941add..0cce4ca83aa0 100644 --- a/arch/arm/plat-omap/include/plat/dma.h +++ b/arch/arm/plat-omap/include/plat/dma.h @@ -319,6 +319,8 @@ #define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */ #define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */ +#define OMAP36XX_DMA_UART4_TX 81 /* S_DMA_80 */ +#define OMAP36XX_DMA_UART4_RX 82 /* S_DMA_81 */ /*----------------------------------------------------------------------------*/ #define OMAP1_DMA_TOUT_IRQ (1 << 0) @@ -335,6 +337,10 @@ #define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11) #define OMAP_DMA_CCR_EN (1 << 7) +#define OMAP_DMA_CCR_RD_ACTIVE (1 << 9) +#define OMAP_DMA_CCR_WR_ACTIVE (1 << 10) +#define OMAP_DMA_CCR_SEL_SRC_DST_SYNC (1 << 24) +#define OMAP_DMA_CCR_BUFFERING_DISABLE (1 << 25) #define OMAP_DMA_DATA_TYPE_S8 0x00 #define OMAP_DMA_DATA_TYPE_S16 0x01 diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index 20f1054c0a80..dfa3aff9761b 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -45,6 +45,8 @@ #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02 struct omap_dm_timer; +extern struct omap_dm_timer *gptimer_wakeup; +extern struct sys_timer omap_timer; struct clk; int omap_dm_timer_init(void); diff --git a/arch/arm/plat-omap/include/plat/gpmc-smsc911x.h b/arch/arm/plat-omap/include/plat/gpmc-smsc911x.h new file mode 100644 index 000000000000..872de0bf1e6b --- /dev/null +++ b/arch/arm/plat-omap/include/plat/gpmc-smsc911x.h @@ -0,0 +1,35 @@ +/* + * arch/arm/plat-omap/include/plat/gpmc-smsc911x.h + * + * Copyright (C) 2009 Li-Pro.Net + * Stephan Linz <linz@li-pro.net> + * + * Modified from arch/arm/plat-omap/include/plat/gpmc-smc91x.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_OMAP_GPMC_SMSC911X_H__ + +struct omap_smsc911x_platform_data { + int cs; + int gpio_irq; + int gpio_reset; + u32 flags; +}; + +#if defined(CONFIG_SMSC911X) || \ + defined(CONFIG_SMSC911X_MODULE) + +extern void gpmc_smsc911x_init(struct omap_smsc911x_platform_data *d); + +#else + +static inline void gpmc_smsc911x_init(struct omap_smsc911x_platform_data *d) +{ +} + +#endif +#endif diff --git a/arch/arm/plat-omap/include/plat/i2c.h b/arch/arm/plat-omap/include/plat/i2c.h index 87f6bf2ea4fa..36a0befd6168 100644 --- a/arch/arm/plat-omap/include/plat/i2c.h +++ b/arch/arm/plat-omap/include/plat/i2c.h @@ -18,6 +18,8 @@ * 02110-1301 USA * */ +#ifndef __ASM__ARCH_OMAP_I2C_H +#define __ASM__ARCH_OMAP_I2C_H #include <linux/i2c.h> @@ -36,3 +38,5 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate, void __init omap1_i2c_mux_pins(int bus_id); void __init omap2_i2c_mux_pins(int bus_id); + +#endif /* __ASM__ARCH_OMAP_I2C_H */ diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h index c01d9f08a198..65e20a686713 100644 --- a/arch/arm/plat-omap/include/plat/irqs.h +++ b/arch/arm/plat-omap/include/plat/irqs.h @@ -345,6 +345,8 @@ #define INT_34XX_MMC3_IRQ 94 #define INT_34XX_GPT12_IRQ 95 +#define INT_36XX_UART4_IRQ 80 + #define INT_35XX_HECC0_IRQ 24 #define INT_35XX_HECC1_IRQ 28 #define INT_35XX_EMAC_C0_RXTHRESH_IRQ 67 diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h index b4ff6a11a8f2..b87d83ccd545 100644 --- a/arch/arm/plat-omap/include/plat/mcbsp.h +++ b/arch/arm/plat-omap/include/plat/mcbsp.h @@ -30,6 +30,13 @@ #include <mach/hardware.h> #include <plat/clock.h> +/* macro for building platform_device for McBSP ports */ +#define OMAP_MCBSP_PLATFORM_DEVICE(port_nr) \ +static struct platform_device omap_mcbsp##port_nr = { \ + .name = "omap-mcbsp-dai", \ + .id = OMAP_MCBSP##port_nr, \ +} + #define OMAP7XX_MCBSP1_BASE 0xfffb1000 #define OMAP7XX_MCBSP2_BASE 0xfffb1800 @@ -312,6 +319,18 @@ #define RFSREN 0x0002 #define RSYNCERREN 0x0001 +/* CLKR signal muxing options */ +#define CLKR_SRC_CLKR 0 +#define CLKR_SRC_CLKX 1 + +/* FSR signal muxing options */ +#define FSR_SRC_FSR 0 +#define FSR_SRC_FSX 1 + +/* McBSP functional clock sources */ +#define MCBSP_CLKS_PRCM_SRC 0 +#define MCBSP_CLKS_PAD_SRC 1 + /* we don't do multichannel for now */ struct omap_mcbsp_reg_cfg { u16 spcr2; @@ -398,6 +417,7 @@ struct omap_mcbsp_spi_cfg { struct omap_mcbsp_ops { void (*request)(unsigned int); void (*free)(unsigned int); + int (*set_clks_src)(u8, u8); }; struct omap_mcbsp_platform_data { @@ -464,6 +484,9 @@ struct omap_mcbsp { extern struct omap_mcbsp **mcbsp_ptr; extern int omap_mcbsp_count, omap_mcbsp_cache_size; +#define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count) +#define id_to_mcbsp_ptr(id) mcbsp_ptr[id]; + int omap_mcbsp_init(void); void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, int size); @@ -502,6 +525,8 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word); int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word); +/* McBSP functional clock source changing function */ +extern int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id); /* SPI specific API */ void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg); @@ -510,6 +535,10 @@ int omap_mcbsp_pollread(unsigned int id, u16 * buf); int omap_mcbsp_pollwrite(unsigned int id, u16 buf); int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type); +/* McBSP signal muxing API */ +void omap2_mcbsp1_mux_clkr_src(u8 mux); +void omap2_mcbsp1_mux_fsr_src(u8 mux); + #ifdef CONFIG_ARCH_OMAP3 /* Sidetone specific API */ int omap_st_set_chgain(unsigned int id, int channel, s16 chgain); diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h index 9b89ec601ee2..f57f36abb07e 100644 --- a/arch/arm/plat-omap/include/plat/mmc.h +++ b/arch/arm/plat-omap/include/plat/mmc.h @@ -71,12 +71,17 @@ struct omap_mmc_platform_data { u64 dma_mask; + /* Register offset deviation */ + u16 reg_offset; + struct omap_mmc_slot_data { - /* 4 wire signaling is optional, and is used for SD/SDIO/HSMMC; - * 8 wire signaling is also optional, and is used with HSMMC + /* + * 4/8 wires and any additional host capabilities + * need to OR'd all capabilities (ref. linux/mmc/host.h) */ - u8 wires; + u8 wires; /* Used for the MMC driver on omap1 and 2420 */ + u32 caps; /* Used for the MMC driver on 2430 and later */ /* * nomux means "standard" muxing is wrong on this board, and @@ -104,6 +109,7 @@ struct omap_mmc_platform_data { /* we can put the features above into this variable */ #define HSMMC_HAS_PBIAS (1 << 0) +#define HSMMC_HAS_UPDATED_RESET (1 << 1) unsigned features; int switch_pin; /* gpio (card detect) */ diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h new file mode 100644 index 000000000000..c8dae02f0704 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/omap-serial.h @@ -0,0 +1,128 @@ +/* + * Driver for OMAP-UART controller. + * Based on drivers/serial/8250.c + * + * Copyright (C) 2010 Texas Instruments. + * + * Authors: + * Govindraj R <govindraj.raja@ti.com> + * Thara Gopinath <thara@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __OMAP_SERIAL_H__ +#define __OMAP_SERIAL_H__ + +#include <linux/serial_core.h> +#include <linux/platform_device.h> + +#include <plat/mux.h> + +#define DRIVER_NAME "omap-hsuart" + +/* + * Use tty device name as ttyO, [O -> OMAP] + * in bootargs we specify as console=ttyO0 if uart1 + * is used as console uart. + */ +#define OMAP_SERIAL_NAME "ttyO" + +#define OMAP_MDR1_DISABLE 0x07 +#define OMAP_MDR1_MODE13X 0x03 +#define OMAP_MDR1_MODE16X 0x00 +#define OMAP_MODE13X_SPEED 230400 + +/* + * LCR = 0XBF: Switch to Configuration Mode B. + * In configuration mode b allow access + * to EFR,DLL,DLH. + * Reference OMAP TRM Chapter 17 + * Section: 1.4.3 Mode Selection + */ +#define OMAP_UART_LCR_CONF_MDB 0XBF + +/* WER = 0x7F + * Enable module level wakeup in WER reg + */ +#define OMAP_UART_WER_MOD_WKUP 0X7F + +/* Enable XON/XOFF flow control on output */ +#define OMAP_UART_SW_TX 0x04 + +/* Enable XON/XOFF flow control on input */ +#define OMAP_UART_SW_RX 0x04 + +#define OMAP_UART_SYSC_RESET 0X07 +#define OMAP_UART_TCR_TRIG 0X0F +#define OMAP_UART_SW_CLR 0XF0 +#define OMAP_UART_FIFO_CLR 0X06 + +#define OMAP_UART_DMA_CH_FREE -1 + +#define RX_TIMEOUT (3 * HZ) +#define OMAP_MAX_HSUART_PORTS 4 + +#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA + +struct omap_uart_port_info { + bool dma_enabled; /* To specify DMA Mode */ + unsigned int uartclk; /* UART clock rate */ + void __iomem *membase; /* ioremap cookie or NULL */ + resource_size_t mapbase; /* resource base */ + unsigned long irqflags; /* request_irq flags */ + upf_t flags; /* UPF_* flags */ +}; + +struct uart_omap_dma { + u8 uart_dma_tx; + u8 uart_dma_rx; + int rx_dma_channel; + int tx_dma_channel; + dma_addr_t rx_buf_dma_phys; + dma_addr_t tx_buf_dma_phys; + unsigned int uart_base; + /* + * Buffer for rx dma.It is not required for tx because the buffer + * comes from port structure. + */ + unsigned char *rx_buf; + unsigned int prev_rx_dma_pos; + int tx_buf_size; + int tx_dma_used; + int rx_dma_used; + spinlock_t tx_lock; + spinlock_t rx_lock; + /* timer to poll activity on rx dma */ + struct timer_list rx_timer; + int rx_buf_size; + int rx_timeout; +}; + +struct uart_omap_port { + struct uart_port port; + struct uart_omap_dma uart_dma; + struct platform_device *pdev; + + unsigned char ier; + unsigned char lcr; + unsigned char mcr; + unsigned char fcr; + unsigned char efr; + + int use_dma; + /* + * Some bits in registers are cleared on a read, so they must + * be saved whenever the register is read but the bits will not + * be immediately processed. + */ + unsigned int lsr_break_flag; + unsigned char msr_saved_flags; + char name[20]; + unsigned long port_activity; +}; + +#endif /* __OMAP_SERIAL_H__ */ diff --git a/arch/arm/plat-omap/include/plat/omap24xx.h b/arch/arm/plat-omap/include/plat/omap24xx.h index 7055672a8c68..92df9e27cc5c 100644 --- a/arch/arm/plat-omap/include/plat/omap24xx.h +++ b/arch/arm/plat-omap/include/plat/omap24xx.h @@ -40,7 +40,7 @@ #define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000) #define OMAP24XX_IVA_INTC_BASE 0x40000000 -#define OMAP2420_CTRL_BASE L4_24XX_BASE +#define OMAP242X_CTRL_BASE L4_24XX_BASE #define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000) #define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000) #define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000) diff --git a/arch/arm/plat-omap/include/plat/omap4-keypad.h b/arch/arm/plat-omap/include/plat/omap4-keypad.h new file mode 100644 index 000000000000..2b1d9bc1eebb --- /dev/null +++ b/arch/arm/plat-omap/include/plat/omap4-keypad.h @@ -0,0 +1,14 @@ +#ifndef ARCH_ARM_PLAT_OMAP4_KEYPAD_H +#define ARCH_ARM_PLAT_OMAP4_KEYPAD_H + +#include <linux/input/matrix_keypad.h> + +struct omap4_keypad_platform_data { + const struct matrix_keymap_data *keymap_data; + + u8 rows; + u8 cols; +}; + +extern int omap4_keyboard_init(struct omap4_keypad_platform_data *); +#endif diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h index 25cd9ac3b095..28e2d1a78433 100644 --- a/arch/arm/plat-omap/include/plat/omap_device.h +++ b/arch/arm/plat-omap/include/plat/omap_device.h @@ -36,6 +36,8 @@ #include <plat/omap_hwmod.h> +extern struct device omap_device_parent; + /* omap_device._state values */ #define OMAP_DEVICE_STATE_UNKNOWN 0 #define OMAP_DEVICE_STATE_ENABLED 1 @@ -62,7 +64,6 @@ * */ struct omap_device { - u32 magic; struct platform_device pdev; struct omap_hwmod **hwmods; struct omap_device_pm_latency *pm_lats; @@ -82,7 +83,6 @@ int omap_device_shutdown(struct platform_device *pdev); /* Core code interface */ -bool omap_device_is_valid(struct omap_device *od); int omap_device_count_resources(struct omap_device *od); int omap_device_fill_resources(struct omap_device *od, struct resource *res); diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index a4e508dfaba2..7eaa8edf3b14 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -14,19 +14,16 @@ * * These headers and macros are used to define OMAP on-chip module * data and their integration with other OMAP modules and Linux. - * - * References: - * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064) - * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090) - * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108) - * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140) - * - Open Core Protocol Specification 2.2 + * Copious documentation and references can also be found in the + * omap_hwmod code, in arch/arm/mach-omap2/omap_hwmod.c (as of this + * writing). * * To do: * - add interconnect error log structures * - add pinmuxing * - init_conn_id_bit (CONNID_BIT_VECTOR) * - implement default hwmod SMS/SDRC flags? + * - remove unused fields * */ #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H @@ -35,6 +32,7 @@ #include <linux/kernel.h> #include <linux/list.h> #include <linux/ioport.h> +#include <linux/mutex.h> #include <plat/cpu.h> struct omap_device; @@ -96,7 +94,7 @@ struct omap_hwmod_irq_info { /** * struct omap_hwmod_dma_info - DMA channels used by the hwmod * @name: name of the DMA channel (module local name) - * @dma_ch: DMA channel ID + * @dma_req: DMA request ID * * @name should be something short, e.g., "tx" or "rx". It is for use * by platform_get_resource_byname(). It is defined locally to the @@ -104,7 +102,20 @@ struct omap_hwmod_irq_info { */ struct omap_hwmod_dma_info { const char *name; - u16 dma_ch; + u16 dma_req; +}; + +/** + * struct omap_hwmod_rst_info - IPs reset lines use by hwmod + * @name: name of the reset line (module local name) + * @rst_shift: Offset of the reset bit + * + * @name should be something short, e.g., "cpu0" or "rst". It is defined + * locally to the hwmod. + */ +struct omap_hwmod_rst_info { + const char *name; + u8 rst_shift; }; /** @@ -237,8 +248,9 @@ struct omap_hwmod_ocp_if { #define SYSC_HAS_CLOCKACTIVITY (1 << 4) #define SYSC_HAS_SIDLEMODE (1 << 5) #define SYSC_HAS_MIDLEMODE (1 << 6) -#define SYSS_MISSING (1 << 7) +#define SYSS_HAS_RESET_STATUS (1 << 7) #define SYSC_NO_CACHE (1 << 8) /* XXX SW flag, belongs elsewhere */ +#define SYSC_HAS_RESET_STATUS (1 << 9) /* omap_hwmod_sysconfig.clockact flags */ #define CLOCKACT_TEST_BOTH 0x0 @@ -327,10 +339,12 @@ struct omap_hwmod_omap2_prcm { /** * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data * @clkctrl_reg: PRCM address of the clock control register + * @rstctrl_reg: adress of the XXX_RSTCTRL register located in the PRM * @submodule_wkdep_bit: bit shift of the WKDEP range */ struct omap_hwmod_omap4_prcm { void __iomem *clkctrl_reg; + void __iomem *rstctrl_reg; u8 submodule_wkdep_bit; }; @@ -352,6 +366,11 @@ struct omap_hwmod_omap4_prcm { * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup * HWMOD_NO_IDLEST : this module does not have idle status - this is the case * only for few initiator modules on OMAP2 & 3. + * HWMOD_CONTROL_OPT_CLKS_IN_RESET: Enable all optional clocks during reset. + * This is needed for devices like DSS that require optional clocks enabled + * in order to complete the reset. Optional clocks will be disabled + * again after the reset. + * HWMOD_16BIT_REG: Module has 16bit registers */ #define HWMOD_SWSUP_SIDLE (1 << 0) #define HWMOD_SWSUP_MSTANDBY (1 << 1) @@ -360,6 +379,8 @@ struct omap_hwmod_omap4_prcm { #define HWMOD_NO_OCP_AUTOIDLE (1 << 4) #define HWMOD_SET_DEFAULT_CLOCKACT (1 << 5) #define HWMOD_NO_IDLEST (1 << 6) +#define HWMOD_CONTROL_OPT_CLKS_IN_RESET (1 << 7) +#define HWMOD_16BIT_REG (1 << 8) /* * omap_hwmod._int_flags definitions @@ -410,7 +431,7 @@ struct omap_hwmod_class { * @class: struct omap_hwmod_class * to the class of this hwmod * @od: struct omap_device currently associated with this hwmod (internal use) * @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt) - * @sdma_chs: ptr to an array of SDMA channel IDs (see also sdma_chs_cnt) + * @sdma_reqs: ptr to an array of System DMA request IDs (see sdma_reqs_cnt) * @prcm: PRCM data pertaining to this hwmod * @main_clk: main clock: OMAP clock name * @_clk: pointer to the main struct clk (filled in at runtime) @@ -424,7 +445,7 @@ struct omap_hwmod_class { * @msuspendmux_reg_id: CONTROL_MSUSPENDMUX register ID (1-6) * @msuspendmux_shift: CONTROL_MSUSPENDMUX register bit shift * @mpu_irqs_cnt: number of @mpu_irqs - * @sdma_chs_cnt: number of @sdma_chs + * @sdma_reqs_cnt: number of @sdma_reqs * @opt_clks_cnt: number of @opt_clks * @master_cnt: number of @master entries * @slaves_cnt: number of @slave entries @@ -433,6 +454,7 @@ struct omap_hwmod_class { * @_state: internal-use hwmod state * @flags: hwmod flags (documented below) * @omap_chip: OMAP chips this hwmod is present on + * @_mutex: mutex serializing operations on this hwmod * @node: list node for hwmod list (internal use) * * @main_clk refers to this module's "main clock," which for our @@ -448,7 +470,8 @@ struct omap_hwmod { struct omap_hwmod_class *class; struct omap_device *od; struct omap_hwmod_irq_info *mpu_irqs; - struct omap_hwmod_dma_info *sdma_chs; + struct omap_hwmod_dma_info *sdma_reqs; + struct omap_hwmod_rst_info *rst_lines; union { struct omap_hwmod_omap2_prcm omap2; struct omap_hwmod_omap4_prcm omap4; @@ -461,6 +484,7 @@ struct omap_hwmod { void *dev_attr; u32 _sysc_cache; void __iomem *_mpu_rt_va; + struct mutex _mutex; struct list_head node; u16 flags; u8 _mpu_port_index; @@ -468,7 +492,8 @@ struct omap_hwmod { u8 msuspendmux_shift; u8 response_lat; u8 mpu_irqs_cnt; - u8 sdma_chs_cnt; + u8 sdma_reqs_cnt; + u8 rst_lines_cnt; u8 opt_clks_cnt; u8 masters_cnt; u8 slaves_cnt; @@ -492,6 +517,10 @@ int omap_hwmod_idle(struct omap_hwmod *oh); int _omap_hwmod_idle(struct omap_hwmod *oh); int omap_hwmod_shutdown(struct omap_hwmod *oh); +int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name); +int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name); +int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name); + int omap_hwmod_enable_clocks(struct omap_hwmod *oh); int omap_hwmod_disable_clocks(struct omap_hwmod *oh); @@ -500,8 +529,8 @@ int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode); int omap_hwmod_reset(struct omap_hwmod *oh); void omap_hwmod_ocp_barrier(struct omap_hwmod *oh); -void omap_hwmod_writel(u32 v, struct omap_hwmod *oh, u16 reg_offs); -u32 omap_hwmod_readl(struct omap_hwmod *oh, u16 reg_offs); +void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs); +u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs); int omap_hwmod_count_resources(struct omap_hwmod *oh); int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res); @@ -534,5 +563,6 @@ int omap_hwmod_for_each_by_class(const char *classname, extern int omap2420_hwmod_init(void); extern int omap2430_hwmod_init(void); extern int omap3xxx_hwmod_init(void); +extern int omap44xx_hwmod_init(void); #endif diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h index fb6ec74fe39e..9ca420dcd2f8 100644 --- a/arch/arm/plat-omap/include/plat/powerdomain.h +++ b/arch/arm/plat-omap/include/plat/powerdomain.h @@ -32,6 +32,7 @@ /* Powerdomain allowable state bitfields */ #define PWRSTS_ON (1 << PWRDM_POWER_ON) +#define PWRSTS_OFF (1 << PWRDM_POWER_OFF) #define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \ (1 << PWRDM_POWER_ON)) @@ -161,5 +162,6 @@ int pwrdm_state_switch(struct powerdomain *pwrdm); int pwrdm_clkdm_state_switch(struct clockdomain *clkdm); int pwrdm_pre_transition(void); int pwrdm_post_transition(void); +int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm); #endif diff --git a/arch/arm/plat-omap/include/plat/prcm.h b/arch/arm/plat-omap/include/plat/prcm.h index 9fbd91419cd1..ab77442e42ab 100644 --- a/arch/arm/plat-omap/include/plat/prcm.h +++ b/arch/arm/plat-omap/include/plat/prcm.h @@ -38,6 +38,8 @@ u32 prm_read_mod_reg(s16 module, u16 idx); void prm_write_mod_reg(u32 val, s16 module, u16 idx); u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask); +u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask); +u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg); u32 cm_read_mod_reg(s16 module, u16 idx); void cm_write_mod_reg(u32 val, s16 module, u16 idx); u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); diff --git a/arch/arm/plat-omap/include/plat/sdrc.h b/arch/arm/plat-omap/include/plat/sdrc.h index 7b76f50564ba..efd87c8dda69 100644 --- a/arch/arm/plat-omap/include/plat/sdrc.h +++ b/arch/arm/plat-omap/include/plat/sdrc.h @@ -147,6 +147,7 @@ struct memory_timings { }; extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode); +struct omap_sdrc_params *rx51_get_sdram_timings(void); u32 omap2xxx_sdrc_dll_is_unlocked(void); u32 omap2xxx_sdrc_reprogram(u32 level, u32 force); diff --git a/arch/arm/plat-omap/include/plat/sram.h b/arch/arm/plat-omap/include/plat/sram.h index 16a1b458d53c..5905100b29a1 100644 --- a/arch/arm/plat-omap/include/plat/sram.h +++ b/arch/arm/plat-omap/include/plat/sram.h @@ -11,7 +11,6 @@ #ifndef __ARCH_ARM_OMAP_SRAM_H #define __ARCH_ARM_OMAP_SRAM_H -extern int __init omap_sram_init(void); extern void * omap_sram_push(void * start, unsigned long size); extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl); diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h index ddf723be48dc..9036e374e0ac 100644 --- a/arch/arm/plat-omap/include/plat/uncompress.h +++ b/arch/arm/plat-omap/include/plat/uncompress.h @@ -139,10 +139,14 @@ static inline void __arch_decomp_setup(unsigned long arch_id) DEBUG_LL_OMAP2(1, omap3evm); DEBUG_LL_OMAP3(1, omap_3430sdp); DEBUG_LL_OMAP3(1, omap_3630sdp); + DEBUG_LL_OMAP3(1, omap3530_lv_som); + DEBUG_LL_OMAP3(1, omap3_torpedo); /* omap3 based boards using UART3 */ DEBUG_LL_OMAP3(3, cm_t35); + DEBUG_LL_OMAP3(3, cm_t3517); DEBUG_LL_OMAP3(3, igep0020); + DEBUG_LL_OMAP3(3, igep0030); DEBUG_LL_OMAP3(3, nokia_rx51); DEBUG_LL_OMAP3(3, omap3517evm); DEBUG_LL_OMAP3(3, omap3_beagle); @@ -153,6 +157,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id) /* omap4 based boards using UART3 */ DEBUG_LL_OMAP4(3, omap_4430sdp); + DEBUG_LL_OMAP4(3, omap4_panda); /* zoom2/3 external uart */ DEBUG_LL_ZOOM(omap_zoom2); diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h index 2a9427c8cc48..59c7fe731f28 100644 --- a/arch/arm/plat-omap/include/plat/usb.h +++ b/arch/arm/plat-omap/include/plat/usb.h @@ -105,7 +105,7 @@ static inline void omap1_usb_init(struct omap_usb_config *pdata) #if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP_OTG_MODULE) void omap2_usbfs_init(struct omap_usb_config *pdata); #else -static inline omap2_usbfs_init(struct omap_usb_config *pdata) +static inline void omap2_usbfs_init(struct omap_usb_config *pdata) { } #endif @@ -218,6 +218,27 @@ static inline omap2_usbfs_init(struct omap_usb_config *pdata) # define USBT2TLL5PI (1 << 17) # define USB0PUENACTLOI (1 << 16) # define USBSTANDBYCTRL (1 << 15) +/* AM35x */ +/* USB 2.0 PHY Control */ +#define CONF2_PHY_GPIOMODE (1 << 23) +#define CONF2_OTGMODE (3 << 14) +#define CONF2_NO_OVERRIDE (0 << 14) +#define CONF2_FORCE_HOST (1 << 14) +#define CONF2_FORCE_DEVICE (2 << 14) +#define CONF2_FORCE_HOST_VBUS_LOW (3 << 14) +#define CONF2_SESENDEN (1 << 13) +#define CONF2_VBDTCTEN (1 << 12) +#define CONF2_REFFREQ_24MHZ (2 << 8) +#define CONF2_REFFREQ_26MHZ (7 << 8) +#define CONF2_REFFREQ_13MHZ (6 << 8) +#define CONF2_REFFREQ (0xf << 8) +#define CONF2_PHYCLKGD (1 << 7) +#define CONF2_VBUSSENSE (1 << 6) +#define CONF2_PHY_PLLON (1 << 5) +#define CONF2_RESET (1 << 4) +#define CONF2_PHYPWRDN (1 << 3) +#define CONF2_OTGPWRDN (1 << 2) +#define CONF2_DATPOL (1 << 1) #if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_USB) u32 omap1_usb0_init(unsigned nwires, unsigned is_device); diff --git a/arch/arm/plat-omap/include/plat/vrfb.h b/arch/arm/plat-omap/include/plat/vrfb.h index d8a03ced3b10..3792bdea2f6d 100644 --- a/arch/arm/plat-omap/include/plat/vrfb.h +++ b/arch/arm/plat-omap/include/plat/vrfb.h @@ -35,6 +35,7 @@ struct vrfb { bool yuv_mode; }; +#ifdef CONFIG_OMAP2_VRFB extern int omap_vrfb_request_ctx(struct vrfb *vrfb); extern void omap_vrfb_release_ctx(struct vrfb *vrfb); extern void omap_vrfb_adjust_size(u16 *width, u16 *height, @@ -47,4 +48,19 @@ extern void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr, extern int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot); extern void omap_vrfb_restore_context(void); +#else +static inline int omap_vrfb_request_ctx(struct vrfb *vrfb) { return 0; } +static inline void omap_vrfb_release_ctx(struct vrfb *vrfb) {} +static inline void omap_vrfb_adjust_size(u16 *width, u16 *height, + u8 bytespp) {} +static inline u32 omap_vrfb_min_phys_size(u16 width, u16 height, u8 bytespp) + { return 0; } +static inline u16 omap_vrfb_max_height(u32 phys_size, u16 width, u8 bytespp) + { return 0; } +static inline void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr, + u16 width, u16 height, unsigned bytespp, bool yuv_mode) {} +static inline int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot) + { return 0; } +static inline void omap_vrfb_restore_context(void) {} +#endif #endif /* __VRFB_H */ diff --git a/arch/arm/plat-omap/iommu-debug.c b/arch/arm/plat-omap/iommu-debug.c index e6c0d536899c..f07cf2f08e09 100644 --- a/arch/arm/plat-omap/iommu-debug.c +++ b/arch/arm/plat-omap/iommu-debug.c @@ -328,12 +328,14 @@ static int debug_open_generic(struct inode *inode, struct file *file) .open = debug_open_generic, \ .read = debug_read_##name, \ .write = debug_write_##name, \ + .llseek = generic_file_llseek, \ }; #define DEBUG_FOPS_RO(name) \ static const struct file_operations debug_##name##_fops = { \ .open = debug_open_generic, \ .read = debug_read_##name, \ + .llseek = generic_file_llseek, \ }; DEBUG_FOPS_RO(ver); diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index 0c8612fd8312..eac4b978e9fd 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c @@ -33,7 +33,7 @@ struct omap_mcbsp **mcbsp_ptr; int omap_mcbsp_count, omap_mcbsp_cache_size; -void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) +static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) { if (cpu_class_is_omap1()) { ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)] = (u16)val; @@ -47,7 +47,7 @@ void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) } } -int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache) +static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache) { if (cpu_class_is_omap1()) { return !from_cache ? __raw_readw(mcbsp->io_base + reg) : @@ -62,12 +62,12 @@ int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache) } #ifdef CONFIG_ARCH_OMAP3 -void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) +static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) { __raw_writel(val, mcbsp->st_data->io_base_st + reg); } -int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg) +static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg) { return __raw_readl(mcbsp->st_data->io_base_st + reg); } @@ -80,9 +80,6 @@ int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg) #define MCBSP_READ_CACHE(mcbsp, reg) \ omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1) -#define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count) -#define id_to_mcbsp_ptr(id) mcbsp_ptr[id]; - #define MCBSP_ST_READ(mcbsp, reg) \ omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg) #define MCBSP_ST_WRITE(mcbsp, reg, val) \ @@ -878,7 +875,7 @@ EXPORT_SYMBOL(omap_mcbsp_free); void omap_mcbsp_start(unsigned int id, int tx, int rx) { struct omap_mcbsp *mcbsp; - int idle; + int enable_srg = 0; u16 w; if (!omap_mcbsp_check_valid_id(id)) { @@ -893,10 +890,13 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx) mcbsp->rx_word_length = (MCBSP_READ_CACHE(mcbsp, RCR1) >> 5) & 0x7; mcbsp->tx_word_length = (MCBSP_READ_CACHE(mcbsp, XCR1) >> 5) & 0x7; - idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) | - MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1); + /* Only enable SRG, if McBSP is master */ + w = MCBSP_READ_CACHE(mcbsp, PCR0); + if (w & (FSXM | FSRM | CLKXM | CLKRM)) + enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) | + MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1); - if (idle) { + if (enable_srg) { /* Start the sample generator */ w = MCBSP_READ_CACHE(mcbsp, SPCR2); MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6)); @@ -919,7 +919,7 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx) */ udelay(500); - if (idle) { + if (enable_srg) { /* Start frame sync */ w = MCBSP_READ_CACHE(mcbsp, SPCR2); MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7)); @@ -1645,7 +1645,7 @@ static const struct attribute_group sidetone_attr_group = { .attrs = (struct attribute **)sidetone_attrs, }; -int __devinit omap_st_add(struct omap_mcbsp *mcbsp) +static int __devinit omap_st_add(struct omap_mcbsp *mcbsp) { struct omap_mcbsp_platform_data *pdata = mcbsp->pdata; struct omap_mcbsp_st_data *st_data; diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c index d2b160942ccc..abe933cd8f09 100644 --- a/arch/arm/plat-omap/omap_device.c +++ b/arch/arm/plat-omap/omap_device.c @@ -82,6 +82,7 @@ #include <linux/slab.h> #include <linux/err.h> #include <linux/io.h> +#include <linux/clk.h> #include <plat/omap_device.h> #include <plat/omap_hwmod.h> @@ -90,12 +91,6 @@ #define USE_WAKEUP_LAT 0 #define IGNORE_WAKEUP_LAT 1 -/* - * OMAP_DEVICE_MAGIC: used to determine whether a struct omap_device - * obtained via container_of() is in fact a struct omap_device - */ -#define OMAP_DEVICE_MAGIC 0xf00dcafe - /* Private functions */ /** @@ -243,6 +238,44 @@ static inline struct omap_device *_find_by_pdev(struct platform_device *pdev) return container_of(pdev, struct omap_device, pdev); } +/** + * _add_optional_clock_alias - Add clock alias for hwmod optional clocks + * @od: struct omap_device *od + * + * For every optional clock present per hwmod per omap_device, this function + * adds an entry in the clocks list of the form <dev-id=dev_name, con-id=role> + * if an entry is already present in it with the form <dev-id=NULL, con-id=role> + * + * The function is called from inside omap_device_build_ss(), after + * omap_device_register. + * + * This allows drivers to get a pointer to its optional clocks based on its role + * by calling clk_get(<dev*>, <role>). + * + * No return value. + */ +static void _add_optional_clock_alias(struct omap_device *od, + struct omap_hwmod *oh) +{ + int i; + + for (i = 0; i < oh->opt_clks_cnt; i++) { + struct omap_hwmod_opt_clk *oc; + int r; + + oc = &oh->opt_clks[i]; + + if (!oc->_clk) + continue; + + r = clk_add_alias(oc->role, dev_name(&od->pdev.dev), + (char *)oc->clk, &od->pdev.dev); + if (r) + pr_err("omap_device: %s: clk_add_alias for %s failed\n", + dev_name(&od->pdev.dev), oc->role); + } +} + /* Public functions for use by core code */ @@ -257,12 +290,11 @@ static inline struct omap_device *_find_by_pdev(struct platform_device *pdev) */ int omap_device_count_resources(struct omap_device *od) { - struct omap_hwmod *oh; int c = 0; int i; - for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) - c += omap_hwmod_count_resources(oh); + for (i = 0; i < od->hwmods_cnt; i++) + c += omap_hwmod_count_resources(od->hwmods[i]); pr_debug("omap_device: %s: counted %d total resources across %d " "hwmods\n", od->pdev.name, c, od->hwmods_cnt); @@ -289,12 +321,11 @@ int omap_device_count_resources(struct omap_device *od) */ int omap_device_fill_resources(struct omap_device *od, struct resource *res) { - struct omap_hwmod *oh; int c = 0; int i, r; - for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) { - r = omap_hwmod_fill_resources(oh, res); + for (i = 0; i < od->hwmods_cnt; i++) { + r = omap_hwmod_fill_resources(od->hwmods[i], res); res += r; c += r; } @@ -414,15 +445,15 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id, od->pm_lats = pm_lats; od->pm_lats_cnt = pm_lats_cnt; - od->magic = OMAP_DEVICE_MAGIC; - if (is_early_device) ret = omap_early_device_register(od); else ret = omap_device_register(od); - for (i = 0; i < oh_cnt; i++) + for (i = 0; i < oh_cnt; i++) { hwmods[i]->od = od; + _add_optional_clock_alias(od, hwmods[i]); + } if (ret) goto odbs_exit4; @@ -473,6 +504,7 @@ int omap_device_register(struct omap_device *od) { pr_debug("omap_device: %s: registering\n", od->pdev.name); + od->pdev.dev.parent = &omap_device_parent; return platform_device_register(&od->pdev); } @@ -566,7 +598,6 @@ int omap_device_shutdown(struct platform_device *pdev) { int ret, i; struct omap_device *od; - struct omap_hwmod *oh; od = _find_by_pdev(pdev); @@ -579,8 +610,8 @@ int omap_device_shutdown(struct platform_device *pdev) ret = _omap_device_deactivate(od, IGNORE_WAKEUP_LAT); - for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) - omap_hwmod_shutdown(oh); + for (i = 0; i < od->hwmods_cnt; i++) + omap_hwmod_shutdown(od->hwmods[i]); od->_state = OMAP_DEVICE_STATE_SHUTDOWN; @@ -627,18 +658,6 @@ int omap_device_align_pm_lat(struct platform_device *pdev, } /** - * omap_device_is_valid - Check if pointer is a valid omap_device - * @od: struct omap_device * - * - * Return whether struct omap_device pointer @od points to a valid - * omap_device. - */ -bool omap_device_is_valid(struct omap_device *od) -{ - return (od && od->magic == OMAP_DEVICE_MAGIC); -} - -/** * omap_device_get_pwrdm - return the powerdomain * associated with @od * @od: struct omap_device * * @@ -692,11 +711,10 @@ void __iomem *omap_device_get_rt_va(struct omap_device *od) */ int omap_device_enable_hwmods(struct omap_device *od) { - struct omap_hwmod *oh; int i; - for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) - omap_hwmod_enable(oh); + for (i = 0; i < od->hwmods_cnt; i++) + omap_hwmod_enable(od->hwmods[i]); /* XXX pass along return value here? */ return 0; @@ -710,11 +728,10 @@ int omap_device_enable_hwmods(struct omap_device *od) */ int omap_device_idle_hwmods(struct omap_device *od) { - struct omap_hwmod *oh; int i; - for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) - omap_hwmod_idle(oh); + for (i = 0; i < od->hwmods_cnt; i++) + omap_hwmod_idle(od->hwmods[i]); /* XXX pass along return value here? */ return 0; @@ -729,11 +746,10 @@ int omap_device_idle_hwmods(struct omap_device *od) */ int omap_device_disable_clocks(struct omap_device *od) { - struct omap_hwmod *oh; int i; - for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) - omap_hwmod_disable_clocks(oh); + for (i = 0; i < od->hwmods_cnt; i++) + omap_hwmod_disable_clocks(od->hwmods[i]); /* XXX pass along return value here? */ return 0; @@ -748,12 +764,22 @@ int omap_device_disable_clocks(struct omap_device *od) */ int omap_device_enable_clocks(struct omap_device *od) { - struct omap_hwmod *oh; int i; - for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) - omap_hwmod_enable_clocks(oh); + for (i = 0; i < od->hwmods_cnt; i++) + omap_hwmod_enable_clocks(od->hwmods[i]); /* XXX pass along return value here? */ return 0; } + +struct device omap_device_parent = { + .init_name = "omap", + .parent = &platform_bus, +}; + +static int __init omap_device_init(void) +{ + return device_register(&omap_device_parent); +} +core_initcall(omap_device_init); diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index 10b3b4c63372..e2c8eebe6b3a 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -19,6 +19,7 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/io.h> +#include <linux/omapfb.h> #include <asm/tlb.h> #include <asm/cacheflush.h> @@ -30,8 +31,8 @@ #include <plat/cpu.h> #include <plat/vram.h> -#include <plat/control.h> - +#include "sram.h" +#include "fb.h" #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) # include "../mach-omap2/prm.h" # include "../mach-omap2/cm.h" @@ -53,7 +54,7 @@ #define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000) #define OMAP4_SRAM_PUB_VA (OMAP4_SRAM_VA + 0x4000) -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) +#if defined(CONFIG_ARCH_OMAP2PLUS) #define SRAM_BOOTLOADER_SZ 0x00 #else #define SRAM_BOOTLOADER_SZ 0x80 @@ -68,7 +69,6 @@ #define OMAP34XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68012858) #define OMAP34XX_VA_ADDR_MATCH2 OMAP2_L3_IO_ADDRESS(0x68012880) #define OMAP34XX_VA_SMS_RG_ATT0 OMAP2_L3_IO_ADDRESS(0x6C000048) -#define OMAP34XX_VA_CONTROL_STAT OMAP2_L4_IO_ADDRESS(0x480022F0) #define GP_DEVICE 0x300 @@ -79,12 +79,6 @@ static unsigned long omap_sram_base; static unsigned long omap_sram_size; static unsigned long omap_sram_ceil; -extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart, - unsigned long sram_vstart, - unsigned long sram_size, - unsigned long pstart_avail, - unsigned long size_avail); - /* * Depending on the target RAMFS firewall setup, the public usable amount of * SRAM varies. The default accessible size for all device types is 2k. A GP @@ -93,16 +87,7 @@ extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart, */ static int is_sram_locked(void) { - int type = 0; - - if (cpu_is_omap44xx()) - /* Not yet supported */ - return 0; - - if (cpu_is_omap242x()) - type = omap_rev() & OMAP2_DEVICETYPE_MASK; - - if (type == GP_DEVICE) { + if (OMAP2_DEVICE_TYPE_GP == omap_type()) { /* RAMFW: R/W access to all initiators for all qualifier sets */ if (cpu_is_omap242x()) { __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */ @@ -127,7 +112,7 @@ static int is_sram_locked(void) * to secure SRAM will hang the system. Also the SRAM is not * yet mapped at this point. */ -void __init omap_detect_sram(void) +static void __init omap_detect_sram(void) { unsigned long reserved; @@ -213,7 +198,7 @@ static struct map_desc omap_sram_io_desc[] __initdata = { /* * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early. */ -void __init omap_map_sram(void) +static void __init omap_map_sram(void) { unsigned long base; @@ -330,7 +315,7 @@ u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass) #endif #ifdef CONFIG_ARCH_OMAP2420 -int __init omap242x_sram_init(void) +static int __init omap242x_sram_init(void) { _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init, omap242x_sram_ddr_init_sz); @@ -351,7 +336,7 @@ static inline int omap242x_sram_init(void) #endif #ifdef CONFIG_ARCH_OMAP2430 -int __init omap243x_sram_init(void) +static int __init omap243x_sram_init(void) { _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init, omap243x_sram_ddr_init_sz); @@ -407,7 +392,7 @@ void omap3_sram_restore_context(void) } #endif /* CONFIG_PM */ -int __init omap34xx_sram_init(void) +static int __init omap34xx_sram_init(void) { _omap3_sram_configure_core_dpll = omap_sram_push(omap3_sram_configure_core_dpll, @@ -423,7 +408,7 @@ static inline int omap34xx_sram_init(void) #endif #ifdef CONFIG_ARCH_OMAP4 -int __init omap44xx_sram_init(void) +static int __init omap44xx_sram_init(void) { printk(KERN_ERR "FIXME: %s not implemented\n", __func__); diff --git a/arch/arm/plat-omap/sram.h b/arch/arm/plat-omap/sram.h new file mode 100644 index 000000000000..29b43ef97f20 --- /dev/null +++ b/arch/arm/plat-omap/sram.h @@ -0,0 +1,6 @@ +#ifndef __PLAT_OMAP_SRAM_H__ +#define __PLAT_OMAP_SRAM_H__ + +extern int __init omap_sram_init(void); + +#endif /* __PLAT_OMAP_SRAM_H__ */ diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c index 452e18438b41..2f91057a0c02 100644 --- a/arch/arm/plat-s3c24xx/devs.c +++ b/arch/arm/plat-s3c24xx/devs.c @@ -247,7 +247,7 @@ static struct resource s3c_iis_resource[] = { static u64 s3c_device_iis_dmamask = 0xffffffffUL; struct platform_device s3c_device_iis = { - .name = "s3c2410-iis", + .name = "s3c24xx-iis", .id = -1, .num_resources = ARRAY_SIZE(s3c_iis_resource), .resource = s3c_iis_resource, @@ -259,6 +259,21 @@ struct platform_device s3c_device_iis = { EXPORT_SYMBOL(s3c_device_iis); +/* ASoC PCM DMA */ + +static u64 s3c_device_audio_dmamask = 0xffffffffUL; + +struct platform_device s3c_device_pcm = { + .name = "s3c24xx-pcm-audio", + .id = -1, + .dev = { + .dma_mask = &s3c_device_audio_dmamask, + .coherent_dma_mask = 0xffffffffUL + } +}; + +EXPORT_SYMBOL(s3c_device_pcm); + /* RTC */ static struct resource s3c_rtc_resource[] = { @@ -481,19 +496,30 @@ static struct resource s3c_ac97_resource[] = { }, }; -static u64 s3c_device_ac97_dmamask = 0xffffffffUL; - struct platform_device s3c_device_ac97 = { .name = "s3c-ac97", .id = -1, .num_resources = ARRAY_SIZE(s3c_ac97_resource), .resource = s3c_ac97_resource, .dev = { - .dma_mask = &s3c_device_ac97_dmamask, + .dma_mask = &s3c_device_audio_dmamask, .coherent_dma_mask = 0xffffffffUL } }; EXPORT_SYMBOL(s3c_device_ac97); +/* ASoC I2S */ + +struct platform_device s3c2412_device_iis = { + .name = "s3c2412-iis", + .id = -1, + .dev = { + .dma_mask = &s3c_device_audio_dmamask, + .coherent_dma_mask = 0xffffffffUL + } +}; + +EXPORT_SYMBOL(s3c2412_device_iis); + #endif // CONFIG_CPU_S32440 diff --git a/arch/arm/plat-samsung/include/plat/adc.h b/arch/arm/plat-samsung/include/plat/adc.h index e8382c7be10b..b258a08de591 100644 --- a/arch/arm/plat-samsung/include/plat/adc.h +++ b/arch/arm/plat-samsung/include/plat/adc.h @@ -1,7 +1,7 @@ /* arch/arm/plat-samsung/include/plat/adc.h * * Copyright (c) 2008 Simtec Electronics - * http://armlinux.simnte.co.uk/ + * http://armlinux.simtec.co.uk/ * Ben Dooks <ben@simtec.co.uk> * * S3C ADC driver information diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h index 7d448e138792..c8b94279bad1 100644 --- a/arch/arm/plat-samsung/include/plat/devs.h +++ b/arch/arm/plat-samsung/include/plat/devs.h @@ -32,6 +32,8 @@ extern struct platform_device s3c64xx_device_iisv4; extern struct platform_device s3c64xx_device_spi0; extern struct platform_device s3c64xx_device_spi1; +extern struct platform_device s3c_device_pcm; + extern struct platform_device s3c64xx_device_pcm0; extern struct platform_device s3c64xx_device_pcm1; |