diff options
Diffstat (limited to 'arch/arm')
164 files changed, 6301 insertions, 923 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 50d9f3e4e0f1..85016313bd11 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -241,6 +241,9 @@ config ARCH_H720X config ARCH_IMX bool "IMX" + select GENERIC_GPIO + select GENERIC_TIME + select GENERIC_CLOCKEVENTS help Support for Motorola's i.MX family of processors (MX1, MXL). @@ -308,6 +311,7 @@ config ARCH_L7200 config ARCH_KS8695 bool "Micrel/Kendin KS8695" + select GENERIC_GPIO help Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based System-on-Chip devices. @@ -320,6 +324,12 @@ config ARCH_NS9XXX <http://www.digi.com/products/microprocessors/index.jsp> +config ARCH_MXC + bool "Freescale MXC/iMX-based" + select ARCH_MTD_XIP + help + Support for Freescale MXC/iMX-based family of processors + config ARCH_PNX4008 bool "Philips Nexperia PNX4008 Mobile" help @@ -384,6 +394,7 @@ config ARCH_DAVINCI bool "TI DaVinci" select GENERIC_TIME select GENERIC_CLOCKEVENTS + select GENERIC_GPIO help Support for TI's DaVinci platform. @@ -427,6 +438,7 @@ source "arch/arm/mach-omap1/Kconfig" source "arch/arm/mach-omap2/Kconfig" source "arch/arm/plat-s3c24xx/Kconfig" +source "arch/arm/plat-s3c/Kconfig" if ARCH_S3C2410 source "arch/arm/mach-s3c2400/Kconfig" @@ -451,6 +463,8 @@ source "arch/arm/mach-realview/Kconfig" source "arch/arm/mach-at91/Kconfig" +source "arch/arm/plat-mxc/Kconfig" + source "arch/arm/mach-netx/Kconfig" source "arch/arm/mach-ns9xxx/Kconfig" @@ -531,6 +545,9 @@ config PCI information about which PCI hardware does work under Linux and which doesn't. +config PCI_SYSCALL + def_bool PCI + # Select the host bridge type config PCI_HOST_VIA82C505 bool @@ -1034,6 +1051,8 @@ source "drivers/mmc/Kconfig" source "drivers/rtc/Kconfig" +source "drivers/dma/Kconfig" + endmenu source "fs/Kconfig" diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 40c5eb1f55c7..18101f5f5f24 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -82,24 +82,24 @@ config DEBUG_CLPS711X_UART2 output to the second serial port on these devices. Saying N will cause the debug messages to appear on the first serial port. -config DEBUG_S3C2410_PORT - depends on DEBUG_LL && ARCH_S3C2410 - bool "Kernel low-level debugging messages via S3C2410 UART" +config DEBUG_S3C_PORT + depends on DEBUG_LL && PLAT_S3C + bool "Kernel low-level debugging messages via S3C UART" help Say Y here if you want debug print routines to go to one of the - S3C2410 internal UARTs. The chosen UART must have been configured + S3C internal UARTs. The chosen UART must have been configured before it is used. -config DEBUG_S3C2410_UART - depends on ARCH_S3C2410 - int "S3C2410 UART to use for low-level debug" +config DEBUG_S3C_UART + depends on PLAT_S3C + int "S3C UART to use for low-level debug" default "0" help - Choice for UART for kernel low-level using S3C2410 UARTS, + Choice for UART for kernel low-level using S3C UARTS, should be between zero and two. The port must have been initialised by the boot-loader before use. The uncompressor code port configuration is now handled - by CONFIG_S3C2410_LOWLEVEL_UART_PORT. + by CONFIG_S3C_LOWLEVEL_UART_PORT. endmenu diff --git a/arch/arm/Makefile b/arch/arm/Makefile index cbd5010d3bc3..fa4ea9ff0797 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -137,6 +137,8 @@ endif textofs-$(CONFIG_ARCH_NS9XXX) := 0x00108000 machine-$(CONFIG_ARCH_DAVINCI) := davinci machine-$(CONFIG_ARCH_KS8695) := ks8695 + incdir-$(CONFIG_ARCH_MXC) := mxc + machine-$(CONFIG_ARCH_MX3) := mx3 ifeq ($(CONFIG_ARCH_EBSA110),y) # This is what happens if you forget the IOCS16 line. @@ -183,6 +185,7 @@ core-$(CONFIG_VFP) += arch/arm/vfp/ core-$(CONFIG_PLAT_IOP) += arch/arm/plat-iop/ core-$(CONFIG_ARCH_OMAP) += arch/arm/plat-omap/ core-$(CONFIG_PLAT_S3C24XX) += arch/arm/plat-s3c24xx/ +core-$(CONFIG_ARCH_MXC) += arch/arm/plat-mxc/ drivers-$(CONFIG_OPROFILE) += arch/arm/oprofile/ drivers-$(CONFIG_ARCH_CLPS7500) += drivers/acorn/char/ diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile index ec9c400c7f82..25f12303b106 100644 --- a/arch/arm/boot/Makefile +++ b/arch/arm/boot/Makefile @@ -91,4 +91,12 @@ zinstall: $(obj)/zImage $(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \ $(obj)/zImage System.map "$(INSTALL_PATH)" +zi: + $(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \ + $(obj)/zImage System.map "$(INSTALL_PATH)" + +i: + $(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \ + $(obj)/Image System.map "$(INSTALL_PATH)" + subdir- := bootp compressed diff --git a/arch/arm/boot/compressed/.gitignore b/arch/arm/boot/compressed/.gitignore index aefee20cbf98..b15f927a5926 100644 --- a/arch/arm/boot/compressed/.gitignore +++ b/arch/arm/boot/compressed/.gitignore @@ -1 +1,2 @@ piggy.gz +font.c diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index adddc7131685..6b8cbd69f249 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -6,15 +6,13 @@ HEAD = head.o OBJS = misc.o -FONTC = drivers/video/console/font_acorn_8x8.c - -FONT = $(addprefix ../../../../drivers/video/console/, font_acorn_8x8.o) +FONTC = $(srctree)/drivers/video/console/font_acorn_8x8.c # # Architecture dependencies # ifeq ($(CONFIG_ARCH_ACORN),y) -OBJS += ll_char_wr.o $(FONT) +OBJS += ll_char_wr.o font.o endif ifeq ($(CONFIG_ARCH_SHARK),y) @@ -73,9 +71,9 @@ endif SEDFLAGS = s/TEXT_START/$(ZTEXTADDR)/;s/BSS_START/$(ZBSSADDR)/ -targets := vmlinux vmlinux.lds piggy.gz piggy.o $(FONT) \ +targets := vmlinux vmlinux.lds piggy.gz piggy.o font.o font.c \ head.o misc.o $(OBJS) -EXTRA_CFLAGS := -fpic +EXTRA_CFLAGS := -fpic -fno-builtin EXTRA_AFLAGS := # Supply ZRELADDR, INITRD_PHYS and PARAMS_PHYS to the decompressor via @@ -105,7 +103,10 @@ $(obj)/piggy.gz: $(obj)/../Image FORCE $(obj)/piggy.o: $(obj)/piggy.gz FORCE -CFLAGS_font_acorn_8x8.o := -Dstatic= +CFLAGS_font.o := -Dstatic= + +$(obj)/font.c: $(FONTC) + $(call cmd,shipped) $(obj)/vmlinux.lds: $(obj)/vmlinux.lds.in arch/arm/boot/Makefile .config @sed "$(SEDFLAGS)" < $< > $@ diff --git a/arch/arm/boot/compressed/head-xscale.S b/arch/arm/boot/compressed/head-xscale.S index 73c5d9e0201c..236bbe578312 100644 --- a/arch/arm/boot/compressed/head-xscale.S +++ b/arch/arm/boot/compressed/head-xscale.S @@ -41,11 +41,6 @@ __XScale_start: mov r7, #MACH_TYPE_COTULLA_IDP #endif -#ifdef CONFIG_MACH_GTWX5715 - mov r7, #(MACH_TYPE_GTWX5715 & 0xff) - orr r7, r7, #(MACH_TYPE_GTWX5715 & 0xff00) -#endif - #ifdef CONFIG_ARCH_IXP2000 mov r1, #-1 mov r0, #0xd6000000 diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 680ea6ed77b8..b9b03eda70e5 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -55,7 +55,7 @@ #elif defined(CONFIG_ARCH_S3C2410) .macro loadsp, rb mov \rb, #0x50000000 - add \rb, \rb, #0x4000 * CONFIG_S3C2410_LOWLEVEL_UART_PORT + add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT .endm #else .macro loadsp, rb @@ -436,6 +436,28 @@ __armv4_mmu_cache_on: mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs mov pc, r12 +__armv7_mmu_cache_on: + mov r12, lr + mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0 + tst r11, #0xf @ VMSA + blne __setup_mmu + mov r0, #0 + mcr p15, 0, r0, c7, c10, 4 @ drain write buffer + tst r11, #0xf @ VMSA + mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs + mrc p15, 0, r0, c1, c0, 0 @ read control reg + orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement + orr r0, r0, #0x003c @ write buffer + orrne r0, r0, #1 @ MMU enabled + movne r1, #-1 + mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer + mcrne p15, 0, r1, c3, c0, 0 @ load domain access control + mcr p15, 0, r0, c1, c0, 0 @ load control register + mrc p15, 0, r0, c1, c0, 0 @ and read it back + mov r0, #0 + mcr p15, 0, r0, c7, c5, 4 @ ISB + mov pc, r12 + __arm6_mmu_cache_on: mov r12, lr bl __setup_mmu @@ -622,11 +644,17 @@ proc_types: b __armv4_mmu_cache_flush .word 0x0007b000 @ ARMv6 - .word 0x0007f000 + .word 0x000ff000 b __armv4_mmu_cache_on b __armv4_mmu_cache_off b __armv6_mmu_cache_flush + .word 0x000f0000 @ new CPU Id + .word 0x000f0000 + b __armv7_mmu_cache_on + b __armv7_mmu_cache_off + b __armv7_mmu_cache_flush + .word 0 @ unrecognised type .word 0 mov pc, lr @@ -674,6 +702,16 @@ __armv4_mmu_cache_off: mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4 mov pc, lr +__armv7_mmu_cache_off: + mrc p15, 0, r0, c1, c0 + bic r0, r0, #0x000d + mcr p15, 0, r0, c1, c0 @ turn MMU and cache off + mov r12, lr + bl __armv7_mmu_cache_flush + mov r0, #0 + mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB + mov pc, r12 + __arm6_mmu_cache_off: mov r0, #0x00000030 @ ARM6 control reg. b __armv3_mmu_cache_off @@ -730,6 +768,59 @@ __armv6_mmu_cache_flush: mcr p15, 0, r1, c7, c10, 4 @ drain WB mov pc, lr +__armv7_mmu_cache_flush: + mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1 + tst r10, #0xf << 16 @ hierarchical cache (ARMv7) + beq hierarchical + mov r10, #0 + mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D + b iflush +hierarchical: + stmfd sp!, {r0-r5, r7, r9-r11} + mrc p15, 1, r0, c0, c0, 1 @ read clidr + ands r3, r0, #0x7000000 @ extract loc from clidr + mov r3, r3, lsr #23 @ left align loc bit field + beq finished @ if loc is 0, then no need to clean + mov r10, #0 @ start clean at cache level 0 +loop1: + add r2, r10, r10, lsr #1 @ work out 3x current cache level + mov r1, r0, lsr r2 @ extract cache type bits from clidr + and r1, r1, #7 @ mask of the bits for current cache only + cmp r1, #2 @ see what cache we have at this level + blt skip @ skip if no cache, or just i-cache + mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr + mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr + mrc p15, 1, r1, c0, c0, 0 @ read the new csidr + and r2, r1, #7 @ extract the length of the cache lines + add r2, r2, #4 @ add 4 (line length offset) + ldr r4, =0x3ff + ands r4, r4, r1, lsr #3 @ find maximum number on the way size + .word 0xe16f5f14 @ clz r5, r4 - find bit position of way size increment + ldr r7, =0x7fff + ands r7, r7, r1, lsr #13 @ extract max number of the index size +loop2: + mov r9, r4 @ create working copy of max way size +loop3: + orr r11, r10, r9, lsl r5 @ factor way and cache number into r11 + orr r11, r11, r7, lsl r2 @ factor index number into r11 + mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way + subs r9, r9, #1 @ decrement the way + bge loop3 + subs r7, r7, #1 @ decrement the index + bge loop2 +skip: + add r10, r10, #2 @ increment cache number + cmp r3, r10 + bgt loop1 +finished: + mov r10, #0 @ swith back to cache level 0 + mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr + ldmfd sp!, {r0-r5, r7, r9-r11} +iflush: + mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB + mcr p15, 0, r10, c7, c10, 4 @ drain WB + mov pc, lr + __armv4_mmu_cache_flush: mov r2, #64*1024 @ default: 32K dcache size (*2) mov r11, #32 @ default: 32 byte line size diff --git a/arch/arm/common/locomo.c b/arch/arm/common/locomo.c index cfe6f4650bc9..ae21755872ed 100644 --- a/arch/arm/common/locomo.c +++ b/arch/arm/common/locomo.c @@ -60,6 +60,9 @@ struct locomo { unsigned int irq; spinlock_t lock; void __iomem *base; +#ifdef CONFIG_PM + void *saved_state; +#endif }; struct locomo_dev_info { @@ -565,7 +568,7 @@ static int locomo_suspend(struct platform_device *dev, pm_message_t state) if (!save) return -ENOMEM; - dev->dev.power.saved_state = (void *) save; + lchip->saved_state = save; spin_lock_irqsave(&lchip->lock, flags); @@ -605,8 +608,8 @@ static int locomo_resume(struct platform_device *dev) struct locomo_save_data *save; unsigned long r; unsigned long flags; - - save = (struct locomo_save_data *) dev->dev.power.saved_state; + + save = lchip->saved_state; if (!save) return 0; @@ -628,6 +631,8 @@ static int locomo_resume(struct platform_device *dev) locomo_writel(0x1, lchip->base + LOCOMO_KEYBOARD + LOCOMO_KCMD); spin_unlock_irqrestore(&lchip->lock, flags); + + lchip->saved_state = NULL; kfree(save); return 0; diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c index 798bbfccafb7..eb06d0b2cb74 100644 --- a/arch/arm/common/sa1111.c +++ b/arch/arm/common/sa1111.c @@ -51,6 +51,9 @@ struct sa1111 { int irq; spinlock_t lock; void __iomem *base; +#ifdef CONFIG_PM + void *saved_state; +#endif }; /* @@ -822,7 +825,7 @@ static int sa1111_suspend(struct platform_device *dev, pm_message_t state) save = kmalloc(sizeof(struct sa1111_save_data), GFP_KERNEL); if (!save) return -ENOMEM; - dev->dev.power.saved_state = save; + sachip->saved_state = save; spin_lock_irqsave(&sachip->lock, flags); @@ -878,7 +881,7 @@ static int sa1111_resume(struct platform_device *dev) unsigned long flags, id; void __iomem *base; - save = (struct sa1111_save_data *)dev->dev.power.saved_state; + save = sachip->saved_state; if (!save) return 0; @@ -923,7 +926,7 @@ static int sa1111_resume(struct platform_device *dev) spin_unlock_irqrestore(&sachip->lock, flags); - dev->dev.power.saved_state = NULL; + sachip->saved_state = NULL; kfree(save); return 0; @@ -958,8 +961,8 @@ static int sa1111_remove(struct platform_device *pdev) platform_set_drvdata(pdev, NULL); #ifdef CONFIG_PM - kfree(pdev->dev.power.saved_state); - pdev->dev.power.saved_state = NULL; + kfree(sachip->saved_state); + sachip->saved_state = NULL; #endif } diff --git a/arch/arm/common/sharpsl_pm.c b/arch/arm/common/sharpsl_pm.c index 3bf3a927ae22..111a7fa5debe 100644 --- a/arch/arm/common/sharpsl_pm.c +++ b/arch/arm/common/sharpsl_pm.c @@ -766,9 +766,7 @@ static void sharpsl_apm_get_power_status(struct apm_power_info *info) } static struct pm_ops sharpsl_pm_ops = { - .prepare = pxa_pm_prepare, .enter = corgi_pxa_pm_enter, - .finish = pxa_pm_finish, .valid = pm_valid_only_mem, }; diff --git a/arch/arm/configs/badge4_defconfig b/arch/arm/configs/badge4_defconfig index 821865f75605..b2bbf217c707 100644 --- a/arch/arm/configs/badge4_defconfig +++ b/arch/arm/configs/badge4_defconfig @@ -708,7 +708,6 @@ CONFIG_I2C_ALGOPCF=m # I2C Hardware Bus support # CONFIG_I2C_ELEKTOR=m -# CONFIG_I2C_ISA is not set # CONFIG_I2C_PARPORT is not set # CONFIG_I2C_PARPORT_LIGHT is not set # CONFIG_I2C_STUB is not set diff --git a/arch/arm/configs/clps7500_defconfig b/arch/arm/configs/clps7500_defconfig index af9ae5389131..49e9f9d8b3d1 100644 --- a/arch/arm/configs/clps7500_defconfig +++ b/arch/arm/configs/clps7500_defconfig @@ -536,7 +536,6 @@ CONFIG_I2C_ALGOBIT=y # I2C Hardware Bus support # # CONFIG_I2C_ELEKTOR is not set -# CONFIG_I2C_ISA is not set # CONFIG_I2C_PARPORT is not set # CONFIG_I2C_PARPORT_LIGHT is not set # CONFIG_I2C_PCA_ISA is not set diff --git a/arch/arm/configs/em_x270_defconfig b/arch/arm/configs/em_x270_defconfig new file mode 100644 index 000000000000..6bea0901bdf0 --- /dev/null +++ b/arch/arm/configs/em_x270_defconfig @@ -0,0 +1,1265 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.22 +# Mon Jul 9 15:18:20 2007 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +# CONFIG_GENERIC_CLOCKEVENTS is not set +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_ARCH_MTD_XIP=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="-em-x270" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set +# CONFIG_AUDIT is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=17 +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y + +# +# Block layer +# +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_PNX4008 is not set +CONFIG_ARCH_PXA=y +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set + +# +# Intel PXA2xx Implementations +# +# CONFIG_ARCH_LUBBOCK is not set +# CONFIG_MACH_LOGICPD_PXA270 is not set +# CONFIG_MACH_MAINSTONE is not set +# CONFIG_ARCH_PXA_IDP is not set +# CONFIG_PXA_SHARPSL is not set +# CONFIG_MACH_TRIZEPS4 is not set +CONFIG_MACH_EM_X270=y +CONFIG_PXA27x=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_XSCALE=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5T=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_OUTER_CACHE is not set +CONFIG_IWMMXT=y +CONFIG_XSCALE_PMU=y + +# +# Bus support +# +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_TICK_ONESHOT is not set +# CONFIG_PREEMPT is not set +# CONFIG_NO_IDLE_HZ is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_FPE_NWFPE=y +# CONFIG_FPE_NWFPE_XP is not set +# CONFIG_FPE_FASTFPE is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +CONFIG_PM=y +CONFIG_PM_LEGACY=y +# CONFIG_PM_DEBUG is not set +# CONFIG_PM_SYSFS_DEPRECATED is not set +CONFIG_APM_EMULATION=m + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +CONFIG_BT=m +CONFIG_BT_L2CAP=m +CONFIG_BT_SCO=m +CONFIG_BT_RFCOMM=m +# CONFIG_BT_RFCOMM_TTY is not set +CONFIG_BT_BNEP=m +# CONFIG_BT_BNEP_MC_FILTER is not set +# CONFIG_BT_BNEP_PROTO_FILTER is not set +CONFIG_BT_HIDP=m + +# +# Bluetooth device drivers +# +CONFIG_BT_HCIUSB=m +# CONFIG_BT_HCIUSB_SCO is not set +CONFIG_BT_HCIUART=m +# CONFIG_BT_HCIUART_H4 is not set +# CONFIG_BT_HCIUART_BCSP is not set +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBFUSB=m +# CONFIG_BT_HCIVHCI is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +CONFIG_IEEE80211=m +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=m +CONFIG_IEEE80211_CRYPT_CCMP=m +# CONFIG_IEEE80211_CRYPT_TKIP is not set +# CONFIG_IEEE80211_SOFTMAC is not set +# CONFIG_RFKILL is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +# CONFIG_MTD_CFI_NOSWAP is not set +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_SHARP_SL is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_H1900 is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_SHARPSL is not set +# CONFIG_MTD_NAND_NANDSIM is not set +CONFIG_MTD_NAND_PLATFORM=y +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNPACPI is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=12000 +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_SCSI_PROC_FS is not set + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set + +# +# SCSI low-level drivers +# +# CONFIG_ISCSI_TCP is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_SMC91X is not set +CONFIG_DM9000=y +# CONFIG_SMC911X is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET_MII is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +CONFIG_KEYBOARD_PXA27x=m +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_UCB1400 is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_SERPORT is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_PXA=y +CONFIG_SERIAL_PXA_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set +CONFIG_HW_RANDOM=m +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set +# CONFIG_HWMON is not set + +# +# Misc devices +# + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# LED devices +# +# CONFIG_NEW_LEDS is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_SYS_FOPS is not set +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +CONFIG_FB_PXA=y +# CONFIG_FB_PXA_PARAMETERS is not set +# CONFIG_FB_MBX is not set +# CONFIG_FB_VIRTUAL is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y + +# +# Sound +# +CONFIG_SOUND=m + +# +# Advanced Linux Sound Architecture +# +CONFIG_SND=m +CONFIG_SND_TIMER=m +CONFIG_SND_PCM=m +# CONFIG_SND_SEQUENCER is not set +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=m +CONFIG_SND_PCM_OSS=m +CONFIG_SND_PCM_OSS_PLUGINS=y +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set + +# +# Generic devices +# +CONFIG_SND_AC97_CODEC=m +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set + +# +# ALSA ARM devices +# +CONFIG_SND_PXA2XX_PCM=m +CONFIG_SND_PXA2XX_AC97=m + +# +# USB devices +# +# CONFIG_SND_USB_AUDIO is not set +# CONFIG_SND_USB_CAIAQ is not set + +# +# System on Chip audio support +# +# CONFIG_SND_SOC is not set + +# +# Open Sound System +# +# CONFIG_SOUND_PRIME is not set +CONFIG_AC97_BUS=m + +# +# HID Devices +# +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_USB_HIDINPUT_POWERBOOK is not set +# CONFIG_HID_FF is not set +# CONFIG_USB_HIDDEV is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +# CONFIG_USB_ARCH_HAS_EHCI is not set +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_SUSPEND is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_SL811_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_DPCM is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USB_MON is not set + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set +CONFIG_MMC=m +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD Card Drivers +# +CONFIG_MMC_BLOCK=m + +# +# MMC/SD Host Controller Drivers +# +CONFIG_MMC_PXA=m + +# +# Real Time Clock +# +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=m + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_M48T86 is not set +CONFIG_RTC_DRV_V3020=m + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_SA1100=m + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +CONFIG_JFFS2_SUMMARY=y +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +CONFIG_SMB_FS=y +# CONFIG_SMB_NLS_DEFAULT is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_DETECT_SOFTLOCKUP is not set +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_LIST is not set +CONFIG_FRAME_POINTER=y +CONFIG_FORCED_INLINING=y +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_FAULT_INJECTION is not set +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_ERRORS=y +CONFIG_DEBUG_LL=y +# CONFIG_DEBUG_ICEDCC is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=m +CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_MANAGER=m +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_TWOFISH is not set +# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_AES=m +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_TEA is not set +CONFIG_CRYPTO_ARC4=m +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Hardware crypto devices +# + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/footbridge_defconfig b/arch/arm/configs/footbridge_defconfig index 2a612d23120b..299dc22294a0 100644 --- a/arch/arm/configs/footbridge_defconfig +++ b/arch/arm/configs/footbridge_defconfig @@ -748,7 +748,6 @@ CONFIG_I2C=m # CONFIG_I2C_ELEKTOR is not set # CONFIG_I2C_I801 is not set # CONFIG_I2C_I810 is not set -# CONFIG_I2C_ISA is not set # CONFIG_I2C_NFORCE2 is not set # CONFIG_I2C_PARPORT is not set # CONFIG_I2C_PARPORT_LIGHT is not set diff --git a/arch/arm/configs/neponset_defconfig b/arch/arm/configs/neponset_defconfig index e86794a10fc0..92ccdc6492f7 100644 --- a/arch/arm/configs/neponset_defconfig +++ b/arch/arm/configs/neponset_defconfig @@ -698,7 +698,6 @@ CONFIG_I2C_ALGOBIT=y # I2C Hardware Bus support # # CONFIG_I2C_ELEKTOR is not set -# CONFIG_I2C_ISA is not set # CONFIG_I2C_PARPORT_LIGHT is not set # CONFIG_I2C_STUB is not set # CONFIG_I2C_PCA_ISA is not set diff --git a/arch/arm/configs/picotux200_defconfig b/arch/arm/configs/picotux200_defconfig index 339c48953a62..3c0c4f192dc1 100644 --- a/arch/arm/configs/picotux200_defconfig +++ b/arch/arm/configs/picotux200_defconfig @@ -735,7 +735,6 @@ CONFIG_I2C_CHARDEV=m # I2C Hardware Bus support # CONFIG_I2C_AT91=m -CONFIG_I2C_ISA=m # CONFIG_I2C_OCORES is not set # CONFIG_I2C_PARPORT_LIGHT is not set # CONFIG_I2C_STUB is not set diff --git a/arch/arm/configs/rpc_defconfig b/arch/arm/configs/rpc_defconfig index bc091264d354..8452dc8c7cc3 100644 --- a/arch/arm/configs/rpc_defconfig +++ b/arch/arm/configs/rpc_defconfig @@ -558,7 +558,6 @@ CONFIG_I2C_ALGOBIT=y # # I2C Hardware Bus support # -# CONFIG_I2C_ISA is not set # CONFIG_I2C_PARPORT is not set # CONFIG_I2C_PARPORT_LIGHT is not set # CONFIG_I2C_STUB is not set diff --git a/arch/arm/configs/s3c2410_defconfig b/arch/arm/configs/s3c2410_defconfig index a850da377a29..f8a1645b3d4a 100644 --- a/arch/arm/configs/s3c2410_defconfig +++ b/arch/arm/configs/s3c2410_defconfig @@ -138,11 +138,11 @@ CONFIG_ARCH_S3C2410=y CONFIG_PLAT_S3C24XX=y CONFIG_CPU_S3C244X=y CONFIG_PM_SIMTEC=y -# CONFIG_S3C2410_BOOT_WATCHDOG is not set -# CONFIG_S3C2410_BOOT_ERROR_RESET is not set +# CONFIG_S3C_BOOT_WATCHDOG is not set +# CONFIG_S3C_BOOT_ERROR_RESET is not set # CONFIG_S3C2410_PM_DEBUG is not set # CONFIG_S3C2410_PM_CHECK is not set -CONFIG_S3C2410_LOWLEVEL_UART_PORT=0 +CONFIG_S3C_LOWLEVEL_UART_PORT=0 CONFIG_S3C2410_DMA=y # CONFIG_S3C2410_DMA_DEBUG is not set CONFIG_MACH_SMDK=y @@ -826,7 +826,6 @@ CONFIG_I2C_ALGOBIT=m # I2C Hardware Bus support # # CONFIG_I2C_ELEKTOR is not set -CONFIG_I2C_ISA=m # CONFIG_I2C_OCORES is not set # CONFIG_I2C_PARPORT is not set # CONFIG_I2C_PARPORT_LIGHT is not set @@ -1393,8 +1392,8 @@ CONFIG_DEBUG_USER=y # CONFIG_DEBUG_ERRORS is not set CONFIG_DEBUG_LL=y # CONFIG_DEBUG_ICEDCC is not set -CONFIG_DEBUG_S3C2410_PORT=y -CONFIG_DEBUG_S3C2410_UART=0 +CONFIG_DEBUG_S3C_PORT=y +CONFIG_DEBUG_S3C_UART=0 # # Security options diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S index a52da0ddb43d..024a9cf469b4 100644 --- a/arch/arm/kernel/head-common.S +++ b/arch/arm/kernel/head-common.S @@ -20,7 +20,8 @@ __switch_data: .long _end @ r7 .long processor_id @ r4 .long __machine_arch_type @ r5 - .long cr_alignment @ r6 + .long __atags_pointer @ r6 + .long cr_alignment @ r7 .long init_thread_union + THREAD_START_SP @ sp /* @@ -29,6 +30,7 @@ __switch_data: * * r0 = cp#15 control register * r1 = machine ID + * r2 = atags pointer * r9 = processor ID */ .type __mmap_switched, %function @@ -47,11 +49,12 @@ __mmap_switched: strcc fp, [r6],#4 bcc 1b - ldmia r3, {r4, r5, r6, sp} + ldmia r3, {r4, r5, r6, r7, sp} str r9, [r4] @ Save processor ID str r1, [r5] @ Save machine type + str r2, [r6] @ Save atags pointer bic r4, r0, #CR_A @ Clear 'A' bit - stmia r6, {r0, r4} @ Save control register values + stmia r7, {r0, r4} @ Save control register values b start_kernel /* @@ -215,3 +218,34 @@ ENTRY(lookup_machine_type) bl __lookup_machine_type mov r0, r5 ldmfd sp!, {r4 - r6, pc} + +/* Determine validity of the r2 atags pointer. The heuristic requires + * that the pointer be aligned, in the first 16k of physical RAM and + * that the ATAG_CORE marker is first and present. Future revisions + * of this function may be more lenient with the physical address and + * may also be able to move the ATAGS block if necessary. + * + * r8 = machinfo + * + * Returns: + * r2 either valid atags pointer, or zero + * r5, r6 corrupted + */ + + .type __vet_atags, %function +__vet_atags: + tst r2, #0x3 @ aligned? + bne 1f + + ldr r5, [r2, #0] @ is first tag ATAG_CORE? + subs r5, r5, #ATAG_CORE_SIZE + bne 1f + ldr r5, [r2, #4] + ldr r6, =ATAG_CORE + cmp r5, r6 + bne 1f + + mov pc, lr @ atag pointer is ok + +1: mov r2, #0 + mov pc, lr diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 41f98b4ba2ee..7898cbc9861a 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -29,6 +29,10 @@ #define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET) #define KERNEL_RAM_PADDR (PHYS_OFFSET + TEXT_OFFSET) +#define ATAG_CORE 0x54410001 +#define ATAG_CORE_SIZE ((2*4 + 3*4) >> 2) + + /* * swapper_pg_dir is the virtual address of the initial page table. * We place the page tables 16K below KERNEL_RAM_VADDR. Therefore, we must @@ -61,7 +65,7 @@ * * This is normally called from the decompressor code. The requirements * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0, - * r1 = machine nr. + * r1 = machine nr, r2 = atags pointer. * * This code is mostly position independent, so if you link the kernel at * 0xc0008000, you call this at __pa(0xc0008000). @@ -85,6 +89,7 @@ ENTRY(stext) bl __lookup_machine_type @ r5=machinfo movs r8, r5 @ invalid machine (r5=0)? beq __error_a @ yes, error 'a' + bl __vet_atags bl __create_page_tables /* diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c index 842361777d4e..93b7f8e22dcc 100644 --- a/arch/arm/kernel/process.c +++ b/arch/arm/kernel/process.c @@ -44,6 +44,10 @@ static const char *processor_modes[] = { "UK8_32" , "UK9_32" , "UK10_32", "UND_32" , "UK12_32", "UK13_32", "UK14_32", "SYS_32" }; +static const char *isa_modes[] = { + "ARM" , "Thumb" , "Jazelle", "ThumbEE" +}; + extern void setup_mm_for_reboot(char mode); static volatile int hlt_counter; @@ -230,11 +234,11 @@ void __show_regs(struct pt_regs *regs) buf[3] = flags & PSR_V_BIT ? 'V' : 'v'; buf[4] = '\0'; - printk("Flags: %s IRQs o%s FIQs o%s Mode %s%s Segment %s\n", + printk("Flags: %s IRQs o%s FIQs o%s Mode %s ISA %s Segment %s\n", buf, interrupts_enabled(regs) ? "n" : "ff", fast_interrupts_enabled(regs) ? "n" : "ff", processor_modes[processor_mode(regs)], - thumb_mode(regs) ? " (T)" : "", + isa_modes[isa_mode(regs)], get_fs() == get_ds() ? "kernel" : "user"); #ifdef CONFIG_CPU_CP15 { diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c index 6f2f46c2e406..78c9f1a3d41f 100644 --- a/arch/arm/kernel/ptrace.c +++ b/arch/arm/kernel/ptrace.c @@ -657,7 +657,6 @@ static int ptrace_setcrunchregs(struct task_struct *tsk, void __user *ufp) long arch_ptrace(struct task_struct *child, long request, long addr, long data) { - unsigned long tmp; int ret; switch (request) { @@ -666,12 +665,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) */ case PTRACE_PEEKTEXT: case PTRACE_PEEKDATA: - ret = access_process_vm(child, addr, &tmp, - sizeof(unsigned long), 0); - if (ret == sizeof(unsigned long)) - ret = put_user(tmp, (unsigned long __user *) data); - else - ret = -EIO; + ret = generic_ptrace_peekdata(child, addr, data); break; case PTRACE_PEEKUSR: @@ -683,12 +677,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) */ case PTRACE_POKETEXT: case PTRACE_POKEDATA: - ret = access_process_vm(child, addr, &data, - sizeof(unsigned long), 1); - if (ret == sizeof(unsigned long)) - ret = 0; - else - ret = -EIO; + ret = generic_ptrace_pokedata(child, addr, data); break; case PTRACE_POKEUSR: diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 650eac1bc0a6..5be2e987b843 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -63,6 +63,8 @@ unsigned int processor_id; unsigned int __machine_arch_type; EXPORT_SYMBOL(__machine_arch_type); +unsigned int __atags_pointer __initdata; + unsigned int system_rev; EXPORT_SYMBOL(system_rev); @@ -780,7 +782,9 @@ void __init setup_arch(char **cmdline_p) if (mdesc->soft_reboot) reboot_setup("s"); - if (mdesc->boot_params) + if (__atags_pointer) + tags = phys_to_virt(__atags_pointer); + else if (mdesc->boot_params) tags = phys_to_virt(mdesc->boot_params); /* diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index 237f4999b9a1..f2114bcf09d5 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -249,6 +249,7 @@ NORET_TYPE void die(const char *str, struct pt_regs *regs, int err) bust_spinlocks(1); __die(str, err, thread, regs); bust_spinlocks(0); + add_taint(TAINT_DIE); spin_unlock_irq(&die_lock); if (in_interrupt()) diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S index 2b7a8f5d8cf2..5ff5406666b4 100644 --- a/arch/arm/kernel/vmlinux.lds.S +++ b/arch/arm/kernel/vmlinux.lds.S @@ -66,6 +66,7 @@ SECTIONS . = ALIGN(4096); __per_cpu_start = .; *(.data.percpu) + *(.data.percpu.shared_aligned) __per_cpu_end = .; #ifndef CONFIG_XIP_KERNEL __init_begin = _stext; diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c index 70599bcf451c..0417c165d50d 100644 --- a/arch/arm/mach-at91/at91rm9200_devices.c +++ b/arch/arm/mach-at91/at91rm9200_devices.c @@ -477,7 +477,7 @@ void __init at91_add_device_i2c(void) {} * SPI * -------------------------------------------------------------------- */ -#if defined(CONFIG_SPI_AT91) || defined(CONFIG_SPI_AT91_MODULE) || defined(CONFIG_AT91_SPI) || defined(CONFIG_AT91_SPI_MODULE) +#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE) static u64 spi_dmamask = 0xffffffffUL; static struct resource spi_resources[] = { @@ -494,7 +494,7 @@ static struct resource spi_resources[] = { }; static struct platform_device at91rm9200_spi_device = { - .name = "at91_spi", + .name = "atmel_spi", .id = 0, .dev = { .dma_mask = &spi_dmamask, @@ -522,18 +522,14 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) else cs_pin = spi_standard_cs[devices[i].chip_select]; -#ifdef CONFIG_SPI_AT91_MANUAL_CS + /* enable chip-select pin */ at91_set_gpio_output(cs_pin, 1); -#else - at91_set_A_periph(cs_pin, 0); -#endif /* pass chip-select pin to driver */ devices[i].controller_data = (void *) cs_pin; } spi_register_board_info(devices, nr_devices); - at91_clock_associate("spi_clk", &at91rm9200_spi_device.dev, "spi"); platform_device_register(&at91rm9200_spi_device); } #else diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c index e18a41e61f0c..dde089922e3b 100644 --- a/arch/arm/mach-at91/board-csb337.c +++ b/arch/arm/mach-at91/board-csb337.c @@ -23,6 +23,7 @@ #include <linux/mm.h> #include <linux/module.h> #include <linux/platform_device.h> +#include <linux/i2c.h> #include <linux/spi/spi.h> #include <linux/mtd/physmap.h> @@ -83,6 +84,13 @@ static struct at91_udc_data __initdata csb337_udc_data = { .pullup_pin = AT91_PIN_PA24, }; +static struct i2c_board_info __initdata csb337_i2c_devices[] = { + { I2C_BOARD_INFO("rtc-ds1307", 0x68), + .type = "ds1307", + }, +}; + + static struct at91_cf_data __initdata csb337_cf_data = { /* * connector P4 on the CSB 337 mates to @@ -161,6 +169,8 @@ static void __init csb337_board_init(void) at91_add_device_udc(&csb337_udc_data); /* I2C */ at91_add_device_i2c(); + i2c_register_board_info(0, csb337_i2c_devices, + ARRAY_SIZE(csb337_i2c_devices)); /* Compact Flash */ at91_set_gpio_input(AT91_PIN_PB22, 1); /* IOIS16 */ at91_add_device_cf(&csb337_cf_data); diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c index 26ca8ab3f62a..42e172cb0f49 100644 --- a/arch/arm/mach-at91/board-sam9261ek.c +++ b/arch/arm/mach-at91/board-sam9261ek.c @@ -27,6 +27,11 @@ #include <linux/spi/spi.h> #include <linux/spi/ads7846.h> #include <linux/dm9000.h> +#include <linux/fb.h> +#include <linux/gpio_keys.h> +#include <linux/input.h> + +#include <video/atmel_lcdc.h> #include <asm/hardware.h> #include <asm/setup.h> @@ -271,6 +276,127 @@ static struct spi_board_info ek_spi_devices[] = { }; +/* + * LCD Controller + */ +#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE) +static struct fb_videomode at91_tft_vga_modes[] = { + { + .name = "TX09D50VM1CCA @ 60", + .refresh = 60, + .xres = 240, .yres = 320, + .pixclock = KHZ2PICOS(4965), + + .left_margin = 1, .right_margin = 33, + .upper_margin = 1, .lower_margin = 0, + .hsync_len = 5, .vsync_len = 1, + + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED, + }, +}; + +static struct fb_monspecs at91fb_default_monspecs = { + .manufacturer = "HIT", + .monitor = "TX09D50VM1CCA", + + .modedb = at91_tft_vga_modes, + .modedb_len = ARRAY_SIZE(at91_tft_vga_modes), + .hfmin = 15000, + .hfmax = 64000, + .vfmin = 50, + .vfmax = 150, +}; + +#define AT91SAM9261_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \ + | ATMEL_LCDC_DISTYPE_TFT \ + | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE) + +static void at91_lcdc_power_control(int on) +{ + if (on) + at91_set_gpio_value(AT91_PIN_PA12, 0); /* power up */ + else + at91_set_gpio_value(AT91_PIN_PA12, 1); /* power down */ +} + +/* Driver datas */ +static struct atmel_lcdfb_info __initdata ek_lcdc_data = { + .default_bpp = 16, + .default_dmacon = ATMEL_LCDC_DMAEN, + .default_lcdcon2 = AT91SAM9261_DEFAULT_LCDCON2, + .default_monspecs = &at91fb_default_monspecs, + .atmel_lcdfb_power_control = at91_lcdc_power_control, + .guard_time = 1, +}; + +#else +static struct atmel_lcdfb_info __initdata ek_lcdc_data; +#endif + + +/* + * GPIO Buttons + */ +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) +static struct gpio_keys_button ek_buttons[] = { + { + .gpio = AT91_PIN_PA27, + .keycode = BTN_0, + .desc = "Button 0", + .active_low = 1, + }, + { + .gpio = AT91_PIN_PA26, + .keycode = BTN_1, + .desc = "Button 1", + .active_low = 1, + }, + { + .gpio = AT91_PIN_PA25, + .keycode = BTN_2, + .desc = "Button 2", + .active_low = 1, + }, + { + .gpio = AT91_PIN_PA24, + .keycode = BTN_3, + .desc = "Button 3", + .active_low = 1, + } +}; + +static struct gpio_keys_platform_data ek_button_data = { + .buttons = ek_buttons, + .nbuttons = ARRAY_SIZE(ek_buttons), +}; + +static struct platform_device ek_button_device = { + .name = "gpio-keys", + .id = -1, + .num_resources = 0, + .dev = { + .platform_data = &ek_button_data, + } +}; + +static void __init ek_add_device_buttons(void) +{ + at91_set_gpio_input(AT91_PIN_PB27, 0); /* btn0 */ + at91_set_deglitch(AT91_PIN_PB27, 1); + at91_set_gpio_input(AT91_PIN_PB26, 0); /* btn1 */ + at91_set_deglitch(AT91_PIN_PB26, 1); + at91_set_gpio_input(AT91_PIN_PB25, 0); /* btn2 */ + at91_set_deglitch(AT91_PIN_PB25, 1); + at91_set_gpio_input(AT91_PIN_PB24, 0); /* btn3 */ + at91_set_deglitch(AT91_PIN_PB24, 1); + + platform_device_register(&ek_button_device); +} +#else +static void __init ek_add_device_buttons(void) {} +#endif + static void __init ek_board_init(void) { /* Serial */ @@ -296,6 +422,10 @@ static void __init ek_board_init(void) /* MMC */ at91_add_device_mmc(0, &ek_mmc_data); #endif + /* LCD Controller */ + at91_add_device_lcdc(&ek_lcdc_data); + /* Push Buttons */ + ek_add_device_buttons(); } MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK") diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c index c164c8e58ae6..2a1cc73390b7 100644 --- a/arch/arm/mach-at91/board-sam9263ek.c +++ b/arch/arm/mach-at91/board-sam9263ek.c @@ -26,6 +26,9 @@ #include <linux/platform_device.h> #include <linux/spi/spi.h> #include <linux/spi/ads7846.h> +#include <linux/fb.h> + +#include <video/atmel_lcdc.h> #include <asm/hardware.h> #include <asm/setup.h> @@ -202,6 +205,65 @@ static struct at91_nand_data __initdata ek_nand_data = { /* + * LCD Controller + */ +#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE) +static struct fb_videomode at91_tft_vga_modes[] = { + { + .name = "TX09D50VM1CCA @ 60", + .refresh = 60, + .xres = 240, .yres = 320, + .pixclock = KHZ2PICOS(4965), + + .left_margin = 1, .right_margin = 33, + .upper_margin = 1, .lower_margin = 0, + .hsync_len = 5, .vsync_len = 1, + + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED, + }, +}; + +static struct fb_monspecs at91fb_default_monspecs = { + .manufacturer = "HIT", + .monitor = "TX09D70VM1CCA", + + .modedb = at91_tft_vga_modes, + .modedb_len = ARRAY_SIZE(at91_tft_vga_modes), + .hfmin = 15000, + .hfmax = 64000, + .vfmin = 50, + .vfmax = 150, +}; + +#define AT91SAM9263_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \ + | ATMEL_LCDC_DISTYPE_TFT \ + | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE) + +static void at91_lcdc_power_control(int on) +{ + if (on) + at91_set_gpio_value(AT91_PIN_PD12, 0); /* power up */ + else + at91_set_gpio_value(AT91_PIN_PD12, 1); /* power down */ +} + +/* Driver datas */ +static struct atmel_lcdfb_info __initdata ek_lcdc_data = { + .default_bpp = 16, + .default_dmacon = ATMEL_LCDC_DMAEN, + .default_lcdcon2 = AT91SAM9263_DEFAULT_LCDCON2, + .default_monspecs = &at91fb_default_monspecs, + .atmel_lcdfb_power_control = at91_lcdc_power_control, + .guard_time = 1, +}; + +#else +static struct atmel_lcdfb_info __initdata ek_lcdc_data; +#endif + + +/* * AC97 */ static struct atmel_ac97_data ek_ac97_data = { @@ -230,6 +292,8 @@ static void __init ek_board_init(void) at91_add_device_nand(&ek_nand_data); /* I2C */ at91_add_device_i2c(); + /* LCD Controller */ + at91_add_device_lcdc(&ek_lcdc_data); /* AC97 */ at91_add_device_ac97(&ek_ac97_data); } diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index a8f88cd29905..99ac2e55774d 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -4,7 +4,8 @@ # # Common objects -obj-y := time.o irq.o serial.o io.o id.o psc.o +obj-y := time.o irq.o clock.o serial.o io.o id.o psc.o \ + gpio.o mux.o # Board specific obj-$(CONFIG_MACH_DAVINCI_EVM) += board-evm.o diff --git a/arch/arm/mach-davinci/board-evm.c b/arch/arm/mach-davinci/board-evm.c index 633c12e43044..9e4024c4965f 100644 --- a/arch/arm/mach-davinci/board-evm.c +++ b/arch/arm/mach-davinci/board-evm.c @@ -32,6 +32,7 @@ void __init davinci_psc_init(void); void __init davinci_irq_init(void); void __init davinci_map_common_io(void); +void __init davinci_init_common_hw(void); /* NOR Flash base address set to CS0 by default */ #define NOR_FLASH_PHYS 0x02000000 @@ -116,6 +117,7 @@ static __init void davinci_evm_init(void) static __init void davinci_evm_irq_init(void) { + davinci_init_common_hw(); davinci_irq_init(); } diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c new file mode 100644 index 000000000000..139ceaa35e24 --- /dev/null +++ b/arch/arm/mach-davinci/clock.c @@ -0,0 +1,323 @@ +/* + * TI DaVinci clock config file + * + * Copyright (C) 2006 Texas Instruments. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/errno.h> +#include <linux/err.h> +#include <linux/mutex.h> +#include <linux/platform_device.h> + +#include <asm/hardware.h> +#include <asm/io.h> + +#include <asm/arch/psc.h> +#include "clock.h" + +/* PLL/Reset register offsets */ +#define PLLM 0x110 + +static LIST_HEAD(clocks); +static DEFINE_MUTEX(clocks_mutex); +static DEFINE_SPINLOCK(clockfw_lock); + +static unsigned int commonrate; +static unsigned int armrate; +static unsigned int fixedrate = 27000000; /* 27 MHZ */ + +extern void davinci_psc_config(unsigned int domain, unsigned int id, char enable); + +/* + * Returns a clock. Note that we first try to use device id on the bus + * and clock name. If this fails, we try to use clock name only. + */ +struct clk *clk_get(struct device *dev, const char *id) +{ + struct clk *p, *clk = ERR_PTR(-ENOENT); + int idno; + + if (dev == NULL || dev->bus != &platform_bus_type) + idno = -1; + else + idno = to_platform_device(dev)->id; + + mutex_lock(&clocks_mutex); + + list_for_each_entry(p, &clocks, node) { + if (p->id == idno && + strcmp(id, p->name) == 0 && try_module_get(p->owner)) { + clk = p; + goto found; + } + } + + list_for_each_entry(p, &clocks, node) { + if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) { + clk = p; + break; + } + } + +found: + mutex_unlock(&clocks_mutex); + + return clk; +} +EXPORT_SYMBOL(clk_get); + +void clk_put(struct clk *clk) +{ + if (clk && !IS_ERR(clk)) + module_put(clk->owner); +} +EXPORT_SYMBOL(clk_put); + +static int __clk_enable(struct clk *clk) +{ + if (clk->flags & ALWAYS_ENABLED) + return 0; + + davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, clk->lpsc, 1); + return 0; +} + +static void __clk_disable(struct clk *clk) +{ + if (clk->usecount) + return; + + davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, clk->lpsc, 0); +} + +int clk_enable(struct clk *clk) +{ + unsigned long flags; + int ret = 0; + + if (clk == NULL || IS_ERR(clk)) + return -EINVAL; + + if (clk->usecount++ == 0) { + spin_lock_irqsave(&clockfw_lock, flags); + ret = __clk_enable(clk); + spin_unlock_irqrestore(&clockfw_lock, flags); + } + + return ret; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ + unsigned long flags; + + if (clk == NULL || IS_ERR(clk)) + return; + + if (clk->usecount > 0 && !(--clk->usecount)) { + spin_lock_irqsave(&clockfw_lock, flags); + __clk_disable(clk); + spin_unlock_irqrestore(&clockfw_lock, flags); + } +} +EXPORT_SYMBOL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + if (clk == NULL || IS_ERR(clk)) + return -EINVAL; + + return *(clk->rate); +} +EXPORT_SYMBOL(clk_get_rate); + +long clk_round_rate(struct clk *clk, unsigned long rate) +{ + if (clk == NULL || IS_ERR(clk)) + return -EINVAL; + + return *(clk->rate); +} +EXPORT_SYMBOL(clk_round_rate); + +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + if (clk == NULL || IS_ERR(clk)) + return -EINVAL; + + /* changing the clk rate is not supported */ + return -EINVAL; +} +EXPORT_SYMBOL(clk_set_rate); + +int clk_register(struct clk *clk) +{ + if (clk == NULL || IS_ERR(clk)) + return -EINVAL; + + mutex_lock(&clocks_mutex); + list_add(&clk->node, &clocks); + mutex_unlock(&clocks_mutex); + + return 0; +} +EXPORT_SYMBOL(clk_register); + +void clk_unregister(struct clk *clk) +{ + if (clk == NULL || IS_ERR(clk)) + return; + + mutex_lock(&clocks_mutex); + list_del(&clk->node); + mutex_unlock(&clocks_mutex); +} +EXPORT_SYMBOL(clk_unregister); + +static struct clk davinci_clks[] = { + { + .name = "ARMCLK", + .rate = &armrate, + .lpsc = -1, + .flags = ALWAYS_ENABLED, + }, + { + .name = "UART", + .rate = &fixedrate, + .lpsc = DAVINCI_LPSC_UART0, + }, + { + .name = "EMACCLK", + .rate = &commonrate, + .lpsc = DAVINCI_LPSC_EMAC_WRAPPER, + }, + { + .name = "I2CCLK", + .rate = &fixedrate, + .lpsc = DAVINCI_LPSC_I2C, + }, + { + .name = "IDECLK", + .rate = &commonrate, + .lpsc = DAVINCI_LPSC_ATA, + }, + { + .name = "McBSPCLK", + .rate = &commonrate, + .lpsc = DAVINCI_LPSC_McBSP, + }, + { + .name = "MMCSDCLK", + .rate = &commonrate, + .lpsc = DAVINCI_LPSC_MMC_SD, + }, + { + .name = "SPICLK", + .rate = &commonrate, + .lpsc = DAVINCI_LPSC_SPI, + }, + { + .name = "gpio", + .rate = &commonrate, + .lpsc = DAVINCI_LPSC_GPIO, + }, + { + .name = "AEMIFCLK", + .rate = &commonrate, + .lpsc = DAVINCI_LPSC_AEMIF, + .usecount = 1, + } +}; + +int __init davinci_clk_init(void) +{ + struct clk *clkp; + int count = 0; + u32 pll_mult; + + pll_mult = davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLM); + commonrate = ((pll_mult + 1) * 27000000) / 6; + armrate = ((pll_mult + 1) * 27000000) / 2; + + for (clkp = davinci_clks; count < ARRAY_SIZE(davinci_clks); + count++, clkp++) { + clk_register(clkp); + + /* Turn on clocks that have been enabled in the + * table above */ + if (clkp->usecount) + clk_enable(clkp); + } + + return 0; +} + +#ifdef CONFIG_PROC_FS +#include <linux/proc_fs.h> +#include <linux/seq_file.h> + +static void *davinci_ck_start(struct seq_file *m, loff_t *pos) +{ + return *pos < 1 ? (void *)1 : NULL; +} + +static void *davinci_ck_next(struct seq_file *m, void *v, loff_t *pos) +{ + ++*pos; + return NULL; +} + +static void davinci_ck_stop(struct seq_file *m, void *v) +{ +} + +static int davinci_ck_show(struct seq_file *m, void *v) +{ + struct clk *cp; + + list_for_each_entry(cp, &clocks, node) + seq_printf(m,"%s %d %d\n", cp->name, *(cp->rate), cp->usecount); + + return 0; +} + +static struct seq_operations davinci_ck_op = { + .start = davinci_ck_start, + .next = davinci_ck_next, + .stop = davinci_ck_stop, + .show = davinci_ck_show +}; + +static int davinci_ck_open(struct inode *inode, struct file *file) +{ + return seq_open(file, &davinci_ck_op); +} + +static struct file_operations proc_davinci_ck_operations = { + .open = davinci_ck_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; + +static int __init davinci_ck_proc_init(void) +{ + struct proc_dir_entry *entry; + + entry = create_proc_entry("davinci_clocks", 0, NULL); + if (entry) + entry->proc_fops = &proc_davinci_ck_operations; + return 0; + +} +__initcall(davinci_ck_proc_init); +#endif /* CONFIG_DEBUG_PROC_FS */ diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h new file mode 100644 index 000000000000..ed47079a52e4 --- /dev/null +++ b/arch/arm/mach-davinci/clock.h @@ -0,0 +1,33 @@ +/* + * TI DaVinci clock definitions + * + * Copyright (C) 2006 Texas Instruments. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_DAVINCI_CLOCK_H +#define __ARCH_ARM_DAVINCI_CLOCK_H + +struct clk { + struct list_head node; + struct module *owner; + const char *name; + unsigned int *rate; + int id; + __s8 usecount; + __u8 flags; + __u8 lpsc; +}; + +/* Clock flags */ +#define RATE_CKCTL 1 +#define RATE_FIXED 2 +#define RATE_PROPAGATES 4 +#define VIRTUAL_CLOCK 8 +#define ALWAYS_ENABLED 16 +#define ENABLE_REG_32BIT 32 + +#endif diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c new file mode 100644 index 000000000000..9c67886e7189 --- /dev/null +++ b/arch/arm/mach-davinci/gpio.c @@ -0,0 +1,286 @@ +/* + * TI DaVinci GPIO Support + * + * Copyright (c) 2006 David Brownell + * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/errno.h> +#include <linux/kernel.h> +#include <linux/list.h> +#include <linux/module.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/irq.h> +#include <linux/bitops.h> + +#include <asm/arch/irqs.h> +#include <asm/arch/hardware.h> +#include <asm/arch/gpio.h> + +#include <asm/mach/irq.h> + +static DEFINE_SPINLOCK(gpio_lock); +static DECLARE_BITMAP(gpio_in_use, DAVINCI_N_GPIO); + +int gpio_request(unsigned gpio, const char *tag) +{ + if (gpio >= DAVINCI_N_GPIO) + return -EINVAL; + + if (test_and_set_bit(gpio, gpio_in_use)) + return -EBUSY; + + return 0; +} +EXPORT_SYMBOL(gpio_request); + +void gpio_free(unsigned gpio) +{ + if (gpio >= DAVINCI_N_GPIO) + return; + + clear_bit(gpio, gpio_in_use); +} +EXPORT_SYMBOL(gpio_free); + +/* create a non-inlined version */ +static struct gpio_controller *__iomem gpio2controller(unsigned gpio) +{ + return __gpio_to_controller(gpio); +} + +/* + * Assuming the pin is muxed as a gpio output, set its output value. + */ +void __gpio_set(unsigned gpio, int value) +{ + struct gpio_controller *__iomem g = gpio2controller(gpio); + + __raw_writel(__gpio_mask(gpio), value ? &g->set_data : &g->clr_data); +} +EXPORT_SYMBOL(__gpio_set); + + +/* + * Read the pin's value (works even if it's set up as output); + * returns zero/nonzero. + * + * Note that changes are synched to the GPIO clock, so reading values back + * right after you've set them may give old values. + */ +int __gpio_get(unsigned gpio) +{ + struct gpio_controller *__iomem g = gpio2controller(gpio); + + return !!(__gpio_mask(gpio) & __raw_readl(&g->in_data)); +} +EXPORT_SYMBOL(__gpio_get); + + +/*--------------------------------------------------------------------------*/ + +/* + * board setup code *MUST* set PINMUX0 and PINMUX1 as + * needed, and enable the GPIO clock. + */ + +int gpio_direction_input(unsigned gpio) +{ + struct gpio_controller *__iomem g = gpio2controller(gpio); + u32 temp; + u32 mask; + + if (!g) + return -EINVAL; + + spin_lock(&gpio_lock); + mask = __gpio_mask(gpio); + temp = __raw_readl(&g->dir); + temp |= mask; + __raw_writel(temp, &g->dir); + spin_unlock(&gpio_lock); + return 0; +} +EXPORT_SYMBOL(gpio_direction_input); + +int gpio_direction_output(unsigned gpio, int value) +{ + struct gpio_controller *__iomem g = gpio2controller(gpio); + u32 temp; + u32 mask; + + if (!g) + return -EINVAL; + + spin_lock(&gpio_lock); + mask = __gpio_mask(gpio); + temp = __raw_readl(&g->dir); + temp &= ~mask; + __raw_writel(mask, value ? &g->set_data : &g->clr_data); + __raw_writel(temp, &g->dir); + spin_unlock(&gpio_lock); + return 0; +} +EXPORT_SYMBOL(gpio_direction_output); + +/* + * We expect irqs will normally be set up as input pins, but they can also be + * used as output pins ... which is convenient for testing. + * + * NOTE: GPIO0..GPIO7 also have direct INTC hookups, which work in addition + * to their GPIOBNK0 irq (but with a bit less overhead). But we don't have + * a good way to hook those up ... + * + * All those INTC hookups (GPIO0..GPIO7 plus five IRQ banks) can also + * serve as EDMA event triggers. + */ + +static void gpio_irq_disable(unsigned irq) +{ + struct gpio_controller *__iomem g = get_irq_chip_data(irq); + u32 mask = __gpio_mask(irq_to_gpio(irq)); + + __raw_writel(mask, &g->clr_falling); + __raw_writel(mask, &g->clr_rising); +} + +static void gpio_irq_enable(unsigned irq) +{ + struct gpio_controller *__iomem g = get_irq_chip_data(irq); + u32 mask = __gpio_mask(irq_to_gpio(irq)); + + if (irq_desc[irq].status & IRQ_TYPE_EDGE_FALLING) + __raw_writel(mask, &g->set_falling); + if (irq_desc[irq].status & IRQ_TYPE_EDGE_RISING) + __raw_writel(mask, &g->set_rising); +} + +static int gpio_irq_type(unsigned irq, unsigned trigger) +{ + struct gpio_controller *__iomem g = get_irq_chip_data(irq); + u32 mask = __gpio_mask(irq_to_gpio(irq)); + + if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) + return -EINVAL; + + irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK; + irq_desc[irq].status |= trigger; + + __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING) + ? &g->set_falling : &g->clr_falling); + __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING) + ? &g->set_rising : &g->clr_rising); + return 0; +} + +static struct irq_chip gpio_irqchip = { + .name = "GPIO", + .enable = gpio_irq_enable, + .disable = gpio_irq_disable, + .set_type = gpio_irq_type, +}; + +static void +gpio_irq_handler(unsigned irq, struct irq_desc *desc) +{ + struct gpio_controller *__iomem g = get_irq_chip_data(irq); + u32 mask = 0xffff; + + /* we only care about one bank */ + if (irq & 1) + mask <<= 16; + + /* temporarily mask (level sensitive) parent IRQ */ + desc->chip->ack(irq); + while (1) { + u32 status; + struct irq_desc *gpio; + int n; + int res; + + /* ack any irqs */ + status = __raw_readl(&g->intstat) & mask; + if (!status) + break; + __raw_writel(status, &g->intstat); + if (irq & 1) + status >>= 16; + + /* now demux them to the right lowlevel handler */ + n = (int)get_irq_data(irq); + gpio = &irq_desc[n]; + while (status) { + res = ffs(status); + n += res; + gpio += res; + desc_handle_irq(n - 1, gpio - 1); + status >>= res; + } + } + desc->chip->unmask(irq); + /* now it may re-trigger */ +} + +/* + * NOTE: for suspend/resume, probably best to make a sysdev (and class) + * with its suspend/resume calls hooking into the results of the set_wake() + * calls ... so if no gpios are wakeup events the clock can be disabled, + * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0 + * can be set appropriately for GPIOV33 pins. + */ + +static int __init davinci_gpio_irq_setup(void) +{ + unsigned gpio, irq, bank; + struct clk *clk; + + clk = clk_get(NULL, "gpio"); + if (IS_ERR(clk)) { + printk(KERN_ERR "Error %ld getting gpio clock?\n", + PTR_ERR(clk)); + return 0; + } + + clk_enable(clk); + + for (gpio = 0, irq = gpio_to_irq(0), bank = IRQ_GPIOBNK0; + gpio < DAVINCI_N_GPIO; bank++) { + struct gpio_controller *__iomem g = gpio2controller(gpio); + unsigned i; + + __raw_writel(~0, &g->clr_falling); + __raw_writel(~0, &g->clr_rising); + + /* set up all irqs in this bank */ + set_irq_chained_handler(bank, gpio_irq_handler); + set_irq_chip_data(bank, g); + set_irq_data(bank, (void *)irq); + + for (i = 0; i < 16 && gpio < DAVINCI_N_GPIO; + i++, irq++, gpio++) { + set_irq_chip(irq, &gpio_irqchip); + set_irq_chip_data(irq, g); + set_irq_handler(irq, handle_simple_irq); + set_irq_flags(irq, IRQF_VALID); + } + } + + /* BINTEN -- per-bank interrupt enable. genirq would also let these + * bits be set/cleared dynamically. + */ + __raw_writel(0x1f, (void *__iomem) + IO_ADDRESS(DAVINCI_GPIO_BASE + 0x08)); + + printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0)); + + return 0; +} + +arch_initcall(davinci_gpio_irq_setup); diff --git a/arch/arm/mach-davinci/io.c b/arch/arm/mach-davinci/io.c index 87fae6fb6ecf..47787ff84a6a 100644 --- a/arch/arm/mach-davinci/io.c +++ b/arch/arm/mach-davinci/io.c @@ -17,6 +17,7 @@ #include <asm/memory.h> #include <asm/mach/map.h> +#include <asm/arch/clock.h> extern void davinci_check_revision(void); @@ -49,3 +50,8 @@ void __init davinci_map_common_io(void) */ davinci_check_revision(); } + +void __init davinci_init_common_hw(void) +{ + davinci_clk_init(); +} diff --git a/arch/arm/mach-davinci/mux.c b/arch/arm/mach-davinci/mux.c new file mode 100644 index 000000000000..92d26bd305b7 --- /dev/null +++ b/arch/arm/mach-davinci/mux.c @@ -0,0 +1,41 @@ +/* + * DaVinci pin multiplexing configurations + * + * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com> + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#include <linux/io.h> +#include <linux/spinlock.h> + +#include <asm/hardware.h> + +#include <asm/arch/mux.h> + +/* System control register offsets */ +#define PINMUX0 0x00 +#define PINMUX1 0x04 + +static DEFINE_SPINLOCK(mux_lock); + +void davinci_mux_peripheral(unsigned int mux, unsigned int enable) +{ + u32 pinmux, muxreg = PINMUX0; + + if (mux >= DAVINCI_MUX_LEVEL2) { + muxreg = PINMUX1; + mux -= DAVINCI_MUX_LEVEL2; + } + + spin_lock(&mux_lock); + pinmux = davinci_readl(DAVINCI_SYSTEM_MODULE_BASE + muxreg); + if (enable) + pinmux |= (1 << mux); + else + pinmux &= ~(1 << mux); + davinci_writel(pinmux, DAVINCI_SYSTEM_MODULE_BASE + muxreg); + spin_unlock(&mux_lock); +} diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c index e1b0050283a6..1334416559ad 100644 --- a/arch/arm/mach-davinci/psc.c +++ b/arch/arm/mach-davinci/psc.c @@ -25,39 +25,40 @@ #include <asm/io.h> #include <asm/hardware.h> #include <asm/arch/psc.h> +#include <asm/arch/mux.h> -#define PTCMD __REG(0x01C41120) -#define PDSTAT __REG(0x01C41200) -#define PDCTL1 __REG(0x01C41304) -#define EPCPR __REG(0x01C41070) -#define PTSTAT __REG(0x01C41128) +/* PSC register offsets */ +#define EPCPR 0x070 +#define PTCMD 0x120 +#define PTSTAT 0x128 +#define PDSTAT 0x200 +#define PDCTL1 0x304 +#define MDSTAT 0x800 +#define MDCTL 0xA00 -#define MDSTAT IO_ADDRESS(0x01C41800) -#define MDCTL IO_ADDRESS(0x01C41A00) - -#define PINMUX0 __REG(0x01c40000) -#define PINMUX1 __REG(0x01c40004) -#define VDD3P3V_PWDN __REG(0x01C40048) +/* System control register offsets */ +#define VDD3P3V_PWDN 0x48 static void davinci_psc_mux(unsigned int id) { switch (id) { case DAVINCI_LPSC_ATA: - PINMUX0 |= (1 << 17) | (1 << 16); + davinci_mux_peripheral(DAVINCI_MUX_HDIREN, 1); + davinci_mux_peripheral(DAVINCI_MUX_ATAEN, 1); break; case DAVINCI_LPSC_MMC_SD: /* VDD power manupulations are done in U-Boot for CPMAC * so applies to MMC as well */ /*Set up the pull regiter for MMC */ - VDD3P3V_PWDN = 0x0; - PINMUX1 &= (~(1 << 9)); + davinci_writel(0, DAVINCI_SYSTEM_MODULE_BASE + VDD3P3V_PWDN); + davinci_mux_peripheral(DAVINCI_MUX_MSTK, 0); break; case DAVINCI_LPSC_I2C: - PINMUX1 |= (1 << 7); + davinci_mux_peripheral(DAVINCI_MUX_I2C, 1); break; case DAVINCI_LPSC_McBSP: - PINMUX1 |= (1 << 10); + davinci_mux_peripheral(DAVINCI_MUX_ASP, 1); break; default: break; @@ -67,33 +68,59 @@ static void davinci_psc_mux(unsigned int id) /* Enable or disable a PSC domain */ void davinci_psc_config(unsigned int domain, unsigned int id, char enable) { - volatile unsigned int *mdstat = (unsigned int *)((int)MDSTAT + 4 * id); - volatile unsigned int *mdctl = (unsigned int *)((int)MDCTL + 4 * id); + u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl, mdstat_mask; if (id < 0) return; + mdctl = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + MDCTL + 4 * id); if (enable) - *mdctl |= 0x00000003; /* Enable Module */ + mdctl |= 0x00000003; /* Enable Module */ else - *mdctl &= 0xFFFFFFF2; /* Disable Module */ + mdctl &= 0xFFFFFFF2; /* Disable Module */ + davinci_writel(mdctl, DAVINCI_PWR_SLEEP_CNTRL_BASE + MDCTL + 4 * id); + + pdstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDSTAT); + if ((pdstat & 0x00000001) == 0) { + pdctl1 = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1); + pdctl1 |= 0x1; + davinci_writel(pdctl1, DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1); + + ptcmd = 1 << domain; + davinci_writel(ptcmd, DAVINCI_PWR_SLEEP_CNTRL_BASE + PTCMD); - if ((PDSTAT & 0x00000001) == 0) { - PDCTL1 |= 0x1; - PTCMD = (1 << domain); - while ((((EPCPR >> domain) & 1) == 0)); + do { + epcpr = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + + EPCPR); + } while ((((epcpr >> domain) & 1) == 0)); - PDCTL1 |= 0x100; - while (!(((PTSTAT >> domain) & 1) == 0)); + pdctl1 = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1); + pdctl1 |= 0x100; + davinci_writel(pdctl1, DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1); + + do { + ptstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + + PTSTAT); + } while (!(((ptstat >> domain) & 1) == 0)); } else { - PTCMD = (1 << domain); - while (!(((PTSTAT >> domain) & 1) == 0)); + ptcmd = 1 << domain; + davinci_writel(ptcmd, DAVINCI_PWR_SLEEP_CNTRL_BASE + PTCMD); + + do { + ptstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + + PTSTAT); + } while (!(((ptstat >> domain) & 1) == 0)); } if (enable) - while (!((*mdstat & 0x0000001F) == 0x3)); + mdstat_mask = 0x3; else - while (!((*mdstat & 0x0000001F) == 0x2)); + mdstat_mask = 0x2; + + do { + mdstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + + MDSTAT + 4 * id); + } while (!((mdstat & 0x0000001F) == mdstat_mask)); if (enable) davinci_psc_mux(id); diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c index 4d8425de6922..e96a3dcdc1a7 100644 --- a/arch/arm/mach-davinci/time.c +++ b/arch/arm/mach-davinci/time.c @@ -285,6 +285,8 @@ static void davinci_set_mode(enum clock_event_mode mode, case CLOCK_EVT_MODE_SHUTDOWN: t->opts = TIMER_OPTS_DISABLED; break; + case CLOCK_EVT_MODE_RESUME: + break; } } diff --git a/arch/arm/mach-imx/generic.c b/arch/arm/mach-imx/generic.c index 1c474cf709ca..a58b678006df 100644 --- a/arch/arm/mach-imx/generic.c +++ b/arch/arm/mach-imx/generic.c @@ -28,12 +28,16 @@ #include <linux/module.h> #include <linux/string.h> +#include <asm/errno.h> #include <asm/arch/imxfb.h> #include <asm/hardware.h> #include <asm/arch/imx-regs.h> #include <asm/mach/map.h> #include <asm/arch/mmc.h> +#include <asm/arch/gpio.h> + +unsigned long imx_gpio_alloc_map[(GPIO_PORT_MAX + 1) * 32 / BITS_PER_LONG]; void imx_gpio_mode(int gpio_mode) { @@ -95,6 +99,120 @@ void imx_gpio_mode(int gpio_mode) EXPORT_SYMBOL(imx_gpio_mode); +int imx_gpio_request(unsigned gpio, const char *label) +{ + if(gpio >= (GPIO_PORT_MAX + 1) * 32) + printk(KERN_ERR "imx_gpio: Attempt to request nonexistent GPIO %d for \"%s\"\n", + gpio, label ? label : "?"); + return -EINVAL; + + if(test_and_set_bit(gpio, imx_gpio_alloc_map)) { + printk(KERN_ERR "imx_gpio: GPIO %d already used. Allocation for \"%s\" failed\n", + gpio, label ? label : "?"); + return -EBUSY; + } + + return 0; +} + +EXPORT_SYMBOL(imx_gpio_request); + +void imx_gpio_free(unsigned gpio) +{ + if(gpio >= (GPIO_PORT_MAX + 1) * 32) + return; + + clear_bit(gpio, imx_gpio_alloc_map); +} + +EXPORT_SYMBOL(imx_gpio_free); + +int imx_gpio_direction_input(unsigned gpio) +{ + imx_gpio_mode(gpio| GPIO_IN); + return 0; +} + +EXPORT_SYMBOL(imx_gpio_direction_input); + +int imx_gpio_direction_output(unsigned gpio, int value) +{ + imx_gpio_set_value(gpio, value); + imx_gpio_mode(gpio| GPIO_OUT); + return 0; +} + +EXPORT_SYMBOL(imx_gpio_direction_output); + +int imx_gpio_setup_multiple_pins(const int *pin_list, unsigned count, + int alloc_mode, const char *label) +{ + const int *p = pin_list; + int i; + unsigned gpio; + unsigned mode; + + for (i = 0; i < count; i++) { + gpio = *p & (GPIO_PIN_MASK | GPIO_PORT_MASK); + mode = *p & ~(GPIO_PIN_MASK | GPIO_PORT_MASK); + + if (gpio >= (GPIO_PORT_MAX + 1) * 32) + goto setup_error; + + if (alloc_mode & IMX_GPIO_ALLOC_MODE_RELEASE) + imx_gpio_free(gpio); + else if (!(alloc_mode & IMX_GPIO_ALLOC_MODE_NO_ALLOC)) + if (imx_gpio_request(gpio, label)) + if (!(alloc_mode & IMX_GPIO_ALLOC_MODE_TRY_ALLOC)) + goto setup_error; + + if (!(alloc_mode & (IMX_GPIO_ALLOC_MODE_ALLOC_ONLY | + IMX_GPIO_ALLOC_MODE_RELEASE))) + imx_gpio_mode(gpio | mode); + + p++; + } + return 0; + +setup_error: + if(alloc_mode & (IMX_GPIO_ALLOC_MODE_NO_ALLOC | + IMX_GPIO_ALLOC_MODE_TRY_ALLOC)) + return -EINVAL; + + while (p != pin_list) { + p--; + gpio = *p & (GPIO_PIN_MASK | GPIO_PORT_MASK); + imx_gpio_free(gpio); + } + + return -EINVAL; +} + +EXPORT_SYMBOL(imx_gpio_setup_multiple_pins); + +void __imx_gpio_set_value(unsigned gpio, int value) +{ + imx_gpio_set_value_inline(gpio, value); +} + +EXPORT_SYMBOL(__imx_gpio_set_value); + +int imx_gpio_to_irq(unsigned gpio) +{ + return IRQ_GPIOA(0) + gpio; +} + +EXPORT_SYMBOL(imx_gpio_to_irq); + +int imx_irq_to_gpio(unsigned irq) +{ + if (irq < IRQ_GPIOA(0)) + return -EINVAL; + return irq - IRQ_GPIOA(0); +} + +EXPORT_SYMBOL(imx_irq_to_gpio); + /* * get the system pll clock in Hz * diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c index 6960a9d04217..d86d124aea22 100644 --- a/arch/arm/mach-imx/time.c +++ b/arch/arm/mach-imx/time.c @@ -3,6 +3,7 @@ * * Copyright (C) 2000-2001 Deep Blue Solutions * Copyright (C) 2002 Shane Nay (shane@minirl.com) + * Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -15,6 +16,7 @@ #include <linux/irq.h> #include <linux/time.h> #include <linux/clocksource.h> +#include <linux/clockchips.h> #include <asm/hardware.h> #include <asm/io.h> @@ -25,7 +27,8 @@ /* Use timer 1 as system timer */ #define TIMER_BASE IMX_TIM1_BASE -static unsigned long evt_diff; +static struct clock_event_device clockevent_imx; +static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED; /* * IRQ handler for the timer @@ -33,25 +36,20 @@ static unsigned long evt_diff; static irqreturn_t imx_timer_interrupt(int irq, void *dev_id) { + struct clock_event_device *evt = &clockevent_imx; uint32_t tstat; + irqreturn_t ret = IRQ_NONE; /* clear the interrupt */ tstat = IMX_TSTAT(TIMER_BASE); IMX_TSTAT(TIMER_BASE) = 0; if (tstat & TSTAT_COMP) { - do { - - write_seqlock(&xtime_lock); - timer_tick(); - write_sequnlock(&xtime_lock); - IMX_TCMP(TIMER_BASE) += evt_diff; - - } while (unlikely((int32_t)(IMX_TCMP(TIMER_BASE) - - IMX_TCN(TIMER_BASE)) < 0)); + evt->event_handler(evt); + ret = IRQ_HANDLED; } - return IRQ_HANDLED; + return ret; } static struct irqaction imx_timer_irq = { @@ -70,10 +68,8 @@ static void __init imx_timer_hardware_init(void) */ IMX_TCTL(TIMER_BASE) = 0; IMX_TPRER(TIMER_BASE) = 0; - IMX_TCMP(TIMER_BASE) = LATCH - 1; - IMX_TCTL(TIMER_BASE) = TCTL_FRR | TCTL_CLK_PCLK1 | TCTL_IRQEN | TCTL_TEN; - evt_diff = LATCH; + IMX_TCTL(TIMER_BASE) = TCTL_FRR | TCTL_CLK_PCLK1 | TCTL_TEN; } cycle_t imx_get_cycles(void) @@ -99,11 +95,109 @@ static int __init imx_clocksource_init(void) return 0; } +static int imx_set_next_event(unsigned long evt, + struct clock_event_device *unused) +{ + unsigned long tcmp; + + tcmp = IMX_TCN(TIMER_BASE) + evt; + IMX_TCMP(TIMER_BASE) = tcmp; + + return (int32_t)(tcmp - IMX_TCN(TIMER_BASE)) < 0 ? -ETIME : 0; +} + +#ifdef DEBUG +static const char *clock_event_mode_label[]={ + [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC", + [CLOCK_EVT_MODE_ONESHOT] = "CLOCK_EVT_MODE_ONESHOT", + [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN", + [CLOCK_EVT_MODE_UNUSED] = "CLOCK_EVT_MODE_UNUSED" +}; +#endif /*DEBUG*/ + +static void imx_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) +{ + unsigned long flags; + + /* + * The timer interrupt generation is disabled at least + * for enough time to call imx_set_next_event() + */ + local_irq_save(flags); + /* Disable interrupt in GPT module */ + IMX_TCTL(TIMER_BASE) &= ~TCTL_IRQEN; + if (mode != clockevent_mode) { + /* Set event time into far-far future */ + IMX_TCMP(TIMER_BASE) = IMX_TCN(TIMER_BASE) - 3; + /* Clear pending interrupt */ + IMX_TSTAT(TIMER_BASE) &= ~TSTAT_COMP; + } + +#ifdef DEBUG + printk(KERN_INFO "imx_set_mode: changing mode from %s to %s\n", + clock_event_mode_label[clockevent_mode], clock_event_mode_label[mode]); +#endif /*DEBUG*/ + + /* Remember timer mode */ + clockevent_mode = mode; + local_irq_restore(flags); + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + printk(KERN_ERR "imx_set_mode: Periodic mode is not supported for i.MX\n"); + break; + case CLOCK_EVT_MODE_ONESHOT: + /* + * Do not put overhead of interrupt enable/disable into + * imx_set_next_event(), the core has about 4 minutes + * to call imx_set_next_event() or shutdown clock after + * mode switching + */ + local_irq_save(flags); + IMX_TCTL(TIMER_BASE) |= TCTL_IRQEN; + local_irq_restore(flags); + break; + case CLOCK_EVT_MODE_SHUTDOWN: + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_RESUME: + /* Left event sources disabled, no more interrupts appears */ + break; + } +} + +static struct clock_event_device clockevent_imx = { + .name = "imx_timer1", + .features = CLOCK_EVT_FEAT_ONESHOT, + .shift = 32, + .set_mode = imx_set_mode, + .set_next_event = imx_set_next_event, + .rating = 200, +}; + +static int __init imx_clockevent_init(void) +{ + clockevent_imx.mult = div_sc(imx_get_perclk1(), NSEC_PER_SEC, + clockevent_imx.shift); + clockevent_imx.max_delta_ns = + clockevent_delta2ns(0xfffffffe, &clockevent_imx); + clockevent_imx.min_delta_ns = + clockevent_delta2ns(0xf, &clockevent_imx); + + clockevent_imx.cpumask = cpumask_of_cpu(0); + + clockevents_register_device(&clockevent_imx); + + return 0; +} + + static void __init imx_timer_init(void) { imx_timer_hardware_init(); imx_clocksource_init(); + imx_clockevent_init(); + /* * Make irqs happen for the system timer */ diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c index 9d63d7f260ca..99d94cb1bafd 100644 --- a/arch/arm/mach-iop13xx/pci.c +++ b/arch/arm/mach-iop13xx/pci.c @@ -1002,11 +1002,10 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) if (nr > 1) return 0; - res = kmalloc(sizeof(struct resource) * 2, GFP_KERNEL); + res = kcalloc(2, sizeof(struct resource), GFP_KERNEL); if (!res) panic("PCI: unable to alloc resources"); - memset(res, 0, sizeof(struct resource) * 2); /* 'nr' assumptions: * ATUX is always 0 diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c index bc4871553f6a..bfe0c87e3397 100644 --- a/arch/arm/mach-iop13xx/setup.c +++ b/arch/arm/mach-iop13xx/setup.c @@ -25,6 +25,7 @@ #include <asm/hardware.h> #include <asm/irq.h> #include <asm/io.h> +#include <asm/hardware/iop_adma.h> #define IOP13XX_UART_XTAL 33334000 #define IOP13XX_SETUP_DEBUG 0 @@ -236,19 +237,143 @@ static unsigned long iq8134x_probe_flash_size(void) } #endif +/* ADMA Channels */ +static struct resource iop13xx_adma_0_resources[] = { + [0] = { + .start = IOP13XX_ADMA_PHYS_BASE(0), + .end = IOP13XX_ADMA_UPPER_PA(0), + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_IOP13XX_ADMA0_EOT, + .end = IRQ_IOP13XX_ADMA0_EOT, + .flags = IORESOURCE_IRQ + }, + [2] = { + .start = IRQ_IOP13XX_ADMA0_EOC, + .end = IRQ_IOP13XX_ADMA0_EOC, + .flags = IORESOURCE_IRQ + }, + [3] = { + .start = IRQ_IOP13XX_ADMA0_ERR, + .end = IRQ_IOP13XX_ADMA0_ERR, + .flags = IORESOURCE_IRQ + } +}; + +static struct resource iop13xx_adma_1_resources[] = { + [0] = { + .start = IOP13XX_ADMA_PHYS_BASE(1), + .end = IOP13XX_ADMA_UPPER_PA(1), + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_IOP13XX_ADMA1_EOT, + .end = IRQ_IOP13XX_ADMA1_EOT, + .flags = IORESOURCE_IRQ + }, + [2] = { + .start = IRQ_IOP13XX_ADMA1_EOC, + .end = IRQ_IOP13XX_ADMA1_EOC, + .flags = IORESOURCE_IRQ + }, + [3] = { + .start = IRQ_IOP13XX_ADMA1_ERR, + .end = IRQ_IOP13XX_ADMA1_ERR, + .flags = IORESOURCE_IRQ + } +}; + +static struct resource iop13xx_adma_2_resources[] = { + [0] = { + .start = IOP13XX_ADMA_PHYS_BASE(2), + .end = IOP13XX_ADMA_UPPER_PA(2), + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_IOP13XX_ADMA2_EOT, + .end = IRQ_IOP13XX_ADMA2_EOT, + .flags = IORESOURCE_IRQ + }, + [2] = { + .start = IRQ_IOP13XX_ADMA2_EOC, + .end = IRQ_IOP13XX_ADMA2_EOC, + .flags = IORESOURCE_IRQ + }, + [3] = { + .start = IRQ_IOP13XX_ADMA2_ERR, + .end = IRQ_IOP13XX_ADMA2_ERR, + .flags = IORESOURCE_IRQ + } +}; + +static u64 iop13xx_adma_dmamask = DMA_64BIT_MASK; +static struct iop_adma_platform_data iop13xx_adma_0_data = { + .hw_id = 0, + .pool_size = PAGE_SIZE, +}; + +static struct iop_adma_platform_data iop13xx_adma_1_data = { + .hw_id = 1, + .pool_size = PAGE_SIZE, +}; + +static struct iop_adma_platform_data iop13xx_adma_2_data = { + .hw_id = 2, + .pool_size = PAGE_SIZE, +}; + +/* The ids are fixed up later in iop13xx_platform_init */ +static struct platform_device iop13xx_adma_0_channel = { + .name = "iop-adma", + .id = 0, + .num_resources = 4, + .resource = iop13xx_adma_0_resources, + .dev = { + .dma_mask = &iop13xx_adma_dmamask, + .coherent_dma_mask = DMA_64BIT_MASK, + .platform_data = (void *) &iop13xx_adma_0_data, + }, +}; + +static struct platform_device iop13xx_adma_1_channel = { + .name = "iop-adma", + .id = 0, + .num_resources = 4, + .resource = iop13xx_adma_1_resources, + .dev = { + .dma_mask = &iop13xx_adma_dmamask, + .coherent_dma_mask = DMA_64BIT_MASK, + .platform_data = (void *) &iop13xx_adma_1_data, + }, +}; + +static struct platform_device iop13xx_adma_2_channel = { + .name = "iop-adma", + .id = 0, + .num_resources = 4, + .resource = iop13xx_adma_2_resources, + .dev = { + .dma_mask = &iop13xx_adma_dmamask, + .coherent_dma_mask = DMA_64BIT_MASK, + .platform_data = (void *) &iop13xx_adma_2_data, + }, +}; + void __init iop13xx_map_io(void) { /* Initialize the Static Page Table maps */ iotable_init(iop13xx_std_desc, ARRAY_SIZE(iop13xx_std_desc)); } -static int init_uart = 0; -static int init_i2c = 0; +static int init_uart; +static int init_i2c; +static int init_adma; void __init iop13xx_platform_init(void) { int i; - u32 uart_idx, i2c_idx, plat_idx; + u32 uart_idx, i2c_idx, adma_idx, plat_idx; struct platform_device *iop13xx_devices[IQ81340_MAX_PLAT_DEVICES]; /* set the bases so we can read the device id */ @@ -294,6 +419,12 @@ void __init iop13xx_platform_init(void) } } + if (init_adma == IOP13XX_INIT_ADMA_DEFAULT) { + init_adma |= IOP13XX_INIT_ADMA_0; + init_adma |= IOP13XX_INIT_ADMA_1; + init_adma |= IOP13XX_INIT_ADMA_2; + } + plat_idx = 0; uart_idx = 0; i2c_idx = 0; @@ -332,6 +463,56 @@ void __init iop13xx_platform_init(void) } } + /* initialize adma channel ids and capabilities */ + adma_idx = 0; + for (i = 0; i < IQ81340_NUM_ADMA; i++) { + struct iop_adma_platform_data *plat_data; + if ((init_adma & (1 << i)) && IOP13XX_SETUP_DEBUG) + printk(KERN_INFO + "Adding adma%d to platform device list\n", i); + switch (init_adma & (1 << i)) { + case IOP13XX_INIT_ADMA_0: + iop13xx_adma_0_channel.id = adma_idx++; + iop13xx_devices[plat_idx++] = &iop13xx_adma_0_channel; + plat_data = &iop13xx_adma_0_data; + dma_cap_set(DMA_MEMCPY, plat_data->cap_mask); + dma_cap_set(DMA_XOR, plat_data->cap_mask); + dma_cap_set(DMA_DUAL_XOR, plat_data->cap_mask); + dma_cap_set(DMA_ZERO_SUM, plat_data->cap_mask); + dma_cap_set(DMA_MEMSET, plat_data->cap_mask); + dma_cap_set(DMA_MEMCPY_CRC32C, plat_data->cap_mask); + dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask); + break; + case IOP13XX_INIT_ADMA_1: + iop13xx_adma_1_channel.id = adma_idx++; + iop13xx_devices[plat_idx++] = &iop13xx_adma_1_channel; + plat_data = &iop13xx_adma_1_data; + dma_cap_set(DMA_MEMCPY, plat_data->cap_mask); + dma_cap_set(DMA_XOR, plat_data->cap_mask); + dma_cap_set(DMA_DUAL_XOR, plat_data->cap_mask); + dma_cap_set(DMA_ZERO_SUM, plat_data->cap_mask); + dma_cap_set(DMA_MEMSET, plat_data->cap_mask); + dma_cap_set(DMA_MEMCPY_CRC32C, plat_data->cap_mask); + dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask); + break; + case IOP13XX_INIT_ADMA_2: + iop13xx_adma_2_channel.id = adma_idx++; + iop13xx_devices[plat_idx++] = &iop13xx_adma_2_channel; + plat_data = &iop13xx_adma_2_data; + dma_cap_set(DMA_MEMCPY, plat_data->cap_mask); + dma_cap_set(DMA_XOR, plat_data->cap_mask); + dma_cap_set(DMA_DUAL_XOR, plat_data->cap_mask); + dma_cap_set(DMA_ZERO_SUM, plat_data->cap_mask); + dma_cap_set(DMA_MEMSET, plat_data->cap_mask); + dma_cap_set(DMA_MEMCPY_CRC32C, plat_data->cap_mask); + dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask); + dma_cap_set(DMA_PQ_XOR, plat_data->cap_mask); + dma_cap_set(DMA_PQ_UPDATE, plat_data->cap_mask); + dma_cap_set(DMA_PQ_ZERO_SUM, plat_data->cap_mask); + break; + } + } + #ifdef CONFIG_MTD_PHYSMAP iq8134x_flash_resource.end = iq8134x_flash_resource.start + iq8134x_probe_flash_size() - 1; @@ -399,5 +580,35 @@ static int __init iop13xx_init_i2c_setup(char *str) return 1; } +static int __init iop13xx_init_adma_setup(char *str) +{ + if (str) { + while (*str != '\0') { + switch (*str) { + case '0': + init_adma |= IOP13XX_INIT_ADMA_0; + break; + case '1': + init_adma |= IOP13XX_INIT_ADMA_1; + break; + case '2': + init_adma |= IOP13XX_INIT_ADMA_2; + break; + case ',': + case '=': + break; + default: + PRINTK("\"iop13xx_init_adma\" malformed" + " at character: \'%c\'", *str); + *(str + 1) = '\0'; + init_adma = IOP13XX_INIT_ADMA_DEFAULT; + } + str++; + } + } + return 1; +} + +__setup("iop13xx_init_adma", iop13xx_init_adma_setup); __setup("iop13xx_init_uart", iop13xx_init_uart_setup); __setup("iop13xx_init_i2c", iop13xx_init_i2c_setup); diff --git a/arch/arm/mach-iop13xx/tpmi.c b/arch/arm/mach-iop13xx/tpmi.c index d3dc278213da..2476347ea62f 100644 --- a/arch/arm/mach-iop13xx/tpmi.c +++ b/arch/arm/mach-iop13xx/tpmi.c @@ -29,13 +29,15 @@ #define IOP13XX_TPMI_MMR(dev) IOP13XX_REG_ADDR32_PHYS(0x48000 + (dev << 12)) #define IOP13XX_TPMI_MEM(dev) IOP13XX_REG_ADDR32_PHYS(0x60000 + (dev << 13)) #define IOP13XX_TPMI_CTRL(dev) IOP13XX_REG_ADDR32_PHYS(0x50000 + (dev << 10)) +#define IOP13XX_TPMI_IOP_CTRL(dev) (IOP13XX_TPMI_CTRL(dev) + 0x2000) #define IOP13XX_TPMI_MMR_SIZE (SZ_4K - 1) #define IOP13XX_TPMI_MEM_SIZE (255) #define IOP13XX_TPMI_MEM_CTRL (SZ_1K - 1) #define IOP13XX_TPMI_RESOURCE_MMR 0 #define IOP13XX_TPMI_RESOURCE_MEM 1 #define IOP13XX_TPMI_RESOURCE_CTRL 2 -#define IOP13XX_TPMI_RESOURCE_IRQ 3 +#define IOP13XX_TPMI_RESOURCE_IOP_CTRL 3 +#define IOP13XX_TPMI_RESOURCE_IRQ 4 static struct resource iop13xx_tpmi_0_resources[] = { [IOP13XX_TPMI_RESOURCE_MMR] = { @@ -53,6 +55,11 @@ static struct resource iop13xx_tpmi_0_resources[] = { .end = IOP13XX_TPMI_CTRL(0) + IOP13XX_TPMI_MEM_CTRL, .flags = IORESOURCE_MEM, }, + [IOP13XX_TPMI_RESOURCE_IOP_CTRL] = { + .start = IOP13XX_TPMI_IOP_CTRL(0), + .end = IOP13XX_TPMI_IOP_CTRL(0) + IOP13XX_TPMI_MEM_CTRL, + .flags = IORESOURCE_MEM, + }, [IOP13XX_TPMI_RESOURCE_IRQ] = { .start = IRQ_IOP13XX_TPMI0_OUT, .end = IRQ_IOP13XX_TPMI0_OUT, @@ -76,6 +83,11 @@ static struct resource iop13xx_tpmi_1_resources[] = { .end = IOP13XX_TPMI_CTRL(1) + IOP13XX_TPMI_MEM_CTRL, .flags = IORESOURCE_MEM, }, + [IOP13XX_TPMI_RESOURCE_IOP_CTRL] = { + .start = IOP13XX_TPMI_IOP_CTRL(1), + .end = IOP13XX_TPMI_IOP_CTRL(1) + IOP13XX_TPMI_MEM_CTRL, + .flags = IORESOURCE_MEM, + }, [IOP13XX_TPMI_RESOURCE_IRQ] = { .start = IRQ_IOP13XX_TPMI1_OUT, .end = IRQ_IOP13XX_TPMI1_OUT, @@ -99,6 +111,11 @@ static struct resource iop13xx_tpmi_2_resources[] = { .end = IOP13XX_TPMI_CTRL(2) + IOP13XX_TPMI_MEM_CTRL, .flags = IORESOURCE_MEM, }, + [IOP13XX_TPMI_RESOURCE_IOP_CTRL] = { + .start = IOP13XX_TPMI_IOP_CTRL(2), + .end = IOP13XX_TPMI_IOP_CTRL(2) + IOP13XX_TPMI_MEM_CTRL, + .flags = IORESOURCE_MEM, + }, [IOP13XX_TPMI_RESOURCE_IRQ] = { .start = IRQ_IOP13XX_TPMI2_OUT, .end = IRQ_IOP13XX_TPMI2_OUT, @@ -122,6 +139,11 @@ static struct resource iop13xx_tpmi_3_resources[] = { .end = IOP13XX_TPMI_CTRL(3) + IOP13XX_TPMI_MEM_CTRL, .flags = IORESOURCE_MEM, }, + [IOP13XX_TPMI_RESOURCE_IOP_CTRL] = { + .start = IOP13XX_TPMI_IOP_CTRL(3), + .end = IOP13XX_TPMI_IOP_CTRL(3) + IOP13XX_TPMI_MEM_CTRL, + .flags = IORESOURCE_MEM, + }, [IOP13XX_TPMI_RESOURCE_IRQ] = { .start = IRQ_IOP13XX_TPMI3_OUT, .end = IRQ_IOP13XX_TPMI3_OUT, @@ -133,7 +155,7 @@ u64 iop13xx_tpmi_mask = DMA_64BIT_MASK; static struct platform_device iop13xx_tpmi_0_device = { .name = "iop-tpmi", .id = 0, - .num_resources = 4, + .num_resources = ARRAY_SIZE(iop13xx_tpmi_0_resources), .resource = iop13xx_tpmi_0_resources, .dev = { .dma_mask = &iop13xx_tpmi_mask, @@ -144,7 +166,7 @@ static struct platform_device iop13xx_tpmi_0_device = { static struct platform_device iop13xx_tpmi_1_device = { .name = "iop-tpmi", .id = 1, - .num_resources = 4, + .num_resources = ARRAY_SIZE(iop13xx_tpmi_1_resources), .resource = iop13xx_tpmi_1_resources, .dev = { .dma_mask = &iop13xx_tpmi_mask, @@ -155,7 +177,7 @@ static struct platform_device iop13xx_tpmi_1_device = { static struct platform_device iop13xx_tpmi_2_device = { .name = "iop-tpmi", .id = 2, - .num_resources = 4, + .num_resources = ARRAY_SIZE(iop13xx_tpmi_2_resources), .resource = iop13xx_tpmi_2_resources, .dev = { .dma_mask = &iop13xx_tpmi_mask, @@ -166,7 +188,7 @@ static struct platform_device iop13xx_tpmi_2_device = { static struct platform_device iop13xx_tpmi_3_device = { .name = "iop-tpmi", .id = 3, - .num_resources = 4, + .num_resources = ARRAY_SIZE(iop13xx_tpmi_3_resources), .resource = iop13xx_tpmi_3_resources, .dev = { .dma_mask = &iop13xx_tpmi_mask, diff --git a/arch/arm/mach-iop32x/Kconfig b/arch/arm/mach-iop32x/Kconfig index 9bb02b6d7ae1..dbe07c9472ed 100644 --- a/arch/arm/mach-iop32x/Kconfig +++ b/arch/arm/mach-iop32x/Kconfig @@ -42,6 +42,13 @@ config IOP3XX_ATU Say N if the IOP is an add in card, the host system owns the PCI bus in this case. +config MACH_EM7210 + bool "Enable support for the Lanner EM7210" + help + Say Y here if you want to run your kernel on the Lanner EM7210 + board. Say also Y here if you have a SS4000e Baxter Creek NAS + appliance." + endmenu endif diff --git a/arch/arm/mach-iop32x/Makefile b/arch/arm/mach-iop32x/Makefile index 7b05b37e1f94..cfdf8a137c2b 100644 --- a/arch/arm/mach-iop32x/Makefile +++ b/arch/arm/mach-iop32x/Makefile @@ -11,3 +11,4 @@ obj-$(CONFIG_MACH_GLANTANK) += glantank.o obj-$(CONFIG_ARCH_IQ80321) += iq80321.o obj-$(CONFIG_ARCH_IQ31244) += iq31244.o obj-$(CONFIG_MACH_N2100) += n2100.o +obj-$(CONFIG_MACH_EM7210) += em7210.o diff --git a/arch/arm/mach-iop32x/em7210.c b/arch/arm/mach-iop32x/em7210.c new file mode 100644 index 000000000000..c947152f9a3c --- /dev/null +++ b/arch/arm/mach-iop32x/em7210.c @@ -0,0 +1,215 @@ +/* + * arch/arm/mach-iop32x/em7210.c + * + * Board support code for the Lanner EM7210 platforms. + * + * Based on arch/arm/mach-iop32x/iq31244.c file. + * + * Copyright (C) 2007 Arnaud Patard <arnaud.patard@rtp-net.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <linux/mm.h> +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/pci.h> +#include <linux/pm.h> +#include <linux/serial_core.h> +#include <linux/serial_8250.h> +#include <linux/mtd/physmap.h> +#include <linux/platform_device.h> +#include <linux/i2c.h> +#include <asm/hardware.h> +#include <linux/io.h> +#include <linux/irq.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/pci.h> +#include <asm/mach/time.h> +#include <asm/mach-types.h> +#include <asm/arch/time.h> + +static void __init em7210_timer_init(void) +{ + /* http://www.kwaak.net/fotos/fotos-nas/slide_24.html */ + /* 33.333 MHz crystal. */ + iop_init_time(200000000); +} + +static struct sys_timer em7210_timer = { + .init = em7210_timer_init, + .offset = iop_gettimeoffset, +}; + +/* + * EM7210 RTC + */ +static struct i2c_board_info __initdata em7210_i2c_devices[] = { + { + I2C_BOARD_INFO("rtc-rs5c372", 0x32), + .type = "rs5c372a", + }, +}; + +/* + * EM7210 I/O + */ +static struct map_desc em7210_io_desc[] __initdata = { + { /* on-board devices */ + .virtual = IQ31244_UART, + .pfn = __phys_to_pfn(IQ31244_UART), + .length = 0x00100000, + .type = MT_DEVICE, + }, +}; + +void __init em7210_map_io(void) +{ + iop3xx_map_io(); + iotable_init(em7210_io_desc, ARRAY_SIZE(em7210_io_desc)); +} + + +/* + * EM7210 PCI + */ +#define INTA IRQ_IOP32X_XINT0 +#define INTB IRQ_IOP32X_XINT1 +#define INTC IRQ_IOP32X_XINT2 +#define INTD IRQ_IOP32X_XINT3 + +static int __init +em7210_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + static int pci_irq_table[][4] = { + /* + * PCI IDSEL/INTPIN->INTLINE + * A B C D + */ + {INTB, INTB, INTB, INTB}, /* console / uart */ + {INTA, INTA, INTA, INTA}, /* 1st 82541 */ + {INTD, INTD, INTD, INTD}, /* 2nd 82541 */ + {INTC, INTC, INTC, INTC}, /* GD31244 */ + {INTD, INTA, INTA, INTA}, /* mini-PCI */ + {INTD, INTC, INTA, INTA}, /* NEC USB */ + }; + + if (pin < 1 || pin > 4) + return -1; + + return pci_irq_table[slot % 6][pin - 1]; +} + +static struct hw_pci em7210_pci __initdata = { + .swizzle = pci_std_swizzle, + .nr_controllers = 1, + .setup = iop3xx_pci_setup, + .preinit = iop3xx_pci_preinit, + .scan = iop3xx_pci_scan_bus, + .map_irq = em7210_pci_map_irq, +}; + +static int __init em7210_pci_init(void) +{ + if (machine_is_em7210()) + pci_common_init(&em7210_pci); + + return 0; +} + +subsys_initcall(em7210_pci_init); + + +/* + * EM7210 Flash + */ +static struct physmap_flash_data em7210_flash_data = { + .width = 2, +}; + +static struct resource em7210_flash_resource = { + .start = 0xf0000000, + .end = 0xf1ffffff, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device em7210_flash_device = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &em7210_flash_data, + }, + .num_resources = 1, + .resource = &em7210_flash_resource, +}; + + +/* + * EM7210 UART + * The physical address of the serial port is 0xfe800000, + * so it can be used for physical and virtual address. + */ +static struct plat_serial8250_port em7210_serial_port[] = { + { + .mapbase = IQ31244_UART, + .membase = (char *)IQ31244_UART, + .irq = IRQ_IOP32X_XINT1, + .flags = UPF_SKIP_TEST, + .iotype = UPIO_MEM, + .regshift = 0, + .uartclk = 1843200, + }, + { }, +}; + +static struct resource em7210_uart_resource = { + .start = IQ31244_UART, + .end = IQ31244_UART + 7, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device em7210_serial_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = em7210_serial_port, + }, + .num_resources = 1, + .resource = &em7210_uart_resource, +}; + +void em7210_power_off(void) +{ + *IOP3XX_GPOE &= 0xfe; + *IOP3XX_GPOD |= 0x01; +} + +static void __init em7210_init_machine(void) +{ + platform_device_register(&em7210_serial_device); + platform_device_register(&iop3xx_i2c0_device); + platform_device_register(&iop3xx_i2c1_device); + platform_device_register(&em7210_flash_device); + platform_device_register(&iop3xx_dma_0_channel); + platform_device_register(&iop3xx_dma_1_channel); + + i2c_register_board_info(0, em7210_i2c_devices, + ARRAY_SIZE(em7210_i2c_devices)); + + + pm_power_off = em7210_power_off; +} + +MACHINE_START(EM7210, "Lanner EM7210") + .phys_io = IQ31244_UART, + .io_pg_offst = ((IQ31244_UART) >> 18) & 0xfffc, + .boot_params = 0xa0000100, + .map_io = em7210_map_io, + .init_irq = iop32x_init_irq, + .timer = &em7210_timer, + .init_machine = em7210_init_machine, +MACHINE_END diff --git a/arch/arm/mach-iop32x/glantank.c b/arch/arm/mach-iop32x/glantank.c index 5776fd884115..2b086ab2668c 100644 --- a/arch/arm/mach-iop32x/glantank.c +++ b/arch/arm/mach-iop32x/glantank.c @@ -180,6 +180,8 @@ static void __init glantank_init_machine(void) platform_device_register(&iop3xx_i2c1_device); platform_device_register(&glantank_flash_device); platform_device_register(&glantank_serial_device); + platform_device_register(&iop3xx_dma_0_channel); + platform_device_register(&iop3xx_dma_1_channel); pm_power_off = glantank_power_off; } diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c index d4eefbea1fe6..98cfa1cd6bdb 100644 --- a/arch/arm/mach-iop32x/iq31244.c +++ b/arch/arm/mach-iop32x/iq31244.c @@ -298,9 +298,14 @@ static void __init iq31244_init_machine(void) platform_device_register(&iop3xx_i2c1_device); platform_device_register(&iq31244_flash_device); platform_device_register(&iq31244_serial_device); + platform_device_register(&iop3xx_dma_0_channel); + platform_device_register(&iop3xx_dma_1_channel); if (is_ep80219()) pm_power_off = ep80219_power_off; + + if (!is_80219()) + platform_device_register(&iop3xx_aau_channel); } static int __init force_ep80219_setup(char *str) diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c index 8d9f49164a84..18ad29f213b2 100644 --- a/arch/arm/mach-iop32x/iq80321.c +++ b/arch/arm/mach-iop32x/iq80321.c @@ -181,6 +181,9 @@ static void __init iq80321_init_machine(void) platform_device_register(&iop3xx_i2c1_device); platform_device_register(&iq80321_flash_device); platform_device_register(&iq80321_serial_device); + platform_device_register(&iop3xx_dma_0_channel); + platform_device_register(&iop3xx_dma_1_channel); + platform_device_register(&iop3xx_aau_channel); } MACHINE_START(IQ80321, "Intel IQ80321") diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c index c971171c2905..55cf0162e8c1 100644 --- a/arch/arm/mach-iop32x/irq.c +++ b/arch/arm/mach-iop32x/irq.c @@ -63,7 +63,8 @@ void __init iop32x_init_irq(void) if (machine_is_glantank() || machine_is_iq80321() || machine_is_iq31244() || - machine_is_n2100()) + machine_is_n2100() || + machine_is_em7210()) *IOP3XX_PCIIRSR = 0x0f; for (i = 0; i < NR_IRQS; i++) { diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c index d55005d64781..1873bd8cd1b2 100644 --- a/arch/arm/mach-iop32x/n2100.c +++ b/arch/arm/mach-iop32x/n2100.c @@ -25,6 +25,7 @@ #include <linux/serial_core.h> #include <linux/serial_8250.h> #include <linux/mtd/physmap.h> +#include <linux/i2c.h> #include <linux/platform_device.h> #include <linux/reboot.h> #include <asm/hardware.h> @@ -199,6 +200,12 @@ static struct platform_device n2100_serial_device = { .resource = &n2100_uart_resource, }; +static struct i2c_board_info __initdata n2100_i2c_devices[] = { + { + I2C_BOARD_INFO("rtc-rs5c372", 0x32), + .type = "rs5c372b", + }, +}; /* * Pull PCA9532 GPIO #8 low to power off the machine. @@ -245,6 +252,11 @@ static void __init n2100_init_machine(void) platform_device_register(&iop3xx_i2c0_device); platform_device_register(&n2100_flash_device); platform_device_register(&n2100_serial_device); + platform_device_register(&iop3xx_dma_0_channel); + platform_device_register(&iop3xx_dma_1_channel); + + i2c_register_board_info(0, n2100_i2c_devices, + ARRAY_SIZE(n2100_i2c_devices)); pm_power_off = n2100_power_off; diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c index 2b063180687a..433188ebff2a 100644 --- a/arch/arm/mach-iop33x/iq80331.c +++ b/arch/arm/mach-iop33x/iq80331.c @@ -136,6 +136,9 @@ static void __init iq80331_init_machine(void) platform_device_register(&iop33x_uart0_device); platform_device_register(&iop33x_uart1_device); platform_device_register(&iq80331_flash_device); + platform_device_register(&iop3xx_dma_0_channel); + platform_device_register(&iop3xx_dma_1_channel); + platform_device_register(&iop3xx_aau_channel); } MACHINE_START(IQ80331, "Intel IQ80331") diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c index 7889ce3cb08e..416c09564cc6 100644 --- a/arch/arm/mach-iop33x/iq80332.c +++ b/arch/arm/mach-iop33x/iq80332.c @@ -136,6 +136,9 @@ static void __init iq80332_init_machine(void) platform_device_register(&iop33x_uart0_device); platform_device_register(&iop33x_uart1_device); platform_device_register(&iq80332_flash_device); + platform_device_register(&iop3xx_dma_0_channel); + platform_device_register(&iop3xx_dma_1_channel); + platform_device_register(&iop3xx_aau_channel); } MACHINE_START(IQ80332, "Intel IQ80332") diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig index 060909870b50..61b2dfcb89d6 100644 --- a/arch/arm/mach-ixp4xx/Kconfig +++ b/arch/arm/mach-ixp4xx/Kconfig @@ -41,6 +41,22 @@ config ARCH_ADI_COYOTE Engineering Coyote Gateway Reference Platform. For more information on this platform, see <file:Documentation/arm/IXP4xx>. +config MACH_GATEWAY7001 + bool "Gateway 7001" + select PCI + help + Say 'Y' here if you want your kernel to support Gateway's + 7001 Access Point. For more information on this platform, + see http://openwrt.org + +config MACH_WG302V2 + bool "Netgear WG302 v2 / WAG302 v2" + select PCI + help + Say 'Y' here if you want your kernel to support Netgear's + WG302 v2 or WAG302 v2 Access Points. For more information + on this platform, see http://openwrt.org + config ARCH_IXDP425 bool "IXDP425" help diff --git a/arch/arm/mach-ixp4xx/Makefile b/arch/arm/mach-ixp4xx/Makefile index 3b87c47e06cf..77e00ade5585 100644 --- a/arch/arm/mach-ixp4xx/Makefile +++ b/arch/arm/mach-ixp4xx/Makefile @@ -13,6 +13,8 @@ obj-pci-$(CONFIG_MACH_GTWX5715) += gtwx5715-pci.o obj-pci-$(CONFIG_MACH_NSLU2) += nslu2-pci.o obj-pci-$(CONFIG_MACH_NAS100D) += nas100d-pci.o obj-pci-$(CONFIG_MACH_DSMG600) += dsmg600-pci.o +obj-pci-$(CONFIG_MACH_GATEWAY7001) += gateway7001-pci.o +obj-pci-$(CONFIG_MACH_WG302V2) += wg302v2-pci.o obj-y += common.o @@ -24,5 +26,7 @@ obj-$(CONFIG_MACH_GTWX5715) += gtwx5715-setup.o obj-$(CONFIG_MACH_NSLU2) += nslu2-setup.o nslu2-power.o obj-$(CONFIG_MACH_NAS100D) += nas100d-setup.o nas100d-power.o obj-$(CONFIG_MACH_DSMG600) += dsmg600-setup.o dsmg600-power.o +obj-$(CONFIG_MACH_GATEWAY7001) += gateway7001-setup.o +obj-$(CONFIG_MACH_WG302V2) += wg302v2-setup.o obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c index 8112f726ffa0..c1271c449246 100644 --- a/arch/arm/mach-ixp4xx/common.c +++ b/arch/arm/mach-ixp4xx/common.c @@ -188,7 +188,7 @@ static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type) *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE)); /* Configure the line as an input */ - gpio_line_config(line, IXP4XX_GPIO_IN); + gpio_line_config(irq2gpio[irq], IXP4XX_GPIO_IN); return 0; } @@ -459,6 +459,8 @@ static void ixp4xx_set_mode(enum clock_event_mode mode, default: osrt = opts = 0; break; + case CLOCK_EVT_MODE_RESUME: + break; } *IXP4XX_OSRT1 = osrt | opts; diff --git a/arch/arm/mach-ixp4xx/gateway7001-pci.c b/arch/arm/mach-ixp4xx/gateway7001-pci.c new file mode 100644 index 000000000000..6abf568322d3 --- /dev/null +++ b/arch/arm/mach-ixp4xx/gateway7001-pci.c @@ -0,0 +1,63 @@ +/* + * arch/arch/mach-ixp4xx/gateway7001-pci.c + * + * PCI setup routines for Gateway 7001 + * + * Copyright (C) 2007 Imre Kaloz <kaloz@openwrt.org> + * + * based on coyote-pci.c: + * Copyright (C) 2002 Jungo Software Technologies. + * Copyright (C) 2003 MontaVista Softwrae, Inc. + * + * Maintainer: Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <linux/kernel.h> +#include <linux/pci.h> +#include <linux/init.h> +#include <linux/irq.h> + +#include <asm/mach-types.h> +#include <asm/hardware.h> + +#include <asm/mach/pci.h> + +void __init gateway7001_pci_preinit(void) +{ + set_irq_type(IRQ_IXP4XX_GPIO10, IRQT_LOW); + set_irq_type(IRQ_IXP4XX_GPIO11, IRQT_LOW); + + ixp4xx_pci_preinit(); +} + +static int __init gateway7001_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + if (slot == 1) + return IRQ_IXP4XX_GPIO11; + else if (slot == 2) + return IRQ_IXP4XX_GPIO10; + else return -1; +} + +struct hw_pci gateway7001_pci __initdata = { + .nr_controllers = 1, + .preinit = gateway7001_pci_preinit, + .swizzle = pci_std_swizzle, + .setup = ixp4xx_setup, + .scan = ixp4xx_scan_bus, + .map_irq = gateway7001_map_irq, +}; + +int __init gateway7001_pci_init(void) +{ + if (machine_is_gateway7001()) + pci_common_init(&gateway7001_pci); + return 0; +} + +subsys_initcall(gateway7001_pci_init); diff --git a/arch/arm/mach-ixp4xx/gateway7001-setup.c b/arch/arm/mach-ixp4xx/gateway7001-setup.c new file mode 100644 index 000000000000..37876832e141 --- /dev/null +++ b/arch/arm/mach-ixp4xx/gateway7001-setup.c @@ -0,0 +1,108 @@ +/* + * arch/arm/mach-ixp4xx/gateway7001-setup.c + * + * Board setup for the Gateway 7001 board + * + * Copyright (C) 2007 Imre Kaloz <kaloz@openwrt.org> + * + * based on coyote-setup.c: + * Copyright (C) 2003-2005 MontaVista Software, Inc. + * + * Author: Imre Kaloz <Kaloz@openwrt.org> + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/device.h> +#include <linux/serial.h> +#include <linux/tty.h> +#include <linux/serial_8250.h> +#include <linux/slab.h> + +#include <asm/types.h> +#include <asm/setup.h> +#include <asm/memory.h> +#include <asm/hardware.h> +#include <asm/irq.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/flash.h> + +static struct flash_platform_data gateway7001_flash_data = { + .map_name = "cfi_probe", + .width = 2, +}; + +static struct resource gateway7001_flash_resource = { + .flags = IORESOURCE_MEM, +}; + +static struct platform_device gateway7001_flash = { + .name = "IXP4XX-Flash", + .id = 0, + .dev = { + .platform_data = &gateway7001_flash_data, + }, + .num_resources = 1, + .resource = &gateway7001_flash_resource, +}; + +static struct resource gateway7001_uart_resource = { + .start = IXP4XX_UART2_BASE_PHYS, + .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, + .flags = IORESOURCE_MEM, +}; + +static struct plat_serial8250_port gateway7001_uart_data[] = { + { + .mapbase = IXP4XX_UART2_BASE_PHYS, + .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, + .irq = IRQ_IXP4XX_UART2, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = IXP4XX_UART_XTAL, + }, + { }, +}; + +static struct platform_device gateway7001_uart = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = gateway7001_uart_data, + }, + .num_resources = 1, + .resource = &gateway7001_uart_resource, +}; + +static struct platform_device *gateway7001_devices[] __initdata = { + &gateway7001_flash, + &gateway7001_uart +}; + +static void __init gateway7001_init(void) +{ + ixp4xx_sys_init(); + + gateway7001_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); + gateway7001_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1; + + *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE; + *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0; + + platform_add_devices(gateway7001_devices, ARRAY_SIZE(gateway7001_devices)); +} + +#ifdef CONFIG_MACH_GATEWAY7001 +MACHINE_START(GATEWAY7001, "Gateway 7001 AP") + /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */ + .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, + .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, + .map_io = ixp4xx_map_io, + .init_irq = ixp4xx_init_irq, + .timer = &ixp4xx_timer, + .boot_params = 0x0100, + .init_machine = gateway7001_init, +MACHINE_END +#endif diff --git a/arch/arm/mach-ixp4xx/gtwx5715-pci.c b/arch/arm/mach-ixp4xx/gtwx5715-pci.c index a66484b63d36..0d5a42455820 100644 --- a/arch/arm/mach-ixp4xx/gtwx5715-pci.c +++ b/arch/arm/mach-ixp4xx/gtwx5715-pci.c @@ -25,17 +25,13 @@ #include <linux/pci.h> #include <linux/init.h> #include <linux/delay.h> +#include <linux/irq.h> + #include <asm/mach-types.h> #include <asm/hardware.h> -#include <asm/irq.h> #include <asm/arch/gtwx5715.h> #include <asm/mach/pci.h> -extern void ixp4xx_pci_preinit(void); -extern int ixp4xx_setup(int nr, struct pci_sys_data *sys); -extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys); - - /* * The exact GPIO pins and IRQs are defined in arch-ixp4xx/gtwx5715.h * Slot 0 isn't actually populated with a card connector but diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c index ec4f07950ec6..d5008d8fc9a5 100644 --- a/arch/arm/mach-ixp4xx/ixdp425-setup.c +++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c @@ -15,6 +15,10 @@ #include <linux/tty.h> #include <linux/serial_8250.h> #include <linux/slab.h> +#include <linux/io.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/partitions.h> #include <asm/types.h> #include <asm/setup.h> @@ -24,6 +28,7 @@ #include <asm/irq.h> #include <asm/mach/arch.h> #include <asm/mach/flash.h> +#include <asm/delay.h> static struct flash_platform_data ixdp425_flash_data = { .map_name = "cfi_probe", @@ -44,6 +49,77 @@ static struct platform_device ixdp425_flash = { .resource = &ixdp425_flash_resource, }; +#if defined(CONFIG_MTD_NAND_PLATFORM) || \ + defined(CONFIG_MTD_NAND_PLATFORM_MODULE) + +#ifdef CONFIG_MTD_PARTITIONS +const char *part_probes[] = { "cmdlinepart", NULL }; + +static struct mtd_partition ixdp425_partitions[] = { + { + .name = "ixp400 NAND FS 0", + .offset = 0, + .size = SZ_8M + }, { + .name = "ixp400 NAND FS 1", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL + }, +}; +#endif + +static void +ixdp425_flash_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + int offset = (int)this->priv; + + if (ctrl & NAND_CTRL_CHANGE) { + if (ctrl & NAND_NCE) { + gpio_line_set(IXDP425_NAND_NCE_PIN, IXP4XX_GPIO_LOW); + udelay(5); + } else + gpio_line_set(IXDP425_NAND_NCE_PIN, IXP4XX_GPIO_HIGH); + + offset = (ctrl & NAND_CLE) ? IXDP425_NAND_CMD_BYTE : 0; + offset |= (ctrl & NAND_ALE) ? IXDP425_NAND_ADDR_BYTE : 0; + this->priv = (void *)offset; + } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W + offset); +} + +static struct platform_nand_data ixdp425_flash_nand_data = { + .chip = { + .chip_delay = 30, + .options = NAND_NO_AUTOINCR, +#ifdef CONFIG_MTD_PARTITIONS + .part_probe_types = part_probes, + .partitions = ixdp425_partitions, + .nr_partitions = ARRAY_SIZE(ixdp425_partitions), +#endif + }, + .ctrl = { + .cmd_ctrl = ixdp425_flash_nand_cmd_ctrl + } +}; + +static struct resource ixdp425_flash_nand_resource = { + .flags = IORESOURCE_MEM, +}; + +static struct platform_device ixdp425_flash_nand = { + .name = "gen_nand", + .id = -1, + .dev = { + .platform_data = &ixdp425_flash_nand_data, + }, + .num_resources = 1, + .resource = &ixdp425_flash_nand_resource, +}; +#endif /* CONFIG_MTD_NAND_PLATFORM */ + static struct ixp4xx_i2c_pins ixdp425_i2c_gpio_pins = { .sda_pin = IXDP425_SDA_PIN, .scl_pin = IXDP425_SCL_PIN, @@ -104,6 +180,10 @@ static struct platform_device ixdp425_uart = { static struct platform_device *ixdp425_devices[] __initdata = { &ixdp425_i2c_controller, &ixdp425_flash, +#if defined(CONFIG_MTD_NAND_PLATFORM) || \ + defined(CONFIG_MTD_NAND_PLATFORM_MODULE) + &ixdp425_flash_nand, +#endif &ixdp425_uart }; @@ -115,6 +195,22 @@ static void __init ixdp425_init(void) ixdp425_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1; +#if defined(CONFIG_MTD_NAND_PLATFORM) || \ + defined(CONFIG_MTD_NAND_PLATFORM_MODULE) + ixdp425_flash_nand_resource.start = IXP4XX_EXP_BUS_BASE(3), + ixdp425_flash_nand_resource.end = IXP4XX_EXP_BUS_BASE(3) + 0x10 - 1; + + gpio_line_config(IXDP425_NAND_NCE_PIN, IXP4XX_GPIO_OUT); + + /* Configure expansion bus for NAND Flash */ + *IXP4XX_EXP_CS3 = IXP4XX_EXP_BUS_CS_EN | + IXP4XX_EXP_BUS_STROBE_T(1) | /* extend by 1 clock */ + IXP4XX_EXP_BUS_CYCLES(0) | /* Intel cycles */ + IXP4XX_EXP_BUS_SIZE(0) | /* 512bytes addr space*/ + IXP4XX_EXP_BUS_WR_EN | + IXP4XX_EXP_BUS_BYTE_EN; /* 8 bit data bus */ +#endif + if (cpu_is_ixp43x()) { ixdp425_uart.num_resources = 1; ixdp425_uart_data[1].flags = 0; diff --git a/arch/arm/mach-ixp4xx/wg302v2-pci.c b/arch/arm/mach-ixp4xx/wg302v2-pci.c new file mode 100644 index 000000000000..6588f2c758e2 --- /dev/null +++ b/arch/arm/mach-ixp4xx/wg302v2-pci.c @@ -0,0 +1,63 @@ +/* + * arch/arch/mach-ixp4xx/wg302v2-pci.c + * + * PCI setup routines for the Netgear WG302 v2 and WAG302 v2 + * + * Copyright (C) 2007 Imre Kaloz <kaloz@openwrt.org> + * + * based on coyote-pci.c: + * Copyright (C) 2002 Jungo Software Technologies. + * Copyright (C) 2003 MontaVista Software, Inc. + * + * Maintainer: Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <linux/kernel.h> +#include <linux/pci.h> +#include <linux/init.h> +#include <linux/irq.h> + +#include <asm/mach-types.h> +#include <asm/hardware.h> + +#include <asm/mach/pci.h> + +void __init wg302v2_pci_preinit(void) +{ + set_irq_type(IRQ_IXP4XX_GPIO8, IRQT_LOW); + set_irq_type(IRQ_IXP4XX_GPIO9, IRQT_LOW); + + ixp4xx_pci_preinit(); +} + +static int __init wg302v2_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + if (slot == 1) + return IRQ_IXP4XX_GPIO8; + else if (slot == 2) + return IRQ_IXP4XX_GPIO9; + else return -1; +} + +struct hw_pci wg302v2_pci __initdata = { + .nr_controllers = 1, + .preinit = wg302v2_pci_preinit, + .swizzle = pci_std_swizzle, + .setup = ixp4xx_setup, + .scan = ixp4xx_scan_bus, + .map_irq = wg302v2_map_irq, +}; + +int __init wg302v2_pci_init(void) +{ + if (machine_is_wg302v2()) + pci_common_init(&wg302v2_pci); + return 0; +} + +subsys_initcall(wg302v2_pci_init); diff --git a/arch/arm/mach-ixp4xx/wg302v2-setup.c b/arch/arm/mach-ixp4xx/wg302v2-setup.c new file mode 100644 index 000000000000..f7e09ad804e8 --- /dev/null +++ b/arch/arm/mach-ixp4xx/wg302v2-setup.c @@ -0,0 +1,109 @@ +/* + * arch/arm/mach-ixp4xx/wg302-setup.c + * + * Board setup for the Netgear WG302 v2 and WAG302 v2 + * + * Copyright (C) 2007 Imre Kaloz <Kaloz@openwrt.org> + * + * based on coyote-setup.c: + * Copyright (C) 2003-2005 MontaVista Software, Inc. + * + * Author: Imre Kaloz <kaloz@openwrt.org> + * + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/device.h> +#include <linux/serial.h> +#include <linux/tty.h> +#include <linux/serial_8250.h> +#include <linux/slab.h> + +#include <asm/types.h> +#include <asm/setup.h> +#include <asm/memory.h> +#include <asm/hardware.h> +#include <asm/irq.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/flash.h> + +static struct flash_platform_data wg302v2_flash_data = { + .map_name = "cfi_probe", + .width = 2, +}; + +static struct resource wg302v2_flash_resource = { + .flags = IORESOURCE_MEM, +}; + +static struct platform_device wg302v2_flash = { + .name = "IXP4XX-Flash", + .id = 0, + .dev = { + .platform_data = &wg302v2_flash_data, + }, + .num_resources = 1, + .resource = &wg302v2_flash_resource, +}; + +static struct resource wg302v2_uart_resource = { + .start = IXP4XX_UART2_BASE_PHYS, + .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, + .flags = IORESOURCE_MEM, +}; + +static struct plat_serial8250_port wg302v2_uart_data[] = { + { + .mapbase = IXP4XX_UART2_BASE_PHYS, + .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, + .irq = IRQ_IXP4XX_UART2, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = IXP4XX_UART_XTAL, + }, + { }, +}; + +static struct platform_device wg302v2_uart = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = wg302v2_uart_data, + }, + .num_resources = 1, + .resource = &wg302v2_uart_resource, +}; + +static struct platform_device *wg302v2_devices[] __initdata = { + &wg302v2_flash, + &wg302v2_uart, +}; + +static void __init wg302v2_init(void) +{ + ixp4xx_sys_init(); + + wg302v2_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); + wg302v2_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1; + + *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE; + *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0; + + platform_add_devices(wg302v2_devices, ARRAY_SIZE(wg302v2_devices)); +} + +#ifdef CONFIG_MACH_WG302V2 +MACHINE_START(WG302V2, "Netgear WG302 v2 / WAG302 v2") + /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */ + .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, + .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, + .map_io = ixp4xx_map_io, + .init_irq = ixp4xx_init_irq, + .timer = &ixp4xx_timer, + .boot_params = 0x0100, + .init_machine = wg302v2_init, +MACHINE_END +#endif diff --git a/arch/arm/mach-ks8695/Makefile b/arch/arm/mach-ks8695/Makefile index 56b7d337333a..2a07a281fa8a 100644 --- a/arch/arm/mach-ks8695/Makefile +++ b/arch/arm/mach-ks8695/Makefile @@ -3,7 +3,7 @@ # Makefile for KS8695 architecture support # -obj-y := cpu.o irq.o time.o devices.o +obj-y := cpu.o irq.o time.o gpio.o devices.o obj-m := obj-n := obj- := diff --git a/arch/arm/mach-ks8695/gpio.c b/arch/arm/mach-ks8695/gpio.c new file mode 100644 index 000000000000..b1aa3cb3d4a3 --- /dev/null +++ b/arch/arm/mach-ks8695/gpio.c @@ -0,0 +1,218 @@ +/* + * arch/arm/mach-ks8695/gpio.c + * + * Copyright (C) 2006 Andrew Victor + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/kernel.h> +#include <linux/mm.h> +#include <linux/init.h> +#include <linux/module.h> + +#include <asm/io.h> +#include <asm/hardware.h> +#include <asm/mach/irq.h> + +#include <asm/arch/regs-gpio.h> +#include <asm/arch/gpio.h> + +/* + * Configure a GPIO line for either GPIO function, or its internal + * function (Interrupt, Timer, etc). + */ +static void __init_or_module ks8695_gpio_mode(unsigned int pin, short gpio) +{ + unsigned int enable[] = { IOPC_IOEINT0EN, IOPC_IOEINT1EN, IOPC_IOEINT2EN, IOPC_IOEINT3EN, IOPC_IOTIM0EN, IOPC_IOTIM1EN }; + unsigned long x, flags; + + if (pin > KS8695_GPIO_5) /* only GPIO 0..5 have internal functions */ + return; + + local_irq_save(flags); + + x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPC); + if (gpio) /* GPIO: set bit to 0 */ + x &= ~enable[pin]; + else /* Internal function: set bit to 1 */ + x |= enable[pin]; + __raw_writel(x, KS8695_GPIO_VA + KS8695_IOPC); + + local_irq_restore(flags); +} + + +static unsigned short gpio_irq[] = { KS8695_IRQ_EXTERN0, KS8695_IRQ_EXTERN1, KS8695_IRQ_EXTERN2, KS8695_IRQ_EXTERN3 }; + +/* + * Configure GPIO pin as external interrupt source. + */ +int __init_or_module ks8695_gpio_interrupt(unsigned int pin, unsigned int type) +{ + unsigned long x, flags; + + if (pin > KS8695_GPIO_3) /* only GPIO 0..3 can generate IRQ */ + return -EINVAL; + + local_irq_save(flags); + + /* set pin as input */ + x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPM); + x &= ~IOPM_(pin); + __raw_writel(x, KS8695_GPIO_VA + KS8695_IOPM); + + local_irq_restore(flags); + + /* Set IRQ triggering type */ + set_irq_type(gpio_irq[pin], type); + + /* enable interrupt mode */ + ks8695_gpio_mode(pin, 0); + + return 0; +} +EXPORT_SYMBOL(ks8695_gpio_interrupt); + + + +/* .... Generic GPIO interface .............................................. */ + +/* + * Configure the GPIO line as an input. + */ +int __init_or_module gpio_direction_input(unsigned int pin) +{ + unsigned long x, flags; + + if (pin > KS8695_GPIO_15) + return -EINVAL; + + /* set pin to GPIO mode */ + ks8695_gpio_mode(pin, 1); + + local_irq_save(flags); + + /* set pin as input */ + x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPM); + x &= ~IOPM_(pin); + __raw_writel(x, KS8695_GPIO_VA + KS8695_IOPM); + + local_irq_restore(flags); + + return 0; +} +EXPORT_SYMBOL(gpio_direction_input); + + +/* + * Configure the GPIO line as an output, with default state. + */ +int __init_or_module gpio_direction_output(unsigned int pin, unsigned int state) +{ + unsigned long x, flags; + + if (pin > KS8695_GPIO_15) + return -EINVAL; + + /* set pin to GPIO mode */ + ks8695_gpio_mode(pin, 1); + + local_irq_save(flags); + + /* set line state */ + x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPD); + if (state) + x |= (1 << pin); + else + x &= ~(1 << pin); + __raw_writel(x, KS8695_GPIO_VA + KS8695_IOPD); + + /* set pin as output */ + x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPM); + x |= IOPM_(pin); + __raw_writel(x, KS8695_GPIO_VA + KS8695_IOPM); + + local_irq_restore(flags); + + return 0; +} +EXPORT_SYMBOL(gpio_direction_output); + + +/* + * Set the state of an output GPIO line. + */ +void gpio_set_value(unsigned int pin, unsigned int state) +{ + unsigned long x, flags; + + if (pin > KS8695_GPIO_15) + return; + + local_irq_save(flags); + + /* set output line state */ + x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPD); + if (state) + x |= (1 << pin); + else + x &= ~(1 << pin); + __raw_writel(x, KS8695_GPIO_VA + KS8695_IOPD); + + local_irq_restore(flags); +} +EXPORT_SYMBOL(gpio_set_value); + + +/* + * Read the state of a GPIO line. + */ +int gpio_get_value(unsigned int pin) +{ + unsigned long x; + + if (pin > KS8695_GPIO_15) + return -EINVAL; + + x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPD); + return (x & (1 << pin)) != 0; +} +EXPORT_SYMBOL(gpio_get_value); + + +/* + * Map GPIO line to IRQ number. + */ +int gpio_to_irq(unsigned int pin) +{ + if (pin > KS8695_GPIO_3) /* only GPIO 0..3 can generate IRQ */ + return -EINVAL; + + return gpio_irq[pin]; +} +EXPORT_SYMBOL(gpio_to_irq); + + +/* + * Map IRQ number to GPIO line. + */ +int irq_to_gpio(unsigned int irq) +{ + if ((irq < KS8695_IRQ_EXTERN0) || (irq > KS8695_IRQ_EXTERN3)) + return -EINVAL; + + return (irq - KS8695_IRQ_EXTERN0); +} +EXPORT_SYMBOL(irq_to_gpio); diff --git a/arch/arm/mach-ks8695/irq.c b/arch/arm/mach-ks8695/irq.c index 2407bba00547..4c3ab43e1046 100644 --- a/arch/arm/mach-ks8695/irq.c +++ b/arch/arm/mach-ks8695/irq.c @@ -23,7 +23,6 @@ #include <linux/module.h> #include <linux/interrupt.h> #include <linux/ioport.h> -#include <linux/ptrace.h> #include <linux/sysdev.h> #include <asm/hardware.h> diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig new file mode 100644 index 000000000000..5fe8606cac08 --- /dev/null +++ b/arch/arm/mach-mx3/Kconfig @@ -0,0 +1,12 @@ +menu "MX3 Options" + depends on ARCH_MX3 + +config MACH_MX31ADS + bool "Support MX31ADS platforms" + default y + help + Include support for MX31ADS platform. This includes specific + configurations for the board and its peripherals. + +endmenu + diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile new file mode 100644 index 000000000000..cbec997f332a --- /dev/null +++ b/arch/arm/mach-mx3/Makefile @@ -0,0 +1,8 @@ +# +# Makefile for the linux kernel. +# + +# Object file lists. + +obj-y := mm.o time.o +obj-$(CONFIG_MACH_MX31ADS) += mx31ads.o diff --git a/arch/arm/mach-mx3/Makefile.boot b/arch/arm/mach-mx3/Makefile.boot new file mode 100644 index 000000000000..e1dd366f836b --- /dev/null +++ b/arch/arm/mach-mx3/Makefile.boot @@ -0,0 +1,3 @@ + zreladdr-y := 0x80008000 +params_phys-y := 0x80000100 +initrd_phys-y := 0x80800000 diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c new file mode 100644 index 000000000000..41dad485ded9 --- /dev/null +++ b/arch/arm/mach-mx3/mm.c @@ -0,0 +1,64 @@ +/* + * Copyright (C) 1999,2000 Arm Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd + * Copyright (C) 2002 Shane Nay (shane@minirl.com) + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * - add MX31 specific definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/mm.h> +#include <linux/init.h> +#include <asm/hardware.h> +#include <asm/pgtable.h> +#include <asm/mach/map.h> +#include <asm/arch/common.h> + +/*! + * @file mm.c + * + * @brief This file creates static virtual to physical mappings, common to all MX3 boards. + * + * @ingroup Memory + */ + +/*! + * This table defines static virtual address mappings for I/O regions. + * These are the mappings common across all MX3 boards. + */ +static struct map_desc mxc_io_desc[] __initdata = { + { + .virtual = X_MEMC_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(X_MEMC_BASE_ADDR), + .length = X_MEMC_SIZE, + .type = MT_DEVICE + }, { + .virtual = AVIC_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(AVIC_BASE_ADDR), + .length = AVIC_SIZE, + .type = MT_NONSHARED_DEVICE + }, +}; + +/*! + * This function initializes the memory map. It is called during the + * system startup to create static physical to virtual memory mappings + * for the IO modules. + */ +void __init mxc_map_io(void) +{ + iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); +} diff --git a/arch/arm/mach-mx3/mx31ads.c b/arch/arm/mach-mx3/mx31ads.c new file mode 100644 index 000000000000..7e89bdc23a9f --- /dev/null +++ b/arch/arm/mach-mx3/mx31ads.c @@ -0,0 +1,142 @@ +/* + * Copyright (C) 2000 Deep Blue Solutions Ltd + * Copyright (C) 2002 Shane Nay (shane@minirl.com) + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/types.h> +#include <linux/init.h> +#include <linux/clk.h> +#include <linux/serial_8250.h> + +#include <asm/hardware.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/memory.h> +#include <asm/mach/map.h> +#include <asm/arch/common.h> + +/*! + * @file mx31ads.c + * + * @brief This file contains the board-specific initialization routines. + * + * @ingroup System + */ + +#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) +/*! + * The serial port definition structure. + */ +static struct plat_serial8250_port serial_platform_data[] = { + { + .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA), + .mapbase = (unsigned long)(CS4_BASE_ADDR + PBC_SC16C652_UARTA), + .irq = EXPIO_INT_XUART_INTA, + .uartclk = 14745600, + .regshift = 0, + .iotype = UPIO_MEM, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ, + }, { + .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB), + .mapbase = (unsigned long)(CS4_BASE_ADDR + PBC_SC16C652_UARTB), + .irq = EXPIO_INT_XUART_INTB, + .uartclk = 14745600, + .regshift = 0, + .iotype = UPIO_MEM, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ, + }, + {}, +}; + +static struct platform_device serial_device = { + .name = "serial8250", + .id = 0, + .dev = { + .platform_data = serial_platform_data, + }, +}; + +static int __init mxc_init_extuart(void) +{ + return platform_device_register(&serial_device); +} +#else +static inline int mxc_init_extuart(void) +{ + return 0; +} +#endif + +/*! + * This structure defines static mappings for the i.MX31ADS board. + */ +static struct map_desc mx31ads_io_desc[] __initdata = { + { + .virtual = AIPS1_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(AIPS1_BASE_ADDR), + .length = AIPS1_SIZE, + .type = MT_NONSHARED_DEVICE + }, { + .virtual = SPBA0_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(SPBA0_BASE_ADDR), + .length = SPBA0_SIZE, + .type = MT_NONSHARED_DEVICE + }, { + .virtual = AIPS2_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(AIPS2_BASE_ADDR), + .length = AIPS2_SIZE, + .type = MT_NONSHARED_DEVICE + }, { + .virtual = CS4_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(CS4_BASE_ADDR), + .length = CS4_SIZE / 2, + .type = MT_DEVICE + }, +}; + +/*! + * Set up static virtual mappings. + */ +void __init mx31ads_map_io(void) +{ + mxc_map_io(); + iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc)); +} + +/*! + * Board specific initialization. + */ +static void __init mxc_board_init(void) +{ + mxc_init_extuart(); +} + +/* + * The following uses standard kernel macros defined in arch.h in order to + * initialize __mach_desc_MX31ADS data structure. + */ +MACHINE_START(MX31ADS, "Freescale MX31ADS") + /* Maintainer: Freescale Semiconductor, Inc. */ + .phys_io = AIPS1_BASE_ADDR, + .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = PHYS_OFFSET + 0x100, + .map_io = mx31ads_map_io, + .init_irq = mxc_init_irq, + .init_machine = mxc_board_init, + .timer = &mxc_timer, +MACHINE_END diff --git a/arch/arm/mach-mx3/time.c b/arch/arm/mach-mx3/time.c new file mode 100644 index 000000000000..e81fb5c5d7c3 --- /dev/null +++ b/arch/arm/mach-mx3/time.c @@ -0,0 +1,152 @@ +/* + * System Timer Interrupt reconfigured to run in free-run mode. + * Author: Vitaly Wool + * Copyright 2004 MontaVista Software Inc. + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/*! + * @file time.c + * @brief This file contains OS tick and wdog timer implementations. + * + * This file contains OS tick and wdog timer implementations. + * + * @ingroup Timers + */ + +#include <linux/module.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <asm/hardware.h> +#include <asm/mach/time.h> +#include <asm/io.h> +#include <asm/arch/common.h> + +/*! + * This is the timer interrupt service routine to do required tasks. + * It also services the WDOG timer at the frequency of twice per WDOG + * timeout value. For example, if the WDOG's timeout value is 4 (2 + * seconds since the WDOG runs at 0.5Hz), it will be serviced once + * every 2/2=1 second. + * + * @param irq GPT interrupt source number (not used) + * @param dev_id this parameter is not used + * @return always returns \b IRQ_HANDLED as defined in + * include/linux/interrupt.h. + */ +static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id) +{ + unsigned int next_match; + + write_seqlock(&xtime_lock); + + if (__raw_readl(MXC_GPT_GPTSR) & GPTSR_OF1) { + do { + timer_tick(); + next_match = __raw_readl(MXC_GPT_GPTOCR1) + LATCH; + __raw_writel(GPTSR_OF1, MXC_GPT_GPTSR); + __raw_writel(next_match, MXC_GPT_GPTOCR1); + } while ((signed long)(next_match - + __raw_readl(MXC_GPT_GPTCNT)) <= 0); + } + + write_sequnlock(&xtime_lock); + + return IRQ_HANDLED; +} + +/*! + * This function is used to obtain the number of microseconds since the last + * timer interrupt. Note that interrupts is disabled by do_gettimeofday(). + * + * @return the number of microseconds since the last timer interrupt. + */ +static unsigned long mxc_gettimeoffset(void) +{ + unsigned long ticks_to_match, elapsed, usec, tick_usec, i; + + /* Get ticks before next timer match */ + ticks_to_match = + __raw_readl(MXC_GPT_GPTOCR1) - __raw_readl(MXC_GPT_GPTCNT); + + /* We need elapsed ticks since last match */ + elapsed = LATCH - ticks_to_match; + + /* Now convert them to usec */ + /* Insure no overflow when calculating the usec below */ + for (i = 1, tick_usec = tick_nsec / 1000;; i *= 2) { + tick_usec /= i; + if ((0xFFFFFFFF / tick_usec) > elapsed) + break; + } + usec = (unsigned long)(elapsed * tick_usec) / (LATCH / i); + + return usec; +} + +/*! + * The OS tick timer interrupt structure. + */ +static struct irqaction timer_irq = { + .name = "MXC Timer Tick", + .flags = IRQF_DISABLED | IRQF_TIMER, + .handler = mxc_timer_interrupt +}; + +/*! + * This function is used to initialize the GPT to produce an interrupt + * based on HZ. It is called by start_kernel() during system startup. + */ +void __init mxc_init_time(void) +{ + u32 reg, v; + reg = __raw_readl(MXC_GPT_GPTCR); + reg &= ~GPTCR_ENABLE; + __raw_writel(reg, MXC_GPT_GPTCR); + reg |= GPTCR_SWR; + __raw_writel(reg, MXC_GPT_GPTCR); + + while ((__raw_readl(MXC_GPT_GPTCR) & GPTCR_SWR) != 0) + cpu_relax(); + + reg = GPTCR_FRR | GPTCR_CLKSRC_HIGHFREQ; + __raw_writel(reg, MXC_GPT_GPTCR); + + /* TODO: get timer rate from clk driver */ + v = 66500000; + + __raw_writel((v / CLOCK_TICK_RATE) - 1, MXC_GPT_GPTPR); + + if ((v % CLOCK_TICK_RATE) != 0) { + pr_info("\nWARNING: Can't generate CLOCK_TICK_RATE at %d Hz\n", + CLOCK_TICK_RATE); + } + pr_info("Actual CLOCK_TICK_RATE is %d Hz\n", + v / ((__raw_readl(MXC_GPT_GPTPR) & 0xFFF) + 1)); + + reg = __raw_readl(MXC_GPT_GPTCNT); + reg += LATCH; + __raw_writel(reg, MXC_GPT_GPTOCR1); + + setup_irq(MXC_INT_GPT, &timer_irq); + + reg = __raw_readl(MXC_GPT_GPTCR); + reg = + GPTCR_FRR | GPTCR_CLKSRC_HIGHFREQ | GPTCR_STOPEN | GPTCR_DOZEN | + GPTCR_WAITEN | GPTCR_ENMOD | GPTCR_ENABLE; + __raw_writel(reg, MXC_GPT_GPTCR); + + __raw_writel(GPTIR_OF1IE, MXC_GPT_GPTIR); +} + +struct sys_timer mxc_timer = { + .init = mxc_init_time, + .offset = mxc_gettimeoffset, +}; diff --git a/arch/arm/mach-ns9xxx/Makefile b/arch/arm/mach-ns9xxx/Makefile index 53213a69f601..4476411b8140 100644 --- a/arch/arm/mach-ns9xxx/Makefile +++ b/arch/arm/mach-ns9xxx/Makefile @@ -1,6 +1,7 @@ obj-y := irq.o time.o generic.o obj-$(CONFIG_MACH_CC9P9360DEV) += mach-cc9p9360dev.o +obj-$(CONFIG_MACH_CC9P9360JS) += mach-cc9p9360js.o obj-$(CONFIG_BOARD_A9M9750DEV) += board-a9m9750dev.o obj-$(CONFIG_BOARD_JSCC9P9360) += board-jscc9p9360.o diff --git a/arch/arm/mach-ns9xxx/board-a9m9750dev.c b/arch/arm/mach-ns9xxx/board-a9m9750dev.c index 25289884a607..925048e7adfe 100644 --- a/arch/arm/mach-ns9xxx/board-a9m9750dev.c +++ b/arch/arm/mach-ns9xxx/board-a9m9750dev.c @@ -77,7 +77,7 @@ static void a9m9750dev_fpga_demux_handler(unsigned int irq, desc = irq_desc + FPGA_IRQ(irqno); - desc_handle_irq(irqno, desc); + desc_handle_irq(FPGA_IRQ(irqno), desc); } } @@ -91,7 +91,7 @@ void __init board_a9m9750dev_init_irq(void) * use GPIO 11, because GPIO 32 is used for the LCD */ /* XXX: proper GPIO handling */ - BBU_GC(2) &= ~0x2000; + BBU_GCONFb1(1) &= ~0x2000; for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) { set_irq_chip(i, &a9m9750dev_fpga_chip); @@ -178,7 +178,7 @@ void __init board_a9m9750dev_init_machine(void) /* setup static CS0: memory configuration */ reg = MEM_SMC(0); - REGSET(reg, MEM_SMC, WSMC, OFF); + REGSET(reg, MEM_SMC, PSMC, OFF); REGSET(reg, MEM_SMC, BSMC, OFF); REGSET(reg, MEM_SMC, EW, OFF); REGSET(reg, MEM_SMC, PB, 1); @@ -196,4 +196,3 @@ void __init board_a9m9750dev_init_machine(void) platform_add_devices(board_a9m9750dev_devices, ARRAY_SIZE(board_a9m9750dev_devices)); } - diff --git a/arch/arm/mach-ns9xxx/generic.c b/arch/arm/mach-ns9xxx/generic.c index 83e2b6532b22..d742c921e34d 100644 --- a/arch/arm/mach-ns9xxx/generic.c +++ b/arch/arm/mach-ns9xxx/generic.c @@ -18,6 +18,8 @@ #include <asm/arch-ns9xxx/regs-mem.h> #include <asm/arch-ns9xxx/board.h> +#include "generic.h" + static struct map_desc standard_io_desc[] __initdata = { { /* BBus */ .virtual = io_p2v(0x90000000), diff --git a/arch/arm/mach-ns9xxx/irq.c b/arch/arm/mach-ns9xxx/irq.c index 83d92724a971..b8c7b00522e6 100644 --- a/arch/arm/mach-ns9xxx/irq.c +++ b/arch/arm/mach-ns9xxx/irq.c @@ -21,6 +21,15 @@ static void ns9xxx_ack_irq_timer(unsigned int irq) { u32 tc = SYS_TC(irq - IRQ_TIMER0); + /* + * If the timer is programmed to halt on terminal count, the + * timer must be disabled before clearing the interrupt. + */ + if (REGGET(tc, SYS_TCx, REN) == 0) { + REGSET(tc, SYS_TCx, TEN, DIS); + SYS_TC(irq - IRQ_TIMER0) = tc; + } + REGSET(tc, SYS_TCx, INTC, SET); SYS_TC(irq - IRQ_TIMER0) = tc; @@ -28,7 +37,7 @@ static void ns9xxx_ack_irq_timer(unsigned int irq) SYS_TC(irq - IRQ_TIMER0) = tc; } -void (*ns9xxx_ack_irq_functions[NR_IRQS])(unsigned int) = { +static void (*ns9xxx_ack_irq_functions[NR_IRQS])(unsigned int) = { [IRQ_TIMER0] = ns9xxx_ack_irq_timer, [IRQ_TIMER1] = ns9xxx_ack_irq_timer, [IRQ_TIMER2] = ns9xxx_ack_irq_timer, diff --git a/arch/arm/mach-ns9xxx/mach-cc9p9360js.c b/arch/arm/mach-ns9xxx/mach-cc9p9360js.c index d09d5fa5620a..85c8b41105c9 100644 --- a/arch/arm/mach-ns9xxx/mach-cc9p9360js.c +++ b/arch/arm/mach-ns9xxx/mach-cc9p9360js.c @@ -20,7 +20,7 @@ static void __init mach_cc9p9360js_init_machine(void) board_jscc9p9360_init_machine(); } -MACHINE_START(CC9P9360DEV, "Digi ConnectCore 9P 9360 on an JSCC9P9360 Devboard") +MACHINE_START(CC9P9360JS, "Digi ConnectCore 9P 9360 on an JSCC9P9360 Devboard") .map_io = ns9xxx_map_io, .init_irq = ns9xxx_init_irq, .init_machine = mach_cc9p9360js_init_machine, diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c index 3705d20c4e5c..237651ebae5d 100644 --- a/arch/arm/mach-omap1/time.c +++ b/arch/arm/mach-omap1/time.c @@ -156,6 +156,7 @@ static void omap_mpu_set_mode(enum clock_event_mode mode, break; case CLOCK_EVT_MODE_UNUSED: case CLOCK_EVT_MODE_SHUTDOWN: + case CLOCK_EVT_MODE_RESUME: break; } } diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index 5c0a10041cd1..5ebec6d88b51 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -37,6 +37,10 @@ config MACH_TRIZEPS4 bool "Keith und Koep Trizeps4 DIMM-Module" select PXA27x +config MACH_EM_X270 + bool "CompuLab EM-x270 platform" + select PXA27x + endchoice if PXA_SHARPSL diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index 9093eb1c94eb..7d6ab5c59ab9 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o sp obj-$(CONFIG_MACH_AKITA) += akita-ioexp.o obj-$(CONFIG_MACH_POODLE) += poodle.o corgi_ssp.o obj-$(CONFIG_MACH_TOSA) += tosa.o +obj-$(CONFIG_MACH_EM_X270) += em-x270.o # Support for blinky lights led-y := leds.o diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c index 8f7c90a0593b..34a31caa6f9d 100644 --- a/arch/arm/mach-pxa/clock.c +++ b/arch/arm/mach-pxa/clock.c @@ -12,7 +12,6 @@ #include <asm/arch/pxa-regs.h> #include <asm/hardware.h> -#include <asm/semaphore.h> struct clk { struct list_head node; @@ -25,21 +24,21 @@ struct clk { }; static LIST_HEAD(clocks); -static DECLARE_MUTEX(clocks_sem); +static DEFINE_MUTEX(clocks_mutex); static DEFINE_SPINLOCK(clocks_lock); struct clk *clk_get(struct device *dev, const char *id) { struct clk *p, *clk = ERR_PTR(-ENOENT); - down(&clocks_sem); + mutex_lock(&clocks_mutex); list_for_each_entry(p, &clocks, node) { if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) { clk = p; break; } } - up(&clocks_sem); + mutex_unlock(&clocks_mutex); return clk; } @@ -101,18 +100,18 @@ static struct clk clk_gpio27 = { int clk_register(struct clk *clk) { - down(&clocks_sem); + mutex_lock(&clocks_mutex); list_add(&clk->node, &clocks); - up(&clocks_sem); + mutex_unlock(&clocks_mutex); return 0; } EXPORT_SYMBOL(clk_register); void clk_unregister(struct clk *clk) { - down(&clocks_sem); + mutex_lock(&clocks_mutex); list_del(&clk->node); - up(&clocks_sem); + mutex_unlock(&clocks_mutex); } EXPORT_SYMBOL(clk_unregister); diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c index a1a900d16665..aab27297b3c6 100644 --- a/arch/arm/mach-pxa/corgi.c +++ b/arch/arm/mach-pxa/corgi.c @@ -44,6 +44,7 @@ #include <asm/hardware/scoop.h> #include "generic.h" +#include "devices.h" #include "sharpsl.h" @@ -368,7 +369,7 @@ MACHINE_START(CORGI, "SHARP Corgi") .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, .fixup = fixup_corgi, .map_io = pxa_map_io, - .init_irq = pxa_init_irq, + .init_irq = pxa25x_init_irq, .init_machine = corgi_init, .timer = &pxa_timer, MACHINE_END @@ -380,7 +381,7 @@ MACHINE_START(SHEPHERD, "SHARP Shepherd") .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, .fixup = fixup_corgi, .map_io = pxa_map_io, - .init_irq = pxa_init_irq, + .init_irq = pxa25x_init_irq, .init_machine = corgi_init, .timer = &pxa_timer, MACHINE_END @@ -392,7 +393,7 @@ MACHINE_START(HUSKY, "SHARP Husky") .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, .fixup = fixup_corgi, .map_io = pxa_map_io, - .init_irq = pxa_init_irq, + .init_irq = pxa25x_init_irq, .init_machine = corgi_init, .timer = &pxa_timer, MACHINE_END diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h new file mode 100644 index 000000000000..636fdb1c049c --- /dev/null +++ b/arch/arm/mach-pxa/devices.h @@ -0,0 +1,11 @@ +extern struct platform_device pxa_device_mci; +extern struct platform_device pxa_device_udc; +extern struct platform_device pxa_device_fb; +extern struct platform_device pxa_device_ffuart; +extern struct platform_device pxa_device_btuart; +extern struct platform_device pxa_device_stuart; +extern struct platform_device pxa_device_hwuart; +extern struct platform_device pxa_device_i2c; +extern struct platform_device pxa_device_i2s; +extern struct platform_device pxa_device_ficp; +extern struct platform_device pxa_device_rtc; diff --git a/arch/arm/mach-pxa/dma.c b/arch/arm/mach-pxa/dma.c index 4440babe7b97..93c4f31f127f 100644 --- a/arch/arm/mach-pxa/dma.c +++ b/arch/arm/mach-pxa/dma.c @@ -25,12 +25,15 @@ #include <asm/arch/pxa-regs.h> -static struct dma_channel { +struct dma_channel { char *name; + pxa_dma_prio prio; void (*irq_handler)(int, void *); void *data; -} dma_channels[PXA_DMA_CHANNELS]; +}; +static struct dma_channel *dma_channels; +static int num_dma_channels; int pxa_request_dma (char *name, pxa_dma_prio prio, void (*irq_handler)(int, void *), @@ -47,8 +50,9 @@ int pxa_request_dma (char *name, pxa_dma_prio prio, do { /* try grabbing a DMA channel with the requested priority */ - pxa_for_each_dma_prio (i, prio) { - if (!dma_channels[i].name) { + for (i = 0; i < num_dma_channels; i++) { + if ((dma_channels[i].prio == prio) && + !dma_channels[i].name) { found = 1; break; } @@ -91,7 +95,7 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id) { int i, dint = DINT; - for (i = 0; i < PXA_DMA_CHANNELS; i++) { + for (i = 0; i < num_dma_channels; i++) { if (dint & (1 << i)) { struct dma_channel *channel = &dma_channels[i]; if (channel->name && channel->irq_handler) { @@ -109,18 +113,32 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id) return IRQ_HANDLED; } -static int __init pxa_dma_init (void) +int __init pxa_init_dma(int num_ch) { - int ret; + int i, ret; - ret = request_irq (IRQ_DMA, dma_irq_handler, 0, "DMA", NULL); - if (ret) + dma_channels = kzalloc(sizeof(struct dma_channel) * num_ch, GFP_KERNEL); + if (dma_channels == NULL) + return -ENOMEM; + + ret = request_irq(IRQ_DMA, dma_irq_handler, IRQF_DISABLED, "DMA", NULL); + if (ret) { printk (KERN_CRIT "Wow! Can't register IRQ for DMA\n"); - return ret; -} + kfree(dma_channels); + return ret; + } -arch_initcall(pxa_dma_init); + /* dma channel priorities on pxa2xx processors: + * ch 0 - 3, 16 - 19 <--> (0) DMA_PRIO_HIGH + * ch 4 - 7, 20 - 23 <--> (1) DMA_PRIO_MEDIUM + * ch 8 - 15, 24 - 31 <--> (2) DMA_PRIO_LOW + */ + for (i = 0; i < num_ch; i++) + dma_channels[i].prio = min((i & 0xf) >> 2, DMA_PRIO_LOW); + + num_dma_channels = num_ch; + return 0; +} EXPORT_SYMBOL(pxa_request_dma); EXPORT_SYMBOL(pxa_free_dma); - diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c new file mode 100644 index 000000000000..3d0ad5065ee5 --- /dev/null +++ b/arch/arm/mach-pxa/em-x270.c @@ -0,0 +1,354 @@ +/* + * Support for CompuLab EM-x270 platform + * + * Copyright (C) 2007 CompuLab, Ltd. + * Author: Mike Rapoport <mike@compulab.co.il> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/irq.h> +#include <linux/platform_device.h> + +#include <linux/dm9000.h> +#include <linux/rtc-v3020.h> + +#include <linux/mtd/nand.h> +#include <linux/mtd/partitions.h> + +#include <asm/mach-types.h> + +#include <asm/mach/arch.h> + +#include <asm/arch/pxa-regs.h> +#include <asm/arch/pxafb.h> +#include <asm/arch/ohci.h> +#include <asm/arch/mmc.h> +#include <asm/arch/bitfield.h> + +#include "generic.h" + +/* GPIO IRQ usage */ +#define EM_X270_MMC_PD (105) +#define EM_X270_ETHIRQ IRQ_GPIO(41) +#define EM_X270_MMC_IRQ IRQ_GPIO(13) + +static struct resource em_x270_dm9k_resource[] = { + [0] = { + .start = PXA_CS2_PHYS, + .end = PXA_CS2_PHYS + 3, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = PXA_CS2_PHYS + 8, + .end = PXA_CS2_PHYS + 8 + 0x3f, + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = EM_X270_ETHIRQ, + .end = EM_X270_ETHIRQ, + .flags = IORESOURCE_IRQ, + } +}; + +/* for the moment we limit ourselves to 32bit IO until some + * better IO routines can be written and tested + */ +static struct dm9000_plat_data em_x270_dm9k_platdata = { + .flags = DM9000_PLATF_32BITONLY, +}; + +/* Ethernet device */ +static struct platform_device em_x270_dm9k = { + .name = "dm9000", + .id = 0, + .num_resources = ARRAY_SIZE(em_x270_dm9k_resource), + .resource = em_x270_dm9k_resource, + .dev = { + .platform_data = &em_x270_dm9k_platdata, + } +}; + +/* audio device */ +static struct platform_device em_x270_audio = { + .name = "pxa2xx-ac97", + .id = -1, +}; + +/* WM9712 touchscreen controller. Hopefully the driver will make it to + * the mainstream sometime */ +static struct platform_device em_x270_ts = { + .name = "wm97xx-ts", + .id = -1, +}; + +/* RTC */ +static struct resource em_x270_v3020_resource[] = { + [0] = { + .start = PXA_CS4_PHYS, + .end = PXA_CS4_PHYS + 3, + .flags = IORESOURCE_MEM, + }, +}; + +static struct v3020_platform_data em_x270_v3020_platdata = { + .leftshift = 0, +}; + +static struct platform_device em_x270_rtc = { + .name = "v3020", + .num_resources = ARRAY_SIZE(em_x270_v3020_resource), + .resource = em_x270_v3020_resource, + .id = -1, + .dev = { + .platform_data = &em_x270_v3020_platdata, + } +}; + +/* NAND flash */ +#define GPIO_NAND_CS (11) +#define GPIO_NAND_RB (56) + +static inline void nand_cs_on(void) +{ + GPCR(GPIO_NAND_CS) = GPIO_bit(GPIO_NAND_CS); +} + +static void nand_cs_off(void) +{ + dsb(); + + GPSR(GPIO_NAND_CS) = GPIO_bit(GPIO_NAND_CS); +} + +/* hardware specific access to control-lines */ +static void em_x270_nand_cmd_ctl(struct mtd_info *mtd, int dat, + unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + unsigned long nandaddr = (unsigned long)this->IO_ADDR_W; + + dsb(); + + if (ctrl & NAND_CTRL_CHANGE) { + if (ctrl & NAND_ALE) + nandaddr |= (1 << 3); + else + nandaddr &= ~(1 << 3); + if (ctrl & NAND_CLE) + nandaddr |= (1 << 2); + else + nandaddr &= ~(1 << 2); + if (ctrl & NAND_NCE) + nand_cs_on(); + else + nand_cs_off(); + } + + dsb(); + this->IO_ADDR_W = (void __iomem *)nandaddr; + if (dat != NAND_CMD_NONE) + writel(dat, this->IO_ADDR_W); + + dsb(); +} + +/* read device ready pin */ +static int em_x270_nand_device_ready(struct mtd_info *mtd) +{ + dsb(); + + return GPLR(GPIO_NAND_RB) & GPIO_bit(GPIO_NAND_RB); +} + +static struct mtd_partition em_x270_partition_info[] = { + [0] = { + .name = "em_x270-0", + .offset = 0, + .size = SZ_4M, + }, + [1] = { + .name = "em_x270-1", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL + }, +}; + +static const char *em_x270_part_probes[] = { "cmdlinepart", NULL }; + +struct platform_nand_data em_x270_nand_platdata = { + .chip = { + .nr_chips = 1, + .chip_offset = 0, + .nr_partitions = ARRAY_SIZE(em_x270_partition_info), + .partitions = em_x270_partition_info, + .chip_delay = 20, + .part_probe_types = em_x270_part_probes, + }, + .ctrl = { + .hwcontrol = 0, + .dev_ready = em_x270_nand_device_ready, + .select_chip = 0, + .cmd_ctrl = em_x270_nand_cmd_ctl, + }, +}; + +static struct resource em_x270_nand_resource[] = { + [0] = { + .start = PXA_CS1_PHYS, + .end = PXA_CS1_PHYS + 12, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device em_x270_nand = { + .name = "gen_nand", + .num_resources = ARRAY_SIZE(em_x270_nand_resource), + .resource = em_x270_nand_resource, + .id = -1, + .dev = { + .platform_data = &em_x270_nand_platdata, + } +}; + +/* platform devices */ +static struct platform_device *platform_devices[] __initdata = { + &em_x270_dm9k, + &em_x270_audio, + &em_x270_ts, + &em_x270_rtc, + &em_x270_nand, +}; + + +/* PXA27x OHCI controller setup */ +static int em_x270_ohci_init(struct device *dev) +{ + /* Set the Power Control Polarity Low */ + UHCHR = (UHCHR | UHCHR_PCPL) & + ~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE); + + /* enable port 2 transiever */ + UP2OCR = UP2OCR_HXS | UP2OCR_HXOE; + + return 0; +} + +static struct pxaohci_platform_data em_x270_ohci_platform_data = { + .port_mode = PMM_PERPORT_MODE, + .init = em_x270_ohci_init, +}; + + +static int em_x270_mci_init(struct device *dev, + irq_handler_t em_x270_detect_int, + void *data) +{ + int err; + + /* setup GPIO for PXA27x MMC controller */ + pxa_gpio_mode(GPIO32_MMCCLK_MD); + pxa_gpio_mode(GPIO112_MMCCMD_MD); + pxa_gpio_mode(GPIO92_MMCDAT0_MD); + pxa_gpio_mode(GPIO109_MMCDAT1_MD); + pxa_gpio_mode(GPIO110_MMCDAT2_MD); + pxa_gpio_mode(GPIO111_MMCDAT3_MD); + + /* EM-X270 uses GPIO13 as SD power enable */ + pxa_gpio_mode(EM_X270_MMC_PD | GPIO_OUT); + + err = request_irq(EM_X270_MMC_IRQ, em_x270_detect_int, + IRQF_DISABLED | IRQF_TRIGGER_FALLING, + "MMC card detect", data); + if (err) { + printk(KERN_ERR "%s: can't request MMC card detect IRQ: %d\n", + __FUNCTION__, err); + return err; + } + + return 0; +} + +static void em_x270_mci_setpower(struct device *dev, unsigned int vdd) +{ + /* + FIXME: current hardware implementation does not allow to + enable/disable MMC power. This will be fixed in next HW releases, + and we'll need to add implmentation here. + */ + return; +} + +static void em_x270_mci_exit(struct device *dev, void *data) +{ + free_irq(EM_X270_MMC_IRQ, data); +} + +static struct pxamci_platform_data em_x270_mci_platform_data = { + .ocr_mask = MMC_VDD_28_29|MMC_VDD_29_30|MMC_VDD_30_31, + .init = em_x270_mci_init, + .setpower = em_x270_mci_setpower, + .exit = em_x270_mci_exit, +}; + +/* LCD 480x640 */ +static struct pxafb_mode_info em_x270_lcd_mode = { + .pixclock = 50000, + .bpp = 16, + .xres = 480, + .yres = 640, + .hsync_len = 8, + .vsync_len = 2, + .left_margin = 8, + .upper_margin = 0, + .right_margin = 24, + .lower_margin = 4, + .cmap_greyscale = 0, +}; + +static struct pxafb_mach_info em_x270_lcd = { + .modes = &em_x270_lcd_mode, + .num_modes = 1, + .cmap_inverse = 0, + .cmap_static = 0, + .lccr0 = LCCR0_PAS, + .lccr3 = LCCR3_PixClkDiv(0x01) | LCCR3_Acb(0xff), +}; + +static void __init em_x270_init(void) +{ + /* setup LCD */ + set_pxa_fb_info(&em_x270_lcd); + + /* register EM-X270 platform devices */ + platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); + + /* set MCI and OHCI platform parameters */ + pxa_set_mci_info(&em_x270_mci_platform_data); + pxa_set_ohci_info(&em_x270_ohci_platform_data); + + /* setup STUART GPIOs */ + pxa_gpio_mode(GPIO46_STRXD_MD); + pxa_gpio_mode(GPIO47_STTXD_MD); + + /* setup BTUART GPIOs */ + pxa_gpio_mode(GPIO42_BTRXD_MD); + pxa_gpio_mode(GPIO43_BTTXD_MD); + pxa_gpio_mode(GPIO44_BTCTS_MD); + pxa_gpio_mode(GPIO45_BTRTS_MD); + + /* Setup interrupt for dm9000 */ + set_irq_type(EM_X270_ETHIRQ, IRQT_RISING); +} + +MACHINE_START(EM_X270, "Compulab EM-x270") + .boot_params = 0xa0000100, + .phys_io = 0x40000000, + .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, + .map_io = pxa_map_io, + .init_irq = pxa27x_init_irq, + .timer = &pxa_timer, + .init_machine = em_x270_init, +MACHINE_END diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c index 64b08b744f9f..5510f6fdce55 100644 --- a/arch/arm/mach-pxa/generic.c +++ b/arch/arm/mach-pxa/generic.c @@ -43,6 +43,7 @@ #include <asm/arch/irda.h> #include <asm/arch/i2c.h> +#include "devices.h" #include "generic.h" /* @@ -242,7 +243,7 @@ static struct resource pxamci_resources[] = { static u64 pxamci_dmamask = 0xffffffffUL; -static struct platform_device pxamci_device = { +struct platform_device pxa_device_mci = { .name = "pxa2xx-mci", .id = -1, .dev = { @@ -255,7 +256,7 @@ static struct platform_device pxamci_device = { void __init pxa_set_mci_info(struct pxamci_platform_data *info) { - pxamci_device.dev.platform_data = info; + pxa_device_mci.dev.platform_data = info; } @@ -281,7 +282,7 @@ static struct resource pxa2xx_udc_resources[] = { static u64 udc_dma_mask = ~(u32)0; -static struct platform_device udc_device = { +struct platform_device pxa_device_udc = { .name = "pxa2xx-udc", .id = -1, .resource = pxa2xx_udc_resources, @@ -307,7 +308,7 @@ static struct resource pxafb_resources[] = { static u64 fb_dma_mask = ~(u64)0; -static struct platform_device pxafb_device = { +struct platform_device pxa_device_fb = { .name = "pxa2xx-fb", .id = -1, .dev = { @@ -320,32 +321,32 @@ static struct platform_device pxafb_device = { void __init set_pxa_fb_info(struct pxafb_mach_info *info) { - pxafb_device.dev.platform_data = info; + pxa_device_fb.dev.platform_data = info; } void __init set_pxa_fb_parent(struct device *parent_dev) { - pxafb_device.dev.parent = parent_dev; + pxa_device_fb.dev.parent = parent_dev; } -static struct platform_device ffuart_device = { +struct platform_device pxa_device_ffuart= { .name = "pxa2xx-uart", .id = 0, }; -static struct platform_device btuart_device = { +struct platform_device pxa_device_btuart = { .name = "pxa2xx-uart", .id = 1, }; -static struct platform_device stuart_device = { +struct platform_device pxa_device_stuart = { .name = "pxa2xx-uart", .id = 2, }; -static struct platform_device hwuart_device = { +struct platform_device pxa_device_hwuart = { .name = "pxa2xx-uart", .id = 3, }; -static struct resource i2c_resources[] = { +static struct resource pxai2c_resources[] = { { .start = 0x40301680, .end = 0x403016a3, @@ -357,40 +358,19 @@ static struct resource i2c_resources[] = { }, }; -static struct platform_device i2c_device = { +struct platform_device pxa_device_i2c = { .name = "pxa2xx-i2c", .id = 0, - .resource = i2c_resources, - .num_resources = ARRAY_SIZE(i2c_resources), + .resource = pxai2c_resources, + .num_resources = ARRAY_SIZE(pxai2c_resources), }; -#ifdef CONFIG_PXA27x -static struct resource i2c_power_resources[] = { - { - .start = 0x40f00180, - .end = 0x40f001a3, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PWRI2C, - .end = IRQ_PWRI2C, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device i2c_power_device = { - .name = "pxa2xx-i2c", - .id = 1, - .resource = i2c_power_resources, - .num_resources = ARRAY_SIZE(i2c_resources), -}; -#endif - void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info) { - i2c_device.dev.platform_data = info; + pxa_device_i2c.dev.platform_data = info; } -static struct resource i2s_resources[] = { +static struct resource pxai2s_resources[] = { { .start = 0x40400000, .end = 0x40400083, @@ -402,16 +382,16 @@ static struct resource i2s_resources[] = { }, }; -static struct platform_device i2s_device = { +struct platform_device pxa_device_i2s = { .name = "pxa2xx-i2s", .id = -1, - .resource = i2s_resources, - .num_resources = ARRAY_SIZE(i2s_resources), + .resource = pxai2s_resources, + .num_resources = ARRAY_SIZE(pxai2s_resources), }; static u64 pxaficp_dmamask = ~(u32)0; -static struct platform_device pxaficp_device = { +struct platform_device pxa_device_ficp = { .name = "pxa2xx-ir", .id = -1, .dev = { @@ -422,45 +402,10 @@ static struct platform_device pxaficp_device = { void __init pxa_set_ficp_info(struct pxaficp_platform_data *info) { - pxaficp_device.dev.platform_data = info; + pxa_device_ficp.dev.platform_data = info; } -static struct platform_device pxartc_device = { +struct platform_device pxa_device_rtc = { .name = "sa1100-rtc", .id = -1, }; - -static struct platform_device *devices[] __initdata = { - &pxamci_device, - &udc_device, - &pxafb_device, - &ffuart_device, - &btuart_device, - &stuart_device, - &pxaficp_device, - &i2c_device, -#ifdef CONFIG_PXA27x - &i2c_power_device, -#endif - &i2s_device, - &pxartc_device, -}; - -static int __init pxa_init(void) -{ - int cpuid, ret; - - ret = platform_add_devices(devices, ARRAY_SIZE(devices)); - if (ret) - return ret; - - /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */ - cpuid = read_cpuid(CPUID_ID); - if (((cpuid >> 4) & 0xfff) == 0x2d0 || - ((cpuid >> 4) & 0xfff) == 0x290) - ret = platform_device_register(&hwuart_device); - - return ret; -} - -subsys_initcall(pxa_init); diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h index e54a8dd63c17..91ab2ad8b34b 100644 --- a/arch/arm/mach-pxa/generic.h +++ b/arch/arm/mach-pxa/generic.h @@ -12,8 +12,12 @@ struct sys_timer; extern struct sys_timer pxa_timer; +extern void __init pxa_init_irq_low(void); +extern void __init pxa_init_irq_high(void); +extern void __init pxa_init_irq_gpio(int gpio_nr); +extern void __init pxa25x_init_irq(void); +extern void __init pxa27x_init_irq(void); extern void __init pxa_map_io(void); -extern void __init pxa_init_irq(void); extern unsigned int get_clk_frequency_khz(int info); diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c index 64df44043a65..465108da2851 100644 --- a/arch/arm/mach-pxa/idp.c +++ b/arch/arm/mach-pxa/idp.c @@ -38,6 +38,7 @@ #include <asm/arch/mmc.h> #include "generic.h" +#include "devices.h" /* TODO: * - add pxa2xx_audio_ops_t device structure @@ -152,7 +153,7 @@ static void __init idp_init(void) static void __init idp_init_irq(void) { - pxa_init_irq(); + pxa25x_init_irq(); set_irq_type(TOUCH_PANEL_IRQ, TOUCH_PANEL_IRQ_EDGE); } diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c index 4619d5fe606c..4b867b0789d5 100644 --- a/arch/arm/mach-pxa/irq.c +++ b/arch/arm/mach-pxa/irq.c @@ -30,12 +30,12 @@ static void pxa_mask_low_irq(unsigned int irq) { - ICMR &= ~(1 << (irq + PXA_IRQ_SKIP)); + ICMR &= ~(1 << irq); } static void pxa_unmask_low_irq(unsigned int irq) { - ICMR |= (1 << (irq + PXA_IRQ_SKIP)); + ICMR |= (1 << irq); } static int pxa_set_wake(unsigned int irq, unsigned int on) @@ -67,7 +67,27 @@ static struct irq_chip pxa_internal_chip_low = { .set_wake = pxa_set_wake, }; -#if PXA_INTERNAL_IRQS > 32 +void __init pxa_init_irq_low(void) +{ + int irq; + + /* disable all IRQs */ + ICMR = 0; + + /* all IRQs are IRQ, not FIQ */ + ICLR = 0; + + /* only unmasked interrupts kick us out of idle */ + ICCR = 1; + + for (irq = PXA_IRQ(0); irq <= PXA_IRQ(31); irq++) { + set_irq_chip(irq, &pxa_internal_chip_low); + set_irq_handler(irq, handle_level_irq); + set_irq_flags(irq, IRQF_VALID); + } +} + +#ifdef CONFIG_PXA27x /* * This is for the second set of internal IRQs as found on the PXA27x. @@ -75,12 +95,12 @@ static struct irq_chip pxa_internal_chip_low = { static void pxa_mask_high_irq(unsigned int irq) { - ICMR2 &= ~(1 << (irq - 32 + PXA_IRQ_SKIP)); + ICMR2 &= ~(1 << (irq - 32)); } static void pxa_unmask_high_irq(unsigned int irq) { - ICMR2 |= (1 << (irq - 32 + PXA_IRQ_SKIP)); + ICMR2 |= (1 << (irq - 32)); } static struct irq_chip pxa_internal_chip_high = { @@ -90,6 +110,19 @@ static struct irq_chip pxa_internal_chip_high = { .unmask = pxa_unmask_high_irq, }; +void __init pxa_init_irq_high(void) +{ + int irq; + + ICMR2 = 0; + ICLR2 = 0; + + for (irq = PXA_IRQ(32); irq < PXA_IRQ(64); irq++) { + set_irq_chip(irq, &pxa_internal_chip_high); + set_irq_handler(irq, handle_level_irq); + set_irq_flags(irq, IRQF_VALID); + } +} #endif /* Note that if an input/irq line ever gets changed to an output during @@ -217,7 +250,7 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc) do { loop = 0; - mask = GEDR0 & ~3; + mask = GEDR0 & GPIO_IRQ_mask[0] & ~3; if (mask) { GEDR0 = mask; irq = IRQ_GPIO(2); @@ -233,7 +266,7 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc) loop = 1; } - mask = GEDR1; + mask = GEDR1 & GPIO_IRQ_mask[1]; if (mask) { GEDR1 = mask; irq = IRQ_GPIO(32); @@ -248,7 +281,7 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc) loop = 1; } - mask = GEDR2; + mask = GEDR2 & GPIO_IRQ_mask[2]; if (mask) { GEDR2 = mask; irq = IRQ_GPIO(64); @@ -263,8 +296,7 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc) loop = 1; } -#if PXA_LAST_GPIO >= 96 - mask = GEDR3; + mask = GEDR3 & GPIO_IRQ_mask[3]; if (mask) { GEDR3 = mask; irq = IRQ_GPIO(96); @@ -278,7 +310,6 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc) } while (mask); loop = 1; } -#endif } while (loop); } @@ -314,64 +345,27 @@ static struct irq_chip pxa_muxed_gpio_chip = { .set_wake = pxa_set_gpio_wake, }; - -void __init pxa_init_irq(void) +void __init pxa_init_irq_gpio(int gpio_nr) { - int irq; - - /* disable all IRQs */ - ICMR = 0; - - /* all IRQs are IRQ, not FIQ */ - ICLR = 0; + int irq, i; /* clear all GPIO edge detects */ - GFER0 = 0; - GFER1 = 0; - GFER2 = 0; - GRER0 = 0; - GRER1 = 0; - GRER2 = 0; - GEDR0 = GEDR0; - GEDR1 = GEDR1; - GEDR2 = GEDR2; - -#ifdef CONFIG_PXA27x - /* And similarly for the extra regs on the PXA27x */ - ICMR2 = 0; - ICLR2 = 0; - GFER3 = 0; - GRER3 = 0; - GEDR3 = GEDR3; -#endif - - /* only unmasked interrupts kick us out of idle */ - ICCR = 1; + for (i = 0; i < gpio_nr; i += 32) { + GFER(i) = 0; + GRER(i) = 0; + GEDR(i) = GEDR(i); + } /* GPIO 0 and 1 must have their mask bit always set */ GPIO_IRQ_mask[0] = 3; - for (irq = PXA_IRQ(PXA_IRQ_SKIP); irq <= PXA_IRQ(31); irq++) { - set_irq_chip(irq, &pxa_internal_chip_low); - set_irq_handler(irq, handle_level_irq); - set_irq_flags(irq, IRQF_VALID); - } - -#if PXA_INTERNAL_IRQS > 32 - for (irq = PXA_IRQ(32); irq < PXA_IRQ(PXA_INTERNAL_IRQS); irq++) { - set_irq_chip(irq, &pxa_internal_chip_high); - set_irq_handler(irq, handle_level_irq); - set_irq_flags(irq, IRQF_VALID); - } -#endif - for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { set_irq_chip(irq, &pxa_low_gpio_chip); set_irq_handler(irq, handle_edge_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } - for (irq = IRQ_GPIO(2); irq <= IRQ_GPIO(PXA_LAST_GPIO); irq++) { + for (irq = IRQ_GPIO(2); irq <= IRQ_GPIO(gpio_nr); irq++) { set_irq_chip(irq, &pxa_muxed_gpio_chip); set_irq_handler(irq, handle_edge_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c index e3097664ffe1..26116440a7c9 100644 --- a/arch/arm/mach-pxa/lpd270.c +++ b/arch/arm/mach-pxa/lpd270.c @@ -46,6 +46,7 @@ #include <asm/arch/ohci.h> #include "generic.h" +#include "devices.h" static unsigned int lpd270_irq_enabled; @@ -97,7 +98,7 @@ static void __init lpd270_init_irq(void) { int irq; - pxa_init_irq(); + pxa27x_init_irq(); __raw_writew(0, LPD270_INT_MASK); __raw_writew(0, LPD270_INT_STATUS); diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c index 6377b2e29ff0..e70048fd00a5 100644 --- a/arch/arm/mach-pxa/lubbock.c +++ b/arch/arm/mach-pxa/lubbock.c @@ -48,6 +48,7 @@ #include <asm/arch/mmc.h> #include "generic.h" +#include "devices.h" #define LUB_MISC_WR __LUB_REG(LUBBOCK_FPGA_PHYS + 0x080) @@ -103,7 +104,7 @@ static void __init lubbock_init_irq(void) { int irq; - pxa_init_irq(); + pxa25x_init_irq(); /* setup extra lubbock irqs */ for (irq = LUBBOCK_IRQ(0); irq <= LUBBOCK_LAST_IRQ; irq++) { diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index ed99a81b98f3..b02c79c7e6a3 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c @@ -46,6 +46,7 @@ #include <asm/arch/ohci.h> #include "generic.h" +#include "devices.h" static unsigned long mainstone_irq_enabled; @@ -89,7 +90,7 @@ static void __init mainstone_init_irq(void) { int irq; - pxa_init_irq(); + pxa27x_init_irq(); /* setup extra Mainstone irqs */ for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) { diff --git a/arch/arm/mach-pxa/pm.c b/arch/arm/mach-pxa/pm.c index 6bf15ae73848..b59a81a8e7d3 100644 --- a/arch/arm/mach-pxa/pm.c +++ b/arch/arm/mach-pxa/pm.c @@ -24,62 +24,13 @@ #include <asm/arch/lubbock.h> #include <asm/mach/time.h> - -/* - * Debug macros - */ -#undef DEBUG - -#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x -#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] - -#define RESTORE_GPLEVEL(n) do { \ - GPSR##n = sleep_save[SLEEP_SAVE_GPLR##n]; \ - GPCR##n = ~sleep_save[SLEEP_SAVE_GPLR##n]; \ -} while (0) - -/* - * List of global PXA peripheral registers to preserve. - * More ones like CP and general purpose register values are preserved - * with the stack pointer in sleep.S. - */ -enum { SLEEP_SAVE_START = 0, - - SLEEP_SAVE_GPLR0, SLEEP_SAVE_GPLR1, SLEEP_SAVE_GPLR2, SLEEP_SAVE_GPLR3, - SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2, SLEEP_SAVE_GPDR3, - SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2, SLEEP_SAVE_GRER3, - SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2, SLEEP_SAVE_GFER3, - SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, SLEEP_SAVE_PGSR3, - - SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U, - SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U, - SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U, - SLEEP_SAVE_GAFR3_L, SLEEP_SAVE_GAFR3_U, - - SLEEP_SAVE_PSTR, - - SLEEP_SAVE_ICMR, - SLEEP_SAVE_CKEN, - -#ifdef CONFIG_PXA27x - SLEEP_SAVE_MDREFR, - SLEEP_SAVE_PWER, SLEEP_SAVE_PCFR, SLEEP_SAVE_PRER, - SLEEP_SAVE_PFER, SLEEP_SAVE_PKWR, -#endif - - SLEEP_SAVE_CKSUM, - - SLEEP_SAVE_SIZE -}; - +struct pxa_cpu_pm_fns *pxa_cpu_pm_fns; +static unsigned long *sleep_save; int pxa_pm_enter(suspend_state_t state) { - unsigned long sleep_save[SLEEP_SAVE_SIZE]; - unsigned long checksum = 0; - struct timespec delta, rtc; + unsigned long sleep_save_checksum = 0, checksum = 0; int i; - extern void pxa_cpu_pm_enter(suspend_state_t state); #ifdef CONFIG_IWMMXT /* force any iWMMXt context to ram **/ @@ -87,109 +38,35 @@ int pxa_pm_enter(suspend_state_t state) iwmmxt_task_disable(NULL); #endif - /* preserve current time */ - rtc.tv_sec = RCNR; - rtc.tv_nsec = 0; - save_time_delta(&delta, &rtc); - - SAVE(GPLR0); SAVE(GPLR1); SAVE(GPLR2); - SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2); - SAVE(GRER0); SAVE(GRER1); SAVE(GRER2); - SAVE(GFER0); SAVE(GFER1); SAVE(GFER2); - SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2); - - SAVE(GAFR0_L); SAVE(GAFR0_U); - SAVE(GAFR1_L); SAVE(GAFR1_U); - SAVE(GAFR2_L); SAVE(GAFR2_U); - -#ifdef CONFIG_PXA27x - SAVE(MDREFR); - SAVE(GPLR3); SAVE(GPDR3); SAVE(GRER3); SAVE(GFER3); SAVE(PGSR3); - SAVE(GAFR3_L); SAVE(GAFR3_U); - SAVE(PWER); SAVE(PCFR); SAVE(PRER); - SAVE(PFER); SAVE(PKWR); -#endif - - SAVE(ICMR); - ICMR = 0; - - SAVE(CKEN); - SAVE(PSTR); - - /* Note: wake up source are set up in each machine specific files */ - - /* clear GPIO transition detect bits */ - GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2; -#ifdef CONFIG_PXA27x - GEDR3 = GEDR3; -#endif + pxa_cpu_pm_fns->save(sleep_save); /* Clear sleep reset status */ RCSR = RCSR_SMR; /* before sleeping, calculate and save a checksum */ - for (i = 0; i < SLEEP_SAVE_SIZE - 1; i++) - checksum += sleep_save[i]; - sleep_save[SLEEP_SAVE_CKSUM] = checksum; + for (i = 0; i < pxa_cpu_pm_fns->save_size - 1; i++) + sleep_save_checksum += sleep_save[i]; /* *** go zzz *** */ - pxa_cpu_pm_enter(state); - + pxa_cpu_pm_fns->enter(state); cpu_init(); /* after sleeping, validate the checksum */ - checksum = 0; - for (i = 0; i < SLEEP_SAVE_SIZE - 1; i++) + for (i = 0; i < pxa_cpu_pm_fns->save_size - 1; i++) checksum += sleep_save[i]; /* if invalid, display message and wait for a hardware reset */ - if (checksum != sleep_save[SLEEP_SAVE_CKSUM]) { + if (checksum != sleep_save_checksum) { #ifdef CONFIG_ARCH_LUBBOCK LUB_HEXLED = 0xbadbadc5; #endif while (1) - pxa_cpu_pm_enter(state); + pxa_cpu_pm_fns->enter(state); } - /* ensure not to come back here if it wasn't intended */ - PSPR = 0; - - /* restore registers */ - RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1); RESTORE_GPLEVEL(2); - RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2); - RESTORE(GAFR0_L); RESTORE(GAFR0_U); - RESTORE(GAFR1_L); RESTORE(GAFR1_U); - RESTORE(GAFR2_L); RESTORE(GAFR2_U); - RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2); - RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2); - RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2); - -#ifdef CONFIG_PXA27x - RESTORE(MDREFR); - RESTORE_GPLEVEL(3); RESTORE(GPDR3); - RESTORE(GAFR3_L); RESTORE(GAFR3_U); - RESTORE(GRER3); RESTORE(GFER3); RESTORE(PGSR3); - RESTORE(PWER); RESTORE(PCFR); RESTORE(PRER); - RESTORE(PFER); RESTORE(PKWR); -#endif - - PSSR = PSSR_RDH | PSSR_PH; - - RESTORE(CKEN); - - ICLR = 0; - ICCR = 1; - RESTORE(ICMR); + pxa_cpu_pm_fns->restore(sleep_save); - RESTORE(PSTR); - - /* restore current time */ - rtc.tv_sec = RCNR; - restore_time_delta(&delta, &rtc); - -#ifdef DEBUG - printk(KERN_DEBUG "*** made it back from resume\n"); -#endif + pr_debug("*** made it back from resume\n"); return 0; } @@ -201,37 +78,32 @@ unsigned long sleep_phys_sp(void *sp) return virt_to_phys(sp); } -/* - * Called after processes are frozen, but before we shut down devices. - */ -int pxa_pm_prepare(suspend_state_t state) +static int pxa_pm_valid(suspend_state_t state) { - extern int pxa_cpu_pm_prepare(suspend_state_t state); + if (pxa_cpu_pm_fns) + return pxa_cpu_pm_fns->valid(state); - return pxa_cpu_pm_prepare(state); + return -EINVAL; } -EXPORT_SYMBOL_GPL(pxa_pm_prepare); - -/* - * Called after devices are re-setup, but before processes are thawed. - */ -int pxa_pm_finish(suspend_state_t state) -{ - return 0; -} - -EXPORT_SYMBOL_GPL(pxa_pm_finish); - static struct pm_ops pxa_pm_ops = { - .prepare = pxa_pm_prepare, + .valid = pxa_pm_valid, .enter = pxa_pm_enter, - .finish = pxa_pm_finish, - .valid = pm_valid_only_mem, }; static int __init pxa_pm_init(void) { + if (!pxa_cpu_pm_fns) { + printk(KERN_ERR "no valid pxa_cpu_pm_fns defined\n"); + return -EINVAL; + } + + sleep_save = kmalloc(pxa_cpu_pm_fns->save_size, GFP_KERNEL); + if (!sleep_save) { + printk(KERN_ERR "failed to alloc memory for pm save\n"); + return -ENOMEM; + } + pm_set_ops(&pxa_pm_ops); return 0; } diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c index 34fb80b37023..655668d4d0e9 100644 --- a/arch/arm/mach-pxa/poodle.c +++ b/arch/arm/mach-pxa/poodle.c @@ -45,6 +45,7 @@ #include <asm/mach/sharpsl_param.h> #include "generic.h" +#include "devices.h" #include "sharpsl.h" static struct resource poodle_scoop_resources[] = { @@ -412,7 +413,7 @@ MACHINE_START(POODLE, "SHARP Poodle") .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, .fixup = fixup_poodle, .map_io = pxa_map_io, - .init_irq = pxa_init_irq, + .init_irq = pxa25x_init_irq, .timer = &pxa_timer, .init_machine = poodle_init, MACHINE_END diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index c1f21739bf71..6dfcca72e90f 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c @@ -19,12 +19,17 @@ #include <linux/module.h> #include <linux/kernel.h> #include <linux/init.h> +#include <linux/platform_device.h> #include <linux/pm.h> #include <asm/hardware.h> +#include <asm/arch/irqs.h> #include <asm/arch/pxa-regs.h> +#include <asm/arch/pm.h> +#include <asm/arch/dma.h> #include "generic.h" +#include "devices.h" /* * Various clock factors driven by the CCCR register. @@ -105,32 +110,138 @@ EXPORT_SYMBOL(get_lcdclk_frequency_10khz); #ifdef CONFIG_PM -int pxa_cpu_pm_prepare(suspend_state_t state) -{ - switch (state) { - case PM_SUSPEND_MEM: - break; - default: - return -EINVAL; - } +#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x +#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] + +#define RESTORE_GPLEVEL(n) do { \ + GPSR##n = sleep_save[SLEEP_SAVE_GPLR##n]; \ + GPCR##n = ~sleep_save[SLEEP_SAVE_GPLR##n]; \ +} while (0) + +/* + * List of global PXA peripheral registers to preserve. + * More ones like CP and general purpose register values are preserved + * with the stack pointer in sleep.S. + */ +enum { SLEEP_SAVE_START = 0, - return 0; + SLEEP_SAVE_GPLR0, SLEEP_SAVE_GPLR1, SLEEP_SAVE_GPLR2, + SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2, + SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2, + SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2, + SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, + + SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U, + SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U, + SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U, + + SLEEP_SAVE_PSTR, + + SLEEP_SAVE_ICMR, + SLEEP_SAVE_CKEN, + + SLEEP_SAVE_SIZE +}; + + +static void pxa25x_cpu_pm_save(unsigned long *sleep_save) +{ + SAVE(GPLR0); SAVE(GPLR1); SAVE(GPLR2); + SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2); + SAVE(GRER0); SAVE(GRER1); SAVE(GRER2); + SAVE(GFER0); SAVE(GFER1); SAVE(GFER2); + SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2); + + SAVE(GAFR0_L); SAVE(GAFR0_U); + SAVE(GAFR1_L); SAVE(GAFR1_U); + SAVE(GAFR2_L); SAVE(GAFR2_U); + + SAVE(ICMR); + SAVE(CKEN); + SAVE(PSTR); } -void pxa_cpu_pm_enter(suspend_state_t state) +static void pxa25x_cpu_pm_restore(unsigned long *sleep_save) { - extern void pxa_cpu_suspend(unsigned int); - extern void pxa_cpu_resume(void); + /* restore registers */ + RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1); RESTORE_GPLEVEL(2); + RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2); + RESTORE(GAFR0_L); RESTORE(GAFR0_U); + RESTORE(GAFR1_L); RESTORE(GAFR1_U); + RESTORE(GAFR2_L); RESTORE(GAFR2_U); + RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2); + RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2); + RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2); + + RESTORE(CKEN); + RESTORE(ICMR); + RESTORE(PSTR); +} +static void pxa25x_cpu_pm_enter(suspend_state_t state) +{ CKEN = 0; switch (state) { case PM_SUSPEND_MEM: /* set resume return address */ PSPR = virt_to_phys(pxa_cpu_resume); - pxa_cpu_suspend(PWRMODE_SLEEP); + pxa25x_cpu_suspend(PWRMODE_SLEEP); break; } } +static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = { + .save_size = SLEEP_SAVE_SIZE, + .valid = pm_valid_only_mem, + .save = pxa25x_cpu_pm_save, + .restore = pxa25x_cpu_pm_restore, + .enter = pxa25x_cpu_pm_enter, +}; + +static void __init pxa25x_init_pm(void) +{ + pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns; +} +#endif + +void __init pxa25x_init_irq(void) +{ + pxa_init_irq_low(); + pxa_init_irq_gpio(85); +} + +static struct platform_device *pxa25x_devices[] __initdata = { + &pxa_device_mci, + &pxa_device_udc, + &pxa_device_fb, + &pxa_device_ffuart, + &pxa_device_btuart, + &pxa_device_stuart, + &pxa_device_i2c, + &pxa_device_i2s, + &pxa_device_ficp, + &pxa_device_rtc, +}; + +static int __init pxa25x_init(void) +{ + int ret = 0; + + if (cpu_is_pxa21x() || cpu_is_pxa25x()) { + if ((ret = pxa_init_dma(16))) + return ret; +#ifdef CONFIG_PM + pxa25x_init_pm(); #endif + ret = platform_add_devices(pxa25x_devices, + ARRAY_SIZE(pxa25x_devices)); + } + /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */ + if (cpu_is_pxa25x()) + ret = platform_device_register(&pxa_device_hwuart); + + return ret; +} + +subsys_initcall(pxa25x_init); diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index 1939acc3f9f7..203371ab19db 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -19,10 +19,14 @@ #include <asm/hardware.h> #include <asm/irq.h> +#include <asm/arch/irqs.h> #include <asm/arch/pxa-regs.h> #include <asm/arch/ohci.h> +#include <asm/arch/pm.h> +#include <asm/arch/dma.h> #include "generic.h" +#include "devices.h" /* Crystal clock: 13MHz */ #define BASE_CLK 13000000 @@ -122,25 +126,107 @@ EXPORT_SYMBOL(get_lcdclk_frequency_10khz); #ifdef CONFIG_PM -int pxa_cpu_pm_prepare(suspend_state_t state) +#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x +#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] + +#define RESTORE_GPLEVEL(n) do { \ + GPSR##n = sleep_save[SLEEP_SAVE_GPLR##n]; \ + GPCR##n = ~sleep_save[SLEEP_SAVE_GPLR##n]; \ +} while (0) + +/* + * List of global PXA peripheral registers to preserve. + * More ones like CP and general purpose register values are preserved + * with the stack pointer in sleep.S. + */ +enum { SLEEP_SAVE_START = 0, + + SLEEP_SAVE_GPLR0, SLEEP_SAVE_GPLR1, SLEEP_SAVE_GPLR2, SLEEP_SAVE_GPLR3, + SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2, SLEEP_SAVE_GPDR3, + SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2, SLEEP_SAVE_GRER3, + SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2, SLEEP_SAVE_GFER3, + SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, SLEEP_SAVE_PGSR3, + + SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U, + SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U, + SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U, + SLEEP_SAVE_GAFR3_L, SLEEP_SAVE_GAFR3_U, + + SLEEP_SAVE_PSTR, + + SLEEP_SAVE_ICMR, + SLEEP_SAVE_CKEN, + + SLEEP_SAVE_MDREFR, + SLEEP_SAVE_PWER, SLEEP_SAVE_PCFR, SLEEP_SAVE_PRER, + SLEEP_SAVE_PFER, SLEEP_SAVE_PKWR, + + SLEEP_SAVE_SIZE +}; + +void pxa27x_cpu_pm_save(unsigned long *sleep_save) { - switch (state) { - case PM_SUSPEND_MEM: - case PM_SUSPEND_STANDBY: - return 0; - default: - return -EINVAL; - } + SAVE(GPLR0); SAVE(GPLR1); SAVE(GPLR2); SAVE(GPLR3); + SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2); SAVE(GPDR3); + SAVE(GRER0); SAVE(GRER1); SAVE(GRER2); SAVE(GRER3); + SAVE(GFER0); SAVE(GFER1); SAVE(GFER2); SAVE(GFER3); + SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2); SAVE(PGSR3); + + SAVE(GAFR0_L); SAVE(GAFR0_U); + SAVE(GAFR1_L); SAVE(GAFR1_U); + SAVE(GAFR2_L); SAVE(GAFR2_U); + SAVE(GAFR3_L); SAVE(GAFR3_U); + + SAVE(MDREFR); + SAVE(PWER); SAVE(PCFR); SAVE(PRER); + SAVE(PFER); SAVE(PKWR); + + SAVE(ICMR); ICMR = 0; + SAVE(CKEN); + SAVE(PSTR); + + /* Clear GPIO transition detect bits */ + GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2; GEDR3 = GEDR3; +} + +void pxa27x_cpu_pm_restore(unsigned long *sleep_save) +{ + /* ensure not to come back here if it wasn't intended */ + PSPR = 0; + + /* restore registers */ + RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1); + RESTORE_GPLEVEL(2); RESTORE_GPLEVEL(3); + RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2); RESTORE(GPDR3); + RESTORE(GAFR0_L); RESTORE(GAFR0_U); + RESTORE(GAFR1_L); RESTORE(GAFR1_U); + RESTORE(GAFR2_L); RESTORE(GAFR2_U); + RESTORE(GAFR3_L); RESTORE(GAFR3_U); + RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2); RESTORE(GRER3); + RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2); RESTORE(GFER3); + RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2); RESTORE(PGSR3); + + RESTORE(MDREFR); + RESTORE(PWER); RESTORE(PCFR); RESTORE(PRER); + RESTORE(PFER); RESTORE(PKWR); + + PSSR = PSSR_RDH | PSSR_PH; + + RESTORE(CKEN); + + ICLR = 0; + ICCR = 1; + RESTORE(ICMR); + RESTORE(PSTR); } -void pxa_cpu_pm_enter(suspend_state_t state) +void pxa27x_cpu_pm_enter(suspend_state_t state) { extern void pxa_cpu_standby(void); - extern void pxa_cpu_suspend(unsigned int); - extern void pxa_cpu_resume(void); if (state == PM_SUSPEND_STANDBY) - CKEN = (1 << CKEN_MEMC) | (1 << CKEN_OSTIMER) | (1 << CKEN_LCD) | (1 << CKEN_PWM0); + CKEN = (1 << CKEN_MEMC) | (1 << CKEN_OSTIMER) | + (1 << CKEN_LCD) | (1 << CKEN_PWM0); else CKEN = (1 << CKEN_MEMC) | (1 << CKEN_OSTIMER); @@ -157,11 +243,28 @@ void pxa_cpu_pm_enter(suspend_state_t state) case PM_SUSPEND_MEM: /* set resume return address */ PSPR = virt_to_phys(pxa_cpu_resume); - pxa_cpu_suspend(PWRMODE_SLEEP); + pxa27x_cpu_suspend(PWRMODE_SLEEP); break; } } +static int pxa27x_cpu_pm_valid(suspend_state_t state) +{ + return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; +} + +static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = { + .save_size = SLEEP_SAVE_SIZE, + .save = pxa27x_cpu_pm_save, + .restore = pxa27x_cpu_pm_restore, + .valid = pxa27x_cpu_pm_valid, + .enter = pxa27x_cpu_pm_enter, +}; + +static void __init pxa27x_init_pm(void) +{ + pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns; +} #endif /* @@ -183,7 +286,7 @@ static struct resource pxa27x_ohci_resources[] = { }, }; -static struct platform_device ohci_device = { +static struct platform_device pxa27x_device_ohci = { .name = "pxa27x-ohci", .id = -1, .dev = { @@ -196,16 +299,62 @@ static struct platform_device ohci_device = { void __init pxa_set_ohci_info(struct pxaohci_platform_data *info) { - ohci_device.dev.platform_data = info; + pxa27x_device_ohci.dev.platform_data = info; } +static struct resource i2c_power_resources[] = { + { + .start = 0x40f00180, + .end = 0x40f001a3, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_PWRI2C, + .end = IRQ_PWRI2C, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device pxa27x_device_i2c_power = { + .name = "pxa2xx-i2c", + .id = 1, + .resource = i2c_power_resources, + .num_resources = ARRAY_SIZE(i2c_power_resources), +}; + static struct platform_device *devices[] __initdata = { - &ohci_device, + &pxa_device_mci, + &pxa_device_udc, + &pxa_device_fb, + &pxa_device_ffuart, + &pxa_device_btuart, + &pxa_device_stuart, + &pxa_device_i2c, + &pxa_device_i2s, + &pxa_device_ficp, + &pxa_device_rtc, + &pxa27x_device_i2c_power, + &pxa27x_device_ohci, }; +void __init pxa27x_init_irq(void) +{ + pxa_init_irq_low(); + pxa_init_irq_high(); + pxa_init_irq_gpio(128); +} + static int __init pxa27x_init(void) { - return platform_add_devices(devices, ARRAY_SIZE(devices)); + int ret = 0; + if (cpu_is_pxa27x()) { + if ((ret = pxa_init_dma(32))) + return ret; +#ifdef CONFIG_PM + pxa27x_init_pm(); +#endif + ret = platform_add_devices(devices, ARRAY_SIZE(devices)); + } + return ret; } subsys_initcall(pxa27x_init); diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S index 15874b360e51..aff71fec618a 100644 --- a/arch/arm/mach-pxa/sleep.S +++ b/arch/arm/mach-pxa/sleep.S @@ -17,28 +17,12 @@ #include <asm/arch/pxa-regs.h> -#ifdef CONFIG_PXA27x // workaround for Errata 50 #define MDREFR_KDIV 0x200a4000 // all banks #define CCCR_SLEEP 0x00000107 // L=7 2N=2 A=0 PPDIS=0 CPDIS=0 -#endif .text -/* - * pxa_cpu_suspend() - * - * Forces CPU into sleep state. - * - * r0 = value for PWRMODE M field for desired sleep state - */ - -ENTRY(pxa_cpu_suspend) - -#ifndef CONFIG_IWMMXT - mra r2, r3, acc0 -#endif - stmfd sp!, {r2 - r12, lr} @ save registers on stack - +pxa_cpu_save_cp: @ get coprocessor registers mrc p14, 0, r3, c6, c0, 0 @ clock configuration, for turbo mode mrc p15, 0, r4, c15, c1, 0 @ CP access reg @@ -54,12 +38,36 @@ ENTRY(pxa_cpu_suspend) mov r10, sp stmfd sp!, {r3 - r10} - mov r5, r0 @ save sleep mode + mov pc, lr + +pxa_cpu_save_sp: @ preserve phys address of stack mov r0, sp + mov r2, lr bl sleep_phys_sp ldr r1, =sleep_save_sp str r0, [r1] + mov pc, r2 + +/* + * pxa27x_cpu_suspend() + * + * Forces CPU into sleep state. + * + * r0 = value for PWRMODE M field for desired sleep state + */ + +ENTRY(pxa27x_cpu_suspend) + +#ifndef CONFIG_IWMMXT + mra r2, r3, acc0 +#endif + stmfd sp!, {r2 - r12, lr} @ save registers on stack + + bl pxa_cpu_save_cp + + mov r5, r0 @ save sleep mode + bl pxa_cpu_save_sp @ clean data cache bl xscale_flush_kern_cache_all @@ -80,13 +88,55 @@ ENTRY(pxa_cpu_suspend) @ enable SDRAM self-refresh mode orr r5, r5, #MDREFR_SLFRSH -#ifdef CONFIG_PXA27x @ set SDCLKx divide-by-2 bits (this is part of a workaround for Errata 50) ldr r6, =MDREFR_KDIV orr r5, r5, r6 -#endif -#ifdef CONFIG_PXA25x + @ Intel PXA270 Specification Update notes problems sleeping + @ with core operating above 91 MHz + @ (see Errata 50, ...processor does not exit from sleep...) + + ldr r6, =CCCR + ldr r8, [r6] @ keep original value for resume + + ldr r7, =CCCR_SLEEP @ prepare CCCR sleep value + mov r0, #0x2 @ prepare value for CLKCFG + + @ align execution to a cache line + b pxa_cpu_do_suspend + +/* + * pxa27x_cpu_suspend() + * + * Forces CPU into sleep state. + * + * r0 = value for PWRMODE M field for desired sleep state + */ + +ENTRY(pxa25x_cpu_suspend) + stmfd sp!, {r2 - r12, lr} @ save registers on stack + + bl pxa_cpu_save_cp + + mov r5, r0 @ save sleep mode + bl pxa_cpu_save_sp + + @ clean data cache + bl xscale_flush_kern_cache_all + + @ prepare value for sleep mode + mov r1, r5 @ sleep mode + + @ prepare pointer to physical address 0 (virtual mapping in generic.c) + mov r2, #UNCACHED_PHYS_0 + + @ prepare SDRAM refresh settings + ldr r4, =MDREFR + ldr r5, [r4] + + @ enable SDRAM self-refresh mode + orr r5, r5, #MDREFR_SLFRSH + @ Intel PXA255 Specification Update notes problems @ about suspending with PXBus operating above 133MHz @ (see Errata 31, GPIO output signals, ... unpredictable in sleep @@ -118,30 +168,15 @@ ENTRY(pxa_cpu_suspend) mov r0, #0 mcr p14, 0, r0, c6, c0, 0 orr r0, r0, #2 @ initiate change bit -#endif -#ifdef CONFIG_PXA27x - @ Intel PXA270 Specification Update notes problems sleeping - @ with core operating above 91 MHz - @ (see Errata 50, ...processor does not exit from sleep...) - - ldr r6, =CCCR - ldr r8, [r6] @ keep original value for resume - - ldr r7, =CCCR_SLEEP @ prepare CCCR sleep value - mov r0, #0x2 @ prepare value for CLKCFG -#endif - - @ align execution to a cache line - b 1f + b pxa_cpu_do_suspend .ltorg .align 5 -1: +pxa_cpu_do_suspend: @ All needed values are now in registers. @ These last instructions should be in cache -#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x) @ initiate the frequency change... str r7, [r6] mcr p14, 0, r0, c6, c0, 0 @@ -155,7 +190,6 @@ ENTRY(pxa_cpu_suspend) mov r0, #42 10: subs r0, r0, #1 bne 10b -#endif @ Do not reorder... @ Intel PXA270 Specification Update notes problems performing diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index 3cbac63bed3c..bae47e145de8 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c @@ -48,6 +48,7 @@ #include <asm/hardware/scoop.h> #include "generic.h" +#include "devices.h" #include "sharpsl.h" /* @@ -560,7 +561,7 @@ MACHINE_START(SPITZ, "SHARP Spitz") .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, .fixup = fixup_spitz, .map_io = pxa_map_io, - .init_irq = pxa_init_irq, + .init_irq = pxa27x_init_irq, .init_machine = spitz_init, .timer = &pxa_timer, MACHINE_END @@ -572,7 +573,7 @@ MACHINE_START(BORZOI, "SHARP Borzoi") .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, .fixup = fixup_spitz, .map_io = pxa_map_io, - .init_irq = pxa_init_irq, + .init_irq = pxa27x_init_irq, .init_machine = spitz_init, .timer = &pxa_timer, MACHINE_END @@ -584,7 +585,7 @@ MACHINE_START(AKITA, "SHARP Akita") .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, .fixup = fixup_spitz, .map_io = pxa_map_io, - .init_irq = pxa_init_irq, + .init_irq = pxa27x_init_irq, .init_machine = akita_init, .timer = &pxa_timer, MACHINE_END diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c index 5248abe334d2..98d27e646b09 100644 --- a/arch/arm/mach-pxa/time.c +++ b/arch/arm/mach-pxa/time.c @@ -1,9 +1,11 @@ /* * arch/arm/mach-pxa/time.c * - * Author: Nicolas Pitre - * Created: Jun 15, 2001 - * Copyright: MontaVista Software Inc. + * PXA clocksource, clockevents, and OST interrupt handlers. + * Copyright (c) 2007 by Bill Gatliff <bgat@billgatliff.com>. + * + * Derived from Nicolas Pitre's PXA timer handler Copyright (c) 2001 + * by MontaVista Software, Inc. (Nico, your code rocks!) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -12,173 +14,160 @@ #include <linux/kernel.h> #include <linux/init.h> -#include <linux/delay.h> #include <linux/interrupt.h> -#include <linux/time.h> -#include <linux/signal.h> -#include <linux/errno.h> -#include <linux/sched.h> -#include <linux/clocksource.h> - -#include <asm/system.h> -#include <asm/hardware.h> -#include <asm/io.h> -#include <asm/leds.h> -#include <asm/irq.h> +#include <linux/clockchips.h> + #include <asm/mach/irq.h> #include <asm/mach/time.h> #include <asm/arch/pxa-regs.h> - -static inline unsigned long pxa_get_rtc_time(void) +static irqreturn_t +pxa_ost0_interrupt(int irq, void *dev_id) { - return RCNR; + int next_match; + struct clock_event_device *c = dev_id; + + if (c->mode == CLOCK_EVT_MODE_ONESHOT) { + /* Disarm the compare/match, signal the event. */ + OIER &= ~OIER_E0; + c->event_handler(c); + } else if (c->mode == CLOCK_EVT_MODE_PERIODIC) { + /* Call the event handler as many times as necessary + * to recover missed events, if any (if we update + * OSMR0 and OSCR0 is still ahead of us, we've missed + * the event). As we're dealing with that, re-arm the + * compare/match for the next event. + * + * HACK ALERT: + * + * There's a latency between the instruction that + * writes to OSMR0 and the actual commit to the + * physical hardware, because the CPU doesn't (have + * to) run at bus speed, there's a write buffer + * between the CPU and the bus, etc. etc. So if the + * target OSCR0 is "very close", to the OSMR0 load + * value, the update to OSMR0 might not get to the + * hardware in time and we'll miss that interrupt. + * + * To be safe, if the new OSMR0 is "very close" to the + * target OSCR0 value, we call the event_handler as + * though the event actually happened. According to + * Nico's comment in the previous version of this + * code, experience has shown that 6 OSCR ticks is + * "very close" but he went with 8. We will use 16, + * based on the results of testing on PXA270. + * + * To be doubly sure, we also tell clkevt via + * clockevents_register_device() not to ask for + * anything that might put us "very close". + */ +#define MIN_OSCR_DELTA 16 + do { + OSSR = OSSR_M0; + next_match = (OSMR0 += LATCH); + c->event_handler(c); + } while (((signed long)(next_match - OSCR) <= MIN_OSCR_DELTA) + && (c->mode == CLOCK_EVT_MODE_PERIODIC)); + } + + return IRQ_HANDLED; } -static int pxa_set_rtc(void) +static int +pxa_osmr0_set_next_event(unsigned long delta, struct clock_event_device *dev) { - unsigned long current_time = xtime.tv_sec; + unsigned long irqflags; - if (RTSR & RTSR_ALE) { - /* make sure not to forward the clock over an alarm */ - unsigned long alarm = RTAR; - if (current_time >= alarm && alarm >= RCNR) - return -ERESTARTSYS; - } - RCNR = current_time; + raw_local_irq_save(irqflags); + OSMR0 = OSCR + delta; + OSSR = OSSR_M0; + OIER |= OIER_E0; + raw_local_irq_restore(irqflags); return 0; } -#ifdef CONFIG_NO_IDLE_HZ -static unsigned long initial_match; -static int match_posponed; -#endif - -static irqreturn_t -pxa_timer_interrupt(int irq, void *dev_id) +static void +pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev) { - int next_match; - - write_seqlock(&xtime_lock); - -#ifdef CONFIG_NO_IDLE_HZ - if (match_posponed) { - match_posponed = 0; - OSMR0 = initial_match; + unsigned long irqflags; + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + raw_local_irq_save(irqflags); + OSMR0 = OSCR + LATCH; + OSSR = OSSR_M0; + OIER |= OIER_E0; + raw_local_irq_restore(irqflags); + break; + + case CLOCK_EVT_MODE_ONESHOT: + raw_local_irq_save(irqflags); + OIER &= ~OIER_E0; + raw_local_irq_restore(irqflags); + break; + + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + /* initializing, released, or preparing for suspend */ + raw_local_irq_save(irqflags); + OIER &= ~OIER_E0; + raw_local_irq_restore(irqflags); + break; } -#endif - - /* Loop until we get ahead of the free running timer. - * This ensures an exact clock tick count and time accuracy. - * Since IRQs are disabled at this point, coherence between - * lost_ticks(updated in do_timer()) and the match reg value is - * ensured, hence we can use do_gettimeofday() from interrupt - * handlers. - * - * HACK ALERT: it seems that the PXA timer regs aren't updated right - * away in all cases when a write occurs. We therefore compare with - * 8 instead of 0 in the while() condition below to avoid missing a - * match if OSCR has already reached the next OSMR value. - * Experience has shown that up to 6 ticks are needed to work around - * this problem, but let's use 8 to be conservative. Note that this - * affect things only when the timer IRQ has been delayed by nearly - * exactly one tick period which should be a pretty rare event. - */ - do { - timer_tick(); - OSSR = OSSR_M0; /* Clear match on timer 0 */ - next_match = (OSMR0 += LATCH); - } while( (signed long)(next_match - OSCR) <= 8 ); - - write_sequnlock(&xtime_lock); - - return IRQ_HANDLED; } -static struct irqaction pxa_timer_irq = { - .name = "PXA Timer Tick", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, - .handler = pxa_timer_interrupt, +static struct clock_event_device ckevt_pxa_osmr0 = { + .name = "osmr0", + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .shift = 32, + .rating = 200, + .cpumask = CPU_MASK_CPU0, + .set_next_event = pxa_osmr0_set_next_event, + .set_mode = pxa_osmr0_set_mode, }; -static cycle_t pxa_get_cycles(void) +static cycle_t pxa_read_oscr(void) { return OSCR; } -static struct clocksource clocksource_pxa = { - .name = "pxa_timer", +static struct clocksource cksrc_pxa_oscr0 = { + .name = "oscr0", .rating = 200, - .read = pxa_get_cycles, + .read = pxa_read_oscr, .mask = CLOCKSOURCE_MASK(32), .shift = 20, .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; +static struct irqaction pxa_ost0_irq = { + .name = "ost0", + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .handler = pxa_ost0_interrupt, + .dev_id = &ckevt_pxa_osmr0, +}; + static void __init pxa_timer_init(void) { - struct timespec tv; - unsigned long flags; - - set_rtc = pxa_set_rtc; + OIER = 0; + OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3; - tv.tv_nsec = 0; - tv.tv_sec = pxa_get_rtc_time(); - do_settimeofday(&tv); + ckevt_pxa_osmr0.mult = + div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt_pxa_osmr0.shift); + ckevt_pxa_osmr0.max_delta_ns = + clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0); + ckevt_pxa_osmr0.min_delta_ns = + clockevent_delta2ns(MIN_OSCR_DELTA, &ckevt_pxa_osmr0) + 1; - OIER = 0; /* disable any timer interrupts */ - OSSR = 0xf; /* clear status on all timers */ - setup_irq(IRQ_OST0, &pxa_timer_irq); - local_irq_save(flags); - OIER = OIER_E0; /* enable match on timer 0 to cause interrupts */ - OSMR0 = OSCR + LATCH; /* set initial match */ - local_irq_restore(flags); - - /* - * OSCR runs continuously on PXA and is not written to, - * so we can use it as clock source directly. - */ - clocksource_pxa.mult = - clocksource_hz2mult(CLOCK_TICK_RATE, clocksource_pxa.shift); - clocksource_register(&clocksource_pxa); -} - -#ifdef CONFIG_NO_IDLE_HZ -static int pxa_dyn_tick_enable_disable(void) -{ - /* nothing to do */ - return 0; -} + cksrc_pxa_oscr0.mult = + clocksource_hz2mult(CLOCK_TICK_RATE, cksrc_pxa_oscr0.shift); -static void pxa_dyn_tick_reprogram(unsigned long ticks) -{ - if (ticks > 1) { - initial_match = OSMR0; - OSMR0 = initial_match + ticks * LATCH; - match_posponed = 1; - } -} + setup_irq(IRQ_OST0, &pxa_ost0_irq); -static irqreturn_t -pxa_dyn_tick_handler(int irq, void *dev_id) -{ - if (match_posponed) { - match_posponed = 0; - OSMR0 = initial_match; - if ( (signed long)(initial_match - OSCR) <= 8 ) - return pxa_timer_interrupt(irq, dev_id); - } - return IRQ_NONE; + clocksource_register(&cksrc_pxa_oscr0); + clockevents_register_device(&ckevt_pxa_osmr0); } -static struct dyn_tick_timer pxa_dyn_tick = { - .enable = pxa_dyn_tick_enable_disable, - .disable = pxa_dyn_tick_enable_disable, - .reprogram = pxa_dyn_tick_reprogram, - .handler = pxa_dyn_tick_handler, -}; -#endif - #ifdef CONFIG_PM static unsigned long osmr[4], oier; @@ -200,7 +189,10 @@ static void pxa_timer_resume(void) OIER = oier; /* - * OSMR0 is the system timer: make sure OSCR is sufficiently behind + * OSCR0 is the system timer, which has to increase + * monotonically until it rolls over in hardware. The value + * (OSMR0 - LATCH) is OSCR0 at the most recent system tick, + * which is a handy value to restore to OSCR0. */ OSCR = OSMR0 - LATCH; } @@ -213,7 +205,4 @@ struct sys_timer pxa_timer = { .init = pxa_timer_init, .suspend = pxa_timer_suspend, .resume = pxa_timer_resume, -#ifdef CONFIG_NO_IDLE_HZ - .dyn_tick = &pxa_dyn_tick, -#endif }; diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c index 72738771fb57..240fd042083d 100644 --- a/arch/arm/mach-pxa/tosa.c +++ b/arch/arm/mach-pxa/tosa.c @@ -42,7 +42,7 @@ #include <asm/mach/sharpsl_param.h> #include "generic.h" - +#include "devices.h" /* * SCOOP Device @@ -332,7 +332,7 @@ MACHINE_START(TOSA, "SHARP Tosa") .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, .fixup = fixup_tosa, .map_io = pxa_map_io, - .init_irq = pxa_init_irq, + .init_irq = pxa25x_init_irq, .init_machine = tosa_init, .timer = &pxa_timer, MACHINE_END diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c index 28c79bd0a3a0..e4ba43bdf85d 100644 --- a/arch/arm/mach-pxa/trizeps4.c +++ b/arch/arm/mach-pxa/trizeps4.c @@ -49,6 +49,7 @@ #include <asm/arch/ohci.h> #include "generic.h" +#include "devices.h" /******************************************************************************************** * ONBOARD FLASH @@ -503,7 +504,7 @@ MACHINE_START(TRIZEPS4, "Keith und Koep Trizeps IV module") .boot_params = TRIZEPS4_SDRAM_BASE + 0x100, .init_machine = trizeps4_init, .map_io = trizeps4_map_io, - .init_irq = pxa_init_irq, + .init_irq = pxa27x_init_irq, .timer = &pxa_timer, MACHINE_END diff --git a/arch/arm/mach-rpc/riscpc.c b/arch/arm/mach-rpc/riscpc.c index 570cf937e73b..a454451c97c3 100644 --- a/arch/arm/mach-rpc/riscpc.c +++ b/arch/arm/mach-rpc/riscpc.c @@ -87,7 +87,7 @@ static void __init rpc_map_io(void) /* * Turn off floppy. */ - outb(0xc, 0x3f2); + writeb(0xc, PCIO_BASE + (0x3f2 << 2)); /* * RiscPC can't handle half-word loads and stores diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig index d4b013b283c3..e2079cf9266f 100644 --- a/arch/arm/mach-s3c2410/Kconfig +++ b/arch/arm/mach-s3c2410/Kconfig @@ -9,6 +9,7 @@ config CPU_S3C2410 depends on ARCH_S3C2410 select S3C2410_CLOCK select S3C2410_GPIO + select CPU_LLSERIAL_S3C2410 select S3C2410_PM if PM help Support for S3C2410 and S3C2410A family from the S3C24XX line diff --git a/arch/arm/mach-s3c2410/clock.c b/arch/arm/mach-s3c2410/clock.c index 5b4831c4c1d8..cab9d6265e9e 100644 --- a/arch/arm/mach-s3c2410/clock.c +++ b/arch/arm/mach-s3c2410/clock.c @@ -37,7 +37,7 @@ #include <asm/hardware.h> #include <asm/io.h> -#include <asm/arch/regs-serial.h> +#include <asm/plat-s3c/regs-serial.h> #include <asm/arch/regs-clock.h> #include <asm/arch/regs-gpio.h> diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c index 67d1ad363973..80d83739ab9f 100644 --- a/arch/arm/mach-s3c2410/dma.c +++ b/arch/arm/mach-s3c2410/dma.c @@ -23,14 +23,14 @@ #include <asm/plat-s3c24xx/cpu.h> #include <asm/plat-s3c24xx/dma.h> -#include <asm/arch/regs-serial.h> +#include <asm/plat-s3c/regs-serial.h> #include <asm/arch/regs-gpio.h> -#include <asm/arch/regs-ac97.h> +#include <asm/plat-s3c/regs-ac97.h> #include <asm/arch/regs-mem.h> #include <asm/arch/regs-lcd.h> #include <asm/arch/regs-sdi.h> -#include <asm/arch/regs-iis.h> -#include <asm/arch/regs-spi.h> +#include <asm/plat-s3c24xx/regs-iis.h> +#include <asm/plat-s3c24xx/regs-spi.h> static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = { [DMACH_XD0] = { diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c2410/mach-amlm5900.c index 435adcce6482..43bb5e106302 100644 --- a/arch/arm/mach-s3c2410/mach-amlm5900.c +++ b/arch/arm/mach-s3c2410/mach-amlm5900.c @@ -48,7 +48,7 @@ #include <asm/mach-types.h> #include <asm/arch/fb.h> -#include <asm/arch/regs-serial.h> +#include <asm/plat-s3c/regs-serial.h> #include <asm/arch/regs-lcd.h> #include <asm/arch/regs-gpio.h> diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c index f01de807b72f..bc926992b4e4 100644 --- a/arch/arm/mach-s3c2410/mach-bast.c +++ b/arch/arm/mach-s3c2410/mach-bast.c @@ -20,6 +20,8 @@ #include <linux/platform_device.h> #include <linux/dm9000.h> +#include <net/ax88796.h> + #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/irq.h> @@ -34,13 +36,13 @@ #include <asm/mach-types.h> //#include <asm/debug-ll.h> -#include <asm/arch/regs-serial.h> +#include <asm/plat-s3c/regs-serial.h> #include <asm/arch/regs-gpio.h> #include <asm/arch/regs-mem.h> #include <asm/arch/regs-lcd.h> -#include <asm/arch/nand.h> -#include <asm/arch/iic.h> +#include <asm/plat-s3c/nand.h> +#include <asm/plat-s3c/iic.h> #include <asm/arch/fb.h> #include <linux/mtd/mtd.h> @@ -409,6 +411,61 @@ static struct s3c2410_platform_i2c bast_i2c_info = { .max_freq = 130*1000, }; +/* Asix AX88796 10/100 ethernet controller */ + +static struct ax_plat_data bast_asix_platdata = { + .flags = AXFLG_MAC_FROMDEV, + .wordlength = 2, + .dcr_val = 0x48, + .rcr_val = 0x40, +}; + +static struct resource bast_asix_resource[] = { + [0] = { + .start = S3C2410_CS5 + BAST_PA_ASIXNET, + .end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20) - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20), + .end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20), + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = IRQ_ASIX, + .end = IRQ_ASIX, + .flags = IORESOURCE_IRQ + } +}; + +static struct platform_device bast_device_asix = { + .name = "ax88796", + .id = 0, + .num_resources = ARRAY_SIZE(bast_asix_resource), + .resource = bast_asix_resource, + .dev = { + .platform_data = &bast_asix_platdata + } +}; + +/* Asix AX88796 10/100 ethernet controller parallel port */ + +static struct resource bast_asixpp_resource[] = { + [0] = { + .start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20), + .end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1b * 0x20) - 1, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device bast_device_axpp = { + .name = "ax88796-pp", + .id = 0, + .num_resources = ARRAY_SIZE(bast_asixpp_resource), + .resource = bast_asixpp_resource, +}; + +/* LCD/VGA controller */ static struct s3c2410fb_mach_info __initdata bast_lcd_info = { .width = 640, @@ -453,6 +510,8 @@ static struct platform_device *bast_devices[] __initdata = { &s3c_device_nand, &bast_device_nor, &bast_device_dm9k, + &bast_device_asix, + &bast_device_axpp, &bast_sio, }; diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c index 5c9bcea74767..9a172b4ad720 100644 --- a/arch/arm/mach-s3c2410/mach-h1940.c +++ b/arch/arm/mach-s3c2410/mach-h1940.c @@ -30,7 +30,7 @@ #include <asm/irq.h> #include <asm/mach-types.h> -#include <asm/arch/regs-serial.h> +#include <asm/plat-s3c/regs-serial.h> #include <asm/arch/regs-lcd.h> #include <asm/arch/regs-gpio.h> #include <asm/arch/regs-clock.h> @@ -38,7 +38,7 @@ #include <asm/arch/h1940.h> #include <asm/arch/h1940-latch.h> #include <asm/arch/fb.h> -#include <asm/arch/udc.h> +#include <asm/plat-s3c24xx/udc.h> #include <asm/plat-s3c24xx/clock.h> #include <asm/plat-s3c24xx/devs.h> diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c index 412e50c3d28a..621f548da610 100644 --- a/arch/arm/mach-s3c2410/mach-n30.c +++ b/arch/arm/mach-s3c2410/mach-n30.c @@ -33,9 +33,9 @@ #include <asm/irq.h> #include <asm/mach-types.h> -#include <asm/arch/regs-serial.h> +#include <asm/plat-s3c/regs-serial.h> #include <asm/arch/regs-gpio.h> -#include <asm/arch/iic.h> +#include <asm/plat-s3c/iic.h> #include <asm/plat-s3c24xx/s3c2410.h> #include <asm/plat-s3c24xx/clock.h> diff --git a/arch/arm/mach-s3c2410/mach-otom.c b/arch/arm/mach-s3c2410/mach-otom.c index 1f899fa588df..717af40e4477 100644 --- a/arch/arm/mach-s3c2410/mach-otom.c +++ b/arch/arm/mach-s3c2410/mach-otom.c @@ -29,7 +29,7 @@ #include <asm/irq.h> #include <asm/mach-types.h> -#include <asm/arch/regs-serial.h> +#include <asm/plat-s3c/regs-serial.h> #include <asm/arch/regs-gpio.h> #include <asm/plat-s3c24xx/s3c2410.h> diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c index d86e6f18bac9..e670b1e1631b 100644 --- a/arch/arm/mach-s3c2410/mach-qt2410.c +++ b/arch/arm/mach-s3c2410/mach-qt2410.c @@ -49,10 +49,10 @@ #include <asm/arch/regs-gpio.h> #include <asm/arch/leds-gpio.h> -#include <asm/arch/regs-serial.h> +#include <asm/plat-s3c/regs-serial.h> #include <asm/arch/fb.h> -#include <asm/arch/nand.h> -#include <asm/arch/udc.h> +#include <asm/plat-s3c/nand.h> +#include <asm/plat-s3c24xx/udc.h> #include <asm/arch/spi.h> #include <asm/arch/spi-gpio.h> diff --git a/arch/arm/mach-s3c2410/mach-smdk2410.c b/arch/arm/mach-s3c2410/mach-smdk2410.c index 5852d300d52f..226550504c85 100644 --- a/arch/arm/mach-s3c2410/mach-smdk2410.c +++ b/arch/arm/mach-s3c2410/mach-smdk2410.c @@ -47,7 +47,7 @@ #include <asm/irq.h> #include <asm/mach-types.h> -#include <asm/arch/regs-serial.h> +#include <asm/plat-s3c/regs-serial.h> #include <asm/plat-s3c24xx/devs.h> #include <asm/plat-s3c24xx/cpu.h> diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c index 7b624bb00490..9f43f3f124f5 100644 --- a/arch/arm/mach-s3c2410/mach-vr1000.c +++ b/arch/arm/mach-s3c2410/mach-vr1000.c @@ -39,7 +39,7 @@ #include <asm/irq.h> #include <asm/mach-types.h> -#include <asm/arch/regs-serial.h> +#include <asm/plat-s3c/regs-serial.h> #include <asm/arch/regs-gpio.h> #include <asm/arch/leds-gpio.h> diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c index 1a86a9803753..e580303cb0ab 100644 --- a/arch/arm/mach-s3c2410/s3c2410.c +++ b/arch/arm/mach-s3c2410/s3c2410.c @@ -29,7 +29,7 @@ #include <asm/irq.h> #include <asm/arch/regs-clock.h> -#include <asm/arch/regs-serial.h> +#include <asm/plat-s3c/regs-serial.h> #include <asm/plat-s3c24xx/s3c2410.h> #include <asm/plat-s3c24xx/cpu.h> @@ -40,7 +40,6 @@ static struct map_desc s3c2410_iodesc[] __initdata = { IODESC_ENT(CLKPWR), - IODESC_ENT(LCD), IODESC_ENT(TIMER), IODESC_ENT(WATCHDOG), }; diff --git a/arch/arm/mach-s3c2410/sleep.S b/arch/arm/mach-s3c2410/sleep.S index d1eeed2ad47c..8a9c5a2bb252 100644 --- a/arch/arm/mach-s3c2410/sleep.S +++ b/arch/arm/mach-s3c2410/sleep.S @@ -32,7 +32,7 @@ #include <asm/arch/regs-gpio.h> #include <asm/arch/regs-clock.h> #include <asm/arch/regs-mem.h> -#include <asm/arch/regs-serial.h> +#include <asm/plat-s3c/regs-serial.h> /* s3c2410_cpu_suspend * diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig index d5be5d053264..8e8fe48ea47f 100644 --- a/arch/arm/mach-s3c2412/Kconfig +++ b/arch/arm/mach-s3c2412/Kconfig @@ -7,6 +7,7 @@ config CPU_S3C2412 bool depends on ARCH_S3C2410 + select CPU_LLSERIAL_S3C2440 select S3C2412_PM if PM select S3C2412_DMA if S3C2410_DMA help diff --git a/arch/arm/mach-s3c2412/clock.c b/arch/arm/mach-s3c2412/clock.c index 6a8e4448770b..8543dd6df391 100644 --- a/arch/arm/mach-s3c2412/clock.c +++ b/arch/arm/mach-s3c2412/clock.c @@ -37,7 +37,7 @@ #include <asm/hardware.h> #include <asm/io.h> -#include <asm/arch/regs-serial.h> +#include <asm/plat-s3c/regs-serial.h> #include <asm/arch/regs-clock.h> #include <asm/arch/regs-gpio.h> diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c index 668cccefe7b0..4b9425c1bf72 100644 --- a/arch/arm/mach-s3c2412/dma.c +++ b/arch/arm/mach-s3c2412/dma.c @@ -24,14 +24,14 @@ #include <asm/plat-s3c24xx/dma.h> #include <asm/plat-s3c24xx/cpu.h> -#include <asm/arch/regs-serial.h> +#include <asm/plat-s3c/regs-serial.h> #include <asm/arch/regs-gpio.h> -#include <asm/arch/regs-ac97.h> +#include <asm/plat-s3c/regs-ac97.h> #include <asm/arch/regs-mem.h> #include <asm/arch/regs-lcd.h> #include <asm/arch/regs-sdi.h> -#include <asm/arch/regs-iis.h> -#include <asm/arch/regs-spi.h> +#include <asm/plat-s3c24xx/regs-iis.h> +#include <asm/plat-s3c24xx/regs-spi.h> #define MAP(x) { (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID } diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c index 063af09f899d..b126a530daa6 100644 --- a/arch/arm/mach-s3c2412/mach-smdk2413.c +++ b/arch/arm/mach-s3c2412/mach-smdk2413.c @@ -32,12 +32,12 @@ #include <asm/mach-types.h> //#include <asm/debug-ll.h> -#include <asm/arch/regs-serial.h> +#include <asm/plat-s3c/regs-serial.h> #include <asm/arch/regs-gpio.h> #include <asm/arch/regs-lcd.h> #include <asm/arch/idle.h> -#include <asm/arch/udc.h> +#include <asm/plat-s3c24xx/udc.h> #include <asm/arch/fb.h> #include <asm/plat-s3c24xx/s3c2410.h> diff --git a/arch/arm/mach-s3c2412/mach-vstms.c b/arch/arm/mach-s3c2412/mach-vstms.c index f2fbd65956ac..32982547cd63 100644 --- a/arch/arm/mach-s3c2412/mach-vstms.c +++ b/arch/arm/mach-s3c2412/mach-vstms.c @@ -33,14 +33,14 @@ #include <asm/irq.h> #include <asm/mach-types.h> -#include <asm/arch/regs-serial.h> +#include <asm/plat-s3c/regs-serial.h> #include <asm/arch/regs-gpio.h> #include <asm/arch/regs-lcd.h> #include <asm/arch/idle.h> #include <asm/arch/fb.h> -#include <asm/arch/nand.h> +#include <asm/plat-s3c/nand.h> #include <asm/plat-s3c24xx/s3c2410.h> #include <asm/plat-s3c24xx/s3c2412.h> diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c index 782b5814ced2..e0ccb404623f 100644 --- a/arch/arm/mach-s3c2412/s3c2412.c +++ b/arch/arm/mach-s3c2412/s3c2412.c @@ -34,12 +34,12 @@ #include <asm/arch/idle.h> #include <asm/arch/regs-clock.h> -#include <asm/arch/regs-serial.h> +#include <asm/plat-s3c/regs-serial.h> #include <asm/arch/regs-power.h> #include <asm/arch/regs-gpio.h> #include <asm/arch/regs-gpioj.h> #include <asm/arch/regs-dsc.h> -#include <asm/arch/regs-spi.h> +#include <asm/plat-s3c24xx/regs-spi.h> #include <asm/arch/regs-s3c2412.h> #include <asm/plat-s3c24xx/s3c2412.h> @@ -63,7 +63,6 @@ static inline void s3c2412_init_gpio2(void) static struct map_desc s3c2412_iodesc[] __initdata = { IODESC_ENT(CLKPWR), - IODESC_ENT(LCD), IODESC_ENT(TIMER), IODESC_ENT(WATCHDOG), }; diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig index e3bfda098c0f..f1915bd61d15 100644 --- a/arch/arm/mach-s3c2440/Kconfig +++ b/arch/arm/mach-s3c2440/Kconfig @@ -12,6 +12,7 @@ config CPU_S3C2440 select S3C2410_GPIO select S3C2440_DMA if S3C2410_DMA select CPU_S3C244X + select CPU_LLSERIAL_S3C2440 help Support for S3C2440 Samsung Mobile CPU based systems. diff --git a/arch/arm/mach-s3c2440/dma.c b/arch/arm/mach-s3c2440/dma.c index cd035a3ec878..f509f062e749 100644 --- a/arch/arm/mach-s3c2440/dma.c +++ b/arch/arm/mach-s3c2440/dma.c @@ -23,14 +23,14 @@ #include <asm/plat-s3c24xx/dma.h> #include <asm/plat-s3c24xx/cpu.h> -#include <asm/arch/regs-serial.h> +#include <asm/plat-s3c/regs-serial.h> #include <asm/arch/regs-gpio.h> -#include <asm/arch/regs-ac97.h> +#include <asm/plat-s3c/regs-ac97.h> #include <asm/arch/regs-mem.h> #include <asm/arch/regs-lcd.h> #include <asm/arch/regs-sdi.h> -#include <asm/arch/regs-iis.h> -#include <asm/arch/regs-spi.h> +#include <asm/plat-s3c24xx/regs-iis.h> +#include <asm/plat-s3c24xx/regs-spi.h> static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = { [DMACH_XD0] = { diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c index bff7ddd06a52..3d3dfa95db8e 100644 --- a/arch/arm/mach-s3c2440/mach-anubis.c +++ b/arch/arm/mach-s3c2440/mach-anubis.c @@ -18,6 +18,9 @@ #include <linux/serial_core.h> #include <linux/platform_device.h> +#include <linux/sm501.h> +#include <linux/sm501-regs.h> + #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/irq.h> @@ -31,17 +34,19 @@ #include <asm/irq.h> #include <asm/mach-types.h> -#include <asm/arch/regs-serial.h> +#include <asm/plat-s3c/regs-serial.h> #include <asm/arch/regs-gpio.h> #include <asm/arch/regs-mem.h> #include <asm/arch/regs-lcd.h> -#include <asm/arch/nand.h> +#include <asm/plat-s3c/nand.h> #include <linux/mtd/mtd.h> #include <linux/mtd/nand.h> #include <linux/mtd/nand_ecc.h> #include <linux/mtd/partitions.h> +#include <net/ax88796.h> + #include <asm/plat-s3c24xx/clock.h> #include <asm/plat-s3c24xx/devs.h> #include <asm/plat-s3c24xx/cpu.h> @@ -153,6 +158,29 @@ static struct mtd_partition anubis_default_nand_part[] = { } }; +static struct mtd_partition anubis_default_nand_part_large[] = { + [0] = { + .name = "Boot Agent", + .size = SZ_128K, + .offset = 0, + }, + [1] = { + .name = "/boot", + .size = SZ_4M - SZ_128K, + .offset = SZ_128K, + }, + [2] = { + .name = "user1", + .offset = SZ_4M, + .size = SZ_32M - SZ_4M, + }, + [3] = { + .name = "user2", + .offset = SZ_32M, + .size = MTDPART_SIZ_FULL, + } +}; + /* the Anubis has 3 selectable slots for nand-flash, the two * on-board chip areas, as well as the external slot. * @@ -260,6 +288,104 @@ static struct platform_device anubis_device_ide1 = { .resource = anubis_ide1_resource, }; +/* Asix AX88796 10/100 ethernet controller */ + +static struct ax_plat_data anubis_asix_platdata = { + .flags = AXFLG_MAC_FROMDEV, + .wordlength = 2, + .dcr_val = 0x48, + .rcr_val = 0x40, +}; + +static struct resource anubis_asix_resource[] = { + [0] = { + .start = S3C2410_CS5, + .end = S3C2410_CS5 + (0x20 * 0x20) -1, + .flags = IORESOURCE_MEM + }, + [1] = { + .start = IRQ_ASIX, + .end = IRQ_ASIX, + .flags = IORESOURCE_IRQ + } +}; + +static struct platform_device anubis_device_asix = { + .name = "ax88796", + .id = 0, + .num_resources = ARRAY_SIZE(anubis_asix_resource), + .resource = anubis_asix_resource, + .dev = { + .platform_data = &anubis_asix_platdata, + } +}; + +/* SM501 */ + +static struct resource anubis_sm501_resource[] = { + [0] = { + .start = S3C2410_CS2, + .end = S3C2410_CS2 + SZ_8M, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = S3C2410_CS2 + SZ_64M - SZ_2M, + .end = S3C2410_CS2 + SZ_64M - 1, + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = IRQ_EINT0, + .end = IRQ_EINT0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct sm501_initdata anubis_sm501_initdata = { + .gpio_high = { + .set = 0x3F000000, /* 24bit panel */ + .mask = 0x0, + }, + .misc_timing = { + .set = 0x010100, /* SDRAM timing */ + .mask = 0x1F1F00, + }, + .misc_control = { + .set = SM501_MISC_PNL_24BIT, + .mask = 0, + }, + + /* set the SDRAM and bus clocks */ + .mclk = 72 * MHZ, + .m1xclk = 144 * MHZ, +}; + +static struct sm501_platdata_gpio_i2c anubis_sm501_gpio_i2c[] = { + [0] = { + .pin_scl = 44, + .pin_sda = 45, + }, + [1] = { + .pin_scl = 40, + .pin_sda = 41, + }, +}; + +static struct sm501_platdata anubis_sm501_platdata = { + .init = &anubis_sm501_initdata, + .gpio_i2c = anubis_sm501_gpio_i2c, + .gpio_i2c_nr = ARRAY_SIZE(anubis_sm501_gpio_i2c), +}; + +static struct platform_device anubis_device_sm501 = { + .name = "sm501", + .id = 0, + .num_resources = ARRAY_SIZE(anubis_sm501_resource), + .resource = anubis_sm501_resource, + .dev = { + .platform_data = &anubis_sm501_platdata, + }, +}; + /* Standard Anubis devices */ static struct platform_device *anubis_devices[] __initdata = { @@ -271,6 +397,8 @@ static struct platform_device *anubis_devices[] __initdata = { &s3c_device_nand, &anubis_device_ide0, &anubis_device_ide1, + &anubis_device_asix, + &anubis_device_sm501, }; static struct clk *anubis_clocks[] = { @@ -304,8 +432,17 @@ static void __init anubis_map_io(void) s3c24xx_init_clocks(0); s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs)); - /* ensure that the GPIO is setup */ - s3c2410_gpio_setpin(S3C2410_GPA0, 1); + /* check for the newer revision boards with large page nand */ + + if ((__raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK) >= 4) { + printk(KERN_INFO "ANUBIS-B detected (revision %d)\n", + __raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK); + anubis_nand_sets[0].partitions = anubis_default_nand_part_large; + anubis_nand_sets[0].nr_partitions = ARRAY_SIZE(anubis_default_nand_part_large); + } else { + /* ensure that the GPIO is setup */ + s3c2410_gpio_setpin(S3C2410_GPA0, 1); + } } static void __init anubis_init(void) diff --git a/arch/arm/mach-s3c2440/mach-nexcoder.c b/arch/arm/mach-s3c2440/mach-nexcoder.c index 5e61f2166c76..afe0d7b7e389 100644 --- a/arch/arm/mach-s3c2440/mach-nexcoder.c +++ b/arch/arm/mach-s3c2440/mach-nexcoder.c @@ -36,7 +36,7 @@ //#include <asm/debug-ll.h> #include <asm/arch/regs-gpio.h> -#include <asm/arch/regs-serial.h> +#include <asm/plat-s3c/regs-serial.h> #include <asm/plat-s3c24xx/s3c2410.h> #include <asm/plat-s3c24xx/s3c2440.h> diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c index 15811601f03d..0ba7e9060c7b 100644 --- a/arch/arm/mach-s3c2440/mach-osiris.c +++ b/arch/arm/mach-s3c2440/mach-osiris.c @@ -31,11 +31,11 @@ #include <asm/irq.h> #include <asm/mach-types.h> -#include <asm/arch/regs-serial.h> +#include <asm/plat-s3c/regs-serial.h> #include <asm/arch/regs-gpio.h> #include <asm/arch/regs-mem.h> #include <asm/arch/regs-lcd.h> -#include <asm/arch/nand.h> +#include <asm/plat-s3c/nand.h> #include <linux/mtd/mtd.h> #include <linux/mtd/nand.h> @@ -166,6 +166,29 @@ static struct mtd_partition osiris_default_nand_part[] = { } }; +static struct mtd_partition osiris_default_nand_part_large[] = { + [0] = { + .name = "Boot Agent", + .size = SZ_128K, + .offset = 0, + }, + [1] = { + .name = "/boot", + .size = SZ_4M - SZ_128K, + .offset = SZ_128K, + }, + [2] = { + .name = "user1", + .offset = SZ_4M, + .size = SZ_32M - SZ_4M, + }, + [3] = { + .name = "user2", + .offset = SZ_32M, + .size = MTDPART_SIZ_FULL, + } +}; + /* the Osiris has 3 selectable slots for nand-flash, the two * on-board chip areas, as well as the external slot. * @@ -322,14 +345,23 @@ static void __init osiris_map_io(void) s3c24xx_init_clocks(0); s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs)); + /* check for the newer revision boards with large page nand */ + + if ((__raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK) >= 4) { + printk(KERN_INFO "OSIRIS-B detected (revision %d)\n", + __raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK); + osiris_nand_sets[0].partitions = osiris_default_nand_part_large; + osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large); + } else { + /* write-protect line to the NAND */ + s3c2410_gpio_setpin(S3C2410_GPA0, 1); + } + /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */ local_irq_save(flags); __raw_writel(__raw_readl(S3C2410_BWSCON) | S3C2410_BWSCON_ST1 | S3C2410_BWSCON_ST2 | S3C2410_BWSCON_ST3 | S3C2410_BWSCON_ST4 | S3C2410_BWSCON_ST5, S3C2410_BWSCON); local_irq_restore(flags); - - /* write-protect line to the NAND */ - s3c2410_gpio_setpin(S3C2410_GPA0, 1); } static void __init osiris_init(void) diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c index 866ff71c01dd..b59e6d39f2f2 100644 --- a/arch/arm/mach-s3c2440/mach-rx3715.c +++ b/arch/arm/mach-s3c2440/mach-rx3715.c @@ -38,12 +38,12 @@ #include <asm/irq.h> #include <asm/mach-types.h> -#include <asm/arch/regs-serial.h> +#include <asm/plat-s3c/regs-serial.h> #include <asm/arch/regs-gpio.h> #include <asm/arch/regs-lcd.h> #include <asm/arch/h1940.h> -#include <asm/arch/nand.h> +#include <asm/plat-s3c/nand.h> #include <asm/arch/fb.h> #include <asm/plat-s3c24xx/clock.h> diff --git a/arch/arm/mach-s3c2440/mach-smdk2440.c b/arch/arm/mach-s3c2440/mach-smdk2440.c index e167254e232e..670115b8a12e 100644 --- a/arch/arm/mach-s3c2440/mach-smdk2440.c +++ b/arch/arm/mach-s3c2440/mach-smdk2440.c @@ -31,7 +31,7 @@ #include <asm/irq.h> #include <asm/mach-types.h> -#include <asm/arch/regs-serial.h> +#include <asm/plat-s3c/regs-serial.h> #include <asm/arch/regs-gpio.h> #include <asm/arch/regs-lcd.h> diff --git a/arch/arm/mach-s3c2442/Kconfig b/arch/arm/mach-s3c2442/Kconfig index bf8d87abfab3..88d5fd34fe3b 100644 --- a/arch/arm/mach-s3c2442/Kconfig +++ b/arch/arm/mach-s3c2442/Kconfig @@ -11,6 +11,7 @@ config CPU_S3C2442 select S3C2410_GPIO select S3C2410_PM if PM select CPU_S3C244X + select CPU_LLSERIAL_S3C2440 help Support for S3C2442 Samsung Mobile CPU based systems. diff --git a/arch/arm/mach-s3c2443/Kconfig b/arch/arm/mach-s3c2443/Kconfig index c649bb2e7ce8..14252f573754 100644 --- a/arch/arm/mach-s3c2443/Kconfig +++ b/arch/arm/mach-s3c2443/Kconfig @@ -8,6 +8,7 @@ config CPU_S3C2443 bool depends on ARCH_S3C2410 select S3C2443_DMA if S3C2410_DMA + select CPU_LLSERIAL_S3C2440 help Support for the S3C2443 SoC from the S3C24XX line diff --git a/arch/arm/mach-s3c2443/dma.c b/arch/arm/mach-s3c2443/dma.c index f70e8ccffc3d..fc3ede82af8f 100644 --- a/arch/arm/mach-s3c2443/dma.c +++ b/arch/arm/mach-s3c2443/dma.c @@ -24,14 +24,14 @@ #include <asm/plat-s3c24xx/dma.h> #include <asm/plat-s3c24xx/cpu.h> -#include <asm/arch/regs-serial.h> +#include <asm/plat-s3c/regs-serial.h> #include <asm/arch/regs-gpio.h> -#include <asm/arch/regs-ac97.h> +#include <asm/plat-s3c/regs-ac97.h> #include <asm/arch/regs-mem.h> #include <asm/arch/regs-lcd.h> #include <asm/arch/regs-sdi.h> -#include <asm/arch/regs-iis.h> -#include <asm/arch/regs-spi.h> +#include <asm/plat-s3c24xx/regs-iis.h> +#include <asm/plat-s3c24xx/regs-spi.h> #define MAP(x) { \ [0] = (x) | DMA_CH_VALID, \ diff --git a/arch/arm/mach-s3c2443/mach-smdk2443.c b/arch/arm/mach-s3c2443/mach-smdk2443.c index b1eb709ee65a..8cd93130ef36 100644 --- a/arch/arm/mach-s3c2443/mach-smdk2443.c +++ b/arch/arm/mach-s3c2443/mach-smdk2443.c @@ -31,7 +31,7 @@ #include <asm/irq.h> #include <asm/mach-types.h> -#include <asm/arch/regs-serial.h> +#include <asm/plat-s3c/regs-serial.h> #include <asm/arch/regs-gpio.h> #include <asm/arch/regs-lcd.h> diff --git a/arch/arm/mach-sa1100/Kconfig b/arch/arm/mach-sa1100/Kconfig index cd67ab1b217b..f99d9013905f 100644 --- a/arch/arm/mach-sa1100/Kconfig +++ b/arch/arm/mach-sa1100/Kconfig @@ -101,6 +101,16 @@ config SA1100_JORNADA720 handheld computer. See <http://www.hp.com/jornada/products/720> for details. +config SA1100_JORNADA720_SSP + bool "HP Jornada 720 Extended SSP driver" + select SA1100_SSP + depends on SA1100_JORNADA720 + help + Say Y here if you have a HP Jornada 7xx handheld computer and you + want to access devices connected to the MCU. Those include the + keyboard, touchscreen, backlight and battery. This driver also activates + the generic SSP which it extends. + config SA1100_HACKKIT bool "HackKit Core CPU Board" help @@ -145,8 +155,7 @@ config SA1100_SSP help Say Y here to enable support for the generic PIO SSP driver. This isn't for audio support, but for attached sensors and - other devices, eg for BadgePAD 4 sensor support, or Jornada - 720 touchscreen support. + other devices, eg for BadgePAD 4 sensor support. config H3600_SLEEVE tristate "Compaq iPAQ Handheld sleeve support" diff --git a/arch/arm/mach-sa1100/Makefile b/arch/arm/mach-sa1100/Makefile index e27f15042a22..7a61e8d33ab7 100644 --- a/arch/arm/mach-sa1100/Makefile +++ b/arch/arm/mach-sa1100/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_SA1100_HACKKIT) += hackkit.o led-$(CONFIG_SA1100_HACKKIT) += leds-hackkit.o obj-$(CONFIG_SA1100_JORNADA720) += jornada720.o +obj-$(CONFIG_SA1100_JORNADA720_SSP) += jornada720_ssp.o obj-$(CONFIG_SA1100_LART) += lart.o led-$(CONFIG_SA1100_LART) += leds-lart.o @@ -51,3 +52,4 @@ obj-$(CONFIG_LEDS) += $(led-y) # Miscelaneous functions obj-$(CONFIG_PM) += pm.o sleep.o obj-$(CONFIG_SA1100_SSP) += ssp.o + diff --git a/arch/arm/mach-sa1100/jornada720_ssp.c b/arch/arm/mach-sa1100/jornada720_ssp.c new file mode 100644 index 000000000000..0a45e1ac8ad6 --- /dev/null +++ b/arch/arm/mach-sa1100/jornada720_ssp.c @@ -0,0 +1,201 @@ +/** + * arch/arm/mac-sa1100/jornada720_ssp.c + * + * Copyright (C) 2006/2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com> + * Copyright (C) 2006 Filip Zyzniewski <filip.zyzniewski@tefnet.pl> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * SSP driver for the HP Jornada 710/720/728 + */ + +#include <linux/delay.h> +#include <linux/errno.h> +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/sched.h> +#include <linux/slab.h> + +#include <asm/hardware.h> +#include <asm/hardware/ssp.h> +#include <asm/arch/jornada720.h> + +static DEFINE_SPINLOCK(jornada_ssp_lock); +static unsigned long jornada_ssp_flags; + +/** + * jornada_ssp_reverse - reverses input byte + * + * we need to reverse all data we recieve from the mcu due to its physical location + * returns : 01110111 -> 11101110 + */ +u8 inline jornada_ssp_reverse(u8 byte) +{ + return + ((0x80 & byte) >> 7) | + ((0x40 & byte) >> 5) | + ((0x20 & byte) >> 3) | + ((0x10 & byte) >> 1) | + ((0x08 & byte) << 1) | + ((0x04 & byte) << 3) | + ((0x02 & byte) << 5) | + ((0x01 & byte) << 7); +}; +EXPORT_SYMBOL(jornada_ssp_reverse); + +/** + * jornada_ssp_byte - waits for ready ssp bus and sends byte + * + * waits for fifo buffer to clear and then transmits, if it doesn't then we will + * timeout after <timeout> rounds. Needs mcu running before its called. + * + * returns : %mcu output on success + * : %-ETIMEOUT on timeout + */ +int jornada_ssp_byte(u8 byte) +{ + int timeout = 400000; + u16 ret; + + while ((GPLR & GPIO_GPIO10)) { + if (!--timeout) { + printk(KERN_WARNING "SSP: timeout while waiting for transmit\n"); + return -ETIMEDOUT; + } + cpu_relax(); + } + + ret = jornada_ssp_reverse(byte) << 8; + + ssp_write_word(ret); + ssp_read_word(&ret); + + return jornada_ssp_reverse(ret); +}; +EXPORT_SYMBOL(jornada_ssp_byte); + +/** + * jornada_ssp_inout - decide if input is command or trading byte + * + * returns : (jornada_ssp_byte(byte)) on success + * : %-ETIMEOUT on timeout failure + */ +int jornada_ssp_inout(u8 byte) +{ + int ret, i; + + /* true means command byte */ + if (byte != TXDUMMY) { + ret = jornada_ssp_byte(byte); + /* Proper return to commands is TxDummy */ + if (ret != TXDUMMY) { + for (i = 0; i < 256; i++)/* flushing bus */ + if (jornada_ssp_byte(TXDUMMY) == -1) + break; + return -ETIMEDOUT; + } + } else /* Exchange TxDummy for data */ + ret = jornada_ssp_byte(TXDUMMY); + + return ret; +}; +EXPORT_SYMBOL(jornada_ssp_inout); + +/** + * jornada_ssp_start - enable mcu + * + */ +int jornada_ssp_start() +{ + spin_lock_irqsave(&jornada_ssp_lock, jornada_ssp_flags); + GPCR = GPIO_GPIO25; + udelay(50); + return 0; +}; +EXPORT_SYMBOL(jornada_ssp_start); + +/** + * jornada_ssp_end - disable mcu and turn off lock + * + */ +int jornada_ssp_end() +{ + GPSR = GPIO_GPIO25; + spin_unlock_irqrestore(&jornada_ssp_lock, jornada_ssp_flags); + return 0; +}; +EXPORT_SYMBOL(jornada_ssp_end); + +static int __init jornada_ssp_probe(struct platform_device *dev) +{ + int ret; + + GPSR = GPIO_GPIO25; + + ret = ssp_init(); + + /* worked fine, lets not bother with anything else */ + if (!ret) { + printk(KERN_INFO "SSP: device initialized with irq\n"); + return ret; + } + + printk(KERN_WARNING "SSP: initialization failed, trying non-irq solution \n"); + + /* init of Serial 4 port */ + Ser4MCCR0 = 0; + Ser4SSCR0 = 0x0387; + Ser4SSCR1 = 0x18; + + /* clear out any left over data */ + ssp_flush(); + + /* enable MCU */ + jornada_ssp_start(); + + /* see if return value makes sense */ + ret = jornada_ssp_inout(GETBRIGHTNESS); + + /* seems like it worked, just feed it with TxDummy to get rid of data */ + if (ret == TxDummy) + jornada_ssp_inout(TXDUMMY); + + jornada_ssp_end(); + + /* failed, lets just kill everything */ + if (ret == -ETIMEDOUT) { + printk(KERN_WARNING "SSP: attempts failed, bailing\n"); + ssp_exit(); + return -ENODEV; + } + + /* all fine */ + printk(KERN_INFO "SSP: device initialized\n"); + return 0; +}; + +static int jornada_ssp_remove(struct platform_device *dev) +{ + /* Note that this doesnt actually remove the driver, since theres nothing to remove + * It just makes sure everything is turned off */ + GPSR = GPIO_GPIO25; + ssp_exit(); + return 0; +}; + +struct platform_driver jornadassp_driver = { + .probe = jornada_ssp_probe, + .remove = jornada_ssp_remove, + .driver = { + .name = "jornada_ssp", + }, +}; + +static int __init jornada_ssp_init(void) +{ + return platform_driver_register(&jornadassp_driver); +} diff --git a/arch/arm/mach-sa1100/neponset.c b/arch/arm/mach-sa1100/neponset.c index 4cbf9468f654..9f1ed1509301 100644 --- a/arch/arm/mach-sa1100/neponset.c +++ b/arch/arm/mach-sa1100/neponset.c @@ -185,28 +185,21 @@ static int __devinit neponset_probe(struct platform_device *dev) /* * LDM power management. */ +static unsigned int neponset_saved_state; + static int neponset_suspend(struct platform_device *dev, pm_message_t state) { /* * Save state. */ - if (!dev->dev.power.saved_state) - dev->dev.power.saved_state = kmalloc(sizeof(unsigned int), GFP_KERNEL); - if (!dev->dev.power.saved_state) - return -ENOMEM; - - *(unsigned int *)dev->dev.power.saved_state = NCR_0; + neponset_saved_state = NCR_0; return 0; } static int neponset_resume(struct platform_device *dev) { - if (dev->dev.power.saved_state) { - NCR_0 = *(unsigned int *)dev->dev.power.saved_state; - kfree(dev->dev.power.saved_state); - dev->dev.power.saved_state = NULL; - } + NCR_0 = neponset_saved_state; return 0; } @@ -299,6 +292,8 @@ static struct platform_device *devices[] __initdata = { &smc91x_device, }; +extern void sa1110_mb_disable(void); + static int __init neponset_init(void) { platform_driver_register(&neponset_device_driver); diff --git a/arch/arm/mach-sa1100/pm.c b/arch/arm/mach-sa1100/pm.c index d674cf343156..01a37d3c0727 100644 --- a/arch/arm/mach-sa1100/pm.c +++ b/arch/arm/mach-sa1100/pm.c @@ -57,12 +57,7 @@ enum { SLEEP_SAVE_SP = 0, static int sa11x0_pm_enter(suspend_state_t state) { unsigned long gpio, sleep_save[SLEEP_SAVE_SIZE]; - struct timespec delta, rtc; - /* preserve current time */ - rtc.tv_sec = RCNR; - rtc.tv_nsec = 0; - save_time_delta(&delta, &rtc); gpio = GPLR; /* save vital registers */ @@ -119,10 +114,6 @@ static int sa11x0_pm_enter(suspend_state_t state) */ PSSR = PSSR_PH; - /* restore current time */ - rtc.tv_sec = RCNR; - restore_time_delta(&delta, &rtc); - return 0; } diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c index 29cb0c1604ab..fdf7b016e7ad 100644 --- a/arch/arm/mach-sa1100/time.c +++ b/arch/arm/mach-sa1100/time.c @@ -21,25 +21,6 @@ #define RTC_DEF_DIVIDER (32768 - 1) #define RTC_DEF_TRIM 0 -static unsigned long __init sa1100_get_rtc_time(void) -{ - /* - * According to the manual we should be able to let RTTR be zero - * and then a default divisor for a 32.768KHz clock is used. - * Apparently this doesn't work, at least for my SA1110 rev 5. - * If the clock divider is uninitialized then reset it to the - * default value to get the 1Hz clock. - */ - if (RTTR == 0) { - RTTR = RTC_DEF_DIVIDER + (RTC_DEF_TRIM << 16); - printk(KERN_WARNING "Warning: uninitialized Real Time Clock\n"); - /* The current RTC value probably doesn't make sense either */ - RCNR = 0; - return 0; - } - return RCNR; -} - static int sa1100_set_rtc(void) { unsigned long current_time = xtime.tv_sec; @@ -117,15 +98,10 @@ static struct irqaction sa1100_timer_irq = { static void __init sa1100_timer_init(void) { - struct timespec tv; unsigned long flags; set_rtc = sa1100_set_rtc; - tv.tv_nsec = 0; - tv.tv_sec = sa1100_get_rtc_time(); - do_settimeofday(&tv); - OIER = 0; /* disable any timer interrupts */ OSSR = 0xf; /* clear status on all timers */ setup_irq(IRQ_OST0, &sa1100_timer_irq); diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index e7904bc92c73..12161ae445da 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -345,13 +345,14 @@ config CPU_XSC3 # ARMv6 config CPU_V6 bool "Support ARM V6 processor" - depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 + depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 + default y if ARCH_MX3 select CPU_32v6 select CPU_ABRT_EV6 select CPU_CACHE_V6 select CPU_CACHE_VIPT select CPU_CP15_MMU - select CPU_HAS_ASID + select CPU_HAS_ASID if MMU select CPU_COPY_V6 if MMU select CPU_TLB_V6 if MMU @@ -359,7 +360,7 @@ config CPU_V6 config CPU_32v6K bool "Support ARM V6K processor extensions" if !SMP depends on CPU_V6 - default y if SMP + default y if SMP && !ARCH_MX3 help Say Y here if your ARMv6 processor supports the 'K' extension. This enables the kernel to use some instructions not present @@ -377,7 +378,7 @@ config CPU_V7 select CPU_CACHE_V7 select CPU_CACHE_VIPT select CPU_CP15_MMU - select CPU_HAS_ASID + select CPU_HAS_ASID if MMU select CPU_COPY_V6 if MMU select CPU_TLB_V7 if MMU @@ -405,6 +406,7 @@ config CPU_32v5 config CPU_32v6 bool + select TLS_REG_EMUL if !CPU_32v6K && !MMU config CPU_32v7 bool @@ -598,7 +600,7 @@ config CPU_DCACHE_SIZE config CPU_DCACHE_WRITETHROUGH bool "Force write through D-cache" - depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE + depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE default y if CPU_ARM925T help Say Y here to use the data cache in writethrough mode. Unless you @@ -611,12 +613,6 @@ config CPU_CACHE_ROUND_ROBIN Say Y here to use the predictable round-robin cache replacement policy. Unless you specifically require this or are unsure, say N. -config CPU_L2CACHE_DISABLE - bool "Disable level 2 cache" - depends on CPU_V7 - help - Say Y here to disable the level 2 cache. If unsure, say N. - config CPU_BPREDICT_DISABLE bool "Disable branch prediction" depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7 diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 08a36f1b35d2..b4e9b734e0bd 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -17,6 +17,7 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/init.h> +#include <linux/spinlock.h> #include <asm/cacheflush.h> #include <asm/io.h> @@ -25,14 +26,19 @@ #define CACHE_LINE_SIZE 32 static void __iomem *l2x0_base; +static DEFINE_SPINLOCK(l2x0_lock); static inline void sync_writel(unsigned long val, unsigned long reg, unsigned long complete_mask) { + unsigned long flags; + + spin_lock_irqsave(&l2x0_lock, flags); writel(val, l2x0_base + reg); /* wait for the operation to complete */ while (readl(l2x0_base + reg) & complete_mask) ; + spin_unlock_irqrestore(&l2x0_lock, flags); } static inline void cache_sync(void) diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c index 75d491448e45..846cce48e2b7 100644 --- a/arch/arm/mm/fault.c +++ b/arch/arm/mm/fault.c @@ -145,8 +145,8 @@ void do_bad_area(unsigned long addr, unsigned int fsr, struct pt_regs *regs) __do_kernel_fault(mm, addr, fsr, regs); } -#define VM_FAULT_BADMAP (-20) -#define VM_FAULT_BADACCESS (-21) +#define VM_FAULT_BADMAP 0x010000 +#define VM_FAULT_BADACCESS 0x020000 static int __do_page_fault(struct mm_struct *mm, unsigned long addr, unsigned int fsr, @@ -183,20 +183,20 @@ good_area: */ survive: fault = handle_mm_fault(mm, vma, addr & PAGE_MASK, fsr & (1 << 11)); - - /* - * Handle the "normal" cases first - successful and sigbus - */ - switch (fault) { - case VM_FAULT_MAJOR: + if (unlikely(fault & VM_FAULT_ERROR)) { + if (fault & VM_FAULT_OOM) + goto out_of_memory; + else if (fault & VM_FAULT_SIGBUS) + return fault; + BUG(); + } + if (fault & VM_FAULT_MAJOR) tsk->maj_flt++; - return fault; - case VM_FAULT_MINOR: + else tsk->min_flt++; - case VM_FAULT_SIGBUS: - return fault; - } + return fault; +out_of_memory: if (!is_init(tsk)) goto out; @@ -249,7 +249,7 @@ do_page_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs) /* * Handle the "normal" case first - VM_FAULT_MAJOR / VM_FAULT_MINOR */ - if (fault >= VM_FAULT_MINOR) + if (likely(!(fault & (VM_FAULT_ERROR | VM_FAULT_BADMAP | VM_FAULT_BADACCESS)))) return 0; /* @@ -259,8 +259,7 @@ do_page_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs) if (!user_mode(regs)) goto no_context; - switch (fault) { - case VM_FAULT_OOM: + if (fault & VM_FAULT_OOM) { /* * We ran out of memory, or some other thing * happened to us that made us unable to handle @@ -269,17 +268,15 @@ do_page_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs) printk("VM: killing process %s\n", tsk->comm); do_exit(SIGKILL); return 0; - - case VM_FAULT_SIGBUS: + } + if (fault & VM_FAULT_SIGBUS) { /* * We had some memory, but were unable to * successfully fix up this page fault. */ sig = SIGBUS; code = BUS_ADRERR; - break; - - default: + } else { /* * Something tried to access memory that * isn't in our memory map.. @@ -287,7 +284,6 @@ do_page_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs) sig = SIGSEGV; code = fault == VM_FAULT_BADACCESS ? SEGV_ACCERR : SEGV_MAPERR; - break; } __do_user_fault(tsk, addr, fsr, sig, code, regs); diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c index f3ade18862aa..75952779ce19 100644 --- a/arch/arm/mm/ioremap.c +++ b/arch/arm/mm/ioremap.c @@ -280,7 +280,10 @@ __arm_ioremap_pfn(unsigned long pfn, unsigned long offset, size_t size, if (!type) return NULL; - size = PAGE_ALIGN(size); + /* + * Page align the mapping size, taking account of any offset. + */ + size = PAGE_ALIGN(offset + size); area = get_vm_area(size, VM_IOREMAP); if (!area) @@ -325,11 +328,6 @@ __arm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype) if (!size || last_addr < phys_addr) return NULL; - /* - * Page align the mapping size - */ - size = PAGE_ALIGN(last_addr + 1) - phys_addr; - return __arm_ioremap_pfn(pfn, offset, size, mtype); } EXPORT_SYMBOL(__arm_ioremap); diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index 3b5e47dc0c97..e5d61ee3d4a1 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -114,6 +114,10 @@ static void __init early_cachepolicy(char **p) } if (i == ARRAY_SIZE(cache_policies)) printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n"); + if (cpu_architecture() >= CPU_ARCH_ARMv6) { + printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n"); + cachepolicy = CPOLICY_WRITEBACK; + } flush_cache_all(); set_cr(cr_alignment); } @@ -252,13 +256,15 @@ static void __init build_mem_type_table(void) int cpu_arch = cpu_architecture(); int i; + if (cpu_arch < CPU_ARCH_ARMv6) { #if defined(CONFIG_CPU_DCACHE_DISABLE) - if (cachepolicy > CPOLICY_BUFFERED) - cachepolicy = CPOLICY_BUFFERED; + if (cachepolicy > CPOLICY_BUFFERED) + cachepolicy = CPOLICY_BUFFERED; #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH) - if (cachepolicy > CPOLICY_WRITETHROUGH) - cachepolicy = CPOLICY_WRITETHROUGH; + if (cachepolicy > CPOLICY_WRITETHROUGH) + cachepolicy = CPOLICY_WRITETHROUGH; #endif + } if (cpu_arch < CPU_ARCH_ARMv5) { if (cachepolicy >= CPOLICY_WRITEALLOC) cachepolicy = CPOLICY_WRITEBACK; diff --git a/arch/arm/mm/proc-syms.c b/arch/arm/mm/proc-syms.c index 9f396b4fa0b7..2b5ba396e3a6 100644 --- a/arch/arm/mm/proc-syms.c +++ b/arch/arm/mm/proc-syms.c @@ -31,12 +31,14 @@ EXPORT_SYMBOL(__cpuc_coherent_kern_range); EXPORT_SYMBOL(cpu_cache); #endif +#ifdef CONFIG_MMU #ifndef MULTI_USER EXPORT_SYMBOL(__cpu_clear_user_page); EXPORT_SYMBOL(__cpu_copy_user_page); #else EXPORT_SYMBOL(cpu_user); #endif +#endif /* * No module should need to touch the TLB (and currently diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 718f4782ee8b..e0acc5ae6f6f 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -77,6 +77,7 @@ ENTRY(cpu_v7_dcache_clean_area) * - we are not using split page tables */ ENTRY(cpu_v7_switch_mm) +#ifdef CONFIG_MMU mov r2, #0 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id orr r0, r0, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB @@ -86,6 +87,7 @@ ENTRY(cpu_v7_switch_mm) isb mcr p15, 0, r1, c13, c0, 1 @ set context ID isb +#endif mov pc, lr /* @@ -109,6 +111,7 @@ ENTRY(cpu_v7_switch_mm) * 1111 0 1 1 r/w r/w */ ENTRY(cpu_v7_set_pte_ext) +#ifdef CONFIG_MMU str r1, [r0], #-2048 @ linux version bic r3, r1, #0x000003f0 @@ -136,6 +139,7 @@ ENTRY(cpu_v7_set_pte_ext) str r3, [r0] mcr p15, 0, r0, c7, c10, 1 @ flush_pte +#endif mov pc, lr cpu_v7_name: @@ -169,6 +173,7 @@ __v7_setup: mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate #endif dsb +#ifdef CONFIG_MMU mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs mcr p15, 0, r10, c2, c0, 2 @ TTB control register orr r4, r4, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB @@ -176,21 +181,12 @@ __v7_setup: mcr p15, 0, r4, c2, c0, 1 @ load TTB1 mov r10, #0x1f @ domains 0, 1 = manager mcr p15, 0, r10, c3, c0, 0 @ load domain access register -#ifndef CONFIG_CPU_L2CACHE_DISABLE - @ L2 cache configuration in the L2 aux control register - mrc p15, 1, r10, c9, c0, 2 - bic r10, r10, #(1 << 16) @ L2 outer cache - mcr p15, 1, r10, c9, c0, 2 - @ L2 cache is enabled in the aux control register - mrc p15, 0, r10, c1, c0, 1 - orr r10, r10, #2 - mcr p15, 0, r10, c1, c0, 1 #endif - mrc p15, 0, r0, c1, c0, 0 @ read control register - ldr r10, cr1_clear @ get mask for bits to clear - bic r0, r0, r10 @ clear bits them - ldr r10, cr1_set @ get mask for bits to set - orr r0, r0, r10 @ set them + adr r5, v7_crval + ldmia r5, {r5, r6} + mrc p15, 0, r0, c1, c0, 0 @ read control register + bic r0, r0, r5 @ clear bits them + orr r0, r0, r6 @ set them mov pc, lr @ return to head.S:__ret /* @@ -199,12 +195,9 @@ __v7_setup: * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced * 0 110 0011 1.00 .111 1101 < we want */ - .type cr1_clear, #object - .type cr1_set, #object -cr1_clear: - .word 0x0120c302 -cr1_set: - .word 0x00c0387d + .type v7_crval, #object +v7_crval: + crval clear=0x0120c302, mmuset=0x00c0387d, ucset=0x00c0187c __v7_setup_stack: .space 4 * 11 @ 11 registers diff --git a/arch/arm/plat-iop/Makefile b/arch/arm/plat-iop/Makefile index 4d2b1da3cd82..36bff0325959 100644 --- a/arch/arm/plat-iop/Makefile +++ b/arch/arm/plat-iop/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_IOP32X) += setup.o obj-$(CONFIG_ARCH_IOP32X) += time.o obj-$(CONFIG_ARCH_IOP32X) += io.o obj-$(CONFIG_ARCH_IOP32X) += cp6.o +obj-$(CONFIG_ARCH_IOP32X) += adma.o # IOP33X obj-$(CONFIG_ARCH_IOP33X) += gpio.o @@ -21,6 +22,7 @@ obj-$(CONFIG_ARCH_IOP33X) += setup.o obj-$(CONFIG_ARCH_IOP33X) += time.o obj-$(CONFIG_ARCH_IOP33X) += io.o obj-$(CONFIG_ARCH_IOP33X) += cp6.o +obj-$(CONFIG_ARCH_IOP33X) += adma.o # IOP13XX obj-$(CONFIG_ARCH_IOP13XX) += cp6.o diff --git a/arch/arm/plat-iop/adma.c b/arch/arm/plat-iop/adma.c new file mode 100644 index 000000000000..53c5e9a52eb1 --- /dev/null +++ b/arch/arm/plat-iop/adma.c @@ -0,0 +1,209 @@ +/* + * platform device definitions for the iop3xx dma/xor engines + * Copyright © 2006, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + */ +#include <linux/platform_device.h> +#include <asm/hardware/iop3xx.h> +#include <linux/dma-mapping.h> +#include <asm/arch/adma.h> +#include <asm/hardware/iop_adma.h> + +#ifdef CONFIG_ARCH_IOP32X +#define IRQ_DMA0_EOT IRQ_IOP32X_DMA0_EOT +#define IRQ_DMA0_EOC IRQ_IOP32X_DMA0_EOC +#define IRQ_DMA0_ERR IRQ_IOP32X_DMA0_ERR + +#define IRQ_DMA1_EOT IRQ_IOP32X_DMA1_EOT +#define IRQ_DMA1_EOC IRQ_IOP32X_DMA1_EOC +#define IRQ_DMA1_ERR IRQ_IOP32X_DMA1_ERR + +#define IRQ_AA_EOT IRQ_IOP32X_AA_EOT +#define IRQ_AA_EOC IRQ_IOP32X_AA_EOC +#define IRQ_AA_ERR IRQ_IOP32X_AA_ERR +#endif +#ifdef CONFIG_ARCH_IOP33X +#define IRQ_DMA0_EOT IRQ_IOP33X_DMA0_EOT +#define IRQ_DMA0_EOC IRQ_IOP33X_DMA0_EOC +#define IRQ_DMA0_ERR IRQ_IOP33X_DMA0_ERR + +#define IRQ_DMA1_EOT IRQ_IOP33X_DMA1_EOT +#define IRQ_DMA1_EOC IRQ_IOP33X_DMA1_EOC +#define IRQ_DMA1_ERR IRQ_IOP33X_DMA1_ERR + +#define IRQ_AA_EOT IRQ_IOP33X_AA_EOT +#define IRQ_AA_EOC IRQ_IOP33X_AA_EOC +#define IRQ_AA_ERR IRQ_IOP33X_AA_ERR +#endif +/* AAU and DMA Channels */ +static struct resource iop3xx_dma_0_resources[] = { + [0] = { + .start = IOP3XX_DMA_PHYS_BASE(0), + .end = IOP3XX_DMA_UPPER_PA(0), + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_DMA0_EOT, + .end = IRQ_DMA0_EOT, + .flags = IORESOURCE_IRQ + }, + [2] = { + .start = IRQ_DMA0_EOC, + .end = IRQ_DMA0_EOC, + .flags = IORESOURCE_IRQ + }, + [3] = { + .start = IRQ_DMA0_ERR, + .end = IRQ_DMA0_ERR, + .flags = IORESOURCE_IRQ + } +}; + +static struct resource iop3xx_dma_1_resources[] = { + [0] = { + .start = IOP3XX_DMA_PHYS_BASE(1), + .end = IOP3XX_DMA_UPPER_PA(1), + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_DMA1_EOT, + .end = IRQ_DMA1_EOT, + .flags = IORESOURCE_IRQ + }, + [2] = { + .start = IRQ_DMA1_EOC, + .end = IRQ_DMA1_EOC, + .flags = IORESOURCE_IRQ + }, + [3] = { + .start = IRQ_DMA1_ERR, + .end = IRQ_DMA1_ERR, + .flags = IORESOURCE_IRQ + } +}; + + +static struct resource iop3xx_aau_resources[] = { + [0] = { + .start = IOP3XX_AAU_PHYS_BASE, + .end = IOP3XX_AAU_UPPER_PA, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_AA_EOT, + .end = IRQ_AA_EOT, + .flags = IORESOURCE_IRQ + }, + [2] = { + .start = IRQ_AA_EOC, + .end = IRQ_AA_EOC, + .flags = IORESOURCE_IRQ + }, + [3] = { + .start = IRQ_AA_ERR, + .end = IRQ_AA_ERR, + .flags = IORESOURCE_IRQ + } +}; + +static u64 iop3xx_adma_dmamask = DMA_32BIT_MASK; + +static struct iop_adma_platform_data iop3xx_dma_0_data = { + .hw_id = DMA0_ID, + .pool_size = PAGE_SIZE, +}; + +static struct iop_adma_platform_data iop3xx_dma_1_data = { + .hw_id = DMA1_ID, + .pool_size = PAGE_SIZE, +}; + +static struct iop_adma_platform_data iop3xx_aau_data = { + .hw_id = AAU_ID, + .pool_size = 3 * PAGE_SIZE, +}; + +struct platform_device iop3xx_dma_0_channel = { + .name = "iop-adma", + .id = 0, + .num_resources = 4, + .resource = iop3xx_dma_0_resources, + .dev = { + .dma_mask = &iop3xx_adma_dmamask, + .coherent_dma_mask = DMA_64BIT_MASK, + .platform_data = (void *) &iop3xx_dma_0_data, + }, +}; + +struct platform_device iop3xx_dma_1_channel = { + .name = "iop-adma", + .id = 1, + .num_resources = 4, + .resource = iop3xx_dma_1_resources, + .dev = { + .dma_mask = &iop3xx_adma_dmamask, + .coherent_dma_mask = DMA_64BIT_MASK, + .platform_data = (void *) &iop3xx_dma_1_data, + }, +}; + +struct platform_device iop3xx_aau_channel = { + .name = "iop-adma", + .id = 2, + .num_resources = 4, + .resource = iop3xx_aau_resources, + .dev = { + .dma_mask = &iop3xx_adma_dmamask, + .coherent_dma_mask = DMA_64BIT_MASK, + .platform_data = (void *) &iop3xx_aau_data, + }, +}; + +static int __init iop3xx_adma_cap_init(void) +{ + #ifdef CONFIG_ARCH_IOP32X /* the 32x DMA does not perform CRC32C */ + dma_cap_set(DMA_MEMCPY, iop3xx_dma_0_data.cap_mask); + dma_cap_set(DMA_INTERRUPT, iop3xx_dma_0_data.cap_mask); + #else + dma_cap_set(DMA_MEMCPY, iop3xx_dma_0_data.cap_mask); + dma_cap_set(DMA_MEMCPY_CRC32C, iop3xx_dma_0_data.cap_mask); + dma_cap_set(DMA_INTERRUPT, iop3xx_dma_0_data.cap_mask); + #endif + + #ifdef CONFIG_ARCH_IOP32X /* the 32x DMA does not perform CRC32C */ + dma_cap_set(DMA_MEMCPY, iop3xx_dma_1_data.cap_mask); + dma_cap_set(DMA_INTERRUPT, iop3xx_dma_1_data.cap_mask); + #else + dma_cap_set(DMA_MEMCPY, iop3xx_dma_1_data.cap_mask); + dma_cap_set(DMA_MEMCPY_CRC32C, iop3xx_dma_1_data.cap_mask); + dma_cap_set(DMA_INTERRUPT, iop3xx_dma_1_data.cap_mask); + #endif + + #ifdef CONFIG_ARCH_IOP32X /* the 32x AAU does not perform zero sum */ + dma_cap_set(DMA_XOR, iop3xx_aau_data.cap_mask); + dma_cap_set(DMA_MEMSET, iop3xx_aau_data.cap_mask); + dma_cap_set(DMA_INTERRUPT, iop3xx_aau_data.cap_mask); + #else + dma_cap_set(DMA_XOR, iop3xx_aau_data.cap_mask); + dma_cap_set(DMA_ZERO_SUM, iop3xx_aau_data.cap_mask); + dma_cap_set(DMA_MEMSET, iop3xx_aau_data.cap_mask); + dma_cap_set(DMA_INTERRUPT, iop3xx_aau_data.cap_mask); + #endif + + return 0; +} + +arch_initcall(iop3xx_adma_cap_init); diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c index 100d57ad98ed..ba3d21d8fba3 100644 --- a/arch/arm/plat-iop/time.c +++ b/arch/arm/plat-iop/time.c @@ -78,6 +78,13 @@ static struct irqaction iop_timer_irq = { .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, }; +static unsigned long iop_tick_rate; +unsigned long get_iop_tick_rate(void) +{ + return iop_tick_rate; +} +EXPORT_SYMBOL(get_iop_tick_rate); + void __init iop_init_time(unsigned long tick_rate) { u32 timer_ctl; @@ -85,6 +92,7 @@ void __init iop_init_time(unsigned long tick_rate) ticks_per_jiffy = (tick_rate + HZ/2) / HZ; ticks_per_usec = tick_rate / 1000000; next_jiffy_time = 0xffffffff; + iop_tick_rate = tick_rate; timer_ctl = IOP_TMR_EN | IOP_TMR_PRIVILEGED | IOP_TMR_RELOAD | IOP_TMR_RATIO_1_1; diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig new file mode 100644 index 000000000000..03a65c0dfb60 --- /dev/null +++ b/arch/arm/plat-mxc/Kconfig @@ -0,0 +1,20 @@ +if ARCH_MXC + +menu "Freescale MXC Implementations" + +choice + prompt "MXC/iMX System Type" + default 0 + +config ARCH_MX3 + bool "MX3-based" + help + This enables support for systems based on the Freescale i.MX3 family + +endchoice + +source "arch/arm/mach-mx3/Kconfig" + +endmenu + +endif diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile new file mode 100644 index 000000000000..66ad9c2b6d64 --- /dev/null +++ b/arch/arm/plat-mxc/Makefile @@ -0,0 +1,10 @@ +# +# Makefile for the linux kernel. +# + +# Common support +obj-y := irq.o + +obj-m := +obj-n := +obj- := diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c new file mode 100644 index 000000000000..87d253bc3d3c --- /dev/null +++ b/arch/arm/plat-mxc/irq.c @@ -0,0 +1,83 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/init.h> +#include <linux/device.h> +#include <linux/errno.h> +#include <asm/hardware.h> +#include <asm/io.h> +#include <asm/irq.h> +#include <asm/mach/irq.h> +#include <asm/arch/common.h> + +/*! + * Disable interrupt number "irq" in the AVIC + * + * @param irq interrupt source number + */ +static void mxc_mask_irq(unsigned int irq) +{ + __raw_writel(irq, AVIC_INTDISNUM); +} + +/*! + * Enable interrupt number "irq" in the AVIC + * + * @param irq interrupt source number + */ +static void mxc_unmask_irq(unsigned int irq) +{ + __raw_writel(irq, AVIC_INTENNUM); +} + +static struct irq_chip mxc_avic_chip = { + .mask_ack = mxc_mask_irq, + .mask = mxc_mask_irq, + .unmask = mxc_unmask_irq, +}; + +/*! + * This function initializes the AVIC hardware and disables all the + * interrupts. It registers the interrupt enable and disable functions + * to the kernel for each interrupt source. + */ +void __init mxc_init_irq(void) +{ + int i; + u32 reg; + + /* put the AVIC into the reset value with + * all interrupts disabled + */ + __raw_writel(0, AVIC_INTCNTL); + __raw_writel(0x1f, AVIC_NIMASK); + + /* disable all interrupts */ + __raw_writel(0, AVIC_INTENABLEH); + __raw_writel(0, AVIC_INTENABLEL); + + /* all IRQ no FIQ */ + __raw_writel(0, AVIC_INTTYPEH); + __raw_writel(0, AVIC_INTTYPEL); + for (i = 0; i < MXC_MAX_INT_LINES; i++) { + set_irq_chip(i, &mxc_avic_chip); + set_irq_handler(i, handle_level_irq); + set_irq_flags(i, IRQF_VALID); + } + + /* Set WDOG2's interrupt the highest priority level (bit 28-31) */ + reg = __raw_readl(AVIC_NIPRIORITY6); + reg |= (0xF << 28); + __raw_writel(reg, AVIC_NIPRIORITY6); + + printk(KERN_INFO "MXC IRQ initialized\n"); +} diff --git a/arch/arm/plat-omap/timer32k.c b/arch/arm/plat-omap/timer32k.c index 2feceec8eccd..b0af014b0e2c 100644 --- a/arch/arm/plat-omap/timer32k.c +++ b/arch/arm/plat-omap/timer32k.c @@ -156,6 +156,8 @@ static void omap_32k_timer_set_mode(enum clock_event_mode mode, case CLOCK_EVT_MODE_SHUTDOWN: omap_32k_timer_stop(); break; + case CLOCK_EVT_MODE_RESUME: + break; } } diff --git a/arch/arm/plat-s3c/Kconfig b/arch/arm/plat-s3c/Kconfig new file mode 100644 index 000000000000..31656c33e05e --- /dev/null +++ b/arch/arm/plat-s3c/Kconfig @@ -0,0 +1,104 @@ +# arch/arm/plat-s3c/Kconfig +# +# Copyright 2007 Simtec Electronics +# +# Licensed under GPLv2 + +config PLAT_S3C + bool + depends on ARCH_S3C2410 + default y if ARCH_S3C2410 + select NO_IOPORT + help + Base platform code for any Samsung S3C device + +# low-level serial option nodes + +config CPU_LLSERIAL_S3C2410_ONLY + bool + depends on ARCH_S3C2410 + default y if CPU_LLSERIAL_S3C2410 && !CPU_LLSERIAL_S3C2440 + +config CPU_LLSERIAL_S3C2440_ONLY + bool + depends on ARCH_S3C2410 + default y if CPU_LLSERIAL_S3C2440 && !CPU_LLSERIAL_S3C2410 + +config CPU_LLSERIAL_S3C2410 + bool + depends on ARCH_S3C2410 + help + Selected if there is an S3C2410 (or register compatible) serial + low-level implementation needed + +config CPU_LLSERIAL_S3C2440 + bool + depends on ARCH_S3C2410 + help + Selected if there is an S3C2440 (or register compatible) serial + low-level implementation needed + +# boot configurations + +comment "Boot options" + +config S3C_BOOT_WATCHDOG + bool "S3C Initialisation watchdog" + depends on PLAT_S3C && S3C2410_WATCHDOG + help + Say y to enable the watchdog during the kernel decompression + stage. If the kernel fails to uncompress, then the watchdog + will trigger a reset and the system should restart. + +config S3C_BOOT_ERROR_RESET + bool "S3C Reboot on decompression error" + depends on PLAT_S3C + help + Say y here to use the watchdog to reset the system if the + kernel decompressor detects an error during decompression. + +comment "Power management" + +config S3C2410_PM_DEBUG + bool "S3C2410 PM Suspend debug" + depends on PLAT_S3C && PM + help + Say Y here if you want verbose debugging from the PM Suspend and + Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt> + for more information. + +config S3C2410_PM_CHECK + bool "S3C2410 PM Suspend Memory CRC" + depends on PLAT_S3C && PM && CRC32 + help + Enable the PM code's memory area checksum over sleep. This option + will generate CRCs of all blocks of memory, and store them before + going to sleep. The blocks are then checked on resume for any + errors. + + Note, this can take several seconds depending on memory size + and CPU speed. + + See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt> + +config S3C2410_PM_CHECK_CHUNKSIZE + int "S3C2410 PM Suspend CRC Chunksize (KiB)" + depends on PLAT_S3C && PM && S3C2410_PM_CHECK + default 64 + help + Set the chunksize in Kilobytes of the CRC for checking memory + corruption over suspend and resume. A smaller value will mean that + the CRC data block will take more memory, but wil identify any + faults with better precision. + + See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt> + +config S3C_LOWLEVEL_UART_PORT + int "S3C UART to use for low-level messages" + depends on PLAT_S3C + default 0 + help + Choice of which UART port to use for the low-level messages, + such as the `Uncompressing...` at start time. The value of + this configuration should be between zero and two. The port + must have been initialised by the boot-loader before use. diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig index b972f36d547c..b66fb3c4e228 100644 --- a/arch/arm/plat-s3c24xx/Kconfig +++ b/arch/arm/plat-s3c24xx/Kconfig @@ -10,7 +10,7 @@ config PLAT_S3C24XX default y if ARCH_S3C2410 select NO_IOPORT help - Base platform code for any Samsung S3C device + Base platform code for any Samsung S3C24XX device if PLAT_S3C24XX @@ -26,64 +26,6 @@ config PM_SIMTEC Common power management code for systems that are compatible with the Simtec style of power management -config S3C2410_BOOT_WATCHDOG - bool "S3C2410 Initialisation watchdog" - depends on ARCH_S3C2410 && S3C2410_WATCHDOG - help - Say y to enable the watchdog during the kernel decompression - stage. If the kernel fails to uncompress, then the watchdog - will trigger a reset and the system should restart. - -config S3C2410_BOOT_ERROR_RESET - bool "S3C2410 Reboot on decompression error" - depends on ARCH_S3C2410 - help - Say y here to use the watchdog to reset the system if the - kernel decompressor detects an error during decompression. - -config S3C2410_PM_DEBUG - bool "S3C2410 PM Suspend debug" - depends on ARCH_S3C2410 && PM - help - Say Y here if you want verbose debugging from the PM Suspend and - Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt> - for more information. - -config S3C2410_PM_CHECK - bool "S3C2410 PM Suspend Memory CRC" - depends on ARCH_S3C2410 && PM && CRC32 - help - Enable the PM code's memory area checksum over sleep. This option - will generate CRCs of all blocks of memory, and store them before - going to sleep. The blocks are then checked on resume for any - errors. - - Note, this can take several seconds depending on memory size - and CPU speed. - - See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt> - -config S3C2410_PM_CHECK_CHUNKSIZE - int "S3C2410 PM Suspend CRC Chunksize (KiB)" - depends on ARCH_S3C2410 && PM && S3C2410_PM_CHECK - default 64 - help - Set the chunksize in Kilobytes of the CRC for checking memory - corruption over suspend and resume. A smaller value will mean that - the CRC data block will take more memory, but wil identify any - faults with better precision. - - See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt> - -config S3C2410_LOWLEVEL_UART_PORT - int "S3C2410 UART to use for low-level messages" - default 0 - help - Choice of which UART port to use for the low-level messages, - such as the `Uncompressing...` at start time. The value of - this configuration should be between zero and two. The port - must have been initialised by the boot-loader before use. - config S3C2410_DMA bool "S3C2410 DMA support" depends on ARCH_S3C2410 diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/plat-s3c24xx/common-smdk.c index 7ed19b23ce56..398c7ac25296 100644 --- a/arch/arm/plat-s3c24xx/common-smdk.c +++ b/arch/arm/plat-s3c24xx/common-smdk.c @@ -38,7 +38,7 @@ #include <asm/arch/regs-gpio.h> #include <asm/arch/leds-gpio.h> -#include <asm/arch/nand.h> +#include <asm/plat-s3c/nand.h> #include <asm/plat-s3c24xx/common-smdk.h> #include <asm/plat-s3c24xx/devs.h> diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c index 8ce4904d3131..f513ab083b8f 100644 --- a/arch/arm/plat-s3c24xx/cpu.c +++ b/arch/arm/plat-s3c24xx/cpu.c @@ -38,7 +38,7 @@ #include <asm/mach/map.h> #include <asm/arch/regs-gpio.h> -#include <asm/arch/regs-serial.h> +#include <asm/plat-s3c/regs-serial.h> #include <asm/plat-s3c24xx/cpu.h> #include <asm/plat-s3c24xx/devs.h> diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c index 5875da0ae0eb..e546e933b3f7 100644 --- a/arch/arm/plat-s3c24xx/devs.c +++ b/arch/arm/plat-s3c24xx/devs.c @@ -28,12 +28,12 @@ #include <asm/io.h> #include <asm/irq.h> -#include <asm/arch/regs-serial.h> -#include <asm/arch/udc.h> +#include <asm/plat-s3c/regs-serial.h> +#include <asm/plat-s3c24xx/udc.h> #include <asm/plat-s3c24xx/devs.h> #include <asm/plat-s3c24xx/cpu.h> -#include <asm/arch/regs-spi.h> +#include <asm/plat-s3c24xx/regs-spi.h> /* Serial port registrations */ diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c index 08d80f2f51f2..6d048490c559 100644 --- a/arch/arm/plat-s3c24xx/dma.c +++ b/arch/arm/plat-s3c24xx/dma.c @@ -1333,7 +1333,7 @@ int __init s3c24xx_dma_init(unsigned int channels, unsigned int irq, dma_kmem = kmem_cache_create("dma_desc", sizeof(struct s3c2410_dma_buf), 0, SLAB_HWCACHE_ALIGN, - s3c2410_dma_cache_ctor, NULL); + s3c2410_dma_cache_ctor); if (dma_kmem == NULL) { printk(KERN_ERR "dma failed to make kmem cache\n"); diff --git a/arch/arm/plat-s3c24xx/pm.c b/arch/arm/plat-s3c24xx/pm.c index 5692eccdf4d1..eab1850616d8 100644 --- a/arch/arm/plat-s3c24xx/pm.c +++ b/arch/arm/plat-s3c24xx/pm.c @@ -40,7 +40,7 @@ #include <asm/hardware.h> #include <asm/io.h> -#include <asm/arch/regs-serial.h> +#include <asm/plat-s3c/regs-serial.h> #include <asm/arch/regs-clock.h> #include <asm/arch/regs-gpio.h> #include <asm/arch/regs-mem.h> diff --git a/arch/arm/plat-s3c24xx/s3c244x.c b/arch/arm/plat-s3c24xx/s3c244x.c index 767f2e9a3a55..3444b13afac5 100644 --- a/arch/arm/plat-s3c24xx/s3c244x.c +++ b/arch/arm/plat-s3c24xx/s3c244x.c @@ -30,7 +30,7 @@ #include <asm/irq.h> #include <asm/arch/regs-clock.h> -#include <asm/arch/regs-serial.h> +#include <asm/plat-s3c/regs-serial.h> #include <asm/arch/regs-gpio.h> #include <asm/arch/regs-gpioj.h> #include <asm/arch/regs-dsc.h> @@ -47,7 +47,6 @@ static struct map_desc s3c244x_iodesc[] __initdata = { IODESC_ENT(CLKPWR), IODESC_ENT(TIMER), IODESC_ENT(WATCHDOG), - IODESC_ENT(LCD), }; /* uart initialisation */ diff --git a/arch/arm/plat-s3c24xx/sleep.S b/arch/arm/plat-s3c24xx/sleep.S index 7b7ae790b00d..d47113bbc34c 100644 --- a/arch/arm/plat-s3c24xx/sleep.S +++ b/arch/arm/plat-s3c24xx/sleep.S @@ -32,7 +32,7 @@ #include <asm/arch/regs-gpio.h> #include <asm/arch/regs-clock.h> #include <asm/arch/regs-mem.h> -#include <asm/arch/regs-serial.h> +#include <asm/plat-s3c/regs-serial.h> /* CONFIG_DEBUG_RESUME is dangerous if your bootloader does not * reset the UART configuration, only enable if you really need this! diff --git a/arch/arm/plat-s3c24xx/time.c b/arch/arm/plat-s3c24xx/time.c index b7667375bcec..2ec1daaa0e53 100644 --- a/arch/arm/plat-s3c24xx/time.c +++ b/arch/arm/plat-s3c24xx/time.c @@ -33,7 +33,7 @@ #include <asm/io.h> #include <asm/irq.h> #include <asm/arch/map.h> -#include <asm/arch/regs-timer.h> +#include <asm/plat-s3c/regs-timer.h> #include <asm/arch/regs-irq.h> #include <asm/mach/time.h> diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S index d4b7b229631d..0ac022f800a1 100644 --- a/arch/arm/vfp/vfphw.S +++ b/arch/arm/vfp/vfphw.S @@ -74,14 +74,14 @@ vfp_support_entry: VFPFMRX r1, FPEXC @ Is the VFP enabled? DBGSTR1 "fpexc %08x", r1 - tst r1, #FPEXC_ENABLE + tst r1, #FPEXC_EN bne look_for_VFP_exceptions @ VFP is already enabled DBGSTR1 "enable %x", r10 ldr r3, last_VFP_context_address - orr r1, r1, #FPEXC_ENABLE @ user FPEXC has the enable bit set + orr r1, r1, #FPEXC_EN @ user FPEXC has the enable bit set ldr r4, [r3, r11, lsl #2] @ last_VFP_context pointer - bic r5, r1, #FPEXC_EXCEPTION @ make sure exceptions are disabled + bic r5, r1, #FPEXC_EX @ make sure exceptions are disabled cmp r4, r10 beq check_for_exception @ we are returning to the same @ process, so the registers are @@ -124,7 +124,7 @@ no_old_VFP_process: VFPFMXR FPSCR, r5 @ restore status check_for_exception: - tst r1, #FPEXC_EXCEPTION + tst r1, #FPEXC_EX bne process_exception @ might as well handle the pending @ exception before retrying branch @ out before setting an FPEXC that @@ -136,10 +136,10 @@ check_for_exception: look_for_VFP_exceptions: - tst r1, #FPEXC_EXCEPTION + tst r1, #FPEXC_EX bne process_exception VFPFMRX r5, FPSCR - tst r5, #FPSCR_IXE @ IXE doesn't set FPEXC_EXCEPTION ! + tst r5, #FPSCR_IXE @ IXE doesn't set FPEXC_EX ! bne process_exception @ Fall into hand on to next handler - appropriate coproc instr diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c index 1106b5f9cf19..04ddab2bd876 100644 --- a/arch/arm/vfp/vfpmodule.c +++ b/arch/arm/vfp/vfpmodule.c @@ -53,7 +53,7 @@ static int vfp_notifier(struct notifier_block *self, unsigned long cmd, void *v) * case the thread migrates to a different CPU. The * restoring is done lazily. */ - if ((fpexc & FPEXC_ENABLE) && last_VFP_context[cpu]) { + if ((fpexc & FPEXC_EN) && last_VFP_context[cpu]) { vfp_save_state(last_VFP_context[cpu], fpexc); last_VFP_context[cpu]->hard.cpu = cpu; } @@ -70,7 +70,7 @@ static int vfp_notifier(struct notifier_block *self, unsigned long cmd, void *v) * Always disable VFP so we can lazily save/restore the * old state. */ - fmxr(FPEXC, fpexc & ~FPEXC_ENABLE); + fmxr(FPEXC, fpexc & ~FPEXC_EN); return NOTIFY_DONE; } @@ -81,13 +81,13 @@ static int vfp_notifier(struct notifier_block *self, unsigned long cmd, void *v) */ memset(vfp, 0, sizeof(union vfp_state)); - vfp->hard.fpexc = FPEXC_ENABLE; + vfp->hard.fpexc = FPEXC_EN; vfp->hard.fpscr = FPSCR_ROUND_NEAREST; /* * Disable VFP to ensure we initialise it first. */ - fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_ENABLE); + fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN); } /* flush and release case: Per-thread VFP cleanup. */ @@ -229,7 +229,7 @@ void VFP9_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs) /* * Enable access to the VFP so we can handle the bounce. */ - fmxr(FPEXC, fpexc & ~(FPEXC_EXCEPTION|FPEXC_INV|FPEXC_UFC|FPEXC_IOC)); + fmxr(FPEXC, fpexc & ~(FPEXC_EX|FPEXC_INV|FPEXC_UFC|FPEXC_IOC)); orig_fpscr = fpscr = fmrx(FPSCR); @@ -248,7 +248,7 @@ void VFP9_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs) /* * Modify fpscr to indicate the number of iterations remaining */ - if (fpexc & FPEXC_EXCEPTION) { + if (fpexc & FPEXC_EX) { u32 len; len = fpexc + (1 << FPEXC_LENGTH_BIT); |